diff --git a/Project/applications/Makefile b/Project/applications/Makefile new file mode 100644 index 0000000..7d58d35 --- /dev/null +++ b/Project/applications/Makefile @@ -0,0 +1,31 @@ +# +# WiSmart Applications Makefile +# +# Copyright 2012 eConais S.A +# + +APPLICATION = 20lines \ + pachube \ + webserver \ + UART_RefDesign \ + UART_Example \ + LCD_Example \ + commander \ + 1wThermo \ + audio + +# +# Build everything (make all) +# +all: + @for dir in $(APPLICATION); do \ + if [ -d $$dir ]; then (cd $$dir; $(MAKE) $@) fi \ + done + +# +# Clean up project (make clean) +# +clean: + @for dir in $(APPLICATION); do \ + if [ -d $$dir ]; then (cd $$dir; $(MAKE) $@) fi \ + done diff --git a/Project/applications/rules.mk b/Project/applications/rules.mk new file mode 100644 index 0000000..752aed9 --- /dev/null +++ b/Project/applications/rules.mk @@ -0,0 +1,374 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# default paramenters +MCU_SIZE ?= MCU_386K_64K +USE_USB_DEVICE ?= no + +# Imported source files and paths +CHIBIOS = $(SDK_ROOT) + +include $(CHIBIOS)/econais/build/configs.inc +CONFIG = $(LIB_CONFIG) +BOOTLOADER = $(LIB_BOOTLOADER) +PLAT = $(LIB_PLAT) +USE_UPNP = $(LIB_USE_UPNP) +USE_DEBUGER = $(LIB_USE_DEBUGER) +USE_WPS = $(LIB_USE_WPS) +USE_8021X = $(LIB_USE_8021X) +RF_TEST = $(LIB_RF_TEST) + +# Select the LWIP version (v140,v141) +LWIP ?= v141 + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -ggdb -fomit-frame-pointer -falign-functions=16 + + ifeq ($(USE_DEBUGER),false) + USE_OPT += -O2 + else + USE_OPT += -O0 + endif +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = yes +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = $(PROJECT_OUT) + + + + + + + + + + +ifeq ($(PLAT),STM32F4) + # Imported source files and paths + include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk + + # Define linker script file here + LDSCRIPT= $(PORTLD)/STM32F407xG.ld + + # platform specific flags + USE_OPT += -mfpu=fpv4-sp-d16 -mhard-float -fsingle-precision-constant +endif + +ifeq ($(PLAT),STM32F1) + # Imported source files and paths + include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk + + # Define linker script file here + ifeq ($(MCU_SIZE),MCU_768K_96K) + ifeq ($(BOOTLOADER),BOOTLOADER_NONE) + # NO bootloader + LDSCRIPT= $(PORTLD)/STM32F103xG_768K_96K.ld + else + # OTA bootloader + LDSCRIPT= $(PORTLD)/STM32F103xG_768K_96K_bootloader_ota.ld + endif + endif + + ifeq ($(MCU_SIZE),MCU_1M_96K) + ifeq ($(BOOTLOADER),BOOTLOADER_NONE) + # NO bootloader + LDSCRIPT= $(PORTLD)/STM32F103xG_1M_96K.ld + else + # OTA bootloader + LDSCRIPT= $(PORTLD)/STM32F103xG_1M_96K_bootloader_ota.ld + endif + endif + + # platform specific flags + USE_OPT += -DUSE_STDPERIPH_DRIVER -DSTM32F10X_XL -DUSE_STM3210E_EVAL -DVECT_TAB_FLASH +endif + +include $(CHIBIOS)/os/kernel/kernel.mk + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(CHIBIOS)/os/various/syscalls.c \ + $(CHIBIOS)/os/various/evtimer.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(CHIBIOS)/os/various + + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +ifeq ($(PLAT),STM32F4) + MCU = cortex-m4 +endif +ifeq ($(PLAT),STM32F1) + MCU = cortex-m3 +endif + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary +SIZE = $(TRGT)size + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wstrict-prototypes -Wunused-variable -Wunused-function + +# Define C++ warning options here +CPPWARN = -Wall -Wunused-variable + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DGCC_ARMCM3 -DCHIBIOS -D$(PLAT) $(USER_DEFS) + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = $(CHIBIOS)/econais/build/libwismart.a + +# +# End of user defines +############################################################################## + +ifeq ($(CONFIG),release) + DDEFS += -DLWIP_NOASSERT + USE_OPT += -DLIBWISMART_RELEASE +endif + +ifeq ($(BOOTLOADER),BOOTLOADER_NONE) + DDEFS += -DLIBWISMART_BOOTLOADER_NONE +endif + +ifeq ($(BOOTLOADER),BOOTLOADER_OTA) + DDEFS += -DLIBWISMART_BOOTLOADER_OTA + DDEFS += -DBOOLOADER_IMAGE_PAGES="(132)" + DDEFS += -DBOOTLOADER_MUTUAL_EEPROM_PAGE_INDEX="(BOOLOADER_IMAGE_PAGES + 0)" + DDEFS += -DBOOTLOADER_APP_PAGE_INDEX="(BOOLOADER_IMAGE_PAGES + 1)" + DDEFS += -DCORTEX_VTOR_INIT="(BOOTLOADER_APP_PAGE_INDEX * 2048)" +endif + +ifeq ($(USE_UPNP),yes) + USE_OPT += -DLWIP_UPNP +endif + +ifeq ($(USE_FWLIB),yes) + USE_OPT += -DUSE_STDPERIPH_DRIVER + +ifeq ($(PLAT),STM32F4) + USE_OPT += -DSTM32F4XX + USE_OPT += -DUSE_STM324xG_EVAL + USE_OPT += -DMEDIA_USB_KEY + USE_OPT += -DUSB_LOCK + USE_OPT += -DMII_MODE +endif + +endif + +ifeq ($(PLAT),STM32F4) + #include USB Host files + include $(CHIBIOS)/stm32f4Driver/usb_key.mk + include $(CHIBIOS)/stm32f4Driver/usb_key_include.mk + CSRC += $(USB_PROJECT_SRC) + INCDIR += $(USB_PROJECT_INC) + + #include stm library + include $(CHIBIOS)/stm32f4Library/stm32f4Library.mk + CSRC += $(STM_LIBRARY_SRC) + INCDIR += $(STM_LIBRARY_INC) + + + #include stm drivers + include $(CHIBIOS)/stm32f4Driver/stm32f4Driver.mk + CSRC += $(STM_DRIVER_ETHERNET_SRC) + INCDIR += $(STM_DRIVER_ETHERNET_INC) + #CSRC += $(STM_DRIVER_EVAL_SRC) + INCDIR += $(STM_DRIVER_EVAL_INC) + + #include fatfs + include $(CHIBIOS)/externalModules/fatfs.mk + CSRC += $(FATFS_SRC) + INCDIR += $(FATFS_INC) + +endif + +ifeq ($(PLAT),STM32F1) + #include stm library + include $(CHIBIOS)/econais/STM32_Libs/F1/stm32f1Library.mk + INCDIR += $(STM_LIBRARY_INC) + + ifeq ($(USE_USB_DEVICE),yes) + #include stm32f1 FS USB Device driver and more stm drivers + include $(CHIBIOS)/stm32f1Driver/stm32f1Driver.mk + + USE_OPT += -DUSE_USB_DEVICE + CSRC += $(STM_DRIVER_FS_USB_DEVICE_SRC) + INCDIR += $(STM_DRIVER_FS_USB_DEVICE_INC) + CSRC += $(STM_DRIVER_EVAL_SRC) + INCDIR += $(STM_DRIVER_EVAL_INC) + INCDIR += $(STM_DRIVER_EVAL_INC) + endif +endif + +############################################################################## +# include files the src code is inside of .a file + +#include lwip +ifeq ($(LWIP),v140) +include $(CHIBIOS)/externalModules/lwip_v14/lwip_include.mk +endif +ifeq ($(LWIP),v141) +include $(CHIBIOS)/externalModules/lwip_v141/lwip_include.mk +endif +INCDIR += $(LWIP_INC) + +#include econais +INCDIR += $(CHIBIOS)/econais/ +INCDIR += $(CHIBIOS)/econais/inc/$(PLAT) + +########## + +#include main +CSRC += $(USER_SRC) +INCDIR += $(USER_INCDIR) + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk + +EXTERNAL: +ifneq ($(PLAT),$(LIB_PLAT)) + $(error The target platform of the libwimart is different from the target platform of application. $(PLAT)-$(LIB_PLAT)) +endif \ No newline at end of file diff --git a/Project/applications/smartcities/.dep/buttonExample.o.d b/Project/applications/smartcities/.dep/buttonExample.o.d new file mode 100644 index 0000000..9878f00 --- /dev/null +++ b/Project/applications/smartcities/.dep/buttonExample.o.d @@ -0,0 +1,218 @@ +build/obj/buttonExample.o: buttonExample.c buttonExample.h \ + ../..//econais/libwismart.h ../..//os/kernel/include/ch.h \ + ../..//econais/inc/STM32F1/chconf.h ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdio.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/_ansi.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/newlib.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/config.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/ieeefp.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/features.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdarg.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/reent.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/_ansi.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/_types.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/_types.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/_default_types.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/lock.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/types.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/types.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/stdio.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/string.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/cdefs.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/string.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdlib.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/stdlib.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/alloca.h \ + ../..//econais/libwismart_mcu.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_gpio.h \ + ../..//econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h \ + ../..//os/ports/common/ARMCMx/CMSIS/include/core_cm3.h \ + ../..//os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h \ + ../..//os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h \ + ../..//econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h \ + ../..//econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x_conf.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_cec.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_dma.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_exti.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_flash.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_fsmc.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_i2c.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_pwr.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_rcc.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_spi.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_tim.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_usart.h \ + ../..//econais/STM32_Libs/F1/inc/misc.h + +buttonExample.h: + +../..//econais/libwismart.h: + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdio.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/_ansi.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/newlib.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/config.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/ieeefp.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/features.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdarg.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/reent.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/_ansi.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/_types.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/_types.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/_default_types.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/lock.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/types.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/types.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/stdio.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/string.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/cdefs.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/string.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdlib.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/stdlib.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/alloca.h: + +../..//econais/libwismart_mcu.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_gpio.h: + +../..//econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h: + +../..//os/ports/common/ARMCMx/CMSIS/include/core_cm3.h: + +../..//os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h: + +../..//os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h: + +../..//econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h: + +../..//econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x_conf.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_cec.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_dma.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_exti.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_flash.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_fsmc.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_i2c.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_pwr.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_rcc.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_spi.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_tim.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_usart.h: + +../..//econais/STM32_Libs/F1/inc/misc.h: diff --git a/Project/applications/smartcities/.dep/chcond.o.d b/Project/applications/smartcities/.dep/chcond.o.d new file mode 100644 index 0000000..0f8b574 --- /dev/null +++ b/Project/applications/smartcities/.dep/chcond.o.d @@ -0,0 +1,88 @@ +build/obj/chcond.o: ../..//os/kernel/src/chcond.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/chcore.o.d b/Project/applications/smartcities/.dep/chcore.o.d new file mode 100644 index 0000000..e8e803b --- /dev/null +++ b/Project/applications/smartcities/.dep/chcore.o.d @@ -0,0 +1,88 @@ +build/obj/chcore.o: ../..//os/ports/GCC/ARMCMx/chcore.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/chcore_v7m.o.d b/Project/applications/smartcities/.dep/chcore_v7m.o.d new file mode 100644 index 0000000..2c82c40 --- /dev/null +++ b/Project/applications/smartcities/.dep/chcore_v7m.o.d @@ -0,0 +1,88 @@ +build/obj/chcore_v7m.o: ../..//os/ports/GCC/ARMCMx/chcore_v7m.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/chdebug.o.d b/Project/applications/smartcities/.dep/chdebug.o.d new file mode 100644 index 0000000..a264531 --- /dev/null +++ b/Project/applications/smartcities/.dep/chdebug.o.d @@ -0,0 +1,159 @@ +build/obj/chdebug.o: ../..//os/kernel/src/chdebug.c \ + ../..//econais/libwismart.h ../..//os/kernel/include/ch.h \ + ../..//econais/inc/STM32F1/chconf.h ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdio.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/_ansi.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/newlib.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/config.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/ieeefp.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/features.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdarg.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/reent.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/_ansi.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/_types.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/_types.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/_default_types.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/lock.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/types.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/types.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/stdio.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/string.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/cdefs.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/string.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdlib.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/stdlib.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/alloca.h \ + ../..//econais/libwismart_mcu.h + +../..//econais/libwismart.h: + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdio.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/_ansi.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/newlib.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/config.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/ieeefp.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/features.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdarg.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/reent.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/_ansi.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/_types.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/_types.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/_default_types.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/lock.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/types.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/types.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/stdio.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/string.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/cdefs.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/string.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdlib.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/stdlib.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/alloca.h: + +../..//econais/libwismart_mcu.h: diff --git a/Project/applications/smartcities/.dep/chdynamic.o.d b/Project/applications/smartcities/.dep/chdynamic.o.d new file mode 100644 index 0000000..3ac5187 --- /dev/null +++ b/Project/applications/smartcities/.dep/chdynamic.o.d @@ -0,0 +1,88 @@ +build/obj/chdynamic.o: ../..//os/kernel/src/chdynamic.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/chevents.o.d b/Project/applications/smartcities/.dep/chevents.o.d new file mode 100644 index 0000000..dfb257a --- /dev/null +++ b/Project/applications/smartcities/.dep/chevents.o.d @@ -0,0 +1,88 @@ +build/obj/chevents.o: ../..//os/kernel/src/chevents.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/chheap.o.d b/Project/applications/smartcities/.dep/chheap.o.d new file mode 100644 index 0000000..b366be2 --- /dev/null +++ b/Project/applications/smartcities/.dep/chheap.o.d @@ -0,0 +1,88 @@ +build/obj/chheap.o: ../..//os/kernel/src/chheap.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/chlists.o.d b/Project/applications/smartcities/.dep/chlists.o.d new file mode 100644 index 0000000..68e58d9 --- /dev/null +++ b/Project/applications/smartcities/.dep/chlists.o.d @@ -0,0 +1,88 @@ +build/obj/chlists.o: ../..//os/kernel/src/chlists.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/chmboxes.o.d b/Project/applications/smartcities/.dep/chmboxes.o.d new file mode 100644 index 0000000..8b224ea --- /dev/null +++ b/Project/applications/smartcities/.dep/chmboxes.o.d @@ -0,0 +1,88 @@ +build/obj/chmboxes.o: ../..//os/kernel/src/chmboxes.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/chmemcore.o.d b/Project/applications/smartcities/.dep/chmemcore.o.d new file mode 100644 index 0000000..3cd621d --- /dev/null +++ b/Project/applications/smartcities/.dep/chmemcore.o.d @@ -0,0 +1,88 @@ +build/obj/chmemcore.o: ../..//os/kernel/src/chmemcore.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/chmempools.o.d b/Project/applications/smartcities/.dep/chmempools.o.d new file mode 100644 index 0000000..505baf5 --- /dev/null +++ b/Project/applications/smartcities/.dep/chmempools.o.d @@ -0,0 +1,88 @@ +build/obj/chmempools.o: ../..//os/kernel/src/chmempools.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/chmsg.o.d b/Project/applications/smartcities/.dep/chmsg.o.d new file mode 100644 index 0000000..69deb75 --- /dev/null +++ b/Project/applications/smartcities/.dep/chmsg.o.d @@ -0,0 +1,88 @@ +build/obj/chmsg.o: ../..//os/kernel/src/chmsg.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/chmtx.o.d b/Project/applications/smartcities/.dep/chmtx.o.d new file mode 100644 index 0000000..3407533 --- /dev/null +++ b/Project/applications/smartcities/.dep/chmtx.o.d @@ -0,0 +1,88 @@ +build/obj/chmtx.o: ../..//os/kernel/src/chmtx.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/chqueues.o.d b/Project/applications/smartcities/.dep/chqueues.o.d new file mode 100644 index 0000000..58b3fa8 --- /dev/null +++ b/Project/applications/smartcities/.dep/chqueues.o.d @@ -0,0 +1,88 @@ +build/obj/chqueues.o: ../..//os/kernel/src/chqueues.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/chregistry.o.d b/Project/applications/smartcities/.dep/chregistry.o.d new file mode 100644 index 0000000..81c342e --- /dev/null +++ b/Project/applications/smartcities/.dep/chregistry.o.d @@ -0,0 +1,88 @@ +build/obj/chregistry.o: ../..//os/kernel/src/chregistry.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/chschd.o.d b/Project/applications/smartcities/.dep/chschd.o.d new file mode 100644 index 0000000..39aa786 --- /dev/null +++ b/Project/applications/smartcities/.dep/chschd.o.d @@ -0,0 +1,88 @@ +build/obj/chschd.o: ../..//os/kernel/src/chschd.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/chsem.o.d b/Project/applications/smartcities/.dep/chsem.o.d new file mode 100644 index 0000000..c7cfb14 --- /dev/null +++ b/Project/applications/smartcities/.dep/chsem.o.d @@ -0,0 +1,88 @@ +build/obj/chsem.o: ../..//os/kernel/src/chsem.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/chsys.o.d b/Project/applications/smartcities/.dep/chsys.o.d new file mode 100644 index 0000000..8201fba --- /dev/null +++ b/Project/applications/smartcities/.dep/chsys.o.d @@ -0,0 +1,88 @@ +build/obj/chsys.o: ../..//os/kernel/src/chsys.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/chthreads.o.d b/Project/applications/smartcities/.dep/chthreads.o.d new file mode 100644 index 0000000..926974e --- /dev/null +++ b/Project/applications/smartcities/.dep/chthreads.o.d @@ -0,0 +1,88 @@ +build/obj/chthreads.o: ../..//os/kernel/src/chthreads.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/chvt.o.d b/Project/applications/smartcities/.dep/chvt.o.d new file mode 100644 index 0000000..652f904 --- /dev/null +++ b/Project/applications/smartcities/.dep/chvt.o.d @@ -0,0 +1,88 @@ +build/obj/chvt.o: ../..//os/kernel/src/chvt.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/crt0.o.d b/Project/applications/smartcities/.dep/crt0.o.d new file mode 100644 index 0000000..00d5e28 --- /dev/null +++ b/Project/applications/smartcities/.dep/crt0.o.d @@ -0,0 +1,88 @@ +build/obj/crt0.o: ../..//os/ports/GCC/ARMCMx/crt0.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/evtimer.o.d b/Project/applications/smartcities/.dep/evtimer.o.d new file mode 100644 index 0000000..cdd30a4 --- /dev/null +++ b/Project/applications/smartcities/.dep/evtimer.o.d @@ -0,0 +1,91 @@ +build/obj/evtimer.o: ../..//os/various/evtimer.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h \ + ../..//os/various/evtimer.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: + +../..//os/various/evtimer.h: diff --git a/Project/applications/smartcities/.dep/main.o.d b/Project/applications/smartcities/.dep/main.o.d new file mode 100644 index 0000000..889162b --- /dev/null +++ b/Project/applications/smartcities/.dep/main.o.d @@ -0,0 +1,246 @@ +build/obj/main.o: main.c ../..//econais/libwismart.h \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdio.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/_ansi.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/newlib.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/config.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/ieeefp.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/features.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdarg.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/reent.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/_ansi.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/_types.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/_types.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/_default_types.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/lock.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/types.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/types.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/stdio.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/string.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/cdefs.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/string.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdlib.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/stdlib.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/alloca.h \ + ../..//econais/libwismart_mcu.h \ + ../..//econais/inc/STM32F1/libwismart_irqs.h \ + ../..//econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h \ + ../..//os/ports/common/ARMCMx/CMSIS/include/core_cm3.h \ + ../..//os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h \ + ../..//os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h \ + ../..//econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h \ + ../..//econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x_conf.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_cec.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_dma.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_exti.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_flash.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_fsmc.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_gpio.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_i2c.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_pwr.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_rcc.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_spi.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_tim.h \ + ../..//econais/STM32_Libs/F1/inc/stm32f10x_usart.h \ + ../..//econais/STM32_Libs/F1/inc/misc.h \ + ../..//externalModules/lwip_v141/src/include/ipv4/lwip/inet.h \ + ../..//externalModules/lwip_v141/src/include/lwip/opt.h \ + ../..//externalModules/lwip_v141/port/lwipopts.h \ + ../..//externalModules/lwip_v141/src/include/lwip/debug.h \ + ../..//externalModules/lwip_v141/src/include/lwip/arch.h \ + ../..//externalModules/lwip_v141/port/arch/cc.h \ + ../..//externalModules/lwip_v141/src/include/lwip/def.h \ + ../..//externalModules/lwip_v141/src/include/ipv4/lwip/ip_addr.h \ + buttonExample.h + +../..//econais/libwismart.h: + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdio.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/_ansi.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/newlib.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/config.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/ieeefp.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/features.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdarg.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/reent.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/_ansi.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/_types.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/_types.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/_default_types.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/lock.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/types.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/types.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/stdio.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/string.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/cdefs.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/string.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdlib.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/stdlib.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/alloca.h: + +../..//econais/libwismart_mcu.h: + +../..//econais/inc/STM32F1/libwismart_irqs.h: + +../..//econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h: + +../..//os/ports/common/ARMCMx/CMSIS/include/core_cm3.h: + +../..//os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h: + +../..//os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h: + +../..//econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h: + +../..//econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x_conf.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_cec.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_dma.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_exti.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_flash.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_fsmc.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_gpio.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_i2c.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_pwr.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_rcc.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_spi.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_tim.h: + +../..//econais/STM32_Libs/F1/inc/stm32f10x_usart.h: + +../..//econais/STM32_Libs/F1/inc/misc.h: + +../..//externalModules/lwip_v141/src/include/ipv4/lwip/inet.h: + +../..//externalModules/lwip_v141/src/include/lwip/opt.h: + +../..//externalModules/lwip_v141/port/lwipopts.h: + +../..//externalModules/lwip_v141/src/include/lwip/debug.h: + +../..//externalModules/lwip_v141/src/include/lwip/arch.h: + +../..//externalModules/lwip_v141/port/arch/cc.h: + +../..//externalModules/lwip_v141/src/include/lwip/def.h: + +../..//externalModules/lwip_v141/src/include/ipv4/lwip/ip_addr.h: + +buttonExample.h: diff --git a/Project/applications/smartcities/.dep/nvic.o.d b/Project/applications/smartcities/.dep/nvic.o.d new file mode 100644 index 0000000..f93c094 --- /dev/null +++ b/Project/applications/smartcities/.dep/nvic.o.d @@ -0,0 +1,91 @@ +build/obj/nvic.o: ../..//os/ports/common/ARMCMx/nvic.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h \ + ../..//os/ports/common/ARMCMx/nvic.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: + +../..//os/ports/common/ARMCMx/nvic.h: diff --git a/Project/applications/smartcities/.dep/syscalls.o.d b/Project/applications/smartcities/.dep/syscalls.o.d new file mode 100644 index 0000000..cae45ca --- /dev/null +++ b/Project/applications/smartcities/.dep/syscalls.o.d @@ -0,0 +1,160 @@ +build/obj/syscalls.o: ../..//os/various/syscalls.c \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdlib.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/ieeefp.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/_ansi.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/newlib.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/config.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/features.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/reent.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/_ansi.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/_types.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/_types.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/_default_types.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/lock.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/stdlib.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/alloca.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/errno.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/errno.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/string.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/cdefs.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/string.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/stat.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/time.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/time.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/types.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/types.h \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdlib.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/ieeefp.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/_ansi.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/newlib.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/config.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/features.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/reent.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/_ansi.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/_types.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/_types.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/_default_types.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/lock.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/stdlib.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/alloca.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/errno.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/errno.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/string.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/cdefs.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/string.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/stat.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/time.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/time.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/types.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/machine/types.h: + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/.dep/vectors.o.d b/Project/applications/smartcities/.dep/vectors.o.d new file mode 100644 index 0000000..6b5d117 --- /dev/null +++ b/Project/applications/smartcities/.dep/vectors.o.d @@ -0,0 +1,88 @@ +build/obj/vectors.o: ../..//os/ports/GCC/ARMCMx/STM32F1xx/vectors.c \ + ../..//os/kernel/include/ch.h ../..//econais/inc/STM32F1/chconf.h \ + ../..//os/ports/GCC/ARMCMx/chtypes.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h \ + c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h \ + c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h \ + ../..//os/kernel/include/chlists.h ../..//os/ports/GCC/ARMCMx/chcore.h \ + ../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h \ + ../..//os/ports/GCC/ARMCMx/chcore_v7m.h \ + ../..//os/ports/common/ARMCMx/nvic.h ../..//os/kernel/include/chsys.h \ + ../..//os/kernel/include/chvt.h ../..//os/kernel/include/chschd.h \ + ../..//os/kernel/include/chsem.h ../..//os/kernel/include/chbsem.h \ + ../..//os/kernel/include/chmtx.h ../..//os/kernel/include/chcond.h \ + ../..//os/kernel/include/chevents.h ../..//os/kernel/include/chmsg.h \ + ../..//os/kernel/include/chmboxes.h ../..//os/kernel/include/chmemcore.h \ + ../..//os/kernel/include/chheap.h ../..//os/kernel/include/chmempools.h \ + ../..//os/kernel/include/chthreads.h \ + ../..//os/kernel/include/chdynamic.h \ + ../..//os/kernel/include/chregistry.h \ + ../..//os/kernel/include/chinline.h ../..//os/kernel/include/chqueues.h \ + ../..//os/kernel/include/chstreams.h ../..//os/kernel/include/chioch.h \ + ../..//os/kernel/include/chfiles.h ../..//os/kernel/include/chdebug.h + +../..//os/kernel/include/ch.h: + +../..//econais/inc/STM32F1/chconf.h: + +../..//os/ports/GCC/ARMCMx/chtypes.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h: + +c:\yagarto\bin\../lib/gcc/arm-none-eabi/4.7.2/include/stdint.h: + +c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h: + +../..//os/kernel/include/chlists.h: + +../..//os/ports/GCC/ARMCMx/chcore.h: + +../..//os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h: + +../..//os/ports/GCC/ARMCMx/chcore_v7m.h: + +../..//os/ports/common/ARMCMx/nvic.h: + +../..//os/kernel/include/chsys.h: + +../..//os/kernel/include/chvt.h: + +../..//os/kernel/include/chschd.h: + +../..//os/kernel/include/chsem.h: + +../..//os/kernel/include/chbsem.h: + +../..//os/kernel/include/chmtx.h: + +../..//os/kernel/include/chcond.h: + +../..//os/kernel/include/chevents.h: + +../..//os/kernel/include/chmsg.h: + +../..//os/kernel/include/chmboxes.h: + +../..//os/kernel/include/chmemcore.h: + +../..//os/kernel/include/chheap.h: + +../..//os/kernel/include/chmempools.h: + +../..//os/kernel/include/chthreads.h: + +../..//os/kernel/include/chdynamic.h: + +../..//os/kernel/include/chregistry.h: + +../..//os/kernel/include/chinline.h: + +../..//os/kernel/include/chqueues.h: + +../..//os/kernel/include/chstreams.h: + +../..//os/kernel/include/chioch.h: + +../..//os/kernel/include/chfiles.h: + +../..//os/kernel/include/chdebug.h: diff --git a/Project/applications/smartcities/Makefile b/Project/applications/smartcities/Makefile new file mode 100644 index 0000000..829f4fa --- /dev/null +++ b/Project/applications/smartcities/Makefile @@ -0,0 +1,34 @@ + +# +# WiSmart Applications Makefile +# +# Copyright 2012 eConais S.A +# + + +# Set the sdk root folder +SDK_ROOT = ../../ +PROJECT_OUT = buttonExample + +USER_SRC = main.c buttonExample.c + + +USER_INCDIR = + +# if you need to add build Defines options add to USER_DEFS define +#USER_DEFS += -D + +# select SDK's version: +SDK_VERSION = SDK_REV_9_2 + +# select the MCU type e.g. STM32F1, STM32F4 +PLAT = STM32F1 + +# select the MCU flash/ram size e.g. MCU_386K_64K, MCU_768K_96K, MCU_1M_96K +MCU_SIZE = MCU_768K_96K + +USER_DEFS += -D$(SDK_VERSION) + +# this must be the last include +include $(SDK_ROOT)/applications/rules.mk + diff --git a/Project/applications/smartcities/build/buttonExample.bin b/Project/applications/smartcities/build/buttonExample.bin new file mode 100644 index 0000000..984f62b --- /dev/null +++ b/Project/applications/smartcities/build/buttonExample.bin diff --git a/Project/applications/smartcities/build/buttonExample.dmp b/Project/applications/smartcities/build/buttonExample.dmp new file mode 100644 index 0000000..8a8b2d9 --- /dev/null +++ b/Project/applications/smartcities/build/buttonExample.dmp @@ -0,0 +1,2025 @@ + +build/buttonExample.elf: file format elf32-littlearm +build/buttonExample.elf +architecture: arm, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x08000130 + +Program Header: + LOAD off 0x00008000 vaddr 0x08000000 paddr 0x08000000 align 2**15 + filesz 0x00035f88 memsz 0x00035f88 flags rwx + LOAD off 0x00040c00 vaddr 0x20000c00 paddr 0x08035f88 align 2**15 + filesz 0x0000066c memsz 0x0000c334 flags rw- + LOAD off 0x00048000 vaddr 0x20000000 paddr 0x20000000 align 2**15 + filesz 0x00000000 memsz 0x00000c00 flags rw- +private flags = 5000002: [Version5 EABI] [has entry point] + +Sections: +Idx Name Size VMA LMA File off Algn + 0 startup 00000130 08000000 08000000 00008000 2**4 + CONTENTS, ALLOC, LOAD, DATA + 1 .text 00035e58 08000130 08000130 00008130 2**4 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .stacks 00000c00 20000000 20000000 00048000 2**0 + ALLOC + 3 .data 0000066c 20000c00 08035f88 00040c00 2**3 + CONTENTS, ALLOC, LOAD, DATA + 4 .bss 0000bcc4 20001270 080365f8 0004126c 2**3 + ALLOC + 5 .debug_info 001316d7 00000000 00000000 0004126c 2**0 + CONTENTS, READONLY, DEBUGGING + 6 .debug_abbrev 00023da0 00000000 00000000 00172943 2**0 + CONTENTS, READONLY, DEBUGGING + 7 .debug_aranges 00005a40 00000000 00000000 001966e8 2**3 + CONTENTS, READONLY, DEBUGGING + 8 .debug_ranges 0000e7d0 00000000 00000000 0019c128 2**0 + CONTENTS, READONLY, DEBUGGING + 9 .debug_line 000342e8 00000000 00000000 001aa8f8 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_str 00022659 00000000 00000000 001debe0 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .comment 00000011 00000000 00000000 00201239 2**0 + CONTENTS, READONLY + 12 .ARM.attributes 00000033 00000000 00000000 0020124a 2**0 + CONTENTS, READONLY + 13 .debug_frame 00010930 00000000 00000000 00201280 2**2 + CONTENTS, READONLY, DEBUGGING + 14 .debug_loc 0006e8a3 00000000 00000000 00211bb0 2**0 + CONTENTS, READONLY, DEBUGGING +SYMBOL TABLE: +08000000 l d startup 00000000 startup +08000130 l d .text 00000000 .text +20000000 l d .stacks 00000000 .stacks +20000c00 l d .data 00000000 .data +20001270 l d .bss 00000000 .bss +00000000 l d .debug_info 00000000 .debug_info +00000000 l d .debug_abbrev 00000000 .debug_abbrev +00000000 l d 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00000000 chcore_v7m.c +08006964 l .text 00000000 _port_exit_from_isr +00000000 l df *ABS* 00000000 nvic.c +00000000 l df *ABS* 00000000 chsys.c +20001270 l O .bss 00000048 mainthread.4814 +00000000 l df *ABS* 00000000 chvt.c +00000000 l df *ABS* 00000000 chschd.c +08006be0 l F .text 00000050 wakeup +00000000 l df *ABS* 00000000 chthreads.c +00000000 l df *ABS* 00000000 chdynamic.c +00000000 l df *ABS* 00000000 chsem.c +00000000 l df *ABS* 00000000 chmtx.c +00000000 l df *ABS* 00000000 chevents.c +00000000 l df *ABS* 00000000 chmboxes.c +00000000 l df *ABS* 00000000 chmemcore.c +200012e8 l O .bss 00000004 endmem +200012ec l O .bss 00000004 nextmem +00000000 l df *ABS* 00000000 chheap.c +200012f0 l O .bss 00000020 default_heap +00000000 l df *ABS* 00000000 chmempools.c +00000000 l df *ABS* 00000000 syscalls.c +00000000 l df *ABS* 00000000 evtimer.c +08007730 l F .text 00000024 tmrcb +00000000 l df *ABS* 00000000 buttonExample.c +00000000 l df *ABS* 00000000 libwismart.c +20001530 l O .bss 0000000c dma2PeripheralSem +2000154d l O .bss 00000001 peripheralLocksInited.11910 +00000000 l df *ABS* 00000000 libwismart_cm.c +20001554 l O .bss 00000001 wps_ongoing +00000000 l df *ABS* 00000000 libwismart_scan.c +08007ea0 l F .text 00000054 handle_bg_scan_timer +08007f00 l F .text 000000d0 handle_scan_timer +20001560 l O .bss 00000001 enable_bg_scan +200010b4 l O .data 00000001 bg_scan_period +20001561 l O .bss 00000001 max_scan_runs +20001584 l O .bss 00000001 num_of_scan_runs +2000158c l O .bss 00000001 scan_state +00000000 l df *ABS* 00000000 libwismart_power.c +08008090 l F .text 000001c8 _wismart_idle_thread +08008260 l F .text 00000056 update_allow_stop_mode +00000000 l df *ABS* 00000000 libwismart_uart.c +080084a0 l F .text 00000002 usart_rx_null_cb +200016dc l O .bss 0000000c uart_tx_sema +200016e8 l O .bss 0000000c tx_dma_bsema +200016f4 l O .bss 0000000c uart_rx_sema +200010b8 l O .data 00000004 usart_rx_complete_func +20001700 l O .bss 0000000c uart_access_sema +2000170c l O .bss 0000000c rx_dma_bsema +00000000 l df *ABS* 00000000 transport.c +080086e0 l F .text 00000550 WifiRX_Thread +20001718 l O .bss 0000000c sdio_bus_sem +20001724 l O .bss 00000040 hic_recv_header +0802ec80 l O .text 00000029 __FUNCTION__.11607 +0802ee60 l O .text 0000002b __FUNCTION__.11630 +20001764 l O .bss 00000004 wifi_irq_event +0802ee90 l O .text 00000013 __FUNCTION__.11583 +20001768 l O .bss 00000002 sdio_irq_count +20001770 l O .bss 000004b0 waWifiRX +00000000 l df *ABS* 00000000 libwismart_lwip.c +08008c70 l F .text 00000058 _handle_packet +08008d70 l F .text 00000150 lwip_thread +20001c20 l O .bss 00000004 lwip_frame_received_event +200022d8 l O .bss 00000028 timer_event_mb +20002300 l O .bss 00000004 lwip_tp +20002304 l O .bss 00000002 timer_event_count +20002308 l O .bss 00000028 timer_event_mb_msgs +20002334 l O .bss 0000001c periodic_evt +20002350 l O .bss 00000004 timer_event_received_event +20002354 l O .bss 0000000c lwip_lock +00000000 l df *ABS* 00000000 netconf.c +00000000 l df *ABS* 00000000 dhcpserver.c +08009190 l F .text 00000134 DHCPOptionsReply +080092d0 l F .text 00000040 haddrtoa +08009310 l F .text 00000090 DHCPScan +080093a0 l F .text 0000002c hex2num +080093d0 l F .text 00000050 DHCPSearchOptionsField.constprop.2 +08009470 l F .text 00000918 dhcp_recv +200023c4 l O .bss 00000118 theAllocatedIP +0802eee0 l O .text 00000046 sDhcpOpt.10790 +200024f4 l O .bss 00000004 stNearest.10816 +0802ef30 l O .text 00000050 tDHCPType +200024f8 l O .bss 00000004 nAllocatedIP +200024fc l O .bss 00000004 stNearest.10785 +20002500 l O .bss 00000031 haddrbuf.10754 +20002534 l O .bss 00000120 sParamDHCP +0802f420 l O .text 00000046 sDhcpOpt.10821 +00000000 l df *ABS* 00000000 wifi_softap.c +20002658 l O .bss 00000120 clients +0802f470 l O .text 00000038 CSWTCH.59 +00000000 l df *ABS* 00000000 wifi_engine.c +0800a4e0 l F .text 00000090 wei_ratelist2mask +0800a570 l F .text 00000068 wei_prune_nonbasic_ratelist +0800a5e0 l F .text 00000160 fix_assoc_ie.constprop.0 +200010bc l O .data 00000001 internal_mode +200027c8 l O .bss 00000004 wpa_ie_len +2000284c l O .bss 00000100 wpa_ie +2000294c l O .bss 0000000c cmdcnt_lock +00000000 l df *ABS* 00000000 wifi_mlme_handler.c +0800b380 l F .text 00001188 RxCmdQueue_Thread +2000297c l O .bss 0000000c rxcmd_count_sem +20002994 l O .bss 00000001 sub_states_counter +0802fd10 l O .text 00000013 __FUNCTION__.11741 +0802fd30 l O .text 0000001c StatusDebugMsg +20002998 l O .bss 00000004 rxcmd_queue_event +0802fd50 l O .text 00000002 CSWTCH.67 +08030650 l O .text 00000014 __FUNCTION__.11733 +200029a0 l O .bss 00000002 rxcmd_count +200029a8 l O .bss 000018b0 waRxCmdQueue +00000000 l df *ABS* 00000000 wifi_ps.c +0800c6c0 l F .text 0000001e wifi_PsSendInterface_Down +0800c6e0 l F .text 0000000c wifi_ps_lock +0800cb80 l F .text 0000008c ps_traffic_timeout_cb +08030670 l O .text 0000000e __FUNCTION__.11475 +20004259 l O .bss 00000001 state +2000425c l O .bss 00000004 ok_to_send +08030680 l O .text 00000011 __FUNCTION__.11522 +08030a10 l O .text 0000000f __FUNCTION__.11478 +200010e4 l O .data 00000001 ps_main_state +08030a20 l O .text 00000010 __FUNCTION__.11514 +20004260 l O .bss 00000001 ps_traffic_timeout_running +200010e8 l O .data 00000004 hic_if_users +20004264 l O .bss 00000020 ps_traffic_te +20004284 l O .bss 0000000c ps_lock +00000000 l df *ABS* 00000000 wifi_cmds_flow.c +0800cd90 l F .text 0000000c cmd_list_find_based_on_trans_id +20004290 l O .bss 00000004 wifi_sem_data_path_limit +20004294 l O .bss 00000004 fw_reset_event +20004298 l O .bss 00000004 list_sended_data_packets +08030a30 l O .text 0000001c __FUNCTION__.11394 +2000429c l O .bss 00000004 wifi_sem_cmd_path_limit +200042a0 l O .bss 0000001c periodic_evt +200042bc l O .bss 0000000e sended_cmd_packet +00000000 l df *ABS* 00000000 wifi_filter.c +20001100 l O .data 00000002 filter_exclude +00000000 l df *ABS* 00000000 wifi_scan.c +0800cfc0 l F .text 0000000e scan_list_find_based_on_counter +0800cfd0 l F .text 00000008 scan_list_exec_dec_count +0800cfe0 l F .text 00000004 scan_list_find_based_on_desire +0800cff0 l F .text 00000010 scan_list_exec_best_rssi +0800d000 l F .text 00000014 scan_list_find_based_on_bssId +0800d020 l F .text 0000007c scan_list_find_based_on_rssi +200042cc l O .bss 00000026 scan_params +200042f4 l O .bss 00000004 scan_list +200042f8 l O .bss 00000001 running_scan +00000000 l df *ABS* 00000000 mibs.c +08030c20 l O .text 000009dc dlm_mib_table_client +08031600 l O .text 000009dc dlm_mib_table_softap +08032330 l O .text 000003e0 g_mib_table +00000000 l df *ABS* 00000000 roam.c +0800dc00 l F .text 00000008 event_list_exec_roam +0800dc10 l F .text 00000004 event_list_find_notvalid +20004304 l O .bss 00000003 bg_scan_times +20004308 l O .bss 00000001 roam_state +2000430c l O .bss 00000004 roam_events_list +00000000 l df *ABS* 00000000 debug.c +00000000 l df *ABS* 00000000 print.c +0800dcf0 l F .text 000000b0 long_itoa +0800dda0 l F .text 00000128 vfprintf_ +0800ded0 l F .text 0000002c putc_strg +20004310 l O .bss 00000002 string_index +20004314 l O .bss 00000100 string_buffer +20004414 l O .bss 0000000c print_lock +00000000 l df *ABS* 00000000 link_list.c +00000000 l df *ABS* 00000000 timer_events.c +0800e0e0 l F .text 00000004 timer_event_forward +00000000 l df *ABS* 00000000 rtc.c +20004420 l O .bss 00000004 PeriodValue +20004428 l O .bss 00000004 OperationComplete +2000442c l O .bss 00000004 LsiFreq +00000000 l df *ABS* 00000000 gpio.c +00000000 l df *ABS* 00000000 wifi_transport.c +0800e620 l F .text 00000150 CmdResp5Error +08032730 l O .text 0000000e __FUNCTION__.11615 +20004438 l O .bss 00000014 SDIO_CmdInitStructure +08032740 l O .text 00000015 __FUNCTION__.11621 +2000444c l O .bss 00000004 GPIO_InitStructure +20004434 l O .bss 00000001 TransferError +20004430 l O .bss 00000004 TransferEnd +0800ec80 l F .text 0000011a HW_WiFiTransport_WaitWriteOperation +08032760 l O .text 00000024 __FUNCTION__.11673 +0800eda0 l F .text 000001fc _HW_WiFiTransport_SendCMD53 +20004450 l O .bss 00000018 SDIO_DataInitStructure +00000000 l df *ABS* 00000000 rcc.c +00000000 l df *ABS* 00000000 registry_driver.c +00000000 l df *ABS* 00000000 stm32_eeprom.c +2000110c l O .data 00000114 profile +00000000 l df *ABS* 00000000 uart.c +20004504 l O .bss 00000004 usart_ptr +2000450c l O .bss 0000002c TX_DMA_InitStructure +20004538 l O .bss 0000002c RX_DMA_InitStructure +00000000 l df *ABS* 00000000 power.c +00000000 l df *ABS* 00000000 common.c +0800fba0 l F .text 0000002c hex2num +00000000 l df *ABS* 00000000 main_wifiengine.c +0800fd60 l F .text 0000000c ec_wpa_supplicant_event_thread +20004564 l O .bss 00000004 global +00000000 l df *ABS* 00000000 os_wifiengine.c +00000000 l df *ABS* 00000000 wpa_supplicant.c +0800ffc0 l F .text 0000009a wpa_supplicant_set_wpa_none_key +080109a0 l F .text 000000a4 wpa_supplicant_timeout +08010520 l F .text 0000004c wpa_supplicant_clear_connection +08032bf0 l O .text 00000022 __FUNCTION__.15210 +08032ec0 l O .text 0000000c CSWTCH.135 +08032ed0 l O .text 00000010 CSWTCH.105 +20004568 l O .bss 00000004 interface_count.15458 +00000000 l df *ABS* 00000000 wps.c +00000000 l df *ABS* 00000000 wps_registrar.c +08011650 l F .text 0000002c wps_set_pushbutton +08011680 l F .text 000000d8 wps_registrar_add_pbc_session +08011760 l F .text 00000086 wps_registrar_remove_pbc_session +080117f0 l F .text 00000056 wps_registrar_remove_authorized_mac +08011850 l F .text 00000034 wps_build_wps_state.isra.17 +08011890 l F .text 00000030 wps_build_ap_setup_locked.part.18 +080118c0 l F .text 00000030 wps_build_selected_registrar.part.19 +080118f0 l F .text 00000066 wps_build_sel_reg_config_methods.part.16 +08011960 l F .text 0000004a wps_build_sel_reg_dev_password_id +080119b0 l F .text 0000013c wps_build_credential +08011be0 l F .text 000002b0 wps_set_ie +08012290 l F .text 00000014 wps_registrar_pbc_timeout +08012240 l F .text 0000000a wps_registrar_set_selected_timeout +08012210 l F .text 00000022 wps_registrar_pin_completed +08012250 l F .text 00000038 wps_registrar_stop_pbc +080122e0 l F .text 00000070 wps_registrar_remove_pin +00000000 l df *ABS* 00000000 wps_supplicant.c +080123a0 l F .text 00000088 wpas_clear_wps +08012430 l F .text 00000004 wpas_wps_timeout +08012440 l F .text 00000128 wpas_wps_add_network +08012570 l F .text 0000005c wpas_wps_reassoc +00000000 l df *ABS* 00000000 ap.c +08012900 l F .text 00000002 ap_public_action_rx +08012910 l F .text 00000002 ap_wps_event_cb +08012920 l F .text 00000004 ap_vendor_action_rx +08012930 l F .text 00000004 ap_probe_req_rx +08012940 l F .text 00000002 ap_wps_reg_success_cb +08012950 l F .text 0000001c wpa_supplicant_ap_wps_sta_cancel +08012970 l F .text 00000004 ap_sta_authorized_cb +080130d0 l F .text 00000004 wpas_wps_ap_pin_timeout +00000000 l df *ABS* 00000000 hostapd.c +080130e0 l F .text 0000002e hostapd_broadcast_key_clear_iface +08013110 l F .text 00000158 hostapd_setup_encryption +080132d0 l F .text 00000044 hostapd_flush_old_stations +00000000 l df *ABS* 00000000 wpa_auth_glue.c +08013930 l F .text 00000002 hostapd_wpa_auth_logger +08013940 l F .text 00000026 hostapd_wpa_auth_for_each_sta +08013970 l F .text 00000032 wpa_auth_iface_iter +080139b0 l F .text 00000028 hostapd_wpa_auth_for_each_auth +080139e0 l F .text 0000002a hostapd_wpa_auth_get_eapol +08013a10 l F .text 00000048 hostapd_wpa_auth_send_eapol +08013a60 l F .text 0000001c hostapd_wpa_auth_get_seqnum +08013a80 l F .text 00000044 hostapd_wpa_auth_set_key +08013ad0 l F .text 0000003e hostapd_wpa_auth_get_msk +08013b10 l F .text 00000006 hostapd_wpa_auth_get_psk +08013b20 l F .text 00000096 hostapd_wpa_auth_set_eapol +08013bc0 l F .text 00000006 hostapd_wpa_auth_mic_failure_report +08013bd0 l F .text 00000010 hostapd_wpa_auth_disconnect +08013be0 l F .text 0000009a hostapd_wpa_auth_send_ether +00000000 l df *ABS* 00000000 utils.c +08013de0 l F .text 0000003a prune_associations +00000000 l df *ABS* 00000000 authsrv.c +00000000 l df *ABS* 00000000 ap_config.c +08013ea0 l F .text 00000024 hostapd_config_free_radius +2000456c l O .bss 00000064 wsc_enrollee.12020 +08033350 l O .text 00000010 txq_be.11900 +08033360 l O .text 00000014 ac_vo.11898 +08033380 l O .text 00000014 ac_vi.11897 +080333a0 l O .text 00000014 ac_bk.11895 +080333c0 l O .text 00000014 ac_be.11896 +080333e0 l O .text 00000010 txq_vo.11902 +080333f0 l O .text 00000010 txq_bk.11899 +08033400 l O .text 00000010 txq_vi.11901 +200045d0 l O .bss 00000064 wsc_registrar.12021 +00000000 l df *ABS* 00000000 sta_info.c +080144c0 l F .text 00000036 ap_sta_remove +08014500 l F .text 0000001a ap_sta_disassoc_cb_timeout +08014520 l F .text 0000001a ap_sta_deauth_cb_timeout +08014950 l F .text 0000003e ap_handle_session_timer +00000000 l df *ABS* 00000000 tkip_countermeasures.c +08014ce0 l F .text 0000001c ieee80211_tkip_countermeasures_stop +00000000 l df *ABS* 00000000 ap_mlme.c +00000000 l df *ABS* 00000000 ieee802_1x.c +08014e30 l F .text 00000002 ieee802_1x_aaa_send +08014e40 l F .text 00000002 ieee802_1x_logger +08014e50 l F .text 00000018 ieee802_1x_sta_key_available +08014e70 l F .text 000000fc ieee802_1x_rekey +08014f70 l F .text 00000012 ieee802_1x_sta_entry_alive +08014f90 l F .text 0000006a ieee802_1x_get_eap_user +08015000 l F .text 00000052 _ieee802_1x_finished +08015060 l F .text 00000096 ieee802_1x_send +08015100 l F .text 00000074 ieee802_1x_eapol_send +08015180 l F .text 00000044 ieee802_1x_alloc_eapol_sm +080151d0 l F .text 0000019a ieee802_1x_tx_key_one +08015370 l F .text 0000001a ieee802_1x_eapol_event +080153d0 l F .text 00000004 ieee802_1x_set_port_authorized +08015490 l F .text 00000004 _ieee802_1x_tx_key +08015810 l F .text 00000004 _ieee802_1x_abort_auth +00000000 l df *ABS* 00000000 eapol_auth_sm.c +08015a20 l F .text 00000016 eapol_sm_get_eap_user +08015a40 l F .text 0000000c eapol_sm_get_eap_req_id_text +08015a50 l F .text 00000058 eapol_auth_vlogger +08015ab0 l F .text 00000098 eapol_auth_tx_canned_eap +08015b50 l F .text 000000b0 eapol_auth_tx_req +08015c00 l F .text 00000090 sm_AUTH_PAE_DISCONNECTED_Enter.constprop.6 +08015c90 l F .text 0000003a sm_AUTH_PAE_RESTART_Enter.constprop.7 +08015cd0 l F .text 00000024 sm_BE_AUTH_REQUEST_Enter.constprop.11 +08016660 l F .text 00000050 eapol_port_timers_tick +08016650 l F .text 00000004 eapol_sm_step_cb +08015d60 l F .text 000008f0 eapol_sm_step_run +20001220 l O .data 00000008 eapol_cb +00000000 l df *ABS* 00000000 ieee802_11_auth.c +00000000 l df *ABS* 00000000 ap_drv_ops.c +00000000 l df *ABS* 00000000 beacon.c +00000000 l df *ABS* 00000000 eap_server.c +080171d0 l F .text 0000008e eap_sm_parseEapResp +08017260 l F .text 0000001c eap_user_free +08017280 l F .text 00000028 eap_copy_buf +080172b0 l F .text 00000050 sm_EAP_FAILURE_Enter +08017300 l F .text 000000b8 sm_EAP_PROPOSE_METHOD_Enter.constprop.19 +080173c0 l F .text 00000066 sm_EAP_METHOD_REQUEST_Enter.constprop.21 +08017430 l F .text 0000002c sm_EAP_IDLE_Enter.constprop.26 +08017460 l F .text 0000002c sm_EAP_IDLE2_Enter.constprop.14 +08017500 l F .text 00000134 sm_EAP_SELECT_ACTION_Enter.constprop.17 +080176d0 l F .text 0000005c sm_EAP_METHOD_RESPONSE_Enter.constprop.20 +08017730 l F .text 00000072 sm_EAP_NAK_Enter.constprop.18 +08017980 l F .text 000000a0 sm_EAP_INITIALIZE_Enter +00000000 l df *ABS* 00000000 eap_server_methods.c +20004634 l O .bss 00000004 eap_methods +00000000 l df *ABS* 00000000 wps_hostapd.c +080180e0 l F .text 0000002e wps_for_each +08018110 l F .text 00000028 hostapd_wps_for_each +08018140 l F .text 00000002 hostapd_wps_pin_needed_cb +08018150 l F .text 0000000e hostapd_wps_cred_cb +08018440 l F .text 000000ec hapd_wps_cred_cb +08018160 l F .text 0000002c hostapd_wps_event_cb +08018370 l F .text 0000009c wps_pwd_auth_fail +08018190 l F .text 0000000a count_interface_cb +080181a0 l F .text 0000002a wps_ap_pin_disable +08018bb0 l F .text 00000004 hostapd_wps_ap_pin_timeout +080181d0 l F .text 00000060 hostapd_wps_set_vendor_ext +08018230 l F .text 0000003c get_uuid_cb +08018270 l F .text 0000005a hostapd_wps_new_psk_cb +080182d0 l F .text 00000012 hostapd_wps_enrollee_seen_cb +080182f0 l F .text 0000001a wps_stop_registrar +08018310 l F .text 00000036 hostapd_wps_set_ie_cb +08018350 l F .text 00000016 hostapd_wps_reenable_ap_pin +08018410 l F .text 0000002a hapd_new_ap_event.isra.4 +08018530 l F .text 00000078 hostapd_wps_probe_req_rx +080185b0 l F .text 0000003c hostapd_wps_reg_success_cb +00000000 l df *ABS* 00000000 wpa_auth.c +08018bc0 l F .text 00000016 wpa_auth_pmksa_clear_cb +08018be0 l F .text 00000018 wpa_auth_pmksa_free_cb +08018c00 l F .text 00000050 wpa_group_config_group_keys +08018c50 l F .text 00000040 wpa_rekey_gmk +08018c90 l F .text 0000006c wpa_group_init_gmk_and_counter +08018d00 l F .text 00000088 wpa_verify_key_mic +08018d90 l F .text 00000032 wpa_free_sta_sm +08018dd0 l F .text 00000150 sm_WPA_PTK_PTKCALCNEGOTIATING_Enter.constprop.14 +0801a4c0 l F .text 00000030 wpa_send_eapol_timeout +08018f20 l F .text 0000002c sm_WPA_PTK_DISCONNECT_Enter.constprop.17 +08018f50 l F .text 000000ec wpa_gtk_update +08019040 l F .text 00000080 sm_WPA_PTK_AUTHENTICATION2_Enter.constprop.11 +080190c0 l F .text 0000003c wpa_group_setkeys +0801a530 l F .text 00000068 wpa_group_update_sta +08019100 l F .text 0000007a wpa_group_sm_step +08019180 l F .text 00000082 wpa_group_init +08019210 l F .text 00000058 wpa_rekey_gtk +0801a5a0 l F .text 00000004 wpa_sm_call_step +0801a4f0 l F .text 00000034 wpa_rekey_ptk +080198d0 l F .text 000000a8 wpa_send_eapol +08019980 l F .text 000000f0 sm_WPA_PTK_PTKSTART_Enter.constprop.15 +08019a70 l F .text 00000108 sm_WPA_PTK_GROUP_REKEYNEGOTIATING_Enter.constprop.8 +08019b80 l F .text 00000174 sm_WPA_PTK_PTKINITNEGOTIATING_Enter.constprop.18 +08019d50 l F .text 000000a2 sm_WPA_PTK_INITIALIZE_Enter.constprop.10 +08019e00 l F .text 000006bc wpa_sm_step +080336a0 l O .text 0000000f CSWTCH.44 +00000000 l df *ABS* 00000000 wpa_auth_ie.c +0801ade0 l F .text 0000001a wpa_auth_okc_iter +00000000 l df *ABS* 00000000 pmksa_cache_auth.c +0801b650 l F .text 0000004a pmksa_cache_link_entry +0801b6a0 l F .text 0000007e pmksa_cache_free_entry +0801b720 l F .text 00000068 pmksa_cache_expire +00000000 l df *ABS* 00000000 system_stm32f10x.c +00000000 l df *ABS* 00000000 misc.c +00000000 l df *ABS* 00000000 stm32f10x_bkp.c +00000000 l df *ABS* 00000000 stm32f10x_dma.c +00000000 l df *ABS* 00000000 stm32f10x_exti.c +00000000 l df *ABS* 00000000 stm32f10x_flash.c +00000000 l df *ABS* 00000000 stm32f10x_gpio.c +00000000 l df *ABS* 00000000 stm32f10x_pwr.c +00000000 l df *ABS* 00000000 stm32f10x_rcc.c +20001228 l O .data 00000004 ADCPrescTable +2000122c l O .data 00000010 APBAHBPrescTable +00000000 l df *ABS* 00000000 stm32f10x_rtc.c +00000000 l df *ABS* 00000000 stm32f10x_sdio.c +00000000 l df *ABS* 00000000 stm32f10x_tim.c +0801c9d0 l F .text 00000084 TI1_Config +0801ca60 l F .text 00000090 TI2_Config +00000000 l df *ABS* 00000000 stm32f10x_dbgmcu.c +00000000 l df *ABS* 00000000 stm32f10x_usart.c +00000000 l df *ABS* 00000000 tcpip.c +20004638 l O .bss 00000004 mbox +00000000 l df *ABS* 00000000 def.c +00000000 l df *ABS* 00000000 dhcp.c +0801d020 l F .text 00000042 dhcp_option_long +0801d070 l F .text 000001a8 dhcp_create_msg +0801d220 l F .text 0000005c dhcp_option_hostname +0801d280 l F .text 0000002a dhcp_check +0801d2b0 l F .text 00000118 dhcp_bind +0801d3d0 l F .text 00000048 dhcp_option_trailer +0801d420 l F .text 00000030 dhcp_delete_msg +0801d450 l F .text 000000cc dhcp_rebind +0801d520 l F .text 000000ec dhcp_reboot +0801d610 l F .text 00000178 dhcp_select +2000463c l O .bss 00000004 xid.7854 +00000000 l df *ABS* 00000000 dns.c +0801dcb0 l F .text 00000108 dns_send +0801ddc0 l F .text 000000b0 dns_check_entry +0801de70 l F .text 000001b0 dns_recv +20004640 l O .bss 00000460 dns_table +20004aa0 l O .bss 00000008 dns_servers +20004aa8 l O .bss 00000203 dns_payload_buffer +20004cac l O .bss 00000004 dns_pcb +20004cb0 l O .bss 00000004 dns_payload +00000000 l df *ABS* 00000000 init.c +00000000 l df *ABS* 00000000 memp.c +08033fe0 l O .text 00000020 memp_num +20004cb4 l O .bss 00007f27 memp_memory +2000cbdc l O .bss 00000040 memp_tab +08034020 l O .text 00000020 memp_sizes +00000000 l df *ABS* 00000000 netif.c +00000000 l df *ABS* 00000000 pbuf.c +0801e400 l F .text 00000038 pbuf_free_ooseq_callback +0801e440 l F .text 0000003c pbuf_pool_is_empty +00000000 l df *ABS* 00000000 stats.c +00000000 l df *ABS* 00000000 tcp.c +0801ef00 l F .text 0000016c tcp_close_shutdown +2000cdb0 l O .bss 00000001 tcp_timer +2000cdbc l O .bss 00000001 tcp_timer_ctr +00000000 l df *ABS* 00000000 tcp_out.c +0801f1f0 l F .text 000000bc tcp_create_segment +0801f2b0 l F .text 0000005a tcp_output_alloc_header.constprop.1 +00000000 l df *ABS* 00000000 udp.c +2000123c l O .data 00000002 udp_port +00000000 l df *ABS* 00000000 timers.c +0801fd70 l F .text 00000030 tcpip_tcp_timer +2000cdcc l O .bss 00000004 tcpip_tcp_timer_active +2000cdd0 l O .bss 00000004 next_timeout +00000000 l df *ABS* 00000000 icmp.c +0801fda0 l F .text 0000009a icmp_send_response +00000000 l df *ABS* 00000000 igmp.c +0801fe50 l F .text 000000c8 igmp_send +0801ff20 l F .text 00000034 igmp_delaying_member +2000cdd4 l O .bss 00000004 allsystems +2000cdd8 l O .bss 00000004 allrouters +2000cddc l O .bss 00000004 igmp_group_list +00000000 l df *ABS* 00000000 inet_chksum.c +08020010 l F .text 0000007c lwip_standard_chksum +00000000 l df *ABS* 00000000 ip.c +2000cde0 l O .bss 00000002 ip_id +00000000 l df *ABS* 00000000 ip_addr.c +2000cde4 l O .bss 00000010 str.7295 +00000000 l df *ABS* 00000000 ip_frag.c +08020600 l F .text 0000009c ip_reass_free_complete_datagram +2000cdf4 l O .bss 00000004 reassdatagrams +2000cdf8 l O .bss 00000002 ip_reass_pbufcount +00000000 l df *ABS* 00000000 etharp.c +08020810 l F .text 00000024 etharp_send_ip +08020840 l F .text 00000048 etharp_free_entry +08020890 l F .text 00000100 etharp_find_entry +2000cdfa l O .bss 00000001 etharp_cached_entry +2000cdfc l O .bss 000000c8 arp_table +00000000 l df *ABS* 00000000 sys_arch.c +00000000 l df *ABS* 00000000 libwismart_softap.c +2000cec4 l O .bss 00000004 client_change_cb +2000cec8 l O .bss 00000004 started_cb +00000000 l df *ABS* 00000000 libwismart_pbuf_queues.c +08020e00 l F .text 0000005c _PBufQueue_RemoveLast +00000000 l df *ABS* 00000000 ec_tools.c +08020fa0 l F .text 0000000e FunctionExecutioner +00000000 l df *ABS* 00000000 eeprom.c +08020ff0 l F .text 0000005a EE_FindValidPage_ +00000000 l df *ABS* 00000000 blacklist.c +00000000 l df *ABS* 00000000 bss.c +08021280 l F .text 00000036 wpa_bss_in_use +080212c0 l F .text 00000042 wpa_bss_remove +08021310 l F .text 0000008c wpa_bss_copy_res +08021670 l F .text 0000012c are_ies_equal +00000000 l df *ABS* 00000000 config.c +08021b20 l F .text 0000002c wpa_config_parse_int +08021b50 l F .text 000000dc wpa_config_parse_auth_alg +08021c30 l F .text 00000118 wpa_config_parse_key_mgmt +08021d50 l F .text 000000d8 wpa_config_parse_proto +08021e30 l F .text 00000136 wpa_config_parse_eap +08021f70 l F .text 000000f4 wpa_config_parse_cipher.isra.1 +08022070 l F .text 00000020 wpa_config_parse_group +08022090 l F .text 00000020 wpa_config_parse_pairwise +080220b0 l F .text 0000007c wpa_config_parse_string +08022130 l F .text 00000074 wpa_config_parse_str +080221b0 l F .text 00000050 wpa_config_parse_wep_key.isra.3 +08022200 l F .text 00000010 wpa_config_parse_wep_key3 +08022210 l F .text 00000010 wpa_config_parse_wep_key2 +08022220 l F .text 00000010 wpa_config_parse_wep_key1 +08022230 l F .text 00000010 wpa_config_parse_wep_key0 +08022240 l F .text 000000b4 wpa_config_parse_password +08022300 l F .text 0000009a wpa_config_parse_freqs.isra.5 +080223a0 l F .text 00000024 wpa_config_parse_freq_list +080223d0 l F .text 00000024 wpa_config_parse_scan_freq +08022400 l F .text 000000ac wpa_config_parse_psk +080224b0 l F .text 00000044 wpa_config_parse_bssid +080342a0 l O .text 0000071c ssid_fields +00000000 l df *ABS* 00000000 eap_common.c +00000000 l df *ABS* 00000000 eap_methods.c +2000cecc l O .bss 00000004 eap_methods +00000000 l df *ABS* 00000000 eap.c +08022a90 l F .text 00000042 sm_EAP_FAILURE_Enter +08022ae0 l F .text 000000ce sm_EAP_INITIALIZE_Enter +08022bb0 l F .text 00000054 eap_peer_sm_tls_event +08022c10 l F .text 0000003c sm_EAP_SUCCESS_Enter.constprop.7 +08022c50 l F .text 00000028 sm_EAP_DISCARD_Enter.constprop.11 +08022c80 l F .text 000000b4 sm_EAP_SEND_RESPONSE_Enter.constprop.12 +08022d40 l F .text 0000011c sm_EAP_METHOD_Enter.constprop.13 +00000000 l df *ABS* 00000000 eapol_supp_sm.c +08023a90 l F .text 00000044 sm_SUPP_PAE_DISCONNECTED_Enter +08023ae0 l F .text 00000028 eapol_sm_txLogoff +08023b10 l F .text 00000006 eapol_sm_get_config +08023b20 l F .text 00000008 eapol_sm_get_eapReqData +08023b30 l F .text 00000048 eapol_sm_get_bool +08023b80 l F .text 00000044 eapol_sm_set_bool +08023bd0 l F .text 0000000c eapol_sm_get_int +08023be0 l F .text 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wpa_supplicant_event_associnfo +08025030 l F .text 00000028 wpa_supplicant_req_new_scan.constprop.16 +08025170 l F .text 00000724 _wpa_supplicant_event_scan_results +00000000 l df *ABS* 00000000 ieee802_11_common.c +00000000 l df *ABS* 00000000 l2_packet_none.c +08026380 l F .text 00000020 l2_packet_receive +00000000 l df *ABS* 00000000 md5-internal.c +08026430 l F .text 0000078e MD5Transform +00000000 l df *ABS* 00000000 md5.c +00000000 l df *ABS* 00000000 notify.c +00000000 l df *ABS* 00000000 pmksa_cache.c +08027000 l F .text 00000034 pmksa_cache_free_entry +08027040 l F .text 00000034 pmksa_cache_reauth +080270c0 l F .text 00000070 pmksa_cache_set_expiration +08027130 l F .text 00000034 pmksa_cache_expire +00000000 l df *ABS* 00000000 preauth.c +08027450 l F .text 00000052 rsn_preauth_eapol_send +080274b0 l F .text 00000054 rsn_preauth_receive +080277f0 l F .text 0000005a rsn_preauth_eapol_cb +080277d0 l F .text 00000012 rsn_preauth_timeout +00000000 l df *ABS* 00000000 rc4.c +00000000 l df *ABS* 00000000 scan.c +08027a80 l F .text 00000016 freq_cmp +08027aa0 l F .text 000000a8 wpa_supplicant_extra_ies.isra.1 +08027ee0 l F .text 00000478 wpa_supplicant_scan +08027e70 l F .text 0000001a wpa_supplicant_delayed_sched_scan_timeout +08027c40 l F .text 0000000a wpa_supplicant_sched_scan_timeout +080283b0 l F .text 00000070 wpa_scan_get_max_rate +08028480 l F .text 00000120 wpa_scan_result_compar +08028650 l F .text 000000ae wpa_scan_result_wps_compar +00000000 l df *ABS* 00000000 sha1-internal.c +00000000 l df *ABS* 00000000 sha1.c +00000000 l df *ABS* 00000000 sha1-pbkdf2.c +00000000 l df *ABS* 00000000 tls_internal.c +2000cf20 l O .bss 00000004 tls_ref_count +00000000 l df *ABS* 00000000 tlsv1_client.c +00000000 l df *ABS* 00000000 uuid.c +00000000 l df *ABS* 00000000 wpabuf.c +00000000 l df *ABS* 00000000 wpa_common.c +0802a200 l F .text 00000066 rsn_selector_to_bitfield +0802a270 l F .text 00000066 wpa_selector_to_bitfield +00000000 l df *ABS* 00000000 wpa_ie.c +00000000 l df *ABS* 00000000 wpa.c +0802ac30 l F .text 0000001c wpa_sm_set_rekey_offload +0802ac50 l F .text 00000098 wpa_supplicant_install_gtk +0802acf0 l F .text 00000004 wpa_sm_start_preauth +0802ad00 l F .text 00000074 wpa_supplicant_key_neg_complete +0802ad80 l F .text 00000080 wpa_supplicant_check_group_cipher.isra.3 +0802afa0 l F .text 00000008 wpa_sm_rekey_ptk +00000000 l df *ABS* 00000000 wpas_glue.c +00000000 l df *ABS* 00000000 wps_attr_build.c +00000000 l df *ABS* 00000000 wps_attr_parse.c +00000000 l df *ABS* 00000000 wps_common.c +00000000 l df *ABS* 00000000 wps_dev_attr.c +00000000 l df *ABS* 00000000 aes-wrap.c +00000000 l df *ABS* 00000000 ieee802_11_shared.c +00000000 l df *ABS* 00000000 drv_callbacks.c +00000000 l df *ABS* 00000000 driver_common.c +00000000 l df *ABS* 00000000 sockets.c +00000000 l df *ABS* 00000000 aes-internal-dec.c +00000000 l df *ABS* 00000000 aes-internal-enc.c +00000000 l df *ABS* 00000000 aes-internal.c +00000000 l df *ABS* 00000000 aes-unwrap.c +00000000 l df *ABS* 00000000 crypto_internal.c +00000000 l df *ABS* 00000000 ctype_.c +00000000 l df *ABS* 00000000 impure.c +20000c10 l O .data 00000428 impure_data +00000000 l df *ABS* 00000000 chregistry.c +00000000 l df *ABS* 00000000 hwif.c +00000000 l df *ABS* 00000000 wpa_debug.c +00000000 l df *ABS* 00000000 tcp_in.c +00000000 l df *ABS* 00000000 reent.c +00000000 l df *ABS* 00000000 +08035f88 l .text 00000000 _etext +00018000 l *ABS* 00000000 __ram_size__ +00000000 l startup 00000000 _text +20000000 l startup 00000000 __ram_start__ +20018000 l *ABS* 00000000 __ram_end__ +2000cf34 l .bss 00000000 _end +00000200 l *ABS* 00000000 __main_stack_size__ +00000a00 l *ABS* 00000000 __process_stack_size__ +0801c370 g F .text 0000002c PWR_EnterSTANDBYMode +0802d5d0 g F .text 00000002 lwip_socket_init +0802df80 g F .text 00000016 aes_encrypt_deinit +08026ef0 g F .text 00000002 wpas_notify_scanning +08020120 g F .text 0000000c inet_chksum +08007e30 g F .text 0000000c libwismart_NetDown +08004f6c g F .text 00000034 _mprec_log10 +08020f90 g F .text 00000006 libwismart_PBufQueue_RemoveLast +0801d010 g F .text 00000004 lwip_ntohl +080263c0 g F .text 0000003c l2_packet_init +08013e80 g F .text 00000004 authsrv_init +080077f0 g F .text 0000000e Vector58 +0800fcb0 g F .text 00000042 wpa_get_ntp_timestamp +0801c460 g F .text 0000000a RCC_HSICmd +08006940 w F .text 00000010 VectorE8 +08006940 w F .text 00000010 Vector9C +0801e560 g F .text 0000003e pbuf_realloc +08008fc0 g F .text 000000fc LwIP_Periodic_Handle +20001324 g O .bss 00000004 dhcp_result_cb +08004fe8 g F .text 00000056 __any_on +080076c0 g F .text 00000004 _isatty_r +0802e718 g O .text 00000028 __mprec_tinytens +20001590 g O .bss 00000130 _wismart_idle_thread_wa +08006764 g F .text 00000012 __aeabi_dcmple +08027bd0 g F .text 0000002c wpa_supplicant_delayed_sched_scan +08014d10 g F .text 000000e0 michael_mic_failure +08001140 g F .text 000000ba strcpy +0801bee0 g F .text 00000022 FLASH_Unlock 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.text 000000a0 libwismart_WiFiConnectedInd +08006940 w F .text 00000010 Vector8C +08017930 g F .text 00000008 eap_sm_notify_cached +08027b70 g F .text 00000060 wpa_supplicant_req_scan +08008510 g F .text 00000004 vfprintf_UART_SendCharIrq +08007bf0 g F .text 0000001c SendSnrValueBack +0801e730 g F .text 0000004c pbuf_cat +0801baf0 g F .text 0000007c NVIC_Init +08007230 g F .text 0000001a chEvtUnregister +0802a160 g F .text 00000022 wpabuf_put +0800a130 g F .text 00000060 WiFi_Client_Update_TIM +20002965 g O .bss 00000001 DHCP_not_update +08020da0 g F .text 00000060 libwismart_SoftAP_Client_Change_Ind +08011520 g F .text 00000106 wps_build_probe_req_ie +080227d0 g F .text 0000003c wpa_config_remove_network +08000290 g F .text 000000bc memmove +080210c0 g F .text 0000003c EE_Format_ +08006940 w F .text 00000010 VectorDC +08020340 g F .text 0000004c ip_output +080240e0 g F .text 0000053c eapol_sm_step +0801fbb0 g F .text 00000048 udp_sendto +0802a7c0 g F .text 00000022 wpa_parse_wpa_ie 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../..//econais/build/libwismart.a(libwismart_uart.o) (HW_DebugTrace_Init) +../..//econais/build/libwismart.a(power.o) + ../..//econais/build/libwismart.a(libwismart_power.o) (HW_Power_EnterMode) +../..//econais/build/libwismart.a(library_bootloader.o) + ../..//econais/build/libwismart.a(transport.o) (bootloader_get_client_fw_info) +../..//econais/build/libwismart.a(common.o) + ../..//econais/build/libwismart.a(libwismart.o) (hwaddr_aton) +../..//econais/build/libwismart.a(config_wifiengine.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) (wpa_set_ssid_psk) +../..//econais/build/libwismart.a(driver_wifiengine.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) (NataliaEngine_DeleteAllKey) +../..//econais/build/libwismart.a(main_wifiengine.o) + ../..//econais/build/libwismart.a(config_wifiengine.o) (wpa_wifiengine_config) +../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(common.o) (os_get_time) +../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(main_wifiengine.o) (wpa_supplicant_rx_eapol) +../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) (wps_build_assoc_req_ie) +../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) (wps_registrar_get_msg) +../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) (wpas_wps_get_req_type) +../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) (wpa_supplicant_ap_deinit) +../..//econais/build/libwismart.a(hostapd.o) + ../..//econais/build/libwismart.a(ap.o) (hostapd_setup_interface) +../..//econais/build/libwismart.a(wpa_auth_glue.o) + ../..//econais/build/libwismart.a(hostapd.o) (hostapd_setup_wpa) +../..//econais/build/libwismart.a(utils.o) + ../..//econais/build/libwismart.a(ap.o) (hostapd_register_probereq_cb) +../..//econais/build/libwismart.a(authsrv.o) + ../..//econais/build/libwismart.a(hostapd.o) (authsrv_init) +../..//econais/build/libwismart.a(ap_config.o) + ../..//econais/build/libwismart.a(ap.o) (hostapd_config_defaults) +../..//econais/build/libwismart.a(sta_info.o) + ../..//econais/build/libwismart.a(ap.o) (ap_for_each_sta) +../..//econais/build/libwismart.a(tkip_countermeasures.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) (ieee80211_tkip_countermeasures_deinit) +../..//econais/build/libwismart.a(ap_mlme.o) + ../..//econais/build/libwismart.a(tkip_countermeasures.o) (mlme_michaelmicfailure_indication) +../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) (ieee802_1x_set_sta_authorized) +../..//econais/build/libwismart.a(eapol_auth_sm.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) (eapol_auth_free) +../..//econais/build/libwismart.a(ieee802_11_auth.o) + ../..//econais/build/libwismart.a(hostapd.o) (hostapd_acl_init) +../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) (hostapd_sta_flags_to_drv) +../..//econais/build/libwismart.a(beacon.o) + ../..//econais/build/libwismart.a(hostapd.o) (ieee802_11_set_beacon) +../..//econais/build/libwismart.a(eap_server.o) + ../..//econais/build/libwismart.a(eapol_auth_sm.o) (eap_server_sm_init) +../..//econais/build/libwismart.a(eap_server_methods.o) + ../..//econais/build/libwismart.a(eap_server.o) (eap_server_get_eap_method) +../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(hostapd.o) (hostapd_init_wps) +../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) (wpa_auth_init) +../..//econais/build/libwismart.a(wpa_auth_ie.o) + ../..//econais/build/libwismart.a(wpa_auth.o) (wpa_auth_gen_wpa_ie) +../..//econais/build/libwismart.a(pmksa_cache_auth.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) (pmksa_cache_to_eapol_data) +../..//econais/build/libwismart.a(system_stm32f10x.o) + ../..//econais/build/libwismart.a(libwismart.o) (SystemInit) +../..//econais/build/libwismart.a(misc.o) + build/obj/buttonExample.o (NVIC_Init) +../..//econais/build/libwismart.a(stm32f10x_bkp.o) + ../..//econais/build/libwismart.a(rtc.o) (BKP_DeInit) +../..//econais/build/libwismart.a(stm32f10x_dma.o) + ../..//econais/build/libwismart.a(uart.o) (DMA_DeInit) +../..//econais/build/libwismart.a(stm32f10x_exti.o) + build/obj/buttonExample.o (EXTI_Init) +../..//econais/build/libwismart.a(stm32f10x_flash.o) + ../..//econais/build/libwismart.a(rcc.o) (FLASH_SetLatency) +../..//econais/build/libwismart.a(stm32f10x_gpio.o) + build/obj/buttonExample.o (GPIO_Init) +../..//econais/build/libwismart.a(stm32f10x_pwr.o) + ../..//econais/build/libwismart.a(rtc.o) (PWR_DeInit) +../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(rcc.o) (RCC_DeInit) +../..//econais/build/libwismart.a(stm32f10x_rtc.o) + ../..//econais/build/libwismart.a(rtc.o) (RTC_ITConfig) +../..//econais/build/libwismart.a(stm32f10x_sdio.o) + ../..//econais/build/libwismart.a(wifi_transport.o) (SDIO_DeInit) +../..//econais/build/libwismart.a(stm32f10x_tim.o) + ../..//econais/build/libwismart.a(rtc.o) (TIM_TimeBaseInit) +../..//econais/build/libwismart.a(stm32f10x_dbgmcu.o) + ../..//econais/build/libwismart.a(rcc.o) (DBGMCU_Config) +../..//econais/build/libwismart.a(stm32f10x_usart.o) + ../..//econais/build/libwismart.a(uart.o) (USART_DeInit) +../..//econais/build/libwismart.a(tcpip.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) (tcpip_init) +../..//econais/build/libwismart.a(def.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) (lwip_htons) +../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(netconf.o) (dhcp_inform) +../..//econais/build/libwismart.a(dns.o) + ../..//econais/build/libwismart.a(dhcp.o) (dns_setserver) +../..//econais/build/libwismart.a(init.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) (lwip_init) +../..//econais/build/libwismart.a(memp.o) + ../..//econais/build/libwismart.a(init.o) (memp_init) +../..//econais/build/libwismart.a(netif.o) + ../..//econais/build/libwismart.a(init.o) (netif_init) +../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(wifi_engine.o) (pbuf_header) +../..//econais/build/libwismart.a(stats.o) + ../..//econais/build/libwismart.a(init.o) (stats_init) +../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(init.o) (tcp_init) +../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(tcp.o) (tcp_enqueue_flags) +../..//econais/build/libwismart.a(udp.o) + ../..//econais/build/libwismart.a(init.o) (udp_init) +../..//econais/build/libwismart.a(timers.o) + ../..//econais/build/libwismart.a(init.o) (sys_timeouts_init) +../..//econais/build/libwismart.a(icmp.o) + ../..//econais/build/libwismart.a(udp.o) (icmp_dest_unreach) +../..//econais/build/libwismart.a(igmp.o) + ../..//econais/build/libwismart.a(init.o) (igmp_init) +../..//econais/build/libwismart.a(inet_chksum.o) + ../..//econais/build/libwismart.a(tcp_out.o) (inet_chksum_pseudo) +../..//econais/build/libwismart.a(ip.o) + ../..//econais/build/libwismart.a(tcp.o) (ip_route) +../..//econais/build/libwismart.a(ip_addr.o) + ../..//econais/build/libwismart.a(wifi_filter.o) (ip4_addr_isbroadcast) +../..//econais/build/libwismart.a(ip_frag.o) + ../..//econais/build/libwismart.a(netconf.o) (ip_reass_tmr) +../..//econais/build/libwismart.a(etharp.o) + ../..//econais/build/libwismart.a(netconf.o) (etharp_tmr) +../..//econais/build/libwismart.a(ethernetif.o) + ../..//econais/build/libwismart.a(netconf.o) (ethernetif_input) +../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(init.o) (sys_init) +../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(libwismart.o) (upnpDebugEnable) +../..//econais/build/libwismart.a(upnp_devices.o) + ../..//econais/build/libwismart.a(upnp_core.o) (upnpDevicesList) +../..//econais/build/libwismart.a(upnp_mediaRenderer.o) + ../..//econais/build/libwismart.a(upnp_core.o) (upnpSetMediaRendererInfo) +../..//econais/build/libwismart.a(upnp_renderingControl.o) + ../..//econais/build/libwismart.a(upnp_mediaRenderer.o) (RenderControl_service) +../..//econais/build/libwismart.a(upnp_connectionManager.o) + ../..//econais/build/libwismart.a(upnp_mediaRenderer.o) (ConnectionMngr_service) +../..//econais/build/libwismart.a(upnp_avTransport.o) + ../..//econais/build/libwismart.a(upnp_mediaRenderer.o) (AVTransport_service) +../..//econais/build/libwismart.a(upnp_mediaServer.o) + ../..//econais/build/libwismart.a(upnp_core.o) (upnpSetMediaServerInfo) +../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + ../..//econais/build/libwismart.a(libwismart.o) (cdPlaybackFileOpen) +../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(libwismart.o) (dlnaSetVolumeCb) +../..//econais/build/libwismart.a(upnp_serviceOperations.o) + ../..//econais/build/libwismart.a(upnp_renderingControl.o) (upnp_getServiceVariableValue) +../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_renderingControl.o) (upnpSubscription_stateVariableChanged) +../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) (upnpNotifying_addTask) +../..//econais/build/libwismart.a(upnp_control.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) (upnpControl_buildReponseHeader) +../..//econais/build/libwismart.a(upnp_configurationServer.o) + ../..//econais/build/libwismart.a(libwismart.o) (upnpEnterConfigurationMode) +../..//econais/build/libwismart.a(ff.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) (f_open) +../..//econais/build/libwismart.a(diskio.o) + ../..//econais/build/libwismart.a(ff.o) (disk_initialize) +../..//econais/build/libwismart.a(ccsbcs.o) + ../..//econais/build/libwismart.a(ff.o) (ff_convert) +../..//econais/build/libwismart.a(syscall.o) + ../..//econais/build/libwismart.a(ff.o) (ff_cre_syncobj) +../..//econais/build/libwismart.a(sdCardOverSpi.o) + ../..//econais/build/libwismart.a(diskio.o) (sdCardInit) +../..//econais/build/libwismart.a(libwismart_softap.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) (libwismart_SoftAP_Started_Ind) +../..//econais/build/libwismart.a(libwismart_pbuf_queues.o) + ../..//econais/build/libwismart.a(wifi_softap.o) (libwismart_PBufQueue_Deinit) +../..//econais/build/libwismart.a(ec_tools.o) + ../..//econais/build/libwismart.a(main_wifiengine.o) (libwismart_ThreadExec) +../..//econais/build/libwismart.a(eeprom.o) + ../..//econais/build/libwismart.a(registry_driver.o) (EE_ReadVariable_) +../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) (hsSetHttpResponseHeaders) +../..//econais/build/libwismart.a(base64.o) + ../..//econais/build/libwismart.a(wps_registrar.o) (base64_encode) +../..//econais/build/libwismart.a(blacklist.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) (wpa_blacklist_get) +../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) (wpa_bss_get) +../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(config_wifiengine.o) (wpa_config_add_network) +../..//econais/build/libwismart.a(dh_group5.o) + ../..//econais/build/libwismart.a(wps.o) (dh5_free) +../..//econais/build/libwismart.a(dh_groups.o) + ../..//econais/build/libwismart.a(dh_group5.o) (dh_groups_get) +../..//econais/build/libwismart.a(drivers.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) (wpa_drivers) +../..//econais/build/libwismart.a(eap_common.o) + ../..//econais/build/libwismart.a(eapol_auth_sm.o) (eap_get_id) +../..//econais/build/libwismart.a(eap_methods.o) + ../..//econais/build/libwismart.a(config.o) (eap_peer_get_type) +../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) (eap_is_wps_pbc_enrollee) +../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) (eapol_sm_get_method_name) +../..//econais/build/libwismart.a(eap_register.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) (eap_register_methods) +../..//econais/build/libwismart.a(eap_tls.o) + ../..//econais/build/libwismart.a(eap_register.o) (eap_peer_tls_register) +../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_register.o) (eap_peer_ttls_register) +../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(eap_register.o) (eap_peer_wsc_register) +../..//econais/build/libwismart.a(eloop_wifiengine.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) (eloop_init) +../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) (wpa_supplicant_stop_countermeasures) +../..//econais/build/libwismart.a(ieee802_11_common.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) (ieee802_11_parse_elems) +../..//econais/build/libwismart.a(l2_packet_none.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) (l2_packet_get_own_addr) +../..//econais/build/libwismart.a(md5-internal.o) + ../..//econais/build/libwismart.a(eap.o) (md5_vector) +../..//econais/build/libwismart.a(md5.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) (hmac_md5) +../..//econais/build/libwismart.a(mschapv2.o) + ../..//econais/build/libwismart.a(eap_ttls.o) (mschapv2_derive_response) +../..//econais/build/libwismart.a(ms_funcs.o) + ../..//econais/build/libwismart.a(mschapv2.o) (nt_password_hash) +../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) (wpas_notify_supplicant_initialized) +../..//econais/build/libwismart.a(pmksa_cache.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) (pmksa_cache_clear_current) +../..//econais/build/libwismart.a(preauth.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) (pmksa_candidate_free) +../..//econais/build/libwismart.a(rc4.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) (rc4_skip) +../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) (wpa_supplicant_enabled_networks) +../..//econais/build/libwismart.a(sha1-internal.o) + ../..//econais/build/libwismart.a(ms_funcs.o) (sha1_vector) +../..//econais/build/libwismart.a(sha1.o) + ../..//econais/build/libwismart.a(wpa_auth.o) (sha1_prf) +../..//econais/build/libwismart.a(sha1-pbkdf2.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) (pbkdf2_sha1) +../..//econais/build/libwismart.a(sha256.o) + ../..//econais/build/libwismart.a(wps_registrar.o) (hmac_sha256_vector) +../..//econais/build/libwismart.a(tls_internal.o) + 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0x0801c4a0 RCC_SYSCLKConfig + .text.RCC_GetSYSCLKSource + 0x0801c4c0 0x10 ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + 0x0801c4c0 RCC_GetSYSCLKSource + .text.RCC_HCLKConfig + 0x0801c4d0 0x20 ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + 0x0801c4d0 RCC_HCLKConfig + .text.RCC_PCLK1Config + 0x0801c4f0 0x20 ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + 0x0801c4f0 RCC_PCLK1Config + .text.RCC_PCLK2Config + 0x0801c510 0x20 ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + 0x0801c510 RCC_PCLK2Config + .text.RCC_LSEConfig + 0x0801c530 0x20 ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + 0x0801c530 RCC_LSEConfig + .text.RCC_LSICmd + 0x0801c550 0x10 ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + 0x0801c550 RCC_LSICmd + .text.RCC_RTCCLKConfig + 0x0801c560 0x10 ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + 0x0801c560 RCC_RTCCLKConfig + .text.RCC_RTCCLKCmd + 0x0801c570 0x10 ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + 0x0801c570 RCC_RTCCLKCmd + .text.RCC_GetClocksFreq + 0x0801c580 0xb0 ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + 0x0801c580 RCC_GetClocksFreq + .text.RCC_AHBPeriphClockCmd + 0x0801c630 0x20 ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + 0x0801c630 RCC_AHBPeriphClockCmd + .text.RCC_APB2PeriphClockCmd + 0x0801c650 0x20 ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + 0x0801c650 RCC_APB2PeriphClockCmd + .text.RCC_APB1PeriphClockCmd + 0x0801c670 0x20 ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + 0x0801c670 RCC_APB1PeriphClockCmd + .text.RCC_APB1PeriphResetCmd + 0x0801c690 0x20 ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + 0x0801c690 RCC_APB1PeriphResetCmd + .text.RCC_BackupResetCmd + 0x0801c6b0 0x10 ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + 0x0801c6b0 RCC_BackupResetCmd + .text.RCC_GetFlagStatus + 0x0801c6c0 0x30 ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + 0x0801c6c0 RCC_GetFlagStatus + .text.RTC_ITConfig + 0x0801c6f0 0x20 ../..//econais/build/libwismart.a(stm32f10x_rtc.o) + 0x0801c6f0 RTC_ITConfig + .text.RTC_GetCounter + 0x0801c710 0x20 ../..//econais/build/libwismart.a(stm32f10x_rtc.o) + 0x0801c710 RTC_GetCounter + .text.RTC_SetPrescaler + 0x0801c730 0x30 ../..//econais/build/libwismart.a(stm32f10x_rtc.o) + 0x0801c730 RTC_SetPrescaler + .text.RTC_SetAlarm + 0x0801c760 0x30 ../..//econais/build/libwismart.a(stm32f10x_rtc.o) + 0x0801c760 RTC_SetAlarm + .text.RTC_WaitForLastTask + 0x0801c790 0x20 ../..//econais/build/libwismart.a(stm32f10x_rtc.o) + 0x0801c790 RTC_WaitForLastTask + .text.RTC_WaitForSynchro + 0x0801c7b0 0x30 ../..//econais/build/libwismart.a(stm32f10x_rtc.o) + 0x0801c7b0 RTC_WaitForSynchro + .text.RTC_GetFlagStatus + 0x0801c7e0 0x20 ../..//econais/build/libwismart.a(stm32f10x_rtc.o) + 0x0801c7e0 RTC_GetFlagStatus + .text.RTC_ClearFlag + 0x0801c800 0x20 ../..//econais/build/libwismart.a(stm32f10x_rtc.o) + 0x0801c800 RTC_ClearFlag + .text.RTC_GetITStatus + 0x0801c820 0x30 ../..//econais/build/libwismart.a(stm32f10x_rtc.o) + 0x0801c820 RTC_GetITStatus + .text.RTC_ClearITPendingBit + 0x0801c850 0x20 ../..//econais/build/libwismart.a(stm32f10x_rtc.o) + 0x0801c850 RTC_ClearITPendingBit + .text.SDIO_DeInit + 0x0801c870 0x30 ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + 0x0801c870 SDIO_DeInit + .text.SDIO_ClockCmd + 0x0801c8a0 0x10 ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + 0x0801c8a0 SDIO_ClockCmd + .text.SDIO_SetPowerState + 0x0801c8b0 0x20 ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + 0x0801c8b0 SDIO_SetPowerState + .text.SDIO_ITConfig + 0x0801c8d0 0x20 ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + 0x0801c8d0 SDIO_ITConfig + .text.SDIO_DMACmd + 0x0801c8f0 0x10 ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + 0x0801c8f0 SDIO_DMACmd + .text.SDIO_SendCommand + 0x0801c900 0x30 ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + 0x0801c900 SDIO_SendCommand + .text.SDIO_GetResponse + 0x0801c930 0x20 ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + 0x0801c930 SDIO_GetResponse + .text.SDIO_DataConfig + 0x0801c950 0x30 ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + 0x0801c950 SDIO_DataConfig + .text.SDIO_SetSDIOOperation + 0x0801c980 0x10 ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + 0x0801c980 SDIO_SetSDIOOperation + .text.SDIO_ClearFlag + 0x0801c990 0x10 ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + 0x0801c990 SDIO_ClearFlag + .text.SDIO_GetITStatus + 0x0801c9a0 0x20 ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + 0x0801c9a0 SDIO_GetITStatus + .text.SDIO_ClearITPendingBit + 0x0801c9c0 0x10 ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + 0x0801c9c0 SDIO_ClearITPendingBit + .text.TI1_Config + 0x0801c9d0 0x90 ../..//econais/build/libwismart.a(stm32f10x_tim.o) + .text.TI2_Config + 0x0801ca60 0x90 ../..//econais/build/libwismart.a(stm32f10x_tim.o) + .text.TIM_TimeBaseInit + 0x0801caf0 0xc0 ../..//econais/build/libwismart.a(stm32f10x_tim.o) + 0x0801caf0 TIM_TimeBaseInit + .text.TIM_ICInit + 0x0801cbb0 0x1b0 ../..//econais/build/libwismart.a(stm32f10x_tim.o) + 0x0801cbb0 TIM_ICInit + .text.TIM_Cmd 0x0801cd60 0x20 ../..//econais/build/libwismart.a(stm32f10x_tim.o) + 0x0801cd60 TIM_Cmd + .text.TIM_ITConfig + 0x0801cd80 0x20 ../..//econais/build/libwismart.a(stm32f10x_tim.o) + 0x0801cd80 TIM_ITConfig + .text.TIM_GetITStatus + 0x0801cda0 0x20 ../..//econais/build/libwismart.a(stm32f10x_tim.o) + 0x0801cda0 TIM_GetITStatus + .text.TIM_ClearITPendingBit + 0x0801cdc0 0x10 ../..//econais/build/libwismart.a(stm32f10x_tim.o) + 0x0801cdc0 TIM_ClearITPendingBit + .text.DBGMCU_Config + 0x0801cdd0 0x20 ../..//econais/build/libwismart.a(stm32f10x_dbgmcu.o) + 0x0801cdd0 DBGMCU_Config + .text.USART_Init + 0x0801cdf0 0xd0 ../..//econais/build/libwismart.a(stm32f10x_usart.o) + 0x0801cdf0 USART_Init + .text.USART_Cmd + 0x0801cec0 0x20 ../..//econais/build/libwismart.a(stm32f10x_usart.o) + 0x0801cec0 USART_Cmd + .text.USART_ITConfig + 0x0801cee0 0x40 ../..//econais/build/libwismart.a(stm32f10x_usart.o) + 0x0801cee0 USART_ITConfig + .text.USART_DMACmd + 0x0801cf20 0x20 ../..//econais/build/libwismart.a(stm32f10x_usart.o) + 0x0801cf20 USART_DMACmd + .text.USART_SendData + 0x0801cf40 0x10 ../..//econais/build/libwismart.a(stm32f10x_usart.o) + 0x0801cf40 USART_SendData + .text.USART_OverSampling8Cmd + 0x0801cf50 0x20 ../..//econais/build/libwismart.a(stm32f10x_usart.o) + 0x0801cf50 USART_OverSampling8Cmd + .text.USART_GetFlagStatus + 0x0801cf70 0x10 ../..//econais/build/libwismart.a(stm32f10x_usart.o) + 0x0801cf70 USART_GetFlagStatus + .text.tcpip_callback_with_block + 0x0801cf80 0x60 ../..//econais/build/libwismart.a(tcpip.o) + 0x0801cf80 tcpip_callback_with_block + .text.lwip_htons + 0x0801cfe0 0x10 ../..//econais/build/libwismart.a(def.o) + 0x0801cfe0 lwip_htons + .text.lwip_ntohs + 0x0801cff0 0x10 ../..//econais/build/libwismart.a(def.o) + 0x0801cff0 lwip_ntohs + .text.lwip_htonl + 0x0801d000 0x10 ../..//econais/build/libwismart.a(def.o) + 0x0801d000 lwip_htonl + .text.lwip_ntohl + 0x0801d010 0x10 ../..//econais/build/libwismart.a(def.o) + 0x0801d010 lwip_ntohl + .text.dhcp_option_long + 0x0801d020 0x50 ../..//econais/build/libwismart.a(dhcp.o) + .text.dhcp_create_msg + 0x0801d070 0x1b0 ../..//econais/build/libwismart.a(dhcp.o) + .text.dhcp_option_hostname + 0x0801d220 0x60 ../..//econais/build/libwismart.a(dhcp.o) + .text.dhcp_check + 0x0801d280 0x30 ../..//econais/build/libwismart.a(dhcp.o) + .text.dhcp_bind + 0x0801d2b0 0x120 ../..//econais/build/libwismart.a(dhcp.o) + .text.dhcp_option_trailer + 0x0801d3d0 0x50 ../..//econais/build/libwismart.a(dhcp.o) + .text.dhcp_delete_msg + 0x0801d420 0x30 ../..//econais/build/libwismart.a(dhcp.o) + .text.dhcp_rebind + 0x0801d450 0xd0 ../..//econais/build/libwismart.a(dhcp.o) + .text.dhcp_reboot + 0x0801d520 0xf0 ../..//econais/build/libwismart.a(dhcp.o) + .text.dhcp_select + 0x0801d610 0x180 ../..//econais/build/libwismart.a(dhcp.o) + .text.dhcp_inform + 0x0801d790 0xe0 ../..//econais/build/libwismart.a(dhcp.o) + 0x0801d790 dhcp_inform + .text.dhcp_discover + 0x0801d870 0x120 ../..//econais/build/libwismart.a(dhcp.o) + 0x0801d870 dhcp_discover + .text.dhcp_network_changed + 0x0801d990 0x40 ../..//econais/build/libwismart.a(dhcp.o) + 0x0801d990 dhcp_network_changed + .text.dhcp_renew + 0x0801d9d0 0xd0 ../..//econais/build/libwismart.a(dhcp.o) + 0x0801d9d0 dhcp_renew + .text.dhcp_coarse_tmr + 0x0801daa0 0x60 ../..//econais/build/libwismart.a(dhcp.o) + 0x0801daa0 dhcp_coarse_tmr + .text.dhcp_release + 0x0801db00 0xc0 ../..//econais/build/libwismart.a(dhcp.o) + 0x0801db00 dhcp_release + .text.dhcp_fine_tmr + 0x0801dbc0 0xa0 ../..//econais/build/libwismart.a(dhcp.o) + 0x0801dbc0 dhcp_fine_tmr + .text.dhcp_stop + 0x0801dc60 0x50 ../..//econais/build/libwismart.a(dhcp.o) + 0x0801dc60 dhcp_stop + .text.dns_send + 0x0801dcb0 0x110 ../..//econais/build/libwismart.a(dns.o) + .text.dns_check_entry + 0x0801ddc0 0xb0 ../..//econais/build/libwismart.a(dns.o) + .text.dns_recv + 0x0801de70 0x1b0 ../..//econais/build/libwismart.a(dns.o) + .text.dns_init + 0x0801e020 0x70 ../..//econais/build/libwismart.a(dns.o) + 0x0801e020 dns_init + .text.dns_tmr 0x0801e090 0x30 ../..//econais/build/libwismart.a(dns.o) + 0x0801e090 dns_tmr + .text.lwip_init + 0x0801e0c0 0x30 ../..//econais/build/libwismart.a(init.o) + 0x0801e0c0 lwip_init + .text.memp_init + 0x0801e0f0 0xa0 ../..//econais/build/libwismart.a(memp.o) + 0x0801e0f0 memp_init + .text.memp_malloc + 0x0801e190 0x80 ../..//econais/build/libwismart.a(memp.o) + 0x0801e190 memp_malloc + .text.memp_free + 0x0801e210 0x40 ../..//econais/build/libwismart.a(memp.o) + 0x0801e210 memp_free + .text.memp_status + 0x0801e250 0x10 ../..//econais/build/libwismart.a(memp.o) + 0x0801e250 memp_status + .text.netif_init + 0x0801e260 0x10 ../..//econais/build/libwismart.a(netif.o) + 0x0801e260 netif_init + .text.netif_set_ipaddr + 0x0801e270 0x70 ../..//econais/build/libwismart.a(netif.o) + 0x0801e270 netif_set_ipaddr + .text.netif_set_addr + 0x0801e2e0 0x20 ../..//econais/build/libwismart.a(netif.o) + 0x0801e2e0 netif_set_addr + .text.netif_set_gw + 0x0801e300 0x10 ../..//econais/build/libwismart.a(netif.o) + 0x0801e300 netif_set_gw + .text.netif_set_netmask + 0x0801e310 0x10 ../..//econais/build/libwismart.a(netif.o) + 0x0801e310 netif_set_netmask + .text.netif_set_up + 0x0801e320 0x40 ../..//econais/build/libwismart.a(netif.o) + 0x0801e320 netif_set_up + .text.netif_set_down + 0x0801e360 0x20 ../..//econais/build/libwismart.a(netif.o) + 0x0801e360 netif_set_down + .text.netif_set_link_up + 0x0801e380 0x60 ../..//econais/build/libwismart.a(netif.o) + 0x0801e380 netif_set_link_up + .text.netif_set_link_down + 0x0801e3e0 0x20 ../..//econais/build/libwismart.a(netif.o) + 0x0801e3e0 netif_set_link_down + .text.pbuf_free_ooseq_callback + 0x0801e400 0x40 ../..//econais/build/libwismart.a(pbuf.o) + .text.pbuf_pool_is_empty + 0x0801e440 0x40 ../..//econais/build/libwismart.a(pbuf.o) + .text.pbuf_header + 0x0801e480 0x80 ../..//econais/build/libwismart.a(pbuf.o) + 0x0801e480 pbuf_header + .text.pbuf_free + 0x0801e500 0x60 ../..//econais/build/libwismart.a(pbuf.o) + 0x0801e500 pbuf_free + .text.pbuf_realloc + 0x0801e560 0x40 ../..//econais/build/libwismart.a(pbuf.o) + 0x0801e560 pbuf_realloc + .text.pbuf_alloc + 0x0801e5a0 0x150 ../..//econais/build/libwismart.a(pbuf.o) + 0x0801e5a0 pbuf_alloc + .text.pbuf_clen + 0x0801e6f0 0x20 ../..//econais/build/libwismart.a(pbuf.o) + 0x0801e6f0 pbuf_clen + .text.pbuf_ref + 0x0801e710 0x20 ../..//econais/build/libwismart.a(pbuf.o) + 0x0801e710 pbuf_ref + .text.pbuf_cat + 0x0801e730 0x50 ../..//econais/build/libwismart.a(pbuf.o) + 0x0801e730 pbuf_cat + .text.pbuf_chain + 0x0801e780 0x20 ../..//econais/build/libwismart.a(pbuf.o) + 0x0801e780 pbuf_chain + .text.pbuf_copy + 0x0801e7a0 0xf0 ../..//econais/build/libwismart.a(pbuf.o) + 0x0801e7a0 pbuf_copy + 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0x0801ea90 0x350 ../..//econais/build/libwismart.a(tcp.o) + 0x0801ea90 tcp_slowtmr + .text.tcp_pcb_remove + 0x0801ede0 0x70 ../..//econais/build/libwismart.a(tcp.o) + 0x0801ede0 tcp_pcb_remove + .text.tcp_abandon + 0x0801ee50 0xa0 ../..//econais/build/libwismart.a(tcp.o) + 0x0801ee50 tcp_abandon + .text.tcp_abort + 0x0801eef0 0x10 ../..//econais/build/libwismart.a(tcp.o) + 0x0801eef0 tcp_abort + .text.tcp_close_shutdown + 0x0801ef00 0x170 ../..//econais/build/libwismart.a(tcp.o) + .text.tcp_close + 0x0801f070 0x20 ../..//econais/build/libwismart.a(tcp.o) + 0x0801f070 tcp_close + .text.tcp_recv_null + 0x0801f090 0x30 ../..//econais/build/libwismart.a(tcp.o) + 0x0801f090 tcp_recv_null + .text.tcp_process_refused_data + 0x0801f0c0 0x70 ../..//econais/build/libwismart.a(tcp.o) + 0x0801f0c0 tcp_process_refused_data + .text.tcp_fasttmr + 0x0801f130 0x70 ../..//econais/build/libwismart.a(tcp.o) + 0x0801f130 tcp_fasttmr + .text.tcp_tmr 0x0801f1a0 0x30 ../..//econais/build/libwismart.a(tcp.o) + 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.text.wpa_config_parse_auth_alg + 0x08021b50 0xe0 ../..//econais/build/libwismart.a(config.o) + .text.wpa_config_parse_key_mgmt + 0x08021c30 0x120 ../..//econais/build/libwismart.a(config.o) + .text.wpa_config_parse_proto + 0x08021d50 0xe0 ../..//econais/build/libwismart.a(config.o) + .text.wpa_config_parse_eap + 0x08021e30 0x140 ../..//econais/build/libwismart.a(config.o) + .text.wpa_config_parse_cipher.isra.1 + 0x08021f70 0x100 ../..//econais/build/libwismart.a(config.o) + .text.wpa_config_parse_group + 0x08022070 0x20 ../..//econais/build/libwismart.a(config.o) + .text.wpa_config_parse_pairwise + 0x08022090 0x20 ../..//econais/build/libwismart.a(config.o) + .text.wpa_config_parse_string + 0x080220b0 0x80 ../..//econais/build/libwismart.a(config.o) + .text.wpa_config_parse_str + 0x08022130 0x80 ../..//econais/build/libwismart.a(config.o) + .text.wpa_config_parse_wep_key.isra.3 + 0x080221b0 0x50 ../..//econais/build/libwismart.a(config.o) + .text.wpa_config_parse_wep_key3 + 0x08022200 0x10 ../..//econais/build/libwismart.a(config.o) + .text.wpa_config_parse_wep_key2 + 0x08022210 0x10 ../..//econais/build/libwismart.a(config.o) + .text.wpa_config_parse_wep_key1 + 0x08022220 0x10 ../..//econais/build/libwismart.a(config.o) + .text.wpa_config_parse_wep_key0 + 0x08022230 0x10 ../..//econais/build/libwismart.a(config.o) + .text.wpa_config_parse_password + 0x08022240 0xc0 ../..//econais/build/libwismart.a(config.o) + .text.wpa_config_parse_freqs.isra.5 + 0x08022300 0xa0 ../..//econais/build/libwismart.a(config.o) + .text.wpa_config_parse_freq_list + 0x080223a0 0x30 ../..//econais/build/libwismart.a(config.o) + .text.wpa_config_parse_scan_freq + 0x080223d0 0x30 ../..//econais/build/libwismart.a(config.o) + .text.wpa_config_parse_psk + 0x08022400 0xb0 ../..//econais/build/libwismart.a(config.o) + .text.wpa_config_parse_bssid + 0x080224b0 0x50 ../..//econais/build/libwismart.a(config.o) + .text.wpa_config_add_prio_network + 0x08022500 0xc0 ../..//econais/build/libwismart.a(config.o) + 0x08022500 wpa_config_add_prio_network + .text.wpa_config_update_prio_list + 0x080225c0 0x40 ../..//econais/build/libwismart.a(config.o) + 0x080225c0 wpa_config_update_prio_list + .text.wpa_config_free_ssid + 0x08022600 0x160 ../..//econais/build/libwismart.a(config.o) + 0x08022600 wpa_config_free_ssid + .text.wpa_config_add_network + 0x08022760 0x70 ../..//econais/build/libwismart.a(config.o) + 0x08022760 wpa_config_add_network + .text.wpa_config_remove_network + 0x080227d0 0x40 ../..//econais/build/libwismart.a(config.o) + 0x080227d0 wpa_config_remove_network + .text.wpa_config_set_network_defaults + 0x08022810 0x30 ../..//econais/build/libwismart.a(config.o) + 0x08022810 wpa_config_set_network_defaults + .text.wpa_config_set + 0x08022840 0x60 ../..//econais/build/libwismart.a(config.o) + 0x08022840 wpa_config_set + .text.eap_hdr_validate + 0x080228a0 0x90 ../..//econais/build/libwismart.a(eap_common.o) + 0x080228a0 eap_hdr_validate + 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../..//econais/build/libwismart.a(rtc.o) + 0x20004424 tmpCC4 + .bss.OperationComplete + 0x20004428 0x4 ../..//econais/build/libwismart.a(rtc.o) + .bss.LsiFreq 0x2000442c 0x4 ../..//econais/build/libwismart.a(rtc.o) + .bss.TransferEnd + 0x20004430 0x4 ../..//econais/build/libwismart.a(wifi_transport.o) + .bss.TransferError + 0x20004434 0x1 ../..//econais/build/libwismart.a(wifi_transport.o) + *fill* 0x20004435 0x3 + .bss.SDIO_CmdInitStructure + 0x20004438 0x14 ../..//econais/build/libwismart.a(wifi_transport.o) + .bss.GPIO_InitStructure + 0x2000444c 0x4 ../..//econais/build/libwismart.a(wifi_transport.o) + .bss.SDIO_DataInitStructure + 0x20004450 0x18 ../..//econais/build/libwismart.a(wifi_transport.o) + .bss.registryFileOpened + 0x20004468 0x20 ../..//econais/build/libwismart.a(registry_driver.o) + 0x20004468 registryFileOpened + .bss.registryFileMaxRegistryKeyAddressCount + 0x20004488 0x3c ../..//econais/build/libwismart.a(registry_driver.o) + 0x20004488 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c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-reent.o) + .debug_loc 0x0006d390 0x79 c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-s_fpclassify.o) + .debug_loc 0x0006d409 0x13bd c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfiprintf.o) + .debug_loc 0x0006e7c6 0xdd c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fclose.o) + +Cross Reference Table + +Symbol File +AHBPrescTable ../..//econais/build/libwismart.a(system_stm32f10x.o) +ARPTimer ../..//econais/build/libwismart.a(netconf.o) +AVTransport_service ../..//econais/build/libwismart.a(upnp_avTransport.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_serviceOperations.o) + ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(upnp_mediaRenderer.o) +Adapter_Status ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(eloop_wifiengine.o) + ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_ps.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(libwismart_scan.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) + ../..//econais/build/libwismart.a(libwismart.o) +AddRoamEvent ../..//econais/build/libwismart.a(roam.o) + ../..//econais/build/libwismart.a(libwismart.o) +Alignment ../..//econais/build/libwismart.a(wifi_engine.o) +BKP_ClearFlag ../..//econais/build/libwismart.a(stm32f10x_bkp.o) +BKP_ClearITPendingBit ../..//econais/build/libwismart.a(stm32f10x_bkp.o) +BKP_DeInit ../..//econais/build/libwismart.a(stm32f10x_bkp.o) + ../..//econais/build/libwismart.a(rtc.o) +BKP_GetFlagStatus ../..//econais/build/libwismart.a(stm32f10x_bkp.o) +BKP_GetITStatus ../..//econais/build/libwismart.a(stm32f10x_bkp.o) +BKP_ITConfig ../..//econais/build/libwismart.a(stm32f10x_bkp.o) +BKP_RTCOutputConfig ../..//econais/build/libwismart.a(stm32f10x_bkp.o) +BKP_ReadBackupRegister ../..//econais/build/libwismart.a(stm32f10x_bkp.o) +BKP_SetRTCCalibrationValue ../..//econais/build/libwismart.a(stm32f10x_bkp.o) +BKP_TamperPinCmd ../..//econais/build/libwismart.a(stm32f10x_bkp.o) +BKP_TamperPinLevelConfig ../..//econais/build/libwismart.a(stm32f10x_bkp.o) +BKP_WriteBackupRegister ../..//econais/build/libwismart.a(stm32f10x_bkp.o) +BusFaultVector build/obj/main.o + build/obj/vectors.o +CheckRoamEvent ../..//econais/build/libwismart.a(roam.o) + ../..//econais/build/libwismart.a(libwismart.o) +CheckRoamThresholds ../..//econais/build/libwismart.a(libwismart.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) +CmdCnt ../..//econais/build/libwismart.a(wifi_engine.o) +ConnectionMngr_service ../..//econais/build/libwismart.a(upnp_connectionManager.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_serviceOperations.o) + ../..//econais/build/libwismart.a(upnp_mediaRenderer.o) +CreateAdHoc ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +CreateBssLeaveRequest ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +CurTrack ../..//econais/build/libwismart.a(upnp_avTransport.o) +CurrentURI ../..//econais/build/libwismart.a(upnp_avTransport.o) +DBGMCU_Config ../..//econais/build/libwismart.a(stm32f10x_dbgmcu.o) + ../..//econais/build/libwismart.a(rcc.o) +DBGMCU_GetDEVID ../..//econais/build/libwismart.a(stm32f10x_dbgmcu.o) +DBGMCU_GetREVID ../..//econais/build/libwismart.a(stm32f10x_dbgmcu.o) +DHCPServer_Init ../..//econais/build/libwismart.a(dhcpserver.o) + ../..//econais/build/libwismart.a(netconf.o) +DHCP_Server_Connection ../..//econais/build/libwismart.a(dhcpserver.o) +DHCP_not_update ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) + ../..//econais/build/libwismart.a(libwismart.o) +DHCP_state ../..//econais/build/libwismart.a(netconf.o) +DHCPcoarseTimer ../..//econais/build/libwismart.a(netconf.o) +DHCPfineTimer ../..//econais/build/libwismart.a(netconf.o) +DMA_ClearFlag ../..//econais/build/libwismart.a(stm32f10x_dma.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +DMA_ClearITPendingBit ../..//econais/build/libwismart.a(stm32f10x_dma.o) + ../..//econais/build/libwismart.a(uart.o) +DMA_Cmd ../..//econais/build/libwismart.a(stm32f10x_dma.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) + ../..//econais/build/libwismart.a(uart.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +DMA_DeInit ../..//econais/build/libwismart.a(stm32f10x_dma.o) + ../..//econais/build/libwismart.a(uart.o) +DMA_GetCurrDataCounter ../..//econais/build/libwismart.a(stm32f10x_dma.o) + ../..//econais/build/libwismart.a(uart.o) +DMA_GetFlagStatus ../..//econais/build/libwismart.a(stm32f10x_dma.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +DMA_GetITStatus ../..//econais/build/libwismart.a(stm32f10x_dma.o) + ../..//econais/build/libwismart.a(uart.o) +DMA_ITConfig ../..//econais/build/libwismart.a(stm32f10x_dma.o) + ../..//econais/build/libwismart.a(uart.o) +DMA_Init ../..//econais/build/libwismart.a(stm32f10x_dma.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) + ../..//econais/build/libwismart.a(uart.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +DMA_SetCurrDataCounter ../..//econais/build/libwismart.a(stm32f10x_dma.o) +DMA_StructInit ../..//econais/build/libwismart.a(stm32f10x_dma.o) +DNSTimer ../..//econais/build/libwismart.a(netconf.o) +DataVar_ ../..//econais/build/libwismart.a(eeprom.o) +DebugMonitorVector build/obj/vectors.o +EE_Format_ ../..//econais/build/libwismart.a(eeprom.o) + ../..//econais/build/libwismart.a(registry_driver.o) +EE_Init_ ../..//econais/build/libwismart.a(eeprom.o) + ../..//econais/build/libwismart.a(registry_driver.o) +EE_ReadVariable_ ../..//econais/build/libwismart.a(eeprom.o) + ../..//econais/build/libwismart.a(registry_driver.o) +EE_WriteVariable_ ../..//econais/build/libwismart.a(eeprom.o) + ../..//econais/build/libwismart.a(registry_driver.o) +EE_getPageInfo_ ../..//econais/build/libwismart.a(eeprom.o) +EXTI_ClearFlag ../..//econais/build/libwismart.a(stm32f10x_exti.o) +EXTI_ClearITPendingBit ../..//econais/build/libwismart.a(stm32f10x_exti.o) + ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(rtc.o) + build/obj/buttonExample.o +EXTI_DeInit ../..//econais/build/libwismart.a(stm32f10x_exti.o) +EXTI_GenerateSWInterrupt ../..//econais/build/libwismart.a(stm32f10x_exti.o) +EXTI_GetFlagStatus ../..//econais/build/libwismart.a(stm32f10x_exti.o) +EXTI_GetITStatus ../..//econais/build/libwismart.a(stm32f10x_exti.o) + ../..//econais/build/libwismart.a(wifi_transport.o) + build/obj/buttonExample.o +EXTI_Init ../..//econais/build/libwismart.a(stm32f10x_exti.o) + ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(rtc.o) + build/obj/buttonExample.o +EXTI_StructInit ../..//econais/build/libwismart.a(stm32f10x_exti.o) +FLASH_BootConfig ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_ClearFlag ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_EnableWriteProtection ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_EraseAllBank1Pages ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_EraseAllBank2Pages ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_EraseAllPages ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_EraseOptionBytes ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_ErasePage ../..//econais/build/libwismart.a(stm32f10x_flash.o) + ../..//econais/build/libwismart.a(eeprom.o) +FLASH_GetBank1Status ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_GetBank2Status ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_GetFlagStatus ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_GetPrefetchBufferStatus ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_GetReadOutProtectionStatus ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_GetStatus ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_GetUserOptionByte ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_GetWriteProtectionOptionByte ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_HalfCycleAccessCmd ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_ITConfig ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_Lock ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_LockBank1 ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_LockBank2 ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_PrefetchBufferCmd ../..//econais/build/libwismart.a(stm32f10x_flash.o) + ../..//econais/build/libwismart.a(rcc.o) +FLASH_ProgramHalfWord ../..//econais/build/libwismart.a(stm32f10x_flash.o) + ../..//econais/build/libwismart.a(eeprom.o) +FLASH_ProgramOptionByteData ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_ProgramWord ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_ReadOutProtection ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_SetLatency ../..//econais/build/libwismart.a(stm32f10x_flash.o) + ../..//econais/build/libwismart.a(rcc.o) +FLASH_Unlock ../..//econais/build/libwismart.a(stm32f10x_flash.o) + ../..//econais/build/libwismart.a(registry_driver.o) +FLASH_UnlockBank1 ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_UnlockBank2 ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_UserOptionByteConfig ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_WaitForLastBank1Operation ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_WaitForLastBank2Operation ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FLASH_WaitForLastOperation ../..//econais/build/libwismart.a(stm32f10x_flash.o) +FindIE ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_engine.o) +FinishTargetSleep ../..//econais/build/libwismart.a(wifi_engine.o) +GPIO_AFIODeInit ../..//econais/build/libwismart.a(stm32f10x_gpio.o) +GPIO_DeInit ../..//econais/build/libwismart.a(stm32f10x_gpio.o) +GPIO_ETH_MediaInterfaceConfig ../..//econais/build/libwismart.a(stm32f10x_gpio.o) +GPIO_EXTILineConfig ../..//econais/build/libwismart.a(stm32f10x_gpio.o) + ../..//econais/build/libwismart.a(wifi_transport.o) + build/obj/buttonExample.o +GPIO_EventOutputCmd ../..//econais/build/libwismart.a(stm32f10x_gpio.o) +GPIO_EventOutputConfig ../..//econais/build/libwismart.a(stm32f10x_gpio.o) +GPIO_Init ../..//econais/build/libwismart.a(stm32f10x_gpio.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) + ../..//econais/build/libwismart.a(uart.o) + ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(gpio.o) + ../..//econais/build/libwismart.a(libwismart_power.o) + build/obj/buttonExample.o +GPIO_InitStructure ../..//econais/build/libwismart.a(gpio.o) +GPIO_PinLockConfig ../..//econais/build/libwismart.a(stm32f10x_gpio.o) +GPIO_PinRemapConfig ../..//econais/build/libwismart.a(stm32f10x_gpio.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) + ../..//econais/build/libwismart.a(gpio.o) + ../..//econais/build/libwismart.a(rtc.o) +GPIO_ReadInputData ../..//econais/build/libwismart.a(stm32f10x_gpio.o) +GPIO_ReadInputDataBit ../..//econais/build/libwismart.a(stm32f10x_gpio.o) +GPIO_ReadOutputData ../..//econais/build/libwismart.a(stm32f10x_gpio.o) +GPIO_ReadOutputDataBit ../..//econais/build/libwismart.a(stm32f10x_gpio.o) + ../..//econais/build/libwismart.a(gpio.o) +GPIO_ResetBits ../..//econais/build/libwismart.a(stm32f10x_gpio.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) + ../..//econais/build/libwismart.a(gpio.o) + ../..//econais/build/libwismart.a(libwismart.o) +GPIO_SetBits ../..//econais/build/libwismart.a(stm32f10x_gpio.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) + ../..//econais/build/libwismart.a(gpio.o) +GPIO_StructInit ../..//econais/build/libwismart.a(stm32f10x_gpio.o) +GPIO_Write ../..//econais/build/libwismart.a(stm32f10x_gpio.o) +GPIO_WriteBit ../..//econais/build/libwismart.a(stm32f10x_gpio.o) +GetBssid ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(driver_wifiengine.o) + ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) + ../..//econais/build/libwismart.a(libwismart.o) +HW_DebugTrace_DeInit ../..//econais/build/libwismart.a(uart.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) +HW_DebugTrace_IRQHandler ../..//econais/build/libwismart.a(uart.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) +HW_DebugTrace_Init ../..//econais/build/libwismart.a(uart.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) +HW_DebugTrace_RXDMA_IRQHandler ../..//econais/build/libwismart.a(uart.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) +HW_DebugTrace_RecvBuff ../..//econais/build/libwismart.a(uart.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) +HW_DebugTrace_SendBuff ../..//econais/build/libwismart.a(uart.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) +HW_DebugTrace_SendData ../..//econais/build/libwismart.a(uart.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) +HW_DebugTrace_StopRecvBuff ../..//econais/build/libwismart.a(uart.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) +HW_DebugTrace_TXDMA_IRQHandler ../..//econais/build/libwismart.a(uart.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) +HW_GPIOS_Init ../..//econais/build/libwismart.a(gpio.o) + ../..//econais/build/libwismart.a(libwismart.o) +HW_GPIOS_PinInit ../..//econais/build/libwismart.a(gpio.o) +HW_GPIOS_PinReset ../..//econais/build/libwismart.a(gpio.o) +HW_GPIOS_PinSet ../..//econais/build/libwismart.a(gpio.o) +HW_GPIOS_PinToggle ../..//econais/build/libwismart.a(gpio.o) +HW_GPIOS_Wifi_1_2v ../..//econais/build/libwismart.a(gpio.o) + ../..//econais/build/libwismart.a(libwismart.o) +HW_GPIOS_Wifi_3_3v ../..//econais/build/libwismart.a(gpio.o) + ../..//econais/build/libwismart.a(libwismart.o) +HW_Power_EnterMode ../..//econais/build/libwismart.a(power.o) + ../..//econais/build/libwismart.a(libwismart_power.o) +HW_RCC_Get ../..//econais/build/libwismart.a(rcc.o) +HW_RCC_Init ../..//econais/build/libwismart.a(rcc.o) + ../..//econais/build/libwismart.a(libwismart.o) +HW_RCC_InitStop ../..//econais/build/libwismart.a(rcc.o) + ../..//econais/build/libwismart.a(libwismart_power.o) +HW_RTC_GetTime ../..//econais/build/libwismart.a(rtc.o) + ../..//econais/build/libwismart.a(libwismart_power.o) +HW_RTC_Init ../..//econais/build/libwismart.a(rtc.o) + ../..//econais/build/libwismart.a(libwismart.o) +HW_RTC_SetAlarm_ms ../..//econais/build/libwismart.a(rtc.o) + ../..//econais/build/libwismart.a(libwismart_power.o) +HW_RTC_SetRTCForWakeup ../..//econais/build/libwismart.a(rtc.o) + ../..//econais/build/libwismart.a(libwismart_power.o) +HW_RTC_Shutdown ../..//econais/build/libwismart.a(rtc.o) + ../..//econais/build/libwismart.a(libwismart_power.o) +HW_SDIO_Write_Direct ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(transport.o) +HW_WiFiTransport_Initialize ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(libwismart.o) +HW_WiFiTransport_Interrupt ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(libwismart.o) +HW_WiFiTransport_Port ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(libwismart.o) +HW_WiFiTransport_ReadCMD53 ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(transport.o) +HW_WiFiTransport_SendCMD52 ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(transport.o) +HW_WiFiTransport_SendCMD53 ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(transport.o) +HW_WiFiTransport_Send_pbuf ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(transport.o) +HW_WiFiTrasport_ProcessSDIRQ ../..//econais/build/libwismart.a(wifi_transport.o) +HardFaultVector build/obj/main.o + build/obj/vectors.o +I2S_Cmd ../..//econais/build/libwismart.a(stm32f10x_spi.o) +I2S_Init ../..//econais/build/libwismart.a(stm32f10x_spi.o) +I2S_StructInit ../..//econais/build/libwismart.a(stm32f10x_spi.o) +IGMPTimer ../..//econais/build/libwismart.a(netconf.o) +IPTimer ../..//econais/build/libwismart.a(netconf.o) +IPaddress ../..//econais/build/libwismart.a(netconf.o) +Join ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +Joining_HT_AP ../..//econais/build/libwismart.a(wifi_engine.o) +LwIP_DHCP_Init ../..//econais/build/libwismart.a(netconf.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +LwIP_DHCP_Process_Handle ../..//econais/build/libwismart.a(netconf.o) +LwIP_DHCP_Start ../..//econais/build/libwismart.a(netconf.o) + ../..//econais/build/libwismart.a(libwismart.o) +LwIP_DHCP_Stop ../..//econais/build/libwismart.a(netconf.o) + ../..//econais/build/libwismart.a(libwismart.o) +LwIP_DeInit ../..//econais/build/libwismart.a(netconf.o) + ../..//econais/build/libwismart.a(libwismart.o) +LwIP_FrameReceivedEvent ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(transport.o) +LwIP_GetStaticIP ../..//econais/build/libwismart.a(netconf.o) + ../..//econais/build/libwismart.a(libwismart.o) +LwIP_Init ../..//econais/build/libwismart.a(netconf.o) + ../..//econais/build/libwismart.a(libwismart.o) +LwIP_PeriodicEventStart ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(libwismart_softap.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +LwIP_PeriodicEventStop ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(libwismart_softap.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) + ../..//econais/build/libwismart.a(libwismart.o) +LwIP_Periodic_Handle ../..//econais/build/libwismart.a(netconf.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) +LwIP_Pkt_Handle ../..//econais/build/libwismart.a(netconf.o) +LwIP_SetStaticIP ../..//econais/build/libwismart.a(netconf.o) + ../..//econais/build/libwismart.a(libwismart.o) +LwIP_StartDHCPServer ../..//econais/build/libwismart.a(netconf.o) + ../..//econais/build/libwismart.a(libwismart_softap.o) +MacAddress ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(ethernetif.o) + ../..//econais/build/libwismart.a(driver_wifiengine.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(libwismart.o) +MemManageVector build/obj/main.o + build/obj/vectors.o +NMIVector build/obj/main.o + build/obj/vectors.o +NRX_MD5Final ../..//econais/build/libwismart.a(md5-internal.o) + ../..//econais/build/libwismart.a(crypto_internal.o) +NRX_MD5Init ../..//econais/build/libwismart.a(md5-internal.o) + ../..//econais/build/libwismart.a(crypto_internal.o) +NRX_MD5Update ../..//econais/build/libwismart.a(md5-internal.o) + ../..//econais/build/libwismart.a(crypto_internal.o) +NRX_des_encrypt ../..//econais/build/libwismart.a(des-internal.o) + ../..//econais/build/libwismart.a(ms_funcs.o) +NVIC_Init ../..//econais/build/libwismart.a(misc.o) + ../..//econais/build/libwismart.a(uart.o) + ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(rtc.o) + build/obj/buttonExample.o +NVIC_InitStructure ../..//econais/build/libwismart.a(uart.o) +NVIC_PriorityGroupConfig ../..//econais/build/libwismart.a(misc.o) +NVIC_SetVectorTable ../..//econais/build/libwismart.a(misc.o) +NVIC_SystemLPConfig ../..//econais/build/libwismart.a(misc.o) +NataliaEngine_AddKey ../..//econais/build/libwismart.a(driver_wifiengine.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +NataliaEngine_AddKey_Client ../..//econais/build/libwismart.a(driver_wifiengine.o) +NataliaEngine_AddKey_SoftAP ../..//econais/build/libwismart.a(driver_wifiengine.o) +NataliaEngine_DeleteAllKey ../..//econais/build/libwismart.a(driver_wifiengine.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +NataliaEngine_DeleteKey ../..//econais/build/libwismart.a(driver_wifiengine.o) +NataliaEngine_SetProtectionReq ../..//econais/build/libwismart.a(driver_wifiengine.o) +NataliaEngine_setKey ../..//econais/build/libwismart.a(driver_wifiengine.o) +NumberOfTracks ../..//econais/build/libwismart.a(upnp_avTransport.o) +PBufQueue_Send_sem ../..//econais/build/libwismart.a(wifi_data_queue.o) + ../..//econais/build/libwismart.a(libwismart_softap.o) +PWR_BackupAccessCmd ../..//econais/build/libwismart.a(stm32f10x_pwr.o) + ../..//econais/build/libwismart.a(rtc.o) +PWR_ClearFlag ../..//econais/build/libwismart.a(stm32f10x_pwr.o) + ../..//econais/build/libwismart.a(power.o) + ../..//econais/build/libwismart.a(rtc.o) +PWR_DeInit ../..//econais/build/libwismart.a(stm32f10x_pwr.o) + ../..//econais/build/libwismart.a(rtc.o) +PWR_EnterSTANDBYMode ../..//econais/build/libwismart.a(stm32f10x_pwr.o) + ../..//econais/build/libwismart.a(power.o) +PWR_EnterSTOPMode ../..//econais/build/libwismart.a(stm32f10x_pwr.o) + ../..//econais/build/libwismart.a(power.o) +PWR_GetFlagStatus ../..//econais/build/libwismart.a(stm32f10x_pwr.o) + ../..//econais/build/libwismart.a(rtc.o) +PWR_PVDCmd ../..//econais/build/libwismart.a(stm32f10x_pwr.o) + ../..//econais/build/libwismart.a(power.o) + ../..//econais/build/libwismart.a(rtc.o) +PWR_PVDLevelConfig ../..//econais/build/libwismart.a(stm32f10x_pwr.o) +PWR_WakeUpPinCmd ../..//econais/build/libwismart.a(stm32f10x_pwr.o) + ../..//econais/build/libwismart.a(rtc.o) +PendSVVector build/obj/chcore_v7m.o + build/obj/vectors.o +PerformRoam ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(roam.o) +Previous_Adapter_Status ../..//econais/build/libwismart.a(wifi_engine.o) +RCC_ADCCLKConfig ../..//econais/build/libwismart.a(stm32f10x_rcc.o) +RCC_AHBPeriphClockCmd ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) + ../..//econais/build/libwismart.a(uart.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +RCC_APB1PeriphClockCmd ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) + ../..//econais/build/libwismart.a(uart.o) + ../..//econais/build/libwismart.a(rtc.o) +RCC_APB1PeriphResetCmd ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(stm32f10x_spi.o) + ../..//econais/build/libwismart.a(stm32f10x_usart.o) + ../..//econais/build/libwismart.a(stm32f10x_tim.o) + ../..//econais/build/libwismart.a(stm32f10x_pwr.o) +RCC_APB2PeriphClockCmd ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) + ../..//econais/build/libwismart.a(uart.o) + ../..//econais/build/libwismart.a(rcc.o) + ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(gpio.o) + build/obj/buttonExample.o +RCC_APB2PeriphResetCmd ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(stm32f10x_spi.o) + ../..//econais/build/libwismart.a(stm32f10x_usart.o) + ../..//econais/build/libwismart.a(stm32f10x_tim.o) + ../..//econais/build/libwismart.a(stm32f10x_gpio.o) +RCC_AdjustHSICalibrationValue ../..//econais/build/libwismart.a(stm32f10x_rcc.o) +RCC_BackupResetCmd ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(stm32f10x_bkp.o) + ../..//econais/build/libwismart.a(rtc.o) +RCC_ClearFlag ../..//econais/build/libwismart.a(stm32f10x_rcc.o) +RCC_ClearITPendingBit ../..//econais/build/libwismart.a(stm32f10x_rcc.o) +RCC_ClockSecuritySystemCmd ../..//econais/build/libwismart.a(stm32f10x_rcc.o) +RCC_DeInit ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(rcc.o) +RCC_GetClocksFreq ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(stm32f10x_spi.o) + ../..//econais/build/libwismart.a(stm32f10x_usart.o) + ../..//econais/build/libwismart.a(rcc.o) + ../..//econais/build/libwismart.a(rtc.o) +RCC_GetFlagStatus ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(rcc.o) + ../..//econais/build/libwismart.a(rtc.o) + ../..//econais/build/libwismart.a(libwismart.o) +RCC_GetITStatus ../..//econais/build/libwismart.a(stm32f10x_rcc.o) +RCC_GetSYSCLKSource ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(rcc.o) +RCC_HCLKConfig ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(rcc.o) +RCC_HSEConfig ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(rcc.o) +RCC_HSICmd ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(rcc.o) +RCC_ITConfig ../..//econais/build/libwismart.a(stm32f10x_rcc.o) +RCC_LSEConfig ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(rcc.o) +RCC_LSICmd ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(rtc.o) +RCC_MCOConfig ../..//econais/build/libwismart.a(stm32f10x_rcc.o) +RCC_PCLK1Config ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(rcc.o) +RCC_PCLK2Config ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(rcc.o) +RCC_PLLCmd ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(rcc.o) +RCC_PLLConfig ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(rcc.o) +RCC_RTCCLKCmd ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(rtc.o) +RCC_RTCCLKConfig ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(rtc.o) +RCC_SYSCLKConfig ../..//econais/build/libwismart.a(stm32f10x_rcc.o) + ../..//econais/build/libwismart.a(rcc.o) +RCC_USBCLKConfig ../..//econais/build/libwismart.a(stm32f10x_rcc.o) +RCC_WaitForHSEStartUp ../..//econais/build/libwismart.a(stm32f10x_rcc.o) +RND_CTRL_actions ../..//econais/build/libwismart.a(upnp_renderingControl.o) +RTC_ClearFlag ../..//econais/build/libwismart.a(stm32f10x_rtc.o) + ../..//econais/build/libwismart.a(rtc.o) +RTC_ClearITPendingBit ../..//econais/build/libwismart.a(stm32f10x_rtc.o) + ../..//econais/build/libwismart.a(rtc.o) +RTC_EnterConfigMode ../..//econais/build/libwismart.a(stm32f10x_rtc.o) +RTC_ExitConfigMode ../..//econais/build/libwismart.a(stm32f10x_rtc.o) +RTC_GetCounter ../..//econais/build/libwismart.a(stm32f10x_rtc.o) + ../..//econais/build/libwismart.a(rtc.o) +RTC_GetDivider ../..//econais/build/libwismart.a(stm32f10x_rtc.o) +RTC_GetFlagStatus ../..//econais/build/libwismart.a(stm32f10x_rtc.o) + ../..//econais/build/libwismart.a(rtc.o) +RTC_GetITStatus ../..//econais/build/libwismart.a(stm32f10x_rtc.o) + ../..//econais/build/libwismart.a(rtc.o) +RTC_ITConfig ../..//econais/build/libwismart.a(stm32f10x_rtc.o) + ../..//econais/build/libwismart.a(rtc.o) +RTC_SetAlarm ../..//econais/build/libwismart.a(stm32f10x_rtc.o) + ../..//econais/build/libwismart.a(rtc.o) +RTC_SetCounter ../..//econais/build/libwismart.a(stm32f10x_rtc.o) +RTC_SetPrescaler ../..//econais/build/libwismart.a(stm32f10x_rtc.o) + ../..//econais/build/libwismart.a(rtc.o) +RTC_WKUP_IRQHandler ../..//econais/build/libwismart.a(rtc.o) +RTC_WaitForLastTask ../..//econais/build/libwismart.a(stm32f10x_rtc.o) + ../..//econais/build/libwismart.a(rtc.o) +RTC_WaitForSynchro ../..//econais/build/libwismart.a(stm32f10x_rtc.o) + ../..//econais/build/libwismart.a(rtc.o) +RXCmdQueue ../..//econais/build/libwismart.a(libwismart.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +RXDataQueueMulticast ../..//econais/build/libwismart.a(libwismart.o) + ../..//econais/build/libwismart.a(ethernetif.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(transport.o) +RXDataQueueUnicast ../..//econais/build/libwismart.a(libwismart.o) + ../..//econais/build/libwismart.a(ethernetif.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(transport.o) +ReadMibTableObject ../..//econais/build/libwismart.a(mibs.o) +RegisterMIBTable ../..//econais/build/libwismart.a(mibs.o) + ../..//econais/build/libwismart.a(wifi_engine.o) +RemoveRoamEvent ../..//econais/build/libwismart.a(roam.o) + ../..//econais/build/libwismart.a(libwismart.o) +RenderControl_service ../..//econais/build/libwismart.a(upnp_renderingControl.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_serviceOperations.o) + ../..//econais/build/libwismart.a(upnp_mediaRenderer.o) +ResetHandler build/obj/crt0.o + build/obj/vectors.o +RoamTimer ../..//econais/build/libwismart.a(libwismart_lwip.o) +SDIO_CEATAITCmd ../..//econais/build/libwismart.a(stm32f10x_sdio.o) +SDIO_ClearFlag ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +SDIO_ClearITPendingBit ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +SDIO_ClockCmd ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +SDIO_CmdStructInit ../..//econais/build/libwismart.a(stm32f10x_sdio.o) +SDIO_CommandCompletionCmd ../..//econais/build/libwismart.a(stm32f10x_sdio.o) +SDIO_DMACmd ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +SDIO_DataConfig ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +SDIO_DataStructInit ../..//econais/build/libwismart.a(stm32f10x_sdio.o) +SDIO_DeInit ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +SDIO_GetCommandResponse ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +SDIO_GetDataCounter ../..//econais/build/libwismart.a(stm32f10x_sdio.o) +SDIO_GetFIFOCount ../..//econais/build/libwismart.a(stm32f10x_sdio.o) +SDIO_GetFlagStatus ../..//econais/build/libwismart.a(stm32f10x_sdio.o) +SDIO_GetITStatus ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +SDIO_GetPowerState ../..//econais/build/libwismart.a(stm32f10x_sdio.o) +SDIO_GetResponse ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +SDIO_ITConfig ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +SDIO_Init ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +SDIO_ReadData ../..//econais/build/libwismart.a(stm32f10x_sdio.o) +SDIO_SendCEATACmd ../..//econais/build/libwismart.a(stm32f10x_sdio.o) +SDIO_SendCommand ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +SDIO_SendSDIOSuspendCmd ../..//econais/build/libwismart.a(stm32f10x_sdio.o) +SDIO_SetPowerState ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +SDIO_SetSDIOOperation ../..//econais/build/libwismart.a(stm32f10x_sdio.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +SDIO_SetSDIOReadWaitMode ../..//econais/build/libwismart.a(stm32f10x_sdio.o) +SDIO_StartSDIOReadWait ../..//econais/build/libwismart.a(stm32f10x_sdio.o) +SDIO_StopSDIOReadWait ../..//econais/build/libwismart.a(stm32f10x_sdio.o) +SDIO_StructInit ../..//econais/build/libwismart.a(stm32f10x_sdio.o) +SDIO_WriteData ../..//econais/build/libwismart.a(stm32f10x_sdio.o) +SD_DMAEndOfTransferStatus ../..//econais/build/libwismart.a(wifi_transport.o) +SD_LowLevel_DMA_RxConfig ../..//econais/build/libwismart.a(wifi_transport.o) +SD_LowLevel_DMA_TxConfig ../..//econais/build/libwismart.a(wifi_transport.o) +SHA1Final ../..//econais/build/libwismart.a(sha1-internal.o) + ../..//econais/build/libwismart.a(crypto_internal.o) +SHA1Init ../..//econais/build/libwismart.a(sha1-internal.o) + ../..//econais/build/libwismart.a(crypto_internal.o) +SHA1Transform ../..//econais/build/libwismart.a(sha1-internal.o) +SHA1Update ../..//econais/build/libwismart.a(sha1-internal.o) + ../..//econais/build/libwismart.a(crypto_internal.o) +SPI_BiDirectionalLineConfig ../..//econais/build/libwismart.a(stm32f10x_spi.o) +SPI_CalculateCRC ../..//econais/build/libwismart.a(stm32f10x_spi.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) +SPI_Cmd ../..//econais/build/libwismart.a(stm32f10x_spi.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) +SPI_DataSizeConfig ../..//econais/build/libwismart.a(stm32f10x_spi.o) +SPI_GetCRC ../..//econais/build/libwismart.a(stm32f10x_spi.o) +SPI_GetCRCPolynomial ../..//econais/build/libwismart.a(stm32f10x_spi.o) +SPI_I2S_ClearFlag ../..//econais/build/libwismart.a(stm32f10x_spi.o) +SPI_I2S_ClearITPendingBit ../..//econais/build/libwismart.a(stm32f10x_spi.o) +SPI_I2S_DMACmd ../..//econais/build/libwismart.a(stm32f10x_spi.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) +SPI_I2S_DeInit ../..//econais/build/libwismart.a(stm32f10x_spi.o) +SPI_I2S_GetFlagStatus ../..//econais/build/libwismart.a(stm32f10x_spi.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) +SPI_I2S_GetITStatus ../..//econais/build/libwismart.a(stm32f10x_spi.o) +SPI_I2S_ITConfig ../..//econais/build/libwismart.a(stm32f10x_spi.o) +SPI_I2S_ReceiveData ../..//econais/build/libwismart.a(stm32f10x_spi.o) +SPI_I2S_SendData ../..//econais/build/libwismart.a(stm32f10x_spi.o) +SPI_Init ../..//econais/build/libwismart.a(stm32f10x_spi.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) +SPI_NSSInternalSoftwareConfig ../..//econais/build/libwismart.a(stm32f10x_spi.o) +SPI_SSOutputCmd ../..//econais/build/libwismart.a(stm32f10x_spi.o) +SPI_StructInit ../..//econais/build/libwismart.a(stm32f10x_spi.o) +SPI_TransmitCRC ../..//econais/build/libwismart.a(stm32f10x_spi.o) +SPI_receive ../..//econais/build/libwismart.a(sdCardOverSpi.o) +SPI_transmit ../..//econais/build/libwismart.a(sdCardOverSpi.o) +SVCallVector build/obj/vectors.o +ScanConfigure ../..//econais/build/libwismart.a(wifi_engine.o) +SendAssocRequest ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +SendAuthRequest ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +SendConsoleRequest ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(libwismart.o) +SendDataPacket ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(ethernetif.o) + ../..//econais/build/libwismart.a(wifi_data_queue.o) + ../..//econais/build/libwismart.a(wifi_softap.o) +SendDeAuthRequest ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(driver_wifiengine.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +SendDisassocRequest ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +SendMgmtPkt ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(mibs.o) +SendRssiValueBack ../..//econais/build/libwismart.a(libwismart.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +SendSleepForEver ../..//econais/build/libwismart.a(wifi_engine.o) +SendSnrValueBack ../..//econais/build/libwismart.a(libwismart.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +SoftAPQueue_Handler_Thread ../..//econais/build/libwismart.a(wifi_softap.o) +SysTickVector build/obj/chcore_v7m.o + build/obj/vectors.o +SysTick_CLKSourceConfig ../..//econais/build/libwismart.a(misc.o) +SystemCoreClock ../..//econais/build/libwismart.a(system_stm32f10x.o) +SystemCoreClockUpdate ../..//econais/build/libwismart.a(system_stm32f10x.o) +SystemInit ../..//econais/build/libwismart.a(system_stm32f10x.o) + ../..//econais/build/libwismart.a(libwismart.o) +TCPTimer ../..//econais/build/libwismart.a(netconf.o) +TIM_ARRPreloadConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_BDTRConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_BDTRStructInit ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_CCPreloadControl ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_CCxCmd ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_CCxNCmd ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_ClearFlag ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_ClearITPendingBit ../..//econais/build/libwismart.a(stm32f10x_tim.o) + ../..//econais/build/libwismart.a(rtc.o) +TIM_ClearOC1Ref ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_ClearOC2Ref ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_ClearOC3Ref ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_ClearOC4Ref ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_Cmd ../..//econais/build/libwismart.a(stm32f10x_tim.o) + ../..//econais/build/libwismart.a(rtc.o) +TIM_CounterModeConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_CtrlPWMOutputs ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_DMACmd ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_DMAConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_DeInit ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_ETRClockMode1Config ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_ETRClockMode2Config ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_ETRConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_EncoderInterfaceConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_ForcedOC1Config ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_ForcedOC2Config ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_ForcedOC3Config ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_ForcedOC4Config ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_GenerateEvent ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_GetCapture1 ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_GetCapture2 ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_GetCapture3 ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_GetCapture4 ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_GetCounter ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_GetFlagStatus ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_GetITStatus ../..//econais/build/libwismart.a(stm32f10x_tim.o) + ../..//econais/build/libwismart.a(rtc.o) +TIM_GetPrescaler ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_ICInit ../..//econais/build/libwismart.a(stm32f10x_tim.o) + ../..//econais/build/libwismart.a(rtc.o) +TIM_ICStructInit ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_ITConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) + ../..//econais/build/libwismart.a(rtc.o) +TIM_ITRxExternalClockConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_InternalClockConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_OC1FastConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_OC1Init ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_OC1NPolarityConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_OC1PolarityConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_OC1PreloadConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_OC2FastConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_OC2Init ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_OC2NPolarityConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_OC2PolarityConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_OC2PreloadConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_OC3FastConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_OC3Init ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_OC3NPolarityConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_OC3PolarityConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_OC3PreloadConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_OC4FastConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_OC4Init ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_OC4PolarityConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_OC4PreloadConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_OCStructInit ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_PWMIConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_PrescalerConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_SelectCCDMA ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_SelectCOM ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_SelectHallSensor ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_SelectInputTrigger ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_SelectMasterSlaveMode ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_SelectOCxM ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_SelectOnePulseMode ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_SelectOutputTrigger ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_SelectSlaveMode ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_SetAutoreload ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_SetClockDivision ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_SetCompare1 ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_SetCompare2 ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_SetCompare3 ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_SetCompare4 ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_SetCounter ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_SetIC1Prescaler ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_SetIC2Prescaler ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_SetIC3Prescaler ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_SetIC4Prescaler ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_TIxExternalClockConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_TimeBaseInit ../..//econais/build/libwismart.a(stm32f10x_tim.o) + ../..//econais/build/libwismart.a(rtc.o) +TIM_TimeBaseStructInit ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_UpdateDisableConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +TIM_UpdateRequestConfig ../..//econais/build/libwismart.a(stm32f10x_tim.o) +Td0 ../..//econais/build/libwismart.a(aes-internal.o) + ../..//econais/build/libwismart.a(aes-internal-dec.o) +Td4s ../..//econais/build/libwismart.a(aes-internal.o) + ../..//econais/build/libwismart.a(aes-internal-dec.o) +Te0 ../..//econais/build/libwismart.a(aes-internal.o) + ../..//econais/build/libwismart.a(aes-internal-enc.o) + ../..//econais/build/libwismart.a(aes-internal-dec.o) +TimerEventHandlerSignal ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(timer_events.o) +TransportState ../..//econais/build/libwismart.a(upnp_avTransport.o) +Transport_AckIRQ ../..//econais/build/libwismart.a(transport.o) +Transport_DownloadFW ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(libwismart.o) +Transport_IRQHandler ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +Transport_Init ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(libwismart.o) +Transport_Lock ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +Transport_ReadData ../..//econais/build/libwismart.a(transport.o) +Transport_SendData ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(driver_wifiengine.o) +Transport_SendData_pbuf ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(wifi_engine.o) +Transport_TargetSleep ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(wifi_ps.o) +Transport_TargetWakeup ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(wifi_ps.o) +Transport_Unlock ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +USART_ClearFlag ../..//econais/build/libwismart.a(stm32f10x_usart.o) +USART_ClearITPendingBit ../..//econais/build/libwismart.a(stm32f10x_usart.o) +USART_ClockInit ../..//econais/build/libwismart.a(stm32f10x_usart.o) +USART_ClockStructInit ../..//econais/build/libwismart.a(stm32f10x_usart.o) +USART_Cmd ../..//econais/build/libwismart.a(stm32f10x_usart.o) + ../..//econais/build/libwismart.a(uart.o) +USART_DMACmd ../..//econais/build/libwismart.a(stm32f10x_usart.o) + ../..//econais/build/libwismart.a(uart.o) +USART_DeInit ../..//econais/build/libwismart.a(stm32f10x_usart.o) + ../..//econais/build/libwismart.a(uart.o) +USART_GetFlagStatus ../..//econais/build/libwismart.a(stm32f10x_usart.o) + ../..//econais/build/libwismart.a(uart.o) +USART_GetITStatus ../..//econais/build/libwismart.a(stm32f10x_usart.o) +USART_HalfDuplexCmd ../..//econais/build/libwismart.a(stm32f10x_usart.o) +USART_ITConfig ../..//econais/build/libwismart.a(stm32f10x_usart.o) + ../..//econais/build/libwismart.a(uart.o) +USART_Init ../..//econais/build/libwismart.a(stm32f10x_usart.o) + ../..//econais/build/libwismart.a(uart.o) +USART_IrDACmd ../..//econais/build/libwismart.a(stm32f10x_usart.o) +USART_IrDAConfig ../..//econais/build/libwismart.a(stm32f10x_usart.o) +USART_LINBreakDetectLengthConfig ../..//econais/build/libwismart.a(stm32f10x_usart.o) +USART_LINCmd ../..//econais/build/libwismart.a(stm32f10x_usart.o) +USART_OneBitMethodCmd ../..//econais/build/libwismart.a(stm32f10x_usart.o) +USART_OverSampling8Cmd ../..//econais/build/libwismart.a(stm32f10x_usart.o) + ../..//econais/build/libwismart.a(uart.o) +USART_ReceiveData ../..//econais/build/libwismart.a(stm32f10x_usart.o) +USART_ReceiverWakeUpCmd ../..//econais/build/libwismart.a(stm32f10x_usart.o) +USART_SendBreak ../..//econais/build/libwismart.a(stm32f10x_usart.o) +USART_SendData ../..//econais/build/libwismart.a(stm32f10x_usart.o) + ../..//econais/build/libwismart.a(uart.o) +USART_SetAddress ../..//econais/build/libwismart.a(stm32f10x_usart.o) +USART_SetGuardTime ../..//econais/build/libwismart.a(stm32f10x_usart.o) +USART_SetPrescaler ../..//econais/build/libwismart.a(stm32f10x_usart.o) +USART_SmartCardCmd ../..//econais/build/libwismart.a(stm32f10x_usart.o) +USART_SmartCardNACKCmd ../..//econais/build/libwismart.a(stm32f10x_usart.o) +USART_StructInit ../..//econais/build/libwismart.a(stm32f10x_usart.o) +USART_WakeUpConfig ../..//econais/build/libwismart.a(stm32f10x_usart.o) +UsageFaultVector build/obj/main.o + build/obj/vectors.o +Vector100 build/obj/vectors.o +Vector104 ../..//econais/build/libwismart.a(wifi_transport.o) + build/obj/vectors.o +Vector108 ../..//econais/build/libwismart.a(rtc.o) + build/obj/vectors.o +Vector10C build/obj/vectors.o +Vector110 build/obj/vectors.o +Vector114 build/obj/vectors.o +Vector118 build/obj/vectors.o +Vector11C build/obj/vectors.o +Vector120 build/obj/vectors.o +Vector124 build/obj/vectors.o +Vector128 build/obj/vectors.o +Vector12C build/obj/vectors.o +Vector1C build/obj/vectors.o +Vector20 build/obj/vectors.o +Vector24 build/obj/vectors.o +Vector28 build/obj/vectors.o +Vector34 build/obj/vectors.o +Vector40 build/obj/vectors.o +Vector44 build/obj/vectors.o +Vector48 build/obj/vectors.o +Vector4C build/obj/vectors.o +Vector50 build/obj/vectors.o +Vector54 build/obj/vectors.o +Vector58 build/obj/main.o + build/obj/vectors.o +Vector5C build/obj/vectors.o +Vector60 build/obj/vectors.o +Vector64 build/obj/vectors.o +Vector68 build/obj/vectors.o +Vector6C build/obj/vectors.o +Vector70 build/obj/vectors.o +Vector74 build/obj/vectors.o +Vector78 build/obj/main.o + build/obj/vectors.o +Vector7C build/obj/main.o + build/obj/vectors.o +Vector80 build/obj/vectors.o +Vector84 build/obj/vectors.o +Vector88 build/obj/vectors.o +Vector8C build/obj/vectors.o +Vector90 build/obj/vectors.o +Vector94 build/obj/vectors.o +Vector98 build/obj/vectors.o +Vector9C build/obj/vectors.o +VectorA0 build/obj/vectors.o +VectorA4 build/obj/vectors.o +VectorA8 build/obj/vectors.o +VectorAC build/obj/vectors.o +VectorB0 build/obj/vectors.o +VectorB4 build/obj/vectors.o +VectorB8 build/obj/vectors.o +VectorBC build/obj/vectors.o +VectorC0 build/obj/vectors.o +VectorC4 build/obj/vectors.o +VectorC8 build/obj/vectors.o +VectorCC build/obj/vectors.o +VectorD0 build/obj/vectors.o +VectorD4 build/obj/main.o + build/obj/vectors.o +VectorD8 build/obj/vectors.o +VectorDC build/obj/vectors.o +VectorE0 build/obj/buttonExample.o + build/obj/vectors.o +VectorE4 ../..//econais/build/libwismart.a(rtc.o) + build/obj/vectors.o +VectorE8 build/obj/vectors.o +VectorEC build/obj/vectors.o +VectorF0 build/obj/vectors.o +VectorF4 build/obj/vectors.o +VectorF8 build/obj/vectors.o +VectorFC build/obj/vectors.o +WiFiEngine_RateCodeToBitposition ../..//econais/build/libwismart.a(wifi_engine.o) +WiFi_Client_Find ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(libwismart_softap.o) +WiFi_Client_Kill ../..//econais/build/libwismart.a(wifi_softap.o) +WiFi_Client_Touch ../..//econais/build/libwismart.a(wifi_softap.o) +WiFi_Client_Update_TIM ../..//econais/build/libwismart.a(wifi_softap.o) +WiFi_Flush_Clients_Packet_to_Air ../..//econais/build/libwismart.a(wifi_softap.o) +WiFi_GetMode ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(libwismart_softap.o) + ../..//econais/build/libwismart.a(ethernetif.o) + ../..//econais/build/libwismart.a(driver_wifiengine.o) + ../..//econais/build/libwismart.a(mibs.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(netconf.o) + ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(libwismart_scan.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) + ../..//econais/build/libwismart.a(libwismart.o) +WiFi_Init ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(libwismart.o) +WiFi_Init_rftest ../..//econais/build/libwismart.a(wifi_engine.o) +WiFi_Pop_and_Send_Clients_Packet ../..//econais/build/libwismart.a(wifi_softap.o) +WiFi_RXCmdQueue_Add ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(transport.o) +WiFi_RxQueues_Init ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(libwismart.o) +WiFi_RxQueues_Init_RfTest ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(libwismart.o) +WiFi_SetMode ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(libwismart_softap.o) + ../..//econais/build/libwismart.a(libwismart_scan.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +WiFi_SoftAP_HandlePacket ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(ethernetif.o) +WiFi_SoftAP_MBDeInit ../..//econais/build/libwismart.a(wifi_softap.o) +WiFi_SoftAP_MBInit ../..//econais/build/libwismart.a(wifi_softap.o) +WiFi_SoftAP_MBPost ../..//econais/build/libwismart.a(wifi_softap.o) +WiFi_SoftAP_MBTrypost ../..//econais/build/libwismart.a(wifi_softap.o) +WiFi_SoftAP_Start ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(driver_wifiengine.o) +WiFi_SoftAP_Stop ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(libwismart.o) +WiFi_Statistics ../..//econais/build/libwismart.a(libwismart.o) + ../..//econais/build/libwismart.a(transport.o) +WiFi_send_frame_req ../..//econais/build/libwismart.a(wifi_softap.o) +_Balloc c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-mprec.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-gdtoa-gethex.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strtod.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-dtoa.o) +_Bfree c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-mprec.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-gdtoa-gethex.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strtod.o) + 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c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-ungetc.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fflush.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-wsetup.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vfprintf.o) +__sinit_lock_acquire c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-findfp.o) +__sinit_lock_release c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-findfp.o) +__smakebuf_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-makebuf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-wsetup.o) +__sprint_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vfiprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vfprintf.o) +__sread c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-stdio.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-findfp.o) +__sseek c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-stdio.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-makebuf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-findfp.o) +__ssprint_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfiprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfprintf.o) +__ssrefill_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfiscanf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfscanf.o) +__ssvfiscanf_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfiscanf.o) +__ssvfscanf_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfscanf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-sscanf.o) +__subdf3 c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/thumb/v7m\libgcc.a(_arm_addsubdf3.o) +__submore c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-ungetc.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfiscanf.o) +__subsf3 c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/thumb/v7m\libgcc.a(_arm_addsubsf3.o) +__swbuf c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-wbuf.o) +__swbuf_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-wbuf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fputwc.o) +__swrite c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-stdio.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-findfp.o) +__swsetup_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-wsetup.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-wbuf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vfiprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fvwrite.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vfprintf.o) +__truncdfsf2 c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/thumb/v7m\libgcc.a(_arm_truncdfsf2.o) +__udivsi3 c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/thumb/v7m\libgcc.a(_udivsi3.o) +__ulp c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-mprec.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strtod.o) +__wctomb c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-wctomb_r.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-wcrtomb.o) +__wpa_send_eapol ../..//econais/build/libwismart.a(wpa_auth.o) +_atoi_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-atoi.o) +_bss_end build/obj/crt0.o +_bss_start build/obj/crt0.o +_calloc_r build/obj/syscalls.o + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-mprec.o) +_cleanup c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-findfp.o) +_cleanup_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-findfp.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-makebuf.o) +_close_r build/obj/syscalls.o + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-stdio.o) +_core_init build/obj/chmemcore.o + build/obj/chsys.o +_ctype_ c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-ctype_.o) +_data build/obj/crt0.o +_default_exit build/obj/crt0.o +_dtoa_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-dtoa.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vfprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfprintf.o) +_edata build/obj/crt0.o +_exit ../..//econais/build/libwismart.a(libwismart.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-abort.o) +_fclose_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fclose.o) +_fflush_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fflush.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-wbuf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fclose.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vfiprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-ungetc.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fvwrite.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vfprintf.o) +_fputwc_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fputwc.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vfiprintf.o) +_free_r build/obj/syscalls.o + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fclose.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfiscanf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfiprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-reent.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fvwrite.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fflush.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-wsetup.o) +_fstat_r build/obj/syscalls.o + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-makebuf.o) +_fwalk c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fwalk.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-findfp.o) +_fwalk_reent c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fwalk.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fflush.o) +_getpid ../..//econais/build/libwismart.a(libwismart.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-signalr.o) +_getpid_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-signalr.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-signal.o) +_global_impure_ptr c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-impure.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-findfp.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fflush.o) +_heap_init build/obj/chheap.o + build/obj/chsys.o +_impure_ptr c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-impure.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-wcrtomb.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-wbuf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fputwc.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fclose.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vfiprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-ungetc.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strtoul.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strtod.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-reent.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-mbrtowc.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-locale.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-findfp.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fflush.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-wsetup.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vsnprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vfprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strtol.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-sscanf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-sprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-snprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-signal.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-rand.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-puts.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-printf.o) +_init_signal c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-signal.o) +_init_signal_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-signal.o) +_isatty_r build/obj/syscalls.o + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-makebuf.o) +_kill ../..//econais/build/libwismart.a(libwismart.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-signalr.o) +_kill_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-signalr.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-signal.o) +_link ../..//econais/build/libwismart.a(libwismart.o) +_localeconv_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-locale.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-gdtoa-gethex.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strtod.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vfprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfprintf.o) +_lseek_r build/obj/syscalls.o + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-stdio.o) +_malloc_r build/obj/syscalls.o + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-ungetc.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfiprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-makebuf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fvwrite.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-findfp.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-signal.o) +_mbrtowc_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-mbrtowc.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfiscanf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfscanf.o) +_mbtowc_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-mbtowc_r.o) +_mprec_log10 c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-mprec.o) +_nrx_os_free ../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(pkcs5.o) + ../..//econais/build/libwismart.a(bignum.o) + ../..//econais/build/libwismart.a(rsa.o) + ../..//econais/build/libwismart.a(pkcs8.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(crypto_internal.o) + ../..//econais/build/libwismart.a(crypto_internal-cipher.o) + ../..//econais/build/libwismart.a(aes-internal-enc.o) + ../..//econais/build/libwismart.a(aes-internal-dec.o) + ../..//econais/build/libwismart.a(driver_common.o) + ../..//econais/build/libwismart.a(x509v3.o) + ../..//econais/build/libwismart.a(wps_dev_attr.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpabuf.o) + ../..//econais/build/libwismart.a(tlsv1_cred.o) + ../..//econais/build/libwismart.a(tlsv1_client_write.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(preauth.o) + ../..//econais/build/libwismart.a(pmksa_cache.o) + ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(l2_packet_none.o) + ../..//econais/build/libwismart.a(eloop_wifiengine.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_tls.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eap_methods.o) + ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(blacklist.o) + ../..//econais/build/libwismart.a(base64.o) + ../..//econais/build/libwismart.a(pmksa_cache_auth.o) + ../..//econais/build/libwismart.a(wpa_auth_ie.o) + ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(eap_server_methods.o) + ../..//econais/build/libwismart.a(eap_server.o) + ../..//econais/build/libwismart.a(beacon.o) + ../..//econais/build/libwismart.a(ieee802_11_auth.o) + ../..//econais/build/libwismart.a(eapol_auth_sm.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(sta_info.o) + ../..//econais/build/libwismart.a(ap_config.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) + ../..//econais/build/libwismart.a(hostapd.o) + ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(driver_wifiengine.o) + ../..//econais/build/libwismart.a(config_wifiengine.o) +_nrx_os_malloc ../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(pkcs5.o) + ../..//econais/build/libwismart.a(bignum.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(aes-internal-enc.o) + ../..//econais/build/libwismart.a(aes-internal-dec.o) + ../..//econais/build/libwismart.a(x509v3.o) + ../..//econais/build/libwismart.a(wps_dev_attr.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(tlsv1_cred.o) + ../..//econais/build/libwismart.a(tlsv1_client_write.o) + ../..//econais/build/libwismart.a(tlsv1_client_read.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(eloop_wifiengine.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_tls.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(base64.o) + ../..//econais/build/libwismart.a(pmksa_cache_auth.o) + ../..//econais/build/libwismart.a(wpa_auth_ie.o) + ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(eap_server.o) + ../..//econais/build/libwismart.a(eapol_auth_sm.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) + ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(driver_wifiengine.o) +_nrx_os_strdup ../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(x509v3.o) + ../..//econais/build/libwismart.a(wps_dev_attr.o) + ../..//econais/build/libwismart.a(eap_methods.o) + ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(eap_server.o) + ../..//econais/build/libwismart.a(eapol_auth_sm.o) + ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(main_wifiengine.o) + ../..//econais/build/libwismart.a(config_wifiengine.o) +_open ../..//econais/build/libwismart.a(libwismart.o) +_port_init build/obj/chcore_v7m.o + build/obj/chsys.o +_port_irq_epilogue build/obj/chcore_v7m.o + ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(rtc.o) + build/obj/buttonExample.o + build/obj/main.o +_port_switch build/obj/chcore_v7m.o + build/obj/chschd.o +_port_switch_from_isr build/obj/chcore_v7m.o +_port_thread_start build/obj/chcore_v7m.o + build/obj/chthreads.o +_printf_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-printf.o) +_puts_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-puts.o) +_raise_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-signal.o) +_read_r build/obj/syscalls.o + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-stdio.o) +_realloc_r build/obj/syscalls.o + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-ungetc.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfiprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fvwrite.o) +_reclaim_reent c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-reent.o) +_rename ../..//econais/build/libwismart.a(libwismart.o) +_sbrk_r build/obj/syscalls.o +_scheduler_init build/obj/chschd.o + build/obj/chsys.o +_setlocale_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-locale.o) +_sfread_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfiscanf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfscanf.o) +_signal_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-signal.o) +_snprintf_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-snprintf.o) +_sprintf_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-sprintf.o) +_sscanf_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-sscanf.o) +_strtod_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strtod.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfscanf.o) +_strtol_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strtol.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfiscanf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfscanf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-atoi.o) +_strtoul_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strtoul.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfiscanf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfscanf.o) +_sungetc_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfiscanf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfscanf.o) +_svfiprintf_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfiprintf.o) +_svfprintf_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vsnprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-sprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-snprintf.o) +_textdata build/obj/crt0.o +_thread_init build/obj/chthreads.o + build/obj/chsys.o +_ungetc_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-ungetc.o) +_unhandled_exception build/obj/vectors.o +_unlink ../..//econais/build/libwismart.a(libwismart.o) +_vectors build/obj/vectors.o +_vfiprintf_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vfiprintf.o) +_vfprintf_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vfprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-printf.o) +_vsnprintf_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vsnprintf.o) +_vt_init build/obj/chvt.o + build/obj/chsys.o +_wcrtomb_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-wcrtomb.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fputwc.o) +_wctomb_r c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-wctomb_r.o) +_wifi_send_mlme ../..//econais/build/libwismart.a(mibs.o) + ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_ps.o) + ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(wifi_softap.o) +_wifi_set_mib ../..//econais/build/libwismart.a(mibs.o) +_wifi_set_mib_raw ../..//econais/build/libwismart.a(mibs.o) + ../..//econais/build/libwismart.a(driver_wifiengine.o) + ../..//econais/build/libwismart.a(wifi_filter.o) + ../..//econais/build/libwismart.a(wifi_engine.o) +_wismart_hw ../..//econais/build/libwismart.a(libwismart.o) + ../..//econais/build/libwismart.a(uart.o) + ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(gpio.o) + ../..//econais/build/libwismart.a(rtc.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) +_wismart_idle_thread_wa ../..//econais/build/libwismart.a(libwismart_power.o) +_wrapup_reent c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-reent.o) +_write_r build/obj/syscalls.o + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-stdio.o) +abort c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-abort.o) + ../..//econais/build/libwismart.a(wpabuf.o) +absoluteCounterPosition ../..//econais/build/libwismart.a(upnp_avTransport.o) +absoluteTimePos ../..//econais/build/libwismart.a(upnp_avTransport.o) +activeServer ../..//econais/build/libwismart.a(hsCore.o) +aes_128_cbc_decrypt ../..//econais/build/libwismart.a(aes-cbc.o) + ../..//econais/build/libwismart.a(wps_common.o) +aes_128_cbc_encrypt ../..//econais/build/libwismart.a(aes-cbc.o) + ../..//econais/build/libwismart.a(wps_attr_build.o) +aes_decrypt ../..//econais/build/libwismart.a(aes-internal-dec.o) + ../..//econais/build/libwismart.a(crypto_internal-cipher.o) + ../..//econais/build/libwismart.a(aes-unwrap.o) + ../..//econais/build/libwismart.a(aes-cbc.o) +aes_decrypt_deinit ../..//econais/build/libwismart.a(aes-internal-dec.o) + ../..//econais/build/libwismart.a(crypto_internal-cipher.o) + ../..//econais/build/libwismart.a(aes-unwrap.o) + ../..//econais/build/libwismart.a(aes-cbc.o) +aes_decrypt_init ../..//econais/build/libwismart.a(aes-internal-dec.o) + ../..//econais/build/libwismart.a(crypto_internal-cipher.o) + ../..//econais/build/libwismart.a(aes-unwrap.o) + ../..//econais/build/libwismart.a(aes-cbc.o) +aes_encrypt ../..//econais/build/libwismart.a(aes-internal-enc.o) + ../..//econais/build/libwismart.a(crypto_internal-cipher.o) + ../..//econais/build/libwismart.a(aes-cbc.o) + ../..//econais/build/libwismart.a(aes-wrap.o) +aes_encrypt_deinit ../..//econais/build/libwismart.a(aes-internal-enc.o) + ../..//econais/build/libwismart.a(crypto_internal-cipher.o) + ../..//econais/build/libwismart.a(aes-cbc.o) + ../..//econais/build/libwismart.a(aes-wrap.o) +aes_encrypt_init ../..//econais/build/libwismart.a(aes-internal-enc.o) + ../..//econais/build/libwismart.a(crypto_internal-cipher.o) + ../..//econais/build/libwismart.a(aes-cbc.o) + ../..//econais/build/libwismart.a(aes-wrap.o) +aes_unwrap ../..//econais/build/libwismart.a(aes-unwrap.o) + ../..//econais/build/libwismart.a(wpa.o) +aes_wrap ../..//econais/build/libwismart.a(aes-wrap.o) + ../..//econais/build/libwismart.a(wpa_auth.o) +alignment_req_bsema ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +allocLimiter_init ../..//econais/build/libwismart.a(smem.o) +allow_stop_mode ../..//econais/build/libwismart.a(libwismart_power.o) +ap_client_poll_ok ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(events.o) +ap_for_each_sta ../..//econais/build/libwismart.a(sta_info.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(ap.o) +ap_free_sta ../..//econais/build/libwismart.a(sta_info.o) + ../..//econais/build/libwismart.a(drv_callbacks.o) +ap_get_sta ../..//econais/build/libwismart.a(sta_info.o) + ../..//econais/build/libwismart.a(drv_callbacks.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(tkip_countermeasures.o) + ../..//econais/build/libwismart.a(utils.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) +ap_handle_timer ../..//econais/build/libwismart.a(sta_info.o) +ap_mgmt_rx ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(events.o) +ap_mgmt_tx_cb ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(events.o) +ap_rx_from_unknown_sta ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(events.o) +ap_sta_add ../..//econais/build/libwismart.a(sta_info.o) + ../..//econais/build/libwismart.a(drv_callbacks.o) +ap_sta_bind_vlan ../..//econais/build/libwismart.a(sta_info.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +ap_sta_deauth_cb ../..//econais/build/libwismart.a(sta_info.o) +ap_sta_deauthenticate ../..//econais/build/libwismart.a(sta_info.o) + ../..//econais/build/libwismart.a(ap.o) +ap_sta_disassoc_cb ../..//econais/build/libwismart.a(sta_info.o) +ap_sta_disassociate ../..//econais/build/libwismart.a(sta_info.o) + ../..//econais/build/libwismart.a(drv_callbacks.o) + ../..//econais/build/libwismart.a(utils.o) +ap_sta_disconnect ../..//econais/build/libwismart.a(sta_info.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) +ap_sta_hash_add ../..//econais/build/libwismart.a(sta_info.o) +ap_sta_no_session_timeout ../..//econais/build/libwismart.a(sta_info.o) +ap_sta_session_timeout ../..//econais/build/libwismart.a(sta_info.o) +ap_sta_set_authorized ../..//econais/build/libwismart.a(sta_info.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(tkip_countermeasures.o) +ap_tx_status ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(events.o) +argument_list ../..//econais/build/libwismart.a(upnp_connectionManager.o) +arguments_getcurrentconnectionids ../..//econais/build/libwismart.a(upnp_connectionManager.o) +arguments_getprotocolinfo ../..//econais/build/libwismart.a(upnp_connectionManager.o) +arguments_setcurrentconnectioninfo ../..//econais/build/libwismart.a(upnp_connectionManager.o) +asn1_bit_string_to_long ../..//econais/build/libwismart.a(asn1.o) + ../..//econais/build/libwismart.a(x509v3.o) +asn1_get_next ../..//econais/build/libwismart.a(asn1.o) + ../..//econais/build/libwismart.a(pkcs5.o) + ../..//econais/build/libwismart.a(rsa.o) + ../..//econais/build/libwismart.a(pkcs8.o) + ../..//econais/build/libwismart.a(x509v3.o) + ../..//econais/build/libwismart.a(tlsv1_cred.o) +asn1_get_oid ../..//econais/build/libwismart.a(asn1.o) + ../..//econais/build/libwismart.a(pkcs5.o) + ../..//econais/build/libwismart.a(pkcs8.o) + ../..//econais/build/libwismart.a(x509v3.o) +asn1_oid_to_str ../..//econais/build/libwismart.a(asn1.o) + ../..//econais/build/libwismart.a(pkcs5.o) + ../..//econais/build/libwismart.a(pkcs8.o) + ../..//econais/build/libwismart.a(x509v3.o) +asn1_parse_oid ../..//econais/build/libwismart.a(asn1.o) + ../..//econais/build/libwismart.a(x509v3.o) +atoi c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-atoi.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(upnp_configurationServer.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + ../..//econais/build/libwismart.a(upnp_avTransport.o) + ../..//econais/build/libwismart.a(upnp_renderingControl.o) +auth_retries ../..//econais/build/libwismart.a(wpa.o) +authsrv_deinit ../..//econais/build/libwismart.a(authsrv.o) + ../..//econais/build/libwismart.a(hostapd.o) +authsrv_init ../..//econais/build/libwismart.a(authsrv.o) + ../..//econais/build/libwismart.a(hostapd.o) +avtUpdatePosInfo ../..//econais/build/libwismart.a(upnp_avTransport.o) + ../..//econais/build/libwismart.a(dlnaAppLinking.o) +avt_convertFromByte2time ../..//econais/build/libwismart.a(upnp_avTransport.o) +avt_convertFromTime2byte ../..//econais/build/libwismart.a(upnp_avTransport.o) +avt_convertTimeStr2Seconds ../..//econais/build/libwismart.a(upnp_avTransport.o) +avt_fixDuration ../..//econais/build/libwismart.a(upnp_avTransport.o) +avt_getResourceDuration ../..//econais/build/libwismart.a(upnp_avTransport.o) +base64_decode ../..//econais/build/libwismart.a(base64.o) + ../..//econais/build/libwismart.a(tlsv1_cred.o) + ../..//econais/build/libwismart.a(config_wifiengine.o) +base64_encode ../..//econais/build/libwismart.a(base64.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +bcast_queue ../..//econais/build/libwismart.a(wifi_softap.o) +bignum_add ../..//econais/build/libwismart.a(bignum.o) + ../..//econais/build/libwismart.a(rsa.o) +bignum_cmp ../..//econais/build/libwismart.a(bignum.o) + ../..//econais/build/libwismart.a(rsa.o) +bignum_cmp_d ../..//econais/build/libwismart.a(bignum.o) + ../..//econais/build/libwismart.a(rsa.o) + ../..//econais/build/libwismart.a(pkcs8.o) +bignum_deinit ../..//econais/build/libwismart.a(bignum.o) + ../..//econais/build/libwismart.a(rsa.o) + ../..//econais/build/libwismart.a(pkcs8.o) + ../..//econais/build/libwismart.a(crypto_internal-modexp.o) +bignum_exptmod ../..//econais/build/libwismart.a(bignum.o) + ../..//econais/build/libwismart.a(rsa.o) + ../..//econais/build/libwismart.a(crypto_internal-modexp.o) +bignum_get_unsigned_bin ../..//econais/build/libwismart.a(bignum.o) + ../..//econais/build/libwismart.a(rsa.o) + ../..//econais/build/libwismart.a(crypto_internal-modexp.o) +bignum_get_unsigned_bin_len ../..//econais/build/libwismart.a(bignum.o) + ../..//econais/build/libwismart.a(rsa.o) +bignum_init ../..//econais/build/libwismart.a(bignum.o) + ../..//econais/build/libwismart.a(rsa.o) + ../..//econais/build/libwismart.a(pkcs8.o) + ../..//econais/build/libwismart.a(crypto_internal-modexp.o) +bignum_mul ../..//econais/build/libwismart.a(bignum.o) + ../..//econais/build/libwismart.a(rsa.o) +bignum_mulmod ../..//econais/build/libwismart.a(bignum.o) + ../..//econais/build/libwismart.a(rsa.o) +bignum_set_unsigned_bin ../..//econais/build/libwismart.a(bignum.o) + ../..//econais/build/libwismart.a(rsa.o) + ../..//econais/build/libwismart.a(pkcs8.o) + ../..//econais/build/libwismart.a(crypto_internal-modexp.o) +bignum_sub ../..//econais/build/libwismart.a(bignum.o) + ../..//econais/build/libwismart.a(rsa.o) +bootloader_get_client_fw_info ../..//econais/build/libwismart.a(library_bootloader.o) + ../..//econais/build/libwismart.a(transport.o) +bootloader_get_rftest_fw_info ../..//econais/build/libwismart.a(library_bootloader.o) +bootloader_get_softap_fw_info ../..//econais/build/libwismart.a(library_bootloader.o) + ../..//econais/build/libwismart.a(transport.o) +browseInfoInUse ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +browseInfoPool ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +browseResponseUpper1 ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +browseResponseUpper2 ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +browseResponseUpper3 ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +browseResponseUpper4 ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +browseResponseUpper5 ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +browseResponseUpper6 ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +bssid_to_connect ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +buttons_init build/obj/buttonExample.o + build/obj/main.o +buttons_process build/obj/buttonExample.o + build/obj/main.o +callUserCb_getMute ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(upnp_renderingControl.o) +callUserCb_getVolume ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(upnp_renderingControl.o) +callUserCb_pause ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(upnp_avTransport.o) +callUserCb_play ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(upnp_avTransport.o) +callUserCb_seek ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(upnp_avTransport.o) +callUserCb_setMute ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(upnp_renderingControl.o) +callUserCb_setUri ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(upnp_avTransport.o) +callUserCb_setVolume ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(upnp_renderingControl.o) +callUserCb_stop ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(upnp_avTransport.o) +callbackServer ../..//econais/build/libwismart.a(hsCore.o) +cdAlloc ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdAllocBrowseInfoStruct ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdAllocFileDescriptor ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdAllocObjPathStrBuffer ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdBuildBrowseResultForContainer ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdBuildBrowseResultForItem ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdBuildBrowseResultLower ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdBuildBrowseResultMid ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdBuildBrowseResultUpper ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdDeallocBrowseInfoStruct ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdDeallocFileDescriptor ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdFileClose ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdFileFormats ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdFileOpen ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdFileRead ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdFileSeek ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdFileTell ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdFree ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdGetBrowseResponseLength ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdGetFileFormatPtr ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdHandleBrowseRequest ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + ../..//econais/build/libwismart.a(upnp_control.o) +cdHandleDmsFileRequest ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + ../..//econais/build/libwismart.a(upnp_description.o) +cdInit ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) +cdIsAudioExtension ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdMemMonitor ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdPlaybackFileClose ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + ../..//econais/build/libwismart.a(libwismart.o) +cdPlaybackFileDesc ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdPlaybackFileLock ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + ../..//econais/build/libwismart.a(libwismart.o) +cdPlaybackFileMtx ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdPlaybackFileOpen ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + ../..//econais/build/libwismart.a(libwismart.o) +cdPlaybackFileRead ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + ../..//econais/build/libwismart.a(libwismart.o) +cdPlaybackFileUnlock ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + ../..//econais/build/libwismart.a(libwismart.o) +cdProcessBrowseRequest ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdProcessDmsFileRequest ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdUriIsFile ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +cdXmlEscapeStr ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +chCondBroadcast build/obj/chcond.o +chCondBroadcastI build/obj/chcond.o +chCondInit build/obj/chcond.o +chCondSignal build/obj/chcond.o +chCondSignalI build/obj/chcond.o +chCondWait build/obj/chcond.o +chCondWaitS build/obj/chcond.o +chCondWaitTimeout build/obj/chcond.o +chCondWaitTimeoutS build/obj/chcond.o +chCoreAlloc build/obj/chmemcore.o + ../..//econais/build/libwismart.a(sys_arch.o) + build/obj/syscalls.o + build/obj/chheap.o +chCoreAllocI build/obj/chmemcore.o +chCoreStatus build/obj/chmemcore.o + ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(libwismart.o) +chEvtAddFlags build/obj/chevents.o +chEvtBroadcastFlags build/obj/chevents.o + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) +chEvtBroadcastFlagsI build/obj/chevents.o + ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(transport.o) + build/obj/evtimer.o +chEvtClearFlags build/obj/chevents.o + ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(transport.o) +chEvtDispatch build/obj/chevents.o +chEvtRegisterMask build/obj/chevents.o + ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(transport.o) +chEvtSignalFlags build/obj/chevents.o + ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) +chEvtSignalFlagsI build/obj/chevents.o +chEvtUnregister build/obj/chevents.o + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(transport.o) +chEvtWaitAll build/obj/chevents.o +chEvtWaitAllTimeout build/obj/chevents.o +chEvtWaitAny build/obj/chevents.o + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(transport.o) +chEvtWaitAnyTimeout build/obj/chevents.o + ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) +chEvtWaitOne build/obj/chevents.o +chEvtWaitOneTimeout build/obj/chevents.o +chHeapAlloc build/obj/chheap.o + ../..//econais/build/libwismart.a(smem.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(libwismart_pbuf_queues.o) + ../..//econais/build/libwismart.a(syscall.o) + ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(driver_wifiengine.o) + ../..//econais/build/libwismart.a(stm32_eeprom.o) + ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(link_list.o) + ../..//econais/build/libwismart.a(roam.o) + ../..//econais/build/libwismart.a(mibs.o) + ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_filter.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + build/obj/syscalls.o + build/obj/chdynamic.o +chHeapFree build/obj/chheap.o + ../..//econais/build/libwismart.a(smem.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(libwismart_pbuf_queues.o) + ../..//econais/build/libwismart.a(syscall.o) + ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(tcpip.o) + ../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(driver_wifiengine.o) + ../..//econais/build/libwismart.a(stm32_eeprom.o) + ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(link_list.o) + ../..//econais/build/libwismart.a(roam.o) + ../..//econais/build/libwismart.a(mibs.o) + ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_filter.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + build/obj/syscalls.o + build/obj/chdynamic.o +chHeapInit build/obj/chheap.o +chHeapMaxMinFraq build/obj/chheap.o + ../..//econais/build/libwismart.a(libwismart.o) +chHeapStatus build/obj/chheap.o + ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(libwismart.o) +chIQGetTimeout build/obj/chqueues.o +chIQInit build/obj/chqueues.o +chIQPutI build/obj/chqueues.o +chIQReadTimeout build/obj/chqueues.o +chIQResetI build/obj/chqueues.o +chMBFetch build/obj/chmboxes.o + ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) +chMBFetchI build/obj/chmboxes.o +chMBFetchS build/obj/chmboxes.o + ../..//econais/build/libwismart.a(sys_arch.o) +chMBInit build/obj/chmboxes.o + ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) +chMBPost build/obj/chmboxes.o + ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(wifi_softap.o) +chMBPostAhead build/obj/chmboxes.o +chMBPostAheadI build/obj/chmboxes.o +chMBPostAheadS build/obj/chmboxes.o +chMBPostI build/obj/chmboxes.o + ../..//econais/build/libwismart.a(libwismart_lwip.o) +chMBPostS build/obj/chmboxes.o +chMBReset build/obj/chmboxes.o + ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(wifi_softap.o) +chMsgRelease build/obj/chmsg.o +chMsgSend build/obj/chmsg.o +chMsgWait build/obj/chmsg.o +chMtxInit build/obj/chmtx.o + ../..//econais/build/libwismart.a(smem.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + build/obj/chheap.o +chMtxLock build/obj/chmtx.o + ../..//econais/build/libwismart.a(smem.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + build/obj/chheap.o +chMtxLockS build/obj/chmtx.o + build/obj/chcond.o +chMtxTryLock build/obj/chmtx.o +chMtxTryLockS build/obj/chmtx.o +chMtxUnlock build/obj/chmtx.o + ../..//econais/build/libwismart.a(smem.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + build/obj/chheap.o +chMtxUnlockAll build/obj/chmtx.o +chMtxUnlockS build/obj/chmtx.o + build/obj/chcond.o +chOQGetI build/obj/chqueues.o +chOQInit build/obj/chqueues.o +chOQPutTimeout build/obj/chqueues.o +chOQResetI build/obj/chqueues.o +chOQWriteTimeout build/obj/chqueues.o +chPoolAlloc build/obj/chmempools.o + build/obj/chdynamic.o +chPoolAllocI build/obj/chmempools.o +chPoolFree build/obj/chmempools.o + build/obj/chdynamic.o +chPoolFreeI build/obj/chmempools.o +chPoolInit build/obj/chmempools.o +chRegFirstThread build/obj/chregistry.o +chRegNextThread build/obj/chregistry.o +chSchDoReschedule build/obj/chschd.o + build/obj/chthreads.o + build/obj/chcore_v7m.o +chSchGoSleepS build/obj/chschd.o + build/obj/chmsg.o + build/obj/chevents.o + build/obj/chcond.o + build/obj/chmtx.o + build/obj/chsem.o + build/obj/chthreads.o +chSchGoSleepTimeoutS build/obj/chschd.o + build/obj/chqueues.o + build/obj/chevents.o + build/obj/chcond.o + build/obj/chsem.o + build/obj/chthreads.o +chSchReadyI build/obj/chschd.o + build/obj/chqueues.o + build/obj/chmsg.o + build/obj/chevents.o + build/obj/chcond.o + build/obj/chmtx.o + build/obj/chsem.o + build/obj/chthreads.o +chSchRescheduleS build/obj/chschd.o + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) + build/obj/chmboxes.o + build/obj/chevents.o + build/obj/chcond.o + build/obj/chmtx.o + build/obj/chsem.o + build/obj/chthreads.o +chSchWakeupS build/obj/chschd.o + build/obj/chmsg.o + build/obj/chcond.o + build/obj/chmtx.o + build/obj/chsem.o + build/obj/chdynamic.o + build/obj/chthreads.o +chSemAddCounterI build/obj/chsem.o +chSemInit build/obj/chsem.o + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(libwismart_pbuf_queues.o) + ../..//econais/build/libwismart.a(libwismart_softap.o) + ../..//econais/build/libwismart.a(syscall.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(link_list.o) + ../..//econais/build/libwismart.a(print.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_ps.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) + ../..//econais/build/libwismart.a(libwismart_power.o) + ../..//econais/build/libwismart.a(libwismart.o) + build/obj/chmboxes.o +chSemReset build/obj/chsem.o + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) +chSemResetI build/obj/chsem.o + ../..//econais/build/libwismart.a(libwismart_uart.o) + build/obj/chmboxes.o +chSemSignal build/obj/chsem.o + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(libwismart_pbuf_queues.o) + ../..//econais/build/libwismart.a(syscall.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(link_list.o) + ../..//econais/build/libwismart.a(print.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_data_queue.o) + ../..//econais/build/libwismart.a(wifi_ps.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(libwismart_power.o) + ../..//econais/build/libwismart.a(libwismart.o) +chSemSignalI build/obj/chsem.o + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) + build/obj/chmboxes.o +chSemSignalWait build/obj/chsem.o +chSemWait build/obj/chsem.o + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(libwismart_pbuf_queues.o) + ../..//econais/build/libwismart.a(syscall.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(link_list.o) + ../..//econais/build/libwismart.a(print.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_data_queue.o) + ../..//econais/build/libwismart.a(wifi_ps.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) + ../..//econais/build/libwismart.a(libwismart_power.o) + ../..//econais/build/libwismart.a(libwismart.o) +chSemWaitS build/obj/chsem.o +chSemWaitTimeout build/obj/chsem.o + ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) +chSemWaitTimeoutS build/obj/chsem.o + ../..//econais/build/libwismart.a(sys_arch.o) + build/obj/chmboxes.o +chSysInit build/obj/chsys.o + ../..//econais/build/libwismart.a(libwismart.o) +chSysTimerHandlerI build/obj/chsys.o + build/obj/chcore_v7m.o +chThdAddRef build/obj/chdynamic.o +chThdCreateFromHeap build/obj/chdynamic.o + ../..//econais/build/libwismart.a(ec_tools.o) + ../..//econais/build/libwismart.a(wifi_softap.o) +chThdCreateFromMemoryPool build/obj/chdynamic.o +chThdCreateI build/obj/chthreads.o + build/obj/chdynamic.o +chThdCreateStatic build/obj/chthreads.o + ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(libwismart_power.o) +chThdExit build/obj/chthreads.o + build/obj/chcore_v7m.o +chThdExitS build/obj/chthreads.o +chThdRelease build/obj/chdynamic.o + build/obj/chregistry.o + build/obj/chthreads.o +chThdResume build/obj/chthreads.o +chThdSetPriority build/obj/chthreads.o + ../..//econais/build/libwismart.a(libwismart_power.o) +chThdSleep build/obj/chthreads.o + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(wifi_ps.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) + ../..//econais/build/libwismart.a(libwismart.o) + build/obj/main.o +chThdSleepUntil build/obj/chthreads.o +chThdTerminate build/obj/chthreads.o + ../..//econais/build/libwismart.a(wifi_softap.o) +chThdWait build/obj/chthreads.o + ../..//econais/build/libwismart.a(ec_tools.o) + ../..//econais/build/libwismart.a(wifi_softap.o) +chThdYield build/obj/chthreads.o + ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) +chTimeIsWithin build/obj/chvt.o +chVTResetI build/obj/chvt.o + ../..//econais/build/libwismart.a(timer_events.o) + build/obj/evtimer.o + build/obj/chschd.o +chVTSetI build/obj/chvt.o + ../..//econais/build/libwismart.a(upnp_configurationServer.o) + ../..//econais/build/libwismart.a(timer_events.o) + build/obj/evtimer.o + build/obj/chschd.o +ch_debug build/obj/chregistry.o + build/obj/chsys.o +challenge_response ../..//econais/build/libwismart.a(ms_funcs.o) + ../..//econais/build/libwismart.a(eap_ttls.o) +channelStr ../..//econais/build/libwismart.a(upnp_configurationServer.o) +chap_md5 ../..//econais/build/libwismart.a(chap.o) + ../..//econais/build/libwismart.a(eap_md5.o) + ../..//econais/build/libwismart.a(eap_ttls.o) +checkId ../..//econais/build/libwismart.a(mibs.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +cipher_suite2driver ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(ap.o) +cleanup_glue c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-reent.o) +clear_scan_runs ../..//econais/build/libwismart.a(libwismart_scan.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +clust2sect ../..//econais/build/libwismart.a(ff.o) +configSPI ../..//econais/build/libwismart.a(sdCardOverSpi.o) +configSPI_gpios ../..//econais/build/libwismart.a(sdCardOverSpi.o) +configSPI_peripheral ../..//econais/build/libwismart.a(sdCardOverSpi.o) +config_eeprom_read_byte ../..//econais/build/libwismart.a(stm32_eeprom.o) +config_eeprom_read_str ../..//econais/build/libwismart.a(stm32_eeprom.o) +config_eeprom_write_str ../..//econais/build/libwismart.a(stm32_eeprom.o) +connected_bss ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_scan.o) +connmgr_actions ../..//econais/build/libwismart.a(upnp_connectionManager.o) +connmgr_values ../..//econais/build/libwismart.a(upnp_connectionManager.o) +connmgr_variables ../..//econais/build/libwismart.a(upnp_connectionManager.o) +crypto_cipher_decrypt ../..//econais/build/libwismart.a(crypto_internal-cipher.o) + ../..//econais/build/libwismart.a(pkcs5.o) + ../..//econais/build/libwismart.a(tlsv1_record.o) +crypto_cipher_deinit ../..//econais/build/libwismart.a(crypto_internal-cipher.o) + ../..//econais/build/libwismart.a(pkcs5.o) + ../..//econais/build/libwismart.a(tlsv1_record.o) +crypto_cipher_encrypt ../..//econais/build/libwismart.a(crypto_internal-cipher.o) + ../..//econais/build/libwismart.a(tlsv1_record.o) +crypto_cipher_init ../..//econais/build/libwismart.a(crypto_internal-cipher.o) + ../..//econais/build/libwismart.a(pkcs5.o) + ../..//econais/build/libwismart.a(tlsv1_record.o) +crypto_global_deinit ../..//econais/build/libwismart.a(crypto_internal.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) +crypto_global_init ../..//econais/build/libwismart.a(crypto_internal.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) +crypto_hash_finish ../..//econais/build/libwismart.a(crypto_internal.o) + ../..//econais/build/libwismart.a(tlsv1_record.o) + ../..//econais/build/libwismart.a(tlsv1_common.o) + ../..//econais/build/libwismart.a(tlsv1_client_write.o) + ../..//econais/build/libwismart.a(tlsv1_client_read.o) +crypto_hash_init ../..//econais/build/libwismart.a(crypto_internal.o) + ../..//econais/build/libwismart.a(tlsv1_record.o) + ../..//econais/build/libwismart.a(tlsv1_common.o) +crypto_hash_update ../..//econais/build/libwismart.a(crypto_internal.o) + ../..//econais/build/libwismart.a(tlsv1_record.o) + ../..//econais/build/libwismart.a(tlsv1_common.o) +crypto_mod_exp ../..//econais/build/libwismart.a(crypto_internal-modexp.o) + ../..//econais/build/libwismart.a(tlsv1_client_write.o) + ../..//econais/build/libwismart.a(dh_groups.o) +crypto_private_key_decrypt_pkcs1_v15 ../..//econais/build/libwismart.a(crypto_internal-rsa.o) +crypto_private_key_free ../..//econais/build/libwismart.a(crypto_internal-rsa.o) + ../..//econais/build/libwismart.a(tlsv1_cred.o) +crypto_private_key_import ../..//econais/build/libwismart.a(crypto_internal-rsa.o) + ../..//econais/build/libwismart.a(tlsv1_cred.o) +crypto_private_key_sign_pkcs1 ../..//econais/build/libwismart.a(crypto_internal-rsa.o) + ../..//econais/build/libwismart.a(tlsv1_client_write.o) +crypto_public_key_decrypt_pkcs1 ../..//econais/build/libwismart.a(crypto_internal-rsa.o) + ../..//econais/build/libwismart.a(x509v3.o) +crypto_public_key_encrypt_pkcs1_v15 ../..//econais/build/libwismart.a(crypto_internal-rsa.o) + ../..//econais/build/libwismart.a(tlsv1_client_write.o) +crypto_public_key_free ../..//econais/build/libwismart.a(crypto_internal-rsa.o) + ../..//econais/build/libwismart.a(x509v3.o) + ../..//econais/build/libwismart.a(tlsv1_client_read.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) +crypto_public_key_from_cert ../..//econais/build/libwismart.a(crypto_internal-rsa.o) + ../..//econais/build/libwismart.a(tlsv1_common.o) +crypto_public_key_import ../..//econais/build/libwismart.a(crypto_internal-rsa.o) + ../..//econais/build/libwismart.a(x509v3.o) + ../..//econais/build/libwismart.a(tlsv1_common.o) +crypto_rsa_exptmod ../..//econais/build/libwismart.a(rsa.o) + ../..//econais/build/libwismart.a(pkcs1.o) +crypto_rsa_free ../..//econais/build/libwismart.a(rsa.o) + ../..//econais/build/libwismart.a(crypto_internal-rsa.o) +crypto_rsa_get_modulus_len ../..//econais/build/libwismart.a(rsa.o) + ../..//econais/build/libwismart.a(pkcs1.o) +crypto_rsa_import_private_key ../..//econais/build/libwismart.a(rsa.o) + ../..//econais/build/libwismart.a(pkcs8.o) + ../..//econais/build/libwismart.a(crypto_internal-rsa.o) +crypto_rsa_import_public_key ../..//econais/build/libwismart.a(rsa.o) + ../..//econais/build/libwismart.a(crypto_internal-rsa.o) +currentMediaDuration ../..//econais/build/libwismart.a(upnp_avTransport.o) +currentTrackDuration ../..//econais/build/libwismart.a(upnp_avTransport.o) +currentTrackSize ../..//econais/build/libwismart.a(upnp_avTransport.o) +current_header ../..//econais/build/libwismart.a(ip.o) +current_iphdr_dest ../..//econais/build/libwismart.a(ip.o) + ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(raw.o) + ../..//econais/build/libwismart.a(icmp.o) + ../..//econais/build/libwismart.a(udp.o) +current_iphdr_src ../..//econais/build/libwismart.a(ip.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(raw.o) + ../..//econais/build/libwismart.a(icmp.o) + ../..//econais/build/libwismart.a(udp.o) +current_netif ../..//econais/build/libwismart.a(ip.o) +des3_decrypt ../..//econais/build/libwismart.a(des-internal.o) + ../..//econais/build/libwismart.a(crypto_internal-cipher.o) +des3_encrypt ../..//econais/build/libwismart.a(des-internal.o) + ../..//econais/build/libwismart.a(crypto_internal-cipher.o) +des3_key_setup ../..//econais/build/libwismart.a(des-internal.o) + ../..//econais/build/libwismart.a(crypto_internal-cipher.o) +des_block_decrypt ../..//econais/build/libwismart.a(des-internal.o) + ../..//econais/build/libwismart.a(crypto_internal-cipher.o) +des_block_encrypt ../..//econais/build/libwismart.a(des-internal.o) + ../..//econais/build/libwismart.a(crypto_internal-cipher.o) +des_key_setup ../..//econais/build/libwismart.a(des-internal.o) + ../..//econais/build/libwismart.a(crypto_internal-cipher.o) +dh5_derive_shared ../..//econais/build/libwismart.a(dh_group5.o) + ../..//econais/build/libwismart.a(wps_common.o) +dh5_free ../..//econais/build/libwismart.a(dh_group5.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps.o) +dh5_init ../..//econais/build/libwismart.a(dh_group5.o) + ../..//econais/build/libwismart.a(wps_attr_build.o) +dh_derive_shared ../..//econais/build/libwismart.a(dh_groups.o) + ../..//econais/build/libwismart.a(dh_group5.o) +dh_groups_get ../..//econais/build/libwismart.a(dh_groups.o) + ../..//econais/build/libwismart.a(dh_group5.o) +dh_init ../..//econais/build/libwismart.a(dh_groups.o) + ../..//econais/build/libwismart.a(dh_group5.o) +dhcp_arp_reply ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(etharp.o) +dhcp_cleanup ../..//econais/build/libwismart.a(dhcp.o) +dhcp_coarse_tmr ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(netconf.o) +dhcp_discover ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(netif.o) +dhcp_fine_tmr ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(netconf.o) +dhcp_inform ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(netconf.o) +dhcp_network_changed ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(netif.o) +dhcp_release ../..//econais/build/libwismart.a(dhcp.o) +dhcp_renew ../..//econais/build/libwismart.a(dhcp.o) +dhcp_result_cb ../..//econais/build/libwismart.a(libwismart.o) +dhcp_rx_options_given ../..//econais/build/libwismart.a(dhcp.o) +dhcp_rx_options_val ../..//econais/build/libwismart.a(dhcp.o) +dhcp_set_struct ../..//econais/build/libwismart.a(dhcp.o) +dhcp_start ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(netconf.o) +dhcp_stop ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(netconf.o) +diskInited ../..//econais/build/libwismart.a(diskio.o) +disk_initialize ../..//econais/build/libwismart.a(diskio.o) + ../..//econais/build/libwismart.a(ff.o) +disk_ioctl ../..//econais/build/libwismart.a(diskio.o) +disk_read ../..//econais/build/libwismart.a(diskio.o) + ../..//econais/build/libwismart.a(ff.o) +disk_status ../..//econais/build/libwismart.a(diskio.o) + ../..//econais/build/libwismart.a(ff.o) +disk_write ../..//econais/build/libwismart.a(diskio.o) +dlm_mib_table_rootentries ../..//econais/build/libwismart.a(mibs.o) +dlm_mib_table_rootindex ../..//econais/build/libwismart.a(mibs.o) +dlm_mib_table_size_client ../..//econais/build/libwismart.a(mibs.o) +dlm_mib_table_size_rftest ../..//econais/build/libwismart.a(mibs.o) +dlm_mib_table_size_softap ../..//econais/build/libwismart.a(mibs.o) +dlm_mib_table_vaddr ../..//econais/build/libwismart.a(mibs.o) +dlnaEnterConfigurationMode ../..//econais/build/libwismart.a(libwismart.o) +dlnaGetMuteCb ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(libwismart.o) +dlnaGetVolumeCb ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(libwismart.o) +dlnaPauseCb ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(libwismart.o) +dlnaPlayCb ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(libwismart.o) +dlnaPlaybackFinished ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(libwismart.o) +dlnaSeekCb ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(libwismart.o) +dlnaSetMuteCb ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(libwismart.o) +dlnaSetUriCb ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(libwismart.o) +dlnaSetVolumeCb ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(libwismart.o) +dlnaStopCb ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(libwismart.o) +dlnaUpdatePositionInfo ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(libwismart.o) +dlnaUserApplicationCbs ../..//econais/build/libwismart.a(dlnaAppLinking.o) +dlnaUserApplicationCbsInit ../..//econais/build/libwismart.a(dlnaAppLinking.o) +dms_cd_actions ../..//econais/build/libwismart.a(upnp_dmsContentDirectory.o) +dms_cd_service ../..//econais/build/libwismart.a(upnp_dmsContentDirectory.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_serviceOperations.o) + ../..//econais/build/libwismart.a(upnp_mediaServer.o) +dms_cm_actions ../..//econais/build/libwismart.a(upnp_dmsConnectionManager.o) +dms_cm_argument_list ../..//econais/build/libwismart.a(upnp_dmsConnectionManager.o) +dms_cm_arguments_connectioncomplete ../..//econais/build/libwismart.a(upnp_dmsConnectionManager.o) +dms_cm_arguments_getcurrentconnectionids ../..//econais/build/libwismart.a(upnp_dmsConnectionManager.o) +dms_cm_arguments_getprotocolinfo ../..//econais/build/libwismart.a(upnp_dmsConnectionManager.o) +dms_cm_arguments_prepareforconnection ../..//econais/build/libwismart.a(upnp_dmsConnectionManager.o) +dms_cm_arguments_setcurrentconnectioninfo ../..//econais/build/libwismart.a(upnp_dmsConnectionManager.o) +dms_cm_connection_complete ../..//econais/build/libwismart.a(upnp_dmsConnectionManager.o) +dms_cm_get_current_conn_ids ../..//econais/build/libwismart.a(upnp_dmsConnectionManager.o) +dms_cm_get_current_conn_info ../..//econais/build/libwismart.a(upnp_dmsConnectionManager.o) +dms_cm_get_protocol_info ../..//econais/build/libwismart.a(upnp_dmsConnectionManager.o) +dms_cm_prepare_for_connection ../..//econais/build/libwismart.a(upnp_dmsConnectionManager.o) +dms_cm_service ../..//econais/build/libwismart.a(upnp_dmsConnectionManager.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_serviceOperations.o) + ../..//econais/build/libwismart.a(upnp_mediaServer.o) +dms_cm_values ../..//econais/build/libwismart.a(upnp_dmsConnectionManager.o) +dms_cm_variables ../..//econais/build/libwismart.a(upnp_dmsConnectionManager.o) +dns_gethostbyname ../..//econais/build/libwismart.a(dns.o) + ../..//econais/build/libwismart.a(api_msg.o) +dns_getserver ../..//econais/build/libwismart.a(dns.o) +dns_init ../..//econais/build/libwismart.a(dns.o) + ../..//econais/build/libwismart.a(init.o) +dns_setserver ../..//econais/build/libwismart.a(dns.o) + ../..//econais/build/libwismart.a(dhcp.o) +dns_tmr ../..//econais/build/libwismart.a(dns.o) + ../..//econais/build/libwismart.a(netconf.o) +do_bind ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) +do_close ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) +do_connect ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) +do_delconn ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) +do_disconnect ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) +do_getaddr ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) +do_gethostbyname ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) +do_join_leave_group ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) +do_listen ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) +do_newconn ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) +do_recv ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) +do_send ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) +do_write ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) +eap_allowed_method ../..//econais/build/libwismart.a(eap.o) +eap_clear_config_otp ../..//econais/build/libwismart.a(eap.o) +eap_get_config ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_tls.o) +eap_get_config_blob ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) +eap_get_config_fragment_size ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eap_wsc.o) +eap_get_config_identity ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(eap_ttls.o) +eap_get_config_new_password ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) +eap_get_config_otp ../..//econais/build/libwismart.a(eap.o) +eap_get_config_password ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(eap_md5.o) + ../..//econais/build/libwismart.a(eap_ttls.o) +eap_get_config_password2 ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(eap_ttls.o) +eap_get_config_phase1 ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eap_wsc.o) +eap_get_config_phase2 ../..//econais/build/libwismart.a(eap.o) +eap_get_eapKeyData ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) +eap_get_eapRespData ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) +eap_get_id ../..//econais/build/libwismart.a(eap_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(eap_md5.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_tls.o) + ../..//econais/build/libwismart.a(eapol_auth_sm.o) +eap_get_identity ../..//econais/build/libwismart.a(eap_server.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +eap_get_interface ../..//econais/build/libwismart.a(eap_server.o) + ../..//econais/build/libwismart.a(eapol_auth_sm.o) +eap_get_name ../..//econais/build/libwismart.a(eap_methods.o) +eap_get_names ../..//econais/build/libwismart.a(eap_methods.o) +eap_get_names_as_string_array ../..//econais/build/libwismart.a(eap_methods.o) +eap_get_phase2_type ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) +eap_get_phase2_types ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) +eap_get_type ../..//econais/build/libwismart.a(eap_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eapol_auth_sm.o) +eap_hdr_validate ../..//econais/build/libwismart.a(eap_common.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(eap_md5.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(eap.o) +eap_invalidate_cached_session ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) +eap_is_wps_pbc_enrollee ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +eap_is_wps_pin_enrollee ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +eap_key_available ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) +eap_msg_alloc ../..//econais/build/libwismart.a(eap_common.o) + ../..//econais/build/libwismart.a(eap_wsc_common.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(eap_md5.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(eap.o) +eap_notify_lower_layer_success ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) +eap_notify_pending ../..//econais/build/libwismart.a(eap.o) +eap_notify_success ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) +eap_peer_get_eap_method ../..//econais/build/libwismart.a(eap_methods.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap.o) +eap_peer_get_methods ../..//econais/build/libwismart.a(eap_methods.o) + ../..//econais/build/libwismart.a(eap.o) +eap_peer_get_type ../..//econais/build/libwismart.a(eap_methods.o) + ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(config.o) +eap_peer_md5_register ../..//econais/build/libwismart.a(eap_md5.o) + ../..//econais/build/libwismart.a(eap_register.o) +eap_peer_method_alloc ../..//econais/build/libwismart.a(eap_methods.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(eap_md5.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_tls.o) +eap_peer_method_free ../..//econais/build/libwismart.a(eap_methods.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(eap_md5.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_tls.o) +eap_peer_method_register ../..//econais/build/libwismart.a(eap_methods.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(eap_md5.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_tls.o) +eap_peer_mschapv2_register ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(eap_register.o) +eap_peer_peap_register ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_register.o) +eap_peer_select_phase2_methods ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_ttls.o) +eap_peer_sm_deinit ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) +eap_peer_sm_init ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) +eap_peer_sm_step ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) +eap_peer_tls_build_ack ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_tls.o) +eap_peer_tls_decrypt ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_ttls.o) +eap_peer_tls_derive_key ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_tls.o) +eap_peer_tls_encrypt ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_ttls.o) +eap_peer_tls_phase2_nak ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_ttls.o) +eap_peer_tls_process_helper ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_tls.o) +eap_peer_tls_process_init ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_tls.o) +eap_peer_tls_reauth_init ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_tls.o) +eap_peer_tls_register ../..//econais/build/libwismart.a(eap_tls.o) + ../..//econais/build/libwismart.a(eap_register.o) +eap_peer_tls_reset_input ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_ttls.o) +eap_peer_tls_reset_output ../..//econais/build/libwismart.a(eap_tls_common.o) +eap_peer_tls_ssl_deinit ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_tls.o) +eap_peer_tls_ssl_init ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_tls.o) +eap_peer_tls_status ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_tls.o) +eap_peer_ttls_register ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_register.o) +eap_peer_unregister_methods ../..//econais/build/libwismart.a(eap_methods.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eap_peer_wsc_register ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(eap_register.o) +eap_register_methods ../..//econais/build/libwismart.a(eap_register.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eap_register_scard_ctx ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) +eap_server_clear_identity ../..//econais/build/libwismart.a(eap_server.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +eap_server_get_eap_method ../..//econais/build/libwismart.a(eap_server_methods.o) + ../..//econais/build/libwismart.a(eap_server.o) +eap_server_get_name ../..//econais/build/libwismart.a(eap_server_methods.o) + ../..//econais/build/libwismart.a(eapol_auth_sm.o) +eap_server_get_type ../..//econais/build/libwismart.a(eap_server_methods.o) + ../..//econais/build/libwismart.a(ap_config.o) +eap_server_method_alloc ../..//econais/build/libwismart.a(eap_server_methods.o) +eap_server_method_free ../..//econais/build/libwismart.a(eap_server_methods.o) +eap_server_method_register ../..//econais/build/libwismart.a(eap_server_methods.o) +eap_server_sm_deinit ../..//econais/build/libwismart.a(eap_server.o) + ../..//econais/build/libwismart.a(eapol_auth_sm.o) +eap_server_sm_init ../..//econais/build/libwismart.a(eap_server.o) + ../..//econais/build/libwismart.a(eapol_auth_sm.o) +eap_server_sm_step ../..//econais/build/libwismart.a(eap_server.o) + ../..//econais/build/libwismart.a(eapol_auth_sm.o) +eap_server_unregister_methods ../..//econais/build/libwismart.a(eap_server_methods.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eap_set_config_blob ../..//econais/build/libwismart.a(eap.o) +eap_set_fast_reauth ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) +eap_set_force_disabled ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) +eap_set_workaround ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) +eap_sm_abort ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) +eap_sm_buildIdentity ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_ttls.o) +eap_sm_get_method_name ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) +eap_sm_method_pending ../..//econais/build/libwismart.a(eap_server.o) +eap_sm_notify_cached ../..//econais/build/libwismart.a(eap_server.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +eap_sm_notify_ctrl_attached ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) +eap_sm_pending_cb ../..//econais/build/libwismart.a(eap_server.o) + ../..//econais/build/libwismart.a(eapol_auth_sm.o) +eap_sm_process_nak ../..//econais/build/libwismart.a(eap_server.o) +eap_sm_request_identity ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(eap_ttls.o) +eap_sm_request_new_password ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) +eap_sm_request_otp ../..//econais/build/libwismart.a(eap.o) +eap_sm_request_passphrase ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eap_tls.o) +eap_sm_request_password ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(eap_md5.o) + ../..//econais/build/libwismart.a(eap_ttls.o) +eap_sm_request_pin ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_tls.o) +eap_update_len ../..//econais/build/libwismart.a(eap_common.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap.o) +eap_user_get ../..//econais/build/libwismart.a(eap_server.o) +eap_wsc_build_frag_ack ../..//econais/build/libwismart.a(eap_wsc_common.o) + ../..//econais/build/libwismart.a(eap_wsc.o) +eapol_auth_alloc ../..//econais/build/libwismart.a(eapol_auth_sm.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +eapol_auth_deinit ../..//econais/build/libwismart.a(eapol_auth_sm.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +eapol_auth_eap_pending_cb ../..//econais/build/libwismart.a(eapol_auth_sm.o) +eapol_auth_free ../..//econais/build/libwismart.a(eapol_auth_sm.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +eapol_auth_init ../..//econais/build/libwismart.a(eapol_auth_sm.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +eapol_auth_step ../..//econais/build/libwismart.a(eapol_auth_sm.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +eapol_sm_configure ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(preauth.o) +eapol_sm_deinit ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(preauth.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eapol_sm_get_key ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(preauth.o) +eapol_sm_get_method_name ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eapol_sm_init ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(preauth.o) +eapol_sm_invalidate_cached_session ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eapol_sm_notify_cached ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(wpa.o) +eapol_sm_notify_config ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(preauth.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eapol_sm_notify_ctrl_attached ../..//econais/build/libwismart.a(eapol_supp_sm.o) +eapol_sm_notify_ctrl_response ../..//econais/build/libwismart.a(eapol_supp_sm.o) +eapol_sm_notify_eap_fail ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eapol_sm_notify_eap_success ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eapol_sm_notify_logoff ../..//econais/build/libwismart.a(eapol_supp_sm.o) +eapol_sm_notify_lower_layer_success ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(wpa.o) +eapol_sm_notify_pmkid_attempt ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eapol_sm_notify_portControl ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eapol_sm_notify_portEnabled ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(preauth.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eapol_sm_notify_portValid ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(preauth.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eapol_sm_notify_tx_eapol_key ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(wpa.o) +eapol_sm_register_scard_ctx ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eapol_sm_request_reauth ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(pmksa_cache.o) +eapol_sm_rx_eapol ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(preauth.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eapol_sm_step ../..//econais/build/libwismart.a(eapol_supp_sm.o) +ec_wpa_supplicant_event ../..//econais/build/libwismart.a(main_wifiengine.o) +eeprom_write_byte ../..//econais/build/libwismart.a(stm32_eeprom.o) +eloop ../..//econais/build/libwismart.a(eloop_wifiengine.o) +eloop_cancel_timeout ../..//econais/build/libwismart.a(eloop_wifiengine.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(preauth.o) + ../..//econais/build/libwismart.a(pmksa_cache.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(pmksa_cache_auth.o) + ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(eapol_auth_sm.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(tkip_countermeasures.o) + ../..//econais/build/libwismart.a(sta_info.o) + ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eloop_destroy ../..//econais/build/libwismart.a(eloop_wifiengine.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eloop_get_user_data ../..//econais/build/libwismart.a(eloop_wifiengine.o) +eloop_init ../..//econais/build/libwismart.a(eloop_wifiengine.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eloop_is_timeout_registered ../..//econais/build/libwismart.a(eloop_wifiengine.o) + ../..//econais/build/libwismart.a(scan.o) +eloop_process_pending_signals ../..//econais/build/libwismart.a(eloop_wifiengine.o) +eloop_register_read_sock ../..//econais/build/libwismart.a(eloop_wifiengine.o) + ../..//econais/build/libwismart.a(l2_packet_none.o) +eloop_register_signal ../..//econais/build/libwismart.a(eloop_wifiengine.o) +eloop_register_signal_reconfig ../..//econais/build/libwismart.a(eloop_wifiengine.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eloop_register_signal_terminate ../..//econais/build/libwismart.a(eloop_wifiengine.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eloop_register_timeout ../..//econais/build/libwismart.a(eloop_wifiengine.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(preauth.o) + ../..//econais/build/libwismart.a(pmksa_cache.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(pmksa_cache_auth.o) + ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(eapol_auth_sm.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(tkip_countermeasures.o) + ../..//econais/build/libwismart.a(sta_info.o) + ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eloop_reschedule ../..//econais/build/libwismart.a(eloop_wifiengine.o) +eloop_run ../..//econais/build/libwismart.a(eloop_wifiengine.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eloop_terminate ../..//econais/build/libwismart.a(eloop_wifiengine.o) + ../..//econais/build/libwismart.a(hostapd.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +eloop_terminated ../..//econais/build/libwismart.a(eloop_wifiengine.o) +eloop_timer ../..//econais/build/libwismart.a(eloop_wifiengine.o) +eloop_unregister_read_sock ../..//econais/build/libwismart.a(eloop_wifiengine.o) + ../..//econais/build/libwismart.a(l2_packet_none.o) +eloop_wait_for_read_sock ../..//econais/build/libwismart.a(eloop_wifiengine.o) +enable_fast_roaming ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +enable_higher_profiler ../..//econais/build/libwismart.a(libwismart_power.o) +enable_power_save ../..//econais/build/libwismart.a(libwismart_power.o) +enabled_ht_rates ../..//econais/build/libwismart.a(wifi_engine.o) +encrypt_pw_block_with_password_hash ../..//econais/build/libwismart.a(ms_funcs.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) +errno c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-reent.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-signalr.o) +etharp_cleanup_netif ../..//econais/build/libwismart.a(etharp.o) +etharp_find_addr ../..//econais/build/libwismart.a(etharp.o) +etharp_output ../..//econais/build/libwismart.a(etharp.o) + ../..//econais/build/libwismart.a(ethernetif.o) +etharp_query ../..//econais/build/libwismart.a(etharp.o) + ../..//econais/build/libwismart.a(dhcp.o) +etharp_request ../..//econais/build/libwismart.a(etharp.o) + ../..//econais/build/libwismart.a(netif.o) +etharp_tmr ../..//econais/build/libwismart.a(etharp.o) + ../..//econais/build/libwismart.a(netconf.o) +etharp_update_arp_entry ../..//econais/build/libwismart.a(etharp.o) + ../..//econais/build/libwismart.a(libwismart_softap.o) + ../..//econais/build/libwismart.a(dhcpserver.o) +ethbroadcast ../..//econais/build/libwismart.a(etharp.o) +ethernet_input ../..//econais/build/libwismart.a(etharp.o) + ../..//econais/build/libwismart.a(tcpip.o) + ../..//econais/build/libwismart.a(netconf.o) +ethernetif_init ../..//econais/build/libwismart.a(ethernetif.o) + ../..//econais/build/libwismart.a(netconf.o) +ethernetif_input ../..//econais/build/libwismart.a(ethernetif.o) + ../..//econais/build/libwismart.a(netconf.o) +ethzero ../..//econais/build/libwismart.a(etharp.o) +event_to_string ../..//econais/build/libwismart.a(driver_common.o) +evtStart build/obj/evtimer.o + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) +evtStop build/obj/evtimer.o + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) +extToMimeType ../..//econais/build/libwismart.a(hsCore.o) +f_close ../..//econais/build/libwismart.a(ff.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +f_lseek ../..//econais/build/libwismart.a(ff.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +f_mount ../..//econais/build/libwismart.a(ff.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) +f_open ../..//econais/build/libwismart.a(ff.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +f_opendir ../..//econais/build/libwismart.a(ff.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +f_read ../..//econais/build/libwismart.a(ff.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +f_readdir ../..//econais/build/libwismart.a(ff.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +fclose c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fclose.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-findfp.o) +ff_convert ../..//econais/build/libwismart.a(ccsbcs.o) + ../..//econais/build/libwismart.a(ff.o) +ff_cre_syncobj ../..//econais/build/libwismart.a(syscall.o) + ../..//econais/build/libwismart.a(ff.o) +ff_del_syncobj ../..//econais/build/libwismart.a(syscall.o) + ../..//econais/build/libwismart.a(ff.o) +ff_memalloc ../..//econais/build/libwismart.a(syscall.o) + ../..//econais/build/libwismart.a(ff.o) +ff_memfree ../..//econais/build/libwismart.a(syscall.o) + ../..//econais/build/libwismart.a(ff.o) +ff_rel_grant ../..//econais/build/libwismart.a(syscall.o) + ../..//econais/build/libwismart.a(ff.o) +ff_req_grant ../..//econais/build/libwismart.a(syscall.o) + ../..//econais/build/libwismart.a(ff.o) +ff_wtoupper ../..//econais/build/libwismart.a(ccsbcs.o) + ../..//econais/build/libwismart.a(ff.o) +fflush c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fflush.o) +fileDescriptorInUse ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +filesystem ../..//econais/build/libwismart.a(upnp_httpServer.o) +fputwc c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-fputwc.o) +g_Client_fwSize ../..//econais/build/libwismart.a(library_bootloader.o) +g_Rftest_fwSize ../..//econais/build/libwismart.a(library_bootloader.o) +g_SoftAP_fwSize ../..//econais/build/libwismart.a(library_bootloader.o) +g_security ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(libwismart_softap.o) + ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +gen_numname ../..//econais/build/libwismart.a(ff.o) +generate_authenticator_response ../..//econais/build/libwismart.a(ms_funcs.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(mschapv2.o) +generate_authenticator_response_pwhash ../..//econais/build/libwismart.a(ms_funcs.o) + ../..//econais/build/libwismart.a(mschapv2.o) +generate_nt_response ../..//econais/build/libwismart.a(ms_funcs.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(mschapv2.o) +generate_nt_response_pwhash ../..//econais/build/libwismart.a(ms_funcs.o) + ../..//econais/build/libwismart.a(mschapv2.o) +getChildCount ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +getCurrentConfiguration ../..//econais/build/libwismart.a(upnp_configurationServer.o) +getItemClass ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +getObjectPathStrFromObjectPathId ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +getResourceProtocolInfo ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +get_asymetric_start_key ../..//econais/build/libwismart.a(ms_funcs.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) +get_current_conn_ids ../..//econais/build/libwismart.a(upnp_connectionManager.o) +get_current_conn_info ../..//econais/build/libwismart.a(upnp_connectionManager.o) +get_fat ../..//econais/build/libwismart.a(ff.o) +get_hdr_bssid ../..//econais/build/libwismart.a(ieee802_11_common.o) +get_master_key ../..//econais/build/libwismart.a(ms_funcs.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(mschapv2.o) +get_protocol_info ../..//econais/build/libwismart.a(upnp_connectionManager.o) +global_0xff ../..//econais/build/libwismart.a(sdCardOverSpi.o) +hash_nt_password_hash ../..//econais/build/libwismart.a(ms_funcs.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(mschapv2.o) +hex2byte ../..//econais/build/libwismart.a(common.o) +hexstr2bin ../..//econais/build/libwismart.a(common.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(uuid.o) + ../..//econais/build/libwismart.a(mschapv2.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +hmac_md5 ../..//econais/build/libwismart.a(md5.o) + ../..//econais/build/libwismart.a(sha1-tlsprf.o) + ../..//econais/build/libwismart.a(wpa_common.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +hmac_md5_vector ../..//econais/build/libwismart.a(md5.o) + ../..//econais/build/libwismart.a(sha1-tlsprf.o) +hmac_sha1 ../..//econais/build/libwismart.a(sha1.o) + ../..//econais/build/libwismart.a(sha1-tlsprf.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(wpa_common.o) + ../..//econais/build/libwismart.a(sha1-pbkdf2.o) +hmac_sha1_vector ../..//econais/build/libwismart.a(sha1.o) + ../..//econais/build/libwismart.a(eap_peap_common.o) + ../..//econais/build/libwismart.a(sha1-tlsprf.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(wpa_common.o) + ../..//econais/build/libwismart.a(sha1-pbkdf2.o) +hmac_sha256 ../..//econais/build/libwismart.a(sha256.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_attr_process.o) + ../..//econais/build/libwismart.a(wps_attr_build.o) +hmac_sha256_vector ../..//econais/build/libwismart.a(sha256.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_attr_process.o) + ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +hostapd_acl_deinit ../..//econais/build/libwismart.a(ieee802_11_auth.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_acl_init ../..//econais/build/libwismart.a(ieee802_11_auth.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_add_sta_node ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_add_tspec ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_alloc_bss_data ../..//econais/build/libwismart.a(hostapd.o) + ../..//econais/build/libwismart.a(ap.o) +hostapd_allowed_address ../..//econais/build/libwismart.a(ieee802_11_auth.o) +hostapd_build_ap_extra_ies ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(beacon.o) +hostapd_config_defaults ../..//econais/build/libwismart.a(ap_config.o) + ../..//econais/build/libwismart.a(ap.o) +hostapd_config_defaults_bss ../..//econais/build/libwismart.a(ap_config.o) +hostapd_config_free ../..//econais/build/libwismart.a(ap_config.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_deinit_wpa ../..//econais/build/libwismart.a(wpa_auth_glue.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_deinit_wps ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_driver_commit ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_driver_get_scan_results ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_driver_scan ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_driver_set_noa ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_drv_none ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_drv_send_mlme ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_drv_set_key ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_drv_sta_deauth ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(tkip_countermeasures.o) + ../..//econais/build/libwismart.a(sta_info.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_drv_sta_disassoc ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(drv_callbacks.o) + ../..//econais/build/libwismart.a(sta_info.o) +hostapd_eid_adv_proto ../..//econais/build/libwismart.a(ieee802_11_shared.o) + ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_eid_ext_capab ../..//econais/build/libwismart.a(ieee802_11_shared.o) + ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_eid_interworking ../..//econais/build/libwismart.a(ieee802_11_shared.o) + ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_eid_roaming_consortium ../..//econais/build/libwismart.a(ieee802_11_shared.o) + ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_eid_time_adv ../..//econais/build/libwismart.a(ieee802_11_shared.o) + ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_eid_time_zone ../..//econais/build/libwismart.a(ieee802_11_shared.o) + ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_event_sta_low_ack ../..//econais/build/libwismart.a(drv_callbacks.o) + ../..//econais/build/libwismart.a(events.o) +hostapd_flush ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_free_ap_extra_ies ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(beacon.o) +hostapd_free_stas ../..//econais/build/libwismart.a(sta_info.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_get_eap_user ../..//econais/build/libwismart.a(ap_config.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +hostapd_get_hw_feature_data ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_get_psk ../..//econais/build/libwismart.a(ap_config.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) +hostapd_get_seqnum ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) +hostapd_get_ssid ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_get_vlan_id_ifname ../..//econais/build/libwismart.a(ap_config.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_if_add ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_if_remove ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_init_wps ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_init_wps_complete ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_interface_deinit ../..//econais/build/libwismart.a(hostapd.o) + ../..//econais/build/libwismart.a(ap.o) +hostapd_interface_free ../..//econais/build/libwismart.a(hostapd.o) + ../..//econais/build/libwismart.a(ap.o) +hostapd_mac_comp ../..//econais/build/libwismart.a(ap_config.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_mac_comp_empty ../..//econais/build/libwismart.a(ap_config.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_maclist_found ../..//econais/build/libwismart.a(ap_config.o) + ../..//econais/build/libwismart.a(ieee802_11_auth.o) +hostapd_new_assoc_sta ../..//econais/build/libwismart.a(hostapd.o) + ../..//econais/build/libwismart.a(drv_callbacks.o) +hostapd_notif_assoc ../..//econais/build/libwismart.a(drv_callbacks.o) + ../..//econais/build/libwismart.a(events.o) +hostapd_notif_disassoc ../..//econais/build/libwismart.a(drv_callbacks.o) + ../..//econais/build/libwismart.a(events.o) +hostapd_probe_req_rx ../..//econais/build/libwismart.a(drv_callbacks.o) + ../..//econais/build/libwismart.a(events.o) +hostapd_prune_associations ../..//econais/build/libwismart.a(utils.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_rate_found ../..//econais/build/libwismart.a(ap_config.o) +hostapd_reconfig_wpa ../..//econais/build/libwismart.a(wpa_auth_glue.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_register_probereq_cb ../..//econais/build/libwismart.a(utils.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(ap.o) +hostapd_reload_config ../..//econais/build/libwismart.a(hostapd.o) +hostapd_set_ap_wps_ie ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(ap.o) +hostapd_set_authorized ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +hostapd_set_country ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_set_drv_ieee8021x ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_set_frag ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_set_freq ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_set_generic_elem ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_set_ieee8021x ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_set_privacy ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_set_rate_sets ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_set_rts ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_set_ssid ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_set_sta_flags ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_set_tx_queue_params ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_set_wds_sta ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(sta_info.o) +hostapd_setup_interface ../..//econais/build/libwismart.a(hostapd.o) + ../..//econais/build/libwismart.a(ap.o) +hostapd_setup_interface_complete ../..//econais/build/libwismart.a(hostapd.o) +hostapd_setup_wpa ../..//econais/build/libwismart.a(wpa_auth_glue.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_setup_wpa_psk ../..//econais/build/libwismart.a(ap_config.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_sta_add ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_sta_assoc ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_sta_auth ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_sta_flags_to_drv ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) +hostapd_sta_set_flags ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_update_time_adv ../..//econais/build/libwismart.a(ieee802_11_shared.o) +hostapd_update_wps ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(hostapd.o) +hostapd_vlan_if_add ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_vlan_if_remove ../..//econais/build/libwismart.a(ap_drv_ops.o) +hostapd_wep_key_cmp ../..//econais/build/libwismart.a(ap_config.o) +hostapd_wps_add_pin ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(ap.o) +hostapd_wps_ap_pin_disable ../..//econais/build/libwismart.a(wps_hostapd.o) +hostapd_wps_ap_pin_get ../..//econais/build/libwismart.a(wps_hostapd.o) +hostapd_wps_ap_pin_random ../..//econais/build/libwismart.a(wps_hostapd.o) +hostapd_wps_ap_pin_set ../..//econais/build/libwismart.a(wps_hostapd.o) +hostapd_wps_button_pushed ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(ap.o) +hostapd_wps_config_ap ../..//econais/build/libwismart.a(wps_hostapd.o) +hostapd_wps_get_mib_sta ../..//econais/build/libwismart.a(wps_hostapd.o) +hostapd_wps_update_ie ../..//econais/build/libwismart.a(wps_hostapd.o) +hsAddClientToNewList ../..//econais/build/libwismart.a(hsCore.o) +hsAddHttpResponseText ../..//econais/build/libwismart.a(hsCore.o) +hsAddPbufToNewList ../..//econais/build/libwismart.a(hsCore.o) +hsAllocClient ../..//econais/build/libwismart.a(hsCore.o) +hsAllocDataBuffer ../..//econais/build/libwismart.a(hsCore.o) +hsAllocDataNode ../..//econais/build/libwismart.a(hsCore.o) +hsAllocIntFileHandler ../..//econais/build/libwismart.a(hsCore.o) +hsAllocProgFileHandler ../..//econais/build/libwismart.a(hsCore.o) +hsAllocResponseBuffer ../..//econais/build/libwismart.a(hsCore.o) +hsAsychronousUpdate ../..//econais/build/libwismart.a(hsCore.o) +hsBinaryTextSearch ../..//econais/build/libwismart.a(hsCore.o) +hsBuildResponses ../..//econais/build/libwismart.a(hsCore.o) +hsCallUserDynamicContentCb ../..//econais/build/libwismart.a(hsCore.o) +hsCallUserFreeCb ../..//econais/build/libwismart.a(hsCore.o) +hsCallUserRequestCb ../..//econais/build/libwismart.a(hsCore.o) +hsCallUserWakeUpCb ../..//econais/build/libwismart.a(hsCore.o) +hsCheckResponseRangeParameters ../..//econais/build/libwismart.a(hsCore.o) +hsCheckTimeouts ../..//econais/build/libwismart.a(hsCore.o) +hsClearClients ../..//econais/build/libwismart.a(hsCore.o) +hsConnectionErrorCb ../..//econais/build/libwismart.a(hsCore.o) +hsDataNodeListRead ../..//econais/build/libwismart.a(hsCore.o) +hsDataReceivedCb ../..//econais/build/libwismart.a(hsCore.o) +hsDeallocClient ../..//econais/build/libwismart.a(hsCore.o) +hsDeallocDataBuffer ../..//econais/build/libwismart.a(hsCore.o) +hsDeallocDataNode ../..//econais/build/libwismart.a(hsCore.o) +hsDeallocIntFileHandler ../..//econais/build/libwismart.a(hsCore.o) +hsDeallocProgFileHandler ../..//econais/build/libwismart.a(hsCore.o) +hsDeallocResponseBuffer ../..//econais/build/libwismart.a(hsCore.o) +hsDeallocateDataNodeList ../..//econais/build/libwismart.a(hsCore.o) +hsFclose ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_description.o) + ../..//econais/build/libwismart.a(upnp_configurationServer.o) + ../..//econais/build/libwismart.a(upnp_control.o) +hsFopen_externalMem ../..//econais/build/libwismart.a(hsCore.o) +hsFopen_internalMem ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_description.o) + ../..//econais/build/libwismart.a(upnp_configurationServer.o) + ../..//econais/build/libwismart.a(upnp_control.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) +hsFopen_progressiveMem ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_configurationServer.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +hsFread ../..//econais/build/libwismart.a(hsCore.o) +hsFree ../..//econais/build/libwismart.a(hsCore.o) +hsFreeRequestsPbufList ../..//econais/build/libwismart.a(hsCore.o) +hsFseek ../..//econais/build/libwismart.a(hsCore.o) +hsFsize ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_description.o) + ../..//econais/build/libwismart.a(upnp_configurationServer.o) + ../..//econais/build/libwismart.a(upnp_control.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +hsFtell ../..//econais/build/libwismart.a(hsCore.o) +hsFtype ../..//econais/build/libwismart.a(hsCore.o) +hsGET ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_configurationServer.o) +hsGenerateDynamicContent ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_description.o) + ../..//econais/build/libwismart.a(upnp_configurationServer.o) + ../..//econais/build/libwismart.a(upnp_control.o) +hsGetActiveServer ../..//econais/build/libwismart.a(hsCore.o) +hsGetConnectionTypeFromUserResponse ../..//econais/build/libwismart.a(hsCore.o) +hsGetDataNodeListSize ../..//econais/build/libwismart.a(hsCore.o) +hsGetDatabaseVariableName ../..//econais/build/libwismart.a(hsCore.o) +hsGetHeaderInfo ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_control.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) +hsGetMimeTypeFromFilename ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +hsGetParsingInfo ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_control.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +hsGetRangeFromResponse ../..//econais/build/libwismart.a(hsCore.o) +hsGetRequestParsingInfo ../..//econais/build/libwismart.a(hsCore.o) +hsGetRequestedRangeInfo ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +hsGetUriInfo ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_control.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +hsInactiveConnectionPollCb ../..//econais/build/libwismart.a(hsCore.o) +hsIsBusy ../..//econais/build/libwismart.a(hsCore.o) +hsLock ../..//econais/build/libwismart.a(hsCore.o) +hsLockInit ../..//econais/build/libwismart.a(hsCore.o) +hsMalloc ../..//econais/build/libwismart.a(hsCore.o) +hsMergeClientLists ../..//econais/build/libwismart.a(hsCore.o) +hsMergePbufLists ../..//econais/build/libwismart.a(hsCore.o) +hsNewConnectionAcceptedCb ../..//econais/build/libwismart.a(hsCore.o) +hsPOST ../..//econais/build/libwismart.a(hsCore.o) +hsParseReadyRequests ../..//econais/build/libwismart.a(hsCore.o) +hsPbufGetArgument_GET ../..//econais/build/libwismart.a(hsCore.o) +hsPbufGetArgument_POST ../..//econais/build/libwismart.a(hsCore.o) +hsPbufGetChar ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_serviceOperations.o) + ../..//econais/build/libwismart.a(upnp_avTransport.o) +hsPbufLen ../..//econais/build/libwismart.a(hsCore.o) +hsPbufSetChar ../..//econais/build/libwismart.a(hsCore.o) +hsPbufStrCmpN ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_avTransport.o) +hsPbufStrCpyN ../..//econais/build/libwismart.a(hsCore.o) +hsPbufStrLenBetween ../..//econais/build/libwismart.a(hsCore.o) +hsPbufStrStr ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_serviceOperations.o) + ../..//econais/build/libwismart.a(upnp_avTransport.o) +hsProcess ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) +hsProcessL ../..//econais/build/libwismart.a(hsCore.o) +hsRemoveBlacklistedClients ../..//econais/build/libwismart.a(hsCore.o) +hsRemoveClientFromReadyList ../..//econais/build/libwismart.a(hsCore.o) +hsRemoveDisconnectedClients ../..//econais/build/libwismart.a(hsCore.o) +hsRequestType ../..//econais/build/libwismart.a(hsCore.o) +hsRequestTypes ../..//econais/build/libwismart.a(hsCore.o) +hsSendHttpResponseBody ../..//econais/build/libwismart.a(hsCore.o) +hsSendHttpResponseHeaders ../..//econais/build/libwismart.a(hsCore.o) +hsSendTcpData ../..//econais/build/libwismart.a(hsCore.o) +hsSendTcpDataL ../..//econais/build/libwismart.a(hsCore.o) +hsServerInit ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) +hsServerInitL ../..//econais/build/libwismart.a(hsCore.o) +hsSetCallbackClient ../..//econais/build/libwismart.a(hsCore.o) +hsSetClientState ../..//econais/build/libwismart.a(hsCore.o) +hsSetHttpResponseBody ../..//econais/build/libwismart.a(hsCore.o) +hsSetHttpResponseFileHandler ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_description.o) + ../..//econais/build/libwismart.a(upnp_configurationServer.o) + ../..//econais/build/libwismart.a(upnp_control.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +hsSetHttpResponseFileRange ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +hsSetHttpResponseHeaders ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_description.o) + ../..//econais/build/libwismart.a(upnp_configurationServer.o) + ../..//econais/build/libwismart.a(upnp_control.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +hsStrToUint32 ../..//econais/build/libwismart.a(hsCore.o) +hsUnlock ../..//econais/build/libwismart.a(hsCore.o) +hsUriCmp ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_description.o) + ../..//econais/build/libwismart.a(upnp_configurationServer.o) +httpResponseHeadersTemplate200 ../..//econais/build/libwismart.a(upnp_configurationServer.o) +httpResponseHeadersTemplate404 ../..//econais/build/libwismart.a(upnp_configurationServer.o) +hwaddr_aton ../..//econais/build/libwismart.a(common.o) + ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(libwismart.o) +hwaddr_aton2 ../..//econais/build/libwismart.a(common.o) + ../..//econais/build/libwismart.a(config.o) +hwaddr_compact_aton ../..//econais/build/libwismart.a(common.o) +icmp_dest_unreach ../..//econais/build/libwismart.a(icmp.o) + ../..//econais/build/libwismart.a(ip.o) + ../..//econais/build/libwismart.a(udp.o) +icmp_input ../..//econais/build/libwismart.a(icmp.o) + ../..//econais/build/libwismart.a(ip.o) +icmp_time_exceeded ../..//econais/build/libwismart.a(icmp.o) + ../..//econais/build/libwismart.a(ip_frag.o) +ieee80211_tkip_countermeasures_deinit ../..//econais/build/libwismart.a(tkip_countermeasures.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) +ieee802_11_ie_count ../..//econais/build/libwismart.a(ieee802_11_common.o) +ieee802_11_parse_elems ../..//econais/build/libwismart.a(ieee802_11_common.o) + ../..//econais/build/libwismart.a(drv_callbacks.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) +ieee802_11_set_beacon ../..//econais/build/libwismart.a(beacon.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(hostapd.o) +ieee802_11_set_beacons ../..//econais/build/libwismart.a(beacon.o) + ../..//econais/build/libwismart.a(sta_info.o) + ../..//econais/build/libwismart.a(ap.o) +ieee802_11_vendor_ie_concat ../..//econais/build/libwismart.a(ieee802_11_common.o) + ../..//econais/build/libwismart.a(drv_callbacks.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +ieee802_1x_abort_auth ../..//econais/build/libwismart.a(ieee802_1x.o) +ieee802_1x_deinit ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) +ieee802_1x_free_station ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(sta_info.o) +ieee802_1x_get_identity ../..//econais/build/libwismart.a(ieee802_1x.o) +ieee802_1x_get_key ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) +ieee802_1x_get_mib ../..//econais/build/libwismart.a(ieee802_1x.o) +ieee802_1x_get_mib_sta ../..//econais/build/libwismart.a(ieee802_1x.o) +ieee802_1x_get_radius_class ../..//econais/build/libwismart.a(ieee802_1x.o) +ieee802_1x_init ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(hostapd.o) +ieee802_1x_new_station ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(hostapd.o) +ieee802_1x_notify_port_enabled ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(drv_callbacks.o) + ../..//econais/build/libwismart.a(sta_info.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) +ieee802_1x_notify_port_valid ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) +ieee802_1x_notify_pre_auth ../..//econais/build/libwismart.a(ieee802_1x.o) +ieee802_1x_receive ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(ap.o) +ieee802_1x_set_sta_authorized ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) +ieee802_1x_tx_key ../..//econais/build/libwismart.a(ieee802_1x.o) +ieee802_1x_tx_status ../..//econais/build/libwismart.a(ieee802_1x.o) +ifup ../..//econais/build/libwismart.a(libwismart.o) + ../..//econais/build/libwismart.a(libwismart_softap.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +igmp_init ../..//econais/build/libwismart.a(igmp.o) + ../..//econais/build/libwismart.a(init.o) +igmp_input ../..//econais/build/libwismart.a(igmp.o) + ../..//econais/build/libwismart.a(ip.o) +igmp_joingroup ../..//econais/build/libwismart.a(igmp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(sockets.o) +igmp_leavegroup ../..//econais/build/libwismart.a(igmp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(sockets.o) +igmp_lookfor_group ../..//econais/build/libwismart.a(igmp.o) + ../..//econais/build/libwismart.a(ip.o) +igmp_report_groups ../..//econais/build/libwismart.a(igmp.o) + ../..//econais/build/libwismart.a(netif.o) +igmp_start ../..//econais/build/libwismart.a(igmp.o) + ../..//econais/build/libwismart.a(netif.o) +igmp_stop ../..//econais/build/libwismart.a(igmp.o) + ../..//econais/build/libwismart.a(netif.o) +igmp_tmr ../..//econais/build/libwismart.a(igmp.o) + ../..//econais/build/libwismart.a(netconf.o) +inLeaveState ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +inc_byte_array ../..//econais/build/libwismart.a(common.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(tlsv1_record.o) + ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(hostapd.o) +inet_chksum ../..//econais/build/libwismart.a(inet_chksum.o) + ../..//econais/build/libwismart.a(ip_frag.o) + ../..//econais/build/libwismart.a(igmp.o) + ../..//econais/build/libwismart.a(icmp.o) +inet_chksum_pbuf ../..//econais/build/libwismart.a(inet_chksum.o) + ../..//econais/build/libwismart.a(icmp.o) +inet_chksum_pseudo ../..//econais/build/libwismart.a(inet_chksum.o) + ../..//econais/build/libwismart.a(udp.o) + ../..//econais/build/libwismart.a(tcp_out.o) +inet_chksum_pseudo_partial ../..//econais/build/libwismart.a(inet_chksum.o) +initFilinfo ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +initLibwismart build/obj/main.o +init_profile_registry_keys ../..//econais/build/libwismart.a(stm32_eeprom.o) + ../..//econais/build/libwismart.a(libwismart.o) +init_registry_key ../..//econais/build/libwismart.a(stm32_eeprom.o) +ip4_addr_isbroadcast ../..//econais/build/libwismart.a(ip_addr.o) + ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(etharp.o) + ../..//econais/build/libwismart.a(ip.o) + ../..//econais/build/libwismart.a(icmp.o) + ../..//econais/build/libwismart.a(udp.o) + ../..//econais/build/libwismart.a(wifi_filter.o) +ip4_addr_netmask_valid ../..//econais/build/libwismart.a(ip_addr.o) +ip_addr_any ../..//econais/build/libwismart.a(ip_addr.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(igmp.o) + ../..//econais/build/libwismart.a(dns.o) + ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(dhcpserver.o) +ip_addr_broadcast ../..//econais/build/libwismart.a(ip_addr.o) + ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(dhcpserver.o) +ip_frag ../..//econais/build/libwismart.a(ip_frag.o) + ../..//econais/build/libwismart.a(ip.o) +ip_input ../..//econais/build/libwismart.a(ip.o) + ../..//econais/build/libwismart.a(etharp.o) + ../..//econais/build/libwismart.a(tcpip.o) +ip_output ../..//econais/build/libwismart.a(ip.o) + ../..//econais/build/libwismart.a(icmp.o) + ../..//econais/build/libwismart.a(tcp_out.o) +ip_output_if ../..//econais/build/libwismart.a(ip.o) + ../..//econais/build/libwismart.a(raw.o) + ../..//econais/build/libwismart.a(icmp.o) + ../..//econais/build/libwismart.a(udp.o) +ip_output_if_opt ../..//econais/build/libwismart.a(ip.o) + ../..//econais/build/libwismart.a(igmp.o) +ip_reass ../..//econais/build/libwismart.a(ip_frag.o) + ../..//econais/build/libwismart.a(ip.o) +ip_reass_tmr ../..//econais/build/libwismart.a(ip_frag.o) + ../..//econais/build/libwismart.a(netconf.o) +ip_route ../..//econais/build/libwismart.a(ip.o) + ../..//econais/build/libwismart.a(raw.o) + ../..//econais/build/libwismart.a(udp.o) + ../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(tcp.o) +ipaddr_addr ../..//econais/build/libwismart.a(ip_addr.o) + ../..//econais/build/libwismart.a(dns.o) + ../..//econais/build/libwismart.a(dhcpserver.o) +ipaddr_aton ../..//econais/build/libwismart.a(ip_addr.o) + ../..//econais/build/libwismart.a(dhcpserver.o) +ipaddr_htoa ../..//econais/build/libwismart.a(ip_addr.o) +ipaddr_ntoa ../..//econais/build/libwismart.a(ip_addr.o) + ../..//econais/build/libwismart.a(dhcpserver.o) +ipaddr_ntoa_r ../..//econais/build/libwismart.a(ip_addr.o) +isAcceptableBSS ../..//econais/build/libwismart.a(wifi_scan.o) +is_nil_uuid ../..//econais/build/libwismart.a(uuid.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +iswspace c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-iswspace.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfiscanf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfscanf.o) +key_mgmt2driver ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(ap.o) +l2_packet_deinit ../..//econais/build/libwismart.a(l2_packet_none.o) + ../..//econais/build/libwismart.a(preauth.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +l2_packet_get_ip_addr ../..//econais/build/libwismart.a(l2_packet_none.o) +l2_packet_get_own_addr ../..//econais/build/libwismart.a(l2_packet_none.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +l2_packet_init ../..//econais/build/libwismart.a(l2_packet_none.o) + ../..//econais/build/libwismart.a(preauth.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +l2_packet_notify_auth_start ../..//econais/build/libwismart.a(l2_packet_none.o) + ../..//econais/build/libwismart.a(events.o) +l2_packet_send ../..//econais/build/libwismart.a(l2_packet_none.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(preauth.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) +libwismart_AddRoamingEventThreshold ../..//econais/build/libwismart.a(libwismart.o) +libwismart_ClearTcpStats ../..//econais/build/libwismart.a(libwismart.o) +libwismart_ClearTraceMask ../..//econais/build/libwismart.a(debug.o) + ../..//econais/build/libwismart.a(libwismart.o) +libwismart_DMATest ../..//econais/build/libwismart.a(libwismart.o) +libwismart_DebugPin_Init ../..//econais/build/libwismart.a(debug.o) + ../..//econais/build/libwismart.a(libwismart.o) +libwismart_DebugPin_Reset ../..//econais/build/libwismart.a(debug.o) + ../..//econais/build/libwismart.a(libwismart_power.o) +libwismart_DebugPin_Set ../..//econais/build/libwismart.a(debug.o) + ../..//econais/build/libwismart.a(libwismart_power.o) +libwismart_DebugPin_Toggle ../..//econais/build/libwismart.a(debug.o) +libwismart_Delay_ms ../..//econais/build/libwismart.a(libwismart.o) + ../..//econais/build/libwismart.a(driver_wifiengine.o) + ../..//econais/build/libwismart.a(transport.o) +libwismart_DhcpEnable ../..//econais/build/libwismart.a(libwismart.o) +libwismart_DhcpResult ../..//econais/build/libwismart.a(libwismart.o) + ../..//econais/build/libwismart.a(netconf.o) +libwismart_DisableRoaming ../..//econais/build/libwismart.a(libwismart.o) +libwismart_ElapsedTime ../..//econais/build/libwismart.a(timer_events.o) + ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(netconf.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) +libwismart_EnableBsdSocketAPI ../..//econais/build/libwismart.a(libwismart_lwip.o) +libwismart_EnableRoaming ../..//econais/build/libwismart.a(libwismart.o) +libwismart_GetApMac ../..//econais/build/libwismart.a(libwismart.o) +libwismart_GetAssocReqIEs ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(main_wifiengine.o) +libwismart_GetCurrentIP ../..//econais/build/libwismart.a(libwismart.o) + ../..//econais/build/libwismart.a(upnp_core.o) +libwismart_GetDefaultHWIF ../..//econais/build/libwismart.a(libwismart.o) + build/obj/main.o +libwismart_GetMac ../..//econais/build/libwismart.a(libwismart.o) +libwismart_GetMemFree_PBufPool ../..//econais/build/libwismart.a(libwismart.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(mibs.o) + ../..//econais/build/libwismart.a(dhcpserver.o) + ../..//econais/build/libwismart.a(transport.o) +libwismart_GetMemFree_Ram ../..//econais/build/libwismart.a(libwismart.o) + ../..//econais/build/libwismart.a(mibs.o) + ../..//econais/build/libwismart.a(transport.o) +libwismart_GetRssi ../..//econais/build/libwismart.a(libwismart.o) +libwismart_GetSnr ../..//econais/build/libwismart.a(libwismart.o) +libwismart_GetTcpStats ../..//econais/build/libwismart.a(libwismart.o) +libwismart_GetTime ../..//econais/build/libwismart.a(timer_events.o) + ../..//econais/build/libwismart.a(eloop_wifiengine.o) + ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(dhcpserver.o) + ../..//econais/build/libwismart.a(netconf.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) +libwismart_GetTraceMask ../..//econais/build/libwismart.a(debug.o) +libwismart_GetVersion ../..//econais/build/libwismart.a(libwismart.o) +libwismart_GetWiFiMode ../..//econais/build/libwismart.a(libwismart.o) +libwismart_GetWismartHWIF ../..//econais/build/libwismart.a(libwismart.o) +libwismart_Init ../..//econais/build/libwismart.a(libwismart.o) + build/obj/main.o +libwismart_Init_RfTest ../..//econais/build/libwismart.a(libwismart.o) +libwismart_IsConnected ../..//econais/build/libwismart.a(libwismart_cm.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) +libwismart_LinkList_AddAfter ../..//econais/build/libwismart.a(link_list.o) +libwismart_LinkList_AddFirst ../..//econais/build/libwismart.a(link_list.o) + ../..//econais/build/libwismart.a(roam.o) + ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_filter.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) +libwismart_LinkList_AddLast ../..//econais/build/libwismart.a(link_list.o) +libwismart_LinkList_Count ../..//econais/build/libwismart.a(link_list.o) + ../..//econais/build/libwismart.a(wifi_filter.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) +libwismart_LinkList_Exec ../..//econais/build/libwismart.a(link_list.o) + ../..//econais/build/libwismart.a(roam.o) + ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_filter.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) +libwismart_LinkList_Exist ../..//econais/build/libwismart.a(link_list.o) +libwismart_LinkList_Find ../..//econais/build/libwismart.a(link_list.o) + ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_filter.o) +libwismart_LinkList_FindAndRemove ../..//econais/build/libwismart.a(link_list.o) + ../..//econais/build/libwismart.a(roam.o) + ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_filter.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) +libwismart_LinkList_GetFirst ../..//econais/build/libwismart.a(link_list.o) +libwismart_LinkList_GetFirstNode ../..//econais/build/libwismart.a(link_list.o) +libwismart_LinkList_GetLast ../..//econais/build/libwismart.a(link_list.o) +libwismart_LinkList_Init ../..//econais/build/libwismart.a(link_list.o) + ../..//econais/build/libwismart.a(roam.o) + ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_filter.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) +libwismart_LinkList_Remove ../..//econais/build/libwismart.a(link_list.o) +libwismart_LinkList_RemoveFirst ../..//econais/build/libwismart.a(link_list.o) + ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) +libwismart_LinkList_RemoveLast ../..//econais/build/libwismart.a(link_list.o) +libwismart_LwIP_SetHostname ../..//econais/build/libwismart.a(netconf.o) +libwismart_LwIP_init ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(libwismart.o) +libwismart_LwIP_lock ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(tcpip.o) +libwismart_LwIP_unlock ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(tcpip.o) +libwismart_NetDown ../..//econais/build/libwismart.a(libwismart_cm.o) + ../..//econais/build/libwismart.a(libwismart.o) +libwismart_PBufQueue_Add ../..//econais/build/libwismart.a(libwismart_pbuf_queues.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(transport.o) +libwismart_PBufQueue_Deinit ../..//econais/build/libwismart.a(libwismart_pbuf_queues.o) + ../..//econais/build/libwismart.a(wifi_softap.o) +libwismart_PBufQueue_GetLast ../..//econais/build/libwismart.a(libwismart_pbuf_queues.o) + ../..//econais/build/libwismart.a(ethernetif.o) + ../..//econais/build/libwismart.a(wifi_data_queue.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) +libwismart_PBufQueue_Init ../..//econais/build/libwismart.a(libwismart_pbuf_queues.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_softap.o) +libwismart_PBufQueue_RemoveFreeLast ../..//econais/build/libwismart.a(libwismart_pbuf_queues.o) + ../..//econais/build/libwismart.a(wifi_data_queue.o) +libwismart_PBufQueue_RemoveLast ../..//econais/build/libwismart.a(libwismart_pbuf_queues.o) + ../..//econais/build/libwismart.a(ethernetif.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) +libwismart_PBufQueue_Send ../..//econais/build/libwismart.a(wifi_data_queue.o) + ../..//econais/build/libwismart.a(wifi_softap.o) +libwismart_PBufQueue_isEmpty ../..//econais/build/libwismart.a(libwismart_pbuf_queues.o) + ../..//econais/build/libwismart.a(wifi_softap.o) +libwismart_PBufQueue_isFull ../..//econais/build/libwismart.a(libwismart_pbuf_queues.o) +libwismart_PowerSave_Disable ../..//econais/build/libwismart.a(libwismart_power.o) +libwismart_PowerSave_Enable ../..//econais/build/libwismart.a(libwismart_power.o) + build/obj/main.o +libwismart_PowerSave_HigherProfile ../..//econais/build/libwismart.a(libwismart_power.o) + build/obj/main.o +libwismart_PowerSave_Init ../..//econais/build/libwismart.a(libwismart_power.o) + ../..//econais/build/libwismart.a(libwismart.o) +libwismart_PowerSave_MCUShutdown ../..//econais/build/libwismart.a(libwismart_power.o) +libwismart_PowerSave_RelResource ../..//econais/build/libwismart.a(libwismart_power.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) + ../..//econais/build/libwismart.a(ethernetif.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) + ../..//econais/build/libwismart.a(libwismart.o) +libwismart_PowerSave_RelResourceI ../..//econais/build/libwismart.a(libwismart_power.o) +libwismart_PowerSave_ReqResource ../..//econais/build/libwismart.a(libwismart_power.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) + ../..//econais/build/libwismart.a(libwismart.o) +libwismart_PowerSave_ReqResourceI ../..//econais/build/libwismart.a(libwismart_power.o) +libwismart_PowerSave_ResetResource ../..//econais/build/libwismart.a(libwismart_power.o) + ../..//econais/build/libwismart.a(wifi_engine.o) +libwismart_PowerSave_ResetResourceI ../..//econais/build/libwismart.a(libwismart_power.o) +libwismart_PowerSave_isEnable ../..//econais/build/libwismart.a(libwismart_power.o) +libwismart_PowerSave_isHigherProfile ../..//econais/build/libwismart.a(libwismart_power.o) +libwismart_PrintTcpStats ../..//econais/build/libwismart.a(libwismart.o) +libwismart_ProfileGet_Buf ../..//econais/build/libwismart.a(stm32_eeprom.o) + ../..//econais/build/libwismart.a(wifi_engine.o) +libwismart_ProfileGet_Int ../..//econais/build/libwismart.a(stm32_eeprom.o) + ../..//econais/build/libwismart.a(libwismart_softap.o) + ../..//econais/build/libwismart.a(upnp_configurationServer.o) + ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(wifi_softap.o) +libwismart_ProfileGet_Str ../..//econais/build/libwismart.a(stm32_eeprom.o) + ../..//econais/build/libwismart.a(libwismart_softap.o) + ../..//econais/build/libwismart.a(upnp_configurationServer.o) +libwismart_ProfileSet_Buf ../..//econais/build/libwismart.a(stm32_eeprom.o) + ../..//econais/build/libwismart.a(libwismart.o) +libwismart_ProfileSet_Int ../..//econais/build/libwismart.a(stm32_eeprom.o) + ../..//econais/build/libwismart.a(upnp_configurationServer.o) +libwismart_ProfileSet_Str ../..//econais/build/libwismart.a(stm32_eeprom.o) + ../..//econais/build/libwismart.a(upnp_configurationServer.o) +libwismart_Reboot ../..//econais/build/libwismart.a(libwismart.o) + ../..//econais/build/libwismart.a(upnp_configurationServer.o) + ../..//econais/build/libwismart.a(wifi_transport.o) +libwismart_RegisterDhcpCB ../..//econais/build/libwismart.a(libwismart.o) +libwismart_RegistryCreateKey ../..//econais/build/libwismart.a(stm32_eeprom.o) +libwismart_RegistryFormat ../..//econais/build/libwismart.a(stm32_eeprom.o) +libwismart_RegistryGet ../..//econais/build/libwismart.a(stm32_eeprom.o) +libwismart_RegistryIsValueEmpty ../..//econais/build/libwismart.a(stm32_eeprom.o) +libwismart_RegistryOpen ../..//econais/build/libwismart.a(stm32_eeprom.o) +libwismart_RegistrySet ../..//econais/build/libwismart.a(stm32_eeprom.o) +libwismart_RemoveRoamingEventThreshold ../..//econais/build/libwismart.a(libwismart.o) +libwismart_Roam_GetBGScanTime ../..//econais/build/libwismart.a(libwismart.o) +libwismart_Roam_SetBGScanTime ../..//econais/build/libwismart.a(libwismart.o) +libwismart_ScanRequest ../..//econais/build/libwismart.a(libwismart_scan.o) +libwismart_Scan_Disable_BG ../..//econais/build/libwismart.a(libwismart_scan.o) +libwismart_Scan_Enable_BG ../..//econais/build/libwismart.a(libwismart_scan.o) + ../..//econais/build/libwismart.a(roam.o) +libwismart_SendConsoleRequest ../..//econais/build/libwismart.a(libwismart.o) +libwismart_SetScanRunsForConnTimeout ../..//econais/build/libwismart.a(libwismart_scan.o) +libwismart_SetStaticIP ../..//econais/build/libwismart.a(libwismart.o) + ../..//econais/build/libwismart.a(dhcpserver.o) +libwismart_SetTraceMask ../..//econais/build/libwismart.a(debug.o) +libwismart_SoftAP_Client_Change_Ind ../..//econais/build/libwismart.a(libwismart_softap.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(dhcpserver.o) +libwismart_SoftAP_Started_Ind ../..//econais/build/libwismart.a(libwismart_softap.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +libwismart_StartDhcpServer ../..//econais/build/libwismart.a(libwismart_softap.o) +libwismart_StartPeriodicScan ../..//econais/build/libwismart.a(libwismart_scan.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) + ../..//econais/build/libwismart.a(libwismart.o) +libwismart_StopPeriodicScan ../..//econais/build/libwismart.a(libwismart_scan.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +libwismart_ThreadExec ../..//econais/build/libwismart.a(ec_tools.o) + ../..//econais/build/libwismart.a(main_wifiengine.o) +libwismart_TimerReset ../..//econais/build/libwismart.a(timer_events.o) + ../..//econais/build/libwismart.a(libwismart_scan.o) +libwismart_TimerSet ../..//econais/build/libwismart.a(timer_events.o) + ../..//econais/build/libwismart.a(eloop_wifiengine.o) + ../..//econais/build/libwismart.a(wifi_ps.o) + ../..//econais/build/libwismart.a(libwismart_scan.o) +libwismart_TimerSetI ../..//econais/build/libwismart.a(timer_events.o) +libwismart_TimerStop ../..//econais/build/libwismart.a(timer_events.o) + ../..//econais/build/libwismart.a(eloop_wifiengine.o) + ../..//econais/build/libwismart.a(wifi_ps.o) + ../..//econais/build/libwismart.a(libwismart_scan.o) +libwismart_UART_DeInit ../..//econais/build/libwismart.a(libwismart_uart.o) +libwismart_UART_IRQHandler ../..//econais/build/libwismart.a(libwismart_uart.o) + build/obj/main.o +libwismart_UART_Init ../..//econais/build/libwismart.a(libwismart_uart.o) + ../..//econais/build/libwismart.a(libwismart.o) +libwismart_UART_InitRecv ../..//econais/build/libwismart.a(libwismart_uart.o) +libwismart_UART_RXDMA_IRQHandler ../..//econais/build/libwismart.a(libwismart_uart.o) + build/obj/main.o +libwismart_UART_RecvBuff ../..//econais/build/libwismart.a(libwismart_uart.o) +libwismart_UART_RecvBuff_Abort ../..//econais/build/libwismart.a(libwismart_uart.o) +libwismart_UART_RecvBuff_AbortI ../..//econais/build/libwismart.a(libwismart_uart.o) +libwismart_UART_SendBuff ../..//econais/build/libwismart.a(libwismart_uart.o) + ../..//econais/build/libwismart.a(print.o) +libwismart_UART_SendChar ../..//econais/build/libwismart.a(libwismart_uart.o) +libwismart_UART_SendCharI ../..//econais/build/libwismart.a(libwismart_uart.o) +libwismart_UART_TXDMA_IRQHandler ../..//econais/build/libwismart.a(libwismart_uart.o) + build/obj/main.o +libwismart_WiFiConnect ../..//econais/build/libwismart.a(libwismart_cm.o) +libwismart_WiFiConnectBSSID ../..//econais/build/libwismart.a(libwismart_cm.o) +libwismart_WiFiConnectEnterprise ../..//econais/build/libwismart.a(libwismart_cm.o) +libwismart_WiFiConnectWPS ../..//econais/build/libwismart.a(libwismart_cm.o) +libwismart_WiFiConnectedInd ../..//econais/build/libwismart.a(libwismart_cm.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +libwismart_WiFiCreateAdHoc ../..//econais/build/libwismart.a(libwismart_cm.o) +libwismart_WiFiDisconnect ../..//econais/build/libwismart.a(libwismart_cm.o) + ../..//econais/build/libwismart.a(libwismart.o) +libwismart_WiFiDisconnectedInd ../..//econais/build/libwismart.a(libwismart_cm.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(libwismart_scan.o) +libwismart_WiFiInit ../..//econais/build/libwismart.a(libwismart.o) + ../..//econais/build/libwismart.a(libwismart_softap.o) + ../..//econais/build/libwismart.a(libwismart_scan.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +libwismart_WiFiReInit ../..//econais/build/libwismart.a(libwismart.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) +libwismart_WiFiSetWep ../..//econais/build/libwismart.a(libwismart_cm.o) +libwismart_WiFiShutdown ../..//econais/build/libwismart.a(libwismart.o) + ../..//econais/build/libwismart.a(libwismart_softap.o) + ../..//econais/build/libwismart.a(libwismart_power.o) +libwismart_WiFiWPSFinalConnect ../..//econais/build/libwismart.a(libwismart_cm.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +libwismart_WiFi_Filter_Clean ../..//econais/build/libwismart.a(wifi_filter.o) +libwismart_WiFi_Filter_Get ../..//econais/build/libwismart.a(wifi_filter.o) +libwismart_WiFi_Filter_Set ../..//econais/build/libwismart.a(wifi_filter.o) +libwismart_WiFi_Get_MAC ../..//econais/build/libwismart.a(libwismart.o) +libwismart_WiFi_IRQHandler ../..//econais/build/libwismart.a(wifi_transport.o) + build/obj/main.o +libwismart_WiFi_PSDisable ../..//econais/build/libwismart.a(wifi_ps.o) +libwismart_WiFi_PSEnable ../..//econais/build/libwismart.a(wifi_ps.o) +libwismart_WiFi_Set_MAC ../..//econais/build/libwismart.a(libwismart.o) +libwismart_WiFi_SoftAP_Start ../..//econais/build/libwismart.a(libwismart_softap.o) +libwismart_WiFi_SoftAP_Stop ../..//econais/build/libwismart.a(libwismart_softap.o) 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../..//econais/build/libwismart.a(mschapv2.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) +mschapv2_verify_auth_response ../..//econais/build/libwismart.a(mschapv2.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(eap_ttls.o) +mute ../..//econais/build/libwismart.a(upnp_renderingControl.o) +muteVal ../..//econais/build/libwismart.a(upnp_renderingControl.o) +n11_enabled ../..//econais/build/libwismart.a(upnp_configurationServer.o) +nanf c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-sf_nan.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strtod.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfscanf.o) +netbuf_alloc ../..//econais/build/libwismart.a(netbuf.o) + ../..//econais/build/libwismart.a(sockets.o) +netbuf_chain ../..//econais/build/libwismart.a(netbuf.o) +netbuf_data ../..//econais/build/libwismart.a(netbuf.o) +netbuf_delete ../..//econais/build/libwismart.a(netbuf.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(sockets.o) +netbuf_first ../..//econais/build/libwismart.a(netbuf.o) +netbuf_free ../..//econais/build/libwismart.a(netbuf.o) + ../..//econais/build/libwismart.a(sockets.o) +netbuf_new ../..//econais/build/libwismart.a(netbuf.o) +netbuf_next ../..//econais/build/libwismart.a(netbuf.o) +netbuf_ref ../..//econais/build/libwismart.a(netbuf.o) +netconn_accept ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(sockets.o) +netconn_alloc ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) +netconn_bind ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(sockets.o) +netconn_close ../..//econais/build/libwismart.a(api_lib.o) +netconn_connect ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(sockets.o) +netconn_delete ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(sockets.o) +netconn_disconnect ../..//econais/build/libwismart.a(api_lib.o) +netconn_free ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) +netconn_getaddr ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(sockets.o) +netconn_gethostbyname ../..//econais/build/libwismart.a(api_lib.o) +netconn_join_leave_group ../..//econais/build/libwismart.a(api_lib.o) +netconn_listen_with_backlog ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(sockets.o) +netconn_new_with_proto_and_callback ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(sockets.o) +netconn_recv ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(sockets.o) +netconn_recv_tcp_pbuf ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(sockets.o) +netconn_recved ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(sockets.o) +netconn_send ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(sockets.o) +netconn_sendto ../..//econais/build/libwismart.a(api_lib.o) +netconn_shutdown ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(sockets.o) +netconn_write_partly ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(sockets.o) +netif_add ../..//econais/build/libwismart.a(netif.o) + ../..//econais/build/libwismart.a(netconf.o) +netif_default ../..//econais/build/libwismart.a(netif.o) + ../..//econais/build/libwismart.a(ip.o) +netif_find ../..//econais/build/libwismart.a(netif.o) +netif_init ../..//econais/build/libwismart.a(netif.o) + ../..//econais/build/libwismart.a(init.o) +netif_list ../..//econais/build/libwismart.a(netif.o) + ../..//econais/build/libwismart.a(ip.o) + ../..//econais/build/libwismart.a(igmp.o) + ../..//econais/build/libwismart.a(dhcp.o) +netif_remove ../..//econais/build/libwismart.a(netif.o) + ../..//econais/build/libwismart.a(netconf.o) +netif_set_addr ../..//econais/build/libwismart.a(netif.o) + ../..//econais/build/libwismart.a(netconf.o) +netif_set_default ../..//econais/build/libwismart.a(netif.o) + ../..//econais/build/libwismart.a(netconf.o) +netif_set_down ../..//econais/build/libwismart.a(netif.o) + ../..//econais/build/libwismart.a(dhcp.o) +netif_set_gw ../..//econais/build/libwismart.a(netif.o) + ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(netconf.o) +netif_set_ipaddr ../..//econais/build/libwismart.a(netif.o) + ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(netconf.o) +netif_set_link_down ../..//econais/build/libwismart.a(netif.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +netif_set_link_up ../..//econais/build/libwismart.a(netif.o) + ../..//econais/build/libwismart.a(libwismart_softap.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +netif_set_netmask ../..//econais/build/libwismart.a(netif.o) + ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(netconf.o) +netif_set_up ../..//econais/build/libwismart.a(netif.o) + ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(netconf.o) +netif_wifi ../..//econais/build/libwismart.a(netconf.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(libwismart_softap.o) + ../..//econais/build/libwismart.a(wifi_filter.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +networkNameStr ../..//econais/build/libwismart.a(upnp_configurationServer.o) +new_password_encrypted_with_old_nt_password_hash ../..//econais/build/libwismart.a(ms_funcs.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) +nr_get_soft_ap_psk ../..//econais/build/libwismart.a(main_wifiengine.o) +nr_p2p_group_wps_pbc ../..//econais/build/libwismart.a(main_wifiengine.o) +nr_softap_start ../..//econais/build/libwismart.a(main_wifiengine.o) + ../..//econais/build/libwismart.a(libwismart_softap.o) +nr_wpa_exit ../..//econais/build/libwismart.a(main_wifiengine.o) +nt_challenge_response ../..//econais/build/libwismart.a(ms_funcs.o) + ../..//econais/build/libwismart.a(eap_ttls.o) +nt_password_hash ../..//econais/build/libwismart.a(ms_funcs.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(mschapv2.o) +nt_password_hash_encrypted_with_block ../..//econais/build/libwismart.a(ms_funcs.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) +nvicDisableVector build/obj/nvic.o +nvicEnableVector build/obj/nvic.o +nvicSetSystemHandlerPriority build/obj/nvic.o + build/obj/chcore_v7m.o +old_nt_password_hash_encrypted_with_new_nt_password_hash ../..//econais/build/libwismart.a(ms_funcs.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) +os_daemonize ../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +os_daemonize_terminate ../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +os_get_random ../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(pkcs1.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(tlsv1_record.o) + ../..//econais/build/libwismart.a(tlsv1_client_write.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(ms_funcs.o) + ../..//econais/build/libwismart.a(dh_groups.o) + ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +os_get_time ../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(ieee802_11_shared.o) + ../..//econais/build/libwismart.a(x509v3.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(tlsv1_client_write.o) + ../..//econais/build/libwismart.a(pmksa_cache.o) + ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(pmksa_cache_auth.o) + ../..//econais/build/libwismart.a(tkip_countermeasures.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(common.o) +os_get_time_mono ../..//econais/build/libwismart.a(eloop_wifiengine.o) +os_gmtime ../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(ieee802_11_shared.o) +os_mktime ../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(x509v3.o) +os_program_deinit ../..//econais/build/libwismart.a(os_wifiengine.o) +os_program_init ../..//econais/build/libwismart.a(os_wifiengine.o) +os_random ../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(wps_common.o) +os_readfile ../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(tlsv1_cred.o) +os_realloc ../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(bignum.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(wpabuf.o) + ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(eloop_wifiengine.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(utils.o) +os_rel2abs_path ../..//econais/build/libwismart.a(os_wifiengine.o) +os_setenv ../..//econais/build/libwismart.a(os_wifiengine.o) +os_sleep ../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(eloop_wifiengine.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +os_strlcpy ../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(l2_packet_none.o) + ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +os_unsetenv ../..//econais/build/libwismart.a(os_wifiengine.o) +os_zalloc ../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(bignum.o) + ../..//econais/build/libwismart.a(rsa.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(crypto_internal.o) + ../..//econais/build/libwismart.a(crypto_internal-cipher.o) + ../..//econais/build/libwismart.a(x509v3.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpabuf.o) + ../..//econais/build/libwismart.a(tlsv1_cred.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(preauth.o) + ../..//econais/build/libwismart.a(pmksa_cache.o) + ../..//econais/build/libwismart.a(l2_packet_none.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_tls.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eap_methods.o) + ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(blacklist.o) + ../..//econais/build/libwismart.a(pmksa_cache_auth.o) + ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(eap_server_methods.o) + ../..//econais/build/libwismart.a(eap_server.o) + ../..//econais/build/libwismart.a(eapol_auth_sm.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(sta_info.o) + ../..//econais/build/libwismart.a(ap_config.o) + ../..//econais/build/libwismart.a(hostapd.o) + ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(main_wifiengine.o) + ../..//econais/build/libwismart.a(driver_wifiengine.o) + ../..//econais/build/libwismart.a(config_wifiengine.o) +passphraseStr ../..//econais/build/libwismart.a(upnp_configurationServer.o) +pbkdf2_sha1 ../..//econais/build/libwismart.a(sha1-pbkdf2.o) + ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(ap_config.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +pbuf_alloc ../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(netbuf.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(raw.o) + ../..//econais/build/libwismart.a(etharp.o) + ../..//econais/build/libwismart.a(ip_frag.o) + ../..//econais/build/libwismart.a(igmp.o) + ../..//econais/build/libwismart.a(icmp.o) + ../..//econais/build/libwismart.a(udp.o) + ../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(dns.o) + ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(mibs.o) + ../..//econais/build/libwismart.a(dhcpserver.o) + ../..//econais/build/libwismart.a(transport.o) +pbuf_cat ../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(netbuf.o) + ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(ip_frag.o) + ../..//econais/build/libwismart.a(tcp_out.o) +pbuf_chain ../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(raw.o) + ../..//econais/build/libwismart.a(udp.o) +pbuf_clen ../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(ip_frag.o) + ../..//econais/build/libwismart.a(tcp_out.o) +pbuf_coalesce ../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(dhcpserver.o) +pbuf_copy ../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(etharp.o) + ../..//econais/build/libwismart.a(icmp.o) +pbuf_copy_partial ../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(sockets.o) + ../..//econais/build/libwismart.a(ip_frag.o) + ../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(dns.o) + ../..//econais/build/libwismart.a(dhcp.o) +pbuf_dechain ../..//econais/build/libwismart.a(pbuf.o) +pbuf_free ../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(netbuf.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(raw.o) + ../..//econais/build/libwismart.a(sockets.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(libwismart_pbuf_queues.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(ethernetif.o) + ../..//econais/build/libwismart.a(etharp.o) + ../..//econais/build/libwismart.a(ip_frag.o) + ../..//econais/build/libwismart.a(ip.o) + ../..//econais/build/libwismart.a(igmp.o) + ../..//econais/build/libwismart.a(icmp.o) + ../..//econais/build/libwismart.a(udp.o) + ../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(dns.o) + ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(tcpip.o) + ../..//econais/build/libwismart.a(mibs.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(dhcpserver.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(transport.o) +pbuf_free_callback ../..//econais/build/libwismart.a(tcpip.o) +pbuf_free_ooseq_pending ../..//econais/build/libwismart.a(pbuf.o) +pbuf_get_at ../..//econais/build/libwismart.a(pbuf.o) +pbuf_header ../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(raw.o) + ../..//econais/build/libwismart.a(etharp.o) + ../..//econais/build/libwismart.a(ip_frag.o) + ../..//econais/build/libwismart.a(ip.o) + ../..//econais/build/libwismart.a(igmp.o) + ../..//econais/build/libwismart.a(icmp.o) + ../..//econais/build/libwismart.a(udp.o) + ../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(wifi_engine.o) +pbuf_memcmp ../..//econais/build/libwismart.a(pbuf.o) +pbuf_memfind ../..//econais/build/libwismart.a(pbuf.o) +pbuf_realloc ../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(ip.o) + ../..//econais/build/libwismart.a(dns.o) + ../..//econais/build/libwismart.a(dhcp.o) +pbuf_ref ../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(libwismart_pbuf_queues.o) + ../..//econais/build/libwismart.a(etharp.o) + ../..//econais/build/libwismart.a(tcp.o) +pbuf_strstr ../..//econais/build/libwismart.a(pbuf.o) +pbuf_take ../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(sockets.o) +peap_prfplus ../..//econais/build/libwismart.a(eap_peap_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) +pkcs1_decrypt_public_key ../..//econais/build/libwismart.a(pkcs1.o) + ../..//econais/build/libwismart.a(crypto_internal-rsa.o) +pkcs1_encrypt ../..//econais/build/libwismart.a(pkcs1.o) + ../..//econais/build/libwismart.a(crypto_internal-rsa.o) +pkcs1_v15_private_key_decrypt ../..//econais/build/libwismart.a(pkcs1.o) + ../..//econais/build/libwismart.a(crypto_internal-rsa.o) +pkcs5_decrypt ../..//econais/build/libwismart.a(pkcs5.o) + ../..//econais/build/libwismart.a(pkcs8.o) +pkcs5_get_alg ../..//econais/build/libwismart.a(pkcs5.o) +pkcs8_enc_key_import ../..//econais/build/libwismart.a(pkcs8.o) + ../..//econais/build/libwismart.a(crypto_internal-rsa.o) +pkcs8_key_import ../..//econais/build/libwismart.a(pkcs8.o) + ../..//econais/build/libwismart.a(crypto_internal-rsa.o) +playbackFinishedEv ../..//econais/build/libwismart.a(upnp_httpServer.o) +pmksa_cache_add ../..//econais/build/libwismart.a(pmksa_cache.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(preauth.o) +pmksa_cache_add_okc ../..//econais/build/libwismart.a(pmksa_cache_auth.o) + ../..//econais/build/libwismart.a(wpa_auth_ie.o) +pmksa_cache_auth_add ../..//econais/build/libwismart.a(pmksa_cache_auth.o) + ../..//econais/build/libwismart.a(wpa_auth.o) +pmksa_cache_auth_deinit ../..//econais/build/libwismart.a(pmksa_cache_auth.o) + ../..//econais/build/libwismart.a(wpa_auth.o) +pmksa_cache_auth_get ../..//econais/build/libwismart.a(pmksa_cache_auth.o) + ../..//econais/build/libwismart.a(wpa_auth_ie.o) +pmksa_cache_auth_init ../..//econais/build/libwismart.a(pmksa_cache_auth.o) + ../..//econais/build/libwismart.a(wpa_auth.o) +pmksa_cache_clear_current ../..//econais/build/libwismart.a(pmksa_cache.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +pmksa_cache_deinit ../..//econais/build/libwismart.a(pmksa_cache.o) + ../..//econais/build/libwismart.a(wpa.o) +pmksa_cache_flush ../..//econais/build/libwismart.a(pmksa_cache.o) + ../..//econais/build/libwismart.a(wpa.o) +pmksa_cache_get ../..//econais/build/libwismart.a(pmksa_cache.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(preauth.o) +pmksa_cache_get_current ../..//econais/build/libwismart.a(pmksa_cache.o) + ../..//econais/build/libwismart.a(wpas_glue.o) +pmksa_cache_get_okc ../..//econais/build/libwismart.a(pmksa_cache_auth.o) + ../..//econais/build/libwismart.a(wpa_auth_ie.o) +pmksa_cache_get_opportunistic ../..//econais/build/libwismart.a(pmksa_cache.o) + ../..//econais/build/libwismart.a(preauth.o) +pmksa_cache_init ../..//econais/build/libwismart.a(pmksa_cache.o) + ../..//econais/build/libwismart.a(wpa.o) +pmksa_cache_list ../..//econais/build/libwismart.a(pmksa_cache.o) + ../..//econais/build/libwismart.a(wpa.o) +pmksa_cache_set_current ../..//econais/build/libwismart.a(pmksa_cache.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +pmksa_cache_to_eapol_data ../..//econais/build/libwismart.a(pmksa_cache_auth.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +pmksa_candidate_add ../..//econais/build/libwismart.a(preauth.o) + ../..//econais/build/libwismart.a(events.o) +pmksa_candidate_free ../..//econais/build/libwismart.a(preauth.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +port_halt build/obj/chcore.o + ../..//econais/build/libwismart.a(netbuf.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(sockets.o) + ../..//econais/build/libwismart.a(igmp.o) + ../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(memp.o) + ../..//econais/build/libwismart.a(dhcp.o) +power_sem ../..//econais/build/libwismart.a(libwismart_power.o) +print ../..//econais/build/libwismart.a(print.o) + ../..//econais/build/libwismart.a(netbuf.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(upnp_description.o) + ../..//econais/build/libwismart.a(upnp_dmsConnectionManager.o) + ../..//econais/build/libwismart.a(smem.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(sockets.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(pmksa_cache.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(eeprom.o) + ../..//econais/build/libwismart.a(libwismart_softap.o) + ../..//econais/build/libwismart.a(sdCardOverSpi.o) + ../..//econais/build/libwismart.a(syscall.o) + ../..//econais/build/libwismart.a(diskio.o) + ../..//econais/build/libwismart.a(upnp_configurationServer.o) + ../..//econais/build/libwismart.a(upnp_control.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_serviceOperations.o) + ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + ../..//econais/build/libwismart.a(upnp_avTransport.o) + ../..//econais/build/libwismart.a(upnp_connectionManager.o) + ../..//econais/build/libwismart.a(upnp_renderingControl.o) + ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(ethernetif.o) + ../..//econais/build/libwismart.a(ip.o) + ../..//econais/build/libwismart.a(igmp.o) + ../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(memp.o) + ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(driver_wifiengine.o) + ../..//econais/build/libwismart.a(config_wifiengine.o) + ../..//econais/build/libwismart.a(stm32_eeprom.o) + ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(rtc.o) + ../..//econais/build/libwismart.a(timer_events.o) + ../..//econais/build/libwismart.a(roam.o) + ../..//econais/build/libwismart.a(mibs.o) + ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_ps.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(dhcpserver.o) + ../..//econais/build/libwismart.a(netconf.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) + ../..//econais/build/libwismart.a(libwismart_power.o) + ../..//econais/build/libwismart.a(libwismart_scan.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) + ../..//econais/build/libwismart.a(libwismart.o) + build/obj/buttonExample.o + build/obj/main.o + build/obj/vectors.o +printI ../..//econais/build/libwismart.a(print.o) + build/obj/buttonExample.o +print_init ../..//econais/build/libwismart.a(print.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) +printf c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-printf.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +ps_enabled ../..//econais/build/libwismart.a(upnp_configurationServer.o) +puts c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-puts.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +qsort c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-qsort.o) + ../..//econais/build/libwismart.a(scan.o) +radius_mode_txt ../..//econais/build/libwismart.a(ieee802_1x.o) +radius_sta_rate ../..//econais/build/libwismart.a(ieee802_1x.o) +raise c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-signal.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-abort.o) +rand c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-rand.o) + ../..//econais/build/libwismart.a(igmp.o) + ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(eap_server.o) +rate_bmask ../..//econais/build/libwismart.a(wifi_engine.o) +rate_configure ../..//econais/build/libwismart.a(wifi_engine.o) +rate_gmask ../..//econais/build/libwismart.a(wifi_engine.o) +rate_htmask ../..//econais/build/libwismart.a(wifi_engine.o) +rate_table ../..//econais/build/libwismart.a(wifi_engine.o) +rate_table_len ../..//econais/build/libwismart.a(wifi_engine.o) +raw_bind ../..//econais/build/libwismart.a(raw.o) + ../..//econais/build/libwismart.a(api_msg.o) +raw_connect ../..//econais/build/libwismart.a(raw.o) + ../..//econais/build/libwismart.a(api_msg.o) +raw_input ../..//econais/build/libwismart.a(raw.o) + ../..//econais/build/libwismart.a(ip.o) +raw_new ../..//econais/build/libwismart.a(raw.o) + ../..//econais/build/libwismart.a(api_msg.o) +raw_recv ../..//econais/build/libwismart.a(raw.o) + ../..//econais/build/libwismart.a(api_msg.o) +raw_remove ../..//econais/build/libwismart.a(raw.o) + ../..//econais/build/libwismart.a(api_msg.o) +raw_send ../..//econais/build/libwismart.a(raw.o) + ../..//econais/build/libwismart.a(api_msg.o) +raw_sendto ../..//econais/build/libwismart.a(raw.o) + ../..//econais/build/libwismart.a(api_msg.o) +rc4_skip ../..//econais/build/libwismart.a(rc4.o) + ../..//econais/build/libwismart.a(crypto_internal-cipher.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(ms_funcs.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +rcons ../..//econais/build/libwismart.a(aes-internal.o) +readCsdReg ../..//econais/build/libwismart.a(sdCardOverSpi.o) +rebootTimerHandler ../..//econais/build/libwismart.a(upnp_configurationServer.o) +registryCreateKey ../..//econais/build/libwismart.a(registry_driver.o) + ../..//econais/build/libwismart.a(stm32_eeprom.o) +registryFileFormat ../..//econais/build/libwismart.a(registry_driver.o) + ../..//econais/build/libwismart.a(stm32_eeprom.o) +registryFileIsEmpty ../..//econais/build/libwismart.a(registry_driver.o) +registryFileMaxRegistryKeyAddressCount ../..//econais/build/libwismart.a(registry_driver.o) +registryFileNextFreeAddress ../..//econais/build/libwismart.a(registry_driver.o) + ../..//econais/build/libwismart.a(eeprom.o) +registryFileOpened ../..//econais/build/libwismart.a(registry_driver.o) +registryGetAddressContents ../..//econais/build/libwismart.a(registry_driver.o) +registryGetValue ../..//econais/build/libwismart.a(registry_driver.o) + ../..//econais/build/libwismart.a(stm32_eeprom.o) +registryInit ../..//econais/build/libwismart.a(registry_driver.o) + ../..//econais/build/libwismart.a(libwismart.o) +registryOpenFile ../..//econais/build/libwismart.a(registry_driver.o) + ../..//econais/build/libwismart.a(stm32_eeprom.o) +registrySetAddressContents ../..//econais/build/libwismart.a(registry_driver.o) +registrySetValue ../..//econais/build/libwismart.a(registry_driver.o) + ../..//econais/build/libwismart.a(stm32_eeprom.o) +registryValueIsEmpty ../..//econais/build/libwismart.a(registry_driver.o) + ../..//econais/build/libwismart.a(stm32_eeprom.o) +relativeCounterPosition ../..//econais/build/libwismart.a(upnp_avTransport.o) +relativeTimePos ../..//econais/build/libwismart.a(upnp_avTransport.o) +res_counters ../..//econais/build/libwismart.a(libwismart_power.o) +rijndaelEncrypt ../..//econais/build/libwismart.a(aes-internal-enc.o) +rijndaelKeySetupDec ../..//econais/build/libwismart.a(aes-internal-dec.o) +rijndaelKeySetupEnc ../..//econais/build/libwismart.a(aes-internal.o) + ../..//econais/build/libwismart.a(aes-internal-enc.o) + ../..//econais/build/libwismart.a(aes-internal-dec.o) +rlist build/obj/chschd.o + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(ec_tools.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(tcpip.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(libwismart_power.o) + build/obj/chqueues.o + build/obj/chmsg.o + build/obj/chevents.o + build/obj/chcond.o + build/obj/chmtx.o + build/obj/chsem.o + build/obj/chregistry.o + build/obj/chthreads.o + build/obj/chsys.o + build/obj/chcore_v7m.o +roam_currds ../..//econais/build/libwismart.a(libwismart.o) +roam_currrssi ../..//econais/build/libwismart.a(libwismart.o) +roam_currsnr ../..//econais/build/libwismart.a(libwismart.o) +roam_enabled ../..//econais/build/libwismart.a(upnp_configurationServer.o) +roam_lastds ../..//econais/build/libwismart.a(libwismart.o) +roam_lastrssi ../..//econais/build/libwismart.a(libwismart.o) +roam_lastsnr ../..//econais/build/libwismart.a(libwismart.o) +roaming_enabled ../..//econais/build/libwismart.a(libwismart.o) +roaming_timer ../..//econais/build/libwismart.a(libwismart_lwip.o) +rsn_pmkid ../..//econais/build/libwismart.a(wpa_common.o) + ../..//econais/build/libwismart.a(pmksa_cache.o) + ../..//econais/build/libwismart.a(pmksa_cache_auth.o) + ../..//econais/build/libwismart.a(wpa_auth.o) +rsn_preauth_candidate_process ../..//econais/build/libwismart.a(preauth.o) + ../..//econais/build/libwismart.a(wpa.o) +rsn_preauth_deinit ../..//econais/build/libwismart.a(preauth.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +rsn_preauth_in_progress ../..//econais/build/libwismart.a(preauth.o) +rsn_preauth_init ../..//econais/build/libwismart.a(preauth.o) +rsn_preauth_scan_result ../..//econais/build/libwismart.a(preauth.o) + ../..//econais/build/libwismart.a(events.o) +rsn_preauth_scan_results ../..//econais/build/libwismart.a(preauth.o) + ../..//econais/build/libwismart.a(events.o) +rssi_cb ../..//econais/build/libwismart.a(libwismart.o) +rssi_cb_set ../..//econais/build/libwismart.a(libwismart.o) +sSettings ../..//econais/build/libwismart.a(dhcpserver.o) +scan_timer ../..//econais/build/libwismart.a(libwismart_scan.o) +sdCard512BlockRead ../..//econais/build/libwismart.a(sdCardOverSpi.o) +sdCardInit ../..//econais/build/libwismart.a(sdCardOverSpi.o) + ../..//econais/build/libwismart.a(diskio.o) +sdCardInited ../..//econais/build/libwismart.a(sdCardOverSpi.o) +sdCardReadSectors ../..//econais/build/libwismart.a(sdCardOverSpi.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(diskio.o) +sdCardTest ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +sdCardWriteSector ../..//econais/build/libwismart.a(sdCardOverSpi.o) +sdDmaRead ../..//econais/build/libwismart.a(sdCardOverSpi.o) +sdDmaReadStart ../..//econais/build/libwismart.a(sdCardOverSpi.o) +sdDmaReadWait ../..//econais/build/libwismart.a(sdCardOverSpi.o) +sdInit ../..//econais/build/libwismart.a(sdCardOverSpi.o) +sdNcrDelay ../..//econais/build/libwismart.a(sdCardOverSpi.o) +sdReadMultipleBlocks ../..//econais/build/libwismart.a(sdCardOverSpi.o) +sdReadSingleBlock ../..//econais/build/libwismart.a(sdCardOverSpi.o) +sdSendCommand ../..//econais/build/libwismart.a(sdCardOverSpi.o) +sdTestSdReadSpeed ../..//econais/build/libwismart.a(upnp_httpServer.o) +sdTestSdReadSpeed2 ../..//econais/build/libwismart.a(upnp_httpServer.o) +sdWaitStartToken ../..//econais/build/libwismart.a(sdCardOverSpi.o) +setClientParameters ../..//econais/build/libwismart.a(upnp_configurationServer.o) +setSoftapParameters ../..//econais/build/libwismart.a(upnp_configurationServer.o) +set_trans_id ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(driver_wifiengine.o) + ../..//econais/build/libwismart.a(mibs.o) +setlocale c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-locale.o) +sha1_prf ../..//econais/build/libwismart.a(sha1.o) + ../..//econais/build/libwismart.a(wpa_common.o) + ../..//econais/build/libwismart.a(wpa_auth.o) +sha1_vector ../..//econais/build/libwismart.a(sha1-internal.o) + ../..//econais/build/libwismart.a(x509v3.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(sha1.o) + ../..//econais/build/libwismart.a(ms_funcs.o) +sha256_prf ../..//econais/build/libwismart.a(sha256.o) +sha256_vector ../..//econais/build/libwismart.a(sha256-internal.o) + ../..//econais/build/libwismart.a(x509v3.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(sha256.o) +signal c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-signal.o) +smemAlign ../..//econais/build/libwismart.a(smem.o) +smemAlloc ../..//econais/build/libwismart.a(smem.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_configurationServer.o) + ../..//econais/build/libwismart.a(upnp_control.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_serviceOperations.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +smemAlloc_ ../..//econais/build/libwismart.a(smem.o) +smemBestFit ../..//econais/build/libwismart.a(smem.o) +smemCurrentUsage ../..//econais/build/libwismart.a(smem.o) +smemDefrag ../..//econais/build/libwismart.a(smem.o) +smemFree ../..//econais/build/libwismart.a(smem.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_serviceOperations.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +smemFree_ ../..//econais/build/libwismart.a(smem.o) +smemInit ../..//econais/build/libwismart.a(smem.o) + ../..//econais/build/libwismart.a(upnp_core.o) +smemLastMbhAddr ../..//econais/build/libwismart.a(smem.o) +smemLimiterInfo ../..//econais/build/libwismart.a(smem.o) +smemLimiter_allocated ../..//econais/build/libwismart.a(smem.o) +smemLimiter_canAllocate ../..//econais/build/libwismart.a(smem.o) +smemLimiter_deallocated ../..//econais/build/libwismart.a(smem.o) +smemLimiter_maxAllocSize ../..//econais/build/libwismart.a(smem.o) +smemMaxAllocSize ../..//econais/build/libwismart.a(smem.o) +smemMaxAllocSize_ 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../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(upnp_control.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(dlnaAppLinking.o) +state_name ../..//econais/build/libwismart.a(wifi_ps.o) +stats_init ../..//econais/build/libwismart.a(stats.o) + ../..//econais/build/libwismart.a(init.o) +stop_wifi ../..//econais/build/libwismart.a(wifi_engine.o) +stpcpy c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-stpcpy.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + ../..//econais/build/libwismart.a(upnp_avTransport.o) +strcasecmp c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strcasecmp.o) + ../..//econais/build/libwismart.a(x509v3.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_control.o) + ../..//econais/build/libwismart.a(upnp_serviceOperations.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +strcasestr c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strcasestr.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_serviceOperations.o) +strcat c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strcat.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +strcat_safe ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +strchr c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strchr.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strstr.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strrchr.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_control.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_avTransport.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +strcmp c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strcmp.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-locale.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(eap_methods.o) + ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(upnp_configurationServer.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_serviceOperations.o) + ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + ../..//econais/build/libwismart.a(upnp_avTransport.o) + ../..//econais/build/libwismart.a(upnp_renderingControl.o) + ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(dns.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(eap_server_methods.o) + ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +strcpy c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strcpy.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strcat.o) + ../..//econais/build/libwismart.a(upnp_serviceOperations.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + ../..//econais/build/libwismart.a(upnp_mediaServer.o) + ../..//econais/build/libwismart.a(upnp_avTransport.o) + ../..//econais/build/libwismart.a(os_wifiengine.o) +strlen c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strlen.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-gdtoa-gethex.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vfiprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfiprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strtod.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vfprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-svfprintf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-sscanf.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-puts.o) + ../..//econais/build/libwismart.a(pkcs5.o) + ../..//econais/build/libwismart.a(eap_peap_common.o) + ../..//econais/build/libwismart.a(sha1-tlsprf.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(ieee802_11_shared.o) + ../..//econais/build/libwismart.a(x509v3.o) + ../..//econais/build/libwismart.a(wps_dev_attr.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(tlsv1_cred.o) + ../..//econais/build/libwismart.a(sha256.o) + ../..//econais/build/libwismart.a(sha1-pbkdf2.o) + ../..//econais/build/libwismart.a(sha1.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_configurationServer.o) + ../..//econais/build/libwismart.a(upnp_control.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_serviceOperations.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + ../..//econais/build/libwismart.a(upnp_mediaServer.o) + ../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(dns.o) + ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(eapol_auth_sm.o) + ../..//econais/build/libwismart.a(ap_config.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(main_wifiengine.o) + ../..//econais/build/libwismart.a(config_wifiengine.o) + ../..//econais/build/libwismart.a(stm32_eeprom.o) + ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +strncasecmp c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strncasecmp.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strcasestr.o) +strncmp c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strncmp.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-gdtoa-gethex.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strtod.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +strncpy c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strncpy.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(main_wifiengine.o) +strrchr c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strrchr.o) + ../..//econais/build/libwismart.a(config.o) +strstr c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strstr.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(hsCore.o) +strtod c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strtod.o) +strtof c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strtod.o) +strtol c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strtol.o) + c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-atoi.o) +strtoul c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-strtoul.o) +subscriber ../..//econais/build/libwismart.a(upnp_subscription.o) +supportedRateSet ../..//econais/build/libwismart.a(wifi_engine.o) +sw1_irqs build/obj/buttonExample.o +sw3_irqs build/obj/buttonExample.o +sys_arch_mbox_fetch ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(timers.o) +sys_arch_mbox_tryfetch ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(api_msg.o) +sys_arch_protect ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(sockets.o) + ../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(memp.o) +sys_arch_sem_wait ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(sockets.o) + ../..//econais/build/libwismart.a(tcpip.o) +sys_arch_timeouts ../..//econais/build/libwismart.a(sys_arch.o) +sys_arch_unprotect ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(sockets.o) + ../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(memp.o) +sys_init ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(init.o) +sys_mbox_free ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) +sys_mbox_new ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(tcpip.o) +sys_mbox_post ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(tcpip.o) +sys_mbox_set_invalid ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(api_msg.o) +sys_mbox_trypost ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(tcpip.o) +sys_mbox_valid ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(tcpip.o) +sys_sem_free ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(sockets.o) +sys_sem_new ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(sockets.o) +sys_sem_set_invalid ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(api_msg.o) +sys_sem_signal ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(sockets.o) +sys_sem_valid ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(api_msg.o) +sys_thread_new ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(tcpip.o) +sys_timeout ../..//econais/build/libwismart.a(timers.o) + ../..//econais/build/libwismart.a(tcpip.o) +sys_timeouts_init ../..//econais/build/libwismart.a(timers.o) + ../..//econais/build/libwismart.a(init.o) +sys_timeouts_mbox_fetch ../..//econais/build/libwismart.a(timers.o) + ../..//econais/build/libwismart.a(tcpip.o) +sys_untimeout ../..//econais/build/libwismart.a(timers.o) + ../..//econais/build/libwismart.a(tcpip.o) +tcp_abandon ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(tcp_in.o) +tcp_abort ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(netif.o) +tcp_accept ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(hsCore.o) +tcp_active_pcbs ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(timers.o) + ../..//econais/build/libwismart.a(pbuf.o) + ../..//econais/build/libwismart.a(netif.o) +tcp_active_pcbs_changed ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(tcp_in.o) +tcp_alloc ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(tcp_in.o) +tcp_arg ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) +tcp_backoff ../..//econais/build/libwismart.a(tcp.o) +tcp_bind ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) +tcp_bound_pcbs ../..//econais/build/libwismart.a(tcp.o) +tcp_close ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) +tcp_connect ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) +tcp_debug_state_str ../..//econais/build/libwismart.a(tcp.o) +tcp_eff_send_mss ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(tcp_out.o) +tcp_enqueue_flags ../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(tcp.o) +tcp_err ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) +tcp_fasttmr ../..//econais/build/libwismart.a(tcp.o) +tcp_init ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(init.o) +tcp_input ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(ip.o) +tcp_input_pcb ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(tcp_out.o) +tcp_keepalive ../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(tcp.o) +tcp_listen_pcbs ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(netif.o) +tcp_listen_with_backlog ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(hsCore.o) +tcp_new ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) +tcp_next_iss ../..//econais/build/libwismart.a(tcp.o) +tcp_output ../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(tcp.o) +tcp_pcb_lists ../..//econais/build/libwismart.a(tcp.o) +tcp_pcb_purge ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(tcp_in.o) +tcp_pcb_remove ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(tcp_in.o) +tcp_persist_backoff ../..//econais/build/libwismart.a(tcp.o) +tcp_poll ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) +tcp_process_refused_data ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(tcp_in.o) +tcp_recv ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) +tcp_recv_null ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(tcp_in.o) +tcp_recved ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) +tcp_rexmit ../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(tcp_in.o) +tcp_rexmit_fast ../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(tcp_in.o) +tcp_rexmit_rto ../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(tcp.o) +tcp_rst ../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(tcp.o) +tcp_seg_copy ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(tcp_in.o) +tcp_seg_free ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(tcp_out.o) +tcp_segs_free ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(pbuf.o) +tcp_send_empty_ack ../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(tcp_in.o) +tcp_send_fin ../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(tcp.o) +tcp_sent ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(hsCore.o) +tcp_setprio ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(hsCore.o) +tcp_shutdown ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(api_msg.o) +tcp_slowtmr ../..//econais/build/libwismart.a(tcp.o) +tcp_state_str ../..//econais/build/libwismart.a(tcp.o) +tcp_ticks ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(tcp_out.o) +tcp_timer_needed ../..//econais/build/libwismart.a(timers.o) + ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(tcp.o) +tcp_tmp_pcb ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(tcp_in.o) +tcp_tmr ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(netconf.o) +tcp_tw_pcbs ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(tcp_in.o) + ../..//econais/build/libwismart.a(timers.o) +tcp_update_rcv_ann_wnd ../..//econais/build/libwismart.a(tcp.o) + ../..//econais/build/libwismart.a(tcp_in.o) +tcp_write ../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_core.o) +tcp_zero_window_probe ../..//econais/build/libwismart.a(tcp_out.o) + ../..//econais/build/libwismart.a(tcp.o) +tcpip_apimsg ../..//econais/build/libwismart.a(tcpip.o) + ../..//econais/build/libwismart.a(api_lib.o) +tcpip_callback_with_block ../..//econais/build/libwismart.a(tcpip.o) + ../..//econais/build/libwismart.a(api_lib.o) + ../..//econais/build/libwismart.a(sockets.o) + ../..//econais/build/libwismart.a(pbuf.o) +tcpip_callbackmsg_delete ../..//econais/build/libwismart.a(tcpip.o) +tcpip_callbackmsg_new ../..//econais/build/libwismart.a(tcpip.o) +tcpip_init ../..//econais/build/libwismart.a(tcpip.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) +tcpip_input ../..//econais/build/libwismart.a(tcpip.o) +tcpip_output ../..//econais/build/libwismart.a(wifi_engine.o) +tcpip_timeout ../..//econais/build/libwismart.a(tcpip.o) +tcpip_trycallback ../..//econais/build/libwismart.a(tcpip.o) +tcpip_untimeout ../..//econais/build/libwismart.a(tcpip.o) +testFileCb ../..//econais/build/libwismart.a(upnp_configurationServer.o) +ticks ../..//econais/build/libwismart.a(libwismart_lwip.o) +tim_timestamp ../..//econais/build/libwismart.a(wifi_softap.o) +tls_alert ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tlsv1_client_write.o) + ../..//econais/build/libwismart.a(tlsv1_client_read.o) +tls_capabilities ../..//econais/build/libwismart.a(tls_internal.o) +tls_connection_client_hello_ext ../..//econais/build/libwismart.a(tls_internal.o) +tls_connection_decrypt ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) +tls_connection_deinit ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) +tls_connection_enable_workaround ../..//econais/build/libwismart.a(tls_internal.o) +tls_connection_encrypt ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) +tls_connection_established ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_tls.o) +tls_connection_get_failed ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) +tls_connection_get_keyblock_size ../..//econais/build/libwismart.a(tls_internal.o) +tls_connection_get_keys ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) +tls_connection_get_read_alerts ../..//econais/build/libwismart.a(tls_internal.o) +tls_connection_get_write_alerts ../..//econais/build/libwismart.a(tls_internal.o) +tls_connection_handshake ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) +tls_connection_init ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) +tls_connection_prf ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) +tls_connection_resumed ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_ttls.o) +tls_connection_server_handshake ../..//econais/build/libwismart.a(tls_internal.o) +tls_connection_set_cipher_list ../..//econais/build/libwismart.a(tls_internal.o) +tls_connection_set_params ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) +tls_connection_set_session_ticket_cb ../..//econais/build/libwismart.a(tls_internal.o) +tls_connection_set_verify ../..//econais/build/libwismart.a(tls_internal.o) +tls_connection_shutdown ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) +tls_deinit ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(eap.o) +tls_derive_keys ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tlsv1_client_write.o) + ../..//econais/build/libwismart.a(tlsv1_client_read.o) +tls_derive_pre_master_secret ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tlsv1_client_write.o) +tls_get_cipher ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) +tls_get_cipher_data ../..//econais/build/libwismart.a(tlsv1_common.o) + ../..//econais/build/libwismart.a(tlsv1_record.o) +tls_get_cipher_suite ../..//econais/build/libwismart.a(tlsv1_common.o) + ../..//econais/build/libwismart.a(tlsv1_record.o) + ../..//econais/build/libwismart.a(tlsv1_client_write.o) + ../..//econais/build/libwismart.a(tlsv1_client_read.o) +tls_get_errors ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) +tls_global_set_params ../..//econais/build/libwismart.a(tls_internal.o) +tls_global_set_verify ../..//econais/build/libwismart.a(tls_internal.o) +tls_init ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(eap.o) +tls_parse_cert ../..//econais/build/libwismart.a(tlsv1_common.o) + ../..//econais/build/libwismart.a(tlsv1_client_read.o) +tls_prf ../..//econais/build/libwismart.a(sha1-tlsprf.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(tlsv1_client_write.o) + ../..//econais/build/libwismart.a(tlsv1_client_read.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) +tls_send_client_hello ../..//econais/build/libwismart.a(tlsv1_client_write.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) +tls_server_key_exchange_allowed ../..//econais/build/libwismart.a(tlsv1_common.o) + ../..//econais/build/libwismart.a(tlsv1_client_read.o) +tls_verify_hash_add ../..//econais/build/libwismart.a(tlsv1_common.o) + ../..//econais/build/libwismart.a(tlsv1_client_write.o) + ../..//econais/build/libwismart.a(tlsv1_client_read.o) +tls_verify_hash_free ../..//econais/build/libwismart.a(tlsv1_common.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) +tls_verify_hash_init ../..//econais/build/libwismart.a(tlsv1_common.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) +tlsv1_client_decrypt ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_client_deinit ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_client_encrypt ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_client_established ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_client_free_dh ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tlsv1_client_write.o) + ../..//econais/build/libwismart.a(tlsv1_client_read.o) +tlsv1_client_get_cipher ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_client_get_keyblock_size ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_client_get_keys ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_client_global_deinit ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_client_global_init ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_client_handshake ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_client_handshake_write ../..//econais/build/libwismart.a(tlsv1_client_write.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) +tlsv1_client_hello_ext ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_client_init ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_client_prf ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_client_process_handshake ../..//econais/build/libwismart.a(tlsv1_client_read.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) +tlsv1_client_resumed ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_client_send_alert ../..//econais/build/libwismart.a(tlsv1_client_write.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) +tlsv1_client_set_cipher_list ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_client_set_cred ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_client_set_session_ticket_cb ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_client_set_time_checks ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_client_shutdown ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_cred_alloc ../..//econais/build/libwismart.a(tlsv1_cred.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_cred_free ../..//econais/build/libwismart.a(tlsv1_cred.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_record_change_read_cipher ../..//econais/build/libwismart.a(tlsv1_record.o) + ../..//econais/build/libwismart.a(tlsv1_client_read.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) +tlsv1_record_change_write_cipher ../..//econais/build/libwismart.a(tlsv1_record.o) + ../..//econais/build/libwismart.a(tlsv1_client_write.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) +tlsv1_record_receive ../..//econais/build/libwismart.a(tlsv1_record.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) +tlsv1_record_send ../..//econais/build/libwismart.a(tlsv1_record.o) + ../..//econais/build/libwismart.a(tlsv1_client_write.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) +tlsv1_record_set_cipher_suite ../..//econais/build/libwismart.a(tlsv1_record.o) + ../..//econais/build/libwismart.a(tlsv1_client_read.o) + ../..//econais/build/libwismart.a(tlsv1_client.o) +tlsv1_set_ca_cert ../..//econais/build/libwismart.a(tlsv1_cred.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_set_cert ../..//econais/build/libwismart.a(tlsv1_cred.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_set_dhparams ../..//econais/build/libwismart.a(tlsv1_cred.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tlsv1_set_private_key ../..//econais/build/libwismart.a(tlsv1_cred.o) + ../..//econais/build/libwismart.a(tls_internal.o) +tmpCC4 ../..//econais/build/libwismart.a(rtc.o) +trace_mask ../..//econais/build/libwismart.a(debug.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(pmksa_cache.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(libwismart_softap.o) + ../..//econais/build/libwismart.a(ethernetif.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(os_wifiengine.o) + ../..//econais/build/libwismart.a(driver_wifiengine.o) + ../..//econais/build/libwismart.a(config_wifiengine.o) + ../..//econais/build/libwismart.a(stm32_eeprom.o) + ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(rtc.o) + ../..//econais/build/libwismart.a(timer_events.o) + ../..//econais/build/libwismart.a(roam.o) + ../..//econais/build/libwismart.a(mibs.o) + ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_ps.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(dhcpserver.o) + ../..//econais/build/libwismart.a(netconf.o) + ../..//econais/build/libwismart.a(libwismart_lwip.o) + ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(libwismart_uart.o) + ../..//econais/build/libwismart.a(libwismart_power.o) + ../..//econais/build/libwismart.a(libwismart_scan.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) + ../..//econais/build/libwismart.a(libwismart.o) +transport_actions ../..//econais/build/libwismart.a(upnp_avTransport.o) +tx_fails ../..//econais/build/libwismart.a(libwismart.o) +udp_bind ../..//econais/build/libwismart.a(udp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(dns.o) + ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(dhcpserver.o) +udp_connect ../..//econais/build/libwismart.a(udp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(dns.o) + ../..//econais/build/libwismart.a(dhcp.o) +udp_disconnect ../..//econais/build/libwismart.a(udp.o) + ../..//econais/build/libwismart.a(api_msg.o) +udp_init ../..//econais/build/libwismart.a(udp.o) + ../..//econais/build/libwismart.a(init.o) +udp_input ../..//econais/build/libwismart.a(udp.o) + ../..//econais/build/libwismart.a(ip.o) +udp_new ../..//econais/build/libwismart.a(udp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(dns.o) + ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(dhcpserver.o) +udp_pcbs ../..//econais/build/libwismart.a(udp.o) +udp_recv ../..//econais/build/libwismart.a(udp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(dns.o) + ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(dhcpserver.o) +udp_remove ../..//econais/build/libwismart.a(udp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(dhcp.o) +udp_send ../..//econais/build/libwismart.a(udp.o) + ../..//econais/build/libwismart.a(api_msg.o) +udp_sendto ../..//econais/build/libwismart.a(udp.o) + ../..//econais/build/libwismart.a(api_msg.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(dns.o) +udp_sendto_if ../..//econais/build/libwismart.a(udp.o) + ../..//econais/build/libwismart.a(dhcp.o) + ../..//econais/build/libwismart.a(dhcpserver.o) +ungetc c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-ungetc.o) +upnpControlInvalidActionResponseBody ../..//econais/build/libwismart.a(upnp_control.o) +upnpControlTask ../..//econais/build/libwismart.a(upnp_control.o) +upnpControl_buildReponseHeader ../..//econais/build/libwismart.a(upnp_control.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +upnpControl_buildResponseBody ../..//econais/build/libwismart.a(upnp_control.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) +upnpControl_callSoapAction ../..//econais/build/libwismart.a(upnp_control.o) +upnpControl_handleRequest ../..//econais/build/libwismart.a(upnp_control.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) +upnpDebugDisable ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(libwismart.o) +upnpDebugEnable ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(libwismart.o) +upnpDebugMsgsOnOff ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(upnp_description.o) + ../..//econais/build/libwismart.a(upnp_dmsConnectionManager.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(upnp_control.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_avTransport.o) + ../..//econais/build/libwismart.a(upnp_connectionManager.o) + ../..//econais/build/libwismart.a(upnp_renderingControl.o) +upnpDescription_AVT_Description_Xml ../..//econais/build/libwismart.a(upnp_description.o) +upnpDescription_CM_Description_Xml ../..//econais/build/libwismart.a(upnp_description.o) +upnpDescription_DMS_CD_XML ../..//econais/build/libwismart.a(upnp_description.o) +upnpDescription_DMS_CM_XML ../..//econais/build/libwismart.a(upnp_description.o) +upnpDescription_DMS_ROOT_XML ../..//econais/build/libwismart.a(upnp_description.o) +upnpDescription_DeviceDescription_Xml ../..//econais/build/libwismart.a(upnp_description.o) +upnpDescription_RC_Description_Xml ../..//econais/build/libwismart.a(upnp_description.o) +upnpDescription_handleRequest ../..//econais/build/libwismart.a(upnp_description.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) +upnpDevicesList ../..//econais/build/libwismart.a(upnp_devices.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_core.o) +upnpDmsIsEnabled ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(upnp_description.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_serviceOperations.o) +upnpElapsedTime ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) +upnpEnableDms ../..//econais/build/libwismart.a(upnp_core.o) +upnpEnterConfigurationMode ../..//econais/build/libwismart.a(upnp_configurationServer.o) + ../..//econais/build/libwismart.a(libwismart.o) +upnpGetLocalIp ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) +upnpHttpServer ../..//econais/build/libwismart.a(upnp_httpServer.o) +upnpHttpServerDynamicContentCb ../..//econais/build/libwismart.a(upnp_httpServer.o) +upnpHttpServerEl ../..//econais/build/libwismart.a(upnp_httpServer.o) +upnpHttpServerEs ../..//econais/build/libwismart.a(upnp_httpServer.o) +upnpHttpServerPacketReceivedCb ../..//econais/build/libwismart.a(upnp_httpServer.o) +upnpHttpServerPacketReceivedEv ../..//econais/build/libwismart.a(upnp_httpServer.o) +upnpHttpServerPlaybackFinishedEvent ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(dlnaAppLinking.o) +upnpHttpServerProcess ../..//econais/build/libwismart.a(upnp_httpServer.o) +upnpHttpServerRequestCb ../..//econais/build/libwismart.a(upnp_httpServer.o) +upnpHttpServerThread ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(upnp_core.o) +upnpHttpServerThreadPtr ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) +upnpHttpServerWaitEventsMask ../..//econais/build/libwismart.a(upnp_httpServer.o) +upnpInited ../..//econais/build/libwismart.a(upnp_core.o) +upnpNetworkInit ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(libwismart.o) +upnpNotifyingInited ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifyingNewTaskEvent ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifyingServerPtr ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifyingTask ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifyingThread ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_core.o) +upnpNotifyingUsedConnections ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifyingWaitEventsMask ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_addTask ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) +upnpNotifying_allocConnectionHandler ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_buildNotifyBody ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_connectionErrorCb ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_connectionEstablishedCb ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_connectionEstablishmentErrorCb ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_connectionPollCb ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_dataReceivedCb ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_deallocConnectionHandler ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_establishConnection ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_init ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_isResponseReceived ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_newTaskEvent ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_process ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_processConnectedTask ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_processConnectingTask ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_processDisconnectedTask ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_processDisconnectingTask ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_processReadyTask ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_processRequest ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_responseCodeIsOk ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpNotifying_waitForNewTasks ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpSetMediaRendererInfo ../..//econais/build/libwismart.a(upnp_mediaRenderer.o) + ../..//econais/build/libwismart.a(upnp_core.o) +upnpSetMediaServerInfo ../..//econais/build/libwismart.a(upnp_mediaServer.o) + ../..//econais/build/libwismart.a(upnp_core.o) +upnpSsdpServerActiveDiscoveryState ../..//econais/build/libwismart.a(upnp_ssdpServer.o) +upnpSsdpServerConnection ../..//econais/build/libwismart.a(upnp_ssdpServer.o) +upnpSsdpServerInited ../..//econais/build/libwismart.a(upnp_ssdpServer.o) +upnpSsdpServerSsdpTask ../..//econais/build/libwismart.a(upnp_ssdpServer.o) +upnpSsdpServer_addTask ../..//econais/build/libwismart.a(upnp_ssdpServer.o) +upnpSsdpServer_handlePassiveDiscoveryPacket ../..//econais/build/libwismart.a(upnp_ssdpServer.o) +upnpSsdpServer_init ../..//econais/build/libwismart.a(upnp_ssdpServer.o) +upnpSsdpServer_passiveDiscoveryReply ../..//econais/build/libwismart.a(upnp_ssdpServer.o) +upnpSsdpServer_process ../..//econais/build/libwismart.a(upnp_ssdpServer.o) +upnpSsdpServer_processActiveDiscovery ../..//econais/build/libwismart.a(upnp_ssdpServer.o) +upnpSsdpServer_processActiveDiscovery2 ../..//econais/build/libwismart.a(upnp_ssdpServer.o) +upnpSsdpServer_processPassiveDiscovery ../..//econais/build/libwismart.a(upnp_ssdpServer.o) +upnpSsdpServer_sendPacket ../..//econais/build/libwismart.a(upnp_ssdpServer.o) +upnpSsdpServer_sendSsdpPacket ../..//econais/build/libwismart.a(upnp_ssdpServer.o) +upnpSsdpServer_sleep ../..//econais/build/libwismart.a(upnp_ssdpServer.o) +upnpSssdpServer_ssdpDataReceivedCb ../..//econais/build/libwismart.a(upnp_ssdpServer.o) +upnpStackInit ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(libwismart.o) +upnpSubscriptionInited ../..//econais/build/libwismart.a(upnp_subscription.o) +upnpSubscriptionLock ../..//econais/build/libwismart.a(upnp_subscription.o) +upnpSubscriptionLockInit ../..//econais/build/libwismart.a(upnp_subscription.o) +upnpSubscriptionTask ../..//econais/build/libwismart.a(upnp_subscription.o) +upnpSubscriptionUnlock ../..//econais/build/libwismart.a(upnp_subscription.o) +upnpSubscription_allocSubscriber ../..//econais/build/libwismart.a(upnp_subscription.o) +upnpSubscription_decreaseTimeout ../..//econais/build/libwismart.a(upnp_subscription.o) +upnpSubscription_freeSubscriber ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpSubscription_generateUuid ../..//econais/build/libwismart.a(upnp_subscription.o) +upnpSubscription_getAndUpdateSubscriberUneventedVarsMask ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpSubscription_getServiceUrl ../..//econais/build/libwismart.a(upnp_subscription.o) +upnpSubscription_handleSubscribeRequest ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) +upnpSubscription_handleUnsubscribeRequest ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) +upnpSubscription_init ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) +upnpSubscription_notifySubscriber ../..//econais/build/libwismart.a(upnp_subscription.o) +upnpSubscription_printSubscriber ../..//econais/build/libwismart.a(upnp_subscription.o) +upnpSubscription_printSubscriberList ../..//econais/build/libwismart.a(upnp_subscription.o) +upnpSubscription_process ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) +upnpSubscription_psTime ../..//econais/build/libwismart.a(upnp_subscription.o) +upnpSubscription_rnd ../..//econais/build/libwismart.a(upnp_subscription.o) +upnpSubscription_stateVariableChanged ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(upnp_avTransport.o) + ../..//econais/build/libwismart.a(upnp_renderingControl.o) +upnpSubscription_subscriberRef ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) +upnpSubscription_updateSubscriberUneventedVarsMask ../..//econais/build/libwismart.a(upnp_subscription.o) +upnpSubscription_updateTimeout ../..//econais/build/libwismart.a(upnp_subscription.o) +upnpTcpConnectionWrite ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) +upnp_getActionId ../..//econais/build/libwismart.a(upnp_serviceOperations.o) + ../..//econais/build/libwismart.a(upnp_control.o) +upnp_getServicePtrFromControlUrl ../..//econais/build/libwismart.a(upnp_serviceOperations.o) + ../..//econais/build/libwismart.a(upnp_control.o) +upnp_getServicePtrFromEventUrl ../..//econais/build/libwismart.a(upnp_serviceOperations.o) +upnp_getServiceVariableValue ../..//econais/build/libwismart.a(upnp_serviceOperations.o) + ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(upnp_avTransport.o) + ../..//econais/build/libwismart.a(upnp_renderingControl.o) +upnp_getXmlElementValue ../..//econais/build/libwismart.a(upnp_serviceOperations.o) +upnp_getXmlElementValueFromPbufChain ../..//econais/build/libwismart.a(upnp_serviceOperations.o) + ../..//econais/build/libwismart.a(upnp_dmsContentDirectorySupport.o) + ../..//econais/build/libwismart.a(upnp_avTransport.o) + ../..//econais/build/libwismart.a(upnp_renderingControl.o) +upnp_mediaRendererDevice ../..//econais/build/libwismart.a(upnp_mediaRenderer.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(upnp_core.o) +upnp_mediaRendererDeviceServices ../..//econais/build/libwismart.a(upnp_mediaRenderer.o) +upnp_mediaServerDevice ../..//econais/build/libwismart.a(upnp_mediaServer.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(upnp_core.o) +upnp_mediaServerDeviceServices ../..//econais/build/libwismart.a(upnp_mediaServer.o) +upnp_setServiceVariableValue ../..//econais/build/libwismart.a(upnp_serviceOperations.o) + ../..//econais/build/libwismart.a(dlnaAppLinking.o) + ../..//econais/build/libwismart.a(upnp_avTransport.o) + ../..//econais/build/libwismart.a(upnp_renderingControl.o) +urlEncodingTable ../..//econais/build/libwismart.a(hsCore.o) +uuid_bin2str ../..//econais/build/libwismart.a(uuid.o) + ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +uuid_gen_mac_addr ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +uuid_str2bin ../..//econais/build/libwismart.a(uuid.o) + ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) +vfiprintf c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vfiprintf.o) +vfprintf c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vfprintf.o) +vfprintf_UART_SendCharIrq ../..//econais/build/libwismart.a(libwismart_uart.o) + ../..//econais/build/libwismart.a(print.o) +volume ../..//econais/build/libwismart.a(upnp_renderingControl.o) +volumeLevel ../..//econais/build/libwismart.a(upnp_renderingControl.o) +vsnprintf c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-vsnprintf.o) + ../..//econais/build/libwismart.a(wpabuf.o) + ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(eapol_auth_sm.o) +vtlist build/obj/chvt.o + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) + ../..//econais/build/libwismart.a(hsCore.o) + ../..//econais/build/libwismart.a(upnp_notifying.o) + ../..//econais/build/libwismart.a(upnp_subscription.o) + ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(sys_arch.o) + ../..//econais/build/libwismart.a(timer_events.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(transport.o) + ../..//econais/build/libwismart.a(libwismart_power.o) + build/obj/chthreads.o + build/obj/chsys.o +wa_cmd_flow_check_thread ../..//econais/build/libwismart.a(wifi_cmds_flow.o) +wa_lwip_thread ../..//econais/build/libwismart.a(libwismart_lwip.o) +wcrtomb c:/yagarto/bin/../lib/gcc/arm-none-eabi/4.7.2/../../../../arm-none-eabi/lib/thumb/v7m\libc.a(lib_a-wcrtomb.o) +webServerDynamicContentCb ../..//econais/build/libwismart.a(upnp_configurationServer.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) +webServerRequestCb ../..//econais/build/libwismart.a(upnp_configurationServer.o) + ../..//econais/build/libwismart.a(upnp_description.o) +wei_get_mib_object ../..//econais/build/libwismart.a(mibs.o) +wei_handle_mlme_p2p_frame_ind ../..//econais/build/libwismart.a(wifi_softap.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +wei_update_rate_table ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +wifi_ConnectedBssIsAvailable ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(libwismart.o) +wifi_DisableConnectedBss ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +wifi_JoinWithOldBSS ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(libwismart.o) +wifi_PsDisable ../..//econais/build/libwismart.a(wifi_ps.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +wifi_PsDisableRF ../..//econais/build/libwismart.a(wifi_ps.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +wifi_PsEnable ../..//econais/build/libwismart.a(wifi_ps.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_engine.o) +wifi_PsEnableRF ../..//econais/build/libwismart.a(wifi_ps.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +wifi_ResetConnectedBss ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(wifi_scan.o) +wifi_adhoc_cb ../..//econais/build/libwismart.a(libwismart_cm.o) +wifi_arp_filter_forward_all ../..//econais/build/libwismart.a(wifi_filter.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +wifi_arp_filter_init ../..//econais/build/libwismart.a(wifi_filter.o) + ../..//econais/build/libwismart.a(wifi_engine.o) +wifi_arp_filter_set_ip ../..//econais/build/libwismart.a(wifi_filter.o) + ../..//econais/build/libwismart.a(netconf.o) +wifi_cmds_flow_data_release ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(transport.o) +wifi_cmds_flow_data_request ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_transport.o) + ../..//econais/build/libwismart.a(transport.o) +wifi_cmds_flow_init ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_engine.o) +wifi_cmds_flow_is_blocked ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_engine.o) +wifi_cmds_flow_mgmt_release ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(transport.o) +wifi_cmds_flow_mgmt_request ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(transport.o) +wifi_cmds_flow_reset_fw ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +wifi_connect_cb ../..//econais/build/libwismart.a(libwismart_cm.o) +wifi_filter_allow_packet ../..//econais/build/libwismart.a(wifi_filter.o) + ../..//econais/build/libwismart.a(transport.o) +wifi_filter_parse_hic ../..//econais/build/libwismart.a(wifi_filter.o) + ../..//econais/build/libwismart.a(transport.o) +wifi_filter_parse_packet ../..//econais/build/libwismart.a(wifi_filter.o) + ../..//econais/build/libwismart.a(transport.o) +wifi_get_mib ../..//econais/build/libwismart.a(mibs.o) +wifi_get_padding_len ../..//econais/build/libwismart.a(mibs.o) + ../..//econais/build/libwismart.a(driver_wifiengine.o) + ../..//econais/build/libwismart.a(wifi_engine.o) +wifi_get_raw_mib ../..//econais/build/libwismart.a(mibs.o) + ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(libwismart.o) +wifi_multicast_list_add ../..//econais/build/libwismart.a(wifi_filter.o) + ../..//econais/build/libwismart.a(netconf.o) +wifi_multicast_list_init ../..//econais/build/libwismart.a(wifi_filter.o) + ../..//econais/build/libwismart.a(wifi_engine.o) +wifi_multicast_list_remove ../..//econais/build/libwismart.a(wifi_filter.o) + ../..//econais/build/libwismart.a(netconf.o) +wifi_multicast_update_fw ../..//econais/build/libwismart.a(wifi_filter.o) + ../..//econais/build/libwismart.a(wifi_engine.o) +wifi_power_mgmt_cfm ../..//econais/build/libwismart.a(wifi_ps.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +wifi_ps_sem_init ../..//econais/build/libwismart.a(wifi_ps.o) + ../..//econais/build/libwismart.a(wifi_engine.o) +wifi_ps_unlock ../..//econais/build/libwismart.a(wifi_ps.o) +wifi_recover_end ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(libwismart.o) +wifi_recover_start ../..//econais/build/libwismart.a(wifi_cmds_flow.o) + ../..//econais/build/libwismart.a(libwismart.o) +wifi_registryFile ../..//econais/build/libwismart.a(stm32_eeprom.o) +wifi_release_resource_hic ../..//econais/build/libwismart.a(wifi_ps.o) + ../..//econais/build/libwismart.a(transport.o) +wifi_request_resource_hic ../..//econais/build/libwismart.a(wifi_ps.o) + ../..//econais/build/libwismart.a(wifi_engine.o) + ../..//econais/build/libwismart.a(transport.o) +wifi_roam_complete ../..//econais/build/libwismart.a(roam.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +wifi_roam_get_bg_scan_time ../..//econais/build/libwismart.a(roam.o) + ../..//econais/build/libwismart.a(libwismart.o) +wifi_roam_get_state ../..//econais/build/libwismart.a(roam.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +wifi_roam_init ../..//econais/build/libwismart.a(roam.o) + ../..//econais/build/libwismart.a(wifi_engine.o) +wifi_roam_set_bg_scan_time ../..//econais/build/libwismart.a(roam.o) + ../..//econais/build/libwismart.a(libwismart.o) +wifi_scan_dec_bss_count ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +wifi_scan_handle_add_scanjob_cfm ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +wifi_scan_handle_ind ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +wifi_scan_handle_scan_complete_ind ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +wifi_scan_init ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(libwismart.o) +wifi_scan_is_candidate_available ../..//econais/build/libwismart.a(wifi_scan.o) +wifi_scan_is_exist_better ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +wifi_scan_list_reset ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_engine.o) +wifi_scan_remove ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +wifi_scan_remove_current ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +wifi_scan_request ../..//econais/build/libwismart.a(wifi_scan.o) + ../..//econais/build/libwismart.a(roam.o) + ../..//econais/build/libwismart.a(libwismart_scan.o) +wifi_scan_result_cb ../..//econais/build/libwismart.a(libwismart_scan.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +wifi_wakeup_cb ../..//econais/build/libwismart.a(wifi_ps.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +wismartConnectedEvent ../..//econais/build/libwismart.a(upnp_core.o) + ../..//econais/build/libwismart.a(upnp_ssdpServer.o) + ../..//econais/build/libwismart.a(upnp_httpServer.o) +wpa_add_kde ../..//econais/build/libwismart.a(wpa_auth_ie.o) + ../..//econais/build/libwismart.a(wpa_auth.o) +wpa_ap_assoc_event ../..//econais/build/libwismart.a(main_wifiengine.o) + ../..//econais/build/libwismart.a(wifi_softap.o) +wpa_ap_deauth_event ../..//econais/build/libwismart.a(main_wifiengine.o) + ../..//econais/build/libwismart.a(wifi_softap.o) +wpa_ap_disassoc_event ../..//econais/build/libwismart.a(main_wifiengine.o) +wpa_assoc_event ../..//econais/build/libwismart.a(main_wifiengine.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +wpa_auth_countermeasures_start ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(tkip_countermeasures.o) +wpa_auth_eapol_key_tx_status ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +wpa_auth_for_each_auth ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(wpa_auth_ie.o) +wpa_auth_for_each_sta ../..//econais/build/libwismart.a(wpa_auth.o) +wpa_auth_gen_wpa_ie ../..//econais/build/libwismart.a(wpa_auth_ie.o) + ../..//econais/build/libwismart.a(wpa_auth.o) +wpa_auth_get_pairwise ../..//econais/build/libwismart.a(wpa_auth.o) +wpa_auth_get_wpa_ie ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) + ../..//econais/build/libwismart.a(hostapd.o) + ../..//econais/build/libwismart.a(ap.o) +wpa_auth_init ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) +wpa_auth_logger ../..//econais/build/libwismart.a(wpa_auth.o) +wpa_auth_pairwise_set ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +wpa_auth_pmksa_add ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +wpa_auth_pmksa_add_preauth ../..//econais/build/libwismart.a(wpa_auth.o) +wpa_auth_sm_event ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(drv_callbacks.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(hostapd.o) +wpa_auth_sm_notify ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +wpa_auth_sta_associated ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(hostapd.o) +wpa_auth_sta_clear_pmksa ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +wpa_auth_sta_deinit ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(sta_info.o) +wpa_auth_sta_get_pmksa ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +wpa_auth_sta_init ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(drv_callbacks.o) +wpa_auth_sta_key_mgmt ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +wpa_auth_sta_local_mic_failure_report ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(tkip_countermeasures.o) +wpa_auth_sta_no_wpa ../..//econais/build/libwismart.a(wpa_auth.o) +wpa_auth_sta_set_vlan ../..//econais/build/libwismart.a(wpa_auth.o) +wpa_auth_sta_wpa_version ../..//econais/build/libwismart.a(wpa_auth.o) +wpa_auth_uses_mfp ../..//econais/build/libwismart.a(wpa_auth_ie.o) +wpa_auth_vlogger ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(wpa_auth_ie.o) +wpa_blacklist_add ../..//econais/build/libwismart.a(blacklist.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_blacklist_clear ../..//econais/build/libwismart.a(blacklist.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_blacklist_del ../..//econais/build/libwismart.a(blacklist.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_blacklist_get ../..//econais/build/libwismart.a(blacklist.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_bss_deinit ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_bss_flush ../..//econais/build/libwismart.a(bss.o) +wpa_bss_flush_by_age ../..//econais/build/libwismart.a(bss.o) +wpa_bss_get ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +wpa_bss_get_bit_rates ../..//econais/build/libwismart.a(bss.o) +wpa_bss_get_bssid ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(events.o) +wpa_bss_get_id ../..//econais/build/libwismart.a(bss.o) +wpa_bss_get_ie ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_bss_get_max_rate ../..//econais/build/libwismart.a(bss.o) +wpa_bss_get_vendor_ie ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_bss_get_vendor_ie_multi ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +wpa_bss_init ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_bss_update_end ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(scan.o) +wpa_bss_update_scan_res ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(scan.o) +wpa_bss_update_start ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(scan.o) +wpa_cipher_txt ../..//econais/build/libwismart.a(wpa_common.o) + ../..//econais/build/libwismart.a(wpa.o) +wpa_clear_keys ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(events.o) +wpa_compare_rsn_ie ../..//econais/build/libwismart.a(wpa_common.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpa_auth.o) +wpa_config_add_network ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(main_wifiengine.o) + ../..//econais/build/libwismart.a(config_wifiengine.o) +wpa_config_add_prio_network ../..//econais/build/libwismart.a(config.o) +wpa_config_alloc_empty ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(config_wifiengine.o) +wpa_config_find_and_add_certificate ../..//econais/build/libwismart.a(config_wifiengine.o) +wpa_config_find_and_add_pkey ../..//econais/build/libwismart.a(config_wifiengine.o) +wpa_config_foreach_network ../..//econais/build/libwismart.a(config.o) +wpa_config_free ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_config_free_blob ../..//econais/build/libwismart.a(config.o) +wpa_config_free_ssid ../..//econais/build/libwismart.a(config.o) +wpa_config_get_blob ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(wpas_glue.o) +wpa_config_get_network ../..//econais/build/libwismart.a(config.o) +wpa_config_process_global ../..//econais/build/libwismart.a(config.o) +wpa_config_read ../..//econais/build/libwismart.a(config_wifiengine.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_config_remove_blob ../..//econais/build/libwismart.a(config.o) +wpa_config_remove_network ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(config_wifiengine.o) +wpa_config_set ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(config_wifiengine.o) +wpa_config_set_blob ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(config_wifiengine.o) +wpa_config_set_network_defaults ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(main_wifiengine.o) + ../..//econais/build/libwismart.a(config_wifiengine.o) +wpa_config_set_quoted ../..//econais/build/libwismart.a(config.o) +wpa_config_update_prio_list ../..//econais/build/libwismart.a(config.o) +wpa_config_update_psk ../..//econais/build/libwismart.a(config.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(config_wifiengine.o) +wpa_config_write ../..//econais/build/libwismart.a(config_wifiengine.o) + ../..//econais/build/libwismart.a(wpas_glue.o) +wpa_debug_level ../..//econais/build/libwismart.a(wpa_debug.o) + ../..//econais/build/libwismart.a(hostapd.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_debug_show_keys ../..//econais/build/libwismart.a(wpa_debug.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_debug_timestamp ../..//econais/build/libwismart.a(wpa_debug.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_deinit ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) + ../..//econais/build/libwismart.a(hostapd.o) +wpa_disconnect ../..//econais/build/libwismart.a(main_wifiengine.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +wpa_driver_WE_deinit ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_get_bssid ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_get_noa ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_get_scan_results ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_get_ssid ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_group_mic_failure ../..//econais/build/libwismart.a(main_wifiengine.o) +wpa_driver_WE_hapd_get_ssid ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_hapd_send_eapol ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_hapd_set_ssid ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_init ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_ops ../..//econais/build/libwismart.a(driver_wifiengine.o) + ../..//econais/build/libwismart.a(drivers.o) +wpa_driver_WE_p2p_connect ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_p2p_find ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_p2p_group_formation_failed ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_p2p_listen ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_p2p_prov_disc_req ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_p2p_sd_request ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_p2p_sd_response ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_p2p_service_update ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_p2p_set_params ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_p2p_stop_find ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_pairwise_mic_failure ../..//econais/build/libwismart.a(main_wifiengine.o) +wpa_driver_WE_scan ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_scan2 ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_sched_scan ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_send_action ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_send_ft_action ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_set_bssid ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_set_freq ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_set_generic_elem ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_set_key ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_set_noa ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_set_p2p_powersave ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_set_supp_port ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_sta_set_flags ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_driver_WE_wps_success_cb ../..//econais/build/libwismart.a(driver_wifiengine.o) +wpa_drivers ../..//econais/build/libwismart.a(drivers.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_eapol_handler ../..//econais/build/libwismart.a(main_wifiengine.o) + ../..//econais/build/libwismart.a(wifi_mlme_handler.o) +wpa_eapol_key_mic ../..//econais/build/libwismart.a(wpa_common.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpa_auth.o) +wpa_eapol_key_send ../..//econais/build/libwismart.a(wpa.o) +wpa_gen_wpa_ie ../..//econais/build/libwismart.a(wpa_ie.o) + ../..//econais/build/libwismart.a(wpa.o) +wpa_get_mib ../..//econais/build/libwismart.a(wpa_auth.o) +wpa_get_mib_sta ../..//econais/build/libwismart.a(wpa_auth.o) +wpa_get_ntp_timestamp ../..//econais/build/libwismart.a(common.o) + ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +wpa_gtk_rekey ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(tkip_countermeasures.o) +wpa_handlers ../..//econais/build/libwismart.a(main_wifiengine.o) +wpa_has_be_init ../..//econais/build/libwismart.a(libwismart.o) +wpa_init ../..//econais/build/libwismart.a(main_wifiengine.o) + ../..//econais/build/libwismart.a(libwismart.o) +wpa_init_keys ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(hostapd.o) +wpa_key_mgmt_txt ../..//econais/build/libwismart.a(wpa_common.o) + ../..//econais/build/libwismart.a(wpa.o) +wpa_parse_kde_ies ../..//econais/build/libwismart.a(wpa_auth_ie.o) + ../..//econais/build/libwismart.a(wpa_auth.o) +wpa_parse_wpa_ie ../..//econais/build/libwismart.a(wpa_ie.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(preauth.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_parse_wpa_ie_rsn ../..//econais/build/libwismart.a(wpa_common.o) + ../..//econais/build/libwismart.a(wpa_ie.o) + ../..//econais/build/libwismart.a(wpa_auth_ie.o) +wpa_parse_wpa_ie_wpa ../..//econais/build/libwismart.a(wpa_common.o) + ../..//econais/build/libwismart.a(wpa_ie.o) + ../..//econais/build/libwismart.a(wpa_auth_ie.o) +wpa_pmk_to_ptk ../..//econais/build/libwismart.a(wpa_common.o) + ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpa_auth.o) +wpa_receive ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) +wpa_reconfig ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(wpa_auth_glue.o) +wpa_remove_ptk ../..//econais/build/libwismart.a(wpa_auth.o) + ../..//econais/build/libwismart.a(ap_mlme.o) +wpa_scan_get_ie ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(bss.o) +wpa_scan_get_vendor_ie ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(bss.o) +wpa_scan_get_vendor_ie_multi ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +wpa_scan_get_vendor_ie_multi_beacon ../..//econais/build/libwismart.a(scan.o) +wpa_scan_results_free ../..//econais/build/libwismart.a(driver_common.o) + ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(events.o) +wpa_set_ssid_eap ../..//econais/build/libwismart.a(config_wifiengine.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +wpa_set_ssid_psk ../..//econais/build/libwismart.a(config_wifiengine.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +wpa_set_wep_keys ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(events.o) +wpa_sm_aborted_cached ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpas_glue.o) +wpa_sm_deinit ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_sm_drop_sa ../..//econais/build/libwismart.a(wpa.o) +wpa_sm_get_param ../..//econais/build/libwismart.a(wpa.o) +wpa_sm_get_status ../..//econais/build/libwismart.a(wpa.o) +wpa_sm_has_ptk ../..//econais/build/libwismart.a(wpa.o) +wpa_sm_init ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpas_glue.o) +wpa_sm_key_request ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(events.o) +wpa_sm_notify_assoc ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(events.o) +wpa_sm_notify_disassoc ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_sm_parse_own_wpa_ie ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_sm_pmksa_cache_flush ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_sm_pmksa_cache_list ../..//econais/build/libwismart.a(wpa.o) +wpa_sm_rx_eapol ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_sm_set_ap_rsn_ie ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_sm_set_ap_wpa_ie ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_sm_set_assoc_wpa_ie ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_sm_set_assoc_wpa_ie_default ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_sm_set_config ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_sm_set_eapol ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_sm_set_fast_reauth ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_sm_set_ifname ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_sm_set_own_addr ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_sm_set_param ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_sm_set_pmk ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_sm_set_pmk_from_pmksa ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_sm_set_scard_ctx ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_sm_update_replay_ctr ../..//econais/build/libwismart.a(wpa.o) + ../..//econais/build/libwismart.a(events.o) +wpa_snprintf_hex ../..//econais/build/libwismart.a(common.o) + ../..//econais/build/libwismart.a(pmksa_cache.o) + ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wpa_snprintf_hex_uppercase ../..//econais/build/libwismart.a(common.o) +wpa_ssid_txt ../..//econais/build/libwismart.a(common.o) +wpa_supplicant_add_iface ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(main_wifiengine.o) +wpa_supplicant_ap_deinit ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_ap_mac_addr_filter ../..//econais/build/libwismart.a(ap.o) +wpa_supplicant_ap_pwd_auth_fail ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +wpa_supplicant_ap_rx_eapol ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_ap_update_beacon ../..//econais/build/libwismart.a(ap.o) +wpa_supplicant_ap_wps_cancel ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +wpa_supplicant_ap_wps_pbc ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(main_wifiengine.o) +wpa_supplicant_ap_wps_pin ../..//econais/build/libwismart.a(ap.o) +wpa_supplicant_associate ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(events.o) +wpa_supplicant_cancel_auth_timeout ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(events.o) +wpa_supplicant_cancel_scan ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_cancel_sched_scan ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_clear_status ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_connect ../..//econais/build/libwismart.a(events.o) +wpa_supplicant_create_ap ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(main_wifiengine.o) +wpa_supplicant_ctrl_req_from_string ../..//econais/build/libwismart.a(wpas_glue.o) +wpa_supplicant_ctrl_req_to_string ../..//econais/build/libwismart.a(wpas_glue.o) +wpa_supplicant_deauthenticate ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +wpa_supplicant_deinit ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(main_wifiengine.o) +wpa_supplicant_delayed_sched_scan ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_disable_network ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_disassociate ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(main_wifiengine.o) +wpa_supplicant_driver_init ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(events.o) +wpa_supplicant_enable_network ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_enabled_networks ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_event ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(main_wifiengine.o) +wpa_supplicant_get_eap_mode ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_get_iface ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_get_scan_results ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(events.o) +wpa_supplicant_get_ssid ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(events.o) +wpa_supplicant_init ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(main_wifiengine.o) +wpa_supplicant_init_eapol ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_init_wpa ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_initiate_eapol ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(events.o) +wpa_supplicant_license ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_mark_disassoc ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_notify_scanning ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_parse_ies ../..//econais/build/libwismart.a(wpa_ie.o) + ../..//econais/build/libwismart.a(wpa.o) +wpa_supplicant_reload_configuration ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_remove_iface ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_req_auth_timeout ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(events.o) +wpa_supplicant_req_scan ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_req_sched_scan ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(events.o) +wpa_supplicant_rsn_supp_set_config ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_run ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_rx_eapol ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(main_wifiengine.o) +wpa_supplicant_scard_init ../..//econais/build/libwismart.a(events.o) +wpa_supplicant_select_network ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_send_2_of_4 ../..//econais/build/libwismart.a(wpa.o) +wpa_supplicant_send_4_of_4 ../..//econais/build/libwismart.a(wpa.o) +wpa_supplicant_set_ap_scan ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_set_bss_expiration_age ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_set_bss_expiration_count ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_set_debug_params ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_set_non_wpa_policy ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(events.o) +wpa_supplicant_set_state ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(ap.o) +wpa_supplicant_set_suites ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(events.o) +wpa_supplicant_state_txt ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_stop_countermeasures ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_terminate_proc ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_trigger_scan ../..//econais/build/libwismart.a(scan.o) +wpa_supplicant_update_config ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_supplicant_update_mac_addr ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(events.o) +wpa_supplicant_update_scan_results ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(wpas_glue.o) + ../..//econais/build/libwismart.a(events.o) +wpa_supplicant_version ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpa_validate_wpa_ie ../..//econais/build/libwismart.a(wpa_auth_ie.o) + ../..//econais/build/libwismart.a(drv_callbacks.o) +wpa_wifiengine_config ../..//econais/build/libwismart.a(main_wifiengine.o) + ../..//econais/build/libwismart.a(config_wifiengine.o) +wpa_write_rsn_ie ../..//econais/build/libwismart.a(wpa_auth_ie.o) +wpabuf_alloc ../..//econais/build/libwismart.a(wpabuf.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(ieee802_11_shared.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(ieee802_11_common.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_common.o) + ../..//econais/build/libwismart.a(dh_groups.o) + ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(eap_server.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) +wpabuf_alloc_copy ../..//econais/build/libwismart.a(wpabuf.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpabuf_alloc_ext_data ../..//econais/build/libwismart.a(wpabuf.o) + ../..//econais/build/libwismart.a(tls_internal.o) +wpabuf_concat ../..//econais/build/libwismart.a(wpabuf.o) +wpabuf_dup ../..//econais/build/libwismart.a(wpabuf.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(eap_server.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wpabuf_free ../..//econais/build/libwismart.a(wpabuf.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(drv_callbacks.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap_tls.o) + ../..//econais/build/libwismart.a(eapol_supp_sm.o) + ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(dh_groups.o) + ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(eap_server.o) + ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(ieee802_1x.o) + ../..//econais/build/libwismart.a(sta_info.o) + ../..//econais/build/libwismart.a(hostapd.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpabuf_printf ../..//econais/build/libwismart.a(wpabuf.o) +wpabuf_put ../..//econais/build/libwismart.a(wpabuf.o) + ../..//econais/build/libwismart.a(eap_wsc_common.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(eap_peap.o) + ../..//econais/build/libwismart.a(eap_mschapv2.o) + ../..//econais/build/libwismart.a(eap_md5.o) + ../..//econais/build/libwismart.a(ieee802_11_shared.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_dev_attr.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(tls_internal.o) + ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(ieee802_11_common.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(eap_ttls.o) + ../..//econais/build/libwismart.a(eap.o) + ../..//econais/build/libwismart.a(eap_common.o) + ../..//econais/build/libwismart.a(dh_groups.o) + ../..//econais/build/libwismart.a(bss.o) + ../..//econais/build/libwismart.a(eap_server.o) + ../..//econais/build/libwismart.a(ap_drv_ops.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) +wpabuf_resize ../..//econais/build/libwismart.a(wpabuf.o) + ../..//econais/build/libwismart.a(eap_tls_common.o) + ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(ap_drv_ops.o) +wpabuf_zeropad ../..//econais/build/libwismart.a(wpabuf.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_attr_build.o) +wpas_ap_configured_cb ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(hostapd.o) +wpas_connection_failed ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(events.o) +wpas_driver_bss_selection ../..//econais/build/libwismart.a(wpa_supplicant.o) + ../..//econais/build/libwismart.a(events.o) +wpas_notify_ap_scan_changed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpas_notify_auth_changed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpas_notify_blob_added ../..//econais/build/libwismart.a(notify.o) +wpas_notify_blob_removed ../..//econais/build/libwismart.a(notify.o) +wpas_notify_bss_added ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(bss.o) +wpas_notify_bss_freq_changed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(bss.o) +wpas_notify_bss_ies_changed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(bss.o) +wpas_notify_bss_mode_changed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(bss.o) +wpas_notify_bss_privacy_changed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(bss.o) +wpas_notify_bss_rates_changed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(bss.o) +wpas_notify_bss_removed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(bss.o) +wpas_notify_bss_rsnie_changed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(bss.o) +wpas_notify_bss_signal_changed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(bss.o) +wpas_notify_bss_wpaie_changed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(bss.o) +wpas_notify_bss_wps_changed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(bss.o) +wpas_notify_bssid_changed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpas_notify_certification ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(wpas_glue.o) +wpas_notify_debug_level_changed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpas_notify_debug_show_keys_changed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpas_notify_debug_timestamp_changed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpas_notify_iface_added ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpas_notify_iface_removed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpas_notify_network_added ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpas_notify_network_changed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpas_notify_network_enabled_changed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpas_notify_network_removed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpas_notify_network_request ../..//econais/build/libwismart.a(notify.o) +wpas_notify_network_selected ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpas_notify_persistent_group_added ../..//econais/build/libwismart.a(notify.o) +wpas_notify_persistent_group_removed ../..//econais/build/libwismart.a(notify.o) +wpas_notify_resume ../..//econais/build/libwismart.a(notify.o) +wpas_notify_scan_done ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(events.o) +wpas_notify_scan_results ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(events.o) +wpas_notify_scanning ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(scan.o) +wpas_notify_sta_authorized ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(ap.o) +wpas_notify_state_changed ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpas_notify_supplicant_deinitialized ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpas_notify_supplicant_initialized ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpas_notify_suspend ../..//econais/build/libwismart.a(notify.o) +wpas_notify_wps_credential ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +wpas_notify_wps_event_fail ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +wpas_notify_wps_event_m2d ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +wpas_notify_wps_event_success ../..//econais/build/libwismart.a(notify.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +wpas_wps_ap_pin_disable ../..//econais/build/libwismart.a(ap.o) +wpas_wps_ap_pin_get ../..//econais/build/libwismart.a(ap.o) +wpas_wps_ap_pin_random ../..//econais/build/libwismart.a(ap.o) +wpas_wps_ap_pin_set ../..//econais/build/libwismart.a(ap.o) +wpas_wps_cancel ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(events.o) +wpas_wps_deinit ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpas_wps_eapol_cb ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wpas_glue.o) +wpas_wps_er_start ../..//econais/build/libwismart.a(wps_supplicant.o) +wpas_wps_er_stop ../..//econais/build/libwismart.a(wps_supplicant.o) +wpas_wps_get_req_type ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(scan.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpas_wps_in_progress ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(scan.o) +wpas_wps_init ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpas_wps_notify_scan_results ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(notify.o) +wpas_wps_scan_pbc_overlap ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(events.o) +wpas_wps_scan_result_text ../..//econais/build/libwismart.a(wps_supplicant.o) +wpas_wps_searching ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(events.o) +wpas_wps_ssid_bss_match ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(events.o) +wpas_wps_ssid_wildcard_ok ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(events.o) +wpas_wps_start_pbc ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(events.o) + ../..//econais/build/libwismart.a(main_wifiengine.o) +wpas_wps_start_pin ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(main_wifiengine.o) +wpas_wps_start_reg ../..//econais/build/libwismart.a(wps_supplicant.o) +wpas_wps_terminate_pending ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wpas_wps_update_config ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wps_ap_priority_compar ../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(scan.o) +wps_attr_text ../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +wps_authorized_macs ../..//econais/build/libwismart.a(wps_registrar.o) +wps_build_assoc_req_ie ../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(wpa_supplicant.o) +wps_build_assoc_resp_ie ../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(ap_drv_ops.o) +wps_build_assoc_state ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) +wps_build_auth_type_flags ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_build_authenticator ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_build_config_error ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) +wps_build_config_methods ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) +wps_build_conn_type_flags ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_build_cred ../..//econais/build/libwismart.a(wps_registrar.o) +wps_build_credential_wrap ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) +wps_build_dev_name ../..//econais/build/libwismart.a(wps_dev_attr.o) + ../..//econais/build/libwismart.a(wps.o) +wps_build_dev_password_id ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) +wps_build_device_attrs ../..//econais/build/libwismart.a(wps_dev_attr.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_build_encr_settings ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_build_encr_type_flags ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_build_enrollee_nonce ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_build_key_wrap_auth ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_build_manufacturer ../..//econais/build/libwismart.a(wps_dev_attr.o) + ../..//econais/build/libwismart.a(wps.o) +wps_build_model_name ../..//econais/build/libwismart.a(wps_dev_attr.o) + ../..//econais/build/libwismart.a(wps.o) +wps_build_model_number ../..//econais/build/libwismart.a(wps_dev_attr.o) + ../..//econais/build/libwismart.a(wps.o) +wps_build_msg_type ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_build_os_version ../..//econais/build/libwismart.a(wps_dev_attr.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_build_primary_dev_type ../..//econais/build/libwismart.a(wps_dev_attr.o) + ../..//econais/build/libwismart.a(wps.o) +wps_build_probe_req_ie ../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(scan.o) +wps_build_public_key ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_build_registrar_nonce ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_build_req_dev_type ../..//econais/build/libwismart.a(wps_dev_attr.o) + ../..//econais/build/libwismart.a(wps.o) +wps_build_req_type ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps.o) +wps_build_resp_type ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) +wps_build_rf_bands ../..//econais/build/libwismart.a(wps_dev_attr.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) +wps_build_secondary_dev_type ../..//econais/build/libwismart.a(wps_dev_attr.o) + ../..//econais/build/libwismart.a(wps.o) +wps_build_uuid_e ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) +wps_build_vendor_ext ../..//econais/build/libwismart.a(wps_dev_attr.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_build_version ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) +wps_build_wfa_ext ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) +wps_build_wsc_ack ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_build_wsc_nack ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_config_methods_str2bin ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +wps_decrypt_encr_settings ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_deinit ../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(eap_wsc.o) +wps_derive_keys ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_derive_psk ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_dev_type_bin2str ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) +wps_dev_type_str2bin ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(config.o) +wps_device_data_dup ../..//econais/build/libwismart.a(wps_dev_attr.o) +wps_device_data_free ../..//econais/build/libwismart.a(wps_dev_attr.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) +wps_device_store ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) +wps_enrollee_get_msg ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps.o) +wps_enrollee_process_msg ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps.o) +wps_fail_event ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_final_creds ../..//econais/build/libwismart.a(wps_supplicant.o) +wps_free_pending_msgs ../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) +wps_generate_pin ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(ap.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +wps_get_msg ../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(eap_wsc.o) +wps_get_uuid_e ../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +wps_ie_encapsulate ../..//econais/build/libwismart.a(wps_attr_build.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) +wps_init ../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(eap_wsc.o) +wps_is_20 ../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(drv_callbacks.o) +wps_is_addr_authorized ../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +wps_is_selected_pbc_registrar ../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +wps_is_selected_pin_registrar ../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +wps_kdf ../..//econais/build/libwismart.a(wps_common.o) +wps_parse_msg ../..//econais/build/libwismart.a(wps_attr_parse.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) +wps_pbc_overlap_event ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_pbc_timeout_event ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_pin_checksum ../..//econais/build/libwismart.a(wps_common.o) +wps_pin_valid ../..//econais/build/libwismart.a(wps_common.o) +wps_process_ap_settings ../..//econais/build/libwismart.a(wps_attr_process.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_process_authenticator ../..//econais/build/libwismart.a(wps_attr_process.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_process_cred ../..//econais/build/libwismart.a(wps_attr_process.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) +wps_process_device_attrs ../..//econais/build/libwismart.a(wps_dev_attr.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_process_key_wrap_auth ../..//econais/build/libwismart.a(wps_attr_process.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_process_msg ../..//econais/build/libwismart.a(wps.o) + ../..//econais/build/libwismart.a(eap_wsc.o) +wps_process_os_version ../..//econais/build/libwismart.a(wps_dev_attr.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_process_rf_bands ../..//econais/build/libwismart.a(wps_dev_attr.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_pwd_auth_fail_event ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +wps_registrar_add_pin ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(eap_wsc.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) +wps_registrar_button_pushed ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) +wps_registrar_complete ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) +wps_registrar_config_ap ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) +wps_registrar_deinit ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +wps_registrar_get_info ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) +wps_registrar_get_msg ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) +wps_registrar_init ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) + ../..//econais/build/libwismart.a(wps_supplicant.o) +wps_registrar_invalidate_pin ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) +wps_registrar_pbc_overlap ../..//econais/build/libwismart.a(wps_registrar.o) +wps_registrar_probe_req_rx ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) +wps_registrar_process_msg ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) +wps_registrar_selected_registrar_changed ../..//econais/build/libwismart.a(wps_registrar.o) +wps_registrar_unlock_pin ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps.o) +wps_registrar_update_ie ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(wps_hostapd.o) +wps_registrar_wps_cancel ../..//econais/build/libwismart.a(wps_registrar.o) + ../..//econais/build/libwismart.a(ap.o) +wps_set_ssid ../..//econais/build/libwismart.a(main_wifiengine.o) + ../..//econais/build/libwismart.a(libwismart_cm.o) +wps_success_event ../..//econais/build/libwismart.a(wps_common.o) + ../..//econais/build/libwismart.a(wps_enrollee.o) + ../..//econais/build/libwismart.a(wps_registrar.o) +x509_certificate_chain_free ../..//econais/build/libwismart.a(x509v3.o) + ../..//econais/build/libwismart.a(tlsv1_cred.o) + ../..//econais/build/libwismart.a(tlsv1_client_read.o) +x509_certificate_chain_validate ../..//econais/build/libwismart.a(x509v3.o) + ../..//econais/build/libwismart.a(tlsv1_client_read.o) +x509_certificate_check_signature ../..//econais/build/libwismart.a(x509v3.o) +x509_certificate_free ../..//econais/build/libwismart.a(x509v3.o) + ../..//econais/build/libwismart.a(tlsv1_common.o) +x509_certificate_get_subject ../..//econais/build/libwismart.a(x509v3.o) + ../..//econais/build/libwismart.a(tlsv1_client_write.o) +x509_certificate_parse ../..//econais/build/libwismart.a(x509v3.o) + ../..//econais/build/libwismart.a(tlsv1_cred.o) + ../..//econais/build/libwismart.a(tlsv1_common.o) + ../..//econais/build/libwismart.a(tlsv1_client_read.o) +x509_certificate_self_signed ../..//econais/build/libwismart.a(x509v3.o) + ../..//econais/build/libwismart.a(tlsv1_client_write.o) +x509_name_compare ../..//econais/build/libwismart.a(x509v3.o) + ../..//econais/build/libwismart.a(tlsv1_cred.o) +x509_name_string ../..//econais/build/libwismart.a(x509v3.o) + ../..//econais/build/libwismart.a(tlsv1_cred.o) diff --git a/Project/applications/smartcities/build/lst/buttonExample.lst b/Project/applications/smartcities/build/lst/buttonExample.lst new file mode 100644 index 0000000..2043b76 --- /dev/null +++ b/Project/applications/smartcities/build/lst/buttonExample.lst @@ -0,0 +1,2964 @@ +ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "buttonExample.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text.buttons_process,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .global buttons_process + 22 .thumb + 23 .thumb_func + 24 .type buttons_process, %function + 25 buttons_process: + 26 .LFB62: + 27 .file 1 "buttonExample.c" + 28 .loc 1 36 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .loc 1 37 0 + 34 0000 40F20002 movw r2, #:lower16:.LANCHOR0 + 35 0004 40F20003 movw r3, #:lower16:.LANCHOR1 + 36 0008 C0F20002 movt r2, #:upper16:.LANCHOR0 + 37 000c C0F20003 movt r3, #:upper16:.LANCHOR1 + 38 0010 1168 ldr r1, [r2, #0] + 39 0012 40F20000 movw r0, #:lower16:.LC0 + 40 0016 1A68 ldr r2, [r3, #0] + 41 0018 C0F20000 movt r0, #:upper16:.LC0 + 42 .loc 1 38 0 + 43 .loc 1 37 0 + 44 001c FFF7FEBF b print + 45 .LVL0: + 46 .cfi_endproc + 47 .LFE62: + 48 .size buttons_process, .-buttons_process + 49 .section .text.buttons_init,"ax",%progbits + 50 .align 2 + 51 .p2align 4,,15 + 52 .global buttons_init + 53 .thumb + 54 .thumb_func + 55 .type buttons_init, %function + 56 buttons_init: + 57 .LFB63: + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 2 + + + 58 .loc 1 40 0 + 59 .cfi_startproc + 60 @ args = 0, pretend = 0, frame = 16 + 61 @ frame_needed = 0, uses_anonymous_args = 0 + 62 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 63 .LCFI0: + 64 .cfi_def_cfa_offset 36 + 65 .cfi_offset 4, -36 + 66 .cfi_offset 5, -32 + 67 .cfi_offset 6, -28 + 68 .cfi_offset 7, -24 + 69 .cfi_offset 8, -20 + 70 .cfi_offset 9, -16 + 71 .cfi_offset 10, -12 + 72 .cfi_offset 11, -8 + 73 .cfi_offset 14, -4 + 74 .loc 1 49 0 + 75 0004 40F20000 movw r0, #:lower16:.LC1 + 76 .loc 1 40 0 + 77 0008 85B0 sub sp, sp, #20 + 78 .LCFI1: + 79 .cfi_def_cfa_offset 56 + 80 .loc 1 49 0 + 81 000a C0F20000 movt r0, #:upper16:.LC1 + 82 .loc 1 55 0 + 83 000e 4FF48058 mov r8, #4096 + 84 .loc 1 49 0 + 85 0012 FFF7FEFF bl print + 86 .LVL1: + 87 .loc 1 55 0 + 88 0016 C4F20108 movt r8, 16385 + 89 .loc 1 50 0 + 90 001a 1020 movs r0, #16 + 91 001c 0121 movs r1, #1 + 92 001e FFF7FEFF bl RCC_APB2PeriphClockCmd + 93 .LVL2: + 94 .loc 1 54 0 + 95 0022 2827 movs r7, #40 + 96 .loc 1 55 0 + 97 0024 6946 mov r1, sp + 98 .loc 1 52 0 + 99 0026 4FF4804A mov sl, #16384 + 100 .loc 1 53 0 + 101 002a 4FF0030B mov fp, #3 + 102 .loc 1 55 0 + 103 002e 4046 mov r0, r8 + 104 .loc 1 60 0 + 105 0030 0124 movs r4, #1 + 106 .loc 1 58 0 + 107 0032 0226 movs r6, #2 + 108 .loc 1 59 0 + 109 0034 0025 movs r5, #0 + 110 .loc 1 52 0 + 111 0036 ADF800A0 strh sl, [sp, #0] @ movhi + 112 .loc 1 53 0 + 113 003a 8DF802B0 strb fp, [sp, #2] + 114 .loc 1 54 0 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 3 + + + 115 003e 8DF80370 strb r7, [sp, #3] + 116 .loc 1 55 0 + 117 0042 FFF7FEFF bl GPIO_Init + 118 .LVL3: + 119 .loc 1 61 0 + 120 0046 01A8 add r0, sp, #4 + 121 .loc 1 67 0 + 122 0048 4FF00809 mov r9, #8 + 123 .loc 1 57 0 + 124 004c 8DF80470 strb r7, [sp, #4] + 125 .loc 1 58 0 + 126 0050 8DF80560 strb r6, [sp, #5] + 127 .loc 1 59 0 + 128 0054 8DF80650 strb r5, [sp, #6] + 129 .loc 1 60 0 + 130 0058 8DF80740 strb r4, [sp, #7] + 131 .loc 1 61 0 + 132 005c FFF7FEFF bl NVIC_Init + 133 .LVL4: + 134 .loc 1 63 0 + 135 0060 0E21 movs r1, #14 + 136 0062 3046 mov r0, r6 + 137 0064 FFF7FEFF bl GPIO_EXTILineConfig + 138 .LVL5: + 139 .loc 1 69 0 + 140 0068 0DEB0900 add r0, sp, r9 + 141 .loc 1 65 0 + 142 006c CDF808A0 str sl, [sp, #8] + 143 .loc 1 66 0 + 144 0070 8DF80C50 strb r5, [sp, #12] + 145 .loc 1 67 0 + 146 0074 8DF80D90 strb r9, [sp, #13] + 147 .loc 1 68 0 + 148 0078 8DF80E40 strb r4, [sp, #14] + 149 .loc 1 69 0 + 150 007c FFF7FEFF bl EXTI_Init + 151 .LVL6: + 152 .loc 1 74 0 + 153 0080 40F20000 movw r0, #:lower16:.LC2 + 154 0084 C0F20000 movt r0, #:upper16:.LC2 + 155 0088 FFF7FEFF bl print + 156 .LVL7: + 157 .loc 1 75 0 + 158 008c 1020 movs r0, #16 + 159 008e 2146 mov r1, r4 + 160 0090 FFF7FEFF bl RCC_APB2PeriphClockCmd + 161 .LVL8: + 162 .loc 1 77 0 + 163 0094 4FF4004A mov sl, #32768 + 164 .loc 1 80 0 + 165 0098 6946 mov r1, sp + 166 009a 4046 mov r0, r8 + 167 .loc 1 77 0 + 168 009c ADF800A0 strh sl, [sp, #0] @ movhi + 169 .loc 1 78 0 + 170 00a0 8DF802B0 strb fp, [sp, #2] + 171 .loc 1 79 0 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 4 + + + 172 00a4 8DF80370 strb r7, [sp, #3] + 173 .loc 1 80 0 + 174 00a8 FFF7FEFF bl GPIO_Init + 175 .LVL9: + 176 .loc 1 86 0 + 177 00ac 01A8 add r0, sp, #4 + 178 .loc 1 82 0 + 179 00ae 8DF80470 strb r7, [sp, #4] + 180 .loc 1 83 0 + 181 00b2 8DF80560 strb r6, [sp, #5] + 182 .loc 1 84 0 + 183 00b6 8DF80650 strb r5, [sp, #6] + 184 .loc 1 85 0 + 185 00ba 8DF80740 strb r4, [sp, #7] + 186 .loc 1 86 0 + 187 00be FFF7FEFF bl NVIC_Init + 188 .LVL10: + 189 .loc 1 88 0 + 190 00c2 3046 mov r0, r6 + 191 00c4 0F21 movs r1, #15 + 192 00c6 FFF7FEFF bl GPIO_EXTILineConfig + 193 .LVL11: + 194 .loc 1 94 0 + 195 00ca 0DEB0900 add r0, sp, r9 + 196 .loc 1 90 0 + 197 00ce CDF808A0 str sl, [sp, #8] + 198 .loc 1 91 0 + 199 00d2 8DF80C50 strb r5, [sp, #12] + 200 .loc 1 92 0 + 201 00d6 8DF80D90 strb r9, [sp, #13] + 202 .loc 1 93 0 + 203 00da 8DF80E40 strb r4, [sp, #14] + 204 .loc 1 94 0 + 205 00de FFF7FEFF bl EXTI_Init + 206 .LVL12: + 207 .loc 1 96 0 + 208 00e2 40F20000 movw r0, #:lower16:.LC3 + 209 00e6 C0F20000 movt r0, #:upper16:.LC3 + 210 00ea FFF7FEFF bl print + 211 .LVL13: + 212 .loc 1 97 0 + 213 00ee 05B0 add sp, sp, #20 + 214 00f0 BDE8F08F pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 215 .cfi_endproc + 216 .LFE63: + 217 .size buttons_init, .-buttons_init + 218 00f4 AFF30080 .section .text.VectorE0,"ax",%progbits + 218 AFF30080 + 218 AFF30080 + 219 .align 2 + 220 .p2align 4,,15 + 221 .global VectorE0 + 222 .thumb + 223 .thumb_func + 224 .type VectorE0, %function + 225 VectorE0: + 226 .LFB64: + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 5 + + + 227 .loc 1 102 0 + 228 .cfi_startproc + 229 @ args = 0, pretend = 0, frame = 0 + 230 @ frame_needed = 0, uses_anonymous_args = 0 + 231 0000 08B5 push {r3, lr} + 232 .LCFI2: + 233 .cfi_def_cfa_offset 8 + 234 .cfi_offset 3, -8 + 235 .cfi_offset 14, -4 + 236 .loc 1 104 0 + 237 @ 104 "buttonExample.c" 1 + 238 0002 72B6 cpsid i + 239 @ 0 "" 2 + 240 .loc 1 114 0 + 241 .thumb + 242 0004 4FF48040 mov r0, #16384 + 243 0008 FFF7FEFF bl EXTI_GetITStatus + 244 .LVL14: + 245 000c A0B9 cbnz r0, .L13 + 246 .L4: + 247 .loc 1 123 0 + 248 000e 4FF40040 mov r0, #32768 + 249 0012 FFF7FEFF bl EXTI_GetITStatus + 250 .LVL15: + 251 0016 50B1 cbz r0, .L5 + 252 .LBB2: + 253 .loc 1 124 0 + 254 0018 4FF40040 mov r0, #32768 + 255 001c FFF7FEFF bl EXTI_ClearITPendingBit + 256 .LVL16: + 257 .loc 1 125 0 + 258 0020 0B48 ldr r0, .L14 + 259 0022 FFF7FEFF bl printI + 260 .LVL17: + 261 .loc 1 126 0 + 262 0026 0B4B ldr r3, .L14+4 + 263 0028 1A68 ldr r2, [r3, #0] + 264 002a 0132 adds r2, r2, #1 + 265 002c 1A60 str r2, [r3, #0] + 266 .L5: + 267 .LBE2: + 268 .loc 1 130 0 + 269 @ 130 "buttonExample.c" 1 + 270 002e 62B6 cpsie i + 271 @ 0 "" 2 + 272 .loc 1 132 0 + 273 .thumb + 274 0030 BDE80840 pop {r3, lr} + 275 .loc 1 131 0 + 276 0034 FFF7FEBF b _port_irq_epilogue + 277 .LVL18: + 278 .L13: + 279 .LBB3: + 280 .loc 1 115 0 + 281 0038 4FF48040 mov r0, #16384 + 282 003c FFF7FEFF bl EXTI_ClearITPendingBit + 283 .LVL19: + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 6 + + + 284 .loc 1 116 0 + 285 0040 0548 ldr r0, .L14+8 + 286 0042 FFF7FEFF bl printI + 287 .LVL20: + 288 .loc 1 117 0 + 289 0046 054B ldr r3, .L14+12 + 290 0048 1A68 ldr r2, [r3, #0] + 291 004a 0132 adds r2, r2, #1 + 292 004c 1A60 str r2, [r3, #0] + 293 004e DEE7 b .L4 + 294 .L15: + 295 .align 2 + 296 .L14: + 297 0050 90000000 .word .LC5 + 298 0054 00000000 .word .LANCHOR1 + 299 0058 84000000 .word .LC4 + 300 005c 00000000 .word .LANCHOR0 + 301 .LBE3: + 302 .cfi_endproc + 303 .LFE64: + 304 .size VectorE0, .-VectorE0 + 305 .global sw3_irqs + 306 .global sw1_irqs + 307 .section .bss.sw1_irqs,"aw",%nobits + 308 .align 2 + 309 .set .LANCHOR0,. + 0 + 310 .type sw1_irqs, %object + 311 .size sw1_irqs, 4 + 312 sw1_irqs: + 313 0000 00000000 .space 4 + 314 .section .rodata.str1.4,"aMS",%progbits,1 + 315 .align 2 + 316 .LC0: + 317 0000 5B444247 .ascii "[DBG] SW1 presses = %u, SW3 presses = %u\015" + 317 5D202020 + 317 20202020 + 317 20205357 + 317 31207072 + 318 0031 0A00 .ascii "\012\000" + 319 0033 00 .space 1 + 320 .LC1: + 321 0034 5B444247 .ascii "[DBG] Setup SW1..\015\012\000" + 321 5D202020 + 321 20202020 + 321 20205365 + 321 74757020 + 322 .LC2: + 323 0050 5B444247 .ascii "[DBG] Setup SW3..\015\012\000" + 323 5D202020 + 323 20202020 + 323 20205365 + 323 74757020 + 324 .LC3: + 325 006c 5B444247 .ascii "[DBG] OK!\015\012\015\012\000" + 325 5D202020 + 325 20202020 + 325 20204F4B + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 7 + + + 325 210D0A0D + 326 0082 0000 .space 2 + 327 .LC4: + 328 0084 53573120 .ascii "SW1 IRQ!\015\012\000" + 328 49525121 + 328 0D0A00 + 329 008f 00 .space 1 + 330 .LC5: + 331 0090 53573320 .ascii "SW3 IRQ!\015\012\000" + 331 49525121 + 331 0D0A00 + 332 009b 00 .section .bss.sw3_irqs,"aw",%nobits + 333 .align 2 + 334 .set .LANCHOR1,. + 0 + 335 .type sw3_irqs, %object + 336 .size sw3_irqs, 4 + 337 sw3_irqs: + 338 0000 00000000 .space 4 + 339 .text + 340 .Letext0: + 341 .file 2 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 342 .file 3 "../..//econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h" + 343 .file 4 "../..//econais/STM32_Libs/F1/inc/stm32f10x_exti.h" + 344 .file 5 "../..//econais/STM32_Libs/F1/inc/misc.h" + 345 .file 6 "../..//econais/STM32_Libs/F1/inc/stm32f10x_gpio.h" + 346 .file 7 "../..//os/ports/common/ARMCMx/CMSIS/include/core_cm3.h" + 347 .file 8 "../..//econais/libwismart.h" + 348 .file 9 "../..//econais/STM32_Libs/F1/inc/stm32f10x_rcc.h" + 349 .file 10 "../..//os/ports/GCC/ARMCMx/chcore_v7m.h" + 350 .section .debug_info,"",%progbits + 351 .Ldebug_info0: + 352 0000 51080000 .4byte 0x851 + 353 0004 0200 .2byte 0x2 + 354 0006 00000000 .4byte .Ldebug_abbrev0 + 355 000a 04 .byte 0x4 + 356 000b 01 .uleb128 0x1 + 357 000c F1040000 .4byte .LASF142 + 358 0010 01 .byte 0x1 + 359 0011 3F080000 .4byte .LASF143 + 360 0015 69040000 .4byte .LASF144 + 361 0019 00000000 .4byte .Ldebug_ranges0+0 + 362 001d 00000000 .4byte 0 + 363 0021 00000000 .4byte 0 + 364 0025 00000000 .4byte .Ldebug_line0 + 365 0029 02 .uleb128 0x2 + 366 002a 04 .byte 0x4 + 367 002b 05 .byte 0x5 + 368 002c 696E7400 .ascii "int\000" + 369 0030 03 .uleb128 0x3 + 370 0031 04 .byte 0x4 + 371 0032 07 .byte 0x7 + 372 0033 82020000 .4byte .LASF0 + 373 0037 03 .uleb128 0x3 + 374 0038 01 .byte 0x1 + 375 0039 06 .byte 0x6 + 376 003a 2B010000 .4byte .LASF1 + 377 003e 04 .uleb128 0x4 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 8 + + + 378 003f C1070000 .4byte .LASF4 + 379 0043 02 .byte 0x2 + 380 0044 2A .byte 0x2a + 381 0045 49000000 .4byte 0x49 + 382 0049 03 .uleb128 0x3 + 383 004a 01 .byte 0x1 + 384 004b 08 .byte 0x8 + 385 004c 8E050000 .4byte .LASF2 + 386 0050 03 .uleb128 0x3 + 387 0051 02 .byte 0x2 + 388 0052 05 .byte 0x5 + 389 0053 00000000 .4byte .LASF3 + 390 0057 04 .uleb128 0x4 + 391 0058 DA010000 .4byte .LASF5 + 392 005c 02 .byte 0x2 + 393 005d 36 .byte 0x36 + 394 005e 62000000 .4byte 0x62 + 395 0062 03 .uleb128 0x3 + 396 0063 02 .byte 0x2 + 397 0064 07 .byte 0x7 + 398 0065 0C030000 .4byte .LASF6 + 399 0069 04 .uleb128 0x4 + 400 006a 86050000 .4byte .LASF7 + 401 006e 02 .byte 0x2 + 402 006f 4F .byte 0x4f + 403 0070 74000000 .4byte 0x74 + 404 0074 03 .uleb128 0x3 + 405 0075 04 .byte 0x4 + 406 0076 05 .byte 0x5 + 407 0077 5B010000 .4byte .LASF8 + 408 007b 04 .uleb128 0x4 + 409 007c 88060000 .4byte .LASF9 + 410 0080 02 .byte 0x2 + 411 0081 50 .byte 0x50 + 412 0082 86000000 .4byte 0x86 + 413 0086 03 .uleb128 0x3 + 414 0087 04 .byte 0x4 + 415 0088 07 .byte 0x7 + 416 0089 AF020000 .4byte .LASF10 + 417 008d 03 .uleb128 0x3 + 418 008e 08 .byte 0x8 + 419 008f 05 .byte 0x5 + 420 0090 1D010000 .4byte .LASF11 + 421 0094 03 .uleb128 0x3 + 422 0095 08 .byte 0x8 + 423 0096 07 .byte 0x7 + 424 0097 A5000000 .4byte .LASF12 + 425 009b 05 .uleb128 0x5 + 426 009c 7B000000 .4byte 0x7b + 427 00a0 03 .uleb128 0x3 + 428 00a1 04 .byte 0x4 + 429 00a2 07 .byte 0x7 + 430 00a3 E5030000 .4byte .LASF13 + 431 00a7 06 .uleb128 0x6 + 432 00a8 04 .byte 0x4 + 433 00a9 AD000000 .4byte 0xad + 434 00ad 07 .uleb128 0x7 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 9 + + + 435 00ae B2000000 .4byte 0xb2 + 436 00b2 03 .uleb128 0x3 + 437 00b3 01 .byte 0x1 + 438 00b4 08 .byte 0x8 + 439 00b5 C8060000 .4byte .LASF14 + 440 00b9 08 .uleb128 0x8 + 441 00ba CD030000 .4byte .LASF145 + 442 00be 01 .byte 0x1 + 443 00bf 03 .byte 0x3 + 444 00c0 A7 .byte 0xa7 + 445 00c1 5E020000 .4byte 0x25e + 446 00c5 09 .uleb128 0x9 + 447 00c6 FC060000 .4byte .LASF15 + 448 00ca 72 .sleb128 -14 + 449 00cb 09 .uleb128 0x9 + 450 00cc 99020000 .4byte .LASF16 + 451 00d0 74 .sleb128 -12 + 452 00d1 09 .uleb128 0x9 + 453 00d2 3D020000 .4byte .LASF17 + 454 00d6 75 .sleb128 -11 + 455 00d7 09 .uleb128 0x9 + 456 00d8 B8060000 .4byte .LASF18 + 457 00dc 76 .sleb128 -10 + 458 00dd 09 .uleb128 0x9 + 459 00de F8030000 .4byte .LASF19 + 460 00e2 7B .sleb128 -5 + 461 00e3 09 .uleb128 0x9 + 462 00e4 F5070000 .4byte .LASF20 + 463 00e8 7C .sleb128 -4 + 464 00e9 09 .uleb128 0x9 + 465 00ea FA010000 .4byte .LASF21 + 466 00ee 7E .sleb128 -2 + 467 00ef 09 .uleb128 0x9 + 468 00f0 A2030000 .4byte .LASF22 + 469 00f4 7F .sleb128 -1 + 470 00f5 09 .uleb128 0x9 + 471 00f6 FC000000 .4byte .LASF23 + 472 00fa 00 .sleb128 0 + 473 00fb 09 .uleb128 0x9 + 474 00fc 60000000 .4byte .LASF24 + 475 0100 01 .sleb128 1 + 476 0101 09 .uleb128 0x9 + 477 0102 53070000 .4byte .LASF25 + 478 0106 02 .sleb128 2 + 479 0107 09 .uleb128 0x9 + 480 0108 25080000 .4byte .LASF26 + 481 010c 03 .sleb128 3 + 482 010d 09 .uleb128 0x9 + 483 010e 7D060000 .4byte .LASF27 + 484 0112 04 .sleb128 4 + 485 0113 09 .uleb128 0x9 + 486 0114 C9070000 .4byte .LASF28 + 487 0118 05 .sleb128 5 + 488 0119 09 .uleb128 0x9 + 489 011a 98070000 .4byte .LASF29 + 490 011e 06 .sleb128 6 + 491 011f 09 .uleb128 0x9 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 10 + + + 492 0120 71080000 .4byte .LASF30 + 493 0124 07 .sleb128 7 + 494 0125 09 .uleb128 0x9 + 495 0126 F1000000 .4byte .LASF31 + 496 012a 08 .sleb128 8 + 497 012b 09 .uleb128 0x9 + 498 012c A3070000 .4byte .LASF32 + 499 0130 09 .sleb128 9 + 500 0131 09 .uleb128 0x9 + 501 0132 EF050000 .4byte .LASF33 + 502 0136 0A .sleb128 10 + 503 0137 09 .uleb128 0x9 + 504 0138 26050000 .4byte .LASF34 + 505 013c 0B .sleb128 11 + 506 013d 09 .uleb128 0x9 + 507 013e D2030000 .4byte .LASF35 + 508 0142 0C .sleb128 12 + 509 0143 09 .uleb128 0x9 + 510 0144 B0010000 .4byte .LASF36 + 511 0148 0D .sleb128 13 + 512 0149 09 .uleb128 0x9 + 513 014a 19020000 .4byte .LASF37 + 514 014e 0E .sleb128 14 + 515 014f 09 .uleb128 0x9 + 516 0150 F9020000 .4byte .LASF38 + 517 0154 0F .sleb128 15 + 518 0155 09 .uleb128 0x9 + 519 0156 3F030000 .4byte .LASF39 + 520 015a 10 .sleb128 16 + 521 015b 09 .uleb128 0x9 + 522 015c E2070000 .4byte .LASF40 + 523 0160 11 .sleb128 17 + 524 0161 09 .uleb128 0x9 + 525 0162 E3010000 .4byte .LASF41 + 526 0166 12 .sleb128 18 + 527 0167 09 .uleb128 0x9 + 528 0168 B1050000 .4byte .LASF42 + 529 016c 13 .sleb128 19 + 530 016d 09 .uleb128 0x9 + 531 016e 9C050000 .4byte .LASF43 + 532 0172 14 .sleb128 20 + 533 0173 09 .uleb128 0x9 + 534 0174 8D000000 .4byte .LASF44 + 535 0178 15 .sleb128 21 + 536 0179 09 .uleb128 0x9 + 537 017a 59080000 .4byte .LASF45 + 538 017e 16 .sleb128 22 + 539 017f 09 .uleb128 0x9 + 540 0180 99010000 .4byte .LASF46 + 541 0184 17 .sleb128 23 + 542 0185 09 .uleb128 0x9 + 543 0186 17040000 .4byte .LASF47 + 544 018a 18 .sleb128 24 + 545 018b 09 .uleb128 0x9 + 546 018c DC050000 .4byte .LASF48 + 547 0190 19 .sleb128 25 + 548 0191 09 .uleb128 0x9 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 11 + + + 549 0192 2A060000 .4byte .LASF49 + 550 0196 1A .sleb128 26 + 551 0197 09 .uleb128 0x9 + 552 0198 AF030000 .4byte .LASF50 + 553 019c 1B .sleb128 27 + 554 019d 09 .uleb128 0x9 + 555 019e 8E070000 .4byte .LASF51 + 556 01a2 1C .sleb128 28 + 557 01a3 09 .uleb128 0x9 + 558 01a4 67080000 .4byte .LASF52 + 559 01a8 1D .sleb128 29 + 560 01a9 09 .uleb128 0x9 + 561 01aa E7000000 .4byte .LASF53 + 562 01ae 1E .sleb128 30 + 563 01af 09 .uleb128 0x9 + 564 01b0 42000000 .4byte .LASF54 + 565 01b4 1F .sleb128 31 + 566 01b5 09 .uleb128 0x9 + 567 01b6 18080000 .4byte .LASF55 + 568 01ba 20 .sleb128 32 + 569 01bb 09 .uleb128 0x9 + 570 01bc 6B010000 .4byte .LASF56 + 571 01c0 21 .sleb128 33 + 572 01c1 09 .uleb128 0x9 + 573 01c2 DA000000 .4byte .LASF57 + 574 01c6 22 .sleb128 34 + 575 01c7 09 .uleb128 0x9 + 576 01c8 52030000 .4byte .LASF58 + 577 01cc 23 .sleb128 35 + 578 01cd 09 .uleb128 0x9 + 579 01ce 51040000 .4byte .LASF59 + 580 01d2 24 .sleb128 36 + 581 01d3 09 .uleb128 0x9 + 582 01d4 57050000 .4byte .LASF60 + 583 01d8 25 .sleb128 37 + 584 01d9 09 .uleb128 0x9 + 585 01da AC060000 .4byte .LASF61 + 586 01de 26 .sleb128 38 + 587 01df 09 .uleb128 0x9 + 588 01e0 82070000 .4byte .LASF62 + 589 01e4 27 .sleb128 39 + 590 01e5 09 .uleb128 0x9 + 591 01e6 30030000 .4byte .LASF63 + 592 01ea 28 .sleb128 40 + 593 01eb 09 .uleb128 0x9 + 594 01ec E4060000 .4byte .LASF64 + 595 01f0 29 .sleb128 41 + 596 01f1 09 .uleb128 0x9 + 597 01f2 73070000 .4byte .LASF65 + 598 01f6 2A .sleb128 42 + 599 01f7 09 .uleb128 0x9 + 600 01f8 6C030000 .4byte .LASF66 + 601 01fc 2B .sleb128 43 + 602 01fd 09 .uleb128 0x9 + 603 01fe 06020000 .4byte .LASF67 + 604 0202 2C .sleb128 44 + 605 0203 09 .uleb128 0x9 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 12 + + + 606 0204 65060000 .4byte .LASF68 + 607 0208 2D .sleb128 45 + 608 0209 09 .uleb128 0x9 + 609 020a 10010000 .4byte .LASF69 + 610 020e 2E .sleb128 46 + 611 020f 09 .uleb128 0x9 + 612 0210 A6010000 .4byte .LASF70 + 613 0214 2F .sleb128 47 + 614 0215 09 .uleb128 0x9 + 615 0216 69050000 .4byte .LASF71 + 616 021a 30 .sleb128 48 + 617 021b 09 .uleb128 0x9 + 618 021c 06010000 .4byte .LASF72 + 619 0220 31 .sleb128 49 + 620 0221 09 .uleb128 0x9 + 621 0222 37040000 .4byte .LASF73 + 622 0226 32 .sleb128 50 + 623 0227 09 .uleb128 0x9 + 624 0228 2E080000 .4byte .LASF74 + 625 022c 33 .sleb128 51 + 626 022d 09 .uleb128 0x9 + 627 022e EF010000 .4byte .LASF75 + 628 0232 34 .sleb128 52 + 629 0233 09 .uleb128 0x9 + 630 0234 1F060000 .4byte .LASF76 + 631 0238 35 .sleb128 53 + 632 0239 09 .uleb128 0x9 + 633 023a D2050000 .4byte .LASF77 + 634 023e 36 .sleb128 54 + 635 023f 09 .uleb128 0x9 + 636 0240 F2060000 .4byte .LASF78 + 637 0244 37 .sleb128 55 + 638 0245 09 .uleb128 0x9 + 639 0246 BC000000 .4byte .LASF79 + 640 024a 38 .sleb128 56 + 641 024b 09 .uleb128 0x9 + 642 024c 04040000 .4byte .LASF80 + 643 0250 39 .sleb128 57 + 644 0251 09 .uleb128 0x9 + 645 0252 73050000 .4byte .LASF81 + 646 0256 3A .sleb128 58 + 647 0257 09 .uleb128 0x9 + 648 0258 42060000 .4byte .LASF82 + 649 025c 3B .sleb128 59 + 650 025d 00 .byte 0 + 651 025e 05 .uleb128 0x5 + 652 025f 69000000 .4byte 0x69 + 653 0263 0A .uleb128 0xa + 654 0264 01 .byte 0x1 + 655 0265 03 .byte 0x3 + 656 0266 0702 .2byte 0x207 + 657 0268 79020000 .4byte 0x279 + 658 026c 09 .uleb128 0x9 + 659 026d 63050000 .4byte .LASF83 + 660 0271 00 .sleb128 0 + 661 0272 0B .uleb128 0xb + 662 0273 53455400 .ascii "SET\000" + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 13 + + + 663 0277 01 .sleb128 1 + 664 0278 00 .byte 0 + 665 0279 0C .uleb128 0xc + 666 027a 79020000 .4byte .LASF84 + 667 027e 03 .byte 0x3 + 668 027f 0702 .2byte 0x207 + 669 0281 63020000 .4byte 0x263 + 670 0285 0A .uleb128 0xa + 671 0286 01 .byte 0x1 + 672 0287 03 .byte 0x3 + 673 0288 0902 .2byte 0x209 + 674 028a 9B020000 .4byte 0x29b + 675 028e 09 .uleb128 0x9 + 676 028f 85000000 .4byte .LASF85 + 677 0293 00 .sleb128 0 + 678 0294 09 .uleb128 0x9 + 679 0295 64010000 .4byte .LASF86 + 680 0299 01 .sleb128 1 + 681 029a 00 .byte 0 + 682 029b 0C .uleb128 0xc + 683 029c D0040000 .4byte .LASF87 + 684 02a0 03 .byte 0x3 + 685 02a1 0902 .2byte 0x209 + 686 02a3 85020000 .4byte 0x285 + 687 02a7 0D .uleb128 0xd + 688 02a8 1C .byte 0x1c + 689 02a9 03 .byte 0x3 + 690 02aa E903 .2byte 0x3e9 + 691 02ac 1A030000 .4byte 0x31a + 692 02b0 0E .uleb128 0xe + 693 02b1 43524C00 .ascii "CRL\000" + 694 02b5 03 .byte 0x3 + 695 02b6 EB03 .2byte 0x3eb + 696 02b8 9B000000 .4byte 0x9b + 697 02bc 02 .byte 0x2 + 698 02bd 23 .byte 0x23 + 699 02be 00 .uleb128 0 + 700 02bf 0E .uleb128 0xe + 701 02c0 43524800 .ascii "CRH\000" + 702 02c4 03 .byte 0x3 + 703 02c5 EC03 .2byte 0x3ec + 704 02c7 9B000000 .4byte 0x9b + 705 02cb 02 .byte 0x2 + 706 02cc 23 .byte 0x23 + 707 02cd 04 .uleb128 0x4 + 708 02ce 0E .uleb128 0xe + 709 02cf 49445200 .ascii "IDR\000" + 710 02d3 03 .byte 0x3 + 711 02d4 ED03 .2byte 0x3ed + 712 02d6 9B000000 .4byte 0x9b + 713 02da 02 .byte 0x2 + 714 02db 23 .byte 0x23 + 715 02dc 08 .uleb128 0x8 + 716 02dd 0E .uleb128 0xe + 717 02de 4F445200 .ascii "ODR\000" + 718 02e2 03 .byte 0x3 + 719 02e3 EE03 .2byte 0x3ee + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 14 + + + 720 02e5 9B000000 .4byte 0x9b + 721 02e9 02 .byte 0x2 + 722 02ea 23 .byte 0x23 + 723 02eb 0C .uleb128 0xc + 724 02ec 0F .uleb128 0xf + 725 02ed 37010000 .4byte .LASF88 + 726 02f1 03 .byte 0x3 + 727 02f2 EF03 .2byte 0x3ef + 728 02f4 9B000000 .4byte 0x9b + 729 02f8 02 .byte 0x2 + 730 02f9 23 .byte 0x23 + 731 02fa 10 .uleb128 0x10 + 732 02fb 0E .uleb128 0xe + 733 02fc 42525200 .ascii "BRR\000" + 734 0300 03 .byte 0x3 + 735 0301 F003 .2byte 0x3f0 + 736 0303 9B000000 .4byte 0x9b + 737 0307 02 .byte 0x2 + 738 0308 23 .byte 0x23 + 739 0309 14 .uleb128 0x14 + 740 030a 0F .uleb128 0xf + 741 030b CE020000 .4byte .LASF89 + 742 030f 03 .byte 0x3 + 743 0310 F103 .2byte 0x3f1 + 744 0312 9B000000 .4byte 0x9b + 745 0316 02 .byte 0x2 + 746 0317 23 .byte 0x23 + 747 0318 18 .uleb128 0x18 + 748 0319 00 .byte 0 + 749 031a 0C .uleb128 0xc + 750 031b C1020000 .4byte .LASF90 + 751 031f 03 .byte 0x3 + 752 0320 F203 .2byte 0x3f2 + 753 0322 A7020000 .4byte 0x2a7 + 754 0326 10 .uleb128 0x10 + 755 0327 01 .byte 0x1 + 756 0328 04 .byte 0x4 + 757 0329 33 .byte 0x33 + 758 032a 3B030000 .4byte 0x33b + 759 032e 09 .uleb128 0x9 + 760 032f 43050000 .4byte .LASF91 + 761 0333 00 .sleb128 0 + 762 0334 09 .uleb128 0x9 + 763 0335 D2070000 .4byte .LASF92 + 764 0339 04 .sleb128 4 + 765 033a 00 .byte 0 + 766 033b 04 .uleb128 0x4 + 767 033c 78010000 .4byte .LASF93 + 768 0340 04 .byte 0x4 + 769 0341 36 .byte 0x36 + 770 0342 26030000 .4byte 0x326 + 771 0346 10 .uleb128 0x10 + 772 0347 01 .byte 0x1 + 773 0348 04 .byte 0x4 + 774 0349 3F .byte 0x3f + 775 034a 61030000 .4byte 0x361 + 776 034e 09 .uleb128 0x9 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 15 + + + 777 034f 5F070000 .4byte .LASF94 + 778 0353 08 .sleb128 8 + 779 0354 09 .uleb128 0x9 + 780 0355 FA050000 .4byte .LASF95 + 781 0359 0C .sleb128 12 + 782 035a 09 .uleb128 0x9 + 783 035b 69000000 .4byte .LASF96 + 784 035f 10 .sleb128 16 + 785 0360 00 .byte 0 + 786 0361 04 .uleb128 0x4 + 787 0362 24070000 .4byte .LASF97 + 788 0366 04 .byte 0x4 + 789 0367 43 .byte 0x43 + 790 0368 46030000 .4byte 0x346 + 791 036c 11 .uleb128 0x11 + 792 036d 08 .byte 0x8 + 793 036e 04 .byte 0x4 + 794 036f 4C .byte 0x4c + 795 0370 AD030000 .4byte 0x3ad + 796 0374 12 .uleb128 0x12 + 797 0375 9B000000 .4byte .LASF98 + 798 0379 04 .byte 0x4 + 799 037a 4E .byte 0x4e + 800 037b 7B000000 .4byte 0x7b + 801 037f 02 .byte 0x2 + 802 0380 23 .byte 0x23 + 803 0381 00 .uleb128 0 + 804 0382 12 .uleb128 0x12 + 805 0383 39050000 .4byte .LASF99 + 806 0387 04 .byte 0x4 + 807 0388 51 .byte 0x51 + 808 0389 3B030000 .4byte 0x33b + 809 038d 02 .byte 0x2 + 810 038e 23 .byte 0x23 + 811 038f 04 .uleb128 0x4 + 812 0390 12 .uleb128 0x12 + 813 0391 06050000 .4byte .LASF100 + 814 0395 04 .byte 0x4 + 815 0396 54 .byte 0x54 + 816 0397 61030000 .4byte 0x361 + 817 039b 02 .byte 0x2 + 818 039c 23 .byte 0x23 + 819 039d 05 .uleb128 0x5 + 820 039e 12 .uleb128 0x12 + 821 039f 35000000 .4byte .LASF101 + 822 03a3 04 .byte 0x4 + 823 03a4 57 .byte 0x57 + 824 03a5 9B020000 .4byte 0x29b + 825 03a9 02 .byte 0x2 + 826 03aa 23 .byte 0x23 + 827 03ab 06 .uleb128 0x6 + 828 03ac 00 .byte 0 + 829 03ad 04 .uleb128 0x4 + 830 03ae 42070000 .4byte .LASF102 + 831 03b2 04 .byte 0x4 + 832 03b3 59 .byte 0x59 + 833 03b4 6C030000 .4byte 0x36c + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 16 + + + 834 03b8 11 .uleb128 0x11 + 835 03b9 04 .byte 0x4 + 836 03ba 05 .byte 0x5 + 837 03bb 32 .byte 0x32 + 838 03bc F9030000 .4byte 0x3f9 + 839 03c0 12 .uleb128 0x12 + 840 03c1 5C030000 .4byte .LASF103 + 841 03c5 05 .byte 0x5 + 842 03c6 34 .byte 0x34 + 843 03c7 3E000000 .4byte 0x3e + 844 03cb 02 .byte 0x2 + 845 03cc 23 .byte 0x23 + 846 03cd 00 .uleb128 0 + 847 03ce 12 .uleb128 0x12 + 848 03cf 80030000 .4byte .LASF104 + 849 03d3 05 .byte 0x5 + 850 03d4 39 .byte 0x39 + 851 03d5 3E000000 .4byte 0x3e + 852 03d9 02 .byte 0x2 + 853 03da 23 .byte 0x23 + 854 03db 01 .uleb128 0x1 + 855 03dc 12 .uleb128 0x12 + 856 03dd 91060000 .4byte .LASF105 + 857 03e1 05 .byte 0x5 + 858 03e2 3D .byte 0x3d + 859 03e3 3E000000 .4byte 0x3e + 860 03e7 02 .byte 0x2 + 861 03e8 23 .byte 0x23 + 862 03e9 02 .uleb128 0x2 + 863 03ea 12 .uleb128 0x12 + 864 03eb 10000000 .4byte .LASF106 + 865 03ef 05 .byte 0x5 + 866 03f0 41 .byte 0x41 + 867 03f1 9B020000 .4byte 0x29b + 868 03f5 02 .byte 0x2 + 869 03f6 23 .byte 0x23 + 870 03f7 03 .uleb128 0x3 + 871 03f8 00 .byte 0 + 872 03f9 04 .uleb128 0x4 + 873 03fa BC030000 .4byte .LASF107 + 874 03fe 05 .byte 0x5 + 875 03ff 44 .byte 0x44 + 876 0400 B8030000 .4byte 0x3b8 + 877 0404 10 .uleb128 0x10 + 878 0405 01 .byte 0x1 + 879 0406 06 .byte 0x6 + 880 0407 3B .byte 0x3b + 881 0408 1F040000 .4byte 0x41f + 882 040c 09 .uleb128 0x9 + 883 040d 4F000000 .4byte .LASF108 + 884 0411 01 .sleb128 1 + 885 0412 09 .uleb128 0x9 + 886 0413 0F060000 .4byte .LASF109 + 887 0417 02 .sleb128 2 + 888 0418 09 .uleb128 0x9 + 889 0419 2C020000 .4byte .LASF110 + 890 041d 03 .sleb128 3 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 17 + + + 891 041e 00 .byte 0 + 892 041f 04 .uleb128 0x4 + 893 0420 4B020000 .4byte .LASF111 + 894 0424 06 .byte 0x6 + 895 0425 3F .byte 0x3f + 896 0426 04040000 .4byte 0x404 + 897 042a 10 .uleb128 0x10 + 898 042b 01 .byte 0x1 + 899 042c 06 .byte 0x6 + 900 042d 48 .byte 0x48 + 901 042e 64040000 .4byte 0x464 + 902 0432 09 .uleb128 0x9 + 903 0433 57060000 .4byte .LASF112 + 904 0437 00 .sleb128 0 + 905 0438 09 .uleb128 0x9 + 906 0439 D3020000 .4byte .LASF113 + 907 043d 04 .sleb128 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.byte 0x2 + 943 0483 23 .byte 0x23 + 944 0484 00 .uleb128 0 + 945 0485 12 .uleb128 0x12 + 946 0486 CF000000 .4byte .LASF122 + 947 048a 06 .byte 0x6 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 18 + + + 948 048b 60 .byte 0x60 + 949 048c 1F040000 .4byte 0x41f + 950 0490 02 .byte 0x2 + 951 0491 23 .byte 0x23 + 952 0492 02 .uleb128 0x2 + 953 0493 12 .uleb128 0x12 + 954 0494 38070000 .4byte .LASF123 + 955 0498 06 .byte 0x6 + 956 0499 63 .byte 0x63 + 957 049a 64040000 .4byte 0x464 + 958 049e 02 .byte 0x2 + 959 049f 23 .byte 0x23 + 960 04a0 03 .uleb128 0x3 + 961 04a1 00 .byte 0 + 962 04a2 04 .uleb128 0x4 + 963 04a3 BF040000 .4byte .LASF124 + 964 04a7 06 .byte 0x6 + 965 04a8 65 .byte 0x65 + 966 04a9 6F040000 .4byte 0x46f + 967 04ad 13 .uleb128 0x13 + 968 04ae 01 .byte 0x1 + 969 04af 89010000 .4byte .LASF125 + 970 04b3 01 .byte 0x1 + 971 04b4 24 .byte 0x24 + 972 04b5 01 .byte 0x1 + 973 04b6 00000000 .4byte .LFB62 + 974 04ba 20000000 .4byte .LFE62 + 975 04be 02 .byte 0x2 + 976 04bf 7D .byte 0x7d + 977 04c0 00 .sleb128 0 + 978 04c1 01 .byte 0x1 + 979 04c2 DB040000 .4byte 0x4db + 980 04c6 14 .uleb128 0x14 + 981 04c7 20000000 .4byte .LVL0 + 982 04cb 01 .byte 0x1 + 983 04cc 67070000 .4byte 0x767 + 984 04d0 15 .uleb128 0x15 + 985 04d1 01 .byte 0x1 + 986 04d2 50 .byte 0x50 + 987 04d3 05 .byte 0x5 + 988 04d4 03 .byte 0x3 + 989 04d5 00000000 .4byte .LC0 + 990 04d9 00 .byte 0 + 991 04da 00 .byte 0 + 992 04db 16 .uleb128 0x16 + 993 04dc 01 .byte 0x1 + 994 04dd 2A040000 .4byte .LASF126 + 995 04e1 01 .byte 0x1 + 996 04e2 28 .byte 0x28 + 997 04e3 01 .byte 0x1 + 998 04e4 00000000 .4byte .LFB63 + 999 04e8 F4000000 .4byte .LFE63 + 1000 04ec 00000000 .4byte .LLST0 + 1001 04f0 01 .byte 0x1 + 1002 04f1 54060000 .4byte 0x654 + 1003 04f5 17 .uleb128 0x17 + 1004 04f6 AC040000 .4byte .LASF127 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 19 + + + 1005 04fa 01 .byte 0x1 + 1006 04fb 2A .byte 0x2a + 1007 04fc A2040000 .4byte 0x4a2 + 1008 0500 02 .byte 0x2 + 1009 0501 91 .byte 0x91 + 1010 0502 48 .sleb128 -56 + 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60000000 .4byte .LFE64 + 1221 0665 2C000000 .4byte .LLST1 + 1222 0669 01 .byte 0x1 + 1223 066a 35070000 .4byte 0x735 + 1224 066e 1A .uleb128 0x1a + 1225 066f 18000000 .4byte .LBB2 + 1226 0673 2E000000 .4byte .LBE2 + 1227 0677 B7060000 .4byte 0x6b7 + 1228 067b 1B .uleb128 0x1b + 1229 067c 01 .byte 0x1 + 1230 067d 38080000 .4byte .LASF131 + 1231 0681 01 .byte 0x1 + 1232 0682 74 .byte 0x74 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 23 + + + 1233 0683 29000000 .4byte 0x29 + 1234 0687 01 .byte 0x1 + 1235 0688 8E060000 .4byte 0x68e + 1236 068c 1C .uleb128 0x1c + 1237 068d 00 .byte 0 + 1238 068e 18 .uleb128 0x18 + 1239 068f 20000000 .4byte .LVL16 + 1240 0693 0A080000 .4byte 0x80a + 1241 0697 A3060000 .4byte 0x6a3 + 1242 069b 15 .uleb128 0x15 + 1243 069c 01 .byte 0x1 + 1244 069d 50 .byte 0x50 + 1245 069e 03 .byte 0x3 + 1246 069f 0A .byte 0xa + 1247 06a0 0080 .2byte 0x8000 + 1248 06a2 00 .byte 0 + 1249 06a3 19 .uleb128 0x19 + 1250 06a4 26000000 .4byte .LVL17 + 1251 06a8 1E080000 .4byte 0x81e + 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072f 01 .byte 0x1 + 1321 0730 49080000 .4byte 0x849 + 1322 0734 00 .byte 0 + 1323 0735 1E .uleb128 0x1e + 1324 0736 C5050000 .4byte .LASF132 + 1325 073a 07 .byte 0x7 + 1326 073b 9404 .2byte 0x494 + 1327 073d 5E020000 .4byte 0x25e + 1328 0741 01 .byte 0x1 + 1329 0742 01 .byte 0x1 + 1330 0743 1F .uleb128 0x1f + 1331 0744 23000000 .4byte .LASF133 + 1332 0748 01 .byte 0x1 + 1333 0749 20 .byte 0x20 + 1334 074a 7B000000 .4byte 0x7b + 1335 074e 01 .byte 0x1 + 1336 074f 05 .byte 0x5 + 1337 0750 03 .byte 0x3 + 1338 0751 00000000 .4byte sw1_irqs + 1339 0755 1F .uleb128 0x1f + 1340 0756 FD040000 .4byte .LASF134 + 1341 075a 01 .byte 0x1 + 1342 075b 21 .byte 0x21 + 1343 075c 7B000000 .4byte 0x7b + 1344 0760 01 .byte 0x1 + 1345 0761 05 .byte 0x5 + 1346 0762 03 .byte 0x3 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 25 + + + 1347 0763 00000000 .4byte sw3_irqs + 1348 0767 20 .uleb128 0x20 + 1349 0768 01 .byte 0x1 + 1350 0769 0A000000 .4byte .LASF135 + 1351 076d 08 .byte 0x8 + 1352 076e 45 .byte 0x45 + 1353 076f 01 .byte 0x1 + 1354 0770 01 .byte 0x1 + 1355 0771 7C070000 .4byte 0x77c + 1356 0775 21 .uleb128 0x21 + 1357 0776 A7000000 .4byte 0xa7 + 1358 077a 1C .uleb128 0x1c + 1359 077b 00 .byte 0 + 1360 077c 22 .uleb128 0x22 + 1361 077d 01 .byte 0x1 + 1362 077e CD060000 .4byte .LASF136 + 1363 0782 09 .byte 0x9 + 1364 0783 B502 .2byte 0x2b5 + 1365 0785 01 .byte 0x1 + 1366 0786 01 .byte 0x1 + 1367 0787 96070000 .4byte 0x796 + 1368 078b 21 .uleb128 0x21 + 1369 078c 7B000000 .4byte 0x7b + 1370 0790 21 .uleb128 0x21 + 1371 0791 9B020000 .4byte 0x29b + 1372 0795 00 .byte 0 + 1373 0796 22 .uleb128 0x22 + 1374 0797 01 .byte 0x1 + 1375 0798 EE030000 .4byte .LASF137 + 1376 079c 06 .byte 0x6 + 1377 079d 5F01 .2byte 0x15f + 1378 079f 01 .byte 0x1 + 1379 07a0 01 .byte 0x1 + 1380 07a1 B0070000 .4byte 0x7b0 + 1381 07a5 21 .uleb128 0x21 + 1382 07a6 B0070000 .4byte 0x7b0 + 1383 07aa 21 .uleb128 0x21 + 1384 07ab B6070000 .4byte 0x7b6 + 1385 07af 00 .byte 0 + 1386 07b0 06 .uleb128 0x6 + 1387 07b1 04 .byte 0x4 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1421 07f2 8F020000 .4byte .LASF140 + 1422 07f6 04 .byte 0x4 + 1423 07f7 9F .byte 0x9f + 1424 07f8 01 .byte 0x1 + 1425 07f9 01 .byte 0x1 + 1426 07fa 04080000 .4byte 0x804 + 1427 07fe 21 .uleb128 0x21 + 1428 07ff 04080000 .4byte 0x804 + 1429 0803 00 .byte 0 + 1430 0804 06 .uleb128 0x6 + 1431 0805 04 .byte 0x4 + 1432 0806 AD030000 .4byte 0x3ad + 1433 080a 20 .uleb128 0x20 + 1434 080b 01 .byte 0x1 + 1435 080c C3010000 .4byte .LASF141 + 1436 0810 04 .byte 0x4 + 1437 0811 A5 .byte 0xa5 + 1438 0812 01 .byte 0x1 + 1439 0813 01 .byte 0x1 + 1440 0814 1E080000 .4byte 0x81e + 1441 0818 21 .uleb128 0x21 + 1442 0819 7B000000 .4byte 0x7b + 1443 081d 00 .byte 0 + 1444 081e 1B .uleb128 0x1b + 1445 081f 01 .byte 0x1 + 1446 0820 38080000 .4byte .LASF131 + 1447 0824 01 .byte 0x1 + 1448 0825 74 .byte 0x74 + 1449 0826 29000000 .4byte 0x29 + 1450 082a 01 .byte 0x1 + 1451 082b 31080000 .4byte 0x831 + 1452 082f 1C .uleb128 0x1c + 1453 0830 00 .byte 0 + 1454 0831 23 .uleb128 0x23 + 1455 0832 01 .byte 0x1 + 1456 0833 3C010000 .4byte .LASF146 + 1457 0837 04 .byte 0x4 + 1458 0838 A4 .byte 0xa4 + 1459 0839 01 .byte 0x1 + 1460 083a 79020000 .4byte 0x279 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 27 + + + 1461 083e 01 .byte 0x1 + 1462 083f 49080000 .4byte 0x849 + 1463 0843 21 .uleb128 0x21 + 1464 0844 7B000000 .4byte 0x7b + 1465 0848 00 .byte 0 + 1466 0849 24 .uleb128 0x24 + 1467 084a 01 .byte 0x1 + 1468 084b AE070000 .4byte .LASF147 + 1469 084f 0A .byte 0xa + 1470 0850 F501 .2byte 0x1f5 + 1471 0852 01 .byte 0x1 + 1472 0853 01 .byte 0x1 + 1473 0854 00 .byte 0 + 1474 .section .debug_abbrev,"",%progbits + 1475 .Ldebug_abbrev0: + 1476 0000 01 .uleb128 0x1 + 1477 0001 11 .uleb128 0x11 + 1478 0002 01 .byte 0x1 + 1479 0003 25 .uleb128 0x25 + 1480 0004 0E .uleb128 0xe + 1481 0005 13 .uleb128 0x13 + 1482 0006 0B .uleb128 0xb + 1483 0007 03 .uleb128 0x3 + 1484 0008 0E .uleb128 0xe + 1485 0009 1B .uleb128 0x1b + 1486 000a 0E .uleb128 0xe + 1487 000b 55 .uleb128 0x55 + 1488 000c 06 .uleb128 0x6 + 1489 000d 11 .uleb128 0x11 + 1490 000e 01 .uleb128 0x1 + 1491 000f 52 .uleb128 0x52 + 1492 0010 01 .uleb128 0x1 + 1493 0011 10 .uleb128 0x10 + 1494 0012 06 .uleb128 0x6 + 1495 0013 00 .byte 0 + 1496 0014 00 .byte 0 + 1497 0015 02 .uleb128 0x2 + 1498 0016 24 .uleb128 0x24 + 1499 0017 00 .byte 0 + 1500 0018 0B .uleb128 0xb + 1501 0019 0B .uleb128 0xb + 1502 001a 3E .uleb128 0x3e + 1503 001b 0B .uleb128 0xb + 1504 001c 03 .uleb128 0x3 + 1505 001d 08 .uleb128 0x8 + 1506 001e 00 .byte 0 + 1507 001f 00 .byte 0 + 1508 0020 03 .uleb128 0x3 + 1509 0021 24 .uleb128 0x24 + 1510 0022 00 .byte 0 + 1511 0023 0B .uleb128 0xb + 1512 0024 0B .uleb128 0xb + 1513 0025 3E .uleb128 0x3e + 1514 0026 0B .uleb128 0xb + 1515 0027 03 .uleb128 0x3 + 1516 0028 0E .uleb128 0xe + 1517 0029 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 28 + + + 1518 002a 00 .byte 0 + 1519 002b 04 .uleb128 0x4 + 1520 002c 16 .uleb128 0x16 + 1521 002d 00 .byte 0 + 1522 002e 03 .uleb128 0x3 + 1523 002f 0E .uleb128 0xe + 1524 0030 3A .uleb128 0x3a + 1525 0031 0B .uleb128 0xb + 1526 0032 3B .uleb128 0x3b + 1527 0033 0B .uleb128 0xb + 1528 0034 49 .uleb128 0x49 + 1529 0035 13 .uleb128 0x13 + 1530 0036 00 .byte 0 + 1531 0037 00 .byte 0 + 1532 0038 05 .uleb128 0x5 + 1533 0039 35 .uleb128 0x35 + 1534 003a 00 .byte 0 + 1535 003b 49 .uleb128 0x49 + 1536 003c 13 .uleb128 0x13 + 1537 003d 00 .byte 0 + 1538 003e 00 .byte 0 + 1539 003f 06 .uleb128 0x6 + 1540 0040 0F .uleb128 0xf + 1541 0041 00 .byte 0 + 1542 0042 0B .uleb128 0xb + 1543 0043 0B .uleb128 0xb + 1544 0044 49 .uleb128 0x49 + 1545 0045 13 .uleb128 0x13 + 1546 0046 00 .byte 0 + 1547 0047 00 .byte 0 + 1548 0048 07 .uleb128 0x7 + 1549 0049 26 .uleb128 0x26 + 1550 004a 00 .byte 0 + 1551 004b 49 .uleb128 0x49 + 1552 004c 13 .uleb128 0x13 + 1553 004d 00 .byte 0 + 1554 004e 00 .byte 0 + 1555 004f 08 .uleb128 0x8 + 1556 0050 04 .uleb128 0x4 + 1557 0051 01 .byte 0x1 + 1558 0052 03 .uleb128 0x3 + 1559 0053 0E .uleb128 0xe + 1560 0054 0B .uleb128 0xb + 1561 0055 0B .uleb128 0xb + 1562 0056 3A .uleb128 0x3a + 1563 0057 0B .uleb128 0xb + 1564 0058 3B .uleb128 0x3b + 1565 0059 0B .uleb128 0xb + 1566 005a 01 .uleb128 0x1 + 1567 005b 13 .uleb128 0x13 + 1568 005c 00 .byte 0 + 1569 005d 00 .byte 0 + 1570 005e 09 .uleb128 0x9 + 1571 005f 28 .uleb128 0x28 + 1572 0060 00 .byte 0 + 1573 0061 03 .uleb128 0x3 + 1574 0062 0E .uleb128 0xe + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 29 + + + 1575 0063 1C .uleb128 0x1c + 1576 0064 0D .uleb128 0xd + 1577 0065 00 .byte 0 + 1578 0066 00 .byte 0 + 1579 0067 0A .uleb128 0xa + 1580 0068 04 .uleb128 0x4 + 1581 0069 01 .byte 0x1 + 1582 006a 0B .uleb128 0xb + 1583 006b 0B .uleb128 0xb + 1584 006c 3A .uleb128 0x3a + 1585 006d 0B .uleb128 0xb + 1586 006e 3B .uleb128 0x3b + 1587 006f 05 .uleb128 0x5 + 1588 0070 01 .uleb128 0x1 + 1589 0071 13 .uleb128 0x13 + 1590 0072 00 .byte 0 + 1591 0073 00 .byte 0 + 1592 0074 0B .uleb128 0xb + 1593 0075 28 .uleb128 0x28 + 1594 0076 00 .byte 0 + 1595 0077 03 .uleb128 0x3 + 1596 0078 08 .uleb128 0x8 + 1597 0079 1C .uleb128 0x1c + 1598 007a 0D .uleb128 0xd + 1599 007b 00 .byte 0 + 1600 007c 00 .byte 0 + 1601 007d 0C .uleb128 0xc + 1602 007e 16 .uleb128 0x16 + 1603 007f 00 .byte 0 + 1604 0080 03 .uleb128 0x3 + 1605 0081 0E .uleb128 0xe + 1606 0082 3A .uleb128 0x3a + 1607 0083 0B .uleb128 0xb + 1608 0084 3B .uleb128 0x3b + 1609 0085 05 .uleb128 0x5 + 1610 0086 49 .uleb128 0x49 + 1611 0087 13 .uleb128 0x13 + 1612 0088 00 .byte 0 + 1613 0089 00 .byte 0 + 1614 008a 0D .uleb128 0xd + 1615 008b 13 .uleb128 0x13 + 1616 008c 01 .byte 0x1 + 1617 008d 0B .uleb128 0xb + 1618 008e 0B .uleb128 0xb + 1619 008f 3A .uleb128 0x3a + 1620 0090 0B .uleb128 0xb + 1621 0091 3B .uleb128 0x3b + 1622 0092 05 .uleb128 0x5 + 1623 0093 01 .uleb128 0x1 + 1624 0094 13 .uleb128 0x13 + 1625 0095 00 .byte 0 + 1626 0096 00 .byte 0 + 1627 0097 0E .uleb128 0xe + 1628 0098 0D .uleb128 0xd + 1629 0099 00 .byte 0 + 1630 009a 03 .uleb128 0x3 + 1631 009b 08 .uleb128 0x8 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 30 + + + 1632 009c 3A .uleb128 0x3a + 1633 009d 0B .uleb128 0xb + 1634 009e 3B .uleb128 0x3b + 1635 009f 05 .uleb128 0x5 + 1636 00a0 49 .uleb128 0x49 + 1637 00a1 13 .uleb128 0x13 + 1638 00a2 38 .uleb128 0x38 + 1639 00a3 0A .uleb128 0xa + 1640 00a4 00 .byte 0 + 1641 00a5 00 .byte 0 + 1642 00a6 0F .uleb128 0xf + 1643 00a7 0D .uleb128 0xd + 1644 00a8 00 .byte 0 + 1645 00a9 03 .uleb128 0x3 + 1646 00aa 0E .uleb128 0xe + 1647 00ab 3A .uleb128 0x3a + 1648 00ac 0B .uleb128 0xb + 1649 00ad 3B .uleb128 0x3b + 1650 00ae 05 .uleb128 0x5 + 1651 00af 49 .uleb128 0x49 + 1652 00b0 13 .uleb128 0x13 + 1653 00b1 38 .uleb128 0x38 + 1654 00b2 0A .uleb128 0xa + 1655 00b3 00 .byte 0 + 1656 00b4 00 .byte 0 + 1657 00b5 10 .uleb128 0x10 + 1658 00b6 04 .uleb128 0x4 + 1659 00b7 01 .byte 0x1 + 1660 00b8 0B .uleb128 0xb + 1661 00b9 0B .uleb128 0xb + 1662 00ba 3A .uleb128 0x3a + 1663 00bb 0B .uleb128 0xb + 1664 00bc 3B .uleb128 0x3b + 1665 00bd 0B .uleb128 0xb + 1666 00be 01 .uleb128 0x1 + 1667 00bf 13 .uleb128 0x13 + 1668 00c0 00 .byte 0 + 1669 00c1 00 .byte 0 + 1670 00c2 11 .uleb128 0x11 + 1671 00c3 13 .uleb128 0x13 + 1672 00c4 01 .byte 0x1 + 1673 00c5 0B .uleb128 0xb + 1674 00c6 0B .uleb128 0xb + 1675 00c7 3A .uleb128 0x3a + 1676 00c8 0B .uleb128 0xb + 1677 00c9 3B .uleb128 0x3b + 1678 00ca 0B .uleb128 0xb + 1679 00cb 01 .uleb128 0x1 + 1680 00cc 13 .uleb128 0x13 + 1681 00cd 00 .byte 0 + 1682 00ce 00 .byte 0 + 1683 00cf 12 .uleb128 0x12 + 1684 00d0 0D .uleb128 0xd + 1685 00d1 00 .byte 0 + 1686 00d2 03 .uleb128 0x3 + 1687 00d3 0E .uleb128 0xe + 1688 00d4 3A .uleb128 0x3a + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 31 + + + 1689 00d5 0B .uleb128 0xb + 1690 00d6 3B .uleb128 0x3b + 1691 00d7 0B .uleb128 0xb + 1692 00d8 49 .uleb128 0x49 + 1693 00d9 13 .uleb128 0x13 + 1694 00da 38 .uleb128 0x38 + 1695 00db 0A .uleb128 0xa + 1696 00dc 00 .byte 0 + 1697 00dd 00 .byte 0 + 1698 00de 13 .uleb128 0x13 + 1699 00df 2E .uleb128 0x2e + 1700 00e0 01 .byte 0x1 + 1701 00e1 3F .uleb128 0x3f + 1702 00e2 0C .uleb128 0xc + 1703 00e3 03 .uleb128 0x3 + 1704 00e4 0E .uleb128 0xe + 1705 00e5 3A .uleb128 0x3a + 1706 00e6 0B .uleb128 0xb + 1707 00e7 3B .uleb128 0x3b + 1708 00e8 0B .uleb128 0xb + 1709 00e9 27 .uleb128 0x27 + 1710 00ea 0C .uleb128 0xc + 1711 00eb 11 .uleb128 0x11 + 1712 00ec 01 .uleb128 0x1 + 1713 00ed 12 .uleb128 0x12 + 1714 00ee 01 .uleb128 0x1 + 1715 00ef 40 .uleb128 0x40 + 1716 00f0 0A .uleb128 0xa + 1717 00f1 9742 .uleb128 0x2117 + 1718 00f3 0C .uleb128 0xc + 1719 00f4 01 .uleb128 0x1 + 1720 00f5 13 .uleb128 0x13 + 1721 00f6 00 .byte 0 + 1722 00f7 00 .byte 0 + 1723 00f8 14 .uleb128 0x14 + 1724 00f9 898201 .uleb128 0x4109 + 1725 00fc 01 .byte 0x1 + 1726 00fd 11 .uleb128 0x11 + 1727 00fe 01 .uleb128 0x1 + 1728 00ff 9542 .uleb128 0x2115 + 1729 0101 0C .uleb128 0xc + 1730 0102 31 .uleb128 0x31 + 1731 0103 13 .uleb128 0x13 + 1732 0104 00 .byte 0 + 1733 0105 00 .byte 0 + 1734 0106 15 .uleb128 0x15 + 1735 0107 8A8201 .uleb128 0x410a + 1736 010a 00 .byte 0 + 1737 010b 02 .uleb128 0x2 + 1738 010c 0A .uleb128 0xa + 1739 010d 9142 .uleb128 0x2111 + 1740 010f 0A .uleb128 0xa + 1741 0110 00 .byte 0 + 1742 0111 00 .byte 0 + 1743 0112 16 .uleb128 0x16 + 1744 0113 2E .uleb128 0x2e + 1745 0114 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 32 + + + 1746 0115 3F .uleb128 0x3f + 1747 0116 0C .uleb128 0xc + 1748 0117 03 .uleb128 0x3 + 1749 0118 0E .uleb128 0xe + 1750 0119 3A .uleb128 0x3a + 1751 011a 0B .uleb128 0xb + 1752 011b 3B .uleb128 0x3b + 1753 011c 0B .uleb128 0xb + 1754 011d 27 .uleb128 0x27 + 1755 011e 0C .uleb128 0xc + 1756 011f 11 .uleb128 0x11 + 1757 0120 01 .uleb128 0x1 + 1758 0121 12 .uleb128 0x12 + 1759 0122 01 .uleb128 0x1 + 1760 0123 40 .uleb128 0x40 + 1761 0124 06 .uleb128 0x6 + 1762 0125 9742 .uleb128 0x2117 + 1763 0127 0C .uleb128 0xc + 1764 0128 01 .uleb128 0x1 + 1765 0129 13 .uleb128 0x13 + 1766 012a 00 .byte 0 + 1767 012b 00 .byte 0 + 1768 012c 17 .uleb128 0x17 + 1769 012d 34 .uleb128 0x34 + 1770 012e 00 .byte 0 + 1771 012f 03 .uleb128 0x3 + 1772 0130 0E .uleb128 0xe + 1773 0131 3A .uleb128 0x3a + 1774 0132 0B .uleb128 0xb + 1775 0133 3B .uleb128 0x3b + 1776 0134 0B .uleb128 0xb + 1777 0135 49 .uleb128 0x49 + 1778 0136 13 .uleb128 0x13 + 1779 0137 02 .uleb128 0x2 + 1780 0138 0A .uleb128 0xa + 1781 0139 00 .byte 0 + 1782 013a 00 .byte 0 + 1783 013b 18 .uleb128 0x18 + 1784 013c 898201 .uleb128 0x4109 + 1785 013f 01 .byte 0x1 + 1786 0140 11 .uleb128 0x11 + 1787 0141 01 .uleb128 0x1 + 1788 0142 31 .uleb128 0x31 + 1789 0143 13 .uleb128 0x13 + 1790 0144 01 .uleb128 0x1 + 1791 0145 13 .uleb128 0x13 + 1792 0146 00 .byte 0 + 1793 0147 00 .byte 0 + 1794 0148 19 .uleb128 0x19 + 1795 0149 898201 .uleb128 0x4109 + 1796 014c 01 .byte 0x1 + 1797 014d 11 .uleb128 0x11 + 1798 014e 01 .uleb128 0x1 + 1799 014f 31 .uleb128 0x31 + 1800 0150 13 .uleb128 0x13 + 1801 0151 00 .byte 0 + 1802 0152 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 33 + + + 1803 0153 1A .uleb128 0x1a + 1804 0154 0B .uleb128 0xb + 1805 0155 01 .byte 0x1 + 1806 0156 11 .uleb128 0x11 + 1807 0157 01 .uleb128 0x1 + 1808 0158 12 .uleb128 0x12 + 1809 0159 01 .uleb128 0x1 + 1810 015a 01 .uleb128 0x1 + 1811 015b 13 .uleb128 0x13 + 1812 015c 00 .byte 0 + 1813 015d 00 .byte 0 + 1814 015e 1B .uleb128 0x1b + 1815 015f 2E .uleb128 0x2e + 1816 0160 01 .byte 0x1 + 1817 0161 3F .uleb128 0x3f + 1818 0162 0C .uleb128 0xc + 1819 0163 03 .uleb128 0x3 + 1820 0164 0E .uleb128 0xe + 1821 0165 3A .uleb128 0x3a + 1822 0166 0B .uleb128 0xb + 1823 0167 3B .uleb128 0x3b + 1824 0168 0B .uleb128 0xb + 1825 0169 49 .uleb128 0x49 + 1826 016a 13 .uleb128 0x13 + 1827 016b 3C .uleb128 0x3c + 1828 016c 0C .uleb128 0xc + 1829 016d 01 .uleb128 0x1 + 1830 016e 13 .uleb128 0x13 + 1831 016f 00 .byte 0 + 1832 0170 00 .byte 0 + 1833 0171 1C .uleb128 0x1c + 1834 0172 18 .uleb128 0x18 + 1835 0173 00 .byte 0 + 1836 0174 00 .byte 0 + 1837 0175 00 .byte 0 + 1838 0176 1D .uleb128 0x1d + 1839 0177 898201 .uleb128 0x4109 + 1840 017a 00 .byte 0 + 1841 017b 11 .uleb128 0x11 + 1842 017c 01 .uleb128 0x1 + 1843 017d 9542 .uleb128 0x2115 + 1844 017f 0C .uleb128 0xc + 1845 0180 31 .uleb128 0x31 + 1846 0181 13 .uleb128 0x13 + 1847 0182 00 .byte 0 + 1848 0183 00 .byte 0 + 1849 0184 1E .uleb128 0x1e + 1850 0185 34 .uleb128 0x34 + 1851 0186 00 .byte 0 + 1852 0187 03 .uleb128 0x3 + 1853 0188 0E .uleb128 0xe + 1854 0189 3A .uleb128 0x3a + 1855 018a 0B .uleb128 0xb + 1856 018b 3B .uleb128 0x3b + 1857 018c 05 .uleb128 0x5 + 1858 018d 49 .uleb128 0x49 + 1859 018e 13 .uleb128 0x13 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 34 + + + 1860 018f 3F .uleb128 0x3f + 1861 0190 0C .uleb128 0xc + 1862 0191 3C .uleb128 0x3c + 1863 0192 0C .uleb128 0xc + 1864 0193 00 .byte 0 + 1865 0194 00 .byte 0 + 1866 0195 1F .uleb128 0x1f + 1867 0196 34 .uleb128 0x34 + 1868 0197 00 .byte 0 + 1869 0198 03 .uleb128 0x3 + 1870 0199 0E .uleb128 0xe + 1871 019a 3A .uleb128 0x3a + 1872 019b 0B .uleb128 0xb + 1873 019c 3B .uleb128 0x3b + 1874 019d 0B .uleb128 0xb + 1875 019e 49 .uleb128 0x49 + 1876 019f 13 .uleb128 0x13 + 1877 01a0 3F .uleb128 0x3f + 1878 01a1 0C .uleb128 0xc + 1879 01a2 02 .uleb128 0x2 + 1880 01a3 0A .uleb128 0xa + 1881 01a4 00 .byte 0 + 1882 01a5 00 .byte 0 + 1883 01a6 20 .uleb128 0x20 + 1884 01a7 2E .uleb128 0x2e + 1885 01a8 01 .byte 0x1 + 1886 01a9 3F .uleb128 0x3f + 1887 01aa 0C .uleb128 0xc + 1888 01ab 03 .uleb128 0x3 + 1889 01ac 0E .uleb128 0xe + 1890 01ad 3A .uleb128 0x3a + 1891 01ae 0B .uleb128 0xb + 1892 01af 3B .uleb128 0x3b + 1893 01b0 0B .uleb128 0xb + 1894 01b1 27 .uleb128 0x27 + 1895 01b2 0C .uleb128 0xc + 1896 01b3 3C .uleb128 0x3c + 1897 01b4 0C .uleb128 0xc + 1898 01b5 01 .uleb128 0x1 + 1899 01b6 13 .uleb128 0x13 + 1900 01b7 00 .byte 0 + 1901 01b8 00 .byte 0 + 1902 01b9 21 .uleb128 0x21 + 1903 01ba 05 .uleb128 0x5 + 1904 01bb 00 .byte 0 + 1905 01bc 49 .uleb128 0x49 + 1906 01bd 13 .uleb128 0x13 + 1907 01be 00 .byte 0 + 1908 01bf 00 .byte 0 + 1909 01c0 22 .uleb128 0x22 + 1910 01c1 2E .uleb128 0x2e + 1911 01c2 01 .byte 0x1 + 1912 01c3 3F .uleb128 0x3f + 1913 01c4 0C .uleb128 0xc + 1914 01c5 03 .uleb128 0x3 + 1915 01c6 0E .uleb128 0xe + 1916 01c7 3A .uleb128 0x3a + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 35 + + + 1917 01c8 0B .uleb128 0xb + 1918 01c9 3B .uleb128 0x3b + 1919 01ca 05 .uleb128 0x5 + 1920 01cb 27 .uleb128 0x27 + 1921 01cc 0C .uleb128 0xc + 1922 01cd 3C .uleb128 0x3c + 1923 01ce 0C .uleb128 0xc + 1924 01cf 01 .uleb128 0x1 + 1925 01d0 13 .uleb128 0x13 + 1926 01d1 00 .byte 0 + 1927 01d2 00 .byte 0 + 1928 01d3 23 .uleb128 0x23 + 1929 01d4 2E .uleb128 0x2e + 1930 01d5 01 .byte 0x1 + 1931 01d6 3F .uleb128 0x3f + 1932 01d7 0C .uleb128 0xc + 1933 01d8 03 .uleb128 0x3 + 1934 01d9 0E .uleb128 0xe + 1935 01da 3A .uleb128 0x3a + 1936 01db 0B .uleb128 0xb + 1937 01dc 3B .uleb128 0x3b + 1938 01dd 0B .uleb128 0xb + 1939 01de 27 .uleb128 0x27 + 1940 01df 0C .uleb128 0xc + 1941 01e0 49 .uleb128 0x49 + 1942 01e1 13 .uleb128 0x13 + 1943 01e2 3C .uleb128 0x3c + 1944 01e3 0C .uleb128 0xc + 1945 01e4 01 .uleb128 0x1 + 1946 01e5 13 .uleb128 0x13 + 1947 01e6 00 .byte 0 + 1948 01e7 00 .byte 0 + 1949 01e8 24 .uleb128 0x24 + 1950 01e9 2E .uleb128 0x2e + 1951 01ea 00 .byte 0 + 1952 01eb 3F .uleb128 0x3f + 1953 01ec 0C .uleb128 0xc + 1954 01ed 03 .uleb128 0x3 + 1955 01ee 0E .uleb128 0xe + 1956 01ef 3A .uleb128 0x3a + 1957 01f0 0B .uleb128 0xb + 1958 01f1 3B .uleb128 0x3b + 1959 01f2 05 .uleb128 0x5 + 1960 01f3 27 .uleb128 0x27 + 1961 01f4 0C .uleb128 0xc + 1962 01f5 3C .uleb128 0x3c + 1963 01f6 0C .uleb128 0xc + 1964 01f7 00 .byte 0 + 1965 01f8 00 .byte 0 + 1966 01f9 00 .byte 0 + 1967 .section .debug_loc,"",%progbits + 1968 .Ldebug_loc0: + 1969 .LLST0: + 1970 0000 00000000 .4byte .LFB63 + 1971 0004 04000000 .4byte .LCFI0 + 1972 0008 0200 .2byte 0x2 + 1973 000a 7D .byte 0x7d + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 36 + + + 1974 000b 00 .sleb128 0 + 1975 000c 04000000 .4byte .LCFI0 + 1976 0010 0A000000 .4byte .LCFI1 + 1977 0014 0200 .2byte 0x2 + 1978 0016 7D .byte 0x7d + 1979 0017 24 .sleb128 36 + 1980 0018 0A000000 .4byte .LCFI1 + 1981 001c F4000000 .4byte .LFE63 + 1982 0020 0200 .2byte 0x2 + 1983 0022 7D .byte 0x7d + 1984 0023 38 .sleb128 56 + 1985 0024 00000000 .4byte 0 + 1986 0028 00000000 .4byte 0 + 1987 .LLST1: + 1988 002c 00000000 .4byte .LFB64 + 1989 0030 02000000 .4byte .LCFI2 + 1990 0034 0200 .2byte 0x2 + 1991 0036 7D .byte 0x7d + 1992 0037 00 .sleb128 0 + 1993 0038 02000000 .4byte .LCFI2 + 1994 003c 60000000 .4byte .LFE64 + 1995 0040 0200 .2byte 0x2 + 1996 0042 7D .byte 0x7d + 1997 0043 08 .sleb128 8 + 1998 0044 00000000 .4byte 0 + 1999 0048 00000000 .4byte 0 + 2000 .section .debug_aranges,"",%progbits + 2001 0000 2C000000 .4byte 0x2c + 2002 0004 0200 .2byte 0x2 + 2003 0006 00000000 .4byte .Ldebug_info0 + 2004 000a 04 .byte 0x4 + 2005 000b 00 .byte 0 + 2006 000c 0000 .2byte 0 + 2007 000e 0000 .2byte 0 + 2008 0010 00000000 .4byte .LFB62 + 2009 0014 20000000 .4byte .LFE62-.LFB62 + 2010 0018 00000000 .4byte .LFB63 + 2011 001c F4000000 .4byte .LFE63-.LFB63 + 2012 0020 00000000 .4byte .LFB64 + 2013 0024 60000000 .4byte .LFE64-.LFB64 + 2014 0028 00000000 .4byte 0 + 2015 002c 00000000 .4byte 0 + 2016 .section .debug_ranges,"",%progbits + 2017 .Ldebug_ranges0: + 2018 0000 00000000 .4byte .LFB62 + 2019 0004 20000000 .4byte .LFE62 + 2020 0008 00000000 .4byte .LFB63 + 2021 000c F4000000 .4byte .LFE63 + 2022 0010 00000000 .4byte .LFB64 + 2023 0014 60000000 .4byte .LFE64 + 2024 0018 00000000 .4byte 0 + 2025 001c 00000000 .4byte 0 + 2026 .section .debug_line,"",%progbits + 2027 .Ldebug_line0: + 2028 0000 2D020000 .section .debug_str,"MS",%progbits,1 + 2028 0200A001 + 2028 00000201 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 37 + + + 2028 FB0E0D00 + 2028 01010101 + 2029 .LASF3: + 2030 0000 73686F72 .ascii "short int\000" + 2030 7420696E + 2030 7400 + 2031 .LASF135: + 2032 000a 7072696E .ascii "print\000" + 2032 7400 + 2033 .LASF106: + 2034 0010 4E564943 .ascii "NVIC_IRQChannelCmd\000" + 2034 5F495251 + 2034 4368616E + 2034 6E656C43 + 2034 6D6400 + 2035 .LASF133: + 2036 0023 7377315F .ascii "sw1_irqs\000" + 2036 69727173 + 2036 00 + 2037 .LASF130: + 2038 002c 56656374 .ascii "VectorE0\000" + 2038 6F724530 + 2038 00 + 2039 .LASF101: + 2040 0035 45585449 .ascii "EXTI_LineCmd\000" + 2040 5F4C696E + 2040 65436D64 + 2040 00 + 2041 .LASF54: + 2042 0042 49324331 .ascii "I2C1_EV_IRQn\000" + 2042 5F45565F + 2042 4952516E + 2042 00 + 2043 .LASF108: + 2044 004f 4750494F .ascii "GPIO_Speed_10MHz\000" + 2044 5F537065 + 2044 65645F31 + 2044 304D487A + 2044 00 + 2045 .LASF24: + 2046 0060 5056445F .ascii "PVD_IRQn\000" + 2046 4952516E + 2046 00 + 2047 .LASF96: + 2048 0069 45585449 .ascii "EXTI_Trigger_Rising_Falling\000" + 2048 5F547269 + 2048 67676572 + 2048 5F526973 + 2048 696E675F + 2049 .LASF85: + 2050 0085 44495341 .ascii "DISABLE\000" + 2050 424C4500 + 2051 .LASF44: + 2052 008d 43414E31 .ascii "CAN1_RX1_IRQn\000" + 2052 5F525831 + 2052 5F495251 + 2052 6E00 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 38 + + + 2053 .LASF98: + 2054 009b 45585449 .ascii "EXTI_Line\000" + 2054 5F4C696E + 2054 6500 + 2055 .LASF12: + 2056 00a5 6C6F6E67 .ascii "long long unsigned int\000" + 2056 206C6F6E + 2056 6720756E + 2056 7369676E + 2056 65642069 + 2057 .LASF79: + 2058 00bc 444D4132 .ascii "DMA2_Channel1_IRQn\000" + 2058 5F436861 + 2058 6E6E656C + 2058 315F4952 + 2058 516E00 + 2059 .LASF122: + 2060 00cf 4750494F .ascii "GPIO_Speed\000" + 2060 5F537065 + 2060 656400 + 2061 .LASF57: + 2062 00da 49324332 .ascii "I2C2_ER_IRQn\000" + 2062 5F45525F + 2062 4952516E + 2062 00 + 2063 .LASF53: + 2064 00e7 54494D34 .ascii "TIM4_IRQn\000" + 2064 5F495251 + 2064 6E00 + 2065 .LASF31: + 2066 00f1 45585449 .ascii "EXTI2_IRQn\000" + 2066 325F4952 + 2066 516E00 + 2067 .LASF23: + 2068 00fc 57574447 .ascii "WWDG_IRQn\000" + 2068 5F495251 + 2068 6E00 + 2069 .LASF72: + 2070 0106 5344494F .ascii "SDIO_IRQn\000" + 2070 5F495251 + 2070 6E00 + 2071 .LASF69: + 2072 0110 54494D38 .ascii "TIM8_CC_IRQn\000" + 2072 5F43435F + 2072 4952516E + 2072 00 + 2073 .LASF11: + 2074 011d 6C6F6E67 .ascii "long long int\000" + 2074 206C6F6E + 2074 6720696E + 2074 7400 + 2075 .LASF1: + 2076 012b 7369676E .ascii "signed char\000" + 2076 65642063 + 2076 68617200 + 2077 .LASF88: + 2078 0137 42535252 .ascii "BSRR\000" + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 39 + + + 2078 00 + 2079 .LASF146: + 2080 013c 45585449 .ascii "EXTI_GetITStatus\000" + 2080 5F476574 + 2080 49545374 + 2080 61747573 + 2080 00 + 2081 .LASF115: + 2082 014d 4750494F .ascii "GPIO_Mode_IPU\000" + 2082 5F4D6F64 + 2082 655F4950 + 2082 5500 + 2083 .LASF8: + 2084 015b 6C6F6E67 .ascii "long int\000" + 2084 20696E74 + 2084 00 + 2085 .LASF86: + 2086 0164 454E4142 .ascii "ENABLE\000" + 2086 4C4500 + 2087 .LASF56: + 2088 016b 49324332 .ascii "I2C2_EV_IRQn\000" + 2088 5F45565F + 2088 4952516E + 2088 00 + 2089 .LASF93: + 2090 0178 45585449 .ascii "EXTIMode_TypeDef\000" + 2090 4D6F6465 + 2090 5F547970 + 2090 65446566 + 2090 00 + 2091 .LASF125: + 2092 0189 62757474 .ascii "buttons_process\000" + 2092 6F6E735F + 2092 70726F63 + 2092 65737300 + 2093 .LASF46: + 2094 0199 45585449 .ascii "EXTI9_5_IRQn\000" + 2094 395F355F + 2094 4952516E + 2094 00 + 2095 .LASF70: + 2096 01a6 41444333 .ascii "ADC3_IRQn\000" + 2096 5F495251 + 2096 6E00 + 2097 .LASF36: + 2098 01b0 444D4131 .ascii "DMA1_Channel3_IRQn\000" + 2098 5F436861 + 2098 6E6E656C + 2098 335F4952 + 2098 516E00 + 2099 .LASF141: + 2100 01c3 45585449 .ascii "EXTI_ClearITPendingBit\000" + 2100 5F436C65 + 2100 61724954 + 2100 50656E64 + 2100 696E6742 + 2101 .LASF5: + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 40 + + + 2102 01da 75696E74 .ascii "uint16_t\000" + 2102 31365F74 + 2102 00 + 2103 .LASF41: + 2104 01e3 41444331 .ascii "ADC1_2_IRQn\000" + 2104 5F325F49 + 2104 52516E00 + 2105 .LASF75: + 2106 01ef 55415254 .ascii "UART4_IRQn\000" + 2106 345F4952 + 2106 516E00 + 2107 .LASF21: + 2108 01fa 50656E64 .ascii "PendSV_IRQn\000" + 2108 53565F49 + 2108 52516E00 + 2109 .LASF67: + 2110 0206 54494D38 .ascii "TIM8_UP_TIM13_IRQn\000" + 2110 5F55505F + 2110 54494D31 + 2110 335F4952 + 2110 516E00 + 2111 .LASF37: + 2112 0219 444D4131 .ascii "DMA1_Channel4_IRQn\000" + 2112 5F436861 + 2112 6E6E656C + 2112 345F4952 + 2112 516E00 + 2113 .LASF110: + 2114 022c 4750494F .ascii "GPIO_Speed_50MHz\000" + 2114 5F537065 + 2114 65645F35 + 2114 304D487A + 2114 00 + 2115 .LASF17: + 2116 023d 42757346 .ascii "BusFault_IRQn\000" + 2116 61756C74 + 2116 5F495251 + 2116 6E00 + 2117 .LASF111: + 2118 024b 4750494F .ascii "GPIOSpeed_TypeDef\000" + 2118 53706565 + 2118 645F5479 + 2118 70654465 + 2118 6600 + 2119 .LASF121: + 2120 025d 4750494F .ascii "GPIO_Pin\000" + 2120 5F50696E + 2120 00 + 2121 .LASF129: + 2122 0266 4E564943 .ascii "NVIC_InitStructure\000" + 2122 5F496E69 + 2122 74537472 + 2122 75637475 + 2122 726500 + 2123 .LASF84: + 2124 0279 49545374 .ascii "ITStatus\000" + 2124 61747573 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 41 + + + 2124 00 + 2125 .LASF0: + 2126 0282 756E7369 .ascii "unsigned int\000" + 2126 676E6564 + 2126 20696E74 + 2126 00 + 2127 .LASF140: + 2128 028f 45585449 .ascii "EXTI_Init\000" + 2128 5F496E69 + 2128 7400 + 2129 .LASF16: + 2130 0299 4D656D6F .ascii "MemoryManagement_IRQn\000" + 2130 72794D61 + 2130 6E616765 + 2130 6D656E74 + 2130 5F495251 + 2131 .LASF10: + 2132 02af 6C6F6E67 .ascii "long unsigned int\000" + 2132 20756E73 + 2132 69676E65 + 2132 6420696E + 2132 7400 + 2133 .LASF90: + 2134 02c1 4750494F .ascii "GPIO_TypeDef\000" + 2134 5F547970 + 2134 65446566 + 2134 00 + 2135 .LASF89: + 2136 02ce 4C434B52 .ascii "LCKR\000" + 2136 00 + 2137 .LASF113: + 2138 02d3 4750494F .ascii "GPIO_Mode_IN_FLOATING\000" + 2138 5F4D6F64 + 2138 655F494E + 2138 5F464C4F + 2138 4154494E + 2139 .LASF118: + 2140 02e9 4750494F .ascii "GPIO_Mode_AF_OD\000" + 2140 5F4D6F64 + 2140 655F4146 + 2140 5F4F4400 + 2141 .LASF38: + 2142 02f9 444D4131 .ascii "DMA1_Channel5_IRQn\000" + 2142 5F436861 + 2142 6E6E656C + 2142 355F4952 + 2142 516E00 + 2143 .LASF6: + 2144 030c 73686F72 .ascii "short unsigned int\000" + 2144 7420756E + 2144 7369676E + 2144 65642069 + 2144 6E7400 + 2145 .LASF116: + 2146 031f 4750494F .ascii "GPIO_Mode_Out_OD\000" + 2146 5F4D6F64 + 2146 655F4F75 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 42 + + + 2146 745F4F44 + 2146 00 + 2147 .LASF63: + 2148 0330 45585449 .ascii "EXTI15_10_IRQn\000" + 2148 31355F31 + 2148 305F4952 + 2148 516E00 + 2149 .LASF39: + 2150 033f 444D4131 .ascii "DMA1_Channel6_IRQn\000" + 2150 5F436861 + 2150 6E6E656C + 2150 365F4952 + 2150 516E00 + 2151 .LASF58: + 2152 0352 53504931 .ascii "SPI1_IRQn\000" + 2152 5F495251 + 2152 6E00 + 2153 .LASF103: + 2154 035c 4E564943 .ascii "NVIC_IRQChannel\000" + 2154 5F495251 + 2154 4368616E + 2154 6E656C00 + 2155 .LASF66: + 2156 036c 54494D38 .ascii "TIM8_BRK_TIM12_IRQn\000" + 2156 5F42524B + 2156 5F54494D + 2156 31325F49 + 2156 52516E00 + 2157 .LASF104: + 2158 0380 4E564943 .ascii "NVIC_IRQChannelPreemptionPriority\000" + 2158 5F495251 + 2158 4368616E + 2158 6E656C50 + 2158 7265656D + 2159 .LASF22: + 2160 03a2 53797354 .ascii "SysTick_IRQn\000" + 2160 69636B5F + 2160 4952516E + 2160 00 + 2161 .LASF50: + 2162 03af 54494D31 .ascii "TIM1_CC_IRQn\000" + 2162 5F43435F + 2162 4952516E + 2162 00 + 2163 .LASF107: + 2164 03bc 4E564943 .ascii "NVIC_InitTypeDef\000" + 2164 5F496E69 + 2164 74547970 + 2164 65446566 + 2164 00 + 2165 .LASF145: + 2166 03cd 4952516E .ascii "IRQn\000" + 2166 00 + 2167 .LASF35: + 2168 03d2 444D4131 .ascii "DMA1_Channel2_IRQn\000" + 2168 5F436861 + 2168 6E6E656C + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 43 + + + 2168 325F4952 + 2168 516E00 + 2169 .LASF13: + 2170 03e5 73697A65 .ascii "sizetype\000" + 2170 74797065 + 2170 00 + 2171 .LASF137: + 2172 03ee 4750494F .ascii "GPIO_Init\000" + 2172 5F496E69 + 2172 7400 + 2173 .LASF19: + 2174 03f8 53564361 .ascii "SVCall_IRQn\000" + 2174 6C6C5F49 + 2174 52516E00 + 2175 .LASF80: + 2176 0404 444D4132 .ascii "DMA2_Channel2_IRQn\000" + 2176 5F436861 + 2176 6E6E656C + 2176 325F4952 + 2176 516E00 + 2177 .LASF47: + 2178 0417 54494D31 .ascii "TIM1_BRK_TIM9_IRQn\000" + 2178 5F42524B + 2178 5F54494D + 2178 395F4952 + 2178 516E00 + 2179 .LASF126: + 2180 042a 62757474 .ascii "buttons_init\000" + 2180 6F6E735F + 2180 696E6974 + 2180 00 + 2181 .LASF73: + 2182 0437 54494D35 .ascii "TIM5_IRQn\000" + 2182 5F495251 + 2182 6E00 + 2183 .LASF119: + 2184 0441 4750494F .ascii "GPIO_Mode_AF_PP\000" + 2184 5F4D6F64 + 2184 655F4146 + 2184 5F505000 + 2185 .LASF59: + 2186 0451 53504932 .ascii "SPI2_IRQn\000" + 2186 5F495251 + 2186 6E00 + 2187 .LASF114: + 2188 045b 4750494F .ascii "GPIO_Mode_IPD\000" + 2188 5F4D6F64 + 2188 655F4950 + 2188 4400 + 2189 .LASF144: + 2190 0469 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 2190 73657273 + 2190 5C496D61 + 2190 6E6F6C5C + 2190 64657665 + 2191 0496 6C696361 .ascii "lications\\smartcities\000" + 2191 74696F6E + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 44 + + + 2191 735C736D + 2191 61727463 + 2191 69746965 + 2192 .LASF127: + 2193 04ac 4750494F .ascii "GPIO_InitStructure\000" + 2193 5F496E69 + 2193 74537472 + 2193 75637475 + 2193 726500 + 2194 .LASF124: + 2195 04bf 4750494F .ascii "GPIO_InitTypeDef\000" + 2195 5F496E69 + 2195 74547970 + 2195 65446566 + 2195 00 + 2196 .LASF87: + 2197 04d0 46756E63 .ascii "FunctionalState\000" + 2197 74696F6E + 2197 616C5374 + 2197 61746500 + 2198 .LASF117: + 2199 04e0 4750494F .ascii "GPIO_Mode_Out_PP\000" + 2199 5F4D6F64 + 2199 655F4F75 + 2199 745F5050 + 2199 00 + 2200 .LASF142: + 2201 04f1 474E5520 .ascii "GNU C 4.7.2\000" + 2201 4320342E + 2201 372E3200 + 2202 .LASF134: + 2203 04fd 7377335F .ascii "sw3_irqs\000" + 2203 69727173 + 2203 00 + 2204 .LASF100: + 2205 0506 45585449 .ascii "EXTI_Trigger\000" + 2205 5F547269 + 2205 67676572 + 2205 00 + 2206 .LASF128: + 2207 0513 45585449 .ascii "EXTI_InitStructure\000" + 2207 5F496E69 + 2207 74537472 + 2207 75637475 + 2207 726500 + 2208 .LASF34: + 2209 0526 444D4131 .ascii "DMA1_Channel1_IRQn\000" + 2209 5F436861 + 2209 6E6E656C + 2209 315F4952 + 2209 516E00 + 2210 .LASF99: + 2211 0539 45585449 .ascii "EXTI_Mode\000" + 2211 5F4D6F64 + 2211 6500 + 2212 .LASF91: + 2213 0543 45585449 .ascii "EXTI_Mode_Interrupt\000" + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 45 + + + 2213 5F4D6F64 + 2213 655F496E + 2213 74657272 + 2213 75707400 + 2214 .LASF60: + 2215 0557 55534152 .ascii "USART1_IRQn\000" + 2215 54315F49 + 2215 52516E00 + 2216 .LASF83: + 2217 0563 52455345 .ascii "RESET\000" + 2217 5400 + 2218 .LASF71: + 2219 0569 46534D43 .ascii "FSMC_IRQn\000" + 2219 5F495251 + 2219 6E00 + 2220 .LASF81: + 2221 0573 444D4132 .ascii "DMA2_Channel3_IRQn\000" + 2221 5F436861 + 2221 6E6E656C + 2221 335F4952 + 2221 516E00 + 2222 .LASF7: + 2223 0586 696E7433 .ascii "int32_t\000" + 2223 325F7400 + 2224 .LASF2: + 2225 058e 756E7369 .ascii "unsigned char\000" + 2225 676E6564 + 2225 20636861 + 2225 7200 + 2226 .LASF43: + 2227 059c 5553425F .ascii "USB_LP_CAN1_RX0_IRQn\000" + 2227 4C505F43 + 2227 414E315F + 2227 5258305F + 2227 4952516E + 2228 .LASF42: + 2229 05b1 5553425F .ascii "USB_HP_CAN1_TX_IRQn\000" + 2229 48505F43 + 2229 414E315F + 2229 54585F49 + 2229 52516E00 + 2230 .LASF132: + 2231 05c5 49544D5F .ascii "ITM_RxBuffer\000" + 2231 52784275 + 2231 66666572 + 2231 00 + 2232 .LASF77: + 2233 05d2 54494D36 .ascii "TIM6_IRQn\000" + 2233 5F495251 + 2233 6E00 + 2234 .LASF48: + 2235 05dc 54494D31 .ascii "TIM1_UP_TIM10_IRQn\000" + 2235 5F55505F + 2235 54494D31 + 2235 305F4952 + 2235 516E00 + 2236 .LASF33: + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 46 + + + 2237 05ef 45585449 .ascii "EXTI4_IRQn\000" + 2237 345F4952 + 2237 516E00 + 2238 .LASF95: + 2239 05fa 45585449 .ascii "EXTI_Trigger_Falling\000" + 2239 5F547269 + 2239 67676572 + 2239 5F46616C + 2239 6C696E67 + 2240 .LASF109: + 2241 060f 4750494F .ascii "GPIO_Speed_2MHz\000" + 2241 5F537065 + 2241 65645F32 + 2241 4D487A00 + 2242 .LASF76: + 2243 061f 55415254 .ascii "UART5_IRQn\000" + 2243 355F4952 + 2243 516E00 + 2244 .LASF49: + 2245 062a 54494D31 .ascii "TIM1_TRG_COM_TIM11_IRQn\000" + 2245 5F545247 + 2245 5F434F4D + 2245 5F54494D + 2245 31315F49 + 2246 .LASF82: + 2247 0642 444D4132 .ascii "DMA2_Channel4_5_IRQn\000" + 2247 5F436861 + 2247 6E6E656C + 2247 345F355F + 2247 4952516E + 2248 .LASF112: + 2249 0657 4750494F .ascii "GPIO_Mode_AIN\000" + 2249 5F4D6F64 + 2249 655F4149 + 2249 4E00 + 2250 .LASF68: + 2251 0665 54494D38 .ascii "TIM8_TRG_COM_TIM14_IRQn\000" + 2251 5F545247 + 2251 5F434F4D + 2251 5F54494D + 2251 31345F49 + 2252 .LASF27: + 2253 067d 464C4153 .ascii "FLASH_IRQn\000" + 2253 485F4952 + 2253 516E00 + 2254 .LASF9: + 2255 0688 75696E74 .ascii "uint32_t\000" + 2255 33325F74 + 2255 00 + 2256 .LASF105: + 2257 0691 4E564943 .ascii "NVIC_IRQChannelSubPriority\000" + 2257 5F495251 + 2257 4368616E + 2257 6E656C53 + 2257 75625072 + 2258 .LASF61: + 2259 06ac 55534152 .ascii "USART2_IRQn\000" + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 47 + + + 2259 54325F49 + 2259 52516E00 + 2260 .LASF18: + 2261 06b8 55736167 .ascii "UsageFault_IRQn\000" + 2261 65466175 + 2261 6C745F49 + 2261 52516E00 + 2262 .LASF14: + 2263 06c8 63686172 .ascii "char\000" + 2263 00 + 2264 .LASF136: + 2265 06cd 5243435F .ascii "RCC_APB2PeriphClockCmd\000" + 2265 41504232 + 2265 50657269 + 2265 7068436C + 2265 6F636B43 + 2266 .LASF64: + 2267 06e4 52544341 .ascii "RTCAlarm_IRQn\000" + 2267 6C61726D + 2267 5F495251 + 2267 6E00 + 2268 .LASF78: + 2269 06f2 54494D37 .ascii "TIM7_IRQn\000" + 2269 5F495251 + 2269 6E00 + 2270 .LASF15: + 2271 06fc 4E6F6E4D .ascii "NonMaskableInt_IRQn\000" + 2271 61736B61 + 2271 626C6549 + 2271 6E745F49 + 2271 52516E00 + 2272 .LASF139: + 2273 0710 4750494F .ascii "GPIO_EXTILineConfig\000" + 2273 5F455854 + 2273 494C696E + 2273 65436F6E + 2273 66696700 + 2274 .LASF97: + 2275 0724 45585449 .ascii "EXTITrigger_TypeDef\000" + 2275 54726967 + 2275 6765725F + 2275 54797065 + 2275 44656600 + 2276 .LASF123: + 2277 0738 4750494F .ascii "GPIO_Mode\000" + 2277 5F4D6F64 + 2277 6500 + 2278 .LASF102: + 2279 0742 45585449 .ascii "EXTI_InitTypeDef\000" + 2279 5F496E69 + 2279 74547970 + 2279 65446566 + 2279 00 + 2280 .LASF25: + 2281 0753 54414D50 .ascii "TAMPER_IRQn\000" + 2281 45525F49 + 2281 52516E00 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 48 + + + 2282 .LASF94: + 2283 075f 45585449 .ascii "EXTI_Trigger_Rising\000" + 2283 5F547269 + 2283 67676572 + 2283 5F526973 + 2283 696E6700 + 2284 .LASF65: + 2285 0773 55534257 .ascii "USBWakeUp_IRQn\000" + 2285 616B6555 + 2285 705F4952 + 2285 516E00 + 2286 .LASF62: + 2287 0782 55534152 .ascii "USART3_IRQn\000" + 2287 54335F49 + 2287 52516E00 + 2288 .LASF51: + 2289 078e 54494D32 .ascii "TIM2_IRQn\000" + 2289 5F495251 + 2289 6E00 + 2290 .LASF29: + 2291 0798 45585449 .ascii "EXTI0_IRQn\000" + 2291 305F4952 + 2291 516E00 + 2292 .LASF32: + 2293 07a3 45585449 .ascii "EXTI3_IRQn\000" + 2293 335F4952 + 2293 516E00 + 2294 .LASF147: + 2295 07ae 5F706F72 .ascii "_port_irq_epilogue\000" + 2295 745F6972 + 2295 715F6570 + 2295 696C6F67 + 2295 756500 + 2296 .LASF4: + 2297 07c1 75696E74 .ascii "uint8_t\000" + 2297 385F7400 + 2298 .LASF28: + 2299 07c9 5243435F .ascii "RCC_IRQn\000" + 2299 4952516E + 2299 00 + 2300 .LASF92: + 2301 07d2 45585449 .ascii "EXTI_Mode_Event\000" + 2301 5F4D6F64 + 2301 655F4576 + 2301 656E7400 + 2302 .LASF40: + 2303 07e2 444D4131 .ascii "DMA1_Channel7_IRQn\000" + 2303 5F436861 + 2303 6E6E656C + 2303 375F4952 + 2303 516E00 + 2304 .LASF20: + 2305 07f5 44656275 .ascii "DebugMonitor_IRQn\000" + 2305 674D6F6E + 2305 69746F72 + 2305 5F495251 + 2305 6E00 + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 49 + + + 2306 .LASF120: + 2307 0807 4750494F .ascii "GPIOMode_TypeDef\000" + 2307 4D6F6465 + 2307 5F547970 + 2307 65446566 + 2307 00 + 2308 .LASF55: + 2309 0818 49324331 .ascii "I2C1_ER_IRQn\000" + 2309 5F45525F + 2309 4952516E + 2309 00 + 2310 .LASF26: + 2311 0825 5254435F .ascii "RTC_IRQn\000" + 2311 4952516E + 2311 00 + 2312 .LASF74: + 2313 082e 53504933 .ascii "SPI3_IRQn\000" + 2313 5F495251 + 2313 6E00 + 2314 .LASF131: + 2315 0838 7072696E .ascii "printI\000" + 2315 744900 + 2316 .LASF143: + 2317 083f 62757474 .ascii "buttonExample.c\000" + 2317 6F6E4578 + 2317 616D706C + 2317 652E6300 + 2318 .LASF138: + 2319 084f 4E564943 .ascii "NVIC_Init\000" + 2319 5F496E69 + 2319 7400 + 2320 .LASF45: + 2321 0859 43414E31 .ascii "CAN1_SCE_IRQn\000" + 2321 5F534345 + 2321 5F495251 + 2321 6E00 + 2322 .LASF52: + 2323 0867 54494D33 .ascii "TIM3_IRQn\000" + 2323 5F495251 + 2323 6E00 + 2324 .LASF30: + 2325 0871 45585449 .ascii "EXTI1_IRQn\000" + 2325 315F4952 + 2325 516E00 + 2326 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\ccRw8XSb.s page 50 + + +DEFINED SYMBOLS + *ABS*:00000000 buttonExample.c +C:\cygwin\tmp\ccRw8XSb.s:19 .text.buttons_process:00000000 $t +C:\cygwin\tmp\ccRw8XSb.s:25 .text.buttons_process:00000000 buttons_process +C:\cygwin\tmp\ccRw8XSb.s:309 .bss.sw1_irqs:00000000 .LANCHOR0 +C:\cygwin\tmp\ccRw8XSb.s:334 .bss.sw3_irqs:00000000 .LANCHOR1 +C:\cygwin\tmp\ccRw8XSb.s:316 .rodata.str1.4:00000000 .LC0 +C:\cygwin\tmp\ccRw8XSb.s:50 .text.buttons_init:00000000 $t +C:\cygwin\tmp\ccRw8XSb.s:56 .text.buttons_init:00000000 buttons_init +C:\cygwin\tmp\ccRw8XSb.s:320 .rodata.str1.4:00000034 .LC1 +C:\cygwin\tmp\ccRw8XSb.s:322 .rodata.str1.4:00000050 .LC2 +C:\cygwin\tmp\ccRw8XSb.s:324 .rodata.str1.4:0000006c .LC3 +C:\cygwin\tmp\ccRw8XSb.s:219 .text.VectorE0:00000000 $t +C:\cygwin\tmp\ccRw8XSb.s:225 .text.VectorE0:00000000 VectorE0 +C:\cygwin\tmp\ccRw8XSb.s:297 .text.VectorE0:00000050 $d +C:\cygwin\tmp\ccRw8XSb.s:337 .bss.sw3_irqs:00000000 sw3_irqs +C:\cygwin\tmp\ccRw8XSb.s:312 .bss.sw1_irqs:00000000 sw1_irqs +C:\cygwin\tmp\ccRw8XSb.s:308 .bss.sw1_irqs:00000000 $d +C:\cygwin\tmp\ccRw8XSb.s:315 .rodata.str1.4:00000000 $d +C:\cygwin\tmp\ccRw8XSb.s:333 .bss.sw3_irqs:00000000 $d + .debug_frame:00000010 $d + +UNDEFINED SYMBOLS +print +RCC_APB2PeriphClockCmd +GPIO_Init +NVIC_Init +GPIO_EXTILineConfig +EXTI_Init +EXTI_GetITStatus +EXTI_ClearITPendingBit +printI +_port_irq_epilogue diff --git a/Project/applications/smartcities/build/lst/chcond.lst b/Project/applications/smartcities/build/lst/chcond.lst new file mode 100644 index 0000000..59bb740 --- /dev/null +++ b/Project/applications/smartcities/build/lst/chcond.lst @@ -0,0 +1,3482 @@ +ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "chcond.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text.chCondInit,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .global chCondInit + 22 .thumb + 23 .thumb_func + 24 .type chCondInit, %function + 25 chCondInit: + 26 .LFB7: + 27 .file 1 "../..//os/kernel/src/chcond.c" + 28 .loc 1 59 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .LVL0: + 34 .loc 1 63 0 + 35 0000 4060 str r0, [r0, #4] + 36 0002 0060 str r0, [r0, #0] + 37 0004 7047 bx lr + 38 .cfi_endproc + 39 .LFE7: + 40 .size chCondInit, .-chCondInit + 41 0006 00BFAFF3 .section .text.chCondSignal,"ax",%progbits + 41 0080AFF3 + 41 0080 + 42 .align 2 + 43 .p2align 4,,15 + 44 .global chCondSignal + 45 .thumb + 46 .thumb_func + 47 .type chCondSignal, %function + 48 chCondSignal: + 49 .LFB8: + 50 .loc 1 73 0 + 51 .cfi_startproc + 52 @ args = 0, pretend = 0, frame = 0 + 53 @ frame_needed = 0, uses_anonymous_args = 0 + 54 .LVL1: + 55 0000 08B5 push {r3, lr} + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 2 + + + 56 .LCFI0: + 57 .cfi_def_cfa_offset 8 + 58 .cfi_offset 3, -8 + 59 .cfi_offset 14, -4 + 60 .loc 1 73 0 + 61 0002 0346 mov r3, r0 + 62 .loc 1 77 0 + 63 @ 77 "../..//os/kernel/src/chcond.c" 1 + 64 0004 72B6 cpsid i + 65 @ 0 "" 2 + 66 .loc 1 78 0 + 67 .thumb + 68 0006 0068 ldr r0, [r0, #0] + 69 .LVL2: + 70 0008 9842 cmp r0, r3 + 71 000a 05D0 beq .L3 + 72 .LVL3: + 73 .LBB12: + 74 .LBB13: + 75 .file 2 "../..//os/kernel/include/chinline.h" + 76 .loc 2 62 0 + 77 000c 0268 ldr r2, [r0, #0] + 78 .LBE13: + 79 .LBE12: + 80 .loc 1 79 0 + 81 000e 0021 movs r1, #0 + 82 .LBB15: + 83 .LBB14: + 84 .loc 2 62 0 + 85 0010 1A60 str r2, [r3, #0] + 86 0012 5360 str r3, [r2, #4] + 87 .LBE14: + 88 .LBE15: + 89 .loc 1 79 0 + 90 0014 FFF7FEFF bl chSchWakeupS + 91 .LVL4: + 92 .L3: + 93 .loc 1 80 0 + 94 @ 80 "../..//os/kernel/src/chcond.c" 1 + 95 0018 62B6 cpsie i + 96 @ 0 "" 2 + 97 .thumb + 98 001a 08BD pop {r3, pc} + 99 .cfi_endproc + 100 .LFE8: + 101 .size chCondSignal, .-chCondSignal + 102 001c AFF30080 .section .text.chCondSignalI,"ax",%progbits + 103 .align 2 + 104 .p2align 4,,15 + 105 .global chCondSignalI + 106 .thumb + 107 .thumb_func + 108 .type chCondSignalI, %function + 109 chCondSignalI: + 110 .LFB9: + 111 .loc 1 94 0 + 112 .cfi_startproc + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 3 + + + 113 @ args = 0, pretend = 0, frame = 0 + 114 @ frame_needed = 0, uses_anonymous_args = 0 + 115 .LVL5: + 116 0000 08B5 push {r3, lr} + 117 .LCFI1: + 118 .cfi_def_cfa_offset 8 + 119 .cfi_offset 3, -8 + 120 .cfi_offset 14, -4 + 121 .loc 1 94 0 + 122 0002 0346 mov r3, r0 + 123 .loc 1 99 0 + 124 0004 0068 ldr r0, [r0, #0] + 125 .LVL6: + 126 0006 9842 cmp r0, r3 + 127 0008 06D0 beq .L5 + 128 .LVL7: + 129 .LBB16: + 130 .LBB17: + 131 .loc 2 62 0 + 132 000a 0268 ldr r2, [r0, #0] + 133 000c 1A60 str r2, [r3, #0] + 134 000e 5360 str r3, [r2, #4] + 135 .LBE17: + 136 .LBE16: + 137 .loc 1 100 0 + 138 0010 FFF7FEFF bl chSchReadyI + 139 .LVL8: + 140 0014 0023 movs r3, #0 + 141 0016 4362 str r3, [r0, #36] + 142 .LVL9: + 143 .L5: + 144 0018 08BD pop {r3, pc} + 145 .cfi_endproc + 146 .LFE9: + 147 .size chCondSignalI, .-chCondSignalI + 148 001a 00BFAFF3 .section .text.chCondBroadcastI,"ax",%progbits + 148 0080 + 149 .align 2 + 150 .p2align 4,,15 + 151 .global chCondBroadcastI + 152 .thumb + 153 .thumb_func + 154 .type chCondBroadcastI, %function + 155 chCondBroadcastI: + 156 .LFB11: + 157 .loc 1 129 0 + 158 .cfi_startproc + 159 @ args = 0, pretend = 0, frame = 0 + 160 @ frame_needed = 0, uses_anonymous_args = 0 + 161 .LVL10: + 162 0000 38B5 push {r3, r4, r5, lr} + 163 .LCFI2: + 164 .cfi_def_cfa_offset 16 + 165 .cfi_offset 3, -16 + 166 .cfi_offset 4, -12 + 167 .cfi_offset 5, -8 + 168 .cfi_offset 14, -4 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 4 + + + 169 .loc 1 129 0 + 170 0002 0446 mov r4, r0 + 171 .loc 1 137 0 + 172 0004 0068 ldr r0, [r0, #0] + 173 .LVL11: + 174 0006 A042 cmp r0, r4 + 175 0008 0AD0 beq .L7 + 176 .loc 1 138 0 + 177 000a 6FF00105 mvn r5, #1 + 178 .L11: + 179 .LVL12: + 180 .LBB18: + 181 .LBB19: + 182 .loc 2 62 0 + 183 000e 0368 ldr r3, [r0, #0] + 184 0010 2360 str r3, [r4, #0] + 185 0012 5C60 str r4, [r3, #4] + 186 .LBE19: + 187 .LBE18: + 188 .loc 1 138 0 + 189 0014 FFF7FEFF bl chSchReadyI + 190 .LVL13: + 191 0018 4562 str r5, [r0, #36] + 192 .loc 1 137 0 + 193 001a 2068 ldr r0, [r4, #0] + 194 001c A042 cmp r0, r4 + 195 001e F6D1 bne .L11 + 196 .LVL14: + 197 .L7: + 198 0020 38BD pop {r3, r4, r5, pc} + 199 .cfi_endproc + 200 .LFE11: + 201 .size chCondBroadcastI, .-chCondBroadcastI + 202 0022 00BFAFF3 .section .text.chCondBroadcast,"ax",%progbits + 202 0080AFF3 + 202 0080AFF3 + 202 0080 + 203 .align 2 + 204 .p2align 4,,15 + 205 .global chCondBroadcast + 206 .thumb + 207 .thumb_func + 208 .type chCondBroadcast, %function + 209 chCondBroadcast: + 210 .LFB10: + 211 .loc 1 110 0 + 212 .cfi_startproc + 213 @ args = 0, pretend = 0, frame = 0 + 214 @ frame_needed = 0, uses_anonymous_args = 0 + 215 .LVL15: + 216 0000 08B5 push {r3, lr} + 217 .LCFI3: + 218 .cfi_def_cfa_offset 8 + 219 .cfi_offset 3, -8 + 220 .cfi_offset 14, -4 + 221 .loc 1 112 0 + 222 @ 112 "../..//os/kernel/src/chcond.c" 1 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 5 + + + 223 0002 72B6 cpsid i + 224 @ 0 "" 2 + 225 .loc 1 113 0 + 226 .thumb + 227 0004 FFF7FEFF bl chCondBroadcastI + 228 .LVL16: + 229 .loc 1 114 0 + 230 0008 FFF7FEFF bl chSchRescheduleS + 231 .LVL17: + 232 .loc 1 115 0 + 233 @ 115 "../..//os/kernel/src/chcond.c" 1 + 234 000c 62B6 cpsie i + 235 @ 0 "" 2 + 236 .thumb + 237 000e 08BD pop {r3, pc} + 238 .cfi_endproc + 239 .LFE10: + 240 .size chCondBroadcast, .-chCondBroadcast + 241 .section .text.chCondWaitS,"ax",%progbits + 242 .align 2 + 243 .p2align 4,,15 + 244 .global chCondWaitS + 245 .thumb + 246 .thumb_func + 247 .type chCondWaitS, %function + 248 chCondWaitS: + 249 .LFB13: + 250 .loc 1 184 0 + 251 .cfi_startproc + 252 @ args = 0, pretend = 0, frame = 0 + 253 @ frame_needed = 0, uses_anonymous_args = 0 + 254 .LVL18: + 255 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 256 .LCFI4: + 257 .cfi_def_cfa_offset 24 + 258 .cfi_offset 3, -24 + 259 .cfi_offset 4, -20 + 260 .cfi_offset 5, -16 + 261 .cfi_offset 6, -12 + 262 .cfi_offset 7, -8 + 263 .cfi_offset 14, -4 + 264 .loc 1 185 0 + 265 0002 104B ldr r3, .L22 + 266 .loc 1 184 0 + 267 0004 0546 mov r5, r0 + 268 .loc 1 185 0 + 269 0006 DC69 ldr r4, [r3, #28] + 270 .LVL19: + 271 .loc 1 195 0 + 272 0008 FFF7FEFF bl chMtxUnlockS + 273 .LVL20: + 274 .loc 1 197 0 + 275 000c 2E46 mov r6, r5 + 276 .loc 1 195 0 + 277 000e 0746 mov r7, r0 + 278 .LVL21: + 279 .loc 1 196 0 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 6 + + + 280 0010 6562 str r5, [r4, #36] + 281 .loc 2 43 0 + 282 0012 2B46 mov r3, r5 + 283 0014 03E0 b .L16 + 284 .LVL22: + 285 .L21: + 286 .LBB20: + 287 .LBB21: + 288 .loc 2 46 0 + 289 0016 9968 ldr r1, [r3, #8] + 290 0018 A268 ldr r2, [r4, #8] + 291 001a 9142 cmp r1, r2 + 292 001c 10D3 bcc .L20 + 293 .L16: + 294 .loc 2 45 0 + 295 001e 1B68 ldr r3, [r3, #0] + 296 .LVL23: + 297 .loc 2 46 0 + 298 0020 9D42 cmp r5, r3 + 299 0022 F8D1 bne .L21 + 300 .L17: + 301 .loc 2 48 0 + 302 0024 7368 ldr r3, [r6, #4] + 303 .LVL24: + 304 .loc 2 47 0 + 305 0026 2660 str r6, [r4, #0] + 306 .loc 2 48 0 + 307 0028 6360 str r3, [r4, #4] + 308 .loc 2 49 0 + 309 002a 1C60 str r4, [r3, #0] + 310 002c 7460 str r4, [r6, #4] + 311 .LBE21: + 312 .LBE20: + 313 .loc 1 198 0 + 314 002e 0520 movs r0, #5 + 315 .LVL25: + 316 0030 FFF7FEFF bl chSchGoSleepS + 317 .LVL26: + 318 .loc 1 199 0 + 319 0034 646A ldr r4, [r4, #36] + 320 .LVL27: + 321 .loc 1 200 0 + 322 0036 3846 mov r0, r7 + 323 0038 FFF7FEFF bl chMtxLockS + 324 .LVL28: + 325 .loc 1 202 0 + 326 003c 2046 mov r0, r4 + 327 003e F8BD pop {r3, r4, r5, r6, r7, pc} + 328 .LVL29: + 329 .L20: + 330 .LBB23: + 331 .LBB22: + 332 .loc 2 46 0 + 333 0040 1E46 mov r6, r3 + 334 0042 EFE7 b .L17 + 335 .L23: + 336 .align 2 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 7 + + + 337 .L22: + 338 0044 00000000 .word rlist + 339 .LBE22: + 340 .LBE23: + 341 .cfi_endproc + 342 .LFE13: + 343 .size chCondWaitS, .-chCondWaitS + 344 0048 AFF30080 .section .text.chCondWait,"ax",%progbits + 344 AFF30080 + 345 .align 2 + 346 .p2align 4,,15 + 347 .global chCondWait + 348 .thumb + 349 .thumb_func + 350 .type chCondWait, %function + 351 chCondWait: + 352 .LFB12: + 353 .loc 1 158 0 + 354 .cfi_startproc + 355 @ args = 0, pretend = 0, frame = 0 + 356 @ frame_needed = 0, uses_anonymous_args = 0 + 357 .LVL30: + 358 0000 08B5 push {r3, lr} + 359 .LCFI5: + 360 .cfi_def_cfa_offset 8 + 361 .cfi_offset 3, -8 + 362 .cfi_offset 14, -4 + 363 .loc 1 161 0 + 364 @ 161 "../..//os/kernel/src/chcond.c" 1 + 365 0002 72B6 cpsid i + 366 @ 0 "" 2 + 367 .loc 1 162 0 + 368 .thumb + 369 0004 FFF7FEFF bl chCondWaitS + 370 .LVL31: + 371 .loc 1 163 0 + 372 @ 163 "../..//os/kernel/src/chcond.c" 1 + 373 0008 62B6 cpsie i + 374 @ 0 "" 2 + 375 .loc 1 165 0 + 376 .thumb + 377 000a 08BD pop {r3, pc} + 378 .cfi_endproc + 379 .LFE12: + 380 .size chCondWait, .-chCondWait + 381 000c AFF30080 .section .text.chCondWaitTimeoutS,"ax",%progbits + 382 .align 2 + 383 .p2align 4,,15 + 384 .global chCondWaitTimeoutS + 385 .thumb + 386 .thumb_func + 387 .type chCondWaitTimeoutS, %function + 388 chCondWaitTimeoutS: + 389 .LFB15: + 390 .loc 1 270 0 + 391 .cfi_startproc + 392 @ args = 0, pretend = 0, frame = 0 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 8 + + + 393 @ frame_needed = 0, uses_anonymous_args = 0 + 394 .LVL32: + 395 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 396 .LCFI6: + 397 .cfi_def_cfa_offset 24 + 398 .cfi_offset 4, -24 + 399 .cfi_offset 5, -20 + 400 .cfi_offset 6, -16 + 401 .cfi_offset 7, -12 + 402 .cfi_offset 8, -8 + 403 .cfi_offset 14, -4 + 404 .loc 1 270 0 + 405 0004 0646 mov r6, r0 + 406 0006 8846 mov r8, r1 + 407 .loc 1 280 0 + 408 0008 FFF7FEFF bl chMtxUnlockS + 409 .LVL33: + 410 .loc 1 281 0 + 411 000c 0E4A ldr r2, .L32 + 412 .loc 1 280 0 + 413 000e 0746 mov r7, r0 + 414 .LVL34: + 415 .loc 1 281 0 + 416 0010 D269 ldr r2, [r2, #28] + 417 .loc 2 43 0 + 418 0012 3346 mov r3, r6 + 419 .loc 1 281 0 + 420 0014 5662 str r6, [r2, #36] + 421 .LVL35: + 422 .L29: + 423 .LBB24: + 424 .LBB25: + 425 .loc 2 45 0 + 426 0016 1B68 ldr r3, [r3, #0] + 427 .LVL36: + 428 .loc 2 46 0 + 429 0018 9E42 cmp r6, r3 + 430 001a 03D0 beq .L30 + 431 001c 9D68 ldr r5, [r3, #8] + 432 001e 9468 ldr r4, [r2, #8] + 433 0020 A542 cmp r5, r4 + 434 0022 F8D2 bcs .L29 + 435 .L30: + 436 .loc 2 48 0 + 437 0024 5C68 ldr r4, [r3, #4] + 438 .LBE25: + 439 .LBE24: + 440 .loc 1 283 0 + 441 0026 0520 movs r0, #5 + 442 .LVL37: + 443 .LBB28: + 444 .LBB26: + 445 .loc 2 48 0 + 446 0028 82E81800 stmia r2, {r3, r4} + 447 .LBE26: + 448 .LBE28: + 449 .loc 1 283 0 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 9 + + + 450 002c 4146 mov r1, r8 + 451 .LBB29: + 452 .LBB27: + 453 .loc 2 49 0 + 454 002e 2260 str r2, [r4, #0] + 455 0030 5A60 str r2, [r3, #4] + 456 .LBE27: + 457 .LBE29: + 458 .loc 1 283 0 + 459 0032 FFF7FEFF bl chSchGoSleepTimeoutS + 460 .LVL38: + 461 .loc 1 284 0 + 462 0036 431C adds r3, r0, #1 + 463 .loc 1 283 0 + 464 0038 0446 mov r4, r0 + 465 .LVL39: + 466 .loc 1 284 0 + 467 003a 02D0 beq .L28 + 468 .loc 1 285 0 + 469 003c 3846 mov r0, r7 + 470 .LVL40: + 471 003e FFF7FEFF bl chMtxLockS + 472 .LVL41: + 473 .L28: + 474 .loc 1 287 0 + 475 0042 2046 mov r0, r4 + 476 0044 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 477 .L33: + 478 .align 2 + 479 .L32: + 480 0048 00000000 .word rlist + 481 .cfi_endproc + 482 .LFE15: + 483 .size chCondWaitTimeoutS, .-chCondWaitTimeoutS + 484 004c AFF30080 .section .text.chCondWaitTimeout,"ax",%progbits + 485 .align 2 + 486 .p2align 4,,15 + 487 .global chCondWaitTimeout + 488 .thumb + 489 .thumb_func + 490 .type chCondWaitTimeout, %function + 491 chCondWaitTimeout: + 492 .LFB14: + 493 .loc 1 233 0 + 494 .cfi_startproc + 495 @ args = 0, pretend = 0, frame = 0 + 496 @ frame_needed = 0, uses_anonymous_args = 0 + 497 .LVL42: + 498 0000 08B5 push {r3, lr} + 499 .LCFI7: + 500 .cfi_def_cfa_offset 8 + 501 .cfi_offset 3, -8 + 502 .cfi_offset 14, -4 + 503 .loc 1 236 0 + 504 @ 236 "../..//os/kernel/src/chcond.c" 1 + 505 0002 72B6 cpsid i + 506 @ 0 "" 2 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 10 + + + 507 .loc 1 237 0 + 508 .thumb + 509 0004 FFF7FEFF bl chCondWaitTimeoutS + 510 .LVL43: + 511 .loc 1 238 0 + 512 @ 238 "../..//os/kernel/src/chcond.c" 1 + 513 0008 62B6 cpsie i + 514 @ 0 "" 2 + 515 .loc 1 240 0 + 516 .thumb + 517 000a 08BD pop {r3, pc} + 518 .cfi_endproc + 519 .LFE14: + 520 .size chCondWaitTimeout, .-chCondWaitTimeout + 521 000c AFF30080 .text + 522 .Letext0: + 523 .file 3 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 524 .file 4 "../..//os/ports/GCC/ARMCMx/chtypes.h" + 525 .file 5 "../..//os/kernel/include/chlists.h" + 526 .file 6 "../..//os/kernel/include/chthreads.h" + 527 .file 7 "../..//os/ports/GCC/ARMCMx/chcore_v7m.h" + 528 .file 8 "../..//os/kernel/include/chschd.h" + 529 .file 9 "../..//os/kernel/include/chmtx.h" + 530 .file 10 "../..//os/kernel/include/chcond.h" + 531 .section .debug_info,"",%progbits + 532 .Ldebug_info0: + 533 0000 0D090000 .4byte 0x90d + 534 0004 0200 .2byte 0x2 + 535 0006 00000000 .4byte .Ldebug_abbrev0 + 536 000a 04 .byte 0x4 + 537 000b 01 .uleb128 0x1 + 538 000c D4010000 .4byte .LASF78 + 539 0010 01 .byte 0x1 + 540 0011 4A030000 .4byte .LASF79 + 541 0015 7F010000 .4byte .LASF80 + 542 0019 A0000000 .4byte .Ldebug_ranges0+0xa0 + 543 001d 00000000 .4byte 0 + 544 0021 00000000 .4byte 0 + 545 0025 00000000 .4byte .Ldebug_line0 + 546 0029 02 .uleb128 0x2 + 547 002a 04 .byte 0x4 + 548 002b 05 .byte 0x5 + 549 002c 696E7400 .ascii "int\000" + 550 0030 03 .uleb128 0x3 + 551 0031 04 .byte 0x4 + 552 0032 07 .byte 0x7 + 553 0033 E9000000 .4byte .LASF0 + 554 0037 03 .uleb128 0x3 + 555 0038 01 .byte 0x1 + 556 0039 06 .byte 0x6 + 557 003a 5E000000 .4byte .LASF1 + 558 003e 04 .uleb128 0x4 + 559 003f 42030000 .4byte .LASF5 + 560 0043 03 .byte 0x3 + 561 0044 2A .byte 0x2a + 562 0045 49000000 .4byte 0x49 + 563 0049 03 .uleb128 0x3 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 11 + + + 564 004a 01 .byte 0x1 + 565 004b 08 .byte 0x8 + 566 004c 2F020000 .4byte .LASF2 + 567 0050 03 .uleb128 0x3 + 568 0051 02 .byte 0x2 + 569 0052 05 .byte 0x5 + 570 0053 47020000 .4byte .LASF3 + 571 0057 03 .uleb128 0x3 + 572 0058 02 .byte 0x2 + 573 0059 07 .byte 0x7 + 574 005a 10010000 .4byte .LASF4 + 575 005e 04 .uleb128 0x4 + 576 005f 27020000 .4byte .LASF6 + 577 0063 03 .byte 0x3 + 578 0064 4F .byte 0x4f + 579 0065 69000000 .4byte 0x69 + 580 0069 03 .uleb128 0x3 + 581 006a 04 .byte 0x4 + 582 006b 05 .byte 0x5 + 583 006c 82000000 .4byte .LASF7 + 584 0070 04 .uleb128 0x4 + 585 0071 9E020000 .4byte .LASF8 + 586 0075 03 .byte 0x3 + 587 0076 50 .byte 0x50 + 588 0077 7B000000 .4byte 0x7b + 589 007b 03 .uleb128 0x3 + 590 007c 04 .byte 0x4 + 591 007d 07 .byte 0x7 + 592 007e F6000000 .4byte .LASF9 + 593 0082 03 .uleb128 0x3 + 594 0083 08 .byte 0x8 + 595 0084 05 .byte 0x5 + 596 0085 50000000 .4byte .LASF10 + 597 0089 03 .uleb128 0x3 + 598 008a 08 .byte 0x8 + 599 008b 07 .byte 0x7 + 600 008c 18000000 .4byte .LASF11 + 601 0090 04 .uleb128 0x4 + 602 0091 35010000 .4byte .LASF12 + 603 0095 04 .byte 0x4 + 604 0096 2F .byte 0x2f + 605 0097 3E000000 .4byte 0x3e + 606 009b 04 .uleb128 0x4 + 607 009c 8B000000 .4byte .LASF13 + 608 00a0 04 .byte 0x4 + 609 00a1 30 .byte 0x30 + 610 00a2 3E000000 .4byte 0x3e + 611 00a6 04 .uleb128 0x4 + 612 00a7 02020000 .4byte .LASF14 + 613 00ab 04 .byte 0x4 + 614 00ac 31 .byte 0x31 + 615 00ad 3E000000 .4byte 0x3e + 616 00b1 04 .uleb128 0x4 + 617 00b2 11020000 .4byte .LASF15 + 618 00b6 04 .byte 0x4 + 619 00b7 32 .byte 0x32 + 620 00b8 70000000 .4byte 0x70 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 12 + + + 621 00bc 04 .uleb128 0x4 + 622 00bd 23010000 .4byte .LASF16 + 623 00c1 04 .byte 0x4 + 624 00c2 33 .byte 0x33 + 625 00c3 5E000000 .4byte 0x5e + 626 00c7 04 .uleb128 0x4 + 627 00c8 49010000 .4byte .LASF17 + 628 00cc 04 .byte 0x4 + 629 00cd 35 .byte 0x35 + 630 00ce 70000000 .4byte 0x70 + 631 00d2 04 .uleb128 0x4 + 632 00d3 DF020000 .4byte .LASF18 + 633 00d7 04 .byte 0x4 + 634 00d8 36 .byte 0x36 + 635 00d9 70000000 .4byte 0x70 + 636 00dd 04 .uleb128 0x4 + 637 00de D6000000 .4byte .LASF19 + 638 00e2 04 .byte 0x4 + 639 00e3 37 .byte 0x37 + 640 00e4 5E000000 .4byte 0x5e + 641 00e8 04 .uleb128 0x4 + 642 00e9 76020000 .4byte .LASF20 + 643 00ed 05 .byte 0x5 + 644 00ee 2A .byte 0x2a + 645 00ef F3000000 .4byte 0xf3 + 646 00f3 05 .uleb128 0x5 + 647 00f4 76020000 .4byte .LASF20 + 648 00f8 48 .byte 0x48 + 649 00f9 06 .byte 0x6 + 650 00fa 5E .byte 0x5e + 651 00fb 0A020000 .4byte 0x20a + 652 00ff 06 .uleb128 0x6 + 653 0100 67020000 .4byte .LASF21 + 654 0104 06 .byte 0x6 + 655 0105 5F .byte 0x5f + 656 0106 2F020000 .4byte 0x22f + 657 010a 02 .byte 0x2 + 658 010b 23 .byte 0x23 + 659 010c 00 .uleb128 0 + 660 010d 06 .uleb128 0x6 + 661 010e 0A020000 .4byte .LASF22 + 662 0112 06 .byte 0x6 + 663 0113 61 .byte 0x61 + 664 0114 2F020000 .4byte 0x22f + 665 0118 02 .byte 0x2 + 666 0119 23 .byte 0x23 + 667 011a 04 .uleb128 0x4 + 668 011b 06 .uleb128 0x6 + 669 011c 49000000 .4byte .LASF23 + 670 0120 06 .byte 0x6 + 671 0121 63 .byte 0x63 + 672 0122 B1000000 .4byte 0xb1 + 673 0126 02 .byte 0x2 + 674 0127 23 .byte 0x23 + 675 0128 08 .uleb128 0x8 + 676 0129 06 .uleb128 0x6 + 677 012a AF030000 .4byte .LASF24 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 13 + + + 678 012e 06 .byte 0x6 + 679 012f 64 .byte 0x64 + 680 0130 FC020000 .4byte 0x2fc + 681 0134 02 .byte 0x2 + 682 0135 23 .byte 0x23 + 683 0136 0C .uleb128 0xc + 684 0137 06 .uleb128 0x6 + 685 0138 9F000000 .4byte .LASF25 + 686 013c 06 .byte 0x6 + 687 013d 66 .byte 0x66 + 688 013e 2F020000 .4byte 0x22f + 689 0142 02 .byte 0x2 + 690 0143 23 .byte 0x23 + 691 0144 10 .uleb128 0x10 + 692 0145 06 .uleb128 0x6 + 693 0146 77010000 .4byte .LASF26 + 694 014a 06 .byte 0x6 + 695 014b 67 .byte 0x67 + 696 014c 2F020000 .4byte 0x22f + 697 0150 02 .byte 0x2 + 698 0151 23 .byte 0x23 + 699 0152 14 .uleb128 0x14 + 700 0153 06 .uleb128 0x6 + 701 0154 6F030000 .4byte .LASF27 + 702 0158 06 .byte 0x6 + 703 0159 6E .byte 0x6e + 704 015a 44040000 .4byte 0x444 + 705 015e 02 .byte 0x2 + 706 015f 23 .byte 0x23 + 707 0160 18 .uleb128 0x18 + 708 0161 06 .uleb128 0x6 + 709 0162 51020000 .4byte .LASF28 + 710 0166 06 .byte 0x6 + 711 0167 79 .byte 0x79 + 712 0168 9B000000 .4byte 0x9b + 713 016c 02 .byte 0x2 + 714 016d 23 .byte 0x23 + 715 016e 1C .uleb128 0x1c + 716 016f 06 .uleb128 0x6 + 717 0170 6E020000 .4byte .LASF29 + 718 0174 06 .byte 0x6 + 719 0175 7D .byte 0x7d + 720 0176 90000000 .4byte 0x90 + 721 017a 02 .byte 0x2 + 722 017b 23 .byte 0x23 + 723 017c 1D .uleb128 0x1d + 724 017d 06 .uleb128 0x6 + 725 017e 2B030000 .4byte .LASF30 + 726 0182 06 .byte 0x6 + 727 0183 82 .byte 0x82 + 728 0184 A6000000 .4byte 0xa6 + 729 0188 02 .byte 0x2 + 730 0189 23 .byte 0x23 + 731 018a 1E .uleb128 0x1e + 732 018b 06 .uleb128 0x6 + 733 018c FF020000 .4byte .LASF31 + 734 0190 06 .byte 0x6 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 14 + + + 735 0191 89 .byte 0x89 + 736 0192 26030000 .4byte 0x326 + 737 0196 02 .byte 0x2 + 738 0197 23 .byte 0x23 + 739 0198 20 .uleb128 0x20 + 740 0199 07 .uleb128 0x7 + 741 019a 705F7500 .ascii "p_u\000" + 742 019e 06 .byte 0x6 + 743 019f AE .byte 0xae + 744 01a0 0F040000 .4byte 0x40f + 745 01a4 02 .byte 0x2 + 746 01a5 23 .byte 0x23 + 747 01a6 24 .uleb128 0x24 + 748 01a7 06 .uleb128 0x6 + 749 01a8 B5030000 .4byte .LASF32 + 750 01ac 06 .byte 0x6 + 751 01ad B3 .byte 0xb3 + 752 01ae 57020000 .4byte 0x257 + 753 01b2 02 .byte 0x2 + 754 01b3 23 .byte 0x23 + 755 01b4 28 .uleb128 0x28 + 756 01b5 06 .uleb128 0x6 + 757 01b6 13030000 .4byte .LASF33 + 758 01ba 06 .byte 0x6 + 759 01bb B9 .byte 0xb9 + 760 01bc 35020000 .4byte 0x235 + 761 01c0 02 .byte 0x2 + 762 01c1 23 .byte 0x23 + 763 01c2 2C .uleb128 0x2c + 764 01c3 06 .uleb128 0x6 + 765 01c4 00000000 .4byte .LASF34 + 766 01c8 06 .byte 0x6 + 767 01c9 BD .byte 0xbd + 768 01ca BC000000 .4byte 0xbc + 769 01ce 02 .byte 0x2 + 770 01cf 23 .byte 0x23 + 771 01d0 34 .uleb128 0x34 + 772 01d1 06 .uleb128 0x6 + 773 01d2 93020000 .4byte .LASF35 + 774 01d6 06 .byte 0x6 + 775 01d7 C3 .byte 0xc3 + 776 01d8 C7000000 .4byte 0xc7 + 777 01dc 02 .byte 0x2 + 778 01dd 23 .byte 0x23 + 779 01de 38 .uleb128 0x38 + 780 01df 06 .uleb128 0x6 + 781 01e0 3D020000 .4byte .LASF36 + 782 01e4 06 .byte 0x6 + 783 01e5 CA .byte 0xca + 784 01e6 56040000 .4byte 0x456 + 785 01ea 02 .byte 0x2 + 786 01eb 23 .byte 0x23 + 787 01ec 3C .uleb128 0x3c + 788 01ed 06 .uleb128 0x6 + 789 01ee E9020000 .4byte .LASF37 + 790 01f2 06 .byte 0x6 + 791 01f3 CE .byte 0xce + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 15 + + + 792 01f4 B1000000 .4byte 0xb1 + 793 01f8 02 .byte 0x2 + 794 01f9 23 .byte 0x23 + 795 01fa 40 .uleb128 0x40 + 796 01fb 06 .uleb128 0x6 + 797 01fc 6A000000 .4byte .LASF38 + 798 0200 06 .byte 0x6 + 799 0201 D4 .byte 0xd4 + 800 0202 6D020000 .4byte 0x26d + 801 0206 02 .byte 0x2 + 802 0207 23 .byte 0x23 + 803 0208 44 .uleb128 0x44 + 804 0209 00 .byte 0 + 805 020a 08 .uleb128 0x8 + 806 020b 08 .byte 0x8 + 807 020c 05 .byte 0x5 + 808 020d 61 .byte 0x61 + 809 020e 2F020000 .4byte 0x22f + 810 0212 06 .uleb128 0x6 + 811 0213 67020000 .4byte .LASF21 + 812 0217 05 .byte 0x5 + 813 0218 62 .byte 0x62 + 814 0219 2F020000 .4byte 0x22f + 815 021d 02 .byte 0x2 + 816 021e 23 .byte 0x23 + 817 021f 00 .uleb128 0 + 818 0220 06 .uleb128 0x6 + 819 0221 0A020000 .4byte .LASF22 + 820 0225 05 .byte 0x5 + 821 0226 64 .byte 0x64 + 822 0227 2F020000 .4byte 0x22f + 823 022b 02 .byte 0x2 + 824 022c 23 .byte 0x23 + 825 022d 04 .uleb128 0x4 + 826 022e 00 .byte 0 + 827 022f 09 .uleb128 0x9 + 828 0230 04 .byte 0x4 + 829 0231 E8000000 .4byte 0xe8 + 830 0235 04 .uleb128 0x4 + 831 0236 C2010000 .4byte .LASF39 + 832 023a 05 .byte 0x5 + 833 023b 66 .byte 0x66 + 834 023c 0A020000 .4byte 0x20a + 835 0240 08 .uleb128 0x8 + 836 0241 04 .byte 0x4 + 837 0242 05 .byte 0x5 + 838 0243 6B .byte 0x6b + 839 0244 57020000 .4byte 0x257 + 840 0248 06 .uleb128 0x6 + 841 0249 67020000 .4byte .LASF21 + 842 024d 05 .byte 0x5 + 843 024e 6D .byte 0x6d + 844 024f 2F020000 .4byte 0x22f + 845 0253 02 .byte 0x2 + 846 0254 23 .byte 0x23 + 847 0255 00 .uleb128 0 + 848 0256 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 16 + + + 849 0257 04 .uleb128 0x4 + 850 0258 3D010000 .4byte .LASF40 + 851 025c 05 .byte 0x5 + 852 025d 70 .byte 0x70 + 853 025e 40020000 .4byte 0x240 + 854 0262 04 .uleb128 0x4 + 855 0263 C0000000 .4byte .LASF41 + 856 0267 07 .byte 0x7 + 857 0268 D7 .byte 0xd7 + 858 0269 6D020000 .4byte 0x26d + 859 026d 0A .uleb128 0xa + 860 026e 04 .byte 0x4 + 861 026f 05 .uleb128 0x5 + 862 0270 0C030000 .4byte .LASF42 + 863 0274 24 .byte 0x24 + 864 0275 07 .byte 0x7 + 865 0276 FE .byte 0xfe + 866 0277 FC020000 .4byte 0x2fc + 867 027b 0B .uleb128 0xb + 868 027c 723400 .ascii "r4\000" + 869 027f 07 .byte 0x7 + 870 0280 1101 .2byte 0x111 + 871 0282 62020000 .4byte 0x262 + 872 0286 02 .byte 0x2 + 873 0287 23 .byte 0x23 + 874 0288 00 .uleb128 0 + 875 0289 0B .uleb128 0xb + 876 028a 723500 .ascii "r5\000" + 877 028d 07 .byte 0x7 + 878 028e 1201 .2byte 0x112 + 879 0290 62020000 .4byte 0x262 + 880 0294 02 .byte 0x2 + 881 0295 23 .byte 0x23 + 882 0296 04 .uleb128 0x4 + 883 0297 0B .uleb128 0xb + 884 0298 723600 .ascii "r6\000" + 885 029b 07 .byte 0x7 + 886 029c 1301 .2byte 0x113 + 887 029e 62020000 .4byte 0x262 + 888 02a2 02 .byte 0x2 + 889 02a3 23 .byte 0x23 + 890 02a4 08 .uleb128 0x8 + 891 02a5 0B .uleb128 0xb + 892 02a6 723700 .ascii "r7\000" + 893 02a9 07 .byte 0x7 + 894 02aa 1401 .2byte 0x114 + 895 02ac 62020000 .4byte 0x262 + 896 02b0 02 .byte 0x2 + 897 02b1 23 .byte 0x23 + 898 02b2 0C .uleb128 0xc + 899 02b3 0B .uleb128 0xb + 900 02b4 723800 .ascii "r8\000" + 901 02b7 07 .byte 0x7 + 902 02b8 1501 .2byte 0x115 + 903 02ba 62020000 .4byte 0x262 + 904 02be 02 .byte 0x2 + 905 02bf 23 .byte 0x23 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 17 + + + 906 02c0 10 .uleb128 0x10 + 907 02c1 0B .uleb128 0xb + 908 02c2 723900 .ascii "r9\000" + 909 02c5 07 .byte 0x7 + 910 02c6 1601 .2byte 0x116 + 911 02c8 62020000 .4byte 0x262 + 912 02cc 02 .byte 0x2 + 913 02cd 23 .byte 0x23 + 914 02ce 14 .uleb128 0x14 + 915 02cf 0B .uleb128 0xb + 916 02d0 72313000 .ascii "r10\000" + 917 02d4 07 .byte 0x7 + 918 02d5 1701 .2byte 0x117 + 919 02d7 62020000 .4byte 0x262 + 920 02db 02 .byte 0x2 + 921 02dc 23 .byte 0x23 + 922 02dd 18 .uleb128 0x18 + 923 02de 0B .uleb128 0xb + 924 02df 72313100 .ascii "r11\000" + 925 02e3 07 .byte 0x7 + 926 02e4 1801 .2byte 0x118 + 927 02e6 62020000 .4byte 0x262 + 928 02ea 02 .byte 0x2 + 929 02eb 23 .byte 0x23 + 930 02ec 1C .uleb128 0x1c + 931 02ed 0B .uleb128 0xb + 932 02ee 6C7200 .ascii "lr\000" + 933 02f1 07 .byte 0x7 + 934 02f2 1901 .2byte 0x119 + 935 02f4 62020000 .4byte 0x262 + 936 02f8 02 .byte 0x2 + 937 02f9 23 .byte 0x23 + 938 02fa 20 .uleb128 0x20 + 939 02fb 00 .byte 0 + 940 02fc 0C .uleb128 0xc + 941 02fd 08010000 .4byte .LASF43 + 942 0301 04 .byte 0x4 + 943 0302 07 .byte 0x7 + 944 0303 2301 .2byte 0x123 + 945 0305 19030000 .4byte 0x319 + 946 0309 0B .uleb128 0xb + 947 030a 72313300 .ascii "r13\000" + 948 030e 07 .byte 0x7 + 949 030f 2401 .2byte 0x124 + 950 0311 19030000 .4byte 0x319 + 951 0315 02 .byte 0x2 + 952 0316 23 .byte 0x23 + 953 0317 00 .uleb128 0 + 954 0318 00 .byte 0 + 955 0319 09 .uleb128 0x9 + 956 031a 04 .byte 0x4 + 957 031b 6F020000 .4byte 0x26f + 958 031f 03 .uleb128 0x3 + 959 0320 04 .byte 0x4 + 960 0321 07 .byte 0x7 + 961 0322 5B010000 .4byte .LASF44 + 962 0326 0D .uleb128 0xd + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 18 + + + 963 0327 D2000000 .4byte 0xd2 + 964 032b 08 .uleb128 0x8 + 965 032c 20 .byte 0x20 + 966 032d 08 .byte 0x8 + 967 032e 5E .byte 0x5e + 968 032f 96030000 .4byte 0x396 + 969 0333 06 .uleb128 0x6 + 970 0334 A7020000 .4byte .LASF45 + 971 0338 08 .byte 0x8 + 972 0339 5F .byte 0x5f + 973 033a 35020000 .4byte 0x235 + 974 033e 02 .byte 0x2 + 975 033f 23 .byte 0x23 + 976 0340 00 .uleb128 0 + 977 0341 06 .uleb128 0x6 + 978 0342 59020000 .4byte .LASF46 + 979 0346 08 .byte 0x8 + 980 0347 60 .byte 0x60 + 981 0348 B1000000 .4byte 0xb1 + 982 034c 02 .byte 0x2 + 983 034d 23 .byte 0x23 + 984 034e 08 .uleb128 0x8 + 985 034f 06 .uleb128 0x6 + 986 0350 06030000 .4byte .LASF47 + 987 0354 08 .byte 0x8 + 988 0355 62 .byte 0x62 + 989 0356 FC020000 .4byte 0x2fc + 990 035a 02 .byte 0x2 + 991 035b 23 .byte 0x23 + 992 035c 0C .uleb128 0xc + 993 035d 06 .uleb128 0x6 + 994 035e B8000000 .4byte .LASF48 + 995 0362 08 .byte 0x8 + 996 0363 65 .byte 0x65 + 997 0364 2F020000 .4byte 0x22f + 998 0368 02 .byte 0x2 + 999 0369 23 .byte 0x23 + 1000 036a 10 .uleb128 0x10 + 1001 036b 06 .uleb128 0x6 + 1002 036c EA010000 .4byte .LASF49 + 1003 0370 08 .byte 0x8 + 1004 0371 66 .byte 0x66 + 1005 0372 2F020000 .4byte 0x22f + 1006 0376 02 .byte 0x2 + 1007 0377 23 .byte 0x23 + 1008 0378 14 .uleb128 0x14 + 1009 0379 06 .uleb128 0x6 + 1010 037a 9D030000 .4byte .LASF50 + 1011 037e 08 .byte 0x8 + 1012 037f 6A .byte 0x6a + 1013 0380 DD000000 .4byte 0xdd + 1014 0384 02 .byte 0x2 + 1015 0385 23 .byte 0x23 + 1016 0386 18 .uleb128 0x18 + 1017 0387 06 .uleb128 0x6 + 1018 0388 E0010000 .4byte .LASF51 + 1019 038c 08 .byte 0x8 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 19 + + + 1020 038d 6C .byte 0x6c + 1021 038e 2F020000 .4byte 0x22f + 1022 0392 02 .byte 0x2 + 1023 0393 23 .byte 0x23 + 1024 0394 1C .uleb128 0x1c + 1025 0395 00 .byte 0 + 1026 0396 04 .uleb128 0x4 + 1027 0397 32030000 .4byte .LASF52 + 1028 039b 08 .byte 0x8 + 1029 039c 6E .byte 0x6e + 1030 039d 2B030000 .4byte 0x32b + 1031 03a1 05 .uleb128 0x5 + 1032 03a2 55010000 .4byte .LASF53 + 1033 03a6 10 .byte 0x10 + 1034 03a7 09 .byte 0x9 + 1035 03a8 2C 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51060000 .4byte 0x651 + 1461 074b 1E .uleb128 0x1e + 1462 074c 01 .byte 0x1 + 1463 074d 50 .byte 0x50 + 1464 074e 03 .byte 0x3 + 1465 074f F3 .byte 0xf3 + 1466 0750 01 .uleb128 0x1 + 1467 0751 50 .byte 0x50 + 1468 0752 00 .byte 0 + 1469 0753 00 .byte 0 + 1470 0754 27 .uleb128 0x27 + 1471 0755 01 .byte 0x1 + 1472 0756 64010000 .4byte .LASF71 + 1473 075a 01 .byte 0x1 + 1474 075b 0E01 .2byte 0x10e + 1475 075d 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 27 + + + 1476 075e BC000000 .4byte 0xbc + 1477 0762 00000000 .4byte .LFB15 + 1478 0766 4C000000 .4byte .LFE15 + 1479 076a C5020000 .4byte .LLST23 + 1480 076e 01 .byte 0x1 + 1481 076f 18080000 .4byte 0x818 + 1482 0773 28 .uleb128 0x28 + 1483 0774 637000 .ascii "cp\000" + 1484 0777 01 .byte 0x1 + 1485 0778 0E01 .2byte 0x10e + 1486 077a DC040000 .4byte 0x4dc + 1487 077e E5020000 .4byte .LLST24 + 1488 0782 29 .uleb128 0x29 + 1489 0783 CF010000 .4byte .LASF72 + 1490 0787 01 .byte 0x1 + 1491 0788 0E01 .2byte 0x10e + 1492 078a D2000000 .4byte 0xd2 + 1493 078e 03030000 .4byte .LLST25 + 1494 0792 2A .uleb128 0x2a + 1495 0793 6D7000 .ascii "mp\000" + 1496 0796 01 .byte 0x1 + 1497 0797 0F01 .2byte 0x10f + 1498 0799 56040000 .4byte 0x456 + 1499 079d 21030000 .4byte .LLST26 + 1500 07a1 2A .uleb128 0x2a + 1501 07a2 6D736700 .ascii "msg\000" + 1502 07a6 01 .byte 0x1 + 1503 07a7 1001 .2byte 0x110 + 1504 07a9 BC000000 .4byte 0xbc + 1505 07ad 3F030000 .4byte .LLST27 + 1506 07b1 2B .uleb128 0x2b + 1507 07b2 89040000 .4byte 0x489 + 1508 07b6 16000000 .4byte .LBB24 + 1509 07ba 60000000 .4byte .Ldebug_ranges0+0x60 + 1510 07be 01 .byte 0x1 + 1511 07bf 1A01 .2byte 0x11a + 1512 07c1 E5070000 .4byte 0x7e5 + 1513 07c5 25 .uleb128 0x25 + 1514 07c6 A0040000 .4byte 0x4a0 + 1515 07ca 01 .byte 0x1 + 1516 07cb 56 .byte 0x56 + 1517 07cc 1A .uleb128 0x1a + 1518 07cd 96040000 .4byte 0x496 + 1519 07d1 5D030000 .4byte .LLST28 + 1520 07d5 1B .uleb128 0x1b + 1521 07d6 80000000 .4byte .Ldebug_ranges0+0x80 + 1522 07da 1C .uleb128 0x1c + 1523 07db AB040000 .4byte 0x4ab + 1524 07df 70030000 .4byte .LLST29 + 1525 07e3 00 .byte 0 + 1526 07e4 00 .byte 0 + 1527 07e5 21 .uleb128 0x21 + 1528 07e6 0C000000 .4byte .LVL33 + 1529 07ea C1080000 .4byte 0x8c1 + 1530 07ee 22 .uleb128 0x22 + 1531 07ef 36000000 .4byte .LVL38 + 1532 07f3 F7080000 .4byte 0x8f7 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 28 + + + 1533 07f7 07080000 .4byte 0x807 + 1534 07fb 1E .uleb128 0x1e + 1535 07fc 01 .byte 0x1 + 1536 07fd 51 .byte 0x51 + 1537 07fe 02 .byte 0x2 + 1538 07ff 78 .byte 0x78 + 1539 0800 00 .sleb128 0 + 1540 0801 1E .uleb128 0x1e + 1541 0802 01 .byte 0x1 + 1542 0803 50 .byte 0x50 + 1543 0804 01 .byte 0x1 + 1544 0805 35 .byte 0x35 + 1545 0806 00 .byte 0 + 1546 0807 1D .uleb128 0x1d + 1547 0808 42000000 .4byte .LVL41 + 1548 080c E3080000 .4byte 0x8e3 + 1549 0810 1E .uleb128 0x1e + 1550 0811 01 .byte 0x1 + 1551 0812 50 .byte 0x50 + 1552 0813 02 .byte 0x2 + 1553 0814 77 .byte 0x77 + 1554 0815 00 .sleb128 0 + 1555 0816 00 .byte 0 + 1556 0817 00 .byte 0 + 1557 0818 23 .uleb128 0x23 + 1558 0819 01 .byte 0x1 + 1559 081a 76030000 .4byte .LASF73 + 1560 081e 01 .byte 0x1 + 1561 081f E9 .byte 0xe9 + 1562 0820 01 .byte 0x1 + 1563 0821 BC000000 .4byte 0xbc + 1564 0825 00000000 .4byte .LFB14 + 1565 0829 0C000000 .4byte .LFE14 + 1566 082d 83030000 .4byte .LLST30 + 1567 0831 01 .byte 0x1 + 1568 0832 79080000 .4byte 0x879 + 1569 0836 18 .uleb128 0x18 + 1570 0837 637000 .ascii "cp\000" + 1571 083a 01 .byte 0x1 + 1572 083b E9 .byte 0xe9 + 1573 083c DC040000 .4byte 0x4dc + 1574 0840 A3030000 .4byte .LLST31 + 1575 0844 2C .uleb128 0x2c + 1576 0845 CF010000 .4byte .LASF72 + 1577 0849 01 .byte 0x1 + 1578 084a E9 .byte 0xe9 + 1579 084b D2000000 .4byte 0xd2 + 1580 084f C4030000 .4byte .LLST32 + 1581 0853 26 .uleb128 0x26 + 1582 0854 6D736700 .ascii "msg\000" + 1583 0858 01 .byte 0x1 + 1584 0859 EA .byte 0xea + 1585 085a BC000000 .4byte 0xbc + 1586 085e 01 .byte 0x1 + 1587 085f 50 .byte 0x50 + 1588 0860 1D .uleb128 0x1d + 1589 0861 08000000 .4byte .LVL43 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 29 + + + 1590 0865 54070000 .4byte 0x754 + 1591 0869 1E .uleb128 0x1e + 1592 086a 01 .byte 0x1 + 1593 086b 51 .byte 0x51 + 1594 086c 03 .byte 0x3 + 1595 086d F3 .byte 0xf3 + 1596 086e 01 .uleb128 0x1 + 1597 086f 51 .byte 0x51 + 1598 0870 1E .uleb128 0x1e + 1599 0871 01 .byte 0x1 + 1600 0872 50 .byte 0x50 + 1601 0873 03 .byte 0x3 + 1602 0874 F3 .byte 0xf3 + 1603 0875 01 .uleb128 0x1 + 1604 0876 50 .byte 0x50 + 1605 0877 00 .byte 0 + 1606 0878 00 .byte 0 + 1607 0879 2D .uleb128 0x2d + 1608 087a 3C030000 .4byte .LASF83 + 1609 087e 08 .byte 0x8 + 1610 087f 72 .byte 0x72 + 1611 0880 96030000 .4byte 0x396 + 1612 0884 01 .byte 0x1 + 1613 0885 01 .byte 0x1 + 1614 0886 2E .uleb128 0x2e + 1615 0887 01 .byte 0x1 + 1616 0888 1E030000 .4byte .LASF74 + 1617 088c 08 .byte 0x8 + 1618 088d 9C .byte 0x9c + 1619 088e 01 .byte 0x1 + 1620 088f 01 .byte 0x1 + 1621 0890 9F080000 .4byte 0x89f + 1622 0894 2F .uleb128 0x2f + 1623 0895 2F020000 .4byte 0x22f + 1624 0899 2F .uleb128 0x2f + 1625 089a BC000000 .4byte 0xbc + 1626 089e 00 .byte 0 + 1627 089f 30 .uleb128 0x30 + 1628 08a0 01 .byte 0x1 + 1629 08a1 AF020000 .4byte .LASF84 + 1630 08a5 08 .byte 0x8 + 1631 08a6 93 .byte 0x93 + 1632 08a7 01 .byte 0x1 + 1633 08a8 2F020000 .4byte 0x22f + 1634 08ac 01 .byte 0x1 + 1635 08ad B7080000 .4byte 0x8b7 + 1636 08b1 2F .uleb128 0x2f + 1637 08b2 2F020000 .4byte 0x22f + 1638 08b6 00 .byte 0 + 1639 08b7 31 .uleb128 0x31 + 1640 08b8 01 .byte 0x1 + 1641 08b9 A7000000 .4byte .LASF85 + 1642 08bd 08 .byte 0x8 + 1643 08be 9F .byte 0x9f + 1644 08bf 01 .byte 0x1 + 1645 08c0 01 .byte 0x1 + 1646 08c1 32 .uleb128 0x32 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 30 + + + 1647 08c2 01 .byte 0x1 + 1648 08c3 DC000000 .4byte .LASF86 + 1649 08c7 09 .byte 0x9 + 1650 08c8 3E .byte 0x3e + 1651 08c9 01 .byte 0x1 + 1652 08ca 56040000 .4byte 0x456 + 1653 08ce 01 .byte 0x1 + 1654 08cf 2E .uleb128 0x2e + 1655 08d0 01 .byte 0x1 + 1656 08d1 85020000 .4byte .LASF75 + 1657 08d5 08 .byte 0x8 + 1658 08d6 96 .byte 0x96 + 1659 08d7 01 .byte 0x1 + 1660 08d8 01 .byte 0x1 + 1661 08d9 E3080000 .4byte 0x8e3 + 1662 08dd 2F .uleb128 0x2f + 1663 08de 9B000000 .4byte 0x9b + 1664 08e2 00 .byte 0 + 1665 08e3 2E .uleb128 0x2e + 1666 08e4 01 .byte 0x1 + 1667 08e5 94000000 .4byte .LASF76 + 1668 08e9 09 .byte 0x9 + 1669 08ea 3A .byte 0x3a + 1670 08eb 01 .byte 0x1 + 1671 08ec 01 .byte 0x1 + 1672 08ed F7080000 .4byte 0x8f7 + 1673 08f1 2F .uleb128 0x2f + 1674 08f2 56040000 .4byte 0x456 + 1675 08f6 00 .byte 0 + 1676 08f7 33 .uleb128 0x33 + 1677 08f8 01 .byte 0x1 + 1678 08f9 88030000 .4byte .LASF77 + 1679 08fd 08 .byte 0x8 + 1680 08fe 99 .byte 0x99 + 1681 08ff 01 .byte 0x1 + 1682 0900 BC000000 .4byte 0xbc + 1683 0904 01 .byte 0x1 + 1684 0905 2F .uleb128 0x2f + 1685 0906 9B000000 .4byte 0x9b + 1686 090a 2F .uleb128 0x2f + 1687 090b D2000000 .4byte 0xd2 + 1688 090f 00 .byte 0 + 1689 0910 00 .byte 0 + 1690 .section .debug_abbrev,"",%progbits + 1691 .Ldebug_abbrev0: + 1692 0000 01 .uleb128 0x1 + 1693 0001 11 .uleb128 0x11 + 1694 0002 01 .byte 0x1 + 1695 0003 25 .uleb128 0x25 + 1696 0004 0E .uleb128 0xe + 1697 0005 13 .uleb128 0x13 + 1698 0006 0B .uleb128 0xb + 1699 0007 03 .uleb128 0x3 + 1700 0008 0E .uleb128 0xe + 1701 0009 1B .uleb128 0x1b + 1702 000a 0E .uleb128 0xe + 1703 000b 55 .uleb128 0x55 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 31 + + + 1704 000c 06 .uleb128 0x6 + 1705 000d 11 .uleb128 0x11 + 1706 000e 01 .uleb128 0x1 + 1707 000f 52 .uleb128 0x52 + 1708 0010 01 .uleb128 0x1 + 1709 0011 10 .uleb128 0x10 + 1710 0012 06 .uleb128 0x6 + 1711 0013 00 .byte 0 + 1712 0014 00 .byte 0 + 1713 0015 02 .uleb128 0x2 + 1714 0016 24 .uleb128 0x24 + 1715 0017 00 .byte 0 + 1716 0018 0B .uleb128 0xb + 1717 0019 0B .uleb128 0xb + 1718 001a 3E .uleb128 0x3e + 1719 001b 0B .uleb128 0xb + 1720 001c 03 .uleb128 0x3 + 1721 001d 08 .uleb128 0x8 + 1722 001e 00 .byte 0 + 1723 001f 00 .byte 0 + 1724 0020 03 .uleb128 0x3 + 1725 0021 24 .uleb128 0x24 + 1726 0022 00 .byte 0 + 1727 0023 0B .uleb128 0xb + 1728 0024 0B .uleb128 0xb + 1729 0025 3E .uleb128 0x3e + 1730 0026 0B .uleb128 0xb + 1731 0027 03 .uleb128 0x3 + 1732 0028 0E .uleb128 0xe + 1733 0029 00 .byte 0 + 1734 002a 00 .byte 0 + 1735 002b 04 .uleb128 0x4 + 1736 002c 16 .uleb128 0x16 + 1737 002d 00 .byte 0 + 1738 002e 03 .uleb128 0x3 + 1739 002f 0E .uleb128 0xe + 1740 0030 3A .uleb128 0x3a + 1741 0031 0B .uleb128 0xb + 1742 0032 3B .uleb128 0x3b + 1743 0033 0B .uleb128 0xb + 1744 0034 49 .uleb128 0x49 + 1745 0035 13 .uleb128 0x13 + 1746 0036 00 .byte 0 + 1747 0037 00 .byte 0 + 1748 0038 05 .uleb128 0x5 + 1749 0039 13 .uleb128 0x13 + 1750 003a 01 .byte 0x1 + 1751 003b 03 .uleb128 0x3 + 1752 003c 0E .uleb128 0xe + 1753 003d 0B .uleb128 0xb + 1754 003e 0B .uleb128 0xb + 1755 003f 3A .uleb128 0x3a + 1756 0040 0B .uleb128 0xb + 1757 0041 3B .uleb128 0x3b + 1758 0042 0B .uleb128 0xb + 1759 0043 01 .uleb128 0x1 + 1760 0044 13 .uleb128 0x13 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 32 + + + 1761 0045 00 .byte 0 + 1762 0046 00 .byte 0 + 1763 0047 06 .uleb128 0x6 + 1764 0048 0D .uleb128 0xd + 1765 0049 00 .byte 0 + 1766 004a 03 .uleb128 0x3 + 1767 004b 0E .uleb128 0xe + 1768 004c 3A .uleb128 0x3a + 1769 004d 0B .uleb128 0xb + 1770 004e 3B .uleb128 0x3b + 1771 004f 0B .uleb128 0xb + 1772 0050 49 .uleb128 0x49 + 1773 0051 13 .uleb128 0x13 + 1774 0052 38 .uleb128 0x38 + 1775 0053 0A .uleb128 0xa + 1776 0054 00 .byte 0 + 1777 0055 00 .byte 0 + 1778 0056 07 .uleb128 0x7 + 1779 0057 0D .uleb128 0xd + 1780 0058 00 .byte 0 + 1781 0059 03 .uleb128 0x3 + 1782 005a 08 .uleb128 0x8 + 1783 005b 3A .uleb128 0x3a + 1784 005c 0B .uleb128 0xb + 1785 005d 3B .uleb128 0x3b + 1786 005e 0B .uleb128 0xb + 1787 005f 49 .uleb128 0x49 + 1788 0060 13 .uleb128 0x13 + 1789 0061 38 .uleb128 0x38 + 1790 0062 0A .uleb128 0xa + 1791 0063 00 .byte 0 + 1792 0064 00 .byte 0 + 1793 0065 08 .uleb128 0x8 + 1794 0066 13 .uleb128 0x13 + 1795 0067 01 .byte 0x1 + 1796 0068 0B .uleb128 0xb + 1797 0069 0B .uleb128 0xb + 1798 006a 3A .uleb128 0x3a + 1799 006b 0B .uleb128 0xb + 1800 006c 3B .uleb128 0x3b + 1801 006d 0B .uleb128 0xb + 1802 006e 01 .uleb128 0x1 + 1803 006f 13 .uleb128 0x13 + 1804 0070 00 .byte 0 + 1805 0071 00 .byte 0 + 1806 0072 09 .uleb128 0x9 + 1807 0073 0F .uleb128 0xf + 1808 0074 00 .byte 0 + 1809 0075 0B .uleb128 0xb + 1810 0076 0B .uleb128 0xb + 1811 0077 49 .uleb128 0x49 + 1812 0078 13 .uleb128 0x13 + 1813 0079 00 .byte 0 + 1814 007a 00 .byte 0 + 1815 007b 0A .uleb128 0xa + 1816 007c 0F .uleb128 0xf + 1817 007d 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 33 + + + 1818 007e 0B .uleb128 0xb + 1819 007f 0B .uleb128 0xb + 1820 0080 00 .byte 0 + 1821 0081 00 .byte 0 + 1822 0082 0B .uleb128 0xb + 1823 0083 0D .uleb128 0xd + 1824 0084 00 .byte 0 + 1825 0085 03 .uleb128 0x3 + 1826 0086 08 .uleb128 0x8 + 1827 0087 3A .uleb128 0x3a + 1828 0088 0B .uleb128 0xb + 1829 0089 3B .uleb128 0x3b + 1830 008a 05 .uleb128 0x5 + 1831 008b 49 .uleb128 0x49 + 1832 008c 13 .uleb128 0x13 + 1833 008d 38 .uleb128 0x38 + 1834 008e 0A .uleb128 0xa + 1835 008f 00 .byte 0 + 1836 0090 00 .byte 0 + 1837 0091 0C .uleb128 0xc + 1838 0092 13 .uleb128 0x13 + 1839 0093 01 .byte 0x1 + 1840 0094 03 .uleb128 0x3 + 1841 0095 0E .uleb128 0xe + 1842 0096 0B .uleb128 0xb + 1843 0097 0B .uleb128 0xb + 1844 0098 3A .uleb128 0x3a + 1845 0099 0B .uleb128 0xb + 1846 009a 3B .uleb128 0x3b + 1847 009b 05 .uleb128 0x5 + 1848 009c 01 .uleb128 0x1 + 1849 009d 13 .uleb128 0x13 + 1850 009e 00 .byte 0 + 1851 009f 00 .byte 0 + 1852 00a0 0D .uleb128 0xd + 1853 00a1 35 .uleb128 0x35 + 1854 00a2 00 .byte 0 + 1855 00a3 49 .uleb128 0x49 + 1856 00a4 13 .uleb128 0x13 + 1857 00a5 00 .byte 0 + 1858 00a6 00 .byte 0 + 1859 00a7 0E .uleb128 0xe + 1860 00a8 17 .uleb128 0x17 + 1861 00a9 01 .byte 0x1 + 1862 00aa 0B .uleb128 0xb + 1863 00ab 0B .uleb128 0xb + 1864 00ac 3A .uleb128 0x3a + 1865 00ad 0B .uleb128 0xb + 1866 00ae 3B .uleb128 0x3b + 1867 00af 0B .uleb128 0xb + 1868 00b0 01 .uleb128 0x1 + 1869 00b1 13 .uleb128 0x13 + 1870 00b2 00 .byte 0 + 1871 00b3 00 .byte 0 + 1872 00b4 0F .uleb128 0xf + 1873 00b5 0D .uleb128 0xd + 1874 00b6 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 34 + + + 1875 00b7 03 .uleb128 0x3 + 1876 00b8 0E .uleb128 0xe + 1877 00b9 3A .uleb128 0x3a + 1878 00ba 0B .uleb128 0xb + 1879 00bb 3B .uleb128 0x3b + 1880 00bc 0B .uleb128 0xb + 1881 00bd 49 .uleb128 0x49 + 1882 00be 13 .uleb128 0x13 + 1883 00bf 00 .byte 0 + 1884 00c0 00 .byte 0 + 1885 00c1 10 .uleb128 0x10 + 1886 00c2 26 .uleb128 0x26 + 1887 00c3 00 .byte 0 + 1888 00c4 49 .uleb128 0x49 + 1889 00c5 13 .uleb128 0x13 + 1890 00c6 00 .byte 0 + 1891 00c7 00 .byte 0 + 1892 00c8 11 .uleb128 0x11 + 1893 00c9 2E .uleb128 0x2e + 1894 00ca 01 .byte 0x1 + 1895 00cb 03 .uleb128 0x3 + 1896 00cc 0E .uleb128 0xe + 1897 00cd 3A .uleb128 0x3a + 1898 00ce 0B .uleb128 0xb + 1899 00cf 3B .uleb128 0x3b + 1900 00d0 0B .uleb128 0xb + 1901 00d1 27 .uleb128 0x27 + 1902 00d2 0C .uleb128 0xc + 1903 00d3 49 .uleb128 0x49 + 1904 00d4 13 .uleb128 0x13 + 1905 00d5 20 .uleb128 0x20 + 1906 00d6 0B .uleb128 0xb + 1907 00d7 01 .uleb128 0x1 + 1908 00d8 13 .uleb128 0x13 + 1909 00d9 00 .byte 0 + 1910 00da 00 .byte 0 + 1911 00db 12 .uleb128 0x12 + 1912 00dc 05 .uleb128 0x5 + 1913 00dd 00 .byte 0 + 1914 00de 03 .uleb128 0x3 + 1915 00df 08 .uleb128 0x8 + 1916 00e0 3A .uleb128 0x3a + 1917 00e1 0B .uleb128 0xb + 1918 00e2 3B .uleb128 0x3b + 1919 00e3 0B .uleb128 0xb + 1920 00e4 49 .uleb128 0x49 + 1921 00e5 13 .uleb128 0x13 + 1922 00e6 00 .byte 0 + 1923 00e7 00 .byte 0 + 1924 00e8 13 .uleb128 0x13 + 1925 00e9 34 .uleb128 0x34 + 1926 00ea 00 .byte 0 + 1927 00eb 03 .uleb128 0x3 + 1928 00ec 08 .uleb128 0x8 + 1929 00ed 3A .uleb128 0x3a + 1930 00ee 0B .uleb128 0xb + 1931 00ef 3B .uleb128 0x3b + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 35 + + + 1932 00f0 0B .uleb128 0xb + 1933 00f1 49 .uleb128 0x49 + 1934 00f2 13 .uleb128 0x13 + 1935 00f3 00 .byte 0 + 1936 00f4 00 .byte 0 + 1937 00f5 14 .uleb128 0x14 + 1938 00f6 2E .uleb128 0x2e + 1939 00f7 01 .byte 0x1 + 1940 00f8 03 .uleb128 0x3 + 1941 00f9 0E .uleb128 0xe + 1942 00fa 3A .uleb128 0x3a + 1943 00fb 0B .uleb128 0xb + 1944 00fc 3B .uleb128 0x3b + 1945 00fd 0B .uleb128 0xb + 1946 00fe 27 .uleb128 0x27 + 1947 00ff 0C .uleb128 0xc + 1948 0100 20 .uleb128 0x20 + 1949 0101 0B .uleb128 0xb + 1950 0102 01 .uleb128 0x1 + 1951 0103 13 .uleb128 0x13 + 1952 0104 00 .byte 0 + 1953 0105 00 .byte 0 + 1954 0106 15 .uleb128 0x15 + 1955 0107 2E .uleb128 0x2e + 1956 0108 01 .byte 0x1 + 1957 0109 3F .uleb128 0x3f + 1958 010a 0C .uleb128 0xc + 1959 010b 03 .uleb128 0x3 + 1960 010c 0E .uleb128 0xe + 1961 010d 3A .uleb128 0x3a + 1962 010e 0B .uleb128 0xb + 1963 010f 3B .uleb128 0x3b + 1964 0110 0B .uleb128 0xb + 1965 0111 27 .uleb128 0x27 + 1966 0112 0C .uleb128 0xc + 1967 0113 11 .uleb128 0x11 + 1968 0114 01 .uleb128 0x1 + 1969 0115 12 .uleb128 0x12 + 1970 0116 01 .uleb128 0x1 + 1971 0117 40 .uleb128 0x40 + 1972 0118 0A .uleb128 0xa + 1973 0119 9742 .uleb128 0x2117 + 1974 011b 0C .uleb128 0xc + 1975 011c 01 .uleb128 0x1 + 1976 011d 13 .uleb128 0x13 + 1977 011e 00 .byte 0 + 1978 011f 00 .byte 0 + 1979 0120 16 .uleb128 0x16 + 1980 0121 05 .uleb128 0x5 + 1981 0122 00 .byte 0 + 1982 0123 03 .uleb128 0x3 + 1983 0124 08 .uleb128 0x8 + 1984 0125 3A .uleb128 0x3a + 1985 0126 0B .uleb128 0xb + 1986 0127 3B .uleb128 0x3b + 1987 0128 0B .uleb128 0xb + 1988 0129 49 .uleb128 0x49 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 36 + + + 1989 012a 13 .uleb128 0x13 + 1990 012b 02 .uleb128 0x2 + 1991 012c 0A .uleb128 0xa + 1992 012d 00 .byte 0 + 1993 012e 00 .byte 0 + 1994 012f 17 .uleb128 0x17 + 1995 0130 2E .uleb128 0x2e + 1996 0131 01 .byte 0x1 + 1997 0132 3F .uleb128 0x3f + 1998 0133 0C .uleb128 0xc + 1999 0134 03 .uleb128 0x3 + 2000 0135 0E .uleb128 0xe + 2001 0136 3A .uleb128 0x3a + 2002 0137 0B .uleb128 0xb + 2003 0138 3B .uleb128 0x3b + 2004 0139 0B .uleb128 0xb + 2005 013a 27 .uleb128 0x27 + 2006 013b 0C .uleb128 0xc + 2007 013c 11 .uleb128 0x11 + 2008 013d 01 .uleb128 0x1 + 2009 013e 12 .uleb128 0x12 + 2010 013f 01 .uleb128 0x1 + 2011 0140 40 .uleb128 0x40 + 2012 0141 06 .uleb128 0x6 + 2013 0142 9742 .uleb128 0x2117 + 2014 0144 0C .uleb128 0xc + 2015 0145 01 .uleb128 0x1 + 2016 0146 13 .uleb128 0x13 + 2017 0147 00 .byte 0 + 2018 0148 00 .byte 0 + 2019 0149 18 .uleb128 0x18 + 2020 014a 05 .uleb128 0x5 + 2021 014b 00 .byte 0 + 2022 014c 03 .uleb128 0x3 + 2023 014d 08 .uleb128 0x8 + 2024 014e 3A .uleb128 0x3a + 2025 014f 0B .uleb128 0xb + 2026 0150 3B .uleb128 0x3b + 2027 0151 0B .uleb128 0xb + 2028 0152 49 .uleb128 0x49 + 2029 0153 13 .uleb128 0x13 + 2030 0154 02 .uleb128 0x2 + 2031 0155 06 .uleb128 0x6 + 2032 0156 00 .byte 0 + 2033 0157 00 .byte 0 + 2034 0158 19 .uleb128 0x19 + 2035 0159 1D .uleb128 0x1d + 2036 015a 01 .byte 0x1 + 2037 015b 31 .uleb128 0x31 + 2038 015c 13 .uleb128 0x13 + 2039 015d 52 .uleb128 0x52 + 2040 015e 01 .uleb128 0x1 + 2041 015f 55 .uleb128 0x55 + 2042 0160 06 .uleb128 0x6 + 2043 0161 58 .uleb128 0x58 + 2044 0162 0B .uleb128 0xb + 2045 0163 59 .uleb128 0x59 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 37 + + + 2046 0164 0B .uleb128 0xb + 2047 0165 01 .uleb128 0x1 + 2048 0166 13 .uleb128 0x13 + 2049 0167 00 .byte 0 + 2050 0168 00 .byte 0 + 2051 0169 1A .uleb128 0x1a + 2052 016a 05 .uleb128 0x5 + 2053 016b 00 .byte 0 + 2054 016c 31 .uleb128 0x31 + 2055 016d 13 .uleb128 0x13 + 2056 016e 02 .uleb128 0x2 + 2057 016f 06 .uleb128 0x6 + 2058 0170 00 .byte 0 + 2059 0171 00 .byte 0 + 2060 0172 1B .uleb128 0x1b + 2061 0173 0B .uleb128 0xb + 2062 0174 01 .byte 0x1 + 2063 0175 55 .uleb128 0x55 + 2064 0176 06 .uleb128 0x6 + 2065 0177 00 .byte 0 + 2066 0178 00 .byte 0 + 2067 0179 1C .uleb128 0x1c + 2068 017a 34 .uleb128 0x34 + 2069 017b 00 .byte 0 + 2070 017c 31 .uleb128 0x31 + 2071 017d 13 .uleb128 0x13 + 2072 017e 02 .uleb128 0x2 + 2073 017f 06 .uleb128 0x6 + 2074 0180 00 .byte 0 + 2075 0181 00 .byte 0 + 2076 0182 1D .uleb128 0x1d + 2077 0183 898201 .uleb128 0x4109 + 2078 0186 01 .byte 0x1 + 2079 0187 11 .uleb128 0x11 + 2080 0188 01 .uleb128 0x1 + 2081 0189 31 .uleb128 0x31 + 2082 018a 13 .uleb128 0x13 + 2083 018b 00 .byte 0 + 2084 018c 00 .byte 0 + 2085 018d 1E .uleb128 0x1e + 2086 018e 8A8201 .uleb128 0x410a + 2087 0191 00 .byte 0 + 2088 0192 02 .uleb128 0x2 + 2089 0193 0A .uleb128 0xa + 2090 0194 9142 .uleb128 0x2111 + 2091 0196 0A .uleb128 0xa + 2092 0197 00 .byte 0 + 2093 0198 00 .byte 0 + 2094 0199 1F .uleb128 0x1f + 2095 019a 1D .uleb128 0x1d + 2096 019b 01 .byte 0x1 + 2097 019c 31 .uleb128 0x31 + 2098 019d 13 .uleb128 0x13 + 2099 019e 11 .uleb128 0x11 + 2100 019f 01 .uleb128 0x1 + 2101 01a0 12 .uleb128 0x12 + 2102 01a1 01 .uleb128 0x1 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 38 + + + 2103 01a2 58 .uleb128 0x58 + 2104 01a3 0B .uleb128 0xb + 2105 01a4 59 .uleb128 0x59 + 2106 01a5 0B .uleb128 0xb + 2107 01a6 01 .uleb128 0x1 + 2108 01a7 13 .uleb128 0x13 + 2109 01a8 00 .byte 0 + 2110 01a9 00 .byte 0 + 2111 01aa 20 .uleb128 0x20 + 2112 01ab 0B .uleb128 0xb + 2113 01ac 01 .byte 0x1 + 2114 01ad 11 .uleb128 0x11 + 2115 01ae 01 .uleb128 0x1 + 2116 01af 12 .uleb128 0x12 + 2117 01b0 01 .uleb128 0x1 + 2118 01b1 00 .byte 0 + 2119 01b2 00 .byte 0 + 2120 01b3 21 .uleb128 0x21 + 2121 01b4 898201 .uleb128 0x4109 + 2122 01b7 00 .byte 0 + 2123 01b8 11 .uleb128 0x11 + 2124 01b9 01 .uleb128 0x1 + 2125 01ba 31 .uleb128 0x31 + 2126 01bb 13 .uleb128 0x13 + 2127 01bc 00 .byte 0 + 2128 01bd 00 .byte 0 + 2129 01be 22 .uleb128 0x22 + 2130 01bf 898201 .uleb128 0x4109 + 2131 01c2 01 .byte 0x1 + 2132 01c3 11 .uleb128 0x11 + 2133 01c4 01 .uleb128 0x1 + 2134 01c5 31 .uleb128 0x31 + 2135 01c6 13 .uleb128 0x13 + 2136 01c7 01 .uleb128 0x1 + 2137 01c8 13 .uleb128 0x13 + 2138 01c9 00 .byte 0 + 2139 01ca 00 .byte 0 + 2140 01cb 23 .uleb128 0x23 + 2141 01cc 2E .uleb128 0x2e + 2142 01cd 01 .byte 0x1 + 2143 01ce 3F .uleb128 0x3f + 2144 01cf 0C .uleb128 0xc + 2145 01d0 03 .uleb128 0x3 + 2146 01d1 0E .uleb128 0xe + 2147 01d2 3A .uleb128 0x3a + 2148 01d3 0B .uleb128 0xb + 2149 01d4 3B .uleb128 0x3b + 2150 01d5 0B .uleb128 0xb + 2151 01d6 27 .uleb128 0x27 + 2152 01d7 0C .uleb128 0xc + 2153 01d8 49 .uleb128 0x49 + 2154 01d9 13 .uleb128 0x13 + 2155 01da 11 .uleb128 0x11 + 2156 01db 01 .uleb128 0x1 + 2157 01dc 12 .uleb128 0x12 + 2158 01dd 01 .uleb128 0x1 + 2159 01de 40 .uleb128 0x40 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 39 + + + 2160 01df 06 .uleb128 0x6 + 2161 01e0 9742 .uleb128 0x2117 + 2162 01e2 0C .uleb128 0xc + 2163 01e3 01 .uleb128 0x1 + 2164 01e4 13 .uleb128 0x13 + 2165 01e5 00 .byte 0 + 2166 01e6 00 .byte 0 + 2167 01e7 24 .uleb128 0x24 + 2168 01e8 34 .uleb128 0x34 + 2169 01e9 00 .byte 0 + 2170 01ea 03 .uleb128 0x3 + 2171 01eb 08 .uleb128 0x8 + 2172 01ec 3A .uleb128 0x3a + 2173 01ed 0B .uleb128 0xb + 2174 01ee 3B .uleb128 0x3b + 2175 01ef 0B .uleb128 0xb + 2176 01f0 49 .uleb128 0x49 + 2177 01f1 13 .uleb128 0x13 + 2178 01f2 02 .uleb128 0x2 + 2179 01f3 06 .uleb128 0x6 + 2180 01f4 00 .byte 0 + 2181 01f5 00 .byte 0 + 2182 01f6 25 .uleb128 0x25 + 2183 01f7 05 .uleb128 0x5 + 2184 01f8 00 .byte 0 + 2185 01f9 31 .uleb128 0x31 + 2186 01fa 13 .uleb128 0x13 + 2187 01fb 02 .uleb128 0x2 + 2188 01fc 0A .uleb128 0xa + 2189 01fd 00 .byte 0 + 2190 01fe 00 .byte 0 + 2191 01ff 26 .uleb128 0x26 + 2192 0200 34 .uleb128 0x34 + 2193 0201 00 .byte 0 + 2194 0202 03 .uleb128 0x3 + 2195 0203 08 .uleb128 0x8 + 2196 0204 3A .uleb128 0x3a + 2197 0205 0B .uleb128 0xb + 2198 0206 3B .uleb128 0x3b + 2199 0207 0B .uleb128 0xb + 2200 0208 49 .uleb128 0x49 + 2201 0209 13 .uleb128 0x13 + 2202 020a 02 .uleb128 0x2 + 2203 020b 0A .uleb128 0xa + 2204 020c 00 .byte 0 + 2205 020d 00 .byte 0 + 2206 020e 27 .uleb128 0x27 + 2207 020f 2E .uleb128 0x2e + 2208 0210 01 .byte 0x1 + 2209 0211 3F .uleb128 0x3f + 2210 0212 0C .uleb128 0xc + 2211 0213 03 .uleb128 0x3 + 2212 0214 0E .uleb128 0xe + 2213 0215 3A .uleb128 0x3a + 2214 0216 0B .uleb128 0xb + 2215 0217 3B .uleb128 0x3b + 2216 0218 05 .uleb128 0x5 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 40 + + + 2217 0219 27 .uleb128 0x27 + 2218 021a 0C .uleb128 0xc + 2219 021b 49 .uleb128 0x49 + 2220 021c 13 .uleb128 0x13 + 2221 021d 11 .uleb128 0x11 + 2222 021e 01 .uleb128 0x1 + 2223 021f 12 .uleb128 0x12 + 2224 0220 01 .uleb128 0x1 + 2225 0221 40 .uleb128 0x40 + 2226 0222 06 .uleb128 0x6 + 2227 0223 9742 .uleb128 0x2117 + 2228 0225 0C .uleb128 0xc + 2229 0226 01 .uleb128 0x1 + 2230 0227 13 .uleb128 0x13 + 2231 0228 00 .byte 0 + 2232 0229 00 .byte 0 + 2233 022a 28 .uleb128 0x28 + 2234 022b 05 .uleb128 0x5 + 2235 022c 00 .byte 0 + 2236 022d 03 .uleb128 0x3 + 2237 022e 08 .uleb128 0x8 + 2238 022f 3A .uleb128 0x3a + 2239 0230 0B .uleb128 0xb + 2240 0231 3B .uleb128 0x3b + 2241 0232 05 .uleb128 0x5 + 2242 0233 49 .uleb128 0x49 + 2243 0234 13 .uleb128 0x13 + 2244 0235 02 .uleb128 0x2 + 2245 0236 06 .uleb128 0x6 + 2246 0237 00 .byte 0 + 2247 0238 00 .byte 0 + 2248 0239 29 .uleb128 0x29 + 2249 023a 05 .uleb128 0x5 + 2250 023b 00 .byte 0 + 2251 023c 03 .uleb128 0x3 + 2252 023d 0E .uleb128 0xe + 2253 023e 3A .uleb128 0x3a + 2254 023f 0B .uleb128 0xb + 2255 0240 3B .uleb128 0x3b + 2256 0241 05 .uleb128 0x5 + 2257 0242 49 .uleb128 0x49 + 2258 0243 13 .uleb128 0x13 + 2259 0244 02 .uleb128 0x2 + 2260 0245 06 .uleb128 0x6 + 2261 0246 00 .byte 0 + 2262 0247 00 .byte 0 + 2263 0248 2A .uleb128 0x2a + 2264 0249 34 .uleb128 0x34 + 2265 024a 00 .byte 0 + 2266 024b 03 .uleb128 0x3 + 2267 024c 08 .uleb128 0x8 + 2268 024d 3A .uleb128 0x3a + 2269 024e 0B .uleb128 0xb + 2270 024f 3B .uleb128 0x3b + 2271 0250 05 .uleb128 0x5 + 2272 0251 49 .uleb128 0x49 + 2273 0252 13 .uleb128 0x13 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 41 + + + 2274 0253 02 .uleb128 0x2 + 2275 0254 06 .uleb128 0x6 + 2276 0255 00 .byte 0 + 2277 0256 00 .byte 0 + 2278 0257 2B .uleb128 0x2b + 2279 0258 1D .uleb128 0x1d + 2280 0259 01 .byte 0x1 + 2281 025a 31 .uleb128 0x31 + 2282 025b 13 .uleb128 0x13 + 2283 025c 52 .uleb128 0x52 + 2284 025d 01 .uleb128 0x1 + 2285 025e 55 .uleb128 0x55 + 2286 025f 06 .uleb128 0x6 + 2287 0260 58 .uleb128 0x58 + 2288 0261 0B .uleb128 0xb + 2289 0262 59 .uleb128 0x59 + 2290 0263 05 .uleb128 0x5 + 2291 0264 01 .uleb128 0x1 + 2292 0265 13 .uleb128 0x13 + 2293 0266 00 .byte 0 + 2294 0267 00 .byte 0 + 2295 0268 2C .uleb128 0x2c + 2296 0269 05 .uleb128 0x5 + 2297 026a 00 .byte 0 + 2298 026b 03 .uleb128 0x3 + 2299 026c 0E .uleb128 0xe + 2300 026d 3A .uleb128 0x3a + 2301 026e 0B .uleb128 0xb + 2302 026f 3B .uleb128 0x3b + 2303 0270 0B .uleb128 0xb + 2304 0271 49 .uleb128 0x49 + 2305 0272 13 .uleb128 0x13 + 2306 0273 02 .uleb128 0x2 + 2307 0274 06 .uleb128 0x6 + 2308 0275 00 .byte 0 + 2309 0276 00 .byte 0 + 2310 0277 2D .uleb128 0x2d + 2311 0278 34 .uleb128 0x34 + 2312 0279 00 .byte 0 + 2313 027a 03 .uleb128 0x3 + 2314 027b 0E .uleb128 0xe + 2315 027c 3A .uleb128 0x3a + 2316 027d 0B .uleb128 0xb + 2317 027e 3B .uleb128 0x3b + 2318 027f 0B .uleb128 0xb + 2319 0280 49 .uleb128 0x49 + 2320 0281 13 .uleb128 0x13 + 2321 0282 3F .uleb128 0x3f + 2322 0283 0C .uleb128 0xc + 2323 0284 3C .uleb128 0x3c + 2324 0285 0C .uleb128 0xc + 2325 0286 00 .byte 0 + 2326 0287 00 .byte 0 + 2327 0288 2E .uleb128 0x2e + 2328 0289 2E .uleb128 0x2e + 2329 028a 01 .byte 0x1 + 2330 028b 3F .uleb128 0x3f + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 42 + + + 2331 028c 0C .uleb128 0xc + 2332 028d 03 .uleb128 0x3 + 2333 028e 0E .uleb128 0xe + 2334 028f 3A .uleb128 0x3a + 2335 0290 0B .uleb128 0xb + 2336 0291 3B .uleb128 0x3b + 2337 0292 0B .uleb128 0xb + 2338 0293 27 .uleb128 0x27 + 2339 0294 0C .uleb128 0xc + 2340 0295 3C .uleb128 0x3c + 2341 0296 0C .uleb128 0xc + 2342 0297 01 .uleb128 0x1 + 2343 0298 13 .uleb128 0x13 + 2344 0299 00 .byte 0 + 2345 029a 00 .byte 0 + 2346 029b 2F .uleb128 0x2f + 2347 029c 05 .uleb128 0x5 + 2348 029d 00 .byte 0 + 2349 029e 49 .uleb128 0x49 + 2350 029f 13 .uleb128 0x13 + 2351 02a0 00 .byte 0 + 2352 02a1 00 .byte 0 + 2353 02a2 30 .uleb128 0x30 + 2354 02a3 2E .uleb128 0x2e + 2355 02a4 01 .byte 0x1 + 2356 02a5 3F .uleb128 0x3f + 2357 02a6 0C .uleb128 0xc + 2358 02a7 03 .uleb128 0x3 + 2359 02a8 0E .uleb128 0xe + 2360 02a9 3A .uleb128 0x3a + 2361 02aa 0B .uleb128 0xb + 2362 02ab 3B .uleb128 0x3b + 2363 02ac 0B .uleb128 0xb + 2364 02ad 27 .uleb128 0x27 + 2365 02ae 0C .uleb128 0xc + 2366 02af 49 .uleb128 0x49 + 2367 02b0 13 .uleb128 0x13 + 2368 02b1 3C .uleb128 0x3c + 2369 02b2 0C .uleb128 0xc + 2370 02b3 01 .uleb128 0x1 + 2371 02b4 13 .uleb128 0x13 + 2372 02b5 00 .byte 0 + 2373 02b6 00 .byte 0 + 2374 02b7 31 .uleb128 0x31 + 2375 02b8 2E .uleb128 0x2e + 2376 02b9 00 .byte 0 + 2377 02ba 3F .uleb128 0x3f + 2378 02bb 0C .uleb128 0xc + 2379 02bc 03 .uleb128 0x3 + 2380 02bd 0E .uleb128 0xe + 2381 02be 3A .uleb128 0x3a + 2382 02bf 0B .uleb128 0xb + 2383 02c0 3B .uleb128 0x3b + 2384 02c1 0B .uleb128 0xb + 2385 02c2 27 .uleb128 0x27 + 2386 02c3 0C .uleb128 0xc + 2387 02c4 3C .uleb128 0x3c + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 43 + + + 2388 02c5 0C .uleb128 0xc + 2389 02c6 00 .byte 0 + 2390 02c7 00 .byte 0 + 2391 02c8 32 .uleb128 0x32 + 2392 02c9 2E .uleb128 0x2e + 2393 02ca 00 .byte 0 + 2394 02cb 3F .uleb128 0x3f + 2395 02cc 0C .uleb128 0xc + 2396 02cd 03 .uleb128 0x3 + 2397 02ce 0E .uleb128 0xe + 2398 02cf 3A .uleb128 0x3a + 2399 02d0 0B .uleb128 0xb + 2400 02d1 3B .uleb128 0x3b + 2401 02d2 0B .uleb128 0xb + 2402 02d3 27 .uleb128 0x27 + 2403 02d4 0C .uleb128 0xc + 2404 02d5 49 .uleb128 0x49 + 2405 02d6 13 .uleb128 0x13 + 2406 02d7 3C .uleb128 0x3c + 2407 02d8 0C .uleb128 0xc + 2408 02d9 00 .byte 0 + 2409 02da 00 .byte 0 + 2410 02db 33 .uleb128 0x33 + 2411 02dc 2E .uleb128 0x2e + 2412 02dd 01 .byte 0x1 + 2413 02de 3F .uleb128 0x3f + 2414 02df 0C .uleb128 0xc + 2415 02e0 03 .uleb128 0x3 + 2416 02e1 0E .uleb128 0xe + 2417 02e2 3A .uleb128 0x3a + 2418 02e3 0B .uleb128 0xb + 2419 02e4 3B .uleb128 0x3b + 2420 02e5 0B .uleb128 0xb + 2421 02e6 27 .uleb128 0x27 + 2422 02e7 0C .uleb128 0xc + 2423 02e8 49 .uleb128 0x49 + 2424 02e9 13 .uleb128 0x13 + 2425 02ea 3C .uleb128 0x3c + 2426 02eb 0C .uleb128 0xc + 2427 02ec 00 .byte 0 + 2428 02ed 00 .byte 0 + 2429 02ee 00 .byte 0 + 2430 .section .debug_loc,"",%progbits + 2431 .Ldebug_loc0: + 2432 .LLST0: + 2433 0000 00000000 .4byte .LFB8 + 2434 0004 02000000 .4byte .LCFI0 + 2435 0008 0200 .2byte 0x2 + 2436 000a 7D .byte 0x7d + 2437 000b 00 .sleb128 0 + 2438 000c 02000000 .4byte .LCFI0 + 2439 0010 1C000000 .4byte .LFE8 + 2440 0014 0200 .2byte 0x2 + 2441 0016 7D .byte 0x7d + 2442 0017 08 .sleb128 8 + 2443 0018 00000000 .4byte 0 + 2444 001c 00000000 .4byte 0 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 44 + + + 2445 .LLST1: + 2446 0020 00000000 .4byte .LVL1 + 2447 0024 08000000 .4byte .LVL2 + 2448 0028 0100 .2byte 0x1 + 2449 002a 50 .byte 0x50 + 2450 002b 08000000 .4byte .LVL2 + 2451 002f 17000000 .4byte .LVL4-1 + 2452 0033 0100 .2byte 0x1 + 2453 0035 53 .byte 0x53 + 2454 0036 17000000 .4byte .LVL4-1 + 2455 003a 1C000000 .4byte .LFE8 + 2456 003e 0400 .2byte 0x4 + 2457 0040 F3 .byte 0xf3 + 2458 0041 01 .uleb128 0x1 + 2459 0042 50 .byte 0x50 + 2460 0043 9F .byte 0x9f + 2461 0044 00000000 .4byte 0 + 2462 0048 00000000 .4byte 0 + 2463 .LLST2: + 2464 004c 0C000000 .4byte .LVL3 + 2465 0050 17000000 .4byte .LVL4-1 + 2466 0054 0100 .2byte 0x1 + 2467 0056 53 .byte 0x53 + 2468 0057 17000000 .4byte .LVL4-1 + 2469 005b 18000000 .4byte .LVL4 + 2470 005f 0400 .2byte 0x4 + 2471 0061 F3 .byte 0xf3 + 2472 0062 01 .uleb128 0x1 + 2473 0063 50 .byte 0x50 + 2474 0064 9F .byte 0x9f + 2475 0065 00000000 .4byte 0 + 2476 0069 00000000 .4byte 0 + 2477 .LLST3: + 2478 006d 0C000000 .4byte .LVL3 + 2479 0071 17000000 .4byte .LVL4-1 + 2480 0075 0100 .2byte 0x1 + 2481 0077 50 .byte 0x50 + 2482 0078 00000000 .4byte 0 + 2483 007c 00000000 .4byte 0 + 2484 .LLST4: + 2485 0080 00000000 .4byte .LFB9 + 2486 0084 02000000 .4byte .LCFI1 + 2487 0088 0200 .2byte 0x2 + 2488 008a 7D .byte 0x7d + 2489 008b 00 .sleb128 0 + 2490 008c 02000000 .4byte .LCFI1 + 2491 0090 1A000000 .4byte .LFE9 + 2492 0094 0200 .2byte 0x2 + 2493 0096 7D .byte 0x7d + 2494 0097 08 .sleb128 8 + 2495 0098 00000000 .4byte 0 + 2496 009c 00000000 .4byte 0 + 2497 .LLST5: + 2498 00a0 00000000 .4byte .LVL5 + 2499 00a4 06000000 .4byte .LVL6 + 2500 00a8 0100 .2byte 0x1 + 2501 00aa 50 .byte 0x50 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 45 + + + 2502 00ab 06000000 .4byte .LVL6 + 2503 00af 13000000 .4byte .LVL8-1 + 2504 00b3 0100 .2byte 0x1 + 2505 00b5 53 .byte 0x53 + 2506 00b6 13000000 .4byte .LVL8-1 + 2507 00ba 1A000000 .4byte .LFE9 + 2508 00be 0400 .2byte 0x4 + 2509 00c0 F3 .byte 0xf3 + 2510 00c1 01 .uleb128 0x1 + 2511 00c2 50 .byte 0x50 + 2512 00c3 9F .byte 0x9f + 2513 00c4 00000000 .4byte 0 + 2514 00c8 00000000 .4byte 0 + 2515 .LLST6: + 2516 00cc 0A000000 .4byte .LVL7 + 2517 00d0 13000000 .4byte .LVL8-1 + 2518 00d4 0100 .2byte 0x1 + 2519 00d6 53 .byte 0x53 + 2520 00d7 13000000 .4byte .LVL8-1 + 2521 00db 18000000 .4byte .LVL9 + 2522 00df 0400 .2byte 0x4 + 2523 00e1 F3 .byte 0xf3 + 2524 00e2 01 .uleb128 0x1 + 2525 00e3 50 .byte 0x50 + 2526 00e4 9F .byte 0x9f + 2527 00e5 00000000 .4byte 0 + 2528 00e9 00000000 .4byte 0 + 2529 .LLST7: + 2530 00ed 0A000000 .4byte .LVL7 + 2531 00f1 13000000 .4byte .LVL8-1 + 2532 00f5 0100 .2byte 0x1 + 2533 00f7 50 .byte 0x50 + 2534 00f8 00000000 .4byte 0 + 2535 00fc 00000000 .4byte 0 + 2536 .LLST8: + 2537 0100 00000000 .4byte .LFB11 + 2538 0104 02000000 .4byte .LCFI2 + 2539 0108 0200 .2byte 0x2 + 2540 010a 7D .byte 0x7d + 2541 010b 00 .sleb128 0 + 2542 010c 02000000 .4byte .LCFI2 + 2543 0110 22000000 .4byte .LFE11 + 2544 0114 0200 .2byte 0x2 + 2545 0116 7D .byte 0x7d + 2546 0117 10 .sleb128 16 + 2547 0118 00000000 .4byte 0 + 2548 011c 00000000 .4byte 0 + 2549 .LLST9: + 2550 0120 00000000 .4byte .LVL10 + 2551 0124 06000000 .4byte .LVL11 + 2552 0128 0100 .2byte 0x1 + 2553 012a 50 .byte 0x50 + 2554 012b 06000000 .4byte .LVL11 + 2555 012f 22000000 .4byte .LFE11 + 2556 0133 0100 .2byte 0x1 + 2557 0135 54 .byte 0x54 + 2558 0136 00000000 .4byte 0 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 46 + + + 2559 013a 00000000 .4byte 0 + 2560 .LLST10: + 2561 013e 0E000000 .4byte .LVL12 + 2562 0142 20000000 .4byte .LVL14 + 2563 0146 0100 .2byte 0x1 + 2564 0148 54 .byte 0x54 + 2565 0149 00000000 .4byte 0 + 2566 014d 00000000 .4byte 0 + 2567 .LLST11: + 2568 0151 0E000000 .4byte .LVL12 + 2569 0155 17000000 .4byte .LVL13-1 + 2570 0159 0100 .2byte 0x1 + 2571 015b 50 .byte 0x50 + 2572 015c 00000000 .4byte 0 + 2573 0160 00000000 .4byte 0 + 2574 .LLST12: + 2575 0164 00000000 .4byte .LFB10 + 2576 0168 02000000 .4byte .LCFI3 + 2577 016c 0200 .2byte 0x2 + 2578 016e 7D .byte 0x7d + 2579 016f 00 .sleb128 0 + 2580 0170 02000000 .4byte .LCFI3 + 2581 0174 10000000 .4byte .LFE10 + 2582 0178 0200 .2byte 0x2 + 2583 017a 7D .byte 0x7d + 2584 017b 08 .sleb128 8 + 2585 017c 00000000 .4byte 0 + 2586 0180 00000000 .4byte 0 + 2587 .LLST13: + 2588 0184 00000000 .4byte .LVL15 + 2589 0188 07000000 .4byte .LVL16-1 + 2590 018c 0100 .2byte 0x1 + 2591 018e 50 .byte 0x50 + 2592 018f 07000000 .4byte .LVL16-1 + 2593 0193 10000000 .4byte .LFE10 + 2594 0197 0400 .2byte 0x4 + 2595 0199 F3 .byte 0xf3 + 2596 019a 01 .uleb128 0x1 + 2597 019b 50 .byte 0x50 + 2598 019c 9F .byte 0x9f + 2599 019d 00000000 .4byte 0 + 2600 01a1 00000000 .4byte 0 + 2601 .LLST14: + 2602 01a5 00000000 .4byte .LFB13 + 2603 01a9 02000000 .4byte .LCFI4 + 2604 01ad 0200 .2byte 0x2 + 2605 01af 7D .byte 0x7d + 2606 01b0 00 .sleb128 0 + 2607 01b1 02000000 .4byte .LCFI4 + 2608 01b5 48000000 .4byte .LFE13 + 2609 01b9 0200 .2byte 0x2 + 2610 01bb 7D .byte 0x7d + 2611 01bc 18 .sleb128 24 + 2612 01bd 00000000 .4byte 0 + 2613 01c1 00000000 .4byte 0 + 2614 .LLST15: + 2615 01c5 00000000 .4byte .LVL18 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 47 + + + 2616 01c9 0B000000 .4byte .LVL20-1 + 2617 01cd 0100 .2byte 0x1 + 2618 01cf 50 .byte 0x50 + 2619 01d0 0B000000 .4byte .LVL20-1 + 2620 01d4 48000000 .4byte .LFE13 + 2621 01d8 0100 .2byte 0x1 + 2622 01da 55 .byte 0x55 + 2623 01db 00000000 .4byte 0 + 2624 01df 00000000 .4byte 0 + 2625 .LLST16: + 2626 01e3 08000000 .4byte .LVL19 + 2627 01e7 36000000 .4byte .LVL27 + 2628 01eb 0100 .2byte 0x1 + 2629 01ed 54 .byte 0x54 + 2630 01ee 40000000 .4byte .LVL29 + 2631 01f2 48000000 .4byte .LFE13 + 2632 01f6 0100 .2byte 0x1 + 2633 01f8 54 .byte 0x54 + 2634 01f9 00000000 .4byte 0 + 2635 01fd 00000000 .4byte 0 + 2636 .LLST17: + 2637 0201 10000000 .4byte .LVL21 + 2638 0205 30000000 .4byte .LVL25 + 2639 0209 0100 .2byte 0x1 + 2640 020b 50 .byte 0x50 + 2641 020c 30000000 .4byte .LVL25 + 2642 0210 40000000 .4byte .LVL29 + 2643 0214 0100 .2byte 0x1 + 2644 0216 57 .byte 0x57 + 2645 0217 40000000 .4byte .LVL29 + 2646 021b 48000000 .4byte .LFE13 + 2647 021f 0100 .2byte 0x1 + 2648 0221 50 .byte 0x50 + 2649 0222 00000000 .4byte 0 + 2650 0226 00000000 .4byte 0 + 2651 .LLST18: + 2652 022a 36000000 .4byte .LVL27 + 2653 022e 40000000 .4byte .LVL29 + 2654 0232 0100 .2byte 0x1 + 2655 0234 54 .byte 0x54 + 2656 0235 00000000 .4byte 0 + 2657 0239 00000000 .4byte 0 + 2658 .LLST19: + 2659 023d 10000000 .4byte .LVL21 + 2660 0241 36000000 .4byte .LVL27 + 2661 0245 0100 .2byte 0x1 + 2662 0247 54 .byte 0x54 + 2663 0248 40000000 .4byte .LVL29 + 2664 024c 48000000 .4byte .LFE13 + 2665 0250 0100 .2byte 0x1 + 2666 0252 54 .byte 0x54 + 2667 0253 00000000 .4byte 0 + 2668 0257 00000000 .4byte 0 + 2669 .LLST20: + 2670 025b 10000000 .4byte .LVL21 + 2671 025f 16000000 .4byte .LVL22 + 2672 0263 0100 .2byte 0x1 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 48 + + + 2673 0265 55 .byte 0x55 + 2674 0266 16000000 .4byte .LVL22 + 2675 026a 26000000 .4byte .LVL24 + 2676 026e 0100 .2byte 0x1 + 2677 0270 53 .byte 0x53 + 2678 0271 40000000 .4byte .LVL29 + 2679 0275 48000000 .4byte .LFE13 + 2680 0279 0100 .2byte 0x1 + 2681 027b 53 .byte 0x53 + 2682 027c 00000000 .4byte 0 + 2683 0280 00000000 .4byte 0 + 2684 .LLST21: + 2685 0284 00000000 .4byte .LFB12 + 2686 0288 02000000 .4byte .LCFI5 + 2687 028c 0200 .2byte 0x2 + 2688 028e 7D .byte 0x7d + 2689 028f 00 .sleb128 0 + 2690 0290 02000000 .4byte .LCFI5 + 2691 0294 0C000000 .4byte .LFE12 + 2692 0298 0200 .2byte 0x2 + 2693 029a 7D .byte 0x7d + 2694 029b 08 .sleb128 8 + 2695 029c 00000000 .4byte 0 + 2696 02a0 00000000 .4byte 0 + 2697 .LLST22: + 2698 02a4 00000000 .4byte .LVL30 + 2699 02a8 07000000 .4byte .LVL31-1 + 2700 02ac 0100 .2byte 0x1 + 2701 02ae 50 .byte 0x50 + 2702 02af 07000000 .4byte .LVL31-1 + 2703 02b3 0C000000 .4byte .LFE12 + 2704 02b7 0400 .2byte 0x4 + 2705 02b9 F3 .byte 0xf3 + 2706 02ba 01 .uleb128 0x1 + 2707 02bb 50 .byte 0x50 + 2708 02bc 9F .byte 0x9f + 2709 02bd 00000000 .4byte 0 + 2710 02c1 00000000 .4byte 0 + 2711 .LLST23: + 2712 02c5 00000000 .4byte .LFB15 + 2713 02c9 04000000 .4byte .LCFI6 + 2714 02cd 0200 .2byte 0x2 + 2715 02cf 7D .byte 0x7d + 2716 02d0 00 .sleb128 0 + 2717 02d1 04000000 .4byte .LCFI6 + 2718 02d5 4C000000 .4byte .LFE15 + 2719 02d9 0200 .2byte 0x2 + 2720 02db 7D .byte 0x7d + 2721 02dc 18 .sleb128 24 + 2722 02dd 00000000 .4byte 0 + 2723 02e1 00000000 .4byte 0 + 2724 .LLST24: + 2725 02e5 00000000 .4byte .LVL32 + 2726 02e9 0B000000 .4byte .LVL33-1 + 2727 02ed 0100 .2byte 0x1 + 2728 02ef 50 .byte 0x50 + 2729 02f0 0B000000 .4byte .LVL33-1 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 49 + + + 2730 02f4 4C000000 .4byte .LFE15 + 2731 02f8 0100 .2byte 0x1 + 2732 02fa 56 .byte 0x56 + 2733 02fb 00000000 .4byte 0 + 2734 02ff 00000000 .4byte 0 + 2735 .LLST25: + 2736 0303 00000000 .4byte .LVL32 + 2737 0307 0B000000 .4byte .LVL33-1 + 2738 030b 0100 .2byte 0x1 + 2739 030d 51 .byte 0x51 + 2740 030e 0B000000 .4byte .LVL33-1 + 2741 0312 4C000000 .4byte .LFE15 + 2742 0316 0100 .2byte 0x1 + 2743 0318 58 .byte 0x58 + 2744 0319 00000000 .4byte 0 + 2745 031d 00000000 .4byte 0 + 2746 .LLST26: + 2747 0321 10000000 .4byte .LVL34 + 2748 0325 28000000 .4byte .LVL37 + 2749 0329 0100 .2byte 0x1 + 2750 032b 50 .byte 0x50 + 2751 032c 28000000 .4byte .LVL37 + 2752 0330 4C000000 .4byte .LFE15 + 2753 0334 0100 .2byte 0x1 + 2754 0336 57 .byte 0x57 + 2755 0337 00000000 .4byte 0 + 2756 033b 00000000 .4byte 0 + 2757 .LLST27: + 2758 033f 3A000000 .4byte .LVL39 + 2759 0343 3E000000 .4byte .LVL40 + 2760 0347 0100 .2byte 0x1 + 2761 0349 50 .byte 0x50 + 2762 034a 3E000000 .4byte .LVL40 + 2763 034e 4C000000 .4byte .LFE15 + 2764 0352 0100 .2byte 0x1 + 2765 0354 54 .byte 0x54 + 2766 0355 00000000 .4byte 0 + 2767 0359 00000000 .4byte 0 + 2768 .LLST28: + 2769 035d 16000000 .4byte .LVL35 + 2770 0361 35000000 .4byte .LVL38-1 + 2771 0365 0100 .2byte 0x1 + 2772 0367 52 .byte 0x52 + 2773 0368 00000000 .4byte 0 + 2774 036c 00000000 .4byte 0 + 2775 .LLST29: + 2776 0370 16000000 .4byte .LVL35 + 2777 0374 35000000 .4byte .LVL38-1 + 2778 0378 0100 .2byte 0x1 + 2779 037a 53 .byte 0x53 + 2780 037b 00000000 .4byte 0 + 2781 037f 00000000 .4byte 0 + 2782 .LLST30: + 2783 0383 00000000 .4byte .LFB14 + 2784 0387 02000000 .4byte .LCFI7 + 2785 038b 0200 .2byte 0x2 + 2786 038d 7D .byte 0x7d + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 50 + + + 2787 038e 00 .sleb128 0 + 2788 038f 02000000 .4byte .LCFI7 + 2789 0393 0C000000 .4byte .LFE14 + 2790 0397 0200 .2byte 0x2 + 2791 0399 7D .byte 0x7d + 2792 039a 08 .sleb128 8 + 2793 039b 00000000 .4byte 0 + 2794 039f 00000000 .4byte 0 + 2795 .LLST31: + 2796 03a3 00000000 .4byte .LVL42 + 2797 03a7 07000000 .4byte .LVL43-1 + 2798 03ab 0100 .2byte 0x1 + 2799 03ad 50 .byte 0x50 + 2800 03ae 07000000 .4byte .LVL43-1 + 2801 03b2 0C000000 .4byte .LFE14 + 2802 03b6 0400 .2byte 0x4 + 2803 03b8 F3 .byte 0xf3 + 2804 03b9 01 .uleb128 0x1 + 2805 03ba 50 .byte 0x50 + 2806 03bb 9F .byte 0x9f + 2807 03bc 00000000 .4byte 0 + 2808 03c0 00000000 .4byte 0 + 2809 .LLST32: + 2810 03c4 00000000 .4byte .LVL42 + 2811 03c8 07000000 .4byte .LVL43-1 + 2812 03cc 0100 .2byte 0x1 + 2813 03ce 51 .byte 0x51 + 2814 03cf 07000000 .4byte .LVL43-1 + 2815 03d3 0C000000 .4byte .LFE14 + 2816 03d7 0400 .2byte 0x4 + 2817 03d9 F3 .byte 0xf3 + 2818 03da 01 .uleb128 0x1 + 2819 03db 51 .byte 0x51 + 2820 03dc 9F .byte 0x9f + 2821 03dd 00000000 .4byte 0 + 2822 03e1 00000000 .4byte 0 + 2823 .section .debug_aranges,"",%progbits + 2824 0000 5C000000 .4byte 0x5c + 2825 0004 0200 .2byte 0x2 + 2826 0006 00000000 .4byte .Ldebug_info0 + 2827 000a 04 .byte 0x4 + 2828 000b 00 .byte 0 + 2829 000c 0000 .2byte 0 + 2830 000e 0000 .2byte 0 + 2831 0010 00000000 .4byte .LFB7 + 2832 0014 06000000 .4byte .LFE7-.LFB7 + 2833 0018 00000000 .4byte .LFB8 + 2834 001c 1C000000 .4byte .LFE8-.LFB8 + 2835 0020 00000000 .4byte .LFB9 + 2836 0024 1A000000 .4byte .LFE9-.LFB9 + 2837 0028 00000000 .4byte .LFB11 + 2838 002c 22000000 .4byte .LFE11-.LFB11 + 2839 0030 00000000 .4byte .LFB10 + 2840 0034 10000000 .4byte .LFE10-.LFB10 + 2841 0038 00000000 .4byte .LFB13 + 2842 003c 48000000 .4byte .LFE13-.LFB13 + 2843 0040 00000000 .4byte .LFB12 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 51 + + + 2844 0044 0C000000 .4byte .LFE12-.LFB12 + 2845 0048 00000000 .4byte .LFB15 + 2846 004c 4C000000 .4byte .LFE15-.LFB15 + 2847 0050 00000000 .4byte .LFB14 + 2848 0054 0C000000 .4byte .LFE14-.LFB14 + 2849 0058 00000000 .4byte 0 + 2850 005c 00000000 .4byte 0 + 2851 .section .debug_ranges,"",%progbits + 2852 .Ldebug_ranges0: + 2853 0000 0C000000 .4byte .LBB12 + 2854 0004 0E000000 .4byte .LBE12 + 2855 0008 10000000 .4byte .LBB15 + 2856 000c 14000000 .4byte .LBE15 + 2857 0010 00000000 .4byte 0 + 2858 0014 00000000 .4byte 0 + 2859 0018 0C000000 .4byte .LBB13 + 2860 001c 0E000000 .4byte .LBE13 + 2861 0020 10000000 .4byte .LBB14 + 2862 0024 14000000 .4byte .LBE14 + 2863 0028 00000000 .4byte 0 + 2864 002c 00000000 .4byte 0 + 2865 0030 16000000 .4byte .LBB20 + 2866 0034 2E000000 .4byte .LBE20 + 2867 0038 40000000 .4byte .LBB23 + 2868 003c 48000000 .4byte .LBE23 + 2869 0040 00000000 .4byte 0 + 2870 0044 00000000 .4byte 0 + 2871 0048 16000000 .4byte .LBB21 + 2872 004c 2E000000 .4byte .LBE21 + 2873 0050 40000000 .4byte .LBB22 + 2874 0054 48000000 .4byte .LBE22 + 2875 0058 00000000 .4byte 0 + 2876 005c 00000000 .4byte 0 + 2877 0060 16000000 .4byte .LBB24 + 2878 0064 26000000 .4byte .LBE24 + 2879 0068 28000000 .4byte .LBB28 + 2880 006c 2C000000 .4byte .LBE28 + 2881 0070 2E000000 .4byte .LBB29 + 2882 0074 32000000 .4byte .LBE29 + 2883 0078 00000000 .4byte 0 + 2884 007c 00000000 .4byte 0 + 2885 0080 16000000 .4byte .LBB25 + 2886 0084 26000000 .4byte .LBE25 + 2887 0088 28000000 .4byte .LBB26 + 2888 008c 2C000000 .4byte .LBE26 + 2889 0090 2E000000 .4byte .LBB27 + 2890 0094 32000000 .4byte .LBE27 + 2891 0098 00000000 .4byte 0 + 2892 009c 00000000 .4byte 0 + 2893 00a0 00000000 .4byte .LFB7 + 2894 00a4 06000000 .4byte .LFE7 + 2895 00a8 00000000 .4byte .LFB8 + 2896 00ac 1C000000 .4byte .LFE8 + 2897 00b0 00000000 .4byte .LFB9 + 2898 00b4 1A000000 .4byte .LFE9 + 2899 00b8 00000000 .4byte .LFB11 + 2900 00bc 22000000 .4byte .LFE11 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 52 + + + 2901 00c0 00000000 .4byte .LFB10 + 2902 00c4 10000000 .4byte .LFE10 + 2903 00c8 00000000 .4byte .LFB13 + 2904 00cc 48000000 .4byte .LFE13 + 2905 00d0 00000000 .4byte .LFB12 + 2906 00d4 0C000000 .4byte .LFE12 + 2907 00d8 00000000 .4byte .LFB15 + 2908 00dc 4C000000 .4byte .LFE15 + 2909 00e0 00000000 .4byte .LFB14 + 2910 00e4 0C000000 .4byte .LFE14 + 2911 00e8 00000000 .4byte 0 + 2912 00ec 00000000 .4byte 0 + 2913 .section .debug_line,"",%progbits + 2914 .Ldebug_line0: + 2915 0000 4A020000 .section .debug_str,"MS",%progbits,1 + 2915 02001101 + 2915 00000201 + 2915 FB0E0D00 + 2915 01010101 + 2916 .LASF34: + 2917 0000 705F6D73 .ascii "p_msg\000" + 2917 6700 + 2918 .LASF64: + 2919 0006 6368436F .ascii "chCondInit\000" + 2919 6E64496E + 2919 697400 + 2920 .LASF59: + 2921 0011 7264796D .ascii "rdymsg\000" + 2921 736700 + 2922 .LASF11: + 2923 0018 6C6F6E67 .ascii "long long unsigned int\000" + 2923 206C6F6E + 2923 6720756E + 2923 7369676E + 2923 65642069 + 2924 .LASF60: + 2925 002f 65786974 .ascii "exitcode\000" + 2925 636F6465 + 2925 00 + 2926 .LASF67: + 2927 0038 6368436F .ascii "chCondBroadcastI\000" + 2927 6E644272 + 2927 6F616463 + 2927 61737449 + 2927 00 + 2928 .LASF23: + 2929 0049 705F7072 .ascii "p_prio\000" + 2929 696F00 + 2930 .LASF10: + 2931 0050 6C6F6E67 .ascii "long long int\000" + 2931 206C6F6E + 2931 6720696E + 2931 7400 + 2932 .LASF1: + 2933 005e 7369676E .ascii "signed char\000" + 2933 65642063 + 2933 68617200 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 53 + + + 2934 .LASF38: + 2935 006a 705F6D70 .ascii "p_mpool\000" + 2935 6F6F6C00 + 2936 .LASF54: + 2937 0072 6D5F7175 .ascii "m_queue\000" + 2937 65756500 + 2938 .LASF57: + 2939 007a 436F6E64 .ascii "CondVar\000" + 2939 56617200 + 2940 .LASF7: + 2941 0082 6C6F6E67 .ascii "long int\000" + 2941 20696E74 + 2941 00 + 2942 .LASF13: + 2943 008b 74737461 .ascii "tstate_t\000" + 2943 74655F74 + 2943 00 + 2944 .LASF76: + 2945 0094 63684D74 .ascii "chMtxLockS\000" + 2945 784C6F63 + 2945 6B5300 + 2946 .LASF25: + 2947 009f 705F6E65 .ascii "p_newer\000" + 2947 77657200 + 2948 .LASF85: + 2949 00a7 63685363 .ascii "chSchRescheduleS\000" + 2949 68526573 + 2949 63686564 + 2949 756C6553 + 2949 00 + 2950 .LASF48: + 2951 00b8 725F6E65 .ascii "r_newer\000" + 2951 77657200 + 2952 .LASF41: + 2953 00c0 72656761 .ascii "regarm_t\000" + 2953 726D5F74 + 2953 00 + 2954 .LASF65: + 2955 00c9 6368436F .ascii "chCondSignal\000" + 2955 6E645369 + 2955 676E616C + 2955 00 + 2956 .LASF19: + 2957 00d6 636E745F .ascii "cnt_t\000" + 2957 7400 + 2958 .LASF86: + 2959 00dc 63684D74 .ascii "chMtxUnlockS\000" + 2959 78556E6C + 2959 6F636B53 + 2959 00 + 2960 .LASF0: + 2961 00e9 756E7369 .ascii "unsigned int\000" + 2961 676E6564 + 2961 20696E74 + 2961 00 + 2962 .LASF9: + 2963 00f6 6C6F6E67 .ascii "long unsigned int\000" + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 54 + + + 2963 20756E73 + 2963 69676E65 + 2963 6420696E + 2963 7400 + 2964 .LASF43: + 2965 0108 636F6E74 .ascii "context\000" + 2965 65787400 + 2966 .LASF4: + 2967 0110 73686F72 .ascii "short unsigned int\000" + 2967 7420756E + 2967 7369676E + 2967 65642069 + 2967 6E7400 + 2968 .LASF16: + 2969 0123 6D73675F .ascii "msg_t\000" + 2969 7400 + 2970 .LASF82: + 2971 0129 7072696F .ascii "prio_insert\000" + 2971 5F696E73 + 2971 65727400 + 2972 .LASF12: + 2973 0135 746D6F64 .ascii "tmode_t\000" + 2973 655F7400 + 2974 .LASF40: + 2975 013d 54687265 .ascii "ThreadsList\000" + 2975 6164734C + 2975 69737400 + 2976 .LASF17: + 2977 0149 6576656E .ascii "eventmask_t\000" + 2977 746D6173 + 2977 6B5F7400 + 2978 .LASF53: + 2979 0155 4D757465 .ascii "Mutex\000" + 2979 7800 + 2980 .LASF44: + 2981 015b 73697A65 .ascii "sizetype\000" + 2981 74797065 + 2981 00 + 2982 .LASF71: + 2983 0164 6368436F .ascii "chCondWaitTimeoutS\000" + 2983 6E645761 + 2983 69745469 + 2983 6D656F75 + 2983 745300 + 2984 .LASF26: + 2985 0177 705F6F6C .ascii "p_older\000" + 2985 64657200 + 2986 .LASF80: + 2987 017f 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 2987 73657273 + 2987 5C496D61 + 2987 6E6F6C5C + 2987 64657665 + 2988 01ac 6C696361 .ascii "lications\\smartcities\000" + 2988 74696F6E + 2988 735C736D + 2988 61727463 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 55 + + + 2988 69746965 + 2989 .LASF39: + 2990 01c2 54687265 .ascii "ThreadsQueue\000" + 2990 61647351 + 2990 75657565 + 2990 00 + 2991 .LASF72: + 2992 01cf 74696D65 .ascii "time\000" + 2992 00 + 2993 .LASF78: + 2994 01d4 474E5520 .ascii "GNU C 4.7.2\000" + 2994 4320342E + 2994 372E3200 + 2995 .LASF51: + 2996 01e0 725F6375 .ascii "r_current\000" + 2996 7272656E + 2996 7400 + 2997 .LASF49: + 2998 01ea 725F6F6C .ascii "r_older\000" + 2998 64657200 + 2999 .LASF68: + 3000 01f2 6368436F .ascii "chCondBroadcast\000" + 3000 6E644272 + 3000 6F616463 + 3000 61737400 + 3001 .LASF14: + 3002 0202 74726566 .ascii "trefs_t\000" + 3002 735F7400 + 3003 .LASF22: + 3004 020a 705F7072 .ascii "p_prev\000" + 3004 657600 + 3005 .LASF15: + 3006 0211 74707269 .ascii "tprio_t\000" + 3006 6F5F7400 + 3007 .LASF66: + 3008 0219 6368436F .ascii "chCondSignalI\000" + 3008 6E645369 + 3008 676E616C + 3008 4900 + 3009 .LASF6: + 3010 0227 696E7433 .ascii "int32_t\000" + 3010 325F7400 + 3011 .LASF2: + 3012 022f 756E7369 .ascii "unsigned char\000" + 3012 676E6564 + 3012 20636861 + 3012 7200 + 3013 .LASF36: + 3014 023d 705F6D74 .ascii "p_mtxlist\000" + 3014 786C6973 + 3014 7400 + 3015 .LASF3: + 3016 0247 73686F72 .ascii "short int\000" + 3016 7420696E + 3016 7400 + 3017 .LASF28: + 3018 0251 705F7374 .ascii "p_state\000" + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 56 + + + 3018 61746500 + 3019 .LASF46: + 3020 0259 725F7072 .ascii "r_prio\000" + 3020 696F00 + 3021 .LASF62: + 3022 0260 65776D61 .ascii "ewmask\000" + 3022 736B00 + 3023 .LASF21: + 3024 0267 705F6E65 .ascii "p_next\000" + 3024 787400 + 3025 .LASF29: + 3026 026e 705F666C .ascii "p_flags\000" + 3026 61677300 + 3027 .LASF20: + 3028 0276 54687265 .ascii "Thread\000" + 3028 616400 + 3029 .LASF58: + 3030 027d 635F7175 .ascii "c_queue\000" + 3030 65756500 + 3031 .LASF75: + 3032 0285 63685363 .ascii "chSchGoSleepS\000" + 3032 68476F53 + 3032 6C656570 + 3032 5300 + 3033 .LASF35: + 3034 0293 705F6570 .ascii "p_epending\000" + 3034 656E6469 + 3034 6E6700 + 3035 .LASF8: + 3036 029e 75696E74 .ascii "uint32_t\000" + 3036 33325F74 + 3036 00 + 3037 .LASF45: + 3038 02a7 725F7175 .ascii "r_queue\000" + 3038 65756500 + 3039 .LASF84: + 3040 02af 63685363 .ascii "chSchReadyI\000" + 3040 68526561 + 3040 64794900 + 3041 .LASF63: + 3042 02bb 63686172 .ascii "char\000" + 3042 00 + 3043 .LASF81: + 3044 02c0 6669666F .ascii "fifo_remove\000" + 3044 5F72656D + 3044 6F766500 + 3045 .LASF69: + 3046 02cc 6368436F .ascii "chCondWaitS\000" + 3046 6E645761 + 3046 69745300 + 3047 .LASF56: + 3048 02d8 6D5F6E65 .ascii "m_next\000" + 3048 787400 + 3049 .LASF18: + 3050 02df 73797374 .ascii "systime_t\000" + 3050 696D655F + 3050 7400 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 57 + + + 3051 .LASF37: + 3052 02e9 705F7265 .ascii "p_realprio\000" + 3052 616C7072 + 3052 696F00 + 3053 .LASF70: + 3054 02f4 6368436F .ascii "chCondWait\000" + 3054 6E645761 + 3054 697400 + 3055 .LASF31: + 3056 02ff 705F7469 .ascii "p_time\000" + 3056 6D6500 + 3057 .LASF47: + 3058 0306 725F6374 .ascii "r_ctx\000" + 3058 7800 + 3059 .LASF42: + 3060 030c 696E7463 .ascii "intctx\000" + 3060 747800 + 3061 .LASF33: + 3062 0313 705F6D73 .ascii "p_msgqueue\000" + 3062 67717565 + 3062 756500 + 3063 .LASF74: + 3064 031e 63685363 .ascii "chSchWakeupS\000" + 3064 6857616B + 3064 65757053 + 3064 00 + 3065 .LASF30: + 3066 032b 705F7265 .ascii "p_refs\000" + 3066 667300 + 3067 .LASF52: + 3068 0332 52656164 .ascii "ReadyList\000" + 3068 794C6973 + 3068 7400 + 3069 .LASF83: + 3070 033c 726C6973 .ascii "rlist\000" + 3070 7400 + 3071 .LASF5: + 3072 0342 75696E74 .ascii "uint8_t\000" + 3072 385F7400 + 3073 .LASF79: + 3074 034a 2E2E2F2E .ascii "../..//os/kernel/src/chcond.c\000" + 3074 2E2F2F6F + 3074 732F6B65 + 3074 726E656C + 3074 2F737263 + 3075 .LASF61: + 3076 0368 77746F62 .ascii "wtobjp\000" + 3076 6A7000 + 3077 .LASF27: + 3078 036f 705F6E61 .ascii "p_name\000" + 3078 6D6500 + 3079 .LASF73: + 3080 0376 6368436F .ascii "chCondWaitTimeout\000" + 3080 6E645761 + 3080 69745469 + 3080 6D656F75 + 3080 7400 + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 58 + + + 3081 .LASF77: + 3082 0388 63685363 .ascii "chSchGoSleepTimeoutS\000" + 3082 68476F53 + 3082 6C656570 + 3082 54696D65 + 3082 6F757453 + 3083 .LASF50: + 3084 039d 725F7072 .ascii "r_preempt\000" + 3084 65656D70 + 3084 7400 + 3085 .LASF55: + 3086 03a7 6D5F6F77 .ascii "m_owner\000" + 3086 6E657200 + 3087 .LASF24: + 3088 03af 705F6374 .ascii "p_ctx\000" + 3088 7800 + 3089 .LASF32: + 3090 03b5 705F7761 .ascii "p_waiting\000" + 3090 6974696E + 3090 6700 + 3091 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\ccOKjfT6.s page 59 + + +DEFINED SYMBOLS + *ABS*:00000000 chcond.c +C:\cygwin\tmp\ccOKjfT6.s:19 .text.chCondInit:00000000 $t +C:\cygwin\tmp\ccOKjfT6.s:25 .text.chCondInit:00000000 chCondInit +C:\cygwin\tmp\ccOKjfT6.s:42 .text.chCondSignal:00000000 $t +C:\cygwin\tmp\ccOKjfT6.s:48 .text.chCondSignal:00000000 chCondSignal +C:\cygwin\tmp\ccOKjfT6.s:103 .text.chCondSignalI:00000000 $t +C:\cygwin\tmp\ccOKjfT6.s:109 .text.chCondSignalI:00000000 chCondSignalI +C:\cygwin\tmp\ccOKjfT6.s:149 .text.chCondBroadcastI:00000000 $t +C:\cygwin\tmp\ccOKjfT6.s:155 .text.chCondBroadcastI:00000000 chCondBroadcastI +C:\cygwin\tmp\ccOKjfT6.s:203 .text.chCondBroadcast:00000000 $t +C:\cygwin\tmp\ccOKjfT6.s:209 .text.chCondBroadcast:00000000 chCondBroadcast +C:\cygwin\tmp\ccOKjfT6.s:242 .text.chCondWaitS:00000000 $t +C:\cygwin\tmp\ccOKjfT6.s:248 .text.chCondWaitS:00000000 chCondWaitS +C:\cygwin\tmp\ccOKjfT6.s:338 .text.chCondWaitS:00000044 $d +C:\cygwin\tmp\ccOKjfT6.s:345 .text.chCondWait:00000000 $t +C:\cygwin\tmp\ccOKjfT6.s:351 .text.chCondWait:00000000 chCondWait +C:\cygwin\tmp\ccOKjfT6.s:382 .text.chCondWaitTimeoutS:00000000 $t +C:\cygwin\tmp\ccOKjfT6.s:388 .text.chCondWaitTimeoutS:00000000 chCondWaitTimeoutS +C:\cygwin\tmp\ccOKjfT6.s:480 .text.chCondWaitTimeoutS:00000048 $d +C:\cygwin\tmp\ccOKjfT6.s:485 .text.chCondWaitTimeout:00000000 $t +C:\cygwin\tmp\ccOKjfT6.s:491 .text.chCondWaitTimeout:00000000 chCondWaitTimeout + .debug_frame:00000010 $d +C:\cygwin\tmp\ccOKjfT6.s:344 .text.chCondWaitS:00000048 $t +C:\cygwin\tmp\ccOKjfT6.s:484 .text.chCondWaitTimeoutS:0000004c $t + +UNDEFINED SYMBOLS +chSchWakeupS +chSchReadyI +chSchRescheduleS +chMtxUnlockS +chSchGoSleepS +chMtxLockS +rlist +chSchGoSleepTimeoutS diff --git a/Project/applications/smartcities/build/lst/chcore.lst b/Project/applications/smartcities/build/lst/chcore.lst new file mode 100644 index 0000000..e07d801 --- /dev/null +++ b/Project/applications/smartcities/build/lst/chcore.lst @@ -0,0 +1,322 @@ +ARM GAS C:\cygwin\tmp\ccrSEfV4.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "chcore.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text.port_halt,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .weak port_halt + 22 .thumb + 23 .thumb_func + 24 .type port_halt, %function + 25 port_halt: + 26 .LFB7: + 27 .file 1 "../..//os/ports/GCC/ARMCMx/chcore.c" + 28 .loc 1 46 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .loc 1 48 0 + 34 @ 48 "../..//os/ports/GCC/ARMCMx/chcore.c" 1 + 35 0000 72B6 cpsid i + 36 @ 0 "" 2 + 37 .thumb + 38 .L2: + 39 0002 FEE7 b .L2 + 40 .cfi_endproc + 41 .LFE7: + 42 .size port_halt, .-port_halt + 43 0004 AFF30080 .text + 43 AFF30080 + 43 AFF30080 + 44 .Letext0: + 45 .section .debug_info,"",%progbits + 46 .Ldebug_info0: + 47 0000 8F000000 .4byte 0x8f + 48 0004 0200 .2byte 0x2 + 49 0006 00000000 .4byte .Ldebug_abbrev0 + 50 000a 04 .byte 0x4 + 51 000b 01 .uleb128 0x1 + 52 000c 5E000000 .4byte .LASF11 + 53 0010 01 .byte 0x1 + 54 0011 93000000 .4byte .LASF12 + 55 0015 1B000000 .4byte .LASF13 + ARM GAS C:\cygwin\tmp\ccrSEfV4.s page 2 + + + 56 0019 00000000 .4byte .Ldebug_ranges0+0 + 57 001d 00000000 .4byte 0 + 58 0021 00000000 .4byte 0 + 59 0025 00000000 .4byte .Ldebug_line0 + 60 0029 02 .uleb128 0x2 + 61 002a 04 .byte 0x4 + 62 002b 05 .byte 0x5 + 63 002c 696E7400 .ascii "int\000" + 64 0030 03 .uleb128 0x3 + 65 0031 04 .byte 0x4 + 66 0032 07 .byte 0x7 + 67 0033 0E000000 .4byte .LASF0 + 68 0037 03 .uleb128 0x3 + 69 0038 01 .byte 0x1 + 70 0039 06 .byte 0x6 + 71 003a E6000000 .4byte .LASF1 + 72 003e 03 .uleb128 0x3 + 73 003f 01 .byte 0x1 + 74 0040 08 .byte 0x8 + 75 0041 B7000000 .4byte .LASF2 + 76 0045 03 .uleb128 0x3 + 77 0046 02 .byte 0x2 + 78 0047 05 .byte 0x5 + 79 0048 FC000000 .4byte .LASF3 + 80 004c 03 .uleb128 0x3 + 81 004d 02 .byte 0x2 + 82 004e 07 .byte 0x7 + 83 004f D3000000 .4byte .LASF4 + 84 0053 03 .uleb128 0x3 + 85 0054 04 .byte 0x4 + 86 0055 05 .byte 0x5 + 87 0056 CA000000 .4byte .LASF5 + 88 005a 03 .uleb128 0x3 + 89 005b 04 .byte 0x4 + 90 005c 07 .byte 0x7 + 91 005d 6A000000 .4byte .LASF6 + 92 0061 03 .uleb128 0x3 + 93 0062 08 .byte 0x8 + 94 0063 05 .byte 0x5 + 95 0064 00000000 .4byte .LASF7 + 96 0068 03 .uleb128 0x3 + 97 0069 08 .byte 0x8 + 98 006a 07 .byte 0x7 + 99 006b 7C000000 .4byte .LASF8 + 100 006f 03 .uleb128 0x3 + 101 0070 04 .byte 0x4 + 102 0071 07 .byte 0x7 + 103 0072 06010000 .4byte .LASF9 + 104 0076 03 .uleb128 0x3 + 105 0077 01 .byte 0x1 + 106 0078 08 .byte 0x8 + 107 0079 C5000000 .4byte .LASF10 + 108 007d 04 .uleb128 0x4 + 109 007e 01 .byte 0x1 + 110 007f F2000000 .4byte .LASF14 + 111 0083 01 .byte 0x1 + 112 0084 2E .byte 0x2e + ARM GAS C:\cygwin\tmp\ccrSEfV4.s page 3 + + + 113 0085 01 .byte 0x1 + 114 0086 00000000 .4byte .LFB7 + 115 008a 04000000 .4byte .LFE7 + 116 008e 02 .byte 0x2 + 117 008f 7D .byte 0x7d + 118 0090 00 .sleb128 0 + 119 0091 01 .byte 0x1 + 120 0092 00 .byte 0 + 121 .section .debug_abbrev,"",%progbits + 122 .Ldebug_abbrev0: + 123 0000 01 .uleb128 0x1 + 124 0001 11 .uleb128 0x11 + 125 0002 01 .byte 0x1 + 126 0003 25 .uleb128 0x25 + 127 0004 0E .uleb128 0xe + 128 0005 13 .uleb128 0x13 + 129 0006 0B .uleb128 0xb + 130 0007 03 .uleb128 0x3 + 131 0008 0E .uleb128 0xe + 132 0009 1B .uleb128 0x1b + 133 000a 0E .uleb128 0xe + 134 000b 55 .uleb128 0x55 + 135 000c 06 .uleb128 0x6 + 136 000d 11 .uleb128 0x11 + 137 000e 01 .uleb128 0x1 + 138 000f 52 .uleb128 0x52 + 139 0010 01 .uleb128 0x1 + 140 0011 10 .uleb128 0x10 + 141 0012 06 .uleb128 0x6 + 142 0013 00 .byte 0 + 143 0014 00 .byte 0 + 144 0015 02 .uleb128 0x2 + 145 0016 24 .uleb128 0x24 + 146 0017 00 .byte 0 + 147 0018 0B .uleb128 0xb + 148 0019 0B .uleb128 0xb + 149 001a 3E .uleb128 0x3e + 150 001b 0B .uleb128 0xb + 151 001c 03 .uleb128 0x3 + 152 001d 08 .uleb128 0x8 + 153 001e 00 .byte 0 + 154 001f 00 .byte 0 + 155 0020 03 .uleb128 0x3 + 156 0021 24 .uleb128 0x24 + 157 0022 00 .byte 0 + 158 0023 0B .uleb128 0xb + 159 0024 0B .uleb128 0xb + 160 0025 3E .uleb128 0x3e + 161 0026 0B .uleb128 0xb + 162 0027 03 .uleb128 0x3 + 163 0028 0E .uleb128 0xe + 164 0029 00 .byte 0 + 165 002a 00 .byte 0 + 166 002b 04 .uleb128 0x4 + 167 002c 2E .uleb128 0x2e + 168 002d 00 .byte 0 + 169 002e 3F .uleb128 0x3f + ARM GAS C:\cygwin\tmp\ccrSEfV4.s page 4 + + + 170 002f 0C .uleb128 0xc + 171 0030 03 .uleb128 0x3 + 172 0031 0E .uleb128 0xe + 173 0032 3A .uleb128 0x3a + 174 0033 0B .uleb128 0xb + 175 0034 3B .uleb128 0x3b + 176 0035 0B .uleb128 0xb + 177 0036 27 .uleb128 0x27 + 178 0037 0C .uleb128 0xc + 179 0038 11 .uleb128 0x11 + 180 0039 01 .uleb128 0x1 + 181 003a 12 .uleb128 0x12 + 182 003b 01 .uleb128 0x1 + 183 003c 40 .uleb128 0x40 + 184 003d 0A .uleb128 0xa + 185 003e 9742 .uleb128 0x2117 + 186 0040 0C .uleb128 0xc + 187 0041 00 .byte 0 + 188 0042 00 .byte 0 + 189 0043 00 .byte 0 + 190 .section .debug_aranges,"",%progbits + 191 0000 1C000000 .4byte 0x1c + 192 0004 0200 .2byte 0x2 + 193 0006 00000000 .4byte .Ldebug_info0 + 194 000a 04 .byte 0x4 + 195 000b 00 .byte 0 + 196 000c 0000 .2byte 0 + 197 000e 0000 .2byte 0 + 198 0010 00000000 .4byte .LFB7 + 199 0014 04000000 .4byte .LFE7-.LFB7 + 200 0018 00000000 .4byte 0 + 201 001c 00000000 .4byte 0 + 202 .section .debug_ranges,"",%progbits + 203 .Ldebug_ranges0: + 204 0000 00000000 .4byte .LFB7 + 205 0004 04000000 .4byte .LFE7 + 206 0008 00000000 .4byte 0 + 207 000c 00000000 .4byte 0 + 208 .section .debug_line,"",%progbits + 209 .Ldebug_line0: + 210 0000 50000000 .section .debug_str,"MS",%progbits,1 + 210 02003A00 + 210 00000201 + 210 FB0E0D00 + 210 01010101 + 211 .LASF7: + 212 0000 6C6F6E67 .ascii "long long int\000" + 212 206C6F6E + 212 6720696E + 212 7400 + 213 .LASF0: + 214 000e 756E7369 .ascii "unsigned int\000" + 214 676E6564 + 214 20696E74 + 214 00 + 215 .LASF13: + 216 001b 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + ARM GAS C:\cygwin\tmp\ccrSEfV4.s page 5 + + + 216 73657273 + 216 5C496D61 + 216 6E6F6C5C + 216 64657665 + 217 0048 6C696361 .ascii "lications\\smartcities\000" + 217 74696F6E + 217 735C736D + 217 61727463 + 217 69746965 + 218 .LASF11: + 219 005e 474E5520 .ascii "GNU C 4.7.2\000" + 219 4320342E + 219 372E3200 + 220 .LASF6: + 221 006a 6C6F6E67 .ascii "long unsigned int\000" + 221 20756E73 + 221 69676E65 + 221 6420696E + 221 7400 + 222 .LASF8: + 223 007c 6C6F6E67 .ascii "long long unsigned int\000" + 223 206C6F6E + 223 6720756E + 223 7369676E + 223 65642069 + 224 .LASF12: + 225 0093 2E2E2F2E .ascii "../..//os/ports/GCC/ARMCMx/chcore.c\000" + 225 2E2F2F6F + 225 732F706F + 225 7274732F + 225 4743432F + 226 .LASF2: + 227 00b7 756E7369 .ascii "unsigned char\000" + 227 676E6564 + 227 20636861 + 227 7200 + 228 .LASF10: + 229 00c5 63686172 .ascii "char\000" + 229 00 + 230 .LASF5: + 231 00ca 6C6F6E67 .ascii "long int\000" + 231 20696E74 + 231 00 + 232 .LASF4: + 233 00d3 73686F72 .ascii "short unsigned int\000" + 233 7420756E + 233 7369676E + 233 65642069 + 233 6E7400 + 234 .LASF1: + 235 00e6 7369676E .ascii "signed char\000" + 235 65642063 + 235 68617200 + 236 .LASF14: + 237 00f2 706F7274 .ascii "port_halt\000" + 237 5F68616C + 237 7400 + ARM GAS C:\cygwin\tmp\ccrSEfV4.s page 6 + + + 238 .LASF3: + 239 00fc 73686F72 .ascii "short int\000" + 239 7420696E + 239 7400 + 240 .LASF9: + 241 0106 73697A65 .ascii "sizetype\000" + 241 74797065 + 241 00 + 242 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\ccrSEfV4.s page 7 + + +DEFINED SYMBOLS + *ABS*:00000000 chcore.c +C:\cygwin\tmp\ccrSEfV4.s:19 .text.port_halt:00000000 $t +C:\cygwin\tmp\ccrSEfV4.s:25 .text.port_halt:00000000 port_halt + .debug_frame:00000010 $d + +NO UNDEFINED SYMBOLS diff --git a/Project/applications/smartcities/build/lst/chcore_v7m.lst b/Project/applications/smartcities/build/lst/chcore_v7m.lst new file mode 100644 index 0000000..2399a96 --- /dev/null +++ b/Project/applications/smartcities/build/lst/chcore_v7m.lst @@ -0,0 +1,2536 @@ +ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "chcore_v7m.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text._port_switch_from_isr,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .global _port_switch_from_isr + 22 .thumb + 23 .thumb_func + 24 .type _port_switch_from_isr, %function + 25 _port_switch_from_isr: + 26 .LFB11: + 27 .file 1 "../..//os/ports/GCC/ARMCMx/chcore_v7m.c" + 28 .loc 1 207 0 + 29 .cfi_startproc + 30 @ Naked Function: prologue and epilogue provided by programmer. + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 .loc 1 210 0 + 34 0000 FFF7FEFF bl chSchDoReschedule + 35 .LVL0: + 36 .loc 1 212 0 + 37 @ 212 "../..//os/ports/GCC/ARMCMx/chcore_v7m.c" 1 + 38 _port_exit_from_isr: + 39 @ 0 "" 2 + 40 .loc 1 216 0 + 41 .thumb + 42 0004 4FF46D43 mov r3, #60672 + 43 0008 CEF20003 movt r3, 57344 + 44 000c 4FF08052 mov r2, #268435456 + 45 0010 5A60 str r2, [r3, #4] + 46 .loc 1 217 0 + 47 @ 217 "../..//os/ports/GCC/ARMCMx/chcore_v7m.c" 1 + 48 0012 62B6 cpsie i + 49 @ 0 "" 2 + 50 .thumb + 51 .L2: + 52 0014 FEE7 b .L2 + 53 .cfi_endproc + 54 .LFE11: + 55 .size _port_switch_from_isr, .-_port_switch_from_isr + 56 0016 00BFAFF3 .section .text.PendSVVector,"ax",%progbits + 56 0080AFF3 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 2 + + + 56 0080 + 57 .align 2 + 58 .p2align 4,,15 + 59 .global PendSVVector + 60 .thumb + 61 .thumb_func + 62 .type PendSVVector, %function + 63 PendSVVector: + 64 .LFB8: + 65 .loc 1 92 0 + 66 .cfi_startproc + 67 @ args = 0, pretend = 0, frame = 0 + 68 @ frame_needed = 0, uses_anonymous_args = 0 + 69 @ link register save eliminated. + 70 .loc 1 96 0 + 71 @ 96 "../..//os/ports/GCC/ARMCMx/chcore_v7m.c" 1 + 72 0000 EFF30983 mrs r3, PSP + 73 @ 0 "" 2 + 74 .LVL1: + 75 .loc 1 100 0 + 76 .thumb + 77 0004 2033 adds r3, r3, #32 + 78 .LVL2: + 79 .loc 1 107 0 + 80 @ 107 "../..//os/ports/GCC/ARMCMx/chcore_v7m.c" 1 + 81 0006 83F30988 msr PSP, r3 + 82 @ 0 "" 2 + 83 .thumb + 84 000a 7047 bx lr + 85 .cfi_endproc + 86 .LFE8: + 87 .size PendSVVector, .-PendSVVector + 88 000c AFF30080 .section .text._port_init,"ax",%progbits + 89 .align 2 + 90 .p2align 4,,15 + 91 .global _port_init + 92 .thumb + 93 .thumb_func + 94 .type _port_init, %function + 95 _port_init: + 96 .LFB9: + 97 .loc 1 118 0 + 98 .cfi_startproc + 99 @ args = 0, pretend = 0, frame = 0 + 100 @ frame_needed = 0, uses_anonymous_args = 0 + 101 .loc 1 122 0 + 102 0000 0022 movs r2, #0 + 103 .loc 1 121 0 + 104 0002 4FF46D43 mov r3, #60672 + 105 .loc 1 118 0 + 106 0006 10B5 push {r4, lr} + 107 .LCFI0: + 108 .cfi_def_cfa_offset 8 + 109 .cfi_offset 4, -8 + 110 .cfi_offset 14, -4 + 111 .loc 1 121 0 + 112 0008 CEF20003 movt r3, 57344 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 3 + + + 113 000c 1446 mov r4, r2 + 114 .loc 1 122 0 + 115 000e C0F2FA52 movt r2, 1530 + 116 .loc 1 121 0 + 117 0012 9C60 str r4, [r3, #8] + 118 .loc 1 125 0 + 119 0014 0720 movs r0, #7 + 120 0016 1021 movs r1, #16 + 121 .loc 1 122 0 + 122 0018 DA60 str r2, [r3, #12] + 123 .loc 1 125 0 + 124 001a FFF7FEFF bl nvicSetSystemHandlerPriority + 125 .LVL3: + 126 .loc 1 127 0 + 127 001e 0A20 movs r0, #10 + 128 0020 2146 mov r1, r4 + 129 0022 FFF7FEFF bl nvicSetSystemHandlerPriority + 130 .LVL4: + 131 .loc 1 129 0 + 132 0026 0B20 movs r0, #11 + 133 0028 8021 movs r1, #128 + 134 .loc 1 131 0 + 135 002a BDE81040 pop {r4, lr} + 136 .loc 1 129 0 + 137 002e FFF7FEBF b nvicSetSystemHandlerPriority + 138 .LVL5: + 139 .cfi_endproc + 140 .LFE9: + 141 .size _port_init, .-_port_init + 142 0032 00BFAFF3 .section .text._port_irq_epilogue,"ax",%progbits + 142 0080AFF3 + 142 0080AFF3 + 142 0080 + 143 .align 2 + 144 .p2align 4,,15 + 145 .global _port_irq_epilogue + 146 .thumb + 147 .thumb_func + 148 .type _port_irq_epilogue, %function + 149 _port_irq_epilogue: + 150 .LFB10: + 151 .loc 1 148 0 + 152 .cfi_startproc + 153 @ args = 0, pretend = 0, frame = 0 + 154 @ frame_needed = 0, uses_anonymous_args = 0 + 155 @ link register save eliminated. + 156 .loc 1 150 0 + 157 @ 150 "../..//os/ports/GCC/ARMCMx/chcore_v7m.c" 1 + 158 0000 72B6 cpsid i + 159 @ 0 "" 2 + 160 .loc 1 151 0 + 161 .thumb + 162 0002 4FF46D43 mov r3, #60672 + 163 0006 CEF20003 movt r3, 57344 + 164 000a 5B68 ldr r3, [r3, #4] + 165 000c 1B05 lsls r3, r3, #20 + 166 000e 19D5 bpl .L7 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 4 + + + 167 .LBB2: + 168 .loc 1 155 0 + 169 @ 155 "../..//os/ports/GCC/ARMCMx/chcore_v7m.c" 1 + 170 0010 EFF30983 mrs r3, PSP + 171 @ 0 "" 2 + 172 .LVL6: + 173 .loc 1 159 0 + 174 .thumb + 175 0014 A3F12002 sub r2, r3, #32 + 176 .LVL7: + 177 .loc 1 160 0 + 178 @ 160 "../..//os/ports/GCC/ARMCMx/chcore_v7m.c" 1 + 179 0018 82F30988 msr PSP, r2 + 180 @ 0 "" 2 + 181 .loc 1 165 0 + 182 .thumb + 183 001c 114A ldr r2, .L13 + 184 .LVL8: + 185 .loc 1 161 0 + 186 001e 4FF08070 mov r0, #16777216 + 187 .loc 1 165 0 + 188 0022 9169 ldr r1, [r2, #24] + 189 .loc 1 161 0 + 190 0024 43F8040C str r0, [r3, #-4] + 191 .loc 1 165 0 + 192 0028 71B1 cbz r1, .L8 + 193 .loc 1 165 0 is_stmt 0 discriminator 1 + 194 002a 1168 ldr r1, [r2, #0] + 195 002c D269 ldr r2, [r2, #28] + 196 002e 8968 ldr r1, [r1, #8] + 197 0030 9268 ldr r2, [r2, #8] + 198 0032 9142 cmp r1, r2 + 199 0034 94BF ite ls + 200 0036 0022 movls r2, #0 + 201 0038 0122 movhi r2, #1 + 202 003a 7AB1 cbz r2, .L10 + 203 .L12: + 204 .loc 1 167 0 is_stmt 1 + 205 003c 0A4A ldr r2, .L13+4 + 206 003e 43F8082C str r2, [r3, #-8] + 207 0042 7047 bx lr + 208 .LVL9: + 209 .L7: + 210 .LBE2: + 211 .loc 1 197 0 + 212 @ 197 "../..//os/ports/GCC/ARMCMx/chcore_v7m.c" 1 + 213 0044 62B6 cpsie i + 214 @ 0 "" 2 + 215 .thumb + 216 0046 7047 bx lr + 217 .LVL10: + 218 .L8: + 219 .LBB3: + 220 .loc 1 165 0 discriminator 2 + 221 0048 1168 ldr r1, [r2, #0] + 222 004a D269 ldr r2, [r2, #28] + 223 004c 8968 ldr r1, [r1, #8] + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 5 + + + 224 004e 9268 ldr r2, [r2, #8] + 225 0050 9142 cmp r1, r2 + 226 0052 34BF ite cc + 227 0054 0022 movcc r2, #0 + 228 0056 0122 movcs r2, #1 + 229 0058 002A cmp r2, #0 + 230 005a EFD1 bne .L12 + 231 .L10: + 232 .loc 1 176 0 + 233 005c 034A ldr r2, .L13+8 + 234 005e 43F8082C str r2, [r3, #-8] + 235 0062 7047 bx lr + 236 .L14: + 237 .align 2 + 238 .L13: + 239 0064 00000000 .word rlist + 240 0068 00000000 .word _port_switch_from_isr + 241 006c 04000000 .word _port_exit_from_isr + 242 .LBE3: + 243 .cfi_endproc + 244 .LFE10: + 245 .size _port_irq_epilogue, .-_port_irq_epilogue + 246 .section .text.SysTickVector,"ax",%progbits + 247 .align 2 + 248 .p2align 4,,15 + 249 .global SysTickVector + 250 .thumb + 251 .thumb_func + 252 .type SysTickVector, %function + 253 SysTickVector: + 254 .LFB7: + 255 .loc 1 47 0 + 256 .cfi_startproc + 257 @ args = 0, pretend = 0, frame = 0 + 258 @ frame_needed = 0, uses_anonymous_args = 0 + 259 0000 08B5 push {r3, lr} + 260 .LCFI1: + 261 .cfi_def_cfa_offset 8 + 262 .cfi_offset 3, -8 + 263 .cfi_offset 14, -4 + 264 .loc 1 51 0 + 265 @ 51 "../..//os/ports/GCC/ARMCMx/chcore_v7m.c" 1 + 266 0002 72B6 cpsid i + 267 @ 0 "" 2 + 268 .loc 1 52 0 + 269 .thumb + 270 0004 FFF7FEFF bl chSysTimerHandlerI + 271 .LVL11: + 272 .loc 1 53 0 + 273 @ 53 "../..//os/ports/GCC/ARMCMx/chcore_v7m.c" 1 + 274 0008 62B6 cpsie i + 275 @ 0 "" 2 + 276 .loc 1 56 0 + 277 .thumb + 278 000a BDE80840 pop {r3, lr} + 279 .loc 1 55 0 + 280 000e FFF7FEBF b _port_irq_epilogue + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 6 + + + 281 .LVL12: + 282 .cfi_endproc + 283 .LFE7: + 284 .size SysTickVector, .-SysTickVector + 285 0012 00BFAFF3 .section .text._port_switch,"ax",%progbits + 285 0080AFF3 + 285 0080AFF3 + 285 0080 + 286 .align 2 + 287 .p2align 4,,15 + 288 .global _port_switch + 289 .thumb + 290 .thumb_func + 291 .type _port_switch, %function + 292 _port_switch: + 293 .LFB12: + 294 .loc 1 236 0 + 295 .cfi_startproc + 296 @ Naked Function: prologue and epilogue provided by programmer. + 297 @ args = 0, pretend = 0, frame = 0 + 298 @ frame_needed = 0, uses_anonymous_args = 0 + 299 .LVL13: + 300 .loc 1 238 0 + 301 @ 238 "../..//os/ports/GCC/ARMCMx/chcore_v7m.c" 1 + 302 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, r11, lr} + 303 @ 0 "" 2 + 304 .loc 1 244 0 + 305 @ 244 "../..//os/ports/GCC/ARMCMx/chcore_v7m.c" 1 + 306 0004 C1F80CD0 str sp, [r1, #12] + 307 0008 D0F80CD0 ldr sp, [r0, #12] + 308 @ 0 "" 2 + 309 .loc 1 250 0 + 310 @ 250 "../..//os/ports/GCC/ARMCMx/chcore_v7m.c" 1 + 311 000c BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} + 312 @ 0 "" 2 + 313 .loc 1 252 0 + 314 .thumb + 315 .cfi_endproc + 316 .LFE12: + 317 .size _port_switch, .-_port_switch + 318 .section .text._port_thread_start,"ax",%progbits + 319 .align 2 + 320 .p2align 4,,15 + 321 .global _port_thread_start + 322 .thumb + 323 .thumb_func + 324 .type _port_thread_start, %function + 325 _port_thread_start: + 326 .LFB13: + 327 .loc 1 259 0 + 328 .cfi_startproc + 329 @ args = 0, pretend = 0, frame = 0 + 330 @ frame_needed = 0, uses_anonymous_args = 0 + 331 @ link register save eliminated. + 332 .loc 1 261 0 + 333 @ 261 "../..//os/ports/GCC/ARMCMx/chcore_v7m.c" 1 + 334 0000 62B6 cpsie i + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 7 + + + 335 @ 0 "" 2 + 336 .loc 1 262 0 + 337 @ 262 "../..//os/ports/GCC/ARMCMx/chcore_v7m.c" 1 + 338 0002 2846 mov r0, r5 + 339 0004 A047 blx r4 + 340 0006 FFF7FEFF bl chThdExit + 341 @ 0 "" 2 + 342 .thumb + 343 000a 7047 bx lr + 344 .cfi_endproc + 345 .LFE13: + 346 .size _port_thread_start, .-_port_thread_start + 347 000c AFF30080 .text + 348 .Letext0: + 349 .file 2 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 350 .file 3 "../..//os/ports/GCC/ARMCMx/chtypes.h" + 351 .file 4 "../..//os/kernel/include/chlists.h" + 352 .file 5 "../..//os/kernel/include/chthreads.h" + 353 .file 6 "../..//os/ports/GCC/ARMCMx/chcore_v7m.h" + 354 .file 7 "../..//os/ports/common/ARMCMx/nvic.h" + 355 .file 8 "../..//os/kernel/include/chschd.h" + 356 .file 9 "../..//os/kernel/include/chmtx.h" + 357 .file 10 "../..//os/kernel/include/chsys.h" + 358 .section .debug_info,"",%progbits + 359 .Ldebug_info0: + 360 0000 E5070000 .4byte 0x7e5 + 361 0004 0200 .2byte 0x2 + 362 0006 00000000 .4byte .Ldebug_abbrev0 + 363 000a 04 .byte 0x4 + 364 000b 01 .uleb128 0x1 + 365 000c 6B020000 .4byte .LASF91 + 366 0010 01 .byte 0x1 + 367 0011 00000000 .4byte .LASF92 + 368 0015 1B020000 .4byte .LASF93 + 369 0019 18000000 .4byte .Ldebug_ranges0+0x18 + 370 001d 00000000 .4byte 0 + 371 0021 00000000 .4byte 0 + 372 0025 00000000 .4byte .Ldebug_line0 + 373 0029 02 .uleb128 0x2 + 374 002a 04 .byte 0x4 + 375 002b 05 .byte 0x5 + 376 002c 696E7400 .ascii "int\000" + 377 0030 03 .uleb128 0x3 + 378 0031 04 .byte 0x4 + 379 0032 07 .byte 0x7 + 380 0033 33010000 .4byte .LASF0 + 381 0037 03 .uleb128 0x3 + 382 0038 01 .byte 0x1 + 383 0039 06 .byte 0x6 + 384 003a 9F000000 .4byte .LASF1 + 385 003e 04 .uleb128 0x4 + 386 003f 9C030000 .4byte .LASF5 + 387 0043 02 .byte 0x2 + 388 0044 2A .byte 0x2a + 389 0045 49000000 .4byte 0x49 + 390 0049 03 .uleb128 0x3 + 391 004a 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 8 + + + 392 004b 08 .byte 0x8 + 393 004c AD020000 .4byte .LASF2 + 394 0050 03 .uleb128 0x3 + 395 0051 02 .byte 0x2 + 396 0052 05 .byte 0x5 + 397 0053 CB020000 .4byte .LASF3 + 398 0057 03 .uleb128 0x3 + 399 0058 02 .byte 0x2 + 400 0059 07 .byte 0x7 + 401 005a 9D010000 .4byte .LASF4 + 402 005e 04 .uleb128 0x4 + 403 005f A5020000 .4byte .LASF6 + 404 0063 02 .byte 0x2 + 405 0064 4F .byte 0x4f + 406 0065 69000000 .4byte 0x69 + 407 0069 03 .uleb128 0x3 + 408 006a 04 .byte 0x4 + 409 006b 05 .byte 0x5 + 410 006c BB000000 .4byte .LASF7 + 411 0070 04 .uleb128 0x4 + 412 0071 11030000 .4byte .LASF8 + 413 0075 02 .byte 0x2 + 414 0076 50 .byte 0x50 + 415 0077 7B000000 .4byte 0x7b + 416 007b 03 .uleb128 0x3 + 417 007c 04 .byte 0x4 + 418 007d 07 .byte 0x7 + 419 007e 5B010000 .4byte .LASF9 + 420 0082 03 .uleb128 0x3 + 421 0083 08 .byte 0x8 + 422 0084 05 .byte 0x5 + 423 0085 91000000 .4byte .LASF10 + 424 0089 03 .uleb128 0x3 + 425 008a 08 .byte 0x8 + 426 008b 07 .byte 0x7 + 427 008c 5E000000 .4byte .LASF11 + 428 0090 04 .uleb128 0x4 + 429 0091 DF010000 .4byte .LASF12 + 430 0095 03 .byte 0x3 + 431 0096 2F .byte 0x2f + 432 0097 3E000000 .4byte 0x3e + 433 009b 04 .uleb128 0x4 + 434 009c C4000000 .4byte .LASF13 + 435 00a0 03 .byte 0x3 + 436 00a1 30 .byte 0x30 + 437 00a2 3E000000 .4byte 0x3e + 438 00a6 04 .uleb128 0x4 + 439 00a7 89020000 .4byte .LASF14 + 440 00ab 03 .byte 0x3 + 441 00ac 31 .byte 0x31 + 442 00ad 3E000000 .4byte 0x3e + 443 00b1 04 .uleb128 0x4 + 444 00b2 9D020000 .4byte .LASF15 + 445 00b6 03 .byte 0x3 + 446 00b7 32 .byte 0x32 + 447 00b8 70000000 .4byte 0x70 + 448 00bc 04 .uleb128 0x4 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 9 + + + 449 00bd B5010000 .4byte .LASF16 + 450 00c1 03 .byte 0x3 + 451 00c2 33 .byte 0x33 + 452 00c3 5E000000 .4byte 0x5e + 453 00c7 04 .uleb128 0x4 + 454 00c8 F3010000 .4byte .LASF17 + 455 00cc 03 .byte 0x3 + 456 00cd 35 .byte 0x35 + 457 00ce 70000000 .4byte 0x70 + 458 00d2 04 .uleb128 0x4 + 459 00d3 43030000 .4byte .LASF18 + 460 00d7 03 .byte 0x3 + 461 00d8 36 .byte 0x36 + 462 00d9 70000000 .4byte 0x70 + 463 00dd 04 .uleb128 0x4 + 464 00de 2D010000 .4byte .LASF19 + 465 00e2 03 .byte 0x3 + 466 00e3 37 .byte 0x37 + 467 00e4 5E000000 .4byte 0x5e + 468 00e8 04 .uleb128 0x4 + 469 00e9 FF020000 .4byte .LASF20 + 470 00ed 04 .byte 0x4 + 471 00ee 2A .byte 0x2a + 472 00ef F3000000 .4byte 0xf3 + 473 00f3 05 .uleb128 0x5 + 474 00f4 FF020000 .4byte .LASF20 + 475 00f8 48 .byte 0x48 + 476 00f9 05 .byte 0x5 + 477 00fa 5E .byte 0x5e + 478 00fb 0A020000 .4byte 0x20a + 479 00ff 06 .uleb128 0x6 + 480 0100 F0020000 .4byte .LASF21 + 481 0104 05 .byte 0x5 + 482 0105 5F .byte 0x5f + 483 0106 2F020000 .4byte 0x22f + 484 010a 02 .byte 0x2 + 485 010b 23 .byte 0x23 + 486 010c 00 .uleb128 0 + 487 010d 06 .uleb128 0x6 + 488 010e 96020000 .4byte .LASF22 + 489 0112 05 .byte 0x5 + 490 0113 61 .byte 0x61 + 491 0114 2F020000 .4byte 0x22f + 492 0118 02 .byte 0x2 + 493 0119 23 .byte 0x23 + 494 011a 04 .uleb128 0x4 + 495 011b 06 .uleb128 0x6 + 496 011c 8A000000 .4byte .LASF23 + 497 0120 05 .byte 0x5 + 498 0121 63 .byte 0x63 + 499 0122 B1000000 .4byte 0xb1 + 500 0126 02 .byte 0x2 + 501 0127 23 .byte 0x23 + 502 0128 08 .uleb128 0x8 + 503 0129 06 .uleb128 0x6 + 504 012a D0030000 .4byte .LASF24 + 505 012e 05 .byte 0x5 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 10 + + + 506 012f 64 .byte 0x64 + 507 0130 74030000 .4byte 0x374 + 508 0134 02 .byte 0x2 + 509 0135 23 .byte 0x23 + 510 0136 0C .uleb128 0xc + 511 0137 06 .uleb128 0x6 + 512 0138 E0000000 .4byte .LASF25 + 513 013c 05 .byte 0x5 + 514 013d 66 .byte 0x66 + 515 013e 2F020000 .4byte 0x22f + 516 0142 02 .byte 0x2 + 517 0143 23 .byte 0x23 + 518 0144 10 .uleb128 0x10 + 519 0145 06 .uleb128 0x6 + 520 0146 13020000 .4byte .LASF26 + 521 014a 05 .byte 0x5 + 522 014b 67 .byte 0x67 + 523 014c 2F020000 .4byte 0x22f + 524 0150 02 .byte 0x2 + 525 0151 23 .byte 0x23 + 526 0152 14 .uleb128 0x14 + 527 0153 06 .uleb128 0x6 + 528 0154 B6030000 .4byte .LASF27 + 529 0158 05 .byte 0x5 + 530 0159 6E .byte 0x6e + 531 015a 3A060000 .4byte 0x63a + 532 015e 02 .byte 0x2 + 533 015f 23 .byte 0x23 + 534 0160 18 .uleb128 0x18 + 535 0161 06 .uleb128 0x6 + 536 0162 D5020000 .4byte .LASF28 + 537 0166 05 .byte 0x5 + 538 0167 79 .byte 0x79 + 539 0168 9B000000 .4byte 0x9b + 540 016c 02 .byte 0x2 + 541 016d 23 .byte 0x23 + 542 016e 1C .uleb128 0x1c + 543 016f 06 .uleb128 0x6 + 544 0170 F7020000 .4byte .LASF29 + 545 0174 05 .byte 0x5 + 546 0175 7D .byte 0x7d + 547 0176 90000000 .4byte 0x90 + 548 017a 02 .byte 0x2 + 549 017b 23 .byte 0x23 + 550 017c 1D .uleb128 0x1d + 551 017d 06 .uleb128 0x6 + 552 017e 80030000 .4byte .LASF30 + 553 0182 05 .byte 0x5 + 554 0183 82 .byte 0x82 + 555 0184 A6000000 .4byte 0xa6 + 556 0188 02 .byte 0x2 + 557 0189 23 .byte 0x23 + 558 018a 1E .uleb128 0x1e + 559 018b 06 .uleb128 0x6 + 560 018c 62030000 .4byte .LASF31 + 561 0190 05 .byte 0x5 + 562 0191 89 .byte 0x89 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 11 + + + 563 0192 42050000 .4byte 0x542 + 564 0196 02 .byte 0x2 + 565 0197 23 .byte 0x23 + 566 0198 20 .uleb128 0x20 + 567 0199 07 .uleb128 0x7 + 568 019a 705F7500 .ascii "p_u\000" + 569 019e 05 .byte 0x5 + 570 019f AE .byte 0xae + 571 01a0 05060000 .4byte 0x605 + 572 01a4 02 .byte 0x2 + 573 01a5 23 .byte 0x23 + 574 01a6 24 .uleb128 0x24 + 575 01a7 06 .uleb128 0x6 + 576 01a8 D6030000 .4byte .LASF32 + 577 01ac 05 .byte 0x5 + 578 01ad B3 .byte 0xb3 + 579 01ae 57020000 .4byte 0x257 + 580 01b2 02 .byte 0x2 + 581 01b3 23 .byte 0x23 + 582 01b4 28 .uleb128 0x28 + 583 01b5 06 .uleb128 0x6 + 584 01b6 75030000 .4byte .LASF33 + 585 01ba 05 .byte 0x5 + 586 01bb B9 .byte 0xb9 + 587 01bc 35020000 .4byte 0x235 + 588 01c0 02 .byte 0x2 + 589 01c1 23 .byte 0x23 + 590 01c2 2C .uleb128 0x2c + 591 01c3 06 .uleb128 0x6 + 592 01c4 28000000 .4byte .LASF34 + 593 01c8 05 .byte 0x5 + 594 01c9 BD .byte 0xbd + 595 01ca BC000000 .4byte 0xbc + 596 01ce 02 .byte 0x2 + 597 01cf 23 .byte 0x23 + 598 01d0 34 .uleb128 0x34 + 599 01d1 06 .uleb128 0x6 + 600 01d2 06030000 .4byte .LASF35 + 601 01d6 05 .byte 0x5 + 602 01d7 C3 .byte 0xc3 + 603 01d8 C7000000 .4byte 0xc7 + 604 01dc 02 .byte 0x2 + 605 01dd 23 .byte 0x23 + 606 01de 38 .uleb128 0x38 + 607 01df 06 .uleb128 0x6 + 608 01e0 C1020000 .4byte .LASF36 + 609 01e4 05 .byte 0x5 + 610 01e5 CA .byte 0xca + 611 01e6 4C060000 .4byte 0x64c + 612 01ea 02 .byte 0x2 + 613 01eb 23 .byte 0x23 + 614 01ec 3C .uleb128 0x3c + 615 01ed 06 .uleb128 0x6 + 616 01ee 4D030000 .4byte .LASF37 + 617 01f2 05 .byte 0x5 + 618 01f3 CE .byte 0xce + 619 01f4 B1000000 .4byte 0xb1 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 12 + + + 620 01f8 02 .byte 0x2 + 621 01f9 23 .byte 0x23 + 622 01fa 40 .uleb128 0x40 + 623 01fb 06 .uleb128 0x6 + 624 01fc AB000000 .4byte .LASF38 + 625 0200 05 .byte 0x5 + 626 0201 D4 .byte 0xd4 + 627 0202 6D020000 .4byte 0x26d + 628 0206 02 .byte 0x2 + 629 0207 23 .byte 0x23 + 630 0208 44 .uleb128 0x44 + 631 0209 00 .byte 0 + 632 020a 08 .uleb128 0x8 + 633 020b 08 .byte 0x8 + 634 020c 04 .byte 0x4 + 635 020d 61 .byte 0x61 + 636 020e 2F020000 .4byte 0x22f + 637 0212 06 .uleb128 0x6 + 638 0213 F0020000 .4byte .LASF21 + 639 0217 04 .byte 0x4 + 640 0218 62 .byte 0x62 + 641 0219 2F020000 .4byte 0x22f + 642 021d 02 .byte 0x2 + 643 021e 23 .byte 0x23 + 644 021f 00 .uleb128 0 + 645 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0x11 + 1198 060e 2E000000 .4byte .LASF77 + 1199 0612 05 .byte 0x5 + 1200 0613 97 .byte 0x97 + 1201 0614 BC000000 .4byte 0xbc + 1202 0618 11 .uleb128 0x11 + 1203 0619 75000000 .4byte .LASF78 + 1204 061d 05 .byte 0x5 + 1205 061e 9E .byte 0x9e + 1206 061f BC000000 .4byte 0xbc + 1207 0623 11 .uleb128 0x11 + 1208 0624 A4030000 .4byte .LASF79 + 1209 0628 05 .byte 0x5 + 1210 0629 A5 .byte 0xa5 + 1211 062a 6D020000 .4byte 0x26d + 1212 062e 11 .uleb128 0x11 + 1213 062f E9020000 .4byte .LASF80 + 1214 0633 05 .byte 0x5 + 1215 0634 AC .byte 0xac + 1216 0635 C7000000 .4byte 0xc7 + 1217 0639 00 .byte 0 + 1218 063a 09 .uleb128 0x9 + 1219 063b 04 .byte 0x4 + 1220 063c 40060000 .4byte 0x640 + 1221 0640 12 .uleb128 0x12 + 1222 0641 45060000 .4byte 0x645 + 1223 0645 03 .uleb128 0x3 + 1224 0646 01 .byte 0x1 + 1225 0647 08 .byte 0x8 + 1226 0648 2F030000 .4byte .LASF81 + 1227 064c 09 .uleb128 0x9 + 1228 064d 04 .byte 0x4 + 1229 064e FA050000 .4byte 0x5fa + 1230 0652 13 .uleb128 0x13 + 1231 0653 01 .byte 0x1 + 1232 0654 7F010000 .4byte .LASF82 + 1233 0658 01 .byte 0x1 + 1234 0659 CF .byte 0xcf + 1235 065a 01 .byte 0x1 + 1236 065b 00000000 .4byte .LFB11 + 1237 065f 16000000 .4byte .LFE11 + 1238 0663 02 .byte 0x2 + 1239 0664 7D .byte 0x7d + 1240 0665 00 .sleb128 0 + 1241 0666 01 .byte 0x1 + 1242 0667 75060000 .4byte 0x675 + 1243 066b 14 .uleb128 0x14 + 1244 066c 04000000 .4byte .LVL0 + 1245 0670 BA070000 .4byte 0x7ba + 1246 0674 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 23 + + + 1247 0675 13 .uleb128 0x13 + 1248 0676 01 .byte 0x1 + 1249 0677 6D010000 .4byte .LASF83 + 1250 067b 01 .byte 0x1 + 1251 067c 5C .byte 0x5c + 1252 067d 01 .byte 0x1 + 1253 067e 00000000 .4byte .LFB8 + 1254 0682 0C000000 .4byte .LFE8 + 1255 0686 02 .byte 0x2 + 1256 0687 7D .byte 0x7d + 1257 0688 00 .sleb128 0 + 1258 0689 01 .byte 0x1 + 1259 068a 9E060000 .4byte 0x69e + 1260 068e 15 .uleb128 0x15 + 1261 068f 91020000 .4byte .LASF86 + 1262 0693 01 .byte 0x1 + 1263 0694 5D .byte 0x5d + 1264 0695 9E060000 .4byte 0x69e + 1265 0699 00000000 .4byte .LLST0 + 1266 069d 00 .byte 0 + 1267 069e 09 .uleb128 0x9 + 1268 069f 04 .byte 0x4 + 1269 06a0 6F020000 .4byte 0x26f + 1270 06a4 16 .uleb128 0x16 + 1271 06a5 01 .byte 0x1 + 1272 06a6 AB030000 .4byte .LASF84 + 1273 06aa 01 .byte 0x1 + 1274 06ab 76 .byte 0x76 + 1275 06ac 01 .byte 0x1 + 1276 06ad 00000000 .4byte .LFB9 + 1277 06b1 32000000 .4byte .LFE9 + 1278 06b5 20000000 .4byte .LLST1 + 1279 06b9 01 .byte 0x1 + 1280 06ba 06070000 .4byte 0x706 + 1281 06be 17 .uleb128 0x17 + 1282 06bf 1E000000 .4byte .LVL3 + 1283 06c3 C4070000 .4byte 0x7c4 + 1284 06c7 D6060000 .4byte 0x6d6 + 1285 06cb 18 .uleb128 0x18 + 1286 06cc 01 .byte 0x1 + 1287 06cd 51 .byte 0x51 + 1288 06ce 01 .byte 0x1 + 1289 06cf 40 .byte 0x40 + 1290 06d0 18 .uleb128 0x18 + 1291 06d1 01 .byte 0x1 + 1292 06d2 50 .byte 0x50 + 1293 06d3 01 .byte 0x1 + 1294 06d4 37 .byte 0x37 + 1295 06d5 00 .byte 0 + 1296 06d6 17 .uleb128 0x17 + 1297 06d7 26000000 .4byte .LVL4 + 1298 06db C4070000 .4byte 0x7c4 + 1299 06df EF060000 .4byte 0x6ef + 1300 06e3 18 .uleb128 0x18 + 1301 06e4 01 .byte 0x1 + 1302 06e5 51 .byte 0x51 + 1303 06e6 02 .byte 0x2 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 24 + + + 1304 06e7 74 .byte 0x74 + 1305 06e8 00 .sleb128 0 + 1306 06e9 18 .uleb128 0x18 + 1307 06ea 01 .byte 0x1 + 1308 06eb 50 .byte 0x50 + 1309 06ec 01 .byte 0x1 + 1310 06ed 3A .byte 0x3a + 1311 06ee 00 .byte 0 + 1312 06ef 19 .uleb128 0x19 + 1313 06f0 32000000 .4byte .LVL5 + 1314 06f4 01 .byte 0x1 + 1315 06f5 C4070000 .4byte 0x7c4 + 1316 06f9 18 .uleb128 0x18 + 1317 06fa 01 .byte 0x1 + 1318 06fb 51 .byte 0x51 + 1319 06fc 02 .byte 0x2 + 1320 06fd 08 .byte 0x8 + 1321 06fe 80 .byte 0x80 + 1322 06ff 18 .uleb128 0x18 + 1323 0700 01 .byte 0x1 + 1324 0701 50 .byte 0x50 + 1325 0702 01 .byte 0x1 + 1326 0703 3B .byte 0x3b + 1327 0704 00 .byte 0 + 1328 0705 00 .byte 0 + 1329 0706 13 .uleb128 0x13 + 1330 0707 01 .byte 0x1 + 1331 0708 CC010000 .4byte .LASF85 + 1332 070c 01 .byte 0x1 + 1333 070d 94 .byte 0x94 + 1334 070e 01 .byte 0x1 + 1335 070f 00000000 .4byte .LFB10 + 1336 0713 70000000 .4byte .LFE10 + 1337 0717 02 .byte 0x2 + 1338 0718 7D .byte 0x7d + 1339 0719 00 .sleb128 0 + 1340 071a 01 .byte 0x1 + 1341 071b 35070000 .4byte 0x735 + 1342 071f 1A .uleb128 0x1a + 1343 0720 00000000 .4byte .Ldebug_ranges0+0 + 1344 0724 15 .uleb128 0x15 + 1345 0725 91020000 .4byte .LASF86 + 1346 0729 01 .byte 0x1 + 1347 072a 98 .byte 0x98 + 1348 072b 9E060000 .4byte 0x69e + 1349 072f 40000000 .4byte .LLST2 + 1350 0733 00 .byte 0 + 1351 0734 00 .byte 0 + 1352 0735 16 .uleb128 0x16 + 1353 0736 01 .byte 0x1 + 1354 0737 50000000 .4byte .LASF87 + 1355 073b 01 .byte 0x1 + 1356 073c 2F .byte 0x2f + 1357 073d 01 .byte 0x1 + 1358 073e 00000000 .4byte .LFB7 + 1359 0742 12000000 .4byte .LFE7 + 1360 0746 7A000000 .4byte .LLST3 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 25 + + + 1361 074a 01 .byte 0x1 + 1362 074b 63070000 .4byte 0x763 + 1363 074f 14 .uleb128 0x14 + 1364 0750 08000000 .4byte .LVL11 + 1365 0754 DE070000 .4byte 0x7de + 1366 0758 1B .uleb128 0x1b + 1367 0759 12000000 .4byte .LVL12 + 1368 075d 01 .byte 0x1 + 1369 075e 06070000 .4byte 0x706 + 1370 0762 00 .byte 0 + 1371 0763 13 .uleb128 0x13 + 1372 0764 01 .byte 0x1 + 1373 0765 4E010000 .4byte .LASF88 + 1374 0769 01 .byte 0x1 + 1375 076a EC .byte 0xec + 1376 076b 01 .byte 0x1 + 1377 076c 00000000 .4byte .LFB12 + 1378 0770 10000000 .4byte .LFE12 + 1379 0774 02 .byte 0x2 + 1380 0775 7D .byte 0x7d + 1381 0776 00 .sleb128 0 + 1382 0777 01 .byte 0x1 + 1383 0778 97070000 .4byte 0x797 + 1384 077c 1C .uleb128 0x1c + 1385 077d 6E747000 .ascii "ntp\000" + 1386 0781 01 .byte 0x1 + 1387 0782 EC .byte 0xec + 1388 0783 2F020000 .4byte 0x22f + 1389 0787 01 .byte 0x1 + 1390 0788 50 .byte 0x50 + 1391 0789 1C .uleb128 0x1c + 1392 078a 6F747000 .ascii "otp\000" + 1393 078e 01 .byte 0x1 + 1394 078f EC .byte 0xec + 1395 0790 2F020000 .4byte 0x22f + 1396 0794 01 .byte 0x1 + 1397 0795 51 .byte 0x51 + 1398 0796 00 .byte 0 + 1399 0797 1D .uleb128 0x1d + 1400 0798 01 .byte 0x1 + 1401 0799 CD000000 .4byte .LASF94 + 1402 079d 01 .byte 0x1 + 1403 079e 0301 .2byte 0x103 + 1404 07a0 01 .byte 0x1 + 1405 07a1 00000000 .4byte .LFB13 + 1406 07a5 0C000000 .4byte .LFE13 + 1407 07a9 02 .byte 0x2 + 1408 07aa 7D .byte 0x7d + 1409 07ab 00 .sleb128 0 + 1410 07ac 01 .byte 0x1 + 1411 07ad 1E .uleb128 0x1e + 1412 07ae 96030000 .4byte .LASF95 + 1413 07b2 08 .byte 0x8 + 1414 07b3 72 .byte 0x72 + 1415 07b4 B2050000 .4byte 0x5b2 + 1416 07b8 01 .byte 0x1 + 1417 07b9 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 26 + + + 1418 07ba 1F .uleb128 0x1f + 1419 07bb 01 .byte 0x1 + 1420 07bc 1B010000 .4byte .LASF89 + 1421 07c0 08 .byte 0x8 + 1422 07c1 A5 .byte 0xa5 + 1423 07c2 01 .byte 0x1 + 1424 07c3 01 .byte 0x1 + 1425 07c4 20 .uleb128 0x20 + 1426 07c5 01 .byte 0x1 + 1427 07c6 F5000000 .4byte .LASF96 + 1428 07ca 07 .byte 0x7 + 1429 07cb 2501 .2byte 0x125 + 1430 07cd 01 .byte 0x1 + 1431 07ce 01 .byte 0x1 + 1432 07cf DE070000 .4byte 0x7de + 1433 07d3 21 .uleb128 0x21 + 1434 07d4 70000000 .4byte 0x70 + 1435 07d8 21 .uleb128 0x21 + 1436 07d9 70000000 .4byte 0x70 + 1437 07dd 00 .byte 0 + 1438 07de 1F .uleb128 0x1f + 1439 07df 01 .byte 0x1 + 1440 07e0 3D000000 .4byte .LASF90 + 1441 07e4 0A .byte 0xa + 1442 07e5 F7 .byte 0xf7 + 1443 07e6 01 .byte 0x1 + 1444 07e7 01 .byte 0x1 + 1445 07e8 00 .byte 0 + 1446 .section .debug_abbrev,"",%progbits + 1447 .Ldebug_abbrev0: + 1448 0000 01 .uleb128 0x1 + 1449 0001 11 .uleb128 0x11 + 1450 0002 01 .byte 0x1 + 1451 0003 25 .uleb128 0x25 + 1452 0004 0E .uleb128 0xe + 1453 0005 13 .uleb128 0x13 + 1454 0006 0B .uleb128 0xb + 1455 0007 03 .uleb128 0x3 + 1456 0008 0E .uleb128 0xe + 1457 0009 1B .uleb128 0x1b + 1458 000a 0E .uleb128 0xe + 1459 000b 55 .uleb128 0x55 + 1460 000c 06 .uleb128 0x6 + 1461 000d 11 .uleb128 0x11 + 1462 000e 01 .uleb128 0x1 + 1463 000f 52 .uleb128 0x52 + 1464 0010 01 .uleb128 0x1 + 1465 0011 10 .uleb128 0x10 + 1466 0012 06 .uleb128 0x6 + 1467 0013 00 .byte 0 + 1468 0014 00 .byte 0 + 1469 0015 02 .uleb128 0x2 + 1470 0016 24 .uleb128 0x24 + 1471 0017 00 .byte 0 + 1472 0018 0B .uleb128 0xb + 1473 0019 0B .uleb128 0xb + 1474 001a 3E .uleb128 0x3e + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 27 + + + 1475 001b 0B .uleb128 0xb + 1476 001c 03 .uleb128 0x3 + 1477 001d 08 .uleb128 0x8 + 1478 001e 00 .byte 0 + 1479 001f 00 .byte 0 + 1480 0020 03 .uleb128 0x3 + 1481 0021 24 .uleb128 0x24 + 1482 0022 00 .byte 0 + 1483 0023 0B .uleb128 0xb + 1484 0024 0B .uleb128 0xb + 1485 0025 3E .uleb128 0x3e + 1486 0026 0B .uleb128 0xb + 1487 0027 03 .uleb128 0x3 + 1488 0028 0E .uleb128 0xe + 1489 0029 00 .byte 0 + 1490 002a 00 .byte 0 + 1491 002b 04 .uleb128 0x4 + 1492 002c 16 .uleb128 0x16 + 1493 002d 00 .byte 0 + 1494 002e 03 .uleb128 0x3 + 1495 002f 0E .uleb128 0xe + 1496 0030 3A .uleb128 0x3a + 1497 0031 0B .uleb128 0xb + 1498 0032 3B .uleb128 0x3b + 1499 0033 0B .uleb128 0xb + 1500 0034 49 .uleb128 0x49 + 1501 0035 13 .uleb128 0x13 + 1502 0036 00 .byte 0 + 1503 0037 00 .byte 0 + 1504 0038 05 .uleb128 0x5 + 1505 0039 13 .uleb128 0x13 + 1506 003a 01 .byte 0x1 + 1507 003b 03 .uleb128 0x3 + 1508 003c 0E .uleb128 0xe + 1509 003d 0B .uleb128 0xb + 1510 003e 0B .uleb128 0xb + 1511 003f 3A .uleb128 0x3a + 1512 0040 0B .uleb128 0xb + 1513 0041 3B .uleb128 0x3b + 1514 0042 0B .uleb128 0xb + 1515 0043 01 .uleb128 0x1 + 1516 0044 13 .uleb128 0x13 + 1517 0045 00 .byte 0 + 1518 0046 00 .byte 0 + 1519 0047 06 .uleb128 0x6 + 1520 0048 0D .uleb128 0xd + 1521 0049 00 .byte 0 + 1522 004a 03 .uleb128 0x3 + 1523 004b 0E .uleb128 0xe + 1524 004c 3A .uleb128 0x3a + 1525 004d 0B .uleb128 0xb + 1526 004e 3B .uleb128 0x3b + 1527 004f 0B .uleb128 0xb + 1528 0050 49 .uleb128 0x49 + 1529 0051 13 .uleb128 0x13 + 1530 0052 38 .uleb128 0x38 + 1531 0053 0A .uleb128 0xa + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 28 + + + 1532 0054 00 .byte 0 + 1533 0055 00 .byte 0 + 1534 0056 07 .uleb128 0x7 + 1535 0057 0D .uleb128 0xd + 1536 0058 00 .byte 0 + 1537 0059 03 .uleb128 0x3 + 1538 005a 08 .uleb128 0x8 + 1539 005b 3A .uleb128 0x3a + 1540 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0081 00 .byte 0 + 1578 0082 0B .uleb128 0xb + 1579 0083 0D .uleb128 0xd + 1580 0084 00 .byte 0 + 1581 0085 03 .uleb128 0x3 + 1582 0086 08 .uleb128 0x8 + 1583 0087 3A .uleb128 0x3a + 1584 0088 0B .uleb128 0xb + 1585 0089 3B .uleb128 0x3b + 1586 008a 05 .uleb128 0x5 + 1587 008b 49 .uleb128 0x49 + 1588 008c 13 .uleb128 0x13 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 29 + + + 1589 008d 38 .uleb128 0x38 + 1590 008e 0A .uleb128 0xa + 1591 008f 00 .byte 0 + 1592 0090 00 .byte 0 + 1593 0091 0C .uleb128 0xc + 1594 0092 13 .uleb128 0x13 + 1595 0093 01 .byte 0x1 + 1596 0094 03 .uleb128 0x3 + 1597 0095 0E .uleb128 0xe + 1598 0096 0B .uleb128 0xb + 1599 0097 0B .uleb128 0xb + 1600 0098 3A .uleb128 0x3a + 1601 0099 0B .uleb128 0xb + 1602 009a 3B .uleb128 0x3b + 1603 009b 05 .uleb128 0x5 + 1604 009c 01 .uleb128 0x1 + 1605 009d 13 .uleb128 0x13 + 1606 009e 00 .byte 0 + 1607 009f 00 .byte 0 + 1608 00a0 0D .uleb128 0xd + 1609 00a1 35 .uleb128 0x35 + 1610 00a2 00 .byte 0 + 1611 00a3 49 .uleb128 0x49 + 1612 00a4 13 .uleb128 0x13 + 1613 00a5 00 .byte 0 + 1614 00a6 00 .byte 0 + 1615 00a7 0E .uleb128 0xe + 1616 00a8 01 .uleb128 0x1 + 1617 00a9 01 .byte 0x1 + 1618 00aa 49 .uleb128 0x49 + 1619 00ab 13 .uleb128 0x13 + 1620 00ac 01 .uleb128 0x1 + 1621 00ad 13 .uleb128 0x13 + 1622 00ae 00 .byte 0 + 1623 00af 00 .byte 0 + 1624 00b0 0F .uleb128 0xf + 1625 00b1 21 .uleb128 0x21 + 1626 00b2 00 .byte 0 + 1627 00b3 49 .uleb128 0x49 + 1628 00b4 13 .uleb128 0x13 + 1629 00b5 2F .uleb128 0x2f + 1630 00b6 0B .uleb128 0xb + 1631 00b7 00 .byte 0 + 1632 00b8 00 .byte 0 + 1633 00b9 10 .uleb128 0x10 + 1634 00ba 17 .uleb128 0x17 + 1635 00bb 01 .byte 0x1 + 1636 00bc 0B .uleb128 0xb + 1637 00bd 0B .uleb128 0xb + 1638 00be 3A .uleb128 0x3a + 1639 00bf 0B .uleb128 0xb + 1640 00c0 3B .uleb128 0x3b + 1641 00c1 0B .uleb128 0xb + 1642 00c2 01 .uleb128 0x1 + 1643 00c3 13 .uleb128 0x13 + 1644 00c4 00 .byte 0 + 1645 00c5 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 30 + + + 1646 00c6 11 .uleb128 0x11 + 1647 00c7 0D .uleb128 0xd + 1648 00c8 00 .byte 0 + 1649 00c9 03 .uleb128 0x3 + 1650 00ca 0E .uleb128 0xe + 1651 00cb 3A .uleb128 0x3a + 1652 00cc 0B .uleb128 0xb + 1653 00cd 3B .uleb128 0x3b + 1654 00ce 0B .uleb128 0xb + 1655 00cf 49 .uleb128 0x49 + 1656 00d0 13 .uleb128 0x13 + 1657 00d1 00 .byte 0 + 1658 00d2 00 .byte 0 + 1659 00d3 12 .uleb128 0x12 + 1660 00d4 26 .uleb128 0x26 + 1661 00d5 00 .byte 0 + 1662 00d6 49 .uleb128 0x49 + 1663 00d7 13 .uleb128 0x13 + 1664 00d8 00 .byte 0 + 1665 00d9 00 .byte 0 + 1666 00da 13 .uleb128 0x13 + 1667 00db 2E .uleb128 0x2e + 1668 00dc 01 .byte 0x1 + 1669 00dd 3F .uleb128 0x3f + 1670 00de 0C .uleb128 0xc + 1671 00df 03 .uleb128 0x3 + 1672 00e0 0E .uleb128 0xe + 1673 00e1 3A .uleb128 0x3a + 1674 00e2 0B .uleb128 0xb + 1675 00e3 3B .uleb128 0x3b + 1676 00e4 0B .uleb128 0xb + 1677 00e5 27 .uleb128 0x27 + 1678 00e6 0C .uleb128 0xc + 1679 00e7 11 .uleb128 0x11 + 1680 00e8 01 .uleb128 0x1 + 1681 00e9 12 .uleb128 0x12 + 1682 00ea 01 .uleb128 0x1 + 1683 00eb 40 .uleb128 0x40 + 1684 00ec 0A .uleb128 0xa + 1685 00ed 9742 .uleb128 0x2117 + 1686 00ef 0C .uleb128 0xc + 1687 00f0 01 .uleb128 0x1 + 1688 00f1 13 .uleb128 0x13 + 1689 00f2 00 .byte 0 + 1690 00f3 00 .byte 0 + 1691 00f4 14 .uleb128 0x14 + 1692 00f5 898201 .uleb128 0x4109 + 1693 00f8 00 .byte 0 + 1694 00f9 11 .uleb128 0x11 + 1695 00fa 01 .uleb128 0x1 + 1696 00fb 31 .uleb128 0x31 + 1697 00fc 13 .uleb128 0x13 + 1698 00fd 00 .byte 0 + 1699 00fe 00 .byte 0 + 1700 00ff 15 .uleb128 0x15 + 1701 0100 34 .uleb128 0x34 + 1702 0101 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 31 + + + 1703 0102 03 .uleb128 0x3 + 1704 0103 0E .uleb128 0xe + 1705 0104 3A .uleb128 0x3a + 1706 0105 0B .uleb128 0xb + 1707 0106 3B .uleb128 0x3b + 1708 0107 0B .uleb128 0xb + 1709 0108 49 .uleb128 0x49 + 1710 0109 13 .uleb128 0x13 + 1711 010a 02 .uleb128 0x2 + 1712 010b 06 .uleb128 0x6 + 1713 010c 00 .byte 0 + 1714 010d 00 .byte 0 + 1715 010e 16 .uleb128 0x16 + 1716 010f 2E .uleb128 0x2e + 1717 0110 01 .byte 0x1 + 1718 0111 3F .uleb128 0x3f + 1719 0112 0C .uleb128 0xc + 1720 0113 03 .uleb128 0x3 + 1721 0114 0E .uleb128 0xe + 1722 0115 3A .uleb128 0x3a + 1723 0116 0B .uleb128 0xb + 1724 0117 3B .uleb128 0x3b + 1725 0118 0B .uleb128 0xb + 1726 0119 27 .uleb128 0x27 + 1727 011a 0C .uleb128 0xc + 1728 011b 11 .uleb128 0x11 + 1729 011c 01 .uleb128 0x1 + 1730 011d 12 .uleb128 0x12 + 1731 011e 01 .uleb128 0x1 + 1732 011f 40 .uleb128 0x40 + 1733 0120 06 .uleb128 0x6 + 1734 0121 9742 .uleb128 0x2117 + 1735 0123 0C .uleb128 0xc + 1736 0124 01 .uleb128 0x1 + 1737 0125 13 .uleb128 0x13 + 1738 0126 00 .byte 0 + 1739 0127 00 .byte 0 + 1740 0128 17 .uleb128 0x17 + 1741 0129 898201 .uleb128 0x4109 + 1742 012c 01 .byte 0x1 + 1743 012d 11 .uleb128 0x11 + 1744 012e 01 .uleb128 0x1 + 1745 012f 31 .uleb128 0x31 + 1746 0130 13 .uleb128 0x13 + 1747 0131 01 .uleb128 0x1 + 1748 0132 13 .uleb128 0x13 + 1749 0133 00 .byte 0 + 1750 0134 00 .byte 0 + 1751 0135 18 .uleb128 0x18 + 1752 0136 8A8201 .uleb128 0x410a + 1753 0139 00 .byte 0 + 1754 013a 02 .uleb128 0x2 + 1755 013b 0A .uleb128 0xa + 1756 013c 9142 .uleb128 0x2111 + 1757 013e 0A .uleb128 0xa + 1758 013f 00 .byte 0 + 1759 0140 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 32 + + + 1760 0141 19 .uleb128 0x19 + 1761 0142 898201 .uleb128 0x4109 + 1762 0145 01 .byte 0x1 + 1763 0146 11 .uleb128 0x11 + 1764 0147 01 .uleb128 0x1 + 1765 0148 9542 .uleb128 0x2115 + 1766 014a 0C .uleb128 0xc + 1767 014b 31 .uleb128 0x31 + 1768 014c 13 .uleb128 0x13 + 1769 014d 00 .byte 0 + 1770 014e 00 .byte 0 + 1771 014f 1A .uleb128 0x1a + 1772 0150 0B .uleb128 0xb + 1773 0151 01 .byte 0x1 + 1774 0152 55 .uleb128 0x55 + 1775 0153 06 .uleb128 0x6 + 1776 0154 00 .byte 0 + 1777 0155 00 .byte 0 + 1778 0156 1B .uleb128 0x1b + 1779 0157 898201 .uleb128 0x4109 + 1780 015a 00 .byte 0 + 1781 015b 11 .uleb128 0x11 + 1782 015c 01 .uleb128 0x1 + 1783 015d 9542 .uleb128 0x2115 + 1784 015f 0C .uleb128 0xc + 1785 0160 31 .uleb128 0x31 + 1786 0161 13 .uleb128 0x13 + 1787 0162 00 .byte 0 + 1788 0163 00 .byte 0 + 1789 0164 1C .uleb128 0x1c + 1790 0165 05 .uleb128 0x5 + 1791 0166 00 .byte 0 + 1792 0167 03 .uleb128 0x3 + 1793 0168 08 .uleb128 0x8 + 1794 0169 3A .uleb128 0x3a + 1795 016a 0B .uleb128 0xb + 1796 016b 3B .uleb128 0x3b + 1797 016c 0B .uleb128 0xb + 1798 016d 49 .uleb128 0x49 + 1799 016e 13 .uleb128 0x13 + 1800 016f 02 .uleb128 0x2 + 1801 0170 0A .uleb128 0xa + 1802 0171 00 .byte 0 + 1803 0172 00 .byte 0 + 1804 0173 1D .uleb128 0x1d + 1805 0174 2E .uleb128 0x2e + 1806 0175 00 .byte 0 + 1807 0176 3F .uleb128 0x3f + 1808 0177 0C .uleb128 0xc + 1809 0178 03 .uleb128 0x3 + 1810 0179 0E .uleb128 0xe + 1811 017a 3A .uleb128 0x3a + 1812 017b 0B .uleb128 0xb + 1813 017c 3B .uleb128 0x3b + 1814 017d 05 .uleb128 0x5 + 1815 017e 27 .uleb128 0x27 + 1816 017f 0C .uleb128 0xc + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 33 + + + 1817 0180 11 .uleb128 0x11 + 1818 0181 01 .uleb128 0x1 + 1819 0182 12 .uleb128 0x12 + 1820 0183 01 .uleb128 0x1 + 1821 0184 40 .uleb128 0x40 + 1822 0185 0A .uleb128 0xa + 1823 0186 9742 .uleb128 0x2117 + 1824 0188 0C .uleb128 0xc + 1825 0189 00 .byte 0 + 1826 018a 00 .byte 0 + 1827 018b 1E .uleb128 0x1e + 1828 018c 34 .uleb128 0x34 + 1829 018d 00 .byte 0 + 1830 018e 03 .uleb128 0x3 + 1831 018f 0E .uleb128 0xe + 1832 0190 3A .uleb128 0x3a + 1833 0191 0B .uleb128 0xb + 1834 0192 3B .uleb128 0x3b + 1835 0193 0B .uleb128 0xb + 1836 0194 49 .uleb128 0x49 + 1837 0195 13 .uleb128 0x13 + 1838 0196 3F .uleb128 0x3f + 1839 0197 0C .uleb128 0xc + 1840 0198 3C .uleb128 0x3c + 1841 0199 0C .uleb128 0xc + 1842 019a 00 .byte 0 + 1843 019b 00 .byte 0 + 1844 019c 1F .uleb128 0x1f + 1845 019d 2E .uleb128 0x2e + 1846 019e 00 .byte 0 + 1847 019f 3F .uleb128 0x3f + 1848 01a0 0C .uleb128 0xc + 1849 01a1 03 .uleb128 0x3 + 1850 01a2 0E .uleb128 0xe + 1851 01a3 3A .uleb128 0x3a + 1852 01a4 0B .uleb128 0xb + 1853 01a5 3B .uleb128 0x3b + 1854 01a6 0B .uleb128 0xb + 1855 01a7 27 .uleb128 0x27 + 1856 01a8 0C .uleb128 0xc + 1857 01a9 3C .uleb128 0x3c + 1858 01aa 0C .uleb128 0xc + 1859 01ab 00 .byte 0 + 1860 01ac 00 .byte 0 + 1861 01ad 20 .uleb128 0x20 + 1862 01ae 2E .uleb128 0x2e + 1863 01af 01 .byte 0x1 + 1864 01b0 3F .uleb128 0x3f + 1865 01b1 0C .uleb128 0xc + 1866 01b2 03 .uleb128 0x3 + 1867 01b3 0E .uleb128 0xe + 1868 01b4 3A .uleb128 0x3a + 1869 01b5 0B .uleb128 0xb + 1870 01b6 3B .uleb128 0x3b + 1871 01b7 05 .uleb128 0x5 + 1872 01b8 27 .uleb128 0x27 + 1873 01b9 0C .uleb128 0xc + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 34 + + + 1874 01ba 3C .uleb128 0x3c + 1875 01bb 0C .uleb128 0xc + 1876 01bc 01 .uleb128 0x1 + 1877 01bd 13 .uleb128 0x13 + 1878 01be 00 .byte 0 + 1879 01bf 00 .byte 0 + 1880 01c0 21 .uleb128 0x21 + 1881 01c1 05 .uleb128 0x5 + 1882 01c2 00 .byte 0 + 1883 01c3 49 .uleb128 0x49 + 1884 01c4 13 .uleb128 0x13 + 1885 01c5 00 .byte 0 + 1886 01c6 00 .byte 0 + 1887 01c7 00 .byte 0 + 1888 .section .debug_loc,"",%progbits + 1889 .Ldebug_loc0: + 1890 .LLST0: + 1891 0000 04000000 .4byte .LVL1 + 1892 0004 06000000 .4byte .LVL2 + 1893 0008 0300 .2byte 0x3 + 1894 000a 73 .byte 0x73 + 1895 000b 20 .sleb128 32 + 1896 000c 9F .byte 0x9f + 1897 000d 06000000 .4byte .LVL2 + 1898 0011 0C000000 .4byte .LFE8 + 1899 0015 0100 .2byte 0x1 + 1900 0017 53 .byte 0x53 + 1901 0018 00000000 .4byte 0 + 1902 001c 00000000 .4byte 0 + 1903 .LLST1: + 1904 0020 00000000 .4byte .LFB9 + 1905 0024 08000000 .4byte .LCFI0 + 1906 0028 0200 .2byte 0x2 + 1907 002a 7D .byte 0x7d + 1908 002b 00 .sleb128 0 + 1909 002c 08000000 .4byte .LCFI0 + 1910 0030 32000000 .4byte .LFE9 + 1911 0034 0200 .2byte 0x2 + 1912 0036 7D .byte 0x7d + 1913 0037 08 .sleb128 8 + 1914 0038 00000000 .4byte 0 + 1915 003c 00000000 .4byte 0 + 1916 .LLST2: + 1917 0040 14000000 .4byte .LVL6 + 1918 0044 18000000 .4byte .LVL7 + 1919 0048 0300 .2byte 0x3 + 1920 004a 73 .byte 0x73 + 1921 004b 60 .sleb128 -32 + 1922 004c 9F .byte 0x9f + 1923 004d 18000000 .4byte .LVL7 + 1924 0051 1E000000 .4byte .LVL8 + 1925 0055 0100 .2byte 0x1 + 1926 0057 52 .byte 0x52 + 1927 0058 1E000000 .4byte .LVL8 + 1928 005c 44000000 .4byte .LVL9 + 1929 0060 0300 .2byte 0x3 + 1930 0062 73 .byte 0x73 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 35 + + + 1931 0063 60 .sleb128 -32 + 1932 0064 9F .byte 0x9f + 1933 0065 48000000 .4byte .LVL10 + 1934 0069 70000000 .4byte .LFE10 + 1935 006d 0300 .2byte 0x3 + 1936 006f 73 .byte 0x73 + 1937 0070 60 .sleb128 -32 + 1938 0071 9F .byte 0x9f + 1939 0072 00000000 .4byte 0 + 1940 0076 00000000 .4byte 0 + 1941 .LLST3: + 1942 007a 00000000 .4byte .LFB7 + 1943 007e 02000000 .4byte .LCFI1 + 1944 0082 0200 .2byte 0x2 + 1945 0084 7D .byte 0x7d + 1946 0085 00 .sleb128 0 + 1947 0086 02000000 .4byte .LCFI1 + 1948 008a 12000000 .4byte .LFE7 + 1949 008e 0200 .2byte 0x2 + 1950 0090 7D .byte 0x7d + 1951 0091 08 .sleb128 8 + 1952 0092 00000000 .4byte 0 + 1953 0096 00000000 .4byte 0 + 1954 .section .debug_aranges,"",%progbits + 1955 0000 4C000000 .4byte 0x4c + 1956 0004 0200 .2byte 0x2 + 1957 0006 00000000 .4byte .Ldebug_info0 + 1958 000a 04 .byte 0x4 + 1959 000b 00 .byte 0 + 1960 000c 0000 .2byte 0 + 1961 000e 0000 .2byte 0 + 1962 0010 00000000 .4byte .LFB11 + 1963 0014 16000000 .4byte .LFE11-.LFB11 + 1964 0018 00000000 .4byte .LFB8 + 1965 001c 0C000000 .4byte .LFE8-.LFB8 + 1966 0020 00000000 .4byte .LFB9 + 1967 0024 32000000 .4byte .LFE9-.LFB9 + 1968 0028 00000000 .4byte .LFB10 + 1969 002c 70000000 .4byte .LFE10-.LFB10 + 1970 0030 00000000 .4byte .LFB7 + 1971 0034 12000000 .4byte .LFE7-.LFB7 + 1972 0038 00000000 .4byte .LFB12 + 1973 003c 10000000 .4byte .LFE12-.LFB12 + 1974 0040 00000000 .4byte .LFB13 + 1975 0044 0C000000 .4byte .LFE13-.LFB13 + 1976 0048 00000000 .4byte 0 + 1977 004c 00000000 .4byte 0 + 1978 .section .debug_ranges,"",%progbits + 1979 .Ldebug_ranges0: + 1980 0000 10000000 .4byte .LBB2 + 1981 0004 44000000 .4byte .LBE2 + 1982 0008 48000000 .4byte .LBB3 + 1983 000c 70000000 .4byte .LBE3 + 1984 0010 00000000 .4byte 0 + 1985 0014 00000000 .4byte 0 + 1986 0018 00000000 .4byte .LFB11 + 1987 001c 16000000 .4byte .LFE11 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 36 + + + 1988 0020 00000000 .4byte .LFB8 + 1989 0024 0C000000 .4byte .LFE8 + 1990 0028 00000000 .4byte .LFB9 + 1991 002c 32000000 .4byte .LFE9 + 1992 0030 00000000 .4byte .LFB10 + 1993 0034 70000000 .4byte .LFE10 + 1994 0038 00000000 .4byte .LFB7 + 1995 003c 12000000 .4byte .LFE7 + 1996 0040 00000000 .4byte .LFB12 + 1997 0044 10000000 .4byte .LFE12 + 1998 0048 00000000 .4byte .LFB13 + 1999 004c 0C000000 .4byte .LFE13 + 2000 0050 00000000 .4byte 0 + 2001 0054 00000000 .4byte 0 + 2002 .section .debug_line,"",%progbits + 2003 .Ldebug_line0: + 2004 0000 CC010000 .section .debug_str,"MS",%progbits,1 + 2004 02001901 + 2004 00000201 + 2004 FB0E0D00 + 2004 01010101 + 2005 .LASF92: + 2006 0000 2E2E2F2E .ascii "../..//os/ports/GCC/ARMCMx/chcore_v7m.c\000" + 2006 2E2F2F6F + 2006 732F706F + 2006 7274732F + 2006 4743432F + 2007 .LASF34: + 2008 0028 705F6D73 .ascii "p_msg\000" + 2008 6700 + 2009 .LASF77: + 2010 002e 7264796D .ascii "rdymsg\000" + 2010 736700 + 2011 .LASF64: + 2012 0035 434D785F .ascii "CMx_SCB\000" + 2012 53434200 + 2013 .LASF90: + 2014 003d 63685379 .ascii "chSysTimerHandlerI\000" + 2014 7354696D + 2014 65724861 + 2014 6E646C65 + 2014 724900 + 2015 .LASF87: + 2016 0050 53797354 .ascii "SysTickVector\000" + 2016 69636B56 + 2016 6563746F + 2016 7200 + 2017 .LASF11: + 2018 005e 6C6F6E67 .ascii "long long unsigned int\000" + 2018 206C6F6E + 2018 6720756E + 2018 7369676E + 2018 65642069 + 2019 .LASF78: + 2020 0075 65786974 .ascii "exitcode\000" + 2020 636F6465 + 2020 00 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 37 + + + 2021 .LASF67: + 2022 007e 725F6374 .ascii "r_ctx\000" + 2022 7800 + 2023 .LASF49: + 2024 0084 43505549 .ascii "CPUID\000" + 2024 4400 + 2025 .LASF23: + 2026 008a 705F7072 .ascii "p_prio\000" + 2026 696F00 + 2027 .LASF10: + 2028 0091 6C6F6E67 .ascii "long long int\000" + 2028 206C6F6E + 2028 6720696E + 2028 7400 + 2029 .LASF1: + 2030 009f 7369676E .ascii "signed char\000" + 2030 65642063 + 2030 68617200 + 2031 .LASF38: + 2032 00ab 705F6D70 .ascii "p_mpool\000" + 2032 6F6F6C00 + 2033 .LASF74: + 2034 00b3 6D5F7175 .ascii "m_queue\000" + 2034 65756500 + 2035 .LASF7: + 2036 00bb 6C6F6E67 .ascii "long int\000" + 2036 20696E74 + 2036 00 + 2037 .LASF13: + 2038 00c4 74737461 .ascii "tstate_t\000" + 2038 74655F74 + 2038 00 + 2039 .LASF94: + 2040 00cd 5F706F72 .ascii "_port_thread_start\000" + 2040 745F7468 + 2040 72656164 + 2040 5F737461 + 2040 727400 + 2041 .LASF25: + 2042 00e0 705F6E65 .ascii "p_newer\000" + 2042 77657200 + 2043 .LASF59: + 2044 00e8 42464152 .ascii "BFAR\000" + 2044 00 + 2045 .LASF68: + 2046 00ed 725F6E65 .ascii "r_newer\000" + 2046 77657200 + 2047 .LASF96: + 2048 00f5 6E766963 .ascii "nvicSetSystemHandlerPriority\000" + 2048 53657453 + 2048 79737465 + 2048 6D48616E + 2048 646C6572 + 2049 .LASF41: + 2050 0112 72656761 .ascii "regarm_t\000" + 2050 726D5F74 + 2050 00 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 38 + + + 2051 .LASF89: + 2052 011b 63685363 .ascii "chSchDoReschedule\000" + 2052 68446F52 + 2052 65736368 + 2052 6564756C + 2052 6500 + 2053 .LASF19: + 2054 012d 636E745F .ascii "cnt_t\000" + 2054 7400 + 2055 .LASF0: + 2056 0133 756E7369 .ascii "unsigned int\000" + 2056 676E6564 + 2056 20696E74 + 2056 00 + 2057 .LASF43: + 2058 0140 6C725F74 .ascii "lr_thd\000" + 2058 686400 + 2059 .LASF42: + 2060 0147 65787463 .ascii "extctx\000" + 2060 747800 + 2061 .LASF88: + 2062 014e 5F706F72 .ascii "_port_switch\000" + 2062 745F7377 + 2062 69746368 + 2062 00 + 2063 .LASF9: + 2064 015b 6C6F6E67 .ascii "long unsigned int\000" + 2064 20756E73 + 2064 69676E65 + 2064 6420696E + 2064 7400 + 2065 .LASF83: + 2066 016d 50656E64 .ascii "PendSVVector\000" + 2066 53565665 + 2066 63746F72 + 2066 00 + 2067 .LASF51: + 2068 017a 56544F52 .ascii "VTOR\000" + 2068 00 + 2069 .LASF82: + 2070 017f 5F706F72 .ascii "_port_switch_from_isr\000" + 2070 745F7377 + 2070 69746368 + 2070 5F66726F + 2070 6D5F6973 + 2071 .LASF46: + 2072 0195 636F6E74 .ascii "context\000" + 2072 65787400 + 2073 .LASF4: + 2074 019d 73686F72 .ascii "short unsigned int\000" + 2074 7420756E + 2074 7369676E + 2074 65642069 + 2074 6E7400 + 2075 .LASF50: + 2076 01b0 49435352 .ascii "ICSR\000" + 2076 00 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 39 + + + 2077 .LASF16: + 2078 01b5 6D73675F .ascii "msg_t\000" + 2078 7400 + 2079 .LASF52: + 2080 01bb 41495243 .ascii "AIRCR\000" + 2080 5200 + 2081 .LASF57: + 2082 01c1 44465352 .ascii "DFSR\000" + 2082 00 + 2083 .LASF58: + 2084 01c6 4D4D4641 .ascii "MMFAR\000" + 2084 5200 + 2085 .LASF85: + 2086 01cc 5F706F72 .ascii "_port_irq_epilogue\000" + 2086 745F6972 + 2086 715F6570 + 2086 696C6F67 + 2086 756500 + 2087 .LASF12: + 2088 01df 746D6F64 .ascii "tmode_t\000" + 2088 655F7400 + 2089 .LASF40: + 2090 01e7 54687265 .ascii "ThreadsList\000" + 2090 6164734C + 2090 69737400 + 2091 .LASF17: + 2092 01f3 6576656E .ascii "eventmask_t\000" + 2092 746D6173 + 2092 6B5F7400 + 2093 .LASF73: + 2094 01ff 4D757465 .ascii "Mutex\000" + 2094 7800 + 2095 .LASF48: + 2096 0205 73697A65 .ascii "sizetype\000" + 2096 74797065 + 2096 00 + 2097 .LASF55: + 2098 020e 43465352 .ascii "CFSR\000" + 2098 00 + 2099 .LASF26: + 2100 0213 705F6F6C .ascii "p_older\000" + 2100 64657200 + 2101 .LASF93: + 2102 021b 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 2102 73657273 + 2102 5C496D61 + 2102 6E6F6C5C + 2102 64657665 + 2103 0248 6C696361 .ascii "lications\\smartcities\000" + 2103 74696F6E + 2103 735C736D + 2103 61727463 + 2103 69746965 + 2104 .LASF39: + 2105 025e 54687265 .ascii "ThreadsQueue\000" + 2105 61647351 + 2105 75657565 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 40 + + + 2105 00 + 2106 .LASF91: + 2107 026b 474E5520 .ascii "GNU C 4.7.2\000" + 2107 4320342E + 2107 372E3200 + 2108 .LASF71: + 2109 0277 725F6375 .ascii "r_current\000" + 2109 7272656E + 2109 7400 + 2110 .LASF69: + 2111 0281 725F6F6C .ascii "r_older\000" + 2111 64657200 + 2112 .LASF14: + 2113 0289 74726566 .ascii "trefs_t\000" + 2113 735F7400 + 2114 .LASF86: + 2115 0291 63747870 .ascii "ctxp\000" + 2115 00 + 2116 .LASF22: + 2117 0296 705F7072 .ascii "p_prev\000" + 2117 657600 + 2118 .LASF15: + 2119 029d 74707269 .ascii "tprio_t\000" + 2119 6F5F7400 + 2120 .LASF6: + 2121 02a5 696E7433 .ascii "int32_t\000" + 2121 325F7400 + 2122 .LASF2: + 2123 02ad 756E7369 .ascii "unsigned char\000" + 2123 676E6564 + 2123 20636861 + 2123 7200 + 2124 .LASF54: + 2125 02bb 53484353 .ascii "SHCSR\000" + 2125 5200 + 2126 .LASF36: + 2127 02c1 705F6D74 .ascii "p_mtxlist\000" + 2127 786C6973 + 2127 7400 + 2128 .LASF3: + 2129 02cb 73686F72 .ascii "short int\000" + 2129 7420696E + 2129 7400 + 2130 .LASF28: + 2131 02d5 705F7374 .ascii "p_state\000" + 2131 61746500 + 2132 .LASF44: + 2133 02dd 78707372 .ascii "xpsr\000" + 2133 00 + 2134 .LASF66: + 2135 02e2 725F7072 .ascii "r_prio\000" + 2135 696F00 + 2136 .LASF80: + 2137 02e9 65776D61 .ascii "ewmask\000" + 2137 736B00 + 2138 .LASF21: + 2139 02f0 705F6E65 .ascii "p_next\000" + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 41 + + + 2139 787400 + 2140 .LASF29: + 2141 02f7 705F666C .ascii "p_flags\000" + 2141 61677300 + 2142 .LASF20: + 2143 02ff 54687265 .ascii "Thread\000" + 2143 616400 + 2144 .LASF35: + 2145 0306 705F6570 .ascii "p_epending\000" + 2145 656E6469 + 2145 6E6700 + 2146 .LASF8: + 2147 0311 75696E74 .ascii "uint32_t\000" + 2147 33325F74 + 2147 00 + 2148 .LASF65: + 2149 031a 725F7175 .ascii "r_queue\000" + 2149 65756500 + 2150 .LASF60: + 2151 0322 41465352 .ascii "AFSR\000" + 2151 00 + 2152 .LASF62: + 2153 0327 756E7573 .ascii "unused1\000" + 2153 65643100 + 2154 .LASF81: + 2155 032f 63686172 .ascii "char\000" + 2155 00 + 2156 .LASF47: + 2157 0334 494F5245 .ascii "IOREG32\000" + 2157 47333200 + 2158 .LASF76: + 2159 033c 6D5F6E65 .ascii "m_next\000" + 2159 787400 + 2160 .LASF18: + 2161 0343 73797374 .ascii "systime_t\000" + 2161 696D655F + 2161 7400 + 2162 .LASF37: + 2163 034d 705F7265 .ascii "p_realprio\000" + 2163 616C7072 + 2163 696F00 + 2164 .LASF70: + 2165 0358 725F7072 .ascii "r_preempt\000" + 2165 65656D70 + 2165 7400 + 2166 .LASF31: + 2167 0362 705F7469 .ascii "p_time\000" + 2167 6D6500 + 2168 .LASF53: + 2169 0369 53485052 .ascii "SHPR\000" + 2169 00 + 2170 .LASF45: + 2171 036e 696E7463 .ascii "intctx\000" + 2171 747800 + 2172 .LASF33: + 2173 0375 705F6D73 .ascii "p_msgqueue\000" + 2173 67717565 + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 42 + + + 2173 756500 + 2174 .LASF30: + 2175 0380 705F7265 .ascii "p_refs\000" + 2175 667300 + 2176 .LASF72: + 2177 0387 52656164 .ascii "ReadyList\000" + 2177 794C6973 + 2177 7400 + 2178 .LASF61: + 2179 0391 4D4D4652 .ascii "MMFR\000" + 2179 00 + 2180 .LASF95: + 2181 0396 726C6973 .ascii "rlist\000" + 2181 7400 + 2182 .LASF5: + 2183 039c 75696E74 .ascii "uint8_t\000" + 2183 385F7400 + 2184 .LASF79: + 2185 03a4 77746F62 .ascii "wtobjp\000" + 2185 6A7000 + 2186 .LASF84: + 2187 03ab 5F706F72 .ascii "_port_init\000" + 2187 745F696E + 2187 697400 + 2188 .LASF27: + 2189 03b6 705F6E61 .ascii "p_name\000" + 2189 6D6500 + 2190 .LASF63: + 2191 03bd 43504143 .ascii "CPACR\000" + 2191 5200 + 2192 .LASF56: + 2193 03c3 48465352 .ascii "HFSR\000" + 2193 00 + 2194 .LASF75: + 2195 03c8 6D5F6F77 .ascii "m_owner\000" + 2195 6E657200 + 2196 .LASF24: + 2197 03d0 705F6374 .ascii "p_ctx\000" + 2197 7800 + 2198 .LASF32: + 2199 03d6 705F7761 .ascii "p_waiting\000" + 2199 6974696E + 2199 6700 + 2200 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\ccFrgcHf.s page 43 + + +DEFINED SYMBOLS + *ABS*:00000000 chcore_v7m.c +C:\cygwin\tmp\ccFrgcHf.s:19 .text._port_switch_from_isr:00000000 $t +C:\cygwin\tmp\ccFrgcHf.s:25 .text._port_switch_from_isr:00000000 _port_switch_from_isr +C:\cygwin\tmp\ccFrgcHf.s:38 .text._port_switch_from_isr:00000004 _port_exit_from_isr +C:\cygwin\tmp\ccFrgcHf.s:57 .text.PendSVVector:00000000 $t +C:\cygwin\tmp\ccFrgcHf.s:63 .text.PendSVVector:00000000 PendSVVector +C:\cygwin\tmp\ccFrgcHf.s:89 .text._port_init:00000000 $t +C:\cygwin\tmp\ccFrgcHf.s:95 .text._port_init:00000000 _port_init +C:\cygwin\tmp\ccFrgcHf.s:143 .text._port_irq_epilogue:00000000 $t +C:\cygwin\tmp\ccFrgcHf.s:149 .text._port_irq_epilogue:00000000 _port_irq_epilogue +C:\cygwin\tmp\ccFrgcHf.s:239 .text._port_irq_epilogue:00000064 $d +C:\cygwin\tmp\ccFrgcHf.s:247 .text.SysTickVector:00000000 $t +C:\cygwin\tmp\ccFrgcHf.s:253 .text.SysTickVector:00000000 SysTickVector +C:\cygwin\tmp\ccFrgcHf.s:286 .text._port_switch:00000000 $t +C:\cygwin\tmp\ccFrgcHf.s:292 .text._port_switch:00000000 _port_switch +C:\cygwin\tmp\ccFrgcHf.s:319 .text._port_thread_start:00000000 $t +C:\cygwin\tmp\ccFrgcHf.s:325 .text._port_thread_start:00000000 _port_thread_start + .debug_frame:00000010 $d + +UNDEFINED SYMBOLS +chSchDoReschedule +nvicSetSystemHandlerPriority +rlist +chSysTimerHandlerI +chThdExit diff --git a/Project/applications/smartcities/build/lst/chdebug.lst b/Project/applications/smartcities/build/lst/chdebug.lst new file mode 100644 index 0000000..84caa8c --- /dev/null +++ b/Project/applications/smartcities/build/lst/chdebug.lst @@ -0,0 +1,229 @@ +ARM GAS C:\cygwin\tmp\cccUL3eQ.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "chdebug.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .Letext0: + 19 .section .debug_info,"",%progbits + 20 .Ldebug_info0: + 21 0000 6E000000 .4byte 0x6e + 22 0004 0200 .2byte 0x2 + 23 0006 00000000 .4byte .Ldebug_abbrev0 + 24 000a 04 .byte 0x4 + 25 000b 01 .uleb128 0x1 + 26 000c 34000000 .4byte .LASF11 + 27 0010 01 .byte 0x1 + 28 0011 6F000000 .4byte .LASF12 + 29 0015 97000000 .4byte .LASF13 + 30 0019 00000000 .4byte .Ldebug_line0 + 31 001d 02 .uleb128 0x2 + 32 001e 04 .byte 0x4 + 33 001f 05 .byte 0x5 + 34 0020 696E7400 .ascii "int\000" + 35 0024 03 .uleb128 0x3 + 36 0025 04 .byte 0x4 + 37 0026 07 .byte 0x7 + 38 0027 00000000 .4byte .LASF0 + 39 002b 03 .uleb128 0x3 + 40 002c 01 .byte 0x1 + 41 002d 06 .byte 0x6 + 42 002e 28000000 .4byte .LASF1 + 43 0032 03 .uleb128 0x3 + 44 0033 01 .byte 0x1 + 45 0034 08 .byte 0x8 + 46 0035 61000000 .4byte .LASF2 + 47 0039 03 .uleb128 0x3 + 48 003a 02 .byte 0x2 + 49 003b 05 .byte 0x5 + 50 003c 40000000 .4byte .LASF3 + 51 0040 03 .uleb128 0x3 + 52 0041 02 .byte 0x2 + 53 0042 07 .byte 0x7 + 54 0043 DF000000 .4byte .LASF4 + 55 0047 03 .uleb128 0x3 + 56 0048 04 .byte 0x4 + 57 0049 05 .byte 0x5 + ARM GAS C:\cygwin\tmp\cccUL3eQ.s page 2 + + + 58 004a 1F000000 .4byte .LASF5 + 59 004e 03 .uleb128 0x3 + 60 004f 04 .byte 0x4 + 61 0050 07 .byte 0x7 + 62 0051 0D000000 .4byte .LASF6 + 63 0055 03 .uleb128 0x3 + 64 0056 08 .byte 0x8 + 65 0057 05 .byte 0x5 + 66 0058 F2000000 .4byte .LASF7 + 67 005c 03 .uleb128 0x3 + 68 005d 08 .byte 0x8 + 69 005e 07 .byte 0x7 + 70 005f 4A000000 .4byte .LASF8 + 71 0063 03 .uleb128 0x3 + 72 0064 04 .byte 0x4 + 73 0065 07 .byte 0x7 + 74 0066 8E000000 .4byte .LASF9 + 75 006a 03 .uleb128 0x3 + 76 006b 01 .byte 0x1 + 77 006c 08 .byte 0x8 + 78 006d DA000000 .4byte .LASF10 + 79 0071 00 .byte 0 + 80 .section .debug_abbrev,"",%progbits + 81 .Ldebug_abbrev0: + 82 0000 01 .uleb128 0x1 + 83 0001 11 .uleb128 0x11 + 84 0002 01 .byte 0x1 + 85 0003 25 .uleb128 0x25 + 86 0004 0E .uleb128 0xe + 87 0005 13 .uleb128 0x13 + 88 0006 0B .uleb128 0xb + 89 0007 03 .uleb128 0x3 + 90 0008 0E .uleb128 0xe + 91 0009 1B .uleb128 0x1b + 92 000a 0E .uleb128 0xe + 93 000b 10 .uleb128 0x10 + 94 000c 06 .uleb128 0x6 + 95 000d 00 .byte 0 + 96 000e 00 .byte 0 + 97 000f 02 .uleb128 0x2 + 98 0010 24 .uleb128 0x24 + 99 0011 00 .byte 0 + 100 0012 0B .uleb128 0xb + 101 0013 0B .uleb128 0xb + 102 0014 3E .uleb128 0x3e + 103 0015 0B .uleb128 0xb + 104 0016 03 .uleb128 0x3 + 105 0017 08 .uleb128 0x8 + 106 0018 00 .byte 0 + 107 0019 00 .byte 0 + 108 001a 03 .uleb128 0x3 + 109 001b 24 .uleb128 0x24 + 110 001c 00 .byte 0 + 111 001d 0B .uleb128 0xb + 112 001e 0B .uleb128 0xb + 113 001f 3E .uleb128 0x3e + 114 0020 0B .uleb128 0xb + ARM GAS C:\cygwin\tmp\cccUL3eQ.s page 3 + + + 115 0021 03 .uleb128 0x3 + 116 0022 0E .uleb128 0xe + 117 0023 00 .byte 0 + 118 0024 00 .byte 0 + 119 0025 00 .byte 0 + 120 .section .debug_aranges,"",%progbits + 121 0000 14000000 .4byte 0x14 + 122 0004 0200 .2byte 0x2 + 123 0006 00000000 .4byte .Ldebug_info0 + 124 000a 04 .byte 0x4 + 125 000b 00 .byte 0 + 126 000c 0000 .2byte 0 + 127 000e 0000 .2byte 0 + 128 0010 00000000 .4byte 0 + 129 0014 00000000 .4byte 0 + 130 .section .debug_line,"",%progbits + 131 .Ldebug_line0: + 132 0000 19000000 .section .debug_str,"MS",%progbits,1 + 132 02001300 + 132 00000201 + 132 FB0E0D00 + 132 01010101 + 133 .LASF0: + 134 0000 756E7369 .ascii "unsigned int\000" + 134 676E6564 + 134 20696E74 + 134 00 + 135 .LASF6: + 136 000d 6C6F6E67 .ascii "long unsigned int\000" + 136 20756E73 + 136 69676E65 + 136 6420696E + 136 7400 + 137 .LASF5: + 138 001f 6C6F6E67 .ascii "long int\000" + 138 20696E74 + 138 00 + 139 .LASF1: + 140 0028 7369676E .ascii "signed char\000" + 140 65642063 + 140 68617200 + 141 .LASF11: + 142 0034 474E5520 .ascii "GNU C 4.7.2\000" + 142 4320342E + 142 372E3200 + 143 .LASF3: + 144 0040 73686F72 .ascii "short int\000" + 144 7420696E + 144 7400 + 145 .LASF8: + 146 004a 6C6F6E67 .ascii "long long unsigned int\000" + 146 206C6F6E + 146 6720756E + 146 7369676E + 146 65642069 + 147 .LASF2: + 148 0061 756E7369 .ascii "unsigned char\000" + ARM GAS C:\cygwin\tmp\cccUL3eQ.s page 4 + + + 148 676E6564 + 148 20636861 + 148 7200 + 149 .LASF12: + 150 006f 2E2E2F2E .ascii "../..//os/kernel/src/chdebug.c\000" + 150 2E2F2F6F + 150 732F6B65 + 150 726E656C + 150 2F737263 + 151 .LASF9: + 152 008e 73697A65 .ascii "sizetype\000" + 152 74797065 + 152 00 + 153 .LASF13: + 154 0097 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 154 73657273 + 154 5C496D61 + 154 6E6F6C5C + 154 64657665 + 155 00c4 6C696361 .ascii "lications\\smartcities\000" + 155 74696F6E + 155 735C736D + 155 61727463 + 155 69746965 + 156 .LASF10: + 157 00da 63686172 .ascii "char\000" + 157 00 + 158 .LASF4: + 159 00df 73686F72 .ascii "short unsigned int\000" + 159 7420756E + 159 7369676E + 159 65642069 + 159 6E7400 + 160 .LASF7: + 161 00f2 6C6F6E67 .ascii "long long int\000" + 161 206C6F6E + 161 6720696E + 161 7400 + 162 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\cccUL3eQ.s page 5 + + +DEFINED SYMBOLS + *ABS*:00000000 chdebug.c + +NO UNDEFINED SYMBOLS diff --git a/Project/applications/smartcities/build/lst/chdynamic.lst b/Project/applications/smartcities/build/lst/chdynamic.lst new file mode 100644 index 0000000..9e86ddf --- /dev/null +++ b/Project/applications/smartcities/build/lst/chdynamic.lst @@ -0,0 +1,2700 @@ +ARM GAS C:\cygwin\tmp\ccztHEA0.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "chdynamic.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text.chThdAddRef,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .global chThdAddRef + 22 .thumb + 23 .thumb_func + 24 .type chThdAddRef, %function + 25 chThdAddRef: + 26 .LFB7: + 27 .file 1 "../..//os/kernel/src/chdynamic.c" + 28 .loc 1 52 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .LVL0: + 34 .loc 1 54 0 + 35 @ 54 "../..//os/kernel/src/chdynamic.c" 1 + 36 0000 72B6 cpsid i + 37 @ 0 "" 2 + 38 .loc 1 56 0 + 39 .thumb + 40 0002 827F ldrb r2, [r0, #30] @ zero_extendqisi2 + 41 0004 0132 adds r2, r2, #1 + 42 0006 8277 strb r2, [r0, #30] + 43 .loc 1 57 0 + 44 @ 57 "../..//os/kernel/src/chdynamic.c" 1 + 45 0008 62B6 cpsie i + 46 @ 0 "" 2 + 47 .loc 1 59 0 + 48 .thumb + 49 000a 7047 bx lr + 50 .cfi_endproc + 51 .LFE7: + 52 .size chThdAddRef, .-chThdAddRef + 53 000c AFF30080 .section .text.chThdRelease,"ax",%progbits + 54 .align 2 + 55 .p2align 4,,15 + 56 .global chThdRelease + 57 .thumb + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 2 + + + 58 .thumb_func + 59 .type chThdRelease, %function + 60 chThdRelease: + 61 .LFB8: + 62 .loc 1 74 0 + 63 .cfi_startproc + 64 @ args = 0, pretend = 0, frame = 0 + 65 @ frame_needed = 0, uses_anonymous_args = 0 + 66 @ link register save eliminated. + 67 .LVL1: + 68 .loc 1 74 0 + 69 0000 0146 mov r1, r0 + 70 .loc 1 77 0 + 71 @ 77 "../..//os/kernel/src/chdynamic.c" 1 + 72 0002 72B6 cpsid i + 73 @ 0 "" 2 + 74 .loc 1 79 0 + 75 .thumb + 76 0004 837F ldrb r3, [r0, #30] @ zero_extendqisi2 + 77 0006 013B subs r3, r3, #1 + 78 0008 DBB2 uxtb r3, r3 + 79 000a 8377 strb r3, [r0, #30] + 80 .LVL2: + 81 .loc 1 80 0 + 82 @ 80 "../..//os/kernel/src/chdynamic.c" 1 + 83 000c 62B6 cpsie i + 84 @ 0 "" 2 + 85 .loc 1 85 0 + 86 .thumb + 87 000e 13B9 cbnz r3, .L2 + 88 .loc 1 85 0 is_stmt 0 discriminator 1 + 89 0010 037F ldrb r3, [r0, #28] @ zero_extendqisi2 + 90 .LVL3: + 91 0012 0E2B cmp r3, #14 + 92 0014 00D0 beq .L7 + 93 .L2: + 94 0016 7047 bx lr + 95 .L7: + 96 .loc 1 86 0 is_stmt 1 + 97 0018 437F ldrb r3, [r0, #29] @ zero_extendqisi2 + 98 001a 03F00303 and r3, r3, #3 + 99 001e 012B cmp r3, #1 + 100 0020 09D0 beq .L4 + 101 0022 022B cmp r3, #2 + 102 0024 F7D1 bne .L2 + 103 .loc 1 98 0 + 104 0026 4369 ldr r3, [r0, #20] + 105 0028 0269 ldr r2, [r0, #16] + 106 .loc 1 100 0 + 107 002a 406C ldr r0, [r0, #68] + 108 .LVL4: + 109 .loc 1 98 0 + 110 002c 1A61 str r2, [r3, #16] + 111 002e 0A69 ldr r2, [r1, #16] + 112 0030 5361 str r3, [r2, #20] + 113 .loc 1 105 0 + 114 .loc 1 100 0 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 3 + + + 115 0032 FFF7FEBF b chPoolFree + 116 .LVL5: + 117 .L4: + 118 .loc 1 90 0 + 119 0036 4369 ldr r3, [r0, #20] + 120 0038 0269 ldr r2, [r0, #16] + 121 003a 1A61 str r2, [r3, #16] + 122 003c 0269 ldr r2, [r0, #16] + 123 003e 5361 str r3, [r2, #20] + 124 .loc 1 105 0 + 125 .loc 1 92 0 + 126 0040 FFF7FEBF b chHeapFree + 127 .LVL6: + 128 .cfi_endproc + 129 .LFE8: + 130 .size chThdRelease, .-chThdRelease + 131 0044 AFF30080 .section .text.chThdCreateFromHeap,"ax",%progbits + 131 AFF30080 + 131 AFF30080 + 132 .align 2 + 133 .p2align 4,,15 + 134 .global chThdCreateFromHeap + 135 .thumb + 136 .thumb_func + 137 .type chThdCreateFromHeap, %function + 138 chThdCreateFromHeap: + 139 .LFB9: + 140 .loc 1 131 0 + 141 .cfi_startproc + 142 @ args = 4, pretend = 0, frame = 0 + 143 @ frame_needed = 0, uses_anonymous_args = 0 + 144 .LVL7: + 145 0000 F0B5 push {r4, r5, r6, r7, lr} + 146 .LCFI0: + 147 .cfi_def_cfa_offset 20 + 148 .cfi_offset 4, -20 + 149 .cfi_offset 5, -16 + 150 .cfi_offset 6, -12 + 151 .cfi_offset 7, -8 + 152 .cfi_offset 14, -4 + 153 0002 83B0 sub sp, sp, #12 + 154 .LCFI1: + 155 .cfi_def_cfa_offset 32 + 156 .loc 1 131 0 + 157 0004 0D46 mov r5, r1 + 158 0006 1746 mov r7, r2 + 159 0008 1E46 mov r6, r3 + 160 .loc 1 135 0 + 161 000a FFF7FEFF bl chHeapAlloc + 162 .LVL8: + 163 .loc 1 136 0 + 164 000e 0446 mov r4, r0 + 165 0010 70B1 cbz r0, .L9 + 166 .loc 1 148 0 + 167 @ 148 "../..//os/kernel/src/chdynamic.c" 1 + 168 0012 72B6 cpsid i + 169 @ 0 "" 2 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 4 + + + 170 .loc 1 149 0 + 171 .thumb + 172 0014 089C ldr r4, [sp, #32] + 173 0016 2946 mov r1, r5 + 174 0018 3A46 mov r2, r7 + 175 001a 3346 mov r3, r6 + 176 001c 0094 str r4, [sp, #0] + 177 001e FFF7FEFF bl chThdCreateI + 178 .LVL9: + 179 .loc 1 150 0 + 180 0022 0123 movs r3, #1 + 181 0024 4377 strb r3, [r0, #29] + 182 .loc 1 151 0 + 183 0026 0021 movs r1, #0 + 184 .loc 1 149 0 + 185 0028 0446 mov r4, r0 + 186 .LVL10: + 187 .loc 1 151 0 + 188 002a FFF7FEFF bl chSchWakeupS + 189 .LVL11: + 190 .loc 1 152 0 + 191 @ 152 "../..//os/kernel/src/chdynamic.c" 1 + 192 002e 62B6 cpsie i + 193 @ 0 "" 2 + 194 .LVL12: + 195 .thumb + 196 .L9: + 197 .loc 1 154 0 + 198 0030 2046 mov r0, r4 + 199 0032 03B0 add sp, sp, #12 + 200 0034 F0BD pop {r4, r5, r6, r7, pc} + 201 .cfi_endproc + 202 .LFE9: + 203 .size chThdCreateFromHeap, .-chThdCreateFromHeap + 204 0036 00BFAFF3 .section .text.chThdCreateFromMemoryPool,"ax",%progbits + 204 0080AFF3 + 204 0080 + 205 .align 2 + 206 .p2align 4,,15 + 207 .global chThdCreateFromMemoryPool + 208 .thumb + 209 .thumb_func + 210 .type chThdCreateFromMemoryPool, %function + 211 chThdCreateFromMemoryPool: + 212 .LFB10: + 213 .loc 1 180 0 + 214 .cfi_startproc + 215 @ args = 0, pretend = 0, frame = 0 + 216 @ frame_needed = 0, uses_anonymous_args = 0 + 217 .LVL13: + 218 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 219 .LCFI2: + 220 .cfi_def_cfa_offset 24 + 221 .cfi_offset 4, -24 + 222 .cfi_offset 5, -20 + 223 .cfi_offset 6, -16 + 224 .cfi_offset 7, -12 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 5 + + + 225 .cfi_offset 8, -8 + 226 .cfi_offset 14, -4 + 227 0004 82B0 sub sp, sp, #8 + 228 .LCFI3: + 229 .cfi_def_cfa_offset 32 + 230 .loc 1 180 0 + 231 0006 0546 mov r5, r0 + 232 0008 8846 mov r8, r1 + 233 000a 1746 mov r7, r2 + 234 000c 1E46 mov r6, r3 + 235 .loc 1 186 0 + 236 000e FFF7FEFF bl chPoolAlloc + 237 .LVL14: + 238 .loc 1 187 0 + 239 0012 0446 mov r4, r0 + 240 0014 70B1 cbz r0, .L12 + 241 .loc 1 199 0 + 242 @ 199 "../..//os/kernel/src/chdynamic.c" 1 + 243 0016 72B6 cpsid i + 244 @ 0 "" 2 + 245 .loc 1 200 0 + 246 .thumb + 247 0018 6968 ldr r1, [r5, #4] + 248 001a 4246 mov r2, r8 + 249 001c 3B46 mov r3, r7 + 250 001e 0096 str r6, [sp, #0] + 251 0020 FFF7FEFF bl chThdCreateI + 252 .LVL15: + 253 .loc 1 201 0 + 254 0024 0223 movs r3, #2 + 255 0026 4377 strb r3, [r0, #29] + 256 .loc 1 202 0 + 257 0028 4564 str r5, [r0, #68] + 258 .loc 1 203 0 + 259 002a 0021 movs r1, #0 + 260 .loc 1 200 0 + 261 002c 0446 mov r4, r0 + 262 .LVL16: + 263 .loc 1 203 0 + 264 002e FFF7FEFF bl chSchWakeupS + 265 .LVL17: + 266 .loc 1 204 0 + 267 @ 204 "../..//os/kernel/src/chdynamic.c" 1 + 268 0032 62B6 cpsie i + 269 @ 0 "" 2 + 270 .LVL18: + 271 .thumb + 272 .L12: + 273 .loc 1 206 0 + 274 0034 2046 mov r0, r4 + 275 0036 02B0 add sp, sp, #8 + 276 0038 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 277 .cfi_endproc + 278 .LFE10: + 279 .size chThdCreateFromMemoryPool, .-chThdCreateFromMemoryPool + 280 003c AFF30080 .text + 281 .Letext0: + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 6 + + + 282 .file 2 "c:\\yagarto\\bin\\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h" + 283 .file 3 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 284 .file 4 "../..//os/ports/GCC/ARMCMx/chtypes.h" + 285 .file 5 "../..//os/kernel/include/chlists.h" + 286 .file 6 "../..//os/kernel/include/chthreads.h" + 287 .file 7 "../..//os/ports/GCC/ARMCMx/chcore_v7m.h" + 288 .file 8 "../..//os/kernel/include/chmtx.h" + 289 .file 9 "../..//os/kernel/include/chmemcore.h" + 290 .file 10 "../..//os/kernel/include/chheap.h" + 291 .file 11 "../..//os/kernel/include/chmempools.h" + 292 .file 12 "../..//os/kernel/include/chschd.h" + 293 .section .debug_info,"",%progbits + 294 .Ldebug_info0: + 295 0000 FA070000 .4byte 0x7fa + 296 0004 0200 .2byte 0x2 + 297 0006 00000000 .4byte .Ldebug_abbrev0 + 298 000a 04 .byte 0x4 + 299 000b 01 .uleb128 0x1 + 300 000c 3C020000 .4byte .LASF85 + 301 0010 01 .byte 0x1 + 302 0011 6E010000 .4byte .LASF86 + 303 0015 DD010000 .4byte .LASF87 + 304 0019 00000000 .4byte .Ldebug_ranges0+0 + 305 001d 00000000 .4byte 0 + 306 0021 00000000 .4byte 0 + 307 0025 00000000 .4byte .Ldebug_line0 + 308 0029 02 .uleb128 0x2 + 309 002a 04 .byte 0x4 + 310 002b 05 .byte 0x5 + 311 002c 696E7400 .ascii "int\000" + 312 0030 03 .uleb128 0x3 + 313 0031 0E000000 .4byte .LASF2 + 314 0035 02 .byte 0x2 + 315 0036 D5 .byte 0xd5 + 316 0037 3B000000 .4byte 0x3b + 317 003b 04 .uleb128 0x4 + 318 003c 04 .byte 0x4 + 319 003d 07 .byte 0x7 + 320 003e 29010000 .4byte .LASF0 + 321 0042 04 .uleb128 0x4 + 322 0043 01 .byte 0x1 + 323 0044 06 .byte 0x6 + 324 0045 84000000 .4byte .LASF1 + 325 0049 03 .uleb128 0x3 + 326 004a 6E030000 .4byte .LASF3 + 327 004e 03 .byte 0x3 + 328 004f 2A .byte 0x2a + 329 0050 54000000 .4byte 0x54 + 330 0054 04 .uleb128 0x4 + 331 0055 01 .byte 0x1 + 332 0056 08 .byte 0x8 + 333 0057 84020000 .4byte .LASF4 + 334 005b 04 .uleb128 0x4 + 335 005c 02 .byte 0x2 + 336 005d 05 .byte 0x5 + 337 005e A7020000 .4byte .LASF5 + 338 0062 04 .uleb128 0x4 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 7 + + + 339 0063 02 .byte 0x2 + 340 0064 07 .byte 0x7 + 341 0065 55010000 .4byte .LASF6 + 342 0069 03 .uleb128 0x3 + 343 006a 7C020000 .4byte .LASF7 + 344 006e 03 .byte 0x3 + 345 006f 4F .byte 0x4f + 346 0070 74000000 .4byte 0x74 + 347 0074 04 .uleb128 0x4 + 348 0075 04 .byte 0x4 + 349 0076 05 .byte 0x5 + 350 0077 BE000000 .4byte .LASF8 + 351 007b 03 .uleb128 0x3 + 352 007c 06030000 .4byte .LASF9 + 353 0080 03 .byte 0x3 + 354 0081 50 .byte 0x50 + 355 0082 86000000 .4byte 0x86 + 356 0086 04 .uleb128 0x4 + 357 0087 04 .byte 0x4 + 358 0088 07 .byte 0x7 + 359 0089 36010000 .4byte .LASF10 + 360 008d 04 .uleb128 0x4 + 361 008e 08 .byte 0x8 + 362 008f 05 .byte 0x5 + 363 0090 76000000 .4byte .LASF11 + 364 0094 03 .uleb128 0x3 + 365 0095 1C000000 .4byte .LASF12 + 366 0099 03 .byte 0x3 + 367 009a 78 .byte 0x78 + 368 009b 9F000000 .4byte 0x9f + 369 009f 04 .uleb128 0x4 + 370 00a0 08 .byte 0x8 + 371 00a1 07 .byte 0x7 + 372 00a2 3D000000 .4byte .LASF13 + 373 00a6 03 .uleb128 0x3 + 374 00a7 8F010000 .4byte .LASF14 + 375 00ab 04 .byte 0x4 + 376 00ac 2F .byte 0x2f + 377 00ad 49000000 .4byte 0x49 + 378 00b1 03 .uleb128 0x3 + 379 00b2 DB000000 .4byte .LASF15 + 380 00b6 04 .byte 0x4 + 381 00b7 30 .byte 0x30 + 382 00b8 49000000 .4byte 0x49 + 383 00bc 03 .uleb128 0x3 + 384 00bd 60020000 .4byte .LASF16 + 385 00c1 04 .byte 0x4 + 386 00c2 31 .byte 0x31 + 387 00c3 49000000 .4byte 0x49 + 388 00c7 03 .uleb128 0x3 + 389 00c8 74020000 .4byte .LASF17 + 390 00cc 04 .byte 0x4 + 391 00cd 32 .byte 0x32 + 392 00ce 7B000000 .4byte 0x7b + 393 00d2 03 .uleb128 0x3 + 394 00d3 68010000 .4byte .LASF18 + 395 00d7 04 .byte 0x4 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 8 + + + 396 00d8 33 .byte 0x33 + 397 00d9 69000000 .4byte 0x69 + 398 00dd 03 .uleb128 0x3 + 399 00de A3010000 .4byte .LASF19 + 400 00e2 04 .byte 0x4 + 401 00e3 35 .byte 0x35 + 402 00e4 7B000000 .4byte 0x7b + 403 00e8 03 .uleb128 0x3 + 404 00e9 20030000 .4byte .LASF20 + 405 00ed 04 .byte 0x4 + 406 00ee 36 .byte 0x36 + 407 00ef 7B000000 .4byte 0x7b + 408 00f3 03 .uleb128 0x3 + 409 00f4 E8020000 .4byte .LASF21 + 410 00f8 05 .byte 0x5 + 411 00f9 2A .byte 0x2a + 412 00fa FE000000 .4byte 0xfe + 413 00fe 05 .uleb128 0x5 + 414 00ff E8020000 .4byte .LASF21 + 415 0103 48 .byte 0x48 + 416 0104 06 .byte 0x6 + 417 0105 5E .byte 0x5e + 418 0106 15020000 .4byte 0x215 + 419 010a 06 .uleb128 0x6 + 420 010b CC020000 .4byte .LASF22 + 421 010f 06 .byte 0x6 + 422 0110 5F .byte 0x5f + 423 0111 3A020000 .4byte 0x23a + 424 0115 02 .byte 0x2 + 425 0116 23 .byte 0x23 + 426 0117 00 .uleb128 0 + 427 0118 06 .uleb128 0x6 + 428 0119 6D020000 .4byte .LASF23 + 429 011d 06 .byte 0x6 + 430 011e 61 .byte 0x61 + 431 011f 3A020000 .4byte 0x23a + 432 0123 02 .byte 0x2 + 433 0124 23 .byte 0x23 + 434 0125 04 .uleb128 0x4 + 435 0126 06 .uleb128 0x6 + 436 0127 6F000000 .4byte .LASF24 + 437 012b 06 .byte 0x6 + 438 012c 63 .byte 0x63 + 439 012d C7000000 .4byte 0xc7 + 440 0131 02 .byte 0x2 + 441 0132 23 .byte 0x23 + 442 0133 08 .uleb128 0x8 + 443 0134 06 .uleb128 0x6 + 444 0135 A3030000 .4byte .LASF25 + 445 0139 06 .byte 0x6 + 446 013a 64 .byte 0x64 + 447 013b 12030000 .4byte 0x312 + 448 013f 02 .byte 0x2 + 449 0140 23 .byte 0x23 + 450 0141 0C .uleb128 0xc + 451 0142 06 .uleb128 0x6 + 452 0143 EC000000 .4byte .LASF26 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 9 + + + 453 0147 06 .byte 0x6 + 454 0148 66 .byte 0x66 + 455 0149 3A020000 .4byte 0x23a + 456 014d 02 .byte 0x2 + 457 014e 23 .byte 0x23 + 458 014f 10 .uleb128 0x10 + 459 0150 06 .uleb128 0x6 + 460 0151 D5010000 .4byte .LASF27 + 461 0155 06 .byte 0x6 + 462 0156 67 .byte 0x67 + 463 0157 3A020000 .4byte 0x23a + 464 015b 02 .byte 0x2 + 465 015c 23 .byte 0x23 + 466 015d 14 .uleb128 0x14 + 467 015e 06 .uleb128 0x6 + 468 015f 94030000 .4byte .LASF28 + 469 0163 06 .byte 0x6 + 470 0164 6E .byte 0x6e + 471 0165 EF040000 .4byte 0x4ef + 472 0169 02 .byte 0x2 + 473 016a 23 .byte 0x23 + 474 016b 18 .uleb128 0x18 + 475 016c 06 .uleb128 0x6 + 476 016d B1020000 .4byte .LASF29 + 477 0171 06 .byte 0x6 + 478 0172 79 .byte 0x79 + 479 0173 B1000000 .4byte 0xb1 + 480 0177 02 .byte 0x2 + 481 0178 23 .byte 0x23 + 482 0179 1C .uleb128 0x1c + 483 017a 06 .uleb128 0x6 + 484 017b D3020000 .4byte .LASF30 + 485 017f 06 .byte 0x6 + 486 0180 7D .byte 0x7d + 487 0181 A6000000 .4byte 0xa6 + 488 0185 02 .byte 0x2 + 489 0186 23 .byte 0x23 + 490 0187 1D .uleb128 0x1d + 491 0188 06 .uleb128 0x6 + 492 0189 67030000 .4byte .LASF31 + 493 018d 06 .byte 0x6 + 494 018e 82 .byte 0x82 + 495 018f BC000000 .4byte 0xbc + 496 0193 02 .byte 0x2 + 497 0194 23 .byte 0x23 + 498 0195 1E .uleb128 0x1e + 499 0196 06 .uleb128 0x6 + 500 0197 35030000 .4byte .LASF32 + 501 019b 06 .byte 0x6 + 502 019c 89 .byte 0x89 + 503 019d 3C030000 .4byte 0x33c + 504 01a1 02 .byte 0x2 + 505 01a2 23 .byte 0x23 + 506 01a3 20 .uleb128 0x20 + 507 01a4 07 .uleb128 0x7 + 508 01a5 705F7500 .ascii "p_u\000" + 509 01a9 06 .byte 0x6 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 10 + + + 510 01aa AE .byte 0xae + 511 01ab BA040000 .4byte 0x4ba + 512 01af 02 .byte 0x2 + 513 01b0 23 .byte 0x23 + 514 01b1 24 .uleb128 0x24 + 515 01b2 06 .uleb128 0x6 + 516 01b3 A9030000 .4byte .LASF33 + 517 01b7 06 .byte 0x6 + 518 01b8 B3 .byte 0xb3 + 519 01b9 62020000 .4byte 0x262 + 520 01bd 02 .byte 0x2 + 521 01be 23 .byte 0x23 + 522 01bf 28 .uleb128 0x28 + 523 01c0 06 .uleb128 0x6 + 524 01c1 43030000 .4byte .LASF34 + 525 01c5 06 .byte 0x6 + 526 01c6 B9 .byte 0xb9 + 527 01c7 40020000 .4byte 0x240 + 528 01cb 02 .byte 0x2 + 529 01cc 23 .byte 0x23 + 530 01cd 2C .uleb128 0x2c + 531 01ce 06 .uleb128 0x6 + 532 01cf 08000000 .4byte .LASF35 + 533 01d3 06 .byte 0x6 + 534 01d4 BD .byte 0xbd + 535 01d5 D2000000 .4byte 0xd2 + 536 01d9 02 .byte 0x2 + 537 01da 23 .byte 0x23 + 538 01db 34 .uleb128 0x34 + 539 01dc 06 .uleb128 0x6 + 540 01dd FB020000 .4byte .LASF36 + 541 01e1 06 .byte 0x6 + 542 01e2 C3 .byte 0xc3 + 543 01e3 DD000000 .4byte 0xdd + 544 01e7 02 .byte 0x2 + 545 01e8 23 .byte 0x23 + 546 01e9 38 .uleb128 0x38 + 547 01ea 06 .uleb128 0x6 + 548 01eb 9D020000 .4byte .LASF37 + 549 01ef 06 .byte 0x6 + 550 01f0 CA .byte 0xca + 551 01f1 01050000 .4byte 0x501 + 552 01f5 02 .byte 0x2 + 553 01f6 23 .byte 0x23 + 554 01f7 3C .uleb128 0x3c + 555 01f8 06 .uleb128 0x6 + 556 01f9 2A030000 .4byte .LASF38 + 557 01fd 06 .byte 0x6 + 558 01fe CE .byte 0xce + 559 01ff C7000000 .4byte 0xc7 + 560 0203 02 .byte 0x2 + 561 0204 23 .byte 0x23 + 562 0205 40 .uleb128 0x40 + 563 0206 06 .uleb128 0x6 + 564 0207 96000000 .4byte .LASF39 + 565 020b 06 .byte 0x6 + 566 020c D4 .byte 0xd4 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 11 + + + 567 020d 78020000 .4byte 0x278 + 568 0211 02 .byte 0x2 + 569 0212 23 .byte 0x23 + 570 0213 44 .uleb128 0x44 + 571 0214 00 .byte 0 + 572 0215 08 .uleb128 0x8 + 573 0216 08 .byte 0x8 + 574 0217 05 .byte 0x5 + 575 0218 61 .byte 0x61 + 576 0219 3A020000 .4byte 0x23a + 577 021d 06 .uleb128 0x6 + 578 021e CC020000 .4byte .LASF22 + 579 0222 05 .byte 0x5 + 580 0223 62 .byte 0x62 + 581 0224 3A020000 .4byte 0x23a + 582 0228 02 .byte 0x2 + 583 0229 23 .byte 0x23 + 584 022a 00 .uleb128 0 + 585 022b 06 .uleb128 0x6 + 586 022c 6D020000 .4byte .LASF23 + 587 0230 05 .byte 0x5 + 588 0231 64 .byte 0x64 + 589 0232 3A020000 .4byte 0x23a + 590 0236 02 .byte 0x2 + 591 0237 23 .byte 0x23 + 592 0238 04 .uleb128 0x4 + 593 0239 00 .byte 0 + 594 023a 09 .uleb128 0x9 + 595 023b 04 .byte 0x4 + 596 023c F3000000 .4byte 0xf3 + 597 0240 03 .uleb128 0x3 + 598 0241 20020000 .4byte .LASF40 + 599 0245 05 .byte 0x5 + 600 0246 66 .byte 0x66 + 601 0247 15020000 .4byte 0x215 + 602 024b 08 .uleb128 0x8 + 603 024c 04 .byte 0x4 + 604 024d 05 .byte 0x5 + 605 024e 6B .byte 0x6b + 606 024f 62020000 .4byte 0x262 + 607 0253 06 .uleb128 0x6 + 608 0254 CC020000 .4byte .LASF22 + 609 0258 05 .byte 0x5 + 610 0259 6D .byte 0x6d + 611 025a 3A020000 .4byte 0x23a + 612 025e 02 .byte 0x2 + 613 025f 23 .byte 0x23 + 614 0260 00 .uleb128 0 + 615 0261 00 .byte 0 + 616 0262 03 .uleb128 0x3 + 617 0263 97010000 .4byte .LASF41 + 618 0267 05 .byte 0x5 + 619 0268 70 .byte 0x70 + 620 0269 4B020000 .4byte 0x24b + 621 026d 03 .uleb128 0x3 + 622 026e 1A010000 .4byte .LASF42 + 623 0272 07 .byte 0x7 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 12 + + + 624 0273 D7 .byte 0xd7 + 625 0274 78020000 .4byte 0x278 + 626 0278 0A .uleb128 0xa + 627 0279 04 .byte 0x4 + 628 027a 03 .uleb128 0x3 + 629 027b C1010000 .4byte .LASF43 + 630 027f 07 .byte 0x7 + 631 0280 DD .byte 0xdd + 632 0281 94000000 .4byte 0x94 + 633 0285 05 .uleb128 0x5 + 634 0286 3C030000 .4byte .LASF44 + 635 028a 24 .byte 0x24 + 636 028b 07 .byte 0x7 + 637 028c FE .byte 0xfe + 638 028d 12030000 .4byte 0x312 + 639 0291 0B .uleb128 0xb + 640 0292 723400 .ascii "r4\000" + 641 0295 07 .byte 0x7 + 642 0296 1101 .2byte 0x111 + 643 0298 6D020000 .4byte 0x26d + 644 029c 02 .byte 0x2 + 645 029d 23 .byte 0x23 + 646 029e 00 .uleb128 0 + 647 029f 0B .uleb128 0xb + 648 02a0 723500 .ascii "r5\000" + 649 02a3 07 .byte 0x7 + 650 02a4 1201 .2byte 0x112 + 651 02a6 6D020000 .4byte 0x26d + 652 02aa 02 .byte 0x2 + 653 02ab 23 .byte 0x23 + 654 02ac 04 .uleb128 0x4 + 655 02ad 0B .uleb128 0xb + 656 02ae 723600 .ascii "r6\000" + 657 02b1 07 .byte 0x7 + 658 02b2 1301 .2byte 0x113 + 659 02b4 6D020000 .4byte 0x26d + 660 02b8 02 .byte 0x2 + 661 02b9 23 .byte 0x23 + 662 02ba 08 .uleb128 0x8 + 663 02bb 0B .uleb128 0xb + 664 02bc 723700 .ascii "r7\000" + 665 02bf 07 .byte 0x7 + 666 02c0 1401 .2byte 0x114 + 667 02c2 6D020000 .4byte 0x26d + 668 02c6 02 .byte 0x2 + 669 02c7 23 .byte 0x23 + 670 02c8 0C .uleb128 0xc + 671 02c9 0B .uleb128 0xb + 672 02ca 723800 .ascii "r8\000" + 673 02cd 07 .byte 0x7 + 674 02ce 1501 .2byte 0x115 + 675 02d0 6D020000 .4byte 0x26d + 676 02d4 02 .byte 0x2 + 677 02d5 23 .byte 0x23 + 678 02d6 10 .uleb128 0x10 + 679 02d7 0B .uleb128 0xb + 680 02d8 723900 .ascii "r9\000" + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 13 + + + 681 02db 07 .byte 0x7 + 682 02dc 1601 .2byte 0x116 + 683 02de 6D020000 .4byte 0x26d + 684 02e2 02 .byte 0x2 + 685 02e3 23 .byte 0x23 + 686 02e4 14 .uleb128 0x14 + 687 02e5 0B .uleb128 0xb + 688 02e6 72313000 .ascii "r10\000" + 689 02ea 07 .byte 0x7 + 690 02eb 1701 .2byte 0x117 + 691 02ed 6D020000 .4byte 0x26d + 692 02f1 02 .byte 0x2 + 693 02f2 23 .byte 0x23 + 694 02f3 18 .uleb128 0x18 + 695 02f4 0B .uleb128 0xb + 696 02f5 72313100 .ascii "r11\000" + 697 02f9 07 .byte 0x7 + 698 02fa 1801 .2byte 0x118 + 699 02fc 6D020000 .4byte 0x26d + 700 0300 02 .byte 0x2 + 701 0301 23 .byte 0x23 + 702 0302 1C .uleb128 0x1c + 703 0303 0B .uleb128 0xb + 704 0304 6C7200 .ascii "lr\000" + 705 0307 07 .byte 0x7 + 706 0308 1901 .2byte 0x119 + 707 030a 6D020000 .4byte 0x26d + 708 030e 02 .byte 0x2 + 709 030f 23 .byte 0x23 + 710 0310 20 .uleb128 0x20 + 711 0311 00 .byte 0 + 712 0312 0C .uleb128 0xc + 713 0313 48010000 .4byte .LASF45 + 714 0317 04 .byte 0x4 + 715 0318 07 .byte 0x7 + 716 0319 2301 .2byte 0x123 + 717 031b 2F030000 .4byte 0x32f + 718 031f 0B .uleb128 0xb + 719 0320 72313300 .ascii "r13\000" + 720 0324 07 .byte 0x7 + 721 0325 2401 .2byte 0x124 + 722 0327 2F030000 .4byte 0x32f + 723 032b 02 .byte 0x2 + 724 032c 23 .byte 0x23 + 725 032d 00 .uleb128 0 + 726 032e 00 .byte 0 + 727 032f 09 .uleb128 0x9 + 728 0330 04 .byte 0x4 + 729 0331 85020000 .4byte 0x285 + 730 0335 04 .uleb128 0x4 + 731 0336 04 .byte 0x4 + 732 0337 07 .byte 0x7 + 733 0338 CC010000 .4byte .LASF46 + 734 033c 0D .uleb128 0xd + 735 033d E8000000 .4byte 0xe8 + 736 0341 05 .uleb128 0x5 + 737 0342 AF010000 .4byte .LASF47 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 14 + + + 738 0346 10 .byte 0x10 + 739 0347 08 .byte 0x8 + 740 0348 2C .byte 0x2c + 741 0349 78030000 .4byte 0x378 + 742 034d 06 .uleb128 0x6 + 743 034e 9E000000 .4byte .LASF48 + 744 0352 08 .byte 0x8 + 745 0353 2D .byte 0x2d + 746 0354 40020000 .4byte 0x240 + 747 0358 02 .byte 0x2 + 748 0359 23 .byte 0x23 + 749 035a 00 .uleb128 0 + 750 035b 06 .uleb128 0x6 + 751 035c 9B030000 .4byte .LASF49 + 752 0360 08 .byte 0x8 + 753 0361 2F .byte 0x2f + 754 0362 3A020000 .4byte 0x23a + 755 0366 02 .byte 0x2 + 756 0367 23 .byte 0x23 + 757 0368 08 .uleb128 0x8 + 758 0369 06 .uleb128 0x6 + 759 036a 19030000 .4byte .LASF50 + 760 036e 08 .byte 0x8 + 761 036f 31 .byte 0x31 + 762 0370 78030000 .4byte 0x378 + 763 0374 02 .byte 0x2 + 764 0375 23 .byte 0x23 + 765 0376 0C .uleb128 0xc + 766 0377 00 .byte 0 + 767 0378 09 .uleb128 0x9 + 768 0379 04 .byte 0x4 + 769 037a 41030000 .4byte 0x341 + 770 037e 03 .uleb128 0x3 + 771 037f AF010000 .4byte .LASF47 + 772 0383 08 .byte 0x8 + 773 0384 33 .byte 0x33 + 774 0385 41030000 .4byte 0x341 + 775 0389 03 .uleb128 0x3 + 776 038a 30000000 .4byte .LASF51 + 777 038e 09 .byte 0x9 + 778 038f 2C .byte 0x2c + 779 0390 94030000 .4byte 0x394 + 780 0394 09 .uleb128 0x9 + 781 0395 04 .byte 0x4 + 782 0396 9A030000 .4byte 0x39a + 783 039a 0E .uleb128 0xe + 784 039b 01 .byte 0x1 + 785 039c 78020000 .4byte 0x278 + 786 03a0 AA030000 .4byte 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1231 06f9 B6 .byte 0xb6 + 1232 06fa 3A020000 .4byte 0x23a + 1233 06fe 2E020000 .4byte .LLST15 + 1234 0702 20 .uleb128 0x20 + 1235 0703 12000000 .4byte .LVL14 + 1236 0707 E9070000 .4byte 0x7e9 + 1237 070b 16070000 .4byte 0x716 + 1238 070f 1B .uleb128 0x1b + 1239 0710 01 .byte 0x1 + 1240 0711 50 .byte 0x50 + 1241 0712 02 .byte 0x2 + 1242 0713 75 .byte 0x75 + 1243 0714 00 .sleb128 0 + 1244 0715 00 .byte 0 + 1245 0716 20 .uleb128 0x20 + 1246 0717 24000000 .4byte .LVL15 + 1247 071b A3070000 .4byte 0x7a3 + 1248 071f 3D070000 .4byte 0x73d + 1249 0723 1B .uleb128 0x1b + 1250 0724 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 23 + + + 1251 0725 53 .byte 0x53 + 1252 0726 02 .byte 0x2 + 1253 0727 77 .byte 0x77 + 1254 0728 00 .sleb128 0 + 1255 0729 1B .uleb128 0x1b + 1256 072a 01 .byte 0x1 + 1257 072b 52 .byte 0x52 + 1258 072c 02 .byte 0x2 + 1259 072d 78 .byte 0x78 + 1260 072e 00 .sleb128 0 + 1261 072f 1B .uleb128 0x1b + 1262 0730 01 .byte 0x1 + 1263 0731 50 .byte 0x50 + 1264 0732 02 .byte 0x2 + 1265 0733 74 .byte 0x74 + 1266 0734 00 .sleb128 0 + 1267 0735 1B .uleb128 0x1b + 1268 0736 02 .byte 0x2 + 1269 0737 7D .byte 0x7d + 1270 0738 00 .sleb128 0 + 1271 0739 02 .byte 0x2 + 1272 073a 76 .byte 0x76 + 1273 073b 00 .sleb128 0 + 1274 073c 00 .byte 0 + 1275 073d 21 .uleb128 0x21 + 1276 073e 32000000 .4byte .LVL17 + 1277 0742 D0070000 .4byte 0x7d0 + 1278 0746 1B .uleb128 0x1b + 1279 0747 01 .byte 0x1 + 1280 0748 51 .byte 0x51 + 1281 0749 01 .byte 0x1 + 1282 074a 30 .byte 0x30 + 1283 074b 1B .uleb128 0x1b + 1284 074c 01 .byte 0x1 + 1285 074d 50 .byte 0x50 + 1286 074e 02 .byte 0x2 + 1287 074f 74 .byte 0x74 + 1288 0750 00 .sleb128 0 + 1289 0751 00 .byte 0 + 1290 0752 00 .byte 0 + 1291 0753 09 .uleb128 0x9 + 1292 0754 04 .byte 0x4 + 1293 0755 AF040000 .4byte 0x4af + 1294 0759 22 .uleb128 0x22 + 1295 075a 01 .byte 0x1 + 1296 075b 82030000 .4byte .LASF79 + 1297 075f 0B .byte 0xb + 1298 0760 5C .byte 0x5c + 1299 0761 01 .byte 0x1 + 1300 0762 01 .byte 0x1 + 1301 0763 72070000 .4byte 0x772 + 1302 0767 0F .uleb128 0xf + 1303 0768 53070000 .4byte 0x753 + 1304 076c 0F .uleb128 0xf + 1305 076d 78020000 .4byte 0x278 + 1306 0771 00 .byte 0 + 1307 0772 22 .uleb128 0x22 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 24 + + + 1308 0773 01 .byte 0x1 + 1309 0774 A6000000 .4byte .LASF80 + 1310 0778 0A .byte 0xa + 1311 0779 5A .byte 0x5a + 1312 077a 01 .byte 0x1 + 1313 077b 01 .byte 0x1 + 1314 077c 86070000 .4byte 0x786 + 1315 0780 0F .uleb128 0xf + 1316 0781 78020000 .4byte 0x278 + 1317 0785 00 .byte 0 + 1318 0786 23 .uleb128 0x23 + 1319 0787 01 .byte 0x1 + 1320 0788 EF020000 .4byte .LASF81 + 1321 078c 0A .byte 0xa + 1322 078d 59 .byte 0x59 + 1323 078e 01 .byte 0x1 + 1324 078f 78020000 .4byte 0x278 + 1325 0793 01 .byte 0x1 + 1326 0794 A3070000 .4byte 0x7a3 + 1327 0798 0F .uleb128 0xf + 1328 0799 32040000 .4byte 0x432 + 1329 079d 0F .uleb128 0xf + 1330 079e 30000000 .4byte 0x30 + 1331 07a2 00 .byte 0 + 1332 07a3 24 .uleb128 0x24 + 1333 07a4 01 .byte 0x1 + 1334 07a5 B1000000 .4byte .LASF82 + 1335 07a9 06 .byte 0x6 + 1336 07aa 6201 .2byte 0x162 + 1337 07ac 01 .byte 0x1 + 1338 07ad 3A020000 .4byte 0x23a + 1339 07b1 01 .byte 0x1 + 1340 07b2 D0070000 .4byte 0x7d0 + 1341 07b6 0F .uleb128 0xf + 1342 07b7 78020000 .4byte 0x278 + 1343 07bb 0F .uleb128 0xf + 1344 07bc 30000000 .4byte 0x30 + 1345 07c0 0F .uleb128 0xf + 1346 07c1 C7000000 .4byte 0xc7 + 1347 07c5 0F .uleb128 0xf + 1348 07c6 07050000 .4byte 0x507 + 1349 07ca 0F .uleb128 0xf + 1350 07cb 78020000 .4byte 0x278 + 1351 07cf 00 .byte 0 + 1352 07d0 22 .uleb128 0x22 + 1353 07d1 01 .byte 0x1 + 1354 07d2 4E030000 .4byte .LASF83 + 1355 07d6 0C .byte 0xc + 1356 07d7 9C .byte 0x9c + 1357 07d8 01 .byte 0x1 + 1358 07d9 01 .byte 0x1 + 1359 07da E9070000 .4byte 0x7e9 + 1360 07de 0F .uleb128 0xf + 1361 07df 3A020000 .4byte 0x23a + 1362 07e3 0F .uleb128 0xf + 1363 07e4 D2000000 .4byte 0xd2 + 1364 07e8 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 25 + + + 1365 07e9 25 .uleb128 0x25 + 1366 07ea 01 .byte 0x1 + 1367 07eb 76030000 .4byte .LASF84 + 1368 07ef 0B .byte 0xb + 1369 07f0 5A .byte 0x5a + 1370 07f1 01 .byte 0x1 + 1371 07f2 78020000 .4byte 0x278 + 1372 07f6 01 .byte 0x1 + 1373 07f7 0F .uleb128 0xf + 1374 07f8 53070000 .4byte 0x753 + 1375 07fc 00 .byte 0 + 1376 07fd 00 .byte 0 + 1377 .section .debug_abbrev,"",%progbits + 1378 .Ldebug_abbrev0: + 1379 0000 01 .uleb128 0x1 + 1380 0001 11 .uleb128 0x11 + 1381 0002 01 .byte 0x1 + 1382 0003 25 .uleb128 0x25 + 1383 0004 0E .uleb128 0xe + 1384 0005 13 .uleb128 0x13 + 1385 0006 0B .uleb128 0xb + 1386 0007 03 .uleb128 0x3 + 1387 0008 0E .uleb128 0xe + 1388 0009 1B .uleb128 0x1b + 1389 000a 0E .uleb128 0xe + 1390 000b 55 .uleb128 0x55 + 1391 000c 06 .uleb128 0x6 + 1392 000d 11 .uleb128 0x11 + 1393 000e 01 .uleb128 0x1 + 1394 000f 52 .uleb128 0x52 + 1395 0010 01 .uleb128 0x1 + 1396 0011 10 .uleb128 0x10 + 1397 0012 06 .uleb128 0x6 + 1398 0013 00 .byte 0 + 1399 0014 00 .byte 0 + 1400 0015 02 .uleb128 0x2 + 1401 0016 24 .uleb128 0x24 + 1402 0017 00 .byte 0 + 1403 0018 0B .uleb128 0xb + 1404 0019 0B .uleb128 0xb + 1405 001a 3E .uleb128 0x3e + 1406 001b 0B .uleb128 0xb + 1407 001c 03 .uleb128 0x3 + 1408 001d 08 .uleb128 0x8 + 1409 001e 00 .byte 0 + 1410 001f 00 .byte 0 + 1411 0020 03 .uleb128 0x3 + 1412 0021 16 .uleb128 0x16 + 1413 0022 00 .byte 0 + 1414 0023 03 .uleb128 0x3 + 1415 0024 0E .uleb128 0xe + 1416 0025 3A .uleb128 0x3a + 1417 0026 0B .uleb128 0xb + 1418 0027 3B .uleb128 0x3b + 1419 0028 0B .uleb128 0xb + 1420 0029 49 .uleb128 0x49 + 1421 002a 13 .uleb128 0x13 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 26 + + + 1422 002b 00 .byte 0 + 1423 002c 00 .byte 0 + 1424 002d 04 .uleb128 0x4 + 1425 002e 24 .uleb128 0x24 + 1426 002f 00 .byte 0 + 1427 0030 0B .uleb128 0xb + 1428 0031 0B .uleb128 0xb + 1429 0032 3E .uleb128 0x3e + 1430 0033 0B .uleb128 0xb + 1431 0034 03 .uleb128 0x3 + 1432 0035 0E .uleb128 0xe + 1433 0036 00 .byte 0 + 1434 0037 00 .byte 0 + 1435 0038 05 .uleb128 0x5 + 1436 0039 13 .uleb128 0x13 + 1437 003a 01 .byte 0x1 + 1438 003b 03 .uleb128 0x3 + 1439 003c 0E .uleb128 0xe + 1440 003d 0B .uleb128 0xb + 1441 003e 0B .uleb128 0xb + 1442 003f 3A .uleb128 0x3a + 1443 0040 0B .uleb128 0xb + 1444 0041 3B .uleb128 0x3b + 1445 0042 0B .uleb128 0xb + 1446 0043 01 .uleb128 0x1 + 1447 0044 13 .uleb128 0x13 + 1448 0045 00 .byte 0 + 1449 0046 00 .byte 0 + 1450 0047 06 .uleb128 0x6 + 1451 0048 0D .uleb128 0xd + 1452 0049 00 .byte 0 + 1453 004a 03 .uleb128 0x3 + 1454 004b 0E .uleb128 0xe + 1455 004c 3A .uleb128 0x3a + 1456 004d 0B .uleb128 0xb + 1457 004e 3B .uleb128 0x3b + 1458 004f 0B .uleb128 0xb + 1459 0050 49 .uleb128 0x49 + 1460 0051 13 .uleb128 0x13 + 1461 0052 38 .uleb128 0x38 + 1462 0053 0A .uleb128 0xa + 1463 0054 00 .byte 0 + 1464 0055 00 .byte 0 + 1465 0056 07 .uleb128 0x7 + 1466 0057 0D .uleb128 0xd + 1467 0058 00 .byte 0 + 1468 0059 03 .uleb128 0x3 + 1469 005a 08 .uleb128 0x8 + 1470 005b 3A .uleb128 0x3a + 1471 005c 0B .uleb128 0xb + 1472 005d 3B .uleb128 0x3b + 1473 005e 0B .uleb128 0xb + 1474 005f 49 .uleb128 0x49 + 1475 0060 13 .uleb128 0x13 + 1476 0061 38 .uleb128 0x38 + 1477 0062 0A .uleb128 0xa + 1478 0063 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 27 + + + 1479 0064 00 .byte 0 + 1480 0065 08 .uleb128 0x8 + 1481 0066 13 .uleb128 0x13 + 1482 0067 01 .byte 0x1 + 1483 0068 0B .uleb128 0xb + 1484 0069 0B .uleb128 0xb + 1485 006a 3A .uleb128 0x3a + 1486 006b 0B .uleb128 0xb + 1487 006c 3B .uleb128 0x3b + 1488 006d 0B .uleb128 0xb + 1489 006e 01 .uleb128 0x1 + 1490 006f 13 .uleb128 0x13 + 1491 0070 00 .byte 0 + 1492 0071 00 .byte 0 + 1493 0072 09 .uleb128 0x9 + 1494 0073 0F .uleb128 0xf + 1495 0074 00 .byte 0 + 1496 0075 0B .uleb128 0xb + 1497 0076 0B .uleb128 0xb + 1498 0077 49 .uleb128 0x49 + 1499 0078 13 .uleb128 0x13 + 1500 0079 00 .byte 0 + 1501 007a 00 .byte 0 + 1502 007b 0A .uleb128 0xa + 1503 007c 0F .uleb128 0xf + 1504 007d 00 .byte 0 + 1505 007e 0B .uleb128 0xb + 1506 007f 0B .uleb128 0xb + 1507 0080 00 .byte 0 + 1508 0081 00 .byte 0 + 1509 0082 0B .uleb128 0xb + 1510 0083 0D .uleb128 0xd + 1511 0084 00 .byte 0 + 1512 0085 03 .uleb128 0x3 + 1513 0086 08 .uleb128 0x8 + 1514 0087 3A .uleb128 0x3a + 1515 0088 0B .uleb128 0xb + 1516 0089 3B .uleb128 0x3b + 1517 008a 05 .uleb128 0x5 + 1518 008b 49 .uleb128 0x49 + 1519 008c 13 .uleb128 0x13 + 1520 008d 38 .uleb128 0x38 + 1521 008e 0A .uleb128 0xa + 1522 008f 00 .byte 0 + 1523 0090 00 .byte 0 + 1524 0091 0C .uleb128 0xc + 1525 0092 13 .uleb128 0x13 + 1526 0093 01 .byte 0x1 + 1527 0094 03 .uleb128 0x3 + 1528 0095 0E .uleb128 0xe + 1529 0096 0B .uleb128 0xb + 1530 0097 0B .uleb128 0xb + 1531 0098 3A .uleb128 0x3a + 1532 0099 0B .uleb128 0xb + 1533 009a 3B .uleb128 0x3b + 1534 009b 05 .uleb128 0x5 + 1535 009c 01 .uleb128 0x1 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 28 + + + 1536 009d 13 .uleb128 0x13 + 1537 009e 00 .byte 0 + 1538 009f 00 .byte 0 + 1539 00a0 0D .uleb128 0xd + 1540 00a1 35 .uleb128 0x35 + 1541 00a2 00 .byte 0 + 1542 00a3 49 .uleb128 0x49 + 1543 00a4 13 .uleb128 0x13 + 1544 00a5 00 .byte 0 + 1545 00a6 00 .byte 0 + 1546 00a7 0E .uleb128 0xe + 1547 00a8 15 .uleb128 0x15 + 1548 00a9 01 .byte 0x1 + 1549 00aa 27 .uleb128 0x27 + 1550 00ab 0C .uleb128 0xc + 1551 00ac 49 .uleb128 0x49 + 1552 00ad 13 .uleb128 0x13 + 1553 00ae 01 .uleb128 0x1 + 1554 00af 13 .uleb128 0x13 + 1555 00b0 00 .byte 0 + 1556 00b1 00 .byte 0 + 1557 00b2 0F .uleb128 0xf + 1558 00b3 05 .uleb128 0x5 + 1559 00b4 00 .byte 0 + 1560 00b5 49 .uleb128 0x49 + 1561 00b6 13 .uleb128 0x13 + 1562 00b7 00 .byte 0 + 1563 00b8 00 .byte 0 + 1564 00b9 10 .uleb128 0x10 + 1565 00ba 17 .uleb128 0x17 + 1566 00bb 01 .byte 0x1 + 1567 00bc 0B .uleb128 0xb + 1568 00bd 0B .uleb128 0xb + 1569 00be 3A .uleb128 0x3a + 1570 00bf 0B .uleb128 0xb + 1571 00c0 3B .uleb128 0x3b + 1572 00c1 0B .uleb128 0xb + 1573 00c2 01 .uleb128 0x1 + 1574 00c3 13 .uleb128 0x13 + 1575 00c4 00 .byte 0 + 1576 00c5 00 .byte 0 + 1577 00c6 11 .uleb128 0x11 + 1578 00c7 0D .uleb128 0xd + 1579 00c8 00 .byte 0 + 1580 00c9 03 .uleb128 0x3 + 1581 00ca 0E .uleb128 0xe + 1582 00cb 3A .uleb128 0x3a + 1583 00cc 0B .uleb128 0xb + 1584 00cd 3B .uleb128 0x3b + 1585 00ce 0B .uleb128 0xb + 1586 00cf 49 .uleb128 0x49 + 1587 00d0 13 .uleb128 0x13 + 1588 00d1 00 .byte 0 + 1589 00d2 00 .byte 0 + 1590 00d3 12 .uleb128 0x12 + 1591 00d4 17 .uleb128 0x17 + 1592 00d5 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 29 + + + 1593 00d6 03 .uleb128 0x3 + 1594 00d7 0E .uleb128 0xe + 1595 00d8 0B .uleb128 0xb + 1596 00d9 0B .uleb128 0xb + 1597 00da 3A .uleb128 0x3a + 1598 00db 0B .uleb128 0xb + 1599 00dc 3B .uleb128 0x3b + 1600 00dd 0B .uleb128 0xb + 1601 00de 01 .uleb128 0x1 + 1602 00df 13 .uleb128 0x13 + 1603 00e0 00 .byte 0 + 1604 00e1 00 .byte 0 + 1605 00e2 13 .uleb128 0x13 + 1606 00e3 0D .uleb128 0xd + 1607 00e4 00 .byte 0 + 1608 00e5 03 .uleb128 0x3 + 1609 00e6 08 .uleb128 0x8 + 1610 00e7 3A .uleb128 0x3a + 1611 00e8 0B .uleb128 0xb + 1612 00e9 3B .uleb128 0x3b + 1613 00ea 0B .uleb128 0xb + 1614 00eb 49 .uleb128 0x49 + 1615 00ec 13 .uleb128 0x13 + 1616 00ed 00 .byte 0 + 1617 00ee 00 .byte 0 + 1618 00ef 14 .uleb128 0x14 + 1619 00f0 26 .uleb128 0x26 + 1620 00f1 00 .byte 0 + 1621 00f2 49 .uleb128 0x49 + 1622 00f3 13 .uleb128 0x13 + 1623 00f4 00 .byte 0 + 1624 00f5 00 .byte 0 + 1625 00f6 15 .uleb128 0x15 + 1626 00f7 2E .uleb128 0x2e + 1627 00f8 01 .byte 0x1 + 1628 00f9 3F .uleb128 0x3f + 1629 00fa 0C .uleb128 0xc + 1630 00fb 03 .uleb128 0x3 + 1631 00fc 0E .uleb128 0xe + 1632 00fd 3A .uleb128 0x3a + 1633 00fe 0B .uleb128 0xb + 1634 00ff 3B .uleb128 0x3b + 1635 0100 0B .uleb128 0xb + 1636 0101 27 .uleb128 0x27 + 1637 0102 0C .uleb128 0xc + 1638 0103 49 .uleb128 0x49 + 1639 0104 13 .uleb128 0x13 + 1640 0105 11 .uleb128 0x11 + 1641 0106 01 .uleb128 0x1 + 1642 0107 12 .uleb128 0x12 + 1643 0108 01 .uleb128 0x1 + 1644 0109 40 .uleb128 0x40 + 1645 010a 0A .uleb128 0xa + 1646 010b 9742 .uleb128 0x2117 + 1647 010d 0C .uleb128 0xc + 1648 010e 01 .uleb128 0x1 + 1649 010f 13 .uleb128 0x13 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 30 + + + 1650 0110 00 .byte 0 + 1651 0111 00 .byte 0 + 1652 0112 16 .uleb128 0x16 + 1653 0113 05 .uleb128 0x5 + 1654 0114 00 .byte 0 + 1655 0115 03 .uleb128 0x3 + 1656 0116 08 .uleb128 0x8 + 1657 0117 3A .uleb128 0x3a + 1658 0118 0B .uleb128 0xb + 1659 0119 3B .uleb128 0x3b + 1660 011a 0B .uleb128 0xb + 1661 011b 49 .uleb128 0x49 + 1662 011c 13 .uleb128 0x13 + 1663 011d 02 .uleb128 0x2 + 1664 011e 0A .uleb128 0xa + 1665 011f 00 .byte 0 + 1666 0120 00 .byte 0 + 1667 0121 17 .uleb128 0x17 + 1668 0122 2E .uleb128 0x2e + 1669 0123 01 .byte 0x1 + 1670 0124 3F .uleb128 0x3f + 1671 0125 0C .uleb128 0xc + 1672 0126 03 .uleb128 0x3 + 1673 0127 0E .uleb128 0xe + 1674 0128 3A .uleb128 0x3a + 1675 0129 0B .uleb128 0xb + 1676 012a 3B .uleb128 0x3b + 1677 012b 0B .uleb128 0xb + 1678 012c 27 .uleb128 0x27 + 1679 012d 0C .uleb128 0xc + 1680 012e 11 .uleb128 0x11 + 1681 012f 01 .uleb128 0x1 + 1682 0130 12 .uleb128 0x12 + 1683 0131 01 .uleb128 0x1 + 1684 0132 40 .uleb128 0x40 + 1685 0133 0A .uleb128 0xa + 1686 0134 9742 .uleb128 0x2117 + 1687 0136 0C .uleb128 0xc + 1688 0137 01 .uleb128 0x1 + 1689 0138 13 .uleb128 0x13 + 1690 0139 00 .byte 0 + 1691 013a 00 .byte 0 + 1692 013b 18 .uleb128 0x18 + 1693 013c 05 .uleb128 0x5 + 1694 013d 00 .byte 0 + 1695 013e 03 .uleb128 0x3 + 1696 013f 08 .uleb128 0x8 + 1697 0140 3A .uleb128 0x3a + 1698 0141 0B .uleb128 0xb + 1699 0142 3B .uleb128 0x3b + 1700 0143 0B .uleb128 0xb + 1701 0144 49 .uleb128 0x49 + 1702 0145 13 .uleb128 0x13 + 1703 0146 02 .uleb128 0x2 + 1704 0147 06 .uleb128 0x6 + 1705 0148 00 .byte 0 + 1706 0149 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 31 + + + 1707 014a 19 .uleb128 0x19 + 1708 014b 34 .uleb128 0x34 + 1709 014c 00 .byte 0 + 1710 014d 03 .uleb128 0x3 + 1711 014e 0E .uleb128 0xe + 1712 014f 3A .uleb128 0x3a + 1713 0150 0B .uleb128 0xb + 1714 0151 3B .uleb128 0x3b + 1715 0152 0B .uleb128 0xb + 1716 0153 49 .uleb128 0x49 + 1717 0154 13 .uleb128 0x13 + 1718 0155 02 .uleb128 0x2 + 1719 0156 06 .uleb128 0x6 + 1720 0157 00 .byte 0 + 1721 0158 00 .byte 0 + 1722 0159 1A .uleb128 0x1a + 1723 015a 898201 .uleb128 0x4109 + 1724 015d 01 .byte 0x1 + 1725 015e 11 .uleb128 0x11 + 1726 015f 01 .uleb128 0x1 + 1727 0160 9542 .uleb128 0x2115 + 1728 0162 0C .uleb128 0xc + 1729 0163 31 .uleb128 0x31 + 1730 0164 13 .uleb128 0x13 + 1731 0165 01 .uleb128 0x1 + 1732 0166 13 .uleb128 0x13 + 1733 0167 00 .byte 0 + 1734 0168 00 .byte 0 + 1735 0169 1B .uleb128 0x1b + 1736 016a 8A8201 .uleb128 0x410a + 1737 016d 00 .byte 0 + 1738 016e 02 .uleb128 0x2 + 1739 016f 0A .uleb128 0xa + 1740 0170 9142 .uleb128 0x2111 + 1741 0172 0A .uleb128 0xa + 1742 0173 00 .byte 0 + 1743 0174 00 .byte 0 + 1744 0175 1C .uleb128 0x1c + 1745 0176 898201 .uleb128 0x4109 + 1746 0179 01 .byte 0x1 + 1747 017a 11 .uleb128 0x11 + 1748 017b 01 .uleb128 0x1 + 1749 017c 9542 .uleb128 0x2115 + 1750 017e 0C .uleb128 0xc + 1751 017f 31 .uleb128 0x31 + 1752 0180 13 .uleb128 0x13 + 1753 0181 00 .byte 0 + 1754 0182 00 .byte 0 + 1755 0183 1D .uleb128 0x1d + 1756 0184 2E .uleb128 0x2e + 1757 0185 01 .byte 0x1 + 1758 0186 3F .uleb128 0x3f + 1759 0187 0C .uleb128 0xc + 1760 0188 03 .uleb128 0x3 + 1761 0189 0E .uleb128 0xe + 1762 018a 3A .uleb128 0x3a + 1763 018b 0B .uleb128 0xb + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 32 + + + 1764 018c 3B .uleb128 0x3b + 1765 018d 0B .uleb128 0xb + 1766 018e 27 .uleb128 0x27 + 1767 018f 0C .uleb128 0xc + 1768 0190 49 .uleb128 0x49 + 1769 0191 13 .uleb128 0x13 + 1770 0192 11 .uleb128 0x11 + 1771 0193 01 .uleb128 0x1 + 1772 0194 12 .uleb128 0x12 + 1773 0195 01 .uleb128 0x1 + 1774 0196 40 .uleb128 0x40 + 1775 0197 06 .uleb128 0x6 + 1776 0198 9742 .uleb128 0x2117 + 1777 019a 0C .uleb128 0xc + 1778 019b 01 .uleb128 0x1 + 1779 019c 13 .uleb128 0x13 + 1780 019d 00 .byte 0 + 1781 019e 00 .byte 0 + 1782 019f 1E .uleb128 0x1e + 1783 01a0 05 .uleb128 0x5 + 1784 01a1 00 .byte 0 + 1785 01a2 03 .uleb128 0x3 + 1786 01a3 0E .uleb128 0xe + 1787 01a4 3A .uleb128 0x3a + 1788 01a5 0B .uleb128 0xb + 1789 01a6 3B .uleb128 0x3b + 1790 01a7 0B .uleb128 0xb + 1791 01a8 49 .uleb128 0x49 + 1792 01a9 13 .uleb128 0x13 + 1793 01aa 02 .uleb128 0x2 + 1794 01ab 06 .uleb128 0x6 + 1795 01ac 00 .byte 0 + 1796 01ad 00 .byte 0 + 1797 01ae 1F .uleb128 0x1f + 1798 01af 34 .uleb128 0x34 + 1799 01b0 00 .byte 0 + 1800 01b1 03 .uleb128 0x3 + 1801 01b2 08 .uleb128 0x8 + 1802 01b3 3A .uleb128 0x3a + 1803 01b4 0B .uleb128 0xb + 1804 01b5 3B .uleb128 0x3b + 1805 01b6 0B .uleb128 0xb + 1806 01b7 49 .uleb128 0x49 + 1807 01b8 13 .uleb128 0x13 + 1808 01b9 02 .uleb128 0x2 + 1809 01ba 06 .uleb128 0x6 + 1810 01bb 00 .byte 0 + 1811 01bc 00 .byte 0 + 1812 01bd 20 .uleb128 0x20 + 1813 01be 898201 .uleb128 0x4109 + 1814 01c1 01 .byte 0x1 + 1815 01c2 11 .uleb128 0x11 + 1816 01c3 01 .uleb128 0x1 + 1817 01c4 31 .uleb128 0x31 + 1818 01c5 13 .uleb128 0x13 + 1819 01c6 01 .uleb128 0x1 + 1820 01c7 13 .uleb128 0x13 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 33 + + + 1821 01c8 00 .byte 0 + 1822 01c9 00 .byte 0 + 1823 01ca 21 .uleb128 0x21 + 1824 01cb 898201 .uleb128 0x4109 + 1825 01ce 01 .byte 0x1 + 1826 01cf 11 .uleb128 0x11 + 1827 01d0 01 .uleb128 0x1 + 1828 01d1 31 .uleb128 0x31 + 1829 01d2 13 .uleb128 0x13 + 1830 01d3 00 .byte 0 + 1831 01d4 00 .byte 0 + 1832 01d5 22 .uleb128 0x22 + 1833 01d6 2E .uleb128 0x2e + 1834 01d7 01 .byte 0x1 + 1835 01d8 3F .uleb128 0x3f + 1836 01d9 0C .uleb128 0xc + 1837 01da 03 .uleb128 0x3 + 1838 01db 0E .uleb128 0xe + 1839 01dc 3A .uleb128 0x3a + 1840 01dd 0B .uleb128 0xb + 1841 01de 3B .uleb128 0x3b + 1842 01df 0B .uleb128 0xb + 1843 01e0 27 .uleb128 0x27 + 1844 01e1 0C .uleb128 0xc + 1845 01e2 3C .uleb128 0x3c + 1846 01e3 0C .uleb128 0xc + 1847 01e4 01 .uleb128 0x1 + 1848 01e5 13 .uleb128 0x13 + 1849 01e6 00 .byte 0 + 1850 01e7 00 .byte 0 + 1851 01e8 23 .uleb128 0x23 + 1852 01e9 2E .uleb128 0x2e + 1853 01ea 01 .byte 0x1 + 1854 01eb 3F .uleb128 0x3f + 1855 01ec 0C .uleb128 0xc + 1856 01ed 03 .uleb128 0x3 + 1857 01ee 0E .uleb128 0xe + 1858 01ef 3A .uleb128 0x3a + 1859 01f0 0B .uleb128 0xb + 1860 01f1 3B .uleb128 0x3b + 1861 01f2 0B .uleb128 0xb + 1862 01f3 27 .uleb128 0x27 + 1863 01f4 0C .uleb128 0xc + 1864 01f5 49 .uleb128 0x49 + 1865 01f6 13 .uleb128 0x13 + 1866 01f7 3C .uleb128 0x3c + 1867 01f8 0C .uleb128 0xc + 1868 01f9 01 .uleb128 0x1 + 1869 01fa 13 .uleb128 0x13 + 1870 01fb 00 .byte 0 + 1871 01fc 00 .byte 0 + 1872 01fd 24 .uleb128 0x24 + 1873 01fe 2E .uleb128 0x2e + 1874 01ff 01 .byte 0x1 + 1875 0200 3F .uleb128 0x3f + 1876 0201 0C .uleb128 0xc + 1877 0202 03 .uleb128 0x3 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 34 + + + 1878 0203 0E .uleb128 0xe + 1879 0204 3A .uleb128 0x3a + 1880 0205 0B .uleb128 0xb + 1881 0206 3B .uleb128 0x3b + 1882 0207 05 .uleb128 0x5 + 1883 0208 27 .uleb128 0x27 + 1884 0209 0C .uleb128 0xc + 1885 020a 49 .uleb128 0x49 + 1886 020b 13 .uleb128 0x13 + 1887 020c 3C .uleb128 0x3c + 1888 020d 0C .uleb128 0xc + 1889 020e 01 .uleb128 0x1 + 1890 020f 13 .uleb128 0x13 + 1891 0210 00 .byte 0 + 1892 0211 00 .byte 0 + 1893 0212 25 .uleb128 0x25 + 1894 0213 2E .uleb128 0x2e + 1895 0214 01 .byte 0x1 + 1896 0215 3F .uleb128 0x3f + 1897 0216 0C .uleb128 0xc + 1898 0217 03 .uleb128 0x3 + 1899 0218 0E .uleb128 0xe + 1900 0219 3A .uleb128 0x3a + 1901 021a 0B .uleb128 0xb + 1902 021b 3B .uleb128 0x3b + 1903 021c 0B .uleb128 0xb + 1904 021d 27 .uleb128 0x27 + 1905 021e 0C .uleb128 0xc + 1906 021f 49 .uleb128 0x49 + 1907 0220 13 .uleb128 0x13 + 1908 0221 3C .uleb128 0x3c + 1909 0222 0C .uleb128 0xc + 1910 0223 00 .byte 0 + 1911 0224 00 .byte 0 + 1912 0225 00 .byte 0 + 1913 .section .debug_loc,"",%progbits + 1914 .Ldebug_loc0: + 1915 .LLST0: + 1916 0000 00000000 .4byte .LVL1 + 1917 0004 2C000000 .4byte .LVL4 + 1918 0008 0100 .2byte 0x1 + 1919 000a 50 .byte 0x50 + 1920 000b 2C000000 .4byte .LVL4 + 1921 000f 35000000 .4byte .LVL5-1 + 1922 0013 0100 .2byte 0x1 + 1923 0015 51 .byte 0x51 + 1924 0016 35000000 .4byte .LVL5-1 + 1925 001a 36000000 .4byte .LVL5 + 1926 001e 0400 .2byte 0x4 + 1927 0020 F3 .byte 0xf3 + 1928 0021 01 .uleb128 0x1 + 1929 0022 50 .byte 0x50 + 1930 0023 9F .byte 0x9f + 1931 0024 36000000 .4byte .LVL5 + 1932 0028 43000000 .4byte .LVL6-1 + 1933 002c 0100 .2byte 0x1 + 1934 002e 50 .byte 0x50 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 35 + + + 1935 002f 43000000 .4byte .LVL6-1 + 1936 0033 44000000 .4byte .LFE8 + 1937 0037 0400 .2byte 0x4 + 1938 0039 F3 .byte 0xf3 + 1939 003a 01 .uleb128 0x1 + 1940 003b 50 .byte 0x50 + 1941 003c 9F .byte 0x9f + 1942 003d 00000000 .4byte 0 + 1943 0041 00000000 .4byte 0 + 1944 .LLST1: + 1945 0045 0C000000 .4byte .LVL2 + 1946 0049 12000000 .4byte .LVL3 + 1947 004d 0100 .2byte 0x1 + 1948 004f 53 .byte 0x53 + 1949 0050 12000000 .4byte .LVL3 + 1950 0054 2C000000 .4byte .LVL4 + 1951 0058 0A00 .2byte 0xa + 1952 005a 70 .byte 0x70 + 1953 005b 1E .sleb128 30 + 1954 005c 94 .byte 0x94 + 1955 005d 01 .byte 0x1 + 1956 005e 08 .byte 0x8 + 1957 005f FF .byte 0xff + 1958 0060 1A .byte 0x1a + 1959 0061 31 .byte 0x31 + 1960 0062 1C .byte 0x1c + 1961 0063 9F .byte 0x9f + 1962 0064 2C000000 .4byte .LVL4 + 1963 0068 35000000 .4byte .LVL5-1 + 1964 006c 0A00 .2byte 0xa + 1965 006e 71 .byte 0x71 + 1966 006f 1E .sleb128 30 + 1967 0070 94 .byte 0x94 + 1968 0071 01 .byte 0x1 + 1969 0072 08 .byte 0x8 + 1970 0073 FF .byte 0xff + 1971 0074 1A .byte 0x1a + 1972 0075 31 .byte 0x31 + 1973 0076 1C .byte 0x1c + 1974 0077 9F .byte 0x9f + 1975 0078 36000000 .4byte .LVL5 + 1976 007c 43000000 .4byte .LVL6-1 + 1977 0080 0A00 .2byte 0xa + 1978 0082 70 .byte 0x70 + 1979 0083 1E .sleb128 30 + 1980 0084 94 .byte 0x94 + 1981 0085 01 .byte 0x1 + 1982 0086 08 .byte 0x8 + 1983 0087 FF .byte 0xff + 1984 0088 1A .byte 0x1a + 1985 0089 31 .byte 0x31 + 1986 008a 1C .byte 0x1c + 1987 008b 9F .byte 0x9f + 1988 008c 00000000 .4byte 0 + 1989 0090 00000000 .4byte 0 + 1990 .LLST2: + 1991 0094 00000000 .4byte .LFB9 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 36 + + + 1992 0098 02000000 .4byte .LCFI0 + 1993 009c 0200 .2byte 0x2 + 1994 009e 7D .byte 0x7d + 1995 009f 00 .sleb128 0 + 1996 00a0 02000000 .4byte .LCFI0 + 1997 00a4 04000000 .4byte .LCFI1 + 1998 00a8 0200 .2byte 0x2 + 1999 00aa 7D .byte 0x7d + 2000 00ab 14 .sleb128 20 + 2001 00ac 04000000 .4byte .LCFI1 + 2002 00b0 36000000 .4byte .LFE9 + 2003 00b4 0200 .2byte 0x2 + 2004 00b6 7D .byte 0x7d + 2005 00b7 20 .sleb128 32 + 2006 00b8 00000000 .4byte 0 + 2007 00bc 00000000 .4byte 0 + 2008 .LLST3: + 2009 00c0 00000000 .4byte .LVL7 + 2010 00c4 0D000000 .4byte .LVL8-1 + 2011 00c8 0100 .2byte 0x1 + 2012 00ca 50 .byte 0x50 + 2013 00cb 0D000000 .4byte .LVL8-1 + 2014 00cf 36000000 .4byte .LFE9 + 2015 00d3 0400 .2byte 0x4 + 2016 00d5 F3 .byte 0xf3 + 2017 00d6 01 .uleb128 0x1 + 2018 00d7 50 .byte 0x50 + 2019 00d8 9F .byte 0x9f + 2020 00d9 00000000 .4byte 0 + 2021 00dd 00000000 .4byte 0 + 2022 .LLST4: + 2023 00e1 00000000 .4byte .LVL7 + 2024 00e5 0D000000 .4byte .LVL8-1 + 2025 00e9 0100 .2byte 0x1 + 2026 00eb 51 .byte 0x51 + 2027 00ec 0D000000 .4byte .LVL8-1 + 2028 00f0 36000000 .4byte .LFE9 + 2029 00f4 0100 .2byte 0x1 + 2030 00f6 55 .byte 0x55 + 2031 00f7 00000000 .4byte 0 + 2032 00fb 00000000 .4byte 0 + 2033 .LLST5: + 2034 00ff 00000000 .4byte .LVL7 + 2035 0103 0D000000 .4byte .LVL8-1 + 2036 0107 0100 .2byte 0x1 + 2037 0109 52 .byte 0x52 + 2038 010a 0D000000 .4byte .LVL8-1 + 2039 010e 36000000 .4byte .LFE9 + 2040 0112 0100 .2byte 0x1 + 2041 0114 57 .byte 0x57 + 2042 0115 00000000 .4byte 0 + 2043 0119 00000000 .4byte 0 + 2044 .LLST6: + 2045 011d 00000000 .4byte .LVL7 + 2046 0121 0D000000 .4byte .LVL8-1 + 2047 0125 0100 .2byte 0x1 + 2048 0127 53 .byte 0x53 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 37 + + + 2049 0128 0D000000 .4byte .LVL8-1 + 2050 012c 36000000 .4byte .LFE9 + 2051 0130 0100 .2byte 0x1 + 2052 0132 56 .byte 0x56 + 2053 0133 00000000 .4byte 0 + 2054 0137 00000000 .4byte 0 + 2055 .LLST7: + 2056 013b 0E000000 .4byte .LVL8 + 2057 013f 21000000 .4byte .LVL9-1 + 2058 0143 0100 .2byte 0x1 + 2059 0145 50 .byte 0x50 + 2060 0146 00000000 .4byte 0 + 2061 014a 00000000 .4byte 0 + 2062 .LLST8: + 2063 014e 2A000000 .4byte .LVL10 + 2064 0152 2D000000 .4byte .LVL11-1 + 2065 0156 0100 .2byte 0x1 + 2066 0158 50 .byte 0x50 + 2067 0159 2D000000 .4byte .LVL11-1 + 2068 015d 30000000 .4byte .LVL12 + 2069 0161 0100 .2byte 0x1 + 2070 0163 54 .byte 0x54 + 2071 0164 00000000 .4byte 0 + 2072 0168 00000000 .4byte 0 + 2073 .LLST9: + 2074 016c 00000000 .4byte .LFB10 + 2075 0170 04000000 .4byte .LCFI2 + 2076 0174 0200 .2byte 0x2 + 2077 0176 7D .byte 0x7d + 2078 0177 00 .sleb128 0 + 2079 0178 04000000 .4byte .LCFI2 + 2080 017c 06000000 .4byte .LCFI3 + 2081 0180 0200 .2byte 0x2 + 2082 0182 7D .byte 0x7d + 2083 0183 18 .sleb128 24 + 2084 0184 06000000 .4byte .LCFI3 + 2085 0188 3C000000 .4byte .LFE10 + 2086 018c 0200 .2byte 0x2 + 2087 018e 7D .byte 0x7d + 2088 018f 20 .sleb128 32 + 2089 0190 00000000 .4byte 0 + 2090 0194 00000000 .4byte 0 + 2091 .LLST10: + 2092 0198 00000000 .4byte .LVL13 + 2093 019c 11000000 .4byte .LVL14-1 + 2094 01a0 0100 .2byte 0x1 + 2095 01a2 50 .byte 0x50 + 2096 01a3 11000000 .4byte .LVL14-1 + 2097 01a7 3C000000 .4byte .LFE10 + 2098 01ab 0100 .2byte 0x1 + 2099 01ad 55 .byte 0x55 + 2100 01ae 00000000 .4byte 0 + 2101 01b2 00000000 .4byte 0 + 2102 .LLST11: + 2103 01b6 00000000 .4byte .LVL13 + 2104 01ba 11000000 .4byte .LVL14-1 + 2105 01be 0100 .2byte 0x1 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 38 + + + 2106 01c0 51 .byte 0x51 + 2107 01c1 11000000 .4byte .LVL14-1 + 2108 01c5 3C000000 .4byte .LFE10 + 2109 01c9 0100 .2byte 0x1 + 2110 01cb 58 .byte 0x58 + 2111 01cc 00000000 .4byte 0 + 2112 01d0 00000000 .4byte 0 + 2113 .LLST12: + 2114 01d4 00000000 .4byte .LVL13 + 2115 01d8 11000000 .4byte .LVL14-1 + 2116 01dc 0100 .2byte 0x1 + 2117 01de 52 .byte 0x52 + 2118 01df 11000000 .4byte .LVL14-1 + 2119 01e3 3C000000 .4byte .LFE10 + 2120 01e7 0100 .2byte 0x1 + 2121 01e9 57 .byte 0x57 + 2122 01ea 00000000 .4byte 0 + 2123 01ee 00000000 .4byte 0 + 2124 .LLST13: + 2125 01f2 00000000 .4byte .LVL13 + 2126 01f6 11000000 .4byte .LVL14-1 + 2127 01fa 0100 .2byte 0x1 + 2128 01fc 53 .byte 0x53 + 2129 01fd 11000000 .4byte .LVL14-1 + 2130 0201 3C000000 .4byte .LFE10 + 2131 0205 0100 .2byte 0x1 + 2132 0207 56 .byte 0x56 + 2133 0208 00000000 .4byte 0 + 2134 020c 00000000 .4byte 0 + 2135 .LLST14: + 2136 0210 12000000 .4byte .LVL14 + 2137 0214 23000000 .4byte .LVL15-1 + 2138 0218 0100 .2byte 0x1 + 2139 021a 50 .byte 0x50 + 2140 021b 23000000 .4byte .LVL15-1 + 2141 021f 2E000000 .4byte .LVL16 + 2142 0223 0100 .2byte 0x1 + 2143 0225 54 .byte 0x54 + 2144 0226 00000000 .4byte 0 + 2145 022a 00000000 .4byte 0 + 2146 .LLST15: + 2147 022e 2E000000 .4byte .LVL16 + 2148 0232 31000000 .4byte .LVL17-1 + 2149 0236 0100 .2byte 0x1 + 2150 0238 50 .byte 0x50 + 2151 0239 31000000 .4byte .LVL17-1 + 2152 023d 34000000 .4byte .LVL18 + 2153 0241 0100 .2byte 0x1 + 2154 0243 54 .byte 0x54 + 2155 0244 00000000 .4byte 0 + 2156 0248 00000000 .4byte 0 + 2157 .section .debug_aranges,"",%progbits + 2158 0000 34000000 .4byte 0x34 + 2159 0004 0200 .2byte 0x2 + 2160 0006 00000000 .4byte .Ldebug_info0 + 2161 000a 04 .byte 0x4 + 2162 000b 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 39 + + + 2163 000c 0000 .2byte 0 + 2164 000e 0000 .2byte 0 + 2165 0010 00000000 .4byte .LFB7 + 2166 0014 0C000000 .4byte .LFE7-.LFB7 + 2167 0018 00000000 .4byte .LFB8 + 2168 001c 44000000 .4byte .LFE8-.LFB8 + 2169 0020 00000000 .4byte .LFB9 + 2170 0024 36000000 .4byte .LFE9-.LFB9 + 2171 0028 00000000 .4byte .LFB10 + 2172 002c 3C000000 .4byte .LFE10-.LFB10 + 2173 0030 00000000 .4byte 0 + 2174 0034 00000000 .4byte 0 + 2175 .section .debug_ranges,"",%progbits + 2176 .Ldebug_ranges0: + 2177 0000 00000000 .4byte .LFB7 + 2178 0004 0C000000 .4byte .LFE7 + 2179 0008 00000000 .4byte .LFB8 + 2180 000c 44000000 .4byte .LFE8 + 2181 0010 00000000 .4byte .LFB9 + 2182 0014 36000000 .4byte .LFE9 + 2183 0018 00000000 .4byte .LFB10 + 2184 001c 3C000000 .4byte .LFE10 + 2185 0020 00000000 .4byte 0 + 2186 0024 00000000 .4byte 0 + 2187 .section .debug_line,"",%progbits + 2188 .Ldebug_line0: + 2189 0000 E8010000 .section .debug_str,"MS",%progbits,1 + 2189 02006701 + 2189 00000201 + 2189 FB0E0D00 + 2189 01010101 + 2190 .LASF72: + 2191 0000 7466756E .ascii "tfunc_t\000" + 2191 635F7400 + 2192 .LASF35: + 2193 0008 705F6D73 .ascii "p_msg\000" + 2193 6700 + 2194 .LASF2: + 2195 000e 73697A65 .ascii "size_t\000" + 2195 5F7400 + 2196 .LASF67: + 2197 0015 7264796D .ascii "rdymsg\000" + 2197 736700 + 2198 .LASF12: + 2199 001c 75696E74 .ascii "uint64_t\000" + 2199 36345F74 + 2199 00 + 2200 .LASF66: + 2201 0025 4D656D6F .ascii "MemoryPool\000" + 2201 7279506F + 2201 6F6C00 + 2202 .LASF51: + 2203 0030 6D656D67 .ascii "memgetfunc_t\000" + 2203 65746675 + 2203 6E635F74 + 2203 00 + 2204 .LASF13: + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 40 + + + 2205 003d 6C6F6E67 .ascii "long long unsigned int\000" + 2205 206C6F6E + 2205 6720756E + 2205 7369676E + 2205 65642069 + 2206 .LASF68: + 2207 0054 65786974 .ascii "exitcode\000" + 2207 636F6465 + 2207 00 + 2208 .LASF55: + 2209 005d 685F6672 .ascii "h_free\000" + 2209 656500 + 2210 .LASF75: + 2211 0064 68656170 .ascii "heapp\000" + 2211 7000 + 2212 .LASF57: + 2213 006a 6E657874 .ascii "next\000" + 2213 00 + 2214 .LASF24: + 2215 006f 705F7072 .ascii "p_prio\000" + 2215 696F00 + 2216 .LASF11: + 2217 0076 6C6F6E67 .ascii "long long int\000" + 2217 206C6F6E + 2217 6720696E + 2217 7400 + 2218 .LASF1: + 2219 0084 7369676E .ascii "signed char\000" + 2219 65642063 + 2219 68617200 + 2220 .LASF56: + 2221 0090 685F6D74 .ascii "h_mtx\000" + 2221 7800 + 2222 .LASF39: + 2223 0096 705F6D70 .ascii "p_mpool\000" + 2223 6F6F6C00 + 2224 .LASF48: + 2225 009e 6D5F7175 .ascii "m_queue\000" + 2225 65756500 + 2226 .LASF80: + 2227 00a6 63684865 .ascii "chHeapFree\000" + 2227 61704672 + 2227 656500 + 2228 .LASF82: + 2229 00b1 63685468 .ascii "chThdCreateI\000" + 2229 64437265 + 2229 61746549 + 2229 00 + 2230 .LASF8: + 2231 00be 6C6F6E67 .ascii "long int\000" + 2231 20696E74 + 2231 00 + 2232 .LASF74: + 2233 00c7 63685468 .ascii "chThdCreateFromHeap\000" + 2233 64437265 + 2233 61746546 + 2233 726F6D48 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 41 + + + 2233 65617000 + 2234 .LASF15: + 2235 00db 74737461 .ascii "tstate_t\000" + 2235 74655F74 + 2235 00 + 2236 .LASF63: + 2237 00e4 6D705F6E .ascii "mp_next\000" + 2237 65787400 + 2238 .LASF26: + 2239 00ec 705F6E65 .ascii "p_newer\000" + 2239 77657200 + 2240 .LASF78: + 2241 00f4 63685468 .ascii "chThdCreateFromMemoryPool\000" + 2241 64437265 + 2241 61746546 + 2241 726F6D4D + 2241 656D6F72 + 2242 .LASF65: + 2243 010e 6D705F70 .ascii "mp_provider\000" + 2243 726F7669 + 2243 64657200 + 2244 .LASF42: + 2245 011a 72656761 .ascii "regarm_t\000" + 2245 726D5F74 + 2245 00 + 2246 .LASF59: + 2247 0123 616C6967 .ascii "align\000" + 2247 6E00 + 2248 .LASF0: + 2249 0129 756E7369 .ascii "unsigned int\000" + 2249 676E6564 + 2249 20696E74 + 2249 00 + 2250 .LASF10: + 2251 0136 6C6F6E67 .ascii "long unsigned int\000" + 2251 20756E73 + 2251 69676E65 + 2251 6420696E + 2251 7400 + 2252 .LASF45: + 2253 0148 636F6E74 .ascii "context\000" + 2253 65787400 + 2254 .LASF60: + 2255 0150 73697A65 .ascii "size\000" + 2255 00 + 2256 .LASF6: + 2257 0155 73686F72 .ascii "short unsigned int\000" + 2257 7420756E + 2257 7369676E + 2257 65642069 + 2257 6E7400 + 2258 .LASF18: + 2259 0168 6D73675F .ascii "msg_t\000" + 2259 7400 + 2260 .LASF86: + 2261 016e 2E2E2F2E .ascii "../..//os/kernel/src/chdynamic.c\000" + 2261 2E2F2F6F + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 42 + + + 2261 732F6B65 + 2261 726E656C + 2261 2F737263 + 2262 .LASF14: + 2263 018f 746D6F64 .ascii "tmode_t\000" + 2263 655F7400 + 2264 .LASF41: + 2265 0197 54687265 .ascii "ThreadsList\000" + 2265 6164734C + 2265 69737400 + 2266 .LASF19: + 2267 01a3 6576656E .ascii "eventmask_t\000" + 2267 746D6173 + 2267 6B5F7400 + 2268 .LASF47: + 2269 01af 4D757465 .ascii "Mutex\000" + 2269 7800 + 2270 .LASF73: + 2271 01b5 63685468 .ascii "chThdAddRef\000" + 2271 64416464 + 2271 52656600 + 2272 .LASF43: + 2273 01c1 73746B61 .ascii "stkalign_t\000" + 2273 6C69676E + 2273 5F7400 + 2274 .LASF46: + 2275 01cc 73697A65 .ascii "sizetype\000" + 2275 74797065 + 2275 00 + 2276 .LASF27: + 2277 01d5 705F6F6C .ascii "p_older\000" + 2277 64657200 + 2278 .LASF87: + 2279 01dd 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 2279 73657273 + 2279 5C496D61 + 2279 6E6F6C5C + 2279 64657665 + 2280 020a 6C696361 .ascii "lications\\smartcities\000" + 2280 74696F6E + 2280 735C736D + 2280 61727463 + 2280 69746965 + 2281 .LASF40: + 2282 0220 54687265 .ascii "ThreadsQueue\000" + 2282 61647351 + 2282 75657565 + 2282 00 + 2283 .LASF64: + 2284 022d 6D705F6F .ascii "mp_object_size\000" + 2284 626A6563 + 2284 745F7369 + 2284 7A6500 + 2285 .LASF85: + 2286 023c 474E5520 .ascii "GNU C 4.7.2\000" + 2286 4320342E + 2286 372E3200 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 43 + + + 2287 .LASF76: + 2288 0248 7072696F .ascii "prio\000" + 2288 00 + 2289 .LASF52: + 2290 024d 4D656D6F .ascii "MemoryHeap\000" + 2290 72794865 + 2290 617000 + 2291 .LASF62: + 2292 0258 70685F6E .ascii "ph_next\000" + 2292 65787400 + 2293 .LASF16: + 2294 0260 74726566 .ascii "trefs_t\000" + 2294 735F7400 + 2295 .LASF77: + 2296 0268 72656673 .ascii "refs\000" + 2296 00 + 2297 .LASF23: + 2298 026d 705F7072 .ascii "p_prev\000" + 2298 657600 + 2299 .LASF17: + 2300 0274 74707269 .ascii "tprio_t\000" + 2300 6F5F7400 + 2301 .LASF7: + 2302 027c 696E7433 .ascii "int32_t\000" + 2302 325F7400 + 2303 .LASF4: + 2304 0284 756E7369 .ascii "unsigned char\000" + 2304 676E6564 + 2304 20636861 + 2304 7200 + 2305 .LASF54: + 2306 0292 685F7072 .ascii "h_provider\000" + 2306 6F766964 + 2306 657200 + 2307 .LASF37: + 2308 029d 705F6D74 .ascii "p_mtxlist\000" + 2308 786C6973 + 2308 7400 + 2309 .LASF5: + 2310 02a7 73686F72 .ascii "short int\000" + 2310 7420696E + 2310 7400 + 2311 .LASF29: + 2312 02b1 705F7374 .ascii "p_state\000" + 2312 61746500 + 2313 .LASF88: + 2314 02b9 68656170 .ascii "heap_header\000" + 2314 5F686561 + 2314 64657200 + 2315 .LASF70: + 2316 02c5 65776D61 .ascii "ewmask\000" + 2316 736B00 + 2317 .LASF22: + 2318 02cc 705F6E65 .ascii "p_next\000" + 2318 787400 + 2319 .LASF30: + 2320 02d3 705F666C .ascii "p_flags\000" + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 44 + + + 2320 61677300 + 2321 .LASF89: + 2322 02db 63685468 .ascii "chThdRelease\000" + 2322 6452656C + 2322 65617365 + 2322 00 + 2323 .LASF21: + 2324 02e8 54687265 .ascii "Thread\000" + 2324 616400 + 2325 .LASF81: + 2326 02ef 63684865 .ascii "chHeapAlloc\000" + 2326 6170416C + 2326 6C6F6300 + 2327 .LASF36: + 2328 02fb 705F6570 .ascii "p_epending\000" + 2328 656E6469 + 2328 6E6700 + 2329 .LASF9: + 2330 0306 75696E74 .ascii "uint32_t\000" + 2330 33325F74 + 2330 00 + 2331 .LASF58: + 2332 030f 68656170 .ascii "heap\000" + 2332 00 + 2333 .LASF71: + 2334 0314 63686172 .ascii "char\000" + 2334 00 + 2335 .LASF50: + 2336 0319 6D5F6E65 .ascii "m_next\000" + 2336 787400 + 2337 .LASF20: + 2338 0320 73797374 .ascii "systime_t\000" + 2338 696D655F + 2338 7400 + 2339 .LASF38: + 2340 032a 705F7265 .ascii "p_realprio\000" + 2340 616C7072 + 2340 696F00 + 2341 .LASF32: + 2342 0335 705F7469 .ascii "p_time\000" + 2342 6D6500 + 2343 .LASF44: + 2344 033c 696E7463 .ascii "intctx\000" + 2344 747800 + 2345 .LASF34: + 2346 0343 705F6D73 .ascii "p_msgqueue\000" + 2346 67717565 + 2346 756500 + 2347 .LASF83: + 2348 034e 63685363 .ascii "chSchWakeupS\000" + 2348 6857616B + 2348 65757053 + 2348 00 + 2349 .LASF61: + 2350 035b 706F6F6C .ascii "pool_header\000" + 2350 5F686561 + 2350 64657200 + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 45 + + + 2351 .LASF31: + 2352 0367 705F7265 .ascii "p_refs\000" + 2352 667300 + 2353 .LASF3: + 2354 036e 75696E74 .ascii "uint8_t\000" + 2354 385F7400 + 2355 .LASF84: + 2356 0376 6368506F .ascii "chPoolAlloc\000" + 2356 6F6C416C + 2356 6C6F6300 + 2357 .LASF79: + 2358 0382 6368506F .ascii "chPoolFree\000" + 2358 6F6C4672 + 2358 656500 + 2359 .LASF69: + 2360 038d 77746F62 .ascii "wtobjp\000" + 2360 6A7000 + 2361 .LASF28: + 2362 0394 705F6E61 .ascii "p_name\000" + 2362 6D6500 + 2363 .LASF49: + 2364 039b 6D5F6F77 .ascii "m_owner\000" + 2364 6E657200 + 2365 .LASF25: + 2366 03a3 705F6374 .ascii "p_ctx\000" + 2366 7800 + 2367 .LASF33: + 2368 03a9 705F7761 .ascii "p_waiting\000" + 2368 6974696E + 2368 6700 + 2369 .LASF53: + 2370 03b3 6D656D6F .ascii "memory_heap\000" + 2370 72795F68 + 2370 65617000 + 2371 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\ccztHEA0.s page 46 + + +DEFINED SYMBOLS + *ABS*:00000000 chdynamic.c +C:\cygwin\tmp\ccztHEA0.s:19 .text.chThdAddRef:00000000 $t +C:\cygwin\tmp\ccztHEA0.s:25 .text.chThdAddRef:00000000 chThdAddRef +C:\cygwin\tmp\ccztHEA0.s:54 .text.chThdRelease:00000000 $t +C:\cygwin\tmp\ccztHEA0.s:60 .text.chThdRelease:00000000 chThdRelease +C:\cygwin\tmp\ccztHEA0.s:132 .text.chThdCreateFromHeap:00000000 $t +C:\cygwin\tmp\ccztHEA0.s:138 .text.chThdCreateFromHeap:00000000 chThdCreateFromHeap +C:\cygwin\tmp\ccztHEA0.s:205 .text.chThdCreateFromMemoryPool:00000000 $t +C:\cygwin\tmp\ccztHEA0.s:211 .text.chThdCreateFromMemoryPool:00000000 chThdCreateFromMemoryPool + .debug_frame:00000010 $d + +UNDEFINED SYMBOLS +chPoolFree +chHeapFree +chHeapAlloc +chThdCreateI +chSchWakeupS +chPoolAlloc diff --git a/Project/applications/smartcities/build/lst/chevents.lst b/Project/applications/smartcities/build/lst/chevents.lst new file mode 100644 index 0000000..e8ef2ab --- /dev/null +++ b/Project/applications/smartcities/build/lst/chevents.lst @@ -0,0 +1,4350 @@ +ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "chevents.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text.chEvtRegisterMask,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .global chEvtRegisterMask + 22 .thumb + 23 .thumb_func + 24 .type chEvtRegisterMask, %function + 25 chEvtRegisterMask: + 26 .LFB7: + 27 .file 1 "../..//os/kernel/src/chevents.c" + 28 .loc 1 82 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .LVL0: + 34 0000 10B4 push {r4} + 35 .LCFI0: + 36 .cfi_def_cfa_offset 4 + 37 .cfi_offset 4, -4 + 38 .loc 1 86 0 + 39 @ 86 "../..//os/kernel/src/chevents.c" 1 + 40 0002 72B6 cpsid i + 41 @ 0 "" 2 + 42 .loc 1 89 0 + 43 .thumb + 44 0004 40F20003 movw r3, #:lower16:rlist + 45 0008 C0F20003 movt r3, #:upper16:rlist + 46 .loc 1 87 0 + 47 000c 0468 ldr r4, [r0, #0] + 48 .loc 1 89 0 + 49 000e DB69 ldr r3, [r3, #28] + 50 .loc 1 87 0 + 51 0010 0C60 str r4, [r1, #0] + 52 .loc 1 88 0 + 53 0012 0160 str r1, [r0, #0] + 54 .loc 1 89 0 + 55 0014 4B60 str r3, [r1, #4] + 56 .loc 1 90 0 + 57 0016 8A60 str r2, [r1, #8] + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 2 + + + 58 .loc 1 91 0 + 59 @ 91 "../..//os/kernel/src/chevents.c" 1 + 60 0018 62B6 cpsie i + 61 @ 0 "" 2 + 62 .loc 1 92 0 + 63 .thumb + 64 001a 10BC pop {r4} + 65 001c 7047 bx lr + 66 .cfi_endproc + 67 .LFE7: + 68 .size chEvtRegisterMask, .-chEvtRegisterMask + 69 001e 00BF .section .text.chEvtUnregister,"ax",%progbits + 70 .align 2 + 71 .p2align 4,,15 + 72 .global chEvtUnregister + 73 .thumb + 74 .thumb_func + 75 .type chEvtUnregister, %function + 76 chEvtUnregister: + 77 .LFB8: + 78 .loc 1 107 0 + 79 .cfi_startproc + 80 @ args = 0, pretend = 0, frame = 0 + 81 @ frame_needed = 0, uses_anonymous_args = 0 + 82 @ link register save eliminated. + 83 .LVL1: + 84 .loc 1 113 0 + 85 @ 113 "../..//os/kernel/src/chevents.c" 1 + 86 0000 72B6 cpsid i + 87 @ 0 "" 2 + 88 .loc 1 112 0 + 89 .thumb + 90 0002 0246 mov r2, r0 + 91 .loc 1 114 0 + 92 0004 00E0 b .L3 + 93 .LVL2: + 94 .L6: + 95 .loc 1 115 0 + 96 0006 1A46 mov r2, r3 + 97 .LVL3: + 98 .L3: + 99 .loc 1 114 0 discriminator 1 + 100 0008 1368 ldr r3, [r2, #0] + 101 000a 8342 cmp r3, r0 + 102 000c 03D0 beq .L4 + 103 .loc 1 115 0 + 104 000e 9942 cmp r1, r3 + 105 0010 F9D1 bne .L6 + 106 .loc 1 116 0 + 107 0012 0B68 ldr r3, [r1, #0] + 108 0014 1360 str r3, [r2, #0] + 109 .L4: + 110 .loc 1 121 0 + 111 @ 121 "../..//os/kernel/src/chevents.c" 1 + 112 0016 62B6 cpsie i + 113 @ 0 "" 2 + 114 .thumb + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 3 + + + 115 0018 7047 bx lr + 116 .cfi_endproc + 117 .LFE8: + 118 .size chEvtUnregister, .-chEvtUnregister + 119 001a 00BFAFF3 .section .text.chEvtClearFlags,"ax",%progbits + 119 0080 + 120 .align 2 + 121 .p2align 4,,15 + 122 .global chEvtClearFlags + 123 .thumb + 124 .thumb_func + 125 .type chEvtClearFlags, %function + 126 chEvtClearFlags: + 127 .LFB9: + 128 .loc 1 132 0 + 129 .cfi_startproc + 130 @ args = 0, pretend = 0, frame = 0 + 131 @ frame_needed = 0, uses_anonymous_args = 0 + 132 @ link register save eliminated. + 133 .LVL4: + 134 .loc 1 135 0 + 135 @ 135 "../..//os/kernel/src/chevents.c" 1 + 136 0000 72B6 cpsid i + 137 @ 0 "" 2 + 138 .loc 1 137 0 + 139 .thumb + 140 0002 40F20003 movw r3, #:lower16:rlist + 141 0006 C0F20003 movt r3, #:upper16:rlist + 142 000a DA69 ldr r2, [r3, #28] + 143 000c 936B ldr r3, [r2, #56] + 144 .LVL5: + 145 .loc 1 138 0 + 146 000e 23EA0001 bic r1, r3, r0 + 147 0012 9163 str r1, [r2, #56] + 148 .loc 1 140 0 + 149 @ 140 "../..//os/kernel/src/chevents.c" 1 + 150 0014 62B6 cpsie i + 151 @ 0 "" 2 + 152 .loc 1 142 0 + 153 .thumb + 154 0016 1840 ands r0, r0, r3 + 155 .LVL6: + 156 0018 7047 bx lr + 157 .cfi_endproc + 158 .LFE9: + 159 .size chEvtClearFlags, .-chEvtClearFlags + 160 001a 00BFAFF3 .section .text.chEvtAddFlags,"ax",%progbits + 160 0080 + 161 .align 2 + 162 .p2align 4,,15 + 163 .global chEvtAddFlags + 164 .thumb + 165 .thumb_func + 166 .type chEvtAddFlags, %function + 167 chEvtAddFlags: + 168 .LFB10: + 169 .loc 1 153 0 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 4 + + + 170 .cfi_startproc + 171 @ args = 0, pretend = 0, frame = 0 + 172 @ frame_needed = 0, uses_anonymous_args = 0 + 173 @ link register save eliminated. + 174 .LVL7: + 175 .loc 1 155 0 + 176 @ 155 "../..//os/kernel/src/chevents.c" 1 + 177 0000 72B6 cpsid i + 178 @ 0 "" 2 + 179 .loc 1 157 0 + 180 .thumb + 181 0002 40F20003 movw r3, #:lower16:rlist + 182 0006 C0F20003 movt r3, #:upper16:rlist + 183 000a DB69 ldr r3, [r3, #28] + 184 000c 9A6B ldr r2, [r3, #56] + 185 000e 1043 orrs r0, r0, r2 + 186 .LVL8: + 187 0010 9863 str r0, [r3, #56] + 188 .LVL9: + 189 .loc 1 159 0 + 190 @ 159 "../..//os/kernel/src/chevents.c" 1 + 191 0012 62B6 cpsie i + 192 @ 0 "" 2 + 193 .loc 1 161 0 + 194 .thumb + 195 0014 7047 bx lr + 196 .cfi_endproc + 197 .LFE10: + 198 .size chEvtAddFlags, .-chEvtAddFlags + 199 0016 00BFAFF3 .section .text.chEvtSignalFlagsI,"ax",%progbits + 199 0080AFF3 + 199 0080 + 200 .align 2 + 201 .p2align 4,,15 + 202 .global chEvtSignalFlagsI + 203 .thumb + 204 .thumb_func + 205 .type chEvtSignalFlagsI, %function + 206 chEvtSignalFlagsI: + 207 .LFB12: + 208 .loc 1 193 0 + 209 .cfi_startproc + 210 @ args = 0, pretend = 0, frame = 0 + 211 @ frame_needed = 0, uses_anonymous_args = 0 + 212 .LVL10: + 213 0000 08B5 push {r3, lr} + 214 .LCFI1: + 215 .cfi_def_cfa_offset 8 + 216 .cfi_offset 3, -8 + 217 .cfi_offset 14, -4 + 218 .loc 1 198 0 + 219 0002 826B ldr r2, [r0, #56] + 220 .loc 1 200 0 + 221 0004 037F ldrb r3, [r0, #28] @ zero_extendqisi2 + 222 .loc 1 198 0 + 223 0006 1143 orrs r1, r1, r2 + 224 .LVL11: + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 5 + + + 225 .loc 1 200 0 + 226 0008 082B cmp r3, #8 + 227 .loc 1 198 0 + 228 000a 8163 str r1, [r0, #56] + 229 .loc 1 200 0 + 230 000c 0BD0 beq .L14 + 231 .loc 1 201 0 + 232 000e 092B cmp r3, #9 + 233 0010 00D0 beq .L15 + 234 .L10: + 235 0012 08BD pop {r3, pc} + 236 .L15: + 237 .loc 1 203 0 + 238 0014 436A ldr r3, [r0, #36] + 239 0016 1940 ands r1, r1, r3 + 240 .loc 1 202 0 + 241 0018 8B42 cmp r3, r1 + 242 001a FAD1 bne .L10 + 243 .L12: + 244 .LVL12: + 245 .LBB4: + 246 .LBB5: + 247 .loc 1 204 0 + 248 001c FFF7FEFF bl chSchReadyI + 249 .LVL13: + 250 0020 0023 movs r3, #0 + 251 0022 4362 str r3, [r0, #36] + 252 0024 08BD pop {r3, pc} + 253 .LVL14: + 254 .L14: + 255 .LBE5: + 256 .LBE4: + 257 .loc 1 201 0 discriminator 1 + 258 0026 436A ldr r3, [r0, #36] + 259 .loc 1 200 0 discriminator 1 + 260 0028 1942 tst r1, r3 + 261 002a F7D1 bne .L12 + 262 002c 08BD pop {r3, pc} + 263 .cfi_endproc + 264 .LFE12: + 265 .size chEvtSignalFlagsI, .-chEvtSignalFlagsI + 266 002e 00BF .section .text.chEvtSignalFlags,"ax",%progbits + 267 .align 2 + 268 .p2align 4,,15 + 269 .global chEvtSignalFlags + 270 .thumb + 271 .thumb_func + 272 .type chEvtSignalFlags, %function + 273 chEvtSignalFlags: + 274 .LFB11: + 275 .loc 1 171 0 + 276 .cfi_startproc + 277 @ args = 0, pretend = 0, frame = 0 + 278 @ frame_needed = 0, uses_anonymous_args = 0 + 279 .LVL15: + 280 0000 08B5 push {r3, lr} + 281 .LCFI2: + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 6 + + + 282 .cfi_def_cfa_offset 8 + 283 .cfi_offset 3, -8 + 284 .cfi_offset 14, -4 + 285 .loc 1 175 0 + 286 @ 175 "../..//os/kernel/src/chevents.c" 1 + 287 0002 72B6 cpsid i + 288 @ 0 "" 2 + 289 .loc 1 176 0 + 290 .thumb + 291 0004 FFF7FEFF bl chEvtSignalFlagsI + 292 .LVL16: + 293 .loc 1 177 0 + 294 0008 FFF7FEFF bl chSchRescheduleS + 295 .LVL17: + 296 .loc 1 178 0 + 297 @ 178 "../..//os/kernel/src/chevents.c" 1 + 298 000c 62B6 cpsie i + 299 @ 0 "" 2 + 300 .thumb + 301 000e 08BD pop {r3, pc} + 302 .cfi_endproc + 303 .LFE11: + 304 .size chEvtSignalFlags, .-chEvtSignalFlags + 305 .section .text.chEvtBroadcastFlagsI,"ax",%progbits + 306 .align 2 + 307 .p2align 4,,15 + 308 .global chEvtBroadcastFlagsI + 309 .thumb + 310 .thumb_func + 311 .type chEvtBroadcastFlagsI, %function + 312 chEvtBroadcastFlagsI: + 313 .LFB14: + 314 .loc 1 245 0 + 315 .cfi_startproc + 316 @ args = 0, pretend = 0, frame = 0 + 317 @ frame_needed = 0, uses_anonymous_args = 0 + 318 .LVL18: + 319 0000 70B5 push {r4, r5, r6, lr} + 320 .LCFI3: + 321 .cfi_def_cfa_offset 16 + 322 .cfi_offset 4, -16 + 323 .cfi_offset 5, -12 + 324 .cfi_offset 6, -8 + 325 .cfi_offset 14, -4 + 326 .loc 1 251 0 + 327 0002 0468 ldr r4, [r0, #0] + 328 .LVL19: + 329 .loc 1 245 0 + 330 0004 0546 mov r5, r0 + 331 .loc 1 252 0 + 332 0006 A042 cmp r0, r4 + 333 .loc 1 245 0 + 334 0008 0E46 mov r6, r1 + 335 .loc 1 252 0 + 336 000a 07D0 beq .L17 + 337 .LVL20: + 338 .L21: + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 7 + + + 339 .loc 1 253 0 + 340 000c A168 ldr r1, [r4, #8] + 341 000e 6068 ldr r0, [r4, #4] + 342 0010 3143 orrs r1, r1, r6 + 343 0012 FFF7FEFF bl chEvtSignalFlagsI + 344 .LVL21: + 345 .loc 1 254 0 + 346 0016 2468 ldr r4, [r4, #0] + 347 .LVL22: + 348 .loc 1 252 0 + 349 0018 A542 cmp r5, r4 + 350 001a F7D1 bne .L21 + 351 .L17: + 352 001c 70BD pop {r4, r5, r6, pc} + 353 .cfi_endproc + 354 .LFE14: + 355 .size chEvtBroadcastFlagsI, .-chEvtBroadcastFlagsI + 356 001e 00BF .section .text.chEvtBroadcastFlags,"ax",%progbits + 357 .align 2 + 358 .p2align 4,,15 + 359 .global chEvtBroadcastFlags + 360 .thumb + 361 .thumb_func + 362 .type chEvtBroadcastFlags, %function + 363 chEvtBroadcastFlags: + 364 .LFB13: + 365 .loc 1 220 0 + 366 .cfi_startproc + 367 @ args = 0, pretend = 0, frame = 0 + 368 @ frame_needed = 0, uses_anonymous_args = 0 + 369 .LVL23: + 370 0000 08B5 push {r3, lr} + 371 .LCFI4: + 372 .cfi_def_cfa_offset 8 + 373 .cfi_offset 3, -8 + 374 .cfi_offset 14, -4 + 375 .loc 1 222 0 + 376 @ 222 "../..//os/kernel/src/chevents.c" 1 + 377 0002 72B6 cpsid i + 378 @ 0 "" 2 + 379 .loc 1 223 0 + 380 .thumb + 381 0004 FFF7FEFF bl chEvtBroadcastFlagsI + 382 .LVL24: + 383 .loc 1 224 0 + 384 0008 FFF7FEFF bl chSchRescheduleS + 385 .LVL25: + 386 .loc 1 225 0 + 387 @ 225 "../..//os/kernel/src/chevents.c" 1 + 388 000c 62B6 cpsie i + 389 @ 0 "" 2 + 390 .thumb + 391 000e 08BD pop {r3, pc} + 392 .cfi_endproc + 393 .LFE13: + 394 .size chEvtBroadcastFlags, .-chEvtBroadcastFlags + 395 .section .text.chEvtDispatch,"ax",%progbits + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 8 + + + 396 .align 2 + 397 .p2align 4,,15 + 398 .global chEvtDispatch + 399 .thumb + 400 .thumb_func + 401 .type chEvtDispatch, %function + 402 chEvtDispatch: + 403 .LFB15: + 404 .loc 1 267 0 + 405 .cfi_startproc + 406 @ args = 0, pretend = 0, frame = 0 + 407 @ frame_needed = 0, uses_anonymous_args = 0 + 408 .LVL26: + 409 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 410 .LCFI5: + 411 .cfi_def_cfa_offset 24 + 412 .cfi_offset 3, -24 + 413 .cfi_offset 4, -20 + 414 .cfi_offset 5, -16 + 415 .cfi_offset 6, -12 + 416 .cfi_offset 7, -8 + 417 .cfi_offset 14, -4 + 418 .loc 1 273 0 + 419 0002 0D46 mov r5, r1 + 420 .loc 1 267 0 + 421 0004 0746 mov r7, r0 + 422 .loc 1 273 0 + 423 0006 89B1 cbz r1, .L24 + 424 0008 0024 movs r4, #0 + 425 .loc 1 274 0 + 426 000a 0126 movs r6, #1 + 427 000c 01E0 b .L25 + 428 .LVL27: + 429 .L26: + 430 .loc 1 281 0 + 431 000e 0134 adds r4, r4, #1 + 432 .LVL28: + 433 .loc 1 273 0 + 434 0010 65B1 cbz r5, .L24 + 435 .LVL29: + 436 .L25: + 437 .loc 1 274 0 + 438 0012 06FA04F3 lsl r3, r6, r4 + 439 0016 2B42 tst r3, r5 + 440 0018 F9D0 beq .L26 + 441 .loc 1 279 0 + 442 001a 57F82420 ldr r2, [r7, r4, lsl #2] + 443 001e 2046 mov r0, r4 + 444 .loc 1 278 0 + 445 0020 25EA0305 bic r5, r5, r3 + 446 .LVL30: + 447 .loc 1 281 0 + 448 0024 0134 adds r4, r4, #1 + 449 .loc 1 279 0 + 450 0026 9047 blx r2 + 451 .LVL31: + 452 .loc 1 273 0 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 9 + + + 453 0028 002D cmp r5, #0 + 454 002a F2D1 bne .L25 + 455 .LVL32: + 456 .L24: + 457 002c F8BD pop {r3, r4, r5, r6, r7, pc} + 458 .cfi_endproc + 459 .LFE15: + 460 .size chEvtDispatch, .-chEvtDispatch + 461 002e 00BF .section .text.chEvtWaitOne,"ax",%progbits + 462 .align 2 + 463 .p2align 4,,15 + 464 .global chEvtWaitOne + 465 .thumb + 466 .thumb_func + 467 .type chEvtWaitOne, %function + 468 chEvtWaitOne: + 469 .LFB16: + 470 .loc 1 302 0 + 471 .cfi_startproc + 472 @ args = 0, pretend = 0, frame = 0 + 473 @ frame_needed = 0, uses_anonymous_args = 0 + 474 .LVL33: + 475 0000 38B5 push {r3, r4, r5, lr} + 476 .LCFI6: + 477 .cfi_def_cfa_offset 16 + 478 .cfi_offset 3, -16 + 479 .cfi_offset 4, -12 + 480 .cfi_offset 5, -8 + 481 .cfi_offset 14, -4 + 482 .loc 1 303 0 + 483 0002 0B4B ldr r3, .L35 + 484 .loc 1 302 0 + 485 0004 0546 mov r5, r0 + 486 .loc 1 303 0 + 487 0006 DC69 ldr r4, [r3, #28] + 488 .LVL34: + 489 .loc 1 306 0 + 490 @ 306 "../..//os/kernel/src/chevents.c" 1 + 491 0008 72B6 cpsid i + 492 @ 0 "" 2 + 493 .loc 1 308 0 + 494 .thumb + 495 000a A36B ldr r3, [r4, #56] + 496 .LVL35: + 497 000c 10EA0302 ands r2, r0, r3 + 498 .LVL36: + 499 0010 06D1 bne .L34 + 500 .loc 1 309 0 + 501 0012 6062 str r0, [r4, #36] + 502 .loc 1 310 0 + 503 0014 0820 movs r0, #8 + 504 .LVL37: + 505 0016 FFF7FEFF bl chSchGoSleepS + 506 .LVL38: + 507 .loc 1 311 0 + 508 001a A36B ldr r3, [r4, #56] + 509 001c 05EA0302 and r2, r5, r3 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 10 + + + 510 .LVL39: + 511 .L34: + 512 .loc 1 313 0 + 513 0020 5042 negs r0, r2 + 514 0022 1040 ands r0, r0, r2 + 515 .LVL40: + 516 .loc 1 314 0 + 517 0024 23EA0003 bic r3, r3, r0 + 518 0028 A363 str r3, [r4, #56] + 519 .loc 1 316 0 + 520 @ 316 "../..//os/kernel/src/chevents.c" 1 + 521 002a 62B6 cpsie i + 522 @ 0 "" 2 + 523 .loc 1 318 0 + 524 .thumb + 525 002c 38BD pop {r3, r4, r5, pc} + 526 .L36: + 527 002e 00BF .align 2 + 528 .L35: + 529 0030 00000000 .word rlist + 530 .cfi_endproc + 531 .LFE16: + 532 .size chEvtWaitOne, .-chEvtWaitOne + 533 0034 AFF30080 .section .text.chEvtWaitAny,"ax",%progbits + 533 AFF30080 + 533 AFF30080 + 534 .align 2 + 535 .p2align 4,,15 + 536 .global chEvtWaitAny + 537 .thumb + 538 .thumb_func + 539 .type chEvtWaitAny, %function + 540 chEvtWaitAny: + 541 .LFB17: + 542 .loc 1 331 0 + 543 .cfi_startproc + 544 @ args = 0, pretend = 0, frame = 0 + 545 @ frame_needed = 0, uses_anonymous_args = 0 + 546 .LVL41: + 547 0000 38B5 push {r3, r4, r5, lr} + 548 .LCFI7: + 549 .cfi_def_cfa_offset 16 + 550 .cfi_offset 3, -16 + 551 .cfi_offset 4, -12 + 552 .cfi_offset 5, -8 + 553 .cfi_offset 14, -4 + 554 .loc 1 332 0 + 555 0002 094B ldr r3, .L39 + 556 .loc 1 331 0 + 557 0004 0546 mov r5, r0 + 558 .loc 1 332 0 + 559 0006 DC69 ldr r4, [r3, #28] + 560 .LVL42: + 561 .loc 1 335 0 + 562 @ 335 "../..//os/kernel/src/chevents.c" 1 + 563 0008 72B6 cpsid i + 564 @ 0 "" 2 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 11 + + + 565 .loc 1 337 0 + 566 .thumb + 567 000a A36B ldr r3, [r4, #56] + 568 .LVL43: + 569 000c 1840 ands r0, r0, r3 + 570 .LVL44: + 571 000e 06D1 bne .L38 + 572 .loc 1 339 0 + 573 0010 0820 movs r0, #8 + 574 .LVL45: + 575 .loc 1 338 0 + 576 0012 6562 str r5, [r4, #36] + 577 .loc 1 339 0 + 578 0014 FFF7FEFF bl chSchGoSleepS + 579 .LVL46: + 580 .loc 1 340 0 + 581 0018 A36B ldr r3, [r4, #56] + 582 001a 05EA0300 and r0, r5, r3 + 583 .LVL47: + 584 .L38: + 585 .loc 1 342 0 + 586 001e 23EA0003 bic r3, r3, r0 + 587 0022 A363 str r3, [r4, #56] + 588 .loc 1 344 0 + 589 @ 344 "../..//os/kernel/src/chevents.c" 1 + 590 0024 62B6 cpsie i + 591 @ 0 "" 2 + 592 .loc 1 346 0 + 593 .thumb + 594 0026 38BD pop {r3, r4, r5, pc} + 595 .L40: + 596 .align 2 + 597 .L39: + 598 0028 00000000 .word rlist + 599 .cfi_endproc + 600 .LFE17: + 601 .size chEvtWaitAny, .-chEvtWaitAny + 602 002c AFF30080 .section .text.chEvtWaitAll,"ax",%progbits + 603 .align 2 + 604 .p2align 4,,15 + 605 .global chEvtWaitAll + 606 .thumb + 607 .thumb_func + 608 .type chEvtWaitAll, %function + 609 chEvtWaitAll: + 610 .LFB18: + 611 .loc 1 359 0 + 612 .cfi_startproc + 613 @ args = 0, pretend = 0, frame = 0 + 614 @ frame_needed = 0, uses_anonymous_args = 0 + 615 .LVL48: + 616 0000 38B5 push {r3, r4, r5, lr} + 617 .LCFI8: + 618 .cfi_def_cfa_offset 16 + 619 .cfi_offset 3, -16 + 620 .cfi_offset 4, -12 + 621 .cfi_offset 5, -8 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 12 + + + 622 .cfi_offset 14, -4 + 623 .loc 1 360 0 + 624 0002 0A4B ldr r3, .L43 + 625 .loc 1 359 0 + 626 0004 0446 mov r4, r0 + 627 .loc 1 360 0 + 628 0006 DD69 ldr r5, [r3, #28] + 629 .LVL49: + 630 .loc 1 362 0 + 631 @ 362 "../..//os/kernel/src/chevents.c" 1 + 632 0008 72B6 cpsid i + 633 @ 0 "" 2 + 634 .loc 1 364 0 + 635 .thumb + 636 000a AB6B ldr r3, [r5, #56] + 637 000c 00EA0302 and r2, r0, r3 + 638 0010 8242 cmp r2, r0 + 639 0012 04D0 beq .L42 + 640 .loc 1 365 0 + 641 0014 6862 str r0, [r5, #36] + 642 .loc 1 366 0 + 643 0016 0920 movs r0, #9 + 644 .LVL50: + 645 0018 FFF7FEFF bl chSchGoSleepS + 646 .LVL51: + 647 001c AB6B ldr r3, [r5, #56] + 648 .L42: + 649 .loc 1 368 0 + 650 001e 23EA0403 bic r3, r3, r4 + 651 0022 AB63 str r3, [r5, #56] + 652 .loc 1 370 0 + 653 @ 370 "../..//os/kernel/src/chevents.c" 1 + 654 0024 62B6 cpsie i + 655 @ 0 "" 2 + 656 .loc 1 372 0 + 657 .thumb + 658 0026 2046 mov r0, r4 + 659 0028 38BD pop {r3, r4, r5, pc} + 660 .L44: + 661 002a 00BF .align 2 + 662 .L43: + 663 002c 00000000 .word rlist + 664 .cfi_endproc + 665 .LFE18: + 666 .size chEvtWaitAll, .-chEvtWaitAll + 667 .section .text.chEvtWaitOneTimeout,"ax",%progbits + 668 .align 2 + 669 .p2align 4,,15 + 670 .global chEvtWaitOneTimeout + 671 .thumb + 672 .thumb_func + 673 .type chEvtWaitOneTimeout, %function + 674 chEvtWaitOneTimeout: + 675 .LFB19: + 676 .loc 1 398 0 + 677 .cfi_startproc + 678 @ args = 0, pretend = 0, frame = 0 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 13 + + + 679 @ frame_needed = 0, uses_anonymous_args = 0 + 680 .LVL52: + 681 .loc 1 399 0 + 682 0000 0D4B ldr r3, .L51 + 683 .loc 1 398 0 + 684 0002 70B5 push {r4, r5, r6, lr} + 685 .LCFI9: + 686 .cfi_def_cfa_offset 16 + 687 .cfi_offset 4, -16 + 688 .cfi_offset 5, -12 + 689 .cfi_offset 6, -8 + 690 .cfi_offset 14, -4 + 691 .loc 1 398 0 + 692 0004 0546 mov r5, r0 + 693 .loc 1 399 0 + 694 0006 DE69 ldr r6, [r3, #28] + 695 .LVL53: + 696 .loc 1 402 0 + 697 @ 402 "../..//os/kernel/src/chevents.c" 1 + 698 0008 72B6 cpsid i + 699 @ 0 "" 2 + 700 .loc 1 404 0 + 701 .thumb + 702 000a B36B ldr r3, [r6, #56] + 703 .LVL54: + 704 000c 10EA0304 ands r4, r0, r3 + 705 .LVL55: + 706 0010 0CD1 bne .L46 + 707 .loc 1 405 0 + 708 0012 11B9 cbnz r1, .L47 + 709 .LVL56: + 710 .L50: + 711 .loc 1 419 0 + 712 @ 419 "../..//os/kernel/src/chevents.c" 1 + 713 0014 62B6 cpsie i + 714 @ 0 "" 2 + 715 .loc 1 421 0 + 716 .thumb + 717 0016 2046 mov r0, r4 + 718 0018 70BD pop {r4, r5, r6, pc} + 719 .LVL57: + 720 .L47: + 721 .loc 1 409 0 + 722 001a 7062 str r0, [r6, #36] + 723 .loc 1 410 0 + 724 001c 0820 movs r0, #8 + 725 .LVL58: + 726 001e FFF7FEFF bl chSchGoSleepTimeoutS + 727 .LVL59: + 728 0022 0028 cmp r0, #0 + 729 0024 F6DB blt .L50 + 730 .loc 1 414 0 + 731 0026 B36B ldr r3, [r6, #56] + 732 0028 05EA0304 and r4, r5, r3 + 733 .LVL60: + 734 .L46: + 735 .loc 1 416 0 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 14 + + + 736 002c 6242 negs r2, r4 + 737 002e 1440 ands r4, r4, r2 + 738 .LVL61: + 739 .loc 1 417 0 + 740 0030 23EA0403 bic r3, r3, r4 + 741 0034 B363 str r3, [r6, #56] + 742 0036 EDE7 b .L50 + 743 .L52: + 744 .align 2 + 745 .L51: + 746 0038 00000000 .word rlist + 747 .cfi_endproc + 748 .LFE19: + 749 .size chEvtWaitOneTimeout, .-chEvtWaitOneTimeout + 750 003c AFF30080 .section .text.chEvtWaitAnyTimeout,"ax",%progbits + 751 .align 2 + 752 .p2align 4,,15 + 753 .global chEvtWaitAnyTimeout + 754 .thumb + 755 .thumb_func + 756 .type chEvtWaitAnyTimeout, %function + 757 chEvtWaitAnyTimeout: + 758 .LFB20: + 759 .loc 1 441 0 + 760 .cfi_startproc + 761 @ args = 0, pretend = 0, frame = 0 + 762 @ frame_needed = 0, uses_anonymous_args = 0 + 763 .LVL62: + 764 .loc 1 442 0 + 765 0000 0C4B ldr r3, .L59 + 766 .loc 1 441 0 + 767 0002 70B5 push {r4, r5, r6, lr} + 768 .LCFI10: + 769 .cfi_def_cfa_offset 16 + 770 .cfi_offset 4, -16 + 771 .cfi_offset 5, -12 + 772 .cfi_offset 6, -8 + 773 .cfi_offset 14, -4 + 774 .loc 1 441 0 + 775 0004 0446 mov r4, r0 + 776 .loc 1 442 0 + 777 0006 DD69 ldr r5, [r3, #28] + 778 .LVL63: + 779 .loc 1 445 0 + 780 @ 445 "../..//os/kernel/src/chevents.c" 1 + 781 0008 72B6 cpsid i + 782 @ 0 "" 2 + 783 .loc 1 447 0 + 784 .thumb + 785 000a AB6B ldr r3, [r5, #56] + 786 .LVL64: + 787 000c 10EA0306 ands r6, r0, r3 + 788 .LVL65: + 789 0010 0CD1 bne .L54 + 790 .loc 1 448 0 + 791 0012 11B9 cbnz r1, .L55 + 792 .LVL66: + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 15 + + + 793 .L58: + 794 .loc 1 461 0 + 795 @ 461 "../..//os/kernel/src/chevents.c" 1 + 796 0014 62B6 cpsie i + 797 @ 0 "" 2 + 798 .loc 1 463 0 + 799 .thumb + 800 0016 3046 mov r0, r6 + 801 0018 70BD pop {r4, r5, r6, pc} + 802 .LVL67: + 803 .L55: + 804 .loc 1 452 0 + 805 001a 6862 str r0, [r5, #36] + 806 .loc 1 453 0 + 807 001c 0820 movs r0, #8 + 808 .LVL68: + 809 001e FFF7FEFF bl chSchGoSleepTimeoutS + 810 .LVL69: + 811 0022 0028 cmp r0, #0 + 812 0024 F6DB blt .L58 + 813 .loc 1 457 0 + 814 0026 AB6B ldr r3, [r5, #56] + 815 0028 04EA0306 and r6, r4, r3 + 816 .LVL70: + 817 .L54: + 818 .loc 1 459 0 + 819 002c 23EA0603 bic r3, r3, r6 + 820 0030 AB63 str r3, [r5, #56] + 821 0032 EFE7 b .L58 + 822 .L60: + 823 .align 2 + 824 .L59: + 825 0034 00000000 .word rlist + 826 .cfi_endproc + 827 .LFE20: + 828 .size chEvtWaitAnyTimeout, .-chEvtWaitAnyTimeout + 829 0038 AFF30080 .section .text.chEvtWaitAllTimeout,"ax",%progbits + 829 AFF30080 + 830 .align 2 + 831 .p2align 4,,15 + 832 .global chEvtWaitAllTimeout + 833 .thumb + 834 .thumb_func + 835 .type chEvtWaitAllTimeout, %function + 836 chEvtWaitAllTimeout: + 837 .LFB21: + 838 .loc 1 482 0 + 839 .cfi_startproc + 840 @ args = 0, pretend = 0, frame = 0 + 841 @ frame_needed = 0, uses_anonymous_args = 0 + 842 .LVL71: + 843 0000 38B5 push {r3, r4, r5, lr} + 844 .LCFI11: + 845 .cfi_def_cfa_offset 16 + 846 .cfi_offset 3, -16 + 847 .cfi_offset 4, -12 + 848 .cfi_offset 5, -8 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 16 + + + 849 .cfi_offset 14, -4 + 850 .loc 1 483 0 + 851 0002 0E4B ldr r3, .L66 + 852 .loc 1 482 0 + 853 0004 0446 mov r4, r0 + 854 .loc 1 483 0 + 855 0006 DD69 ldr r5, [r3, #28] + 856 .LVL72: + 857 .loc 1 485 0 + 858 @ 485 "../..//os/kernel/src/chevents.c" 1 + 859 0008 72B6 cpsid i + 860 @ 0 "" 2 + 861 .loc 1 487 0 + 862 .thumb + 863 000a AB6B ldr r3, [r5, #56] + 864 000c 1840 ands r0, r0, r3 + 865 .LVL73: + 866 000e A042 cmp r0, r4 + 867 0010 0BD0 beq .L62 + 868 .loc 1 488 0 + 869 0012 19B9 cbnz r1, .L63 + 870 .loc 1 489 0 + 871 @ 489 "../..//os/kernel/src/chevents.c" 1 + 872 0014 62B6 cpsie i + 873 @ 0 "" 2 + 874 .loc 1 490 0 + 875 .thumb + 876 0016 0C46 mov r4, r1 + 877 .LVL74: + 878 .loc 1 502 0 + 879 0018 2046 mov r0, r4 + 880 001a 38BD pop {r3, r4, r5, pc} + 881 .LVL75: + 882 .L63: + 883 .loc 1 493 0 + 884 001c 0920 movs r0, #9 + 885 .loc 1 492 0 + 886 001e 6C62 str r4, [r5, #36] + 887 .loc 1 493 0 + 888 0020 FFF7FEFF bl chSchGoSleepTimeoutS + 889 .LVL76: + 890 0024 0028 cmp r0, #0 + 891 0026 06DB blt .L65 + 892 0028 AB6B ldr r3, [r5, #56] + 893 .L62: + 894 .loc 1 498 0 + 895 002a 23EA0403 bic r3, r3, r4 + 896 002e AB63 str r3, [r5, #56] + 897 .loc 1 500 0 + 898 @ 500 "../..//os/kernel/src/chevents.c" 1 + 899 0030 62B6 cpsie i + 900 @ 0 "" 2 + 901 .LVL77: + 902 .thumb + 903 .L64: + 904 .loc 1 502 0 + 905 0032 2046 mov r0, r4 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 17 + + + 906 0034 38BD pop {r3, r4, r5, pc} + 907 .LVL78: + 908 .L65: + 909 .loc 1 494 0 + 910 @ 494 "../..//os/kernel/src/chevents.c" 1 + 911 0036 62B6 cpsie i + 912 @ 0 "" 2 + 913 .loc 1 495 0 + 914 .thumb + 915 0038 0024 movs r4, #0 + 916 .LVL79: + 917 003a FAE7 b .L64 + 918 .L67: + 919 .align 2 + 920 .L66: + 921 003c 00000000 .word rlist + 922 .cfi_endproc + 923 .LFE21: + 924 .size chEvtWaitAllTimeout, .-chEvtWaitAllTimeout + 925 .text + 926 .Letext0: + 927 .file 2 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 928 .file 3 "../..//os/ports/GCC/ARMCMx/chtypes.h" + 929 .file 4 "../..//os/kernel/include/chlists.h" + 930 .file 5 "../..//os/kernel/include/chthreads.h" + 931 .file 6 "../..//os/ports/GCC/ARMCMx/chcore_v7m.h" + 932 .file 7 "../..//os/kernel/include/chschd.h" + 933 .file 8 "../..//os/kernel/include/chmtx.h" + 934 .file 9 "../..//os/kernel/include/chevents.h" + 935 .section .debug_info,"",%progbits + 936 .Ldebug_info0: + 937 0000 3E0A0000 .4byte 0xa3e + 938 0004 0200 .2byte 0x2 + 939 0006 00000000 .4byte .Ldebug_abbrev0 + 940 000a 04 .byte 0x4 + 941 000b 01 .uleb128 0x1 + 942 000c 67020000 .4byte .LASF90 + 943 0010 01 .byte 0x1 + 944 0011 8D020000 .4byte .LASF91 + 945 0015 12020000 .4byte .LASF92 + 946 0019 00000000 .4byte .Ldebug_ranges0+0 + 947 001d 00000000 .4byte 0 + 948 0021 00000000 .4byte 0 + 949 0025 00000000 .4byte .Ldebug_line0 + 950 0029 02 .uleb128 0x2 + 951 002a 04 .byte 0x4 + 952 002b 05 .byte 0x5 + 953 002c 696E7400 .ascii "int\000" + 954 0030 03 .uleb128 0x3 + 955 0031 04 .byte 0x4 + 956 0032 07 .byte 0x7 + 957 0033 63010000 .4byte .LASF0 + 958 0037 03 .uleb128 0x3 + 959 0038 01 .byte 0x1 + 960 0039 06 .byte 0x6 + 961 003a 68000000 .4byte .LASF1 + 962 003e 04 .uleb128 0x4 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 18 + + + 963 003f D9030000 .4byte .LASF5 + 964 0043 02 .byte 0x2 + 965 0044 2A .byte 0x2a + 966 0045 49000000 .4byte 0x49 + 967 0049 03 .uleb128 0x3 + 968 004a 01 .byte 0x1 + 969 004b 08 .byte 0x8 + 970 004c E5020000 .4byte .LASF2 + 971 0050 03 .uleb128 0x3 + 972 0051 02 .byte 0x2 + 973 0052 05 .byte 0x5 + 974 0053 16030000 .4byte .LASF3 + 975 0057 03 .uleb128 0x3 + 976 0058 02 .byte 0x2 + 977 0059 07 .byte 0x7 + 978 005a 8A010000 .4byte .LASF4 + 979 005e 04 .uleb128 0x4 + 980 005f DD020000 .4byte .LASF6 + 981 0063 02 .byte 0x2 + 982 0064 4F .byte 0x4f + 983 0065 69000000 .4byte 0x69 + 984 0069 03 .uleb128 0x3 + 985 006a 04 .byte 0x4 + 986 006b 05 .byte 0x5 + 987 006c A6000000 .4byte .LASF7 + 988 0070 04 .uleb128 0x4 + 989 0071 65030000 .4byte .LASF8 + 990 0075 02 .byte 0x2 + 991 0076 50 .byte 0x50 + 992 0077 7B000000 .4byte 0x7b + 993 007b 03 .uleb128 0x3 + 994 007c 04 .byte 0x4 + 995 007d 07 .byte 0x7 + 996 007e 70010000 .4byte .LASF9 + 997 0082 03 .uleb128 0x3 + 998 0083 08 .byte 0x8 + 999 0084 05 .byte 0x5 + 1000 0085 5A000000 .4byte .LASF10 + 1001 0089 03 .uleb128 0x3 + 1002 008a 08 .byte 0x8 + 1003 008b 07 .byte 0x7 + 1004 008c 0D000000 .4byte .LASF11 + 1005 0090 04 .uleb128 0x4 + 1006 0091 CD010000 .4byte .LASF12 + 1007 0095 03 .byte 0x3 + 1008 0096 2F .byte 0x2f + 1009 0097 3E000000 .4byte 0x3e + 1010 009b 04 .uleb128 0x4 + 1011 009c AF000000 .4byte .LASF13 + 1012 00a0 03 .byte 0x3 + 1013 00a1 30 .byte 0x30 + 1014 00a2 3E000000 .4byte 0x3e + 1015 00a6 04 .uleb128 0x4 + 1016 00a7 B6020000 .4byte .LASF14 + 1017 00ab 03 .byte 0x3 + 1018 00ac 31 .byte 0x31 + 1019 00ad 3E000000 .4byte 0x3e + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 19 + + + 1020 00b1 04 .uleb128 0x4 + 1021 00b2 C5020000 .4byte .LASF15 + 1022 00b6 03 .byte 0x3 + 1023 00b7 32 .byte 0x32 + 1024 00b8 70000000 .4byte 0x70 + 1025 00bc 04 .uleb128 0x4 + 1026 00bd AF010000 .4byte .LASF16 + 1027 00c1 03 .byte 0x3 + 1028 00c2 33 .byte 0x33 + 1029 00c3 5E000000 .4byte 0x5e + 1030 00c7 04 .uleb128 0x4 + 1031 00c8 2A010000 .4byte .LASF17 + 1032 00cc 03 .byte 0x3 + 1033 00cd 34 .byte 0x34 + 1034 00ce 5E000000 .4byte 0x5e + 1035 00d2 04 .uleb128 0x4 + 1036 00d3 E1010000 .4byte .LASF18 + 1037 00d7 03 .byte 0x3 + 1038 00d8 35 .byte 0x35 + 1039 00d9 70000000 .4byte 0x70 + 1040 00dd 04 .uleb128 0x4 + 1041 00de 8E030000 .4byte .LASF19 + 1042 00e2 03 .byte 0x3 + 1043 00e3 36 .byte 0x36 + 1044 00e4 70000000 .4byte 0x70 + 1045 00e8 04 .uleb128 0x4 + 1046 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.byte 0x23 + 1148 01a3 20 .uleb128 0x20 + 1149 01a4 07 .uleb128 0x7 + 1150 01a5 705F7500 .ascii "p_u\000" + 1151 01a9 05 .byte 0x5 + 1152 01aa AE .byte 0xae + 1153 01ab 7F040000 .4byte 0x47f + 1154 01af 02 .byte 0x2 + 1155 01b0 23 .byte 0x23 + 1156 01b1 24 .uleb128 0x24 + 1157 01b2 06 .uleb128 0x6 + 1158 01b3 46040000 .4byte .LASF33 + 1159 01b7 05 .byte 0x5 + 1160 01b8 B3 .byte 0xb3 + 1161 01b9 62020000 .4byte 0x262 + 1162 01bd 02 .byte 0x2 + 1163 01be 23 .byte 0x23 + 1164 01bf 28 .uleb128 0x28 + 1165 01c0 06 .uleb128 0x6 + 1166 01c1 B7030000 .4byte .LASF34 + 1167 01c5 05 .byte 0x5 + 1168 01c6 B9 .byte 0xb9 + 1169 01c7 40020000 .4byte 0x240 + 1170 01cb 02 .byte 0x2 + 1171 01cc 23 .byte 0x23 + 1172 01cd 2C .uleb128 0x2c + 1173 01ce 06 .uleb128 0x6 + 1174 01cf 00000000 .4byte .LASF35 + 1175 01d3 05 .byte 0x5 + 1176 01d4 BD .byte 0xbd + 1177 01d5 BC000000 .4byte 0xbc + 1178 01d9 02 .byte 0x2 + 1179 01da 23 .byte 0x23 + 1180 01db 34 .uleb128 0x34 + 1181 01dc 06 .uleb128 0x6 + 1182 01dd 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.4byte .LASF58 + 1486 0404 0C .byte 0xc + 1487 0405 09 .byte 0x9 + 1488 0406 2E .byte 0x2e + 1489 0407 36040000 .4byte 0x436 + 1490 040b 06 .uleb128 0x6 + 1491 040c B5010000 .4byte .LASF59 + 1492 0410 09 .byte 0x9 + 1493 0411 2F .byte 0x2f + 1494 0412 36040000 .4byte 0x436 + 1495 0416 02 .byte 0x2 + 1496 0417 23 .byte 0x23 + 1497 0418 00 .uleb128 0 + 1498 0419 06 .uleb128 0x6 + 1499 041a 00030000 .4byte .LASF60 + 1500 041e 09 .byte 0x9 + 1501 041f 32 .byte 0x32 + 1502 0420 3A020000 .4byte 0x23a + 1503 0424 02 .byte 0x2 + 1504 0425 23 .byte 0x23 + 1505 0426 04 .uleb128 0x4 + 1506 0427 06 .uleb128 0x6 + 1507 0428 85020000 .4byte .LASF61 + 1508 042c 09 .byte 0x9 + 1509 042d 34 .byte 0x34 + 1510 042e D2000000 .4byte 0xd2 + 1511 0432 02 .byte 0x2 + 1512 0433 23 .byte 0x23 + 1513 0434 08 .uleb128 0x8 + 1514 0435 00 .byte 0 + 1515 0436 09 .uleb128 0x9 + 1516 0437 04 .byte 0x4 + 1517 0438 F4030000 .4byte 0x3f4 + 1518 043c 05 .uleb128 0x5 + 1519 043d 34010000 .4byte .LASF62 + 1520 0441 04 .byte 0x4 + 1521 0442 09 .byte 0x9 + 1522 0443 3C .byte 0x3c + 1523 0444 57040000 .4byte 0x457 + 1524 0448 06 .uleb128 0x6 + 1525 0449 11040000 .4byte .LASF63 + 1526 044d 09 .byte 0x9 + 1527 044e 3D .byte 0x3d + 1528 044f 36040000 .4byte 0x436 + 1529 0453 02 .byte 0x2 + 1530 0454 23 .byte 0x23 + 1531 0455 00 .uleb128 0 + 1532 0456 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 28 + + + 1533 0457 04 .uleb128 0x4 + 1534 0458 34010000 .4byte .LASF62 + 1535 045c 09 .byte 0x9 + 1536 045d 40 .byte 0x40 + 1537 045e 3C040000 .4byte 0x43c + 1538 0462 04 .uleb128 0x4 + 1539 0463 40010000 .4byte .LASF64 + 1540 0467 09 .byte 0x9 + 1541 0468 45 .byte 0x45 + 1542 0469 6D040000 .4byte 0x46d + 1543 046d 09 .uleb128 0x9 + 1544 046e 04 .byte 0x4 + 1545 046f 73040000 .4byte 0x473 + 1546 0473 0E .uleb128 0xe + 1547 0474 01 .byte 0x1 + 1548 0475 7F040000 .4byte 0x47f + 1549 0479 0F .uleb128 0xf + 1550 047a C7000000 .4byte 0xc7 + 1551 047e 00 .byte 0 + 1552 047f 10 .uleb128 0x10 + 1553 0480 04 .byte 0x4 + 1554 0481 05 .byte 0x5 + 1555 0482 90 .byte 0x90 + 1556 0483 B4040000 .4byte 0x4b4 + 1557 0487 11 .uleb128 0x11 + 1558 0488 06000000 .4byte .LASF65 + 1559 048c 05 .byte 0x5 + 1560 048d 97 .byte 0x97 + 1561 048e BC000000 .4byte 0xbc + 1562 0492 11 .uleb128 0x11 + 1563 0493 24000000 .4byte .LASF66 + 1564 0497 05 .byte 0x5 + 1565 0498 9E .byte 0x9e + 1566 0499 BC000000 .4byte 0xbc + 1567 049d 11 .uleb128 0x11 + 1568 049e 03040000 .4byte .LASF67 + 1569 04a2 05 .byte 0x5 + 1570 04a3 A5 .byte 0xa5 + 1571 04a4 78020000 .4byte 0x278 + 1572 04a8 11 .uleb128 0x11 + 1573 04a9 2F030000 .4byte .LASF68 + 1574 04ad 05 .byte 0x5 + 1575 04ae AC .byte 0xac + 1576 04af D2000000 .4byte 0xd2 + 1577 04b3 00 .byte 0 + 1578 04b4 09 .uleb128 0x9 + 1579 04b5 04 .byte 0x4 + 1580 04b6 BA040000 .4byte 0x4ba + 1581 04ba 12 .uleb128 0x12 + 1582 04bb BF040000 .4byte 0x4bf + 1583 04bf 03 .uleb128 0x3 + 1584 04c0 01 .byte 0x1 + 1585 04c1 08 .byte 0x8 + 1586 04c2 82030000 .4byte .LASF69 + 1587 04c6 09 .uleb128 0x9 + 1588 04c7 04 .byte 0x4 + 1589 04c8 E9030000 .4byte 0x3e9 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 29 + + + 1590 04cc 13 .uleb128 0x13 + 1591 04cd 01 .byte 0x1 + 1592 04ce 2D000000 .4byte .LASF87 + 1593 04d2 01 .byte 0x1 + 1594 04d3 C1 .byte 0xc1 + 1595 04d4 01 .byte 0x1 + 1596 04d5 01 .byte 0x1 + 1597 04d6 F0040000 .4byte 0x4f0 + 1598 04da 14 .uleb128 0x14 + 1599 04db 747000 .ascii "tp\000" + 1600 04de 01 .byte 0x1 + 1601 04df C1 .byte 0xc1 + 1602 04e0 3A020000 .4byte 0x23a + 1603 04e4 15 .uleb128 0x15 + 1604 04e5 08010000 .4byte .LASF70 + 1605 04e9 01 .byte 0x1 + 1606 04ea C1 .byte 0xc1 + 1607 04eb D2000000 .4byte 0xd2 + 1608 04ef 00 .byte 0 + 1609 04f0 16 .uleb128 0x16 + 1610 04f1 01 .byte 0x1 + 1611 04f2 9D010000 .4byte .LASF71 + 1612 04f6 01 .byte 0x1 + 1613 04f7 52 .byte 0x52 + 1614 04f8 01 .byte 0x1 + 1615 04f9 00000000 .4byte .LFB7 + 1616 04fd 1E000000 .4byte .LFE7 + 1617 0501 00000000 .4byte .LLST0 + 1618 0505 01 .byte 0x1 + 1619 0506 32050000 .4byte 0x532 + 1620 050a 17 .uleb128 0x17 + 1621 050b 65737000 .ascii "esp\000" + 1622 050f 01 .byte 0x1 + 1623 0510 52 .byte 0x52 + 1624 0511 32050000 .4byte 0x532 + 1625 0515 01 .byte 0x1 + 1626 0516 50 .byte 0x50 + 1627 0517 17 .uleb128 0x17 + 1628 0518 656C7000 .ascii "elp\000" + 1629 051c 01 .byte 0x1 + 1630 051d 52 .byte 0x52 + 1631 051e 36040000 .4byte 0x436 + 1632 0522 01 .byte 0x1 + 1633 0523 51 .byte 0x51 + 1634 0524 18 .uleb128 0x18 + 1635 0525 08010000 .4byte .LASF70 + 1636 0529 01 .byte 0x1 + 1637 052a 52 .byte 0x52 + 1638 052b D2000000 .4byte 0xd2 + 1639 052f 01 .byte 0x1 + 1640 0530 52 .byte 0x52 + 1641 0531 00 .byte 0 + 1642 0532 09 .uleb128 0x9 + 1643 0533 04 .byte 0x4 + 1644 0534 57040000 .4byte 0x457 + 1645 0538 19 .uleb128 0x19 + 1646 0539 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 30 + + + 1647 053a BD010000 .4byte .LASF72 + 1648 053e 01 .byte 0x1 + 1649 053f 6B .byte 0x6b + 1650 0540 01 .byte 0x1 + 1651 0541 00000000 .4byte .LFB8 + 1652 0545 1A000000 .4byte .LFE8 + 1653 0549 02 .byte 0x2 + 1654 054a 7D .byte 0x7d + 1655 054b 00 .sleb128 0 + 1656 054c 01 .byte 0x1 + 1657 054d 79050000 .4byte 0x579 + 1658 0551 17 .uleb128 0x17 + 1659 0552 65737000 .ascii "esp\000" + 1660 0556 01 .byte 0x1 + 1661 0557 6B .byte 0x6b + 1662 0558 32050000 .4byte 0x532 + 1663 055c 01 .byte 0x1 + 1664 055d 50 .byte 0x50 + 1665 055e 17 .uleb128 0x17 + 1666 055f 656C7000 .ascii "elp\000" + 1667 0563 01 .byte 0x1 + 1668 0564 6B .byte 0x6b + 1669 0565 36040000 .4byte 0x436 + 1670 0569 01 .byte 0x1 + 1671 056a 51 .byte 0x51 + 1672 056b 1A .uleb128 0x1a + 1673 056c 7000 .ascii "p\000" + 1674 056e 01 .byte 0x1 + 1675 056f 6C .byte 0x6c + 1676 0570 36040000 .4byte 0x436 + 1677 0574 20000000 .4byte .LLST1 + 1678 0578 00 .byte 0 + 1679 0579 1B .uleb128 0x1b + 1680 057a 01 .byte 0x1 + 1681 057b CD020000 .4byte .LASF73 + 1682 057f 01 .byte 0x1 + 1683 0580 84 .byte 0x84 + 1684 0581 01 .byte 0x1 + 1685 0582 D2000000 .4byte 0xd2 + 1686 0586 00000000 .4byte .LFB9 + 1687 058a 1A000000 .4byte .LFE9 + 1688 058e 02 .byte 0x2 + 1689 058f 7D .byte 0x7d + 1690 0590 00 .sleb128 0 + 1691 0591 01 .byte 0x1 + 1692 0592 B3050000 .4byte 0x5b3 + 1693 0596 1C .uleb128 0x1c + 1694 0597 08010000 .4byte .LASF70 + 1695 059b 01 .byte 0x1 + 1696 059c 84 .byte 0x84 + 1697 059d D2000000 .4byte 0xd2 + 1698 05a1 3E000000 .4byte .LLST2 + 1699 05a5 1A .uleb128 0x1a + 1700 05a6 6D00 .ascii "m\000" + 1701 05a8 01 .byte 0x1 + 1702 05a9 85 .byte 0x85 + 1703 05aa D2000000 .4byte 0xd2 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 31 + + + 1704 05ae 5F000000 .4byte .LLST3 + 1705 05b2 00 .byte 0 + 1706 05b3 1B .uleb128 0x1b + 1707 05b4 01 .byte 0x1 + 1708 05b5 98000000 .4byte .LASF74 + 1709 05b9 01 .byte 0x1 + 1710 05ba 99 .byte 0x99 + 1711 05bb 01 .byte 0x1 + 1712 05bc D2000000 .4byte 0xd2 + 1713 05c0 00000000 .4byte .LFB10 + 1714 05c4 16000000 .4byte .LFE10 + 1715 05c8 02 .byte 0x2 + 1716 05c9 7D .byte 0x7d + 1717 05ca 00 .sleb128 0 + 1718 05cb 01 .byte 0x1 + 1719 05cc E0050000 .4byte 0x5e0 + 1720 05d0 1C .uleb128 0x1c + 1721 05d1 08010000 .4byte .LASF70 + 1722 05d5 01 .byte 0x1 + 1723 05d6 99 .byte 0x99 + 1724 05d7 D2000000 .4byte 0xd2 + 1725 05db 82000000 .4byte .LLST4 + 1726 05df 00 .byte 0 + 1727 05e0 1D .uleb128 0x1d + 1728 05e1 CC040000 .4byte 0x4cc + 1729 05e5 00000000 .4byte .LFB12 + 1730 05e9 2E000000 .4byte .LFE12 + 1731 05ed AE000000 .4byte .LLST5 + 1732 05f1 01 .byte 0x1 + 1733 05f2 42060000 .4byte 0x642 + 1734 05f6 1E .uleb128 0x1e + 1735 05f7 DA040000 .4byte 0x4da + 1736 05fb CE000000 .4byte .LLST6 + 1737 05ff 1E .uleb128 0x1e + 1738 0600 E4040000 .4byte 0x4e4 + 1739 0604 FA000000 .4byte .LLST7 + 1740 0608 1F .uleb128 0x1f + 1741 0609 CC040000 .4byte 0x4cc + 1742 060d 1C000000 .4byte .LBB4 + 1743 0611 26000000 .4byte .LBE4 + 1744 0615 01 .byte 0x1 + 1745 0616 C1 .byte 0xc1 + 1746 0617 1E .uleb128 0x1e + 1747 0618 DA040000 .4byte 0x4da + 1748 061c 1B010000 .4byte .LLST8 + 1749 0620 20 .uleb128 0x20 + 1750 0621 1C000000 .4byte .LBB5 + 1751 0625 26000000 .4byte .LBE5 + 1752 0629 21 .uleb128 0x21 + 1753 062a E4040000 .4byte 0x4e4 + 1754 062e 22 .uleb128 0x22 + 1755 062f 20000000 .4byte .LVL13 + 1756 0633 F2090000 .4byte 0x9f2 + 1757 0637 23 .uleb128 0x23 + 1758 0638 01 .byte 0x1 + 1759 0639 50 .byte 0x50 + 1760 063a 03 .byte 0x3 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 32 + + + 1761 063b F3 .byte 0xf3 + 1762 063c 01 .uleb128 0x1 + 1763 063d 50 .byte 0x50 + 1764 063e 00 .byte 0 + 1765 063f 00 .byte 0 + 1766 0640 00 .byte 0 + 1767 0641 00 .byte 0 + 1768 0642 16 .uleb128 0x16 + 1769 0643 01 .byte 0x1 + 1770 0644 52010000 .4byte .LASF75 + 1771 0648 01 .byte 0x1 + 1772 0649 AB .byte 0xab + 1773 064a 01 .byte 0x1 + 1774 064b 00000000 .4byte .LFB11 + 1775 064f 10000000 .4byte .LFE11 + 1776 0653 3C010000 .4byte .LLST9 + 1777 0657 01 .byte 0x1 + 1778 0658 9F060000 .4byte 0x69f + 1779 065c 24 .uleb128 0x24 + 1780 065d 747000 .ascii "tp\000" + 1781 0660 01 .byte 0x1 + 1782 0661 AB .byte 0xab + 1783 0662 3A020000 .4byte 0x23a + 1784 0666 5C010000 .4byte .LLST10 + 1785 066a 1C .uleb128 0x1c + 1786 066b 08010000 .4byte .LASF70 + 1787 066f 01 .byte 0x1 + 1788 0670 AB .byte 0xab + 1789 0671 D2000000 .4byte 0xd2 + 1790 0675 7D010000 .4byte .LLST11 + 1791 0679 25 .uleb128 0x25 + 1792 067a 08000000 .4byte .LVL16 + 1793 067e CC040000 .4byte 0x4cc + 1794 0682 95060000 .4byte 0x695 + 1795 0686 23 .uleb128 0x23 + 1796 0687 01 .byte 0x1 + 1797 0688 51 .byte 0x51 + 1798 0689 03 .byte 0x3 + 1799 068a F3 .byte 0xf3 + 1800 068b 01 .uleb128 0x1 + 1801 068c 51 .byte 0x51 + 1802 068d 23 .uleb128 0x23 + 1803 068e 01 .byte 0x1 + 1804 068f 50 .byte 0x50 + 1805 0690 03 .byte 0x3 + 1806 0691 F3 .byte 0xf3 + 1807 0692 01 .uleb128 0x1 + 1808 0693 50 .byte 0x50 + 1809 0694 00 .byte 0 + 1810 0695 26 .uleb128 0x26 + 1811 0696 0C000000 .4byte .LVL17 + 1812 069a 0A0A0000 .4byte 0xa0a + 1813 069e 00 .byte 0 + 1814 069f 16 .uleb128 0x16 + 1815 06a0 01 .byte 0x1 + 1816 06a1 D2000000 .4byte .LASF76 + 1817 06a5 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 33 + + + 1818 06a6 F5 .byte 0xf5 + 1819 06a7 01 .byte 0x1 + 1820 06a8 00000000 .4byte .LFB14 + 1821 06ac 1E000000 .4byte .LFE14 + 1822 06b0 9E010000 .4byte .LLST12 + 1823 06b4 01 .byte 0x1 + 1824 06b5 EE060000 .4byte 0x6ee + 1825 06b9 24 .uleb128 0x24 + 1826 06ba 65737000 .ascii "esp\000" + 1827 06be 01 .byte 0x1 + 1828 06bf F5 .byte 0xf5 + 1829 06c0 32050000 .4byte 0x532 + 1830 06c4 BE010000 .4byte .LLST13 + 1831 06c8 1C .uleb128 0x1c + 1832 06c9 08010000 .4byte .LASF70 + 1833 06cd 01 .byte 0x1 + 1834 06ce F5 .byte 0xf5 + 1835 06cf D2000000 .4byte 0xd2 + 1836 06d3 DC010000 .4byte .LLST14 + 1837 06d7 27 .uleb128 0x27 + 1838 06d8 656C7000 .ascii "elp\000" + 1839 06dc 01 .byte 0x1 + 1840 06dd F6 .byte 0xf6 + 1841 06de 36040000 .4byte 0x436 + 1842 06e2 01 .byte 0x1 + 1843 06e3 54 .byte 0x54 + 1844 06e4 26 .uleb128 0x26 + 1845 06e5 16000000 .4byte .LVL21 + 1846 06e9 CC040000 .4byte 0x4cc + 1847 06ed 00 .byte 0 + 1848 06ee 16 .uleb128 0x16 + 1849 06ef 01 .byte 0x1 + 1850 06f0 16010000 .4byte .LASF77 + 1851 06f4 01 .byte 0x1 + 1852 06f5 DC .byte 0xdc + 1853 06f6 01 .byte 0x1 + 1854 06f7 00000000 .4byte .LFB13 + 1855 06fb 10000000 .4byte .LFE13 + 1856 06ff FA010000 .4byte .LLST15 + 1857 0703 01 .byte 0x1 + 1858 0704 4C070000 .4byte 0x74c + 1859 0708 24 .uleb128 0x24 + 1860 0709 65737000 .ascii "esp\000" + 1861 070d 01 .byte 0x1 + 1862 070e DC .byte 0xdc + 1863 070f 32050000 .4byte 0x532 + 1864 0713 1A020000 .4byte .LLST16 + 1865 0717 1C .uleb128 0x1c + 1866 0718 08010000 .4byte .LASF70 + 1867 071c 01 .byte 0x1 + 1868 071d DC .byte 0xdc + 1869 071e D2000000 .4byte 0xd2 + 1870 0722 3B020000 .4byte .LLST17 + 1871 0726 25 .uleb128 0x25 + 1872 0727 08000000 .4byte .LVL24 + 1873 072b 9F060000 .4byte 0x69f + 1874 072f 42070000 .4byte 0x742 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 34 + + + 1875 0733 23 .uleb128 0x23 + 1876 0734 01 .byte 0x1 + 1877 0735 51 .byte 0x51 + 1878 0736 03 .byte 0x3 + 1879 0737 F3 .byte 0xf3 + 1880 0738 01 .uleb128 0x1 + 1881 0739 51 .byte 0x51 + 1882 073a 23 .uleb128 0x23 + 1883 073b 01 .byte 0x1 + 1884 073c 50 .byte 0x50 + 1885 073d 03 .byte 0x3 + 1886 073e F3 .byte 0xf3 + 1887 073f 01 .uleb128 0x1 + 1888 0740 50 .byte 0x50 + 1889 0741 00 .byte 0 + 1890 0742 26 .uleb128 0x26 + 1891 0743 0C000000 .4byte .LVL25 + 1892 0747 0A0A0000 .4byte 0xa0a + 1893 074b 00 .byte 0 + 1894 074c 28 .uleb128 0x28 + 1895 074d 01 .byte 0x1 + 1896 074e FC010000 .4byte .LASF78 + 1897 0752 01 .byte 0x1 + 1898 0753 0B01 .2byte 0x10b + 1899 0755 01 .byte 0x1 + 1900 0756 00000000 .4byte .LFB15 + 1901 075a 2E000000 .4byte .LFE15 + 1902 075e 5C020000 .4byte .LLST18 + 1903 0762 01 .byte 0x1 + 1904 0763 A4070000 .4byte 0x7a4 + 1905 0767 29 .uleb128 0x29 + 1906 0768 AD020000 .4byte .LASF79 + 1907 076c 01 .byte 0x1 + 1908 076d 0B01 .2byte 0x10b + 1909 076f A4070000 .4byte 0x7a4 + 1910 0773 7C020000 .4byte .LLST19 + 1911 0777 29 .uleb128 0x29 + 1912 0778 08010000 .4byte .LASF70 + 1913 077c 01 .byte 0x1 + 1914 077d 0B01 .2byte 0x10b + 1915 077f D2000000 .4byte 0xd2 + 1916 0783 9A020000 .4byte .LLST20 + 1917 0787 2A .uleb128 0x2a + 1918 0788 65696400 .ascii "eid\000" + 1919 078c 01 .byte 0x1 + 1920 078d 0C01 .2byte 0x10c + 1921 078f C7000000 .4byte 0xc7 + 1922 0793 B8020000 .4byte .LLST21 + 1923 0797 2B .uleb128 0x2b + 1924 0798 28000000 .4byte .LVL31 + 1925 079c 23 .uleb128 0x23 + 1926 079d 01 .byte 0x1 + 1927 079e 50 .byte 0x50 + 1928 079f 02 .byte 0x2 + 1929 07a0 74 .byte 0x74 + 1930 07a1 7F .sleb128 -1 + 1931 07a2 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 35 + + + 1932 07a3 00 .byte 0 + 1933 07a4 09 .uleb128 0x9 + 1934 07a5 04 .byte 0x4 + 1935 07a6 AA070000 .4byte 0x7aa + 1936 07aa 12 .uleb128 0x12 + 1937 07ab 62040000 .4byte 0x462 + 1938 07af 2C .uleb128 0x2c + 1939 07b0 01 .byte 0x1 + 1940 07b1 F3020000 .4byte .LASF80 + 1941 07b5 01 .byte 0x1 + 1942 07b6 2E01 .2byte 0x12e + 1943 07b8 01 .byte 0x1 + 1944 07b9 D2000000 .4byte 0xd2 + 1945 07bd 00000000 .4byte .LFB16 + 1946 07c1 34000000 .4byte .LFE16 + 1947 07c5 E2020000 .4byte .LLST22 + 1948 07c9 01 .byte 0x1 + 1949 07ca 0A080000 .4byte 0x80a + 1950 07ce 29 .uleb128 0x29 + 1951 07cf 08010000 .4byte .LASF70 + 1952 07d3 01 .byte 0x1 + 1953 07d4 2E01 .2byte 0x12e + 1954 07d6 D2000000 .4byte 0xd2 + 1955 07da 02030000 .4byte .LLST23 + 1956 07de 2D .uleb128 0x2d + 1957 07df 63747000 .ascii "ctp\000" + 1958 07e3 01 .byte 0x1 + 1959 07e4 2F01 .2byte 0x12f + 1960 07e6 3A020000 .4byte 0x23a + 1961 07ea 01 .byte 0x1 + 1962 07eb 54 .byte 0x54 + 1963 07ec 2A .uleb128 0x2a + 1964 07ed 6D00 .ascii "m\000" + 1965 07ef 01 .byte 0x1 + 1966 07f0 3001 .2byte 0x130 + 1967 07f2 D2000000 .4byte 0xd2 + 1968 07f6 20030000 .4byte .LLST24 + 1969 07fa 22 .uleb128 0x22 + 1970 07fb 1A000000 .4byte .LVL38 + 1971 07ff 140A0000 .4byte 0xa14 + 1972 0803 23 .uleb128 0x23 + 1973 0804 01 .byte 0x1 + 1974 0805 50 .byte 0x50 + 1975 0806 01 .byte 0x1 + 1976 0807 38 .byte 0x38 + 1977 0808 00 .byte 0 + 1978 0809 00 .byte 0 + 1979 080a 2C .uleb128 0x2c + 1980 080b 01 .byte 0x1 + 1981 080c C5000000 .4byte .LASF81 + 1982 0810 01 .byte 0x1 + 1983 0811 4B01 .2byte 0x14b + 1984 0813 01 .byte 0x1 + 1985 0814 D2000000 .4byte 0xd2 + 1986 0818 00000000 .4byte .LFB17 + 1987 081c 2C000000 .4byte .LFE17 + 1988 0820 59030000 .4byte .LLST25 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 36 + + + 1989 0824 01 .byte 0x1 + 1990 0825 65080000 .4byte 0x865 + 1991 0829 29 .uleb128 0x29 + 1992 082a 08010000 .4byte .LASF70 + 1993 082e 01 .byte 0x1 + 1994 082f 4B01 .2byte 0x14b + 1995 0831 D2000000 .4byte 0xd2 + 1996 0835 79030000 .4byte .LLST26 + 1997 0839 2D .uleb128 0x2d + 1998 083a 63747000 .ascii "ctp\000" + 1999 083e 01 .byte 0x1 + 2000 083f 4C01 .2byte 0x14c + 2001 0841 3A020000 .4byte 0x23a + 2002 0845 01 .byte 0x1 + 2003 0846 54 .byte 0x54 + 2004 0847 2A .uleb128 0x2a + 2005 0848 6D00 .ascii "m\000" + 2006 084a 01 .byte 0x1 + 2007 084b 4D01 .2byte 0x14d + 2008 084d D2000000 .4byte 0xd2 + 2009 0851 97030000 .4byte .LLST27 + 2010 0855 22 .uleb128 0x22 + 2011 0856 18000000 .4byte .LVL46 + 2012 085a 140A0000 .4byte 0xa14 + 2013 085e 23 .uleb128 0x23 + 2014 085f 01 .byte 0x1 + 2015 0860 50 .byte 0x50 + 2016 0861 01 .byte 0x1 + 2017 0862 38 .byte 0x38 + 2018 0863 00 .byte 0 + 2019 0864 00 .byte 0 + 2020 0865 2C .uleb128 0x2c + 2021 0866 01 .byte 0x1 + 2022 0867 B8000000 .4byte .LASF82 + 2023 086b 01 .byte 0x1 + 2024 086c 6701 .2byte 0x167 + 2025 086e 01 .byte 0x1 + 2026 086f D2000000 .4byte 0xd2 + 2027 0873 00000000 .4byte .LFB18 + 2028 0877 30000000 .4byte .LFE18 + 2029 087b D5030000 .4byte .LLST28 + 2030 087f 01 .byte 0x1 + 2031 0880 B2080000 .4byte 0x8b2 + 2032 0884 29 .uleb128 0x29 + 2033 0885 08010000 .4byte .LASF70 + 2034 0889 01 .byte 0x1 + 2035 088a 6701 .2byte 0x167 + 2036 088c D2000000 .4byte 0xd2 + 2037 0890 F5030000 .4byte .LLST29 + 2038 0894 2D .uleb128 0x2d + 2039 0895 63747000 .ascii "ctp\000" + 2040 0899 01 .byte 0x1 + 2041 089a 6801 .2byte 0x168 + 2042 089c 3A020000 .4byte 0x23a + 2043 08a0 01 .byte 0x1 + 2044 08a1 55 .byte 0x55 + 2045 08a2 22 .uleb128 0x22 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 37 + + + 2046 08a3 1C000000 .4byte .LVL51 + 2047 08a7 140A0000 .4byte 0xa14 + 2048 08ab 23 .uleb128 0x23 + 2049 08ac 01 .byte 0x1 + 2050 08ad 50 .byte 0x50 + 2051 08ae 01 .byte 0x1 + 2052 08af 39 .byte 0x39 + 2053 08b0 00 .byte 0 + 2054 08b1 00 .byte 0 + 2055 08b2 2C .uleb128 0x2c + 2056 08b3 01 .byte 0x1 + 2057 08b4 EF030000 .4byte .LASF83 + 2058 08b8 01 .byte 0x1 + 2059 08b9 8E01 .2byte 0x18e + 2060 08bb 01 .byte 0x1 + 2061 08bc D2000000 .4byte 0xd2 + 2062 08c0 00000000 .4byte .LFB19 + 2063 08c4 3C000000 .4byte .LFE19 + 2064 08c8 13040000 .4byte .LLST30 + 2065 08cc 01 .byte 0x1 + 2066 08cd 1D090000 .4byte 0x91d + 2067 08d1 29 .uleb128 0x29 + 2068 08d2 08010000 .4byte .LASF70 + 2069 08d6 01 .byte 0x1 + 2070 08d7 8E01 .2byte 0x18e + 2071 08d9 D2000000 .4byte 0xd2 + 2072 08dd 33040000 .4byte .LLST31 + 2073 08e1 29 .uleb128 0x29 + 2074 08e2 62020000 .4byte .LASF84 + 2075 08e6 01 .byte 0x1 + 2076 08e7 8E01 .2byte 0x18e + 2077 08e9 DD000000 .4byte 0xdd + 2078 08ed 67040000 .4byte .LLST32 + 2079 08f1 2D .uleb128 0x2d + 2080 08f2 63747000 .ascii "ctp\000" + 2081 08f6 01 .byte 0x1 + 2082 08f7 8F01 .2byte 0x18f + 2083 08f9 3A020000 .4byte 0x23a + 2084 08fd 01 .byte 0x1 + 2085 08fe 56 .byte 0x56 + 2086 08ff 2A .uleb128 0x2a + 2087 0900 6D00 .ascii "m\000" + 2088 0902 01 .byte 0x1 + 2089 0903 9001 .2byte 0x190 + 2090 0905 D2000000 .4byte 0xd2 + 2091 0909 A1040000 .4byte .LLST33 + 2092 090d 22 .uleb128 0x22 + 2093 090e 22000000 .4byte .LVL59 + 2094 0912 280A0000 .4byte 0xa28 + 2095 0916 23 .uleb128 0x23 + 2096 0917 01 .byte 0x1 + 2097 0918 50 .byte 0x50 + 2098 0919 01 .byte 0x1 + 2099 091a 38 .byte 0x38 + 2100 091b 00 .byte 0 + 2101 091c 00 .byte 0 + 2102 091d 2C .uleb128 0x2c + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 38 + + + 2103 091e 01 .byte 0x1 + 2104 091f 3F000000 .4byte .LASF85 + 2105 0923 01 .byte 0x1 + 2106 0924 B901 .2byte 0x1b9 + 2107 0926 01 .byte 0x1 + 2108 0927 D2000000 .4byte 0xd2 + 2109 092b 00000000 .4byte .LFB20 + 2110 092f 38000000 .4byte .LFE20 + 2111 0933 C4040000 .4byte .LLST34 + 2112 0937 01 .byte 0x1 + 2113 0938 88090000 .4byte 0x988 + 2114 093c 29 .uleb128 0x29 + 2115 093d 08010000 .4byte .LASF70 + 2116 0941 01 .byte 0x1 + 2117 0942 B901 .2byte 0x1b9 + 2118 0944 D2000000 .4byte 0xd2 + 2119 0948 E4040000 .4byte .LLST35 + 2120 094c 29 .uleb128 0x29 + 2121 094d 62020000 .4byte .LASF84 + 2122 0951 01 .byte 0x1 + 2123 0952 B901 .2byte 0x1b9 + 2124 0954 DD000000 .4byte 0xdd + 2125 0958 18050000 .4byte .LLST36 + 2126 095c 2D .uleb128 0x2d + 2127 095d 63747000 .ascii "ctp\000" + 2128 0961 01 .byte 0x1 + 2129 0962 BA01 .2byte 0x1ba + 2130 0964 3A020000 .4byte 0x23a + 2131 0968 01 .byte 0x1 + 2132 0969 55 .byte 0x55 + 2133 096a 2A .uleb128 0x2a + 2134 096b 6D00 .ascii "m\000" + 2135 096d 01 .byte 0x1 + 2136 096e BB01 .2byte 0x1bb + 2137 0970 D2000000 .4byte 0xd2 + 2138 0974 52050000 .4byte .LLST37 + 2139 0978 22 .uleb128 0x22 + 2140 0979 22000000 .4byte .LVL69 + 2141 097d 280A0000 .4byte 0xa28 + 2142 0981 23 .uleb128 0x23 + 2143 0982 01 .byte 0x1 + 2144 0983 50 .byte 0x50 + 2145 0984 01 .byte 0x1 + 2146 0985 38 .byte 0x38 + 2147 0986 00 .byte 0 + 2148 0987 00 .byte 0 + 2149 0988 2C .uleb128 0x2c + 2150 0989 01 .byte 0x1 + 2151 098a 74000000 .4byte .LASF86 + 2152 098e 01 .byte 0x1 + 2153 098f E201 .2byte 0x1e2 + 2154 0991 01 .byte 0x1 + 2155 0992 D2000000 .4byte 0xd2 + 2156 0996 00000000 .4byte .LFB21 + 2157 099a 40000000 .4byte .LFE21 + 2158 099e 75050000 .4byte .LLST38 + 2159 09a2 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 39 + + + 2160 09a3 E5090000 .4byte 0x9e5 + 2161 09a7 29 .uleb128 0x29 + 2162 09a8 08010000 .4byte .LASF70 + 2163 09ac 01 .byte 0x1 + 2164 09ad E201 .2byte 0x1e2 + 2165 09af D2000000 .4byte 0xd2 + 2166 09b3 95050000 .4byte .LLST39 + 2167 09b7 29 .uleb128 0x29 + 2168 09b8 62020000 .4byte .LASF84 + 2169 09bc 01 .byte 0x1 + 2170 09bd E201 .2byte 0x1e2 + 2171 09bf DD000000 .4byte 0xdd + 2172 09c3 F3050000 .4byte .LLST40 + 2173 09c7 2D .uleb128 0x2d + 2174 09c8 63747000 .ascii "ctp\000" + 2175 09cc 01 .byte 0x1 + 2176 09cd E301 .2byte 0x1e3 + 2177 09cf 3A020000 .4byte 0x23a + 2178 09d3 01 .byte 0x1 + 2179 09d4 55 .byte 0x55 + 2180 09d5 22 .uleb128 0x22 + 2181 09d6 24000000 .4byte .LVL76 + 2182 09da 280A0000 .4byte 0xa28 + 2183 09de 23 .uleb128 0x23 + 2184 09df 01 .byte 0x1 + 2185 09e0 50 .byte 0x50 + 2186 09e1 01 .byte 0x1 + 2187 09e2 39 .byte 0x39 + 2188 09e3 00 .byte 0 + 2189 09e4 00 .byte 0 + 2190 09e5 2E .uleb128 0x2e + 2191 09e6 D3030000 .4byte .LASF93 + 2192 09ea 07 .byte 0x7 + 2193 09eb 72 .byte 0x72 + 2194 09ec A1030000 .4byte 0x3a1 + 2195 09f0 01 .byte 0x1 + 2196 09f1 01 .byte 0x1 + 2197 09f2 2F .uleb128 0x2f + 2198 09f3 01 .byte 0x1 + 2199 09f4 76030000 .4byte .LASF94 + 2200 09f8 07 .byte 0x7 + 2201 09f9 93 .byte 0x93 + 2202 09fa 01 .byte 0x1 + 2203 09fb 3A020000 .4byte 0x23a + 2204 09ff 01 .byte 0x1 + 2205 0a00 0A0A0000 .4byte 0xa0a + 2206 0a04 0F .uleb128 0xf + 2207 0a05 3A020000 .4byte 0x23a + 2208 0a09 00 .byte 0 + 2209 0a0a 30 .uleb128 0x30 + 2210 0a0b 01 .byte 0x1 + 2211 0a0c EF000000 .4byte .LASF95 + 2212 0a10 07 .byte 0x7 + 2213 0a11 9F .byte 0x9f + 2214 0a12 01 .byte 0x1 + 2215 0a13 01 .byte 0x1 + 2216 0a14 31 .uleb128 0x31 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 40 + + + 2217 0a15 01 .byte 0x1 + 2218 0a16 4C030000 .4byte .LASF88 + 2219 0a1a 07 .byte 0x7 + 2220 0a1b 96 .byte 0x96 + 2221 0a1c 01 .byte 0x1 + 2222 0a1d 01 .byte 0x1 + 2223 0a1e 280A0000 .4byte 0xa28 + 2224 0a22 0F .uleb128 0xf + 2225 0a23 9B000000 .4byte 0x9b + 2226 0a27 00 .byte 0 + 2227 0a28 32 .uleb128 0x32 + 2228 0a29 01 .byte 0x1 + 2229 0a2a 19040000 .4byte .LASF89 + 2230 0a2e 07 .byte 0x7 + 2231 0a2f 99 .byte 0x99 + 2232 0a30 01 .byte 0x1 + 2233 0a31 BC000000 .4byte 0xbc + 2234 0a35 01 .byte 0x1 + 2235 0a36 0F .uleb128 0xf + 2236 0a37 9B000000 .4byte 0x9b + 2237 0a3b 0F .uleb128 0xf + 2238 0a3c DD000000 .4byte 0xdd + 2239 0a40 00 .byte 0 + 2240 0a41 00 .byte 0 + 2241 .section .debug_abbrev,"",%progbits + 2242 .Ldebug_abbrev0: + 2243 0000 01 .uleb128 0x1 + 2244 0001 11 .uleb128 0x11 + 2245 0002 01 .byte 0x1 + 2246 0003 25 .uleb128 0x25 + 2247 0004 0E .uleb128 0xe + 2248 0005 13 .uleb128 0x13 + 2249 0006 0B .uleb128 0xb + 2250 0007 03 .uleb128 0x3 + 2251 0008 0E .uleb128 0xe + 2252 0009 1B .uleb128 0x1b + 2253 000a 0E .uleb128 0xe + 2254 000b 55 .uleb128 0x55 + 2255 000c 06 .uleb128 0x6 + 2256 000d 11 .uleb128 0x11 + 2257 000e 01 .uleb128 0x1 + 2258 000f 52 .uleb128 0x52 + 2259 0010 01 .uleb128 0x1 + 2260 0011 10 .uleb128 0x10 + 2261 0012 06 .uleb128 0x6 + 2262 0013 00 .byte 0 + 2263 0014 00 .byte 0 + 2264 0015 02 .uleb128 0x2 + 2265 0016 24 .uleb128 0x24 + 2266 0017 00 .byte 0 + 2267 0018 0B .uleb128 0xb + 2268 0019 0B .uleb128 0xb + 2269 001a 3E .uleb128 0x3e + 2270 001b 0B .uleb128 0xb + 2271 001c 03 .uleb128 0x3 + 2272 001d 08 .uleb128 0x8 + 2273 001e 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 41 + + + 2274 001f 00 .byte 0 + 2275 0020 03 .uleb128 0x3 + 2276 0021 24 .uleb128 0x24 + 2277 0022 00 .byte 0 + 2278 0023 0B .uleb128 0xb + 2279 0024 0B .uleb128 0xb + 2280 0025 3E .uleb128 0x3e + 2281 0026 0B .uleb128 0xb + 2282 0027 03 .uleb128 0x3 + 2283 0028 0E .uleb128 0xe + 2284 0029 00 .byte 0 + 2285 002a 00 .byte 0 + 2286 002b 04 .uleb128 0x4 + 2287 002c 16 .uleb128 0x16 + 2288 002d 00 .byte 0 + 2289 002e 03 .uleb128 0x3 + 2290 002f 0E .uleb128 0xe + 2291 0030 3A .uleb128 0x3a + 2292 0031 0B .uleb128 0xb + 2293 0032 3B .uleb128 0x3b + 2294 0033 0B .uleb128 0xb + 2295 0034 49 .uleb128 0x49 + 2296 0035 13 .uleb128 0x13 + 2297 0036 00 .byte 0 + 2298 0037 00 .byte 0 + 2299 0038 05 .uleb128 0x5 + 2300 0039 13 .uleb128 0x13 + 2301 003a 01 .byte 0x1 + 2302 003b 03 .uleb128 0x3 + 2303 003c 0E .uleb128 0xe + 2304 003d 0B .uleb128 0xb + 2305 003e 0B .uleb128 0xb + 2306 003f 3A .uleb128 0x3a + 2307 0040 0B .uleb128 0xb + 2308 0041 3B .uleb128 0x3b + 2309 0042 0B .uleb128 0xb + 2310 0043 01 .uleb128 0x1 + 2311 0044 13 .uleb128 0x13 + 2312 0045 00 .byte 0 + 2313 0046 00 .byte 0 + 2314 0047 06 .uleb128 0x6 + 2315 0048 0D .uleb128 0xd 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.uleb128 0xb + 2351 006c 3B .uleb128 0x3b + 2352 006d 0B .uleb128 0xb + 2353 006e 01 .uleb128 0x1 + 2354 006f 13 .uleb128 0x13 + 2355 0070 00 .byte 0 + 2356 0071 00 .byte 0 + 2357 0072 09 .uleb128 0x9 + 2358 0073 0F .uleb128 0xf + 2359 0074 00 .byte 0 + 2360 0075 0B .uleb128 0xb + 2361 0076 0B .uleb128 0xb + 2362 0077 49 .uleb128 0x49 + 2363 0078 13 .uleb128 0x13 + 2364 0079 00 .byte 0 + 2365 007a 00 .byte 0 + 2366 007b 0A .uleb128 0xa + 2367 007c 0F .uleb128 0xf + 2368 007d 00 .byte 0 + 2369 007e 0B .uleb128 0xb + 2370 007f 0B .uleb128 0xb + 2371 0080 00 .byte 0 + 2372 0081 00 .byte 0 + 2373 0082 0B .uleb128 0xb + 2374 0083 0D .uleb128 0xd + 2375 0084 00 .byte 0 + 2376 0085 03 .uleb128 0x3 + 2377 0086 08 .uleb128 0x8 + 2378 0087 3A .uleb128 0x3a + 2379 0088 0B .uleb128 0xb + 2380 0089 3B .uleb128 0x3b + 2381 008a 05 .uleb128 0x5 + 2382 008b 49 .uleb128 0x49 + 2383 008c 13 .uleb128 0x13 + 2384 008d 38 .uleb128 0x38 + 2385 008e 0A .uleb128 0xa + 2386 008f 00 .byte 0 + 2387 0090 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 43 + + + 2388 0091 0C .uleb128 0xc + 2389 0092 13 .uleb128 0x13 + 2390 0093 01 .byte 0x1 + 2391 0094 03 .uleb128 0x3 + 2392 0095 0E .uleb128 0xe + 2393 0096 0B .uleb128 0xb + 2394 0097 0B .uleb128 0xb + 2395 0098 3A .uleb128 0x3a + 2396 0099 0B .uleb128 0xb + 2397 009a 3B .uleb128 0x3b + 2398 009b 05 .uleb128 0x5 + 2399 009c 01 .uleb128 0x1 + 2400 009d 13 .uleb128 0x13 + 2401 009e 00 .byte 0 + 2402 009f 00 .byte 0 + 2403 00a0 0D .uleb128 0xd + 2404 00a1 35 .uleb128 0x35 + 2405 00a2 00 .byte 0 + 2406 00a3 49 .uleb128 0x49 + 2407 00a4 13 .uleb128 0x13 + 2408 00a5 00 .byte 0 + 2409 00a6 00 .byte 0 + 2410 00a7 0E .uleb128 0xe + 2411 00a8 15 .uleb128 0x15 + 2412 00a9 01 .byte 0x1 + 2413 00aa 27 .uleb128 0x27 + 2414 00ab 0C .uleb128 0xc + 2415 00ac 01 .uleb128 0x1 + 2416 00ad 13 .uleb128 0x13 + 2417 00ae 00 .byte 0 + 2418 00af 00 .byte 0 + 2419 00b0 0F .uleb128 0xf + 2420 00b1 05 .uleb128 0x5 + 2421 00b2 00 .byte 0 + 2422 00b3 49 .uleb128 0x49 + 2423 00b4 13 .uleb128 0x13 + 2424 00b5 00 .byte 0 + 2425 00b6 00 .byte 0 + 2426 00b7 10 .uleb128 0x10 + 2427 00b8 17 .uleb128 0x17 + 2428 00b9 01 .byte 0x1 + 2429 00ba 0B .uleb128 0xb + 2430 00bb 0B .uleb128 0xb + 2431 00bc 3A .uleb128 0x3a + 2432 00bd 0B .uleb128 0xb + 2433 00be 3B .uleb128 0x3b + 2434 00bf 0B .uleb128 0xb + 2435 00c0 01 .uleb128 0x1 + 2436 00c1 13 .uleb128 0x13 + 2437 00c2 00 .byte 0 + 2438 00c3 00 .byte 0 + 2439 00c4 11 .uleb128 0x11 + 2440 00c5 0D .uleb128 0xd + 2441 00c6 00 .byte 0 + 2442 00c7 03 .uleb128 0x3 + 2443 00c8 0E .uleb128 0xe + 2444 00c9 3A .uleb128 0x3a + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 44 + + + 2445 00ca 0B .uleb128 0xb + 2446 00cb 3B .uleb128 0x3b + 2447 00cc 0B .uleb128 0xb + 2448 00cd 49 .uleb128 0x49 + 2449 00ce 13 .uleb128 0x13 + 2450 00cf 00 .byte 0 + 2451 00d0 00 .byte 0 + 2452 00d1 12 .uleb128 0x12 + 2453 00d2 26 .uleb128 0x26 + 2454 00d3 00 .byte 0 + 2455 00d4 49 .uleb128 0x49 + 2456 00d5 13 .uleb128 0x13 + 2457 00d6 00 .byte 0 + 2458 00d7 00 .byte 0 + 2459 00d8 13 .uleb128 0x13 + 2460 00d9 2E .uleb128 0x2e + 2461 00da 01 .byte 0x1 + 2462 00db 3F .uleb128 0x3f + 2463 00dc 0C .uleb128 0xc + 2464 00dd 03 .uleb128 0x3 + 2465 00de 0E .uleb128 0xe + 2466 00df 3A .uleb128 0x3a + 2467 00e0 0B .uleb128 0xb + 2468 00e1 3B .uleb128 0x3b + 2469 00e2 0B .uleb128 0xb + 2470 00e3 27 .uleb128 0x27 + 2471 00e4 0C .uleb128 0xc + 2472 00e5 20 .uleb128 0x20 + 2473 00e6 0B .uleb128 0xb + 2474 00e7 01 .uleb128 0x1 + 2475 00e8 13 .uleb128 0x13 + 2476 00e9 00 .byte 0 + 2477 00ea 00 .byte 0 + 2478 00eb 14 .uleb128 0x14 + 2479 00ec 05 .uleb128 0x5 + 2480 00ed 00 .byte 0 + 2481 00ee 03 .uleb128 0x3 + 2482 00ef 08 .uleb128 0x8 + 2483 00f0 3A .uleb128 0x3a + 2484 00f1 0B .uleb128 0xb + 2485 00f2 3B .uleb128 0x3b + 2486 00f3 0B .uleb128 0xb + 2487 00f4 49 .uleb128 0x49 + 2488 00f5 13 .uleb128 0x13 + 2489 00f6 00 .byte 0 + 2490 00f7 00 .byte 0 + 2491 00f8 15 .uleb128 0x15 + 2492 00f9 05 .uleb128 0x5 + 2493 00fa 00 .byte 0 + 2494 00fb 03 .uleb128 0x3 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2529 011f 17 .uleb128 0x17 + 2530 0120 05 .uleb128 0x5 + 2531 0121 00 .byte 0 + 2532 0122 03 .uleb128 0x3 + 2533 0123 08 .uleb128 0x8 + 2534 0124 3A .uleb128 0x3a + 2535 0125 0B .uleb128 0xb + 2536 0126 3B .uleb128 0x3b + 2537 0127 0B .uleb128 0xb + 2538 0128 49 .uleb128 0x49 + 2539 0129 13 .uleb128 0x13 + 2540 012a 02 .uleb128 0x2 + 2541 012b 0A .uleb128 0xa + 2542 012c 00 .byte 0 + 2543 012d 00 .byte 0 + 2544 012e 18 .uleb128 0x18 + 2545 012f 05 .uleb128 0x5 + 2546 0130 00 .byte 0 + 2547 0131 03 .uleb128 0x3 + 2548 0132 0E .uleb128 0xe + 2549 0133 3A .uleb128 0x3a + 2550 0134 0B .uleb128 0xb + 2551 0135 3B .uleb128 0x3b + 2552 0136 0B .uleb128 0xb + 2553 0137 49 .uleb128 0x49 + 2554 0138 13 .uleb128 0x13 + 2555 0139 02 .uleb128 0x2 + 2556 013a 0A .uleb128 0xa + 2557 013b 00 .byte 0 + 2558 013c 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 46 + + + 2559 013d 19 .uleb128 0x19 + 2560 013e 2E .uleb128 0x2e + 2561 013f 01 .byte 0x1 + 2562 0140 3F .uleb128 0x3f + 2563 0141 0C .uleb128 0xc + 2564 0142 03 .uleb128 0x3 + 2565 0143 0E .uleb128 0xe + 2566 0144 3A .uleb128 0x3a + 2567 0145 0B .uleb128 0xb + 2568 0146 3B .uleb128 0x3b + 2569 0147 0B .uleb128 0xb + 2570 0148 27 .uleb128 0x27 + 2571 0149 0C .uleb128 0xc + 2572 014a 11 .uleb128 0x11 + 2573 014b 01 .uleb128 0x1 + 2574 014c 12 .uleb128 0x12 + 2575 014d 01 .uleb128 0x1 + 2576 014e 40 .uleb128 0x40 + 2577 014f 0A .uleb128 0xa + 2578 0150 9742 .uleb128 0x2117 + 2579 0152 0C .uleb128 0xc + 2580 0153 01 .uleb128 0x1 + 2581 0154 13 .uleb128 0x13 + 2582 0155 00 .byte 0 + 2583 0156 00 .byte 0 + 2584 0157 1A .uleb128 0x1a + 2585 0158 34 .uleb128 0x34 + 2586 0159 00 .byte 0 + 2587 015a 03 .uleb128 0x3 + 2588 015b 08 .uleb128 0x8 + 2589 015c 3A .uleb128 0x3a + 2590 015d 0B .uleb128 0xb + 2591 015e 3B .uleb128 0x3b + 2592 015f 0B .uleb128 0xb + 2593 0160 49 .uleb128 0x49 + 2594 0161 13 .uleb128 0x13 + 2595 0162 02 .uleb128 0x2 + 2596 0163 06 .uleb128 0x6 + 2597 0164 00 .byte 0 + 2598 0165 00 .byte 0 + 2599 0166 1B .uleb128 0x1b + 2600 0167 2E .uleb128 0x2e + 2601 0168 01 .byte 0x1 + 2602 0169 3F .uleb128 0x3f + 2603 016a 0C .uleb128 0xc + 2604 016b 03 .uleb128 0x3 + 2605 016c 0E .uleb128 0xe + 2606 016d 3A .uleb128 0x3a + 2607 016e 0B .uleb128 0xb + 2608 016f 3B .uleb128 0x3b + 2609 0170 0B .uleb128 0xb + 2610 0171 27 .uleb128 0x27 + 2611 0172 0C .uleb128 0xc + 2612 0173 49 .uleb128 0x49 + 2613 0174 13 .uleb128 0x13 + 2614 0175 11 .uleb128 0x11 + 2615 0176 01 .uleb128 0x1 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 47 + + + 2616 0177 12 .uleb128 0x12 + 2617 0178 01 .uleb128 0x1 + 2618 0179 40 .uleb128 0x40 + 2619 017a 0A .uleb128 0xa + 2620 017b 9742 .uleb128 0x2117 + 2621 017d 0C .uleb128 0xc + 2622 017e 01 .uleb128 0x1 + 2623 017f 13 .uleb128 0x13 + 2624 0180 00 .byte 0 + 2625 0181 00 .byte 0 + 2626 0182 1C .uleb128 0x1c + 2627 0183 05 .uleb128 0x5 + 2628 0184 00 .byte 0 + 2629 0185 03 .uleb128 0x3 + 2630 0186 0E .uleb128 0xe + 2631 0187 3A .uleb128 0x3a + 2632 0188 0B .uleb128 0xb + 2633 0189 3B .uleb128 0x3b + 2634 018a 0B .uleb128 0xb + 2635 018b 49 .uleb128 0x49 + 2636 018c 13 .uleb128 0x13 + 2637 018d 02 .uleb128 0x2 + 2638 018e 06 .uleb128 0x6 + 2639 018f 00 .byte 0 + 2640 0190 00 .byte 0 + 2641 0191 1D .uleb128 0x1d + 2642 0192 2E .uleb128 0x2e + 2643 0193 01 .byte 0x1 + 2644 0194 31 .uleb128 0x31 + 2645 0195 13 .uleb128 0x13 + 2646 0196 11 .uleb128 0x11 + 2647 0197 01 .uleb128 0x1 + 2648 0198 12 .uleb128 0x12 + 2649 0199 01 .uleb128 0x1 + 2650 019a 40 .uleb128 0x40 + 2651 019b 06 .uleb128 0x6 + 2652 019c 9742 .uleb128 0x2117 + 2653 019e 0C .uleb128 0xc + 2654 019f 01 .uleb128 0x1 + 2655 01a0 13 .uleb128 0x13 + 2656 01a1 00 .byte 0 + 2657 01a2 00 .byte 0 + 2658 01a3 1E .uleb128 0x1e + 2659 01a4 05 .uleb128 0x5 + 2660 01a5 00 .byte 0 + 2661 01a6 31 .uleb128 0x31 + 2662 01a7 13 .uleb128 0x13 + 2663 01a8 02 .uleb128 0x2 + 2664 01a9 06 .uleb128 0x6 + 2665 01aa 00 .byte 0 + 2666 01ab 00 .byte 0 + 2667 01ac 1F .uleb128 0x1f + 2668 01ad 1D .uleb128 0x1d + 2669 01ae 01 .byte 0x1 + 2670 01af 31 .uleb128 0x31 + 2671 01b0 13 .uleb128 0x13 + 2672 01b1 11 .uleb128 0x11 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 48 + + + 2673 01b2 01 .uleb128 0x1 + 2674 01b3 12 .uleb128 0x12 + 2675 01b4 01 .uleb128 0x1 + 2676 01b5 58 .uleb128 0x58 + 2677 01b6 0B .uleb128 0xb + 2678 01b7 59 .uleb128 0x59 + 2679 01b8 0B .uleb128 0xb + 2680 01b9 00 .byte 0 + 2681 01ba 00 .byte 0 + 2682 01bb 20 .uleb128 0x20 + 2683 01bc 0B .uleb128 0xb + 2684 01bd 01 .byte 0x1 + 2685 01be 11 .uleb128 0x11 + 2686 01bf 01 .uleb128 0x1 + 2687 01c0 12 .uleb128 0x12 + 2688 01c1 01 .uleb128 0x1 + 2689 01c2 00 .byte 0 + 2690 01c3 00 .byte 0 + 2691 01c4 21 .uleb128 0x21 + 2692 01c5 05 .uleb128 0x5 + 2693 01c6 00 .byte 0 + 2694 01c7 31 .uleb128 0x31 + 2695 01c8 13 .uleb128 0x13 + 2696 01c9 00 .byte 0 + 2697 01ca 00 .byte 0 + 2698 01cb 22 .uleb128 0x22 + 2699 01cc 898201 .uleb128 0x4109 + 2700 01cf 01 .byte 0x1 + 2701 01d0 11 .uleb128 0x11 + 2702 01d1 01 .uleb128 0x1 + 2703 01d2 31 .uleb128 0x31 + 2704 01d3 13 .uleb128 0x13 + 2705 01d4 00 .byte 0 + 2706 01d5 00 .byte 0 + 2707 01d6 23 .uleb128 0x23 + 2708 01d7 8A8201 .uleb128 0x410a + 2709 01da 00 .byte 0 + 2710 01db 02 .uleb128 0x2 + 2711 01dc 0A .uleb128 0xa + 2712 01dd 9142 .uleb128 0x2111 + 2713 01df 0A .uleb128 0xa + 2714 01e0 00 .byte 0 + 2715 01e1 00 .byte 0 + 2716 01e2 24 .uleb128 0x24 + 2717 01e3 05 .uleb128 0x5 + 2718 01e4 00 .byte 0 + 2719 01e5 03 .uleb128 0x3 + 2720 01e6 08 .uleb128 0x8 + 2721 01e7 3A .uleb128 0x3a + 2722 01e8 0B .uleb128 0xb + 2723 01e9 3B .uleb128 0x3b + 2724 01ea 0B .uleb128 0xb + 2725 01eb 49 .uleb128 0x49 + 2726 01ec 13 .uleb128 0x13 + 2727 01ed 02 .uleb128 0x2 + 2728 01ee 06 .uleb128 0x6 + 2729 01ef 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 49 + + + 2730 01f0 00 .byte 0 + 2731 01f1 25 .uleb128 0x25 + 2732 01f2 898201 .uleb128 0x4109 + 2733 01f5 01 .byte 0x1 + 2734 01f6 11 .uleb128 0x11 + 2735 01f7 01 .uleb128 0x1 + 2736 01f8 31 .uleb128 0x31 + 2737 01f9 13 .uleb128 0x13 + 2738 01fa 01 .uleb128 0x1 + 2739 01fb 13 .uleb128 0x13 + 2740 01fc 00 .byte 0 + 2741 01fd 00 .byte 0 + 2742 01fe 26 .uleb128 0x26 + 2743 01ff 898201 .uleb128 0x4109 + 2744 0202 00 .byte 0 + 2745 0203 11 .uleb128 0x11 + 2746 0204 01 .uleb128 0x1 + 2747 0205 31 .uleb128 0x31 + 2748 0206 13 .uleb128 0x13 + 2749 0207 00 .byte 0 + 2750 0208 00 .byte 0 + 2751 0209 27 .uleb128 0x27 + 2752 020a 34 .uleb128 0x34 + 2753 020b 00 .byte 0 + 2754 020c 03 .uleb128 0x3 + 2755 020d 08 .uleb128 0x8 + 2756 020e 3A .uleb128 0x3a + 2757 020f 0B .uleb128 0xb + 2758 0210 3B .uleb128 0x3b + 2759 0211 0B .uleb128 0xb + 2760 0212 49 .uleb128 0x49 + 2761 0213 13 .uleb128 0x13 + 2762 0214 02 .uleb128 0x2 + 2763 0215 0A .uleb128 0xa + 2764 0216 00 .byte 0 + 2765 0217 00 .byte 0 + 2766 0218 28 .uleb128 0x28 + 2767 0219 2E .uleb128 0x2e + 2768 021a 01 .byte 0x1 + 2769 021b 3F .uleb128 0x3f + 2770 021c 0C .uleb128 0xc + 2771 021d 03 .uleb128 0x3 + 2772 021e 0E .uleb128 0xe + 2773 021f 3A .uleb128 0x3a + 2774 0220 0B .uleb128 0xb + 2775 0221 3B .uleb128 0x3b + 2776 0222 05 .uleb128 0x5 + 2777 0223 27 .uleb128 0x27 + 2778 0224 0C .uleb128 0xc + 2779 0225 11 .uleb128 0x11 + 2780 0226 01 .uleb128 0x1 + 2781 0227 12 .uleb128 0x12 + 2782 0228 01 .uleb128 0x1 + 2783 0229 40 .uleb128 0x40 + 2784 022a 06 .uleb128 0x6 + 2785 022b 9742 .uleb128 0x2117 + 2786 022d 0C .uleb128 0xc + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 50 + + + 2787 022e 01 .uleb128 0x1 + 2788 022f 13 .uleb128 0x13 + 2789 0230 00 .byte 0 + 2790 0231 00 .byte 0 + 2791 0232 29 .uleb128 0x29 + 2792 0233 05 .uleb128 0x5 + 2793 0234 00 .byte 0 + 2794 0235 03 .uleb128 0x3 + 2795 0236 0E .uleb128 0xe + 2796 0237 3A .uleb128 0x3a + 2797 0238 0B .uleb128 0xb + 2798 0239 3B .uleb128 0x3b + 2799 023a 05 .uleb128 0x5 + 2800 023b 49 .uleb128 0x49 + 2801 023c 13 .uleb128 0x13 + 2802 023d 02 .uleb128 0x2 + 2803 023e 06 .uleb128 0x6 + 2804 023f 00 .byte 0 + 2805 0240 00 .byte 0 + 2806 0241 2A .uleb128 0x2a + 2807 0242 34 .uleb128 0x34 + 2808 0243 00 .byte 0 + 2809 0244 03 .uleb128 0x3 + 2810 0245 08 .uleb128 0x8 + 2811 0246 3A .uleb128 0x3a + 2812 0247 0B .uleb128 0xb + 2813 0248 3B .uleb128 0x3b + 2814 0249 05 .uleb128 0x5 + 2815 024a 49 .uleb128 0x49 + 2816 024b 13 .uleb128 0x13 + 2817 024c 02 .uleb128 0x2 + 2818 024d 06 .uleb128 0x6 + 2819 024e 00 .byte 0 + 2820 024f 00 .byte 0 + 2821 0250 2B .uleb128 0x2b + 2822 0251 898201 .uleb128 0x4109 + 2823 0254 01 .byte 0x1 + 2824 0255 11 .uleb128 0x11 + 2825 0256 01 .uleb128 0x1 + 2826 0257 00 .byte 0 + 2827 0258 00 .byte 0 + 2828 0259 2C .uleb128 0x2c + 2829 025a 2E .uleb128 0x2e + 2830 025b 01 .byte 0x1 + 2831 025c 3F .uleb128 0x3f + 2832 025d 0C .uleb128 0xc + 2833 025e 03 .uleb128 0x3 + 2834 025f 0E .uleb128 0xe + 2835 0260 3A .uleb128 0x3a + 2836 0261 0B .uleb128 0xb + 2837 0262 3B .uleb128 0x3b + 2838 0263 05 .uleb128 0x5 + 2839 0264 27 .uleb128 0x27 + 2840 0265 0C .uleb128 0xc + 2841 0266 49 .uleb128 0x49 + 2842 0267 13 .uleb128 0x13 + 2843 0268 11 .uleb128 0x11 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 51 + + + 2844 0269 01 .uleb128 0x1 + 2845 026a 12 .uleb128 0x12 + 2846 026b 01 .uleb128 0x1 + 2847 026c 40 .uleb128 0x40 + 2848 026d 06 .uleb128 0x6 + 2849 026e 9742 .uleb128 0x2117 + 2850 0270 0C .uleb128 0xc + 2851 0271 01 .uleb128 0x1 + 2852 0272 13 .uleb128 0x13 + 2853 0273 00 .byte 0 + 2854 0274 00 .byte 0 + 2855 0275 2D .uleb128 0x2d + 2856 0276 34 .uleb128 0x34 + 2857 0277 00 .byte 0 + 2858 0278 03 .uleb128 0x3 + 2859 0279 08 .uleb128 0x8 + 2860 027a 3A .uleb128 0x3a + 2861 027b 0B .uleb128 0xb + 2862 027c 3B .uleb128 0x3b + 2863 027d 05 .uleb128 0x5 + 2864 027e 49 .uleb128 0x49 + 2865 027f 13 .uleb128 0x13 + 2866 0280 02 .uleb128 0x2 + 2867 0281 0A .uleb128 0xa + 2868 0282 00 .byte 0 + 2869 0283 00 .byte 0 + 2870 0284 2E .uleb128 0x2e + 2871 0285 34 .uleb128 0x34 + 2872 0286 00 .byte 0 + 2873 0287 03 .uleb128 0x3 + 2874 0288 0E .uleb128 0xe + 2875 0289 3A .uleb128 0x3a + 2876 028a 0B .uleb128 0xb + 2877 028b 3B .uleb128 0x3b + 2878 028c 0B .uleb128 0xb + 2879 028d 49 .uleb128 0x49 + 2880 028e 13 .uleb128 0x13 + 2881 028f 3F .uleb128 0x3f + 2882 0290 0C .uleb128 0xc + 2883 0291 3C .uleb128 0x3c + 2884 0292 0C .uleb128 0xc + 2885 0293 00 .byte 0 + 2886 0294 00 .byte 0 + 2887 0295 2F .uleb128 0x2f + 2888 0296 2E .uleb128 0x2e + 2889 0297 01 .byte 0x1 + 2890 0298 3F .uleb128 0x3f + 2891 0299 0C .uleb128 0xc + 2892 029a 03 .uleb128 0x3 + 2893 029b 0E .uleb128 0xe + 2894 029c 3A .uleb128 0x3a + 2895 029d 0B .uleb128 0xb + 2896 029e 3B .uleb128 0x3b + 2897 029f 0B .uleb128 0xb + 2898 02a0 27 .uleb128 0x27 + 2899 02a1 0C .uleb128 0xc + 2900 02a2 49 .uleb128 0x49 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 52 + + + 2901 02a3 13 .uleb128 0x13 + 2902 02a4 3C .uleb128 0x3c + 2903 02a5 0C .uleb128 0xc + 2904 02a6 01 .uleb128 0x1 + 2905 02a7 13 .uleb128 0x13 + 2906 02a8 00 .byte 0 + 2907 02a9 00 .byte 0 + 2908 02aa 30 .uleb128 0x30 + 2909 02ab 2E .uleb128 0x2e + 2910 02ac 00 .byte 0 + 2911 02ad 3F .uleb128 0x3f + 2912 02ae 0C .uleb128 0xc + 2913 02af 03 .uleb128 0x3 + 2914 02b0 0E .uleb128 0xe + 2915 02b1 3A .uleb128 0x3a + 2916 02b2 0B .uleb128 0xb + 2917 02b3 3B .uleb128 0x3b + 2918 02b4 0B .uleb128 0xb + 2919 02b5 27 .uleb128 0x27 + 2920 02b6 0C .uleb128 0xc + 2921 02b7 3C .uleb128 0x3c + 2922 02b8 0C .uleb128 0xc + 2923 02b9 00 .byte 0 + 2924 02ba 00 .byte 0 + 2925 02bb 31 .uleb128 0x31 + 2926 02bc 2E .uleb128 0x2e + 2927 02bd 01 .byte 0x1 + 2928 02be 3F .uleb128 0x3f + 2929 02bf 0C .uleb128 0xc + 2930 02c0 03 .uleb128 0x3 + 2931 02c1 0E .uleb128 0xe + 2932 02c2 3A .uleb128 0x3a + 2933 02c3 0B .uleb128 0xb + 2934 02c4 3B .uleb128 0x3b + 2935 02c5 0B .uleb128 0xb + 2936 02c6 27 .uleb128 0x27 + 2937 02c7 0C .uleb128 0xc + 2938 02c8 3C .uleb128 0x3c + 2939 02c9 0C .uleb128 0xc + 2940 02ca 01 .uleb128 0x1 + 2941 02cb 13 .uleb128 0x13 + 2942 02cc 00 .byte 0 + 2943 02cd 00 .byte 0 + 2944 02ce 32 .uleb128 0x32 + 2945 02cf 2E .uleb128 0x2e + 2946 02d0 01 .byte 0x1 + 2947 02d1 3F .uleb128 0x3f + 2948 02d2 0C .uleb128 0xc + 2949 02d3 03 .uleb128 0x3 + 2950 02d4 0E .uleb128 0xe + 2951 02d5 3A .uleb128 0x3a + 2952 02d6 0B .uleb128 0xb + 2953 02d7 3B .uleb128 0x3b + 2954 02d8 0B .uleb128 0xb + 2955 02d9 27 .uleb128 0x27 + 2956 02da 0C .uleb128 0xc + 2957 02db 49 .uleb128 0x49 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 53 + + + 2958 02dc 13 .uleb128 0x13 + 2959 02dd 3C .uleb128 0x3c + 2960 02de 0C .uleb128 0xc + 2961 02df 00 .byte 0 + 2962 02e0 00 .byte 0 + 2963 02e1 00 .byte 0 + 2964 .section .debug_loc,"",%progbits + 2965 .Ldebug_loc0: + 2966 .LLST0: + 2967 0000 00000000 .4byte .LFB7 + 2968 0004 02000000 .4byte .LCFI0 + 2969 0008 0200 .2byte 0x2 + 2970 000a 7D .byte 0x7d + 2971 000b 00 .sleb128 0 + 2972 000c 02000000 .4byte .LCFI0 + 2973 0010 1E000000 .4byte .LFE7 + 2974 0014 0200 .2byte 0x2 + 2975 0016 7D .byte 0x7d + 2976 0017 04 .sleb128 4 + 2977 0018 00000000 .4byte 0 + 2978 001c 00000000 .4byte 0 + 2979 .LLST1: + 2980 0020 00000000 .4byte .LVL1 + 2981 0024 06000000 .4byte .LVL2 + 2982 0028 0100 .2byte 0x1 + 2983 002a 50 .byte 0x50 + 2984 002b 06000000 .4byte .LVL2 + 2985 002f 1A000000 .4byte .LFE8 + 2986 0033 0100 .2byte 0x1 + 2987 0035 52 .byte 0x52 + 2988 0036 00000000 .4byte 0 + 2989 003a 00000000 .4byte 0 + 2990 .LLST2: + 2991 003e 00000000 .4byte .LVL4 + 2992 0042 18000000 .4byte .LVL6 + 2993 0046 0100 .2byte 0x1 + 2994 0048 50 .byte 0x50 + 2995 0049 18000000 .4byte .LVL6 + 2996 004d 1A000000 .4byte .LFE9 + 2997 0051 0400 .2byte 0x4 + 2998 0053 F3 .byte 0xf3 + 2999 0054 01 .uleb128 0x1 + 3000 0055 50 .byte 0x50 + 3001 0056 9F .byte 0x9f + 3002 0057 00000000 .4byte 0 + 3003 005b 00000000 .4byte 0 + 3004 .LLST3: + 3005 005f 0E000000 .4byte .LVL5 + 3006 0063 18000000 .4byte .LVL6 + 3007 0067 0600 .2byte 0x6 + 3008 0069 70 .byte 0x70 + 3009 006a 00 .sleb128 0 + 3010 006b 73 .byte 0x73 + 3011 006c 00 .sleb128 0 + 3012 006d 1A .byte 0x1a + 3013 006e 9F .byte 0x9f + 3014 006f 18000000 .4byte .LVL6 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 54 + + + 3015 0073 1A000000 .4byte .LFE9 + 3016 0077 0100 .2byte 0x1 + 3017 0079 50 .byte 0x50 + 3018 007a 00000000 .4byte 0 + 3019 007e 00000000 .4byte 0 + 3020 .LLST4: + 3021 0082 00000000 .4byte .LVL7 + 3022 0086 10000000 .4byte .LVL8 + 3023 008a 0100 .2byte 0x1 + 3024 008c 50 .byte 0x50 + 3025 008d 10000000 .4byte .LVL8 + 3026 0091 12000000 .4byte .LVL9 + 3027 0095 0400 .2byte 0x4 + 3028 0097 F3 .byte 0xf3 + 3029 0098 01 .uleb128 0x1 + 3030 0099 50 .byte 0x50 + 3031 009a 9F .byte 0x9f + 3032 009b 12000000 .4byte .LVL9 + 3033 009f 16000000 .4byte .LFE10 + 3034 00a3 0100 .2byte 0x1 + 3035 00a5 50 .byte 0x50 + 3036 00a6 00000000 .4byte 0 + 3037 00aa 00000000 .4byte 0 + 3038 .LLST5: + 3039 00ae 00000000 .4byte .LFB12 + 3040 00b2 02000000 .4byte .LCFI1 + 3041 00b6 0200 .2byte 0x2 + 3042 00b8 7D .byte 0x7d + 3043 00b9 00 .sleb128 0 + 3044 00ba 02000000 .4byte .LCFI1 + 3045 00be 2E000000 .4byte .LFE12 + 3046 00c2 0200 .2byte 0x2 + 3047 00c4 7D .byte 0x7d + 3048 00c5 08 .sleb128 8 + 3049 00c6 00000000 .4byte 0 + 3050 00ca 00000000 .4byte 0 + 3051 .LLST6: + 3052 00ce 00000000 .4byte .LVL10 + 3053 00d2 1F000000 .4byte .LVL13-1 + 3054 00d6 0100 .2byte 0x1 + 3055 00d8 50 .byte 0x50 + 3056 00d9 1F000000 .4byte .LVL13-1 + 3057 00dd 26000000 .4byte .LVL14 + 3058 00e1 0400 .2byte 0x4 + 3059 00e3 F3 .byte 0xf3 + 3060 00e4 01 .uleb128 0x1 + 3061 00e5 50 .byte 0x50 + 3062 00e6 9F .byte 0x9f + 3063 00e7 26000000 .4byte .LVL14 + 3064 00eb 2E000000 .4byte .LFE12 + 3065 00ef 0100 .2byte 0x1 + 3066 00f1 50 .byte 0x50 + 3067 00f2 00000000 .4byte 0 + 3068 00f6 00000000 .4byte 0 + 3069 .LLST7: + 3070 00fa 00000000 .4byte .LVL10 + 3071 00fe 08000000 .4byte .LVL11 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 55 + + + 3072 0102 0100 .2byte 0x1 + 3073 0104 51 .byte 0x51 + 3074 0105 08000000 .4byte .LVL11 + 3075 0109 2E000000 .4byte .LFE12 + 3076 010d 0400 .2byte 0x4 + 3077 010f F3 .byte 0xf3 + 3078 0110 01 .uleb128 0x1 + 3079 0111 51 .byte 0x51 + 3080 0112 9F .byte 0x9f + 3081 0113 00000000 .4byte 0 + 3082 0117 00000000 .4byte 0 + 3083 .LLST8: + 3084 011b 1C000000 .4byte .LVL12 + 3085 011f 1F000000 .4byte .LVL13-1 + 3086 0123 0100 .2byte 0x1 + 3087 0125 50 .byte 0x50 + 3088 0126 1F000000 .4byte .LVL13-1 + 3089 012a 26000000 .4byte .LVL14 + 3090 012e 0400 .2byte 0x4 + 3091 0130 F3 .byte 0xf3 + 3092 0131 01 .uleb128 0x1 + 3093 0132 50 .byte 0x50 + 3094 0133 9F .byte 0x9f + 3095 0134 00000000 .4byte 0 + 3096 0138 00000000 .4byte 0 + 3097 .LLST9: + 3098 013c 00000000 .4byte .LFB11 + 3099 0140 02000000 .4byte .LCFI2 + 3100 0144 0200 .2byte 0x2 + 3101 0146 7D .byte 0x7d + 3102 0147 00 .sleb128 0 + 3103 0148 02000000 .4byte .LCFI2 + 3104 014c 10000000 .4byte .LFE11 + 3105 0150 0200 .2byte 0x2 + 3106 0152 7D .byte 0x7d + 3107 0153 08 .sleb128 8 + 3108 0154 00000000 .4byte 0 + 3109 0158 00000000 .4byte 0 + 3110 .LLST10: + 3111 015c 00000000 .4byte .LVL15 + 3112 0160 07000000 .4byte .LVL16-1 + 3113 0164 0100 .2byte 0x1 + 3114 0166 50 .byte 0x50 + 3115 0167 07000000 .4byte .LVL16-1 + 3116 016b 10000000 .4byte .LFE11 + 3117 016f 0400 .2byte 0x4 + 3118 0171 F3 .byte 0xf3 + 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05e7 F3 .byte 0xf3 + 3584 05e8 01 .uleb128 0x1 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 64 + + + 3585 05e9 50 .byte 0x50 + 3586 05ea 9F .byte 0x9f + 3587 05eb 00000000 .4byte 0 + 3588 05ef 00000000 .4byte 0 + 3589 .LLST40: + 3590 05f3 00000000 .4byte .LVL71 + 3591 05f7 23000000 .4byte .LVL76-1 + 3592 05fb 0100 .2byte 0x1 + 3593 05fd 51 .byte 0x51 + 3594 05fe 23000000 .4byte .LVL76-1 + 3595 0602 40000000 .4byte .LFE21 + 3596 0606 0400 .2byte 0x4 + 3597 0608 F3 .byte 0xf3 + 3598 0609 01 .uleb128 0x1 + 3599 060a 51 .byte 0x51 + 3600 060b 9F .byte 0x9f + 3601 060c 00000000 .4byte 0 + 3602 0610 00000000 .4byte 0 + 3603 .section .debug_aranges,"",%progbits + 3604 0000 8C000000 .4byte 0x8c + 3605 0004 0200 .2byte 0x2 + 3606 0006 00000000 .4byte .Ldebug_info0 + 3607 000a 04 .byte 0x4 + 3608 000b 00 .byte 0 + 3609 000c 0000 .2byte 0 + 3610 000e 0000 .2byte 0 + 3611 0010 00000000 .4byte .LFB7 + 3612 0014 1E000000 .4byte .LFE7-.LFB7 + 3613 0018 00000000 .4byte .LFB8 + 3614 001c 1A000000 .4byte .LFE8-.LFB8 + 3615 0020 00000000 .4byte .LFB9 + 3616 0024 1A000000 .4byte .LFE9-.LFB9 + 3617 0028 00000000 .4byte .LFB10 + 3618 002c 16000000 .4byte .LFE10-.LFB10 + 3619 0030 00000000 .4byte .LFB12 + 3620 0034 2E000000 .4byte .LFE12-.LFB12 + 3621 0038 00000000 .4byte .LFB11 + 3622 003c 10000000 .4byte .LFE11-.LFB11 + 3623 0040 00000000 .4byte .LFB14 + 3624 0044 1E000000 .4byte .LFE14-.LFB14 + 3625 0048 00000000 .4byte .LFB13 + 3626 004c 10000000 .4byte .LFE13-.LFB13 + 3627 0050 00000000 .4byte .LFB15 + 3628 0054 2E000000 .4byte .LFE15-.LFB15 + 3629 0058 00000000 .4byte .LFB16 + 3630 005c 34000000 .4byte .LFE16-.LFB16 + 3631 0060 00000000 .4byte .LFB17 + 3632 0064 2C000000 .4byte .LFE17-.LFB17 + 3633 0068 00000000 .4byte .LFB18 + 3634 006c 30000000 .4byte .LFE18-.LFB18 + 3635 0070 00000000 .4byte .LFB19 + 3636 0074 3C000000 .4byte .LFE19-.LFB19 + 3637 0078 00000000 .4byte .LFB20 + 3638 007c 38000000 .4byte .LFE20-.LFB20 + 3639 0080 00000000 .4byte .LFB21 + 3640 0084 40000000 .4byte .LFE21-.LFB21 + 3641 0088 00000000 .4byte 0 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 65 + + + 3642 008c 00000000 .4byte 0 + 3643 .section .debug_ranges,"",%progbits + 3644 .Ldebug_ranges0: + 3645 0000 00000000 .4byte .LFB7 + 3646 0004 1E000000 .4byte .LFE7 + 3647 0008 00000000 .4byte .LFB8 + 3648 000c 1A000000 .4byte .LFE8 + 3649 0010 00000000 .4byte .LFB9 + 3650 0014 1A000000 .4byte .LFE9 + 3651 0018 00000000 .4byte .LFB10 + 3652 001c 16000000 .4byte .LFE10 + 3653 0020 00000000 .4byte .LFB12 + 3654 0024 2E000000 .4byte .LFE12 + 3655 0028 00000000 .4byte .LFB11 + 3656 002c 10000000 .4byte .LFE11 + 3657 0030 00000000 .4byte .LFB14 + 3658 0034 1E000000 .4byte .LFE14 + 3659 0038 00000000 .4byte .LFB13 + 3660 003c 10000000 .4byte .LFE13 + 3661 0040 00000000 .4byte .LFB15 + 3662 0044 2E000000 .4byte .LFE15 + 3663 0048 00000000 .4byte .LFB16 + 3664 004c 34000000 .4byte .LFE16 + 3665 0050 00000000 .4byte .LFB17 + 3666 0054 2C000000 .4byte .LFE17 + 3667 0058 00000000 .4byte .LFB18 + 3668 005c 30000000 .4byte .LFE18 + 3669 0060 00000000 .4byte .LFB19 + 3670 0064 3C000000 .4byte .LFE19 + 3671 0068 00000000 .4byte .LFB20 + 3672 006c 38000000 .4byte .LFE20 + 3673 0070 00000000 .4byte .LFB21 + 3674 0074 40000000 .4byte .LFE21 + 3675 0078 00000000 .4byte 0 + 3676 007c 00000000 .4byte 0 + 3677 .section .debug_line,"",%progbits + 3678 .Ldebug_line0: + 3679 0000 B2020000 .section .debug_str,"MS",%progbits,1 + 3679 02000701 + 3679 00000201 + 3679 FB0E0D00 + 3679 01010101 + 3680 .LASF35: + 3681 0000 705F6D73 .ascii "p_msg\000" + 3681 6700 + 3682 .LASF65: + 3683 0006 7264796D .ascii "rdymsg\000" + 3683 736700 + 3684 .LASF11: + 3685 000d 6C6F6E67 .ascii "long long unsigned int\000" + 3685 206C6F6E + 3685 6720756E + 3685 7369676E + 3685 65642069 + 3686 .LASF66: + 3687 0024 65786974 .ascii "exitcode\000" + 3687 636F6465 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 66 + + + 3687 00 + 3688 .LASF87: + 3689 002d 63684576 .ascii "chEvtSignalFlagsI\000" + 3689 74536967 + 3689 6E616C46 + 3689 6C616773 + 3689 4900 + 3690 .LASF85: + 3691 003f 63684576 .ascii "chEvtWaitAnyTimeout\000" + 3691 74576169 + 3691 74416E79 + 3691 54696D65 + 3691 6F757400 + 3692 .LASF24: + 3693 0053 705F7072 .ascii "p_prio\000" + 3693 696F00 + 3694 .LASF10: + 3695 005a 6C6F6E67 .ascii "long long int\000" + 3695 206C6F6E + 3695 6720696E + 3695 7400 + 3696 .LASF1: + 3697 0068 7369676E .ascii "signed char\000" + 3697 65642063 + 3697 68617200 + 3698 .LASF86: + 3699 0074 63684576 .ascii "chEvtWaitAllTimeout\000" + 3699 74576169 + 3699 74416C6C + 3699 54696D65 + 3699 6F757400 + 3700 .LASF39: + 3701 0088 705F6D70 .ascii "p_mpool\000" + 3701 6F6F6C00 + 3702 .LASF55: + 3703 0090 6D5F7175 .ascii "m_queue\000" + 3703 65756500 + 3704 .LASF74: + 3705 0098 63684576 .ascii "chEvtAddFlags\000" + 3705 74416464 + 3705 466C6167 + 3705 7300 + 3706 .LASF7: + 3707 00a6 6C6F6E67 .ascii "long int\000" + 3707 20696E74 + 3707 00 + 3708 .LASF13: + 3709 00af 74737461 .ascii "tstate_t\000" + 3709 74655F74 + 3709 00 + 3710 .LASF82: + 3711 00b8 63684576 .ascii "chEvtWaitAll\000" + 3711 74576169 + 3711 74416C6C + 3711 00 + 3712 .LASF81: + 3713 00c5 63684576 .ascii "chEvtWaitAny\000" + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 67 + + + 3713 74576169 + 3713 74416E79 + 3713 00 + 3714 .LASF76: + 3715 00d2 63684576 .ascii "chEvtBroadcastFlagsI\000" + 3715 7442726F + 3715 61646361 + 3715 7374466C + 3715 61677349 + 3716 .LASF26: + 3717 00e7 705F6E65 .ascii "p_newer\000" + 3717 77657200 + 3718 .LASF95: + 3719 00ef 63685363 .ascii "chSchRescheduleS\000" + 3719 68526573 + 3719 63686564 + 3719 756C6553 + 3719 00 + 3720 .LASF49: + 3721 0100 725F6E65 .ascii "r_newer\000" + 3721 77657200 + 3722 .LASF70: + 3723 0108 6D61736B .ascii "mask\000" + 3723 00 + 3724 .LASF42: + 3725 010d 72656761 .ascii "regarm_t\000" + 3725 726D5F74 + 3725 00 + 3726 .LASF77: + 3727 0116 63684576 .ascii "chEvtBroadcastFlags\000" + 3727 7442726F + 3727 61646361 + 3727 7374466C + 3727 61677300 + 3728 .LASF17: + 3729 012a 6576656E .ascii "eventid_t\000" + 3729 7469645F + 3729 7400 + 3730 .LASF62: + 3731 0134 4576656E .ascii "EventSource\000" + 3731 74536F75 + 3731 72636500 + 3732 .LASF64: + 3733 0140 65766861 .ascii "evhandler_t\000" + 3733 6E646C65 + 3733 725F7400 + 3734 .LASF20: + 3735 014c 636E745F .ascii "cnt_t\000" + 3735 7400 + 3736 .LASF75: + 3737 0152 63684576 .ascii "chEvtSignalFlags\000" + 3737 74536967 + 3737 6E616C46 + 3737 6C616773 + 3737 00 + 3738 .LASF0: + 3739 0163 756E7369 .ascii "unsigned int\000" + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 68 + + + 3739 676E6564 + 3739 20696E74 + 3739 00 + 3740 .LASF9: + 3741 0170 6C6F6E67 .ascii "long unsigned int\000" + 3741 20756E73 + 3741 69676E65 + 3741 6420696E + 3741 7400 + 3742 .LASF44: + 3743 0182 636F6E74 .ascii "context\000" + 3743 65787400 + 3744 .LASF4: + 3745 018a 73686F72 .ascii "short unsigned int\000" + 3745 7420756E + 3745 7369676E + 3745 65642069 + 3745 6E7400 + 3746 .LASF71: + 3747 019d 63684576 .ascii "chEvtRegisterMask\000" + 3747 74526567 + 3747 69737465 + 3747 724D6173 + 3747 6B00 + 3748 .LASF16: + 3749 01af 6D73675F .ascii "msg_t\000" + 3749 7400 + 3750 .LASF59: + 3751 01b5 656C5F6E .ascii "el_next\000" + 3751 65787400 + 3752 .LASF72: + 3753 01bd 63684576 .ascii "chEvtUnregister\000" + 3753 74556E72 + 3753 65676973 + 3753 74657200 + 3754 .LASF12: + 3755 01cd 746D6F64 .ascii "tmode_t\000" + 3755 655F7400 + 3756 .LASF41: + 3757 01d5 54687265 .ascii "ThreadsList\000" + 3757 6164734C + 3757 69737400 + 3758 .LASF18: + 3759 01e1 6576656E .ascii "eventmask_t\000" + 3759 746D6173 + 3759 6B5F7400 + 3760 .LASF54: + 3761 01ed 4D757465 .ascii "Mutex\000" + 3761 7800 + 3762 .LASF45: + 3763 01f3 73697A65 .ascii "sizetype\000" + 3763 74797065 + 3763 00 + 3764 .LASF78: + 3765 01fc 63684576 .ascii "chEvtDispatch\000" + 3765 74446973 + 3765 70617463 + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 69 + + + 3765 6800 + 3766 .LASF27: + 3767 020a 705F6F6C .ascii "p_older\000" + 3767 64657200 + 3768 .LASF92: + 3769 0212 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 3769 73657273 + 3769 5C496D61 + 3769 6E6F6C5C + 3769 64657665 + 3770 023f 6C696361 .ascii "lications\\smartcities\000" + 3770 74696F6E + 3770 735C736D + 3770 61727463 + 3770 69746965 + 3771 .LASF40: + 3772 0255 54687265 .ascii "ThreadsQueue\000" + 3772 61647351 + 3772 75657565 + 3772 00 + 3773 .LASF84: + 3774 0262 74696D65 .ascii "time\000" + 3774 00 + 3775 .LASF90: + 3776 0267 474E5520 .ascii "GNU C 4.7.2\000" + 3776 4320342E + 3776 372E3200 + 3777 .LASF52: + 3778 0273 725F6375 .ascii "r_current\000" + 3778 7272656E + 3778 7400 + 3779 .LASF50: + 3780 027d 725F6F6C .ascii "r_older\000" + 3780 64657200 + 3781 .LASF61: + 3782 0285 656C5F6D .ascii "el_mask\000" + 3782 61736B00 + 3783 .LASF91: + 3784 028d 2E2E2F2E .ascii "../..//os/kernel/src/chevents.c\000" + 3784 2E2F2F6F + 3784 732F6B65 + 3784 726E656C + 3784 2F737263 + 3785 .LASF79: + 3786 02ad 68616E64 .ascii "handlers\000" + 3786 6C657273 + 3786 00 + 3787 .LASF14: + 3788 02b6 74726566 .ascii "trefs_t\000" + 3788 735F7400 + 3789 .LASF23: + 3790 02be 705F7072 .ascii "p_prev\000" + 3790 657600 + 3791 .LASF15: + 3792 02c5 74707269 .ascii "tprio_t\000" + 3792 6F5F7400 + 3793 .LASF73: + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 70 + + + 3794 02cd 63684576 .ascii "chEvtClearFlags\000" + 3794 74436C65 + 3794 6172466C + 3794 61677300 + 3795 .LASF6: + 3796 02dd 696E7433 .ascii "int32_t\000" + 3796 325F7400 + 3797 .LASF2: + 3798 02e5 756E7369 .ascii "unsigned char\000" + 3798 676E6564 + 3798 20636861 + 3798 7200 + 3799 .LASF80: + 3800 02f3 63684576 .ascii "chEvtWaitOne\000" + 3800 74576169 + 3800 744F6E65 + 3800 00 + 3801 .LASF60: + 3802 0300 656C5F6C .ascii "el_listener\000" + 3802 69737465 + 3802 6E657200 + 3803 .LASF37: + 3804 030c 705F6D74 .ascii "p_mtxlist\000" + 3804 786C6973 + 3804 7400 + 3805 .LASF3: + 3806 0316 73686F72 .ascii "short int\000" + 3806 7420696E + 3806 7400 + 3807 .LASF29: + 3808 0320 705F7374 .ascii "p_state\000" + 3808 61746500 + 3809 .LASF47: + 3810 0328 725F7072 .ascii "r_prio\000" + 3810 696F00 + 3811 .LASF68: + 3812 032f 65776D61 .ascii "ewmask\000" + 3812 736B00 + 3813 .LASF22: + 3814 0336 705F6E65 .ascii "p_next\000" + 3814 787400 + 3815 .LASF30: + 3816 033d 705F666C .ascii "p_flags\000" + 3816 61677300 + 3817 .LASF21: + 3818 0345 54687265 .ascii "Thread\000" + 3818 616400 + 3819 .LASF88: + 3820 034c 63685363 .ascii "chSchGoSleepS\000" + 3820 68476F53 + 3820 6C656570 + 3820 5300 + 3821 .LASF36: + 3822 035a 705F6570 .ascii "p_epending\000" + 3822 656E6469 + 3822 6E6700 + 3823 .LASF8: + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 71 + + + 3824 0365 75696E74 .ascii "uint32_t\000" + 3824 33325F74 + 3824 00 + 3825 .LASF46: + 3826 036e 725F7175 .ascii "r_queue\000" + 3826 65756500 + 3827 .LASF94: + 3828 0376 63685363 .ascii "chSchReadyI\000" + 3828 68526561 + 3828 64794900 + 3829 .LASF69: + 3830 0382 63686172 .ascii "char\000" + 3830 00 + 3831 .LASF57: + 3832 0387 6D5F6E65 .ascii "m_next\000" + 3832 787400 + 3833 .LASF19: + 3834 038e 73797374 .ascii "systime_t\000" + 3834 696D655F + 3834 7400 + 3835 .LASF38: + 3836 0398 705F7265 .ascii "p_realprio\000" + 3836 616C7072 + 3836 696F00 + 3837 .LASF32: + 3838 03a3 705F7469 .ascii "p_time\000" + 3838 6D6500 + 3839 .LASF48: + 3840 03aa 725F6374 .ascii "r_ctx\000" + 3840 7800 + 3841 .LASF43: + 3842 03b0 696E7463 .ascii "intctx\000" + 3842 747800 + 3843 .LASF34: + 3844 03b7 705F6D73 .ascii "p_msgqueue\000" + 3844 67717565 + 3844 756500 + 3845 .LASF31: + 3846 03c2 705F7265 .ascii "p_refs\000" + 3846 667300 + 3847 .LASF53: + 3848 03c9 52656164 .ascii "ReadyList\000" + 3848 794C6973 + 3848 7400 + 3849 .LASF93: + 3850 03d3 726C6973 .ascii "rlist\000" + 3850 7400 + 3851 .LASF5: + 3852 03d9 75696E74 .ascii "uint8_t\000" + 3852 385F7400 + 3853 .LASF58: + 3854 03e1 4576656E .ascii "EventListener\000" + 3854 744C6973 + 3854 74656E65 + 3854 7200 + 3855 .LASF83: + 3856 03ef 63684576 .ascii "chEvtWaitOneTimeout\000" + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 72 + + + 3856 74576169 + 3856 744F6E65 + 3856 54696D65 + 3856 6F757400 + 3857 .LASF67: + 3858 0403 77746F62 .ascii "wtobjp\000" + 3858 6A7000 + 3859 .LASF28: + 3860 040a 705F6E61 .ascii "p_name\000" + 3860 6D6500 + 3861 .LASF63: + 3862 0411 65735F6E .ascii "es_next\000" + 3862 65787400 + 3863 .LASF89: + 3864 0419 63685363 .ascii "chSchGoSleepTimeoutS\000" + 3864 68476F53 + 3864 6C656570 + 3864 54696D65 + 3864 6F757453 + 3865 .LASF51: + 3866 042e 725F7072 .ascii "r_preempt\000" + 3866 65656D70 + 3866 7400 + 3867 .LASF56: + 3868 0438 6D5F6F77 .ascii "m_owner\000" + 3868 6E657200 + 3869 .LASF25: + 3870 0440 705F6374 .ascii "p_ctx\000" + 3870 7800 + 3871 .LASF33: + 3872 0446 705F7761 .ascii "p_waiting\000" + 3872 6974696E + 3872 6700 + 3873 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\ccDEkqGh.s page 73 + + +DEFINED SYMBOLS + *ABS*:00000000 chevents.c +C:\cygwin\tmp\ccDEkqGh.s:19 .text.chEvtRegisterMask:00000000 $t +C:\cygwin\tmp\ccDEkqGh.s:25 .text.chEvtRegisterMask:00000000 chEvtRegisterMask +C:\cygwin\tmp\ccDEkqGh.s:70 .text.chEvtUnregister:00000000 $t +C:\cygwin\tmp\ccDEkqGh.s:76 .text.chEvtUnregister:00000000 chEvtUnregister +C:\cygwin\tmp\ccDEkqGh.s:120 .text.chEvtClearFlags:00000000 $t +C:\cygwin\tmp\ccDEkqGh.s:126 .text.chEvtClearFlags:00000000 chEvtClearFlags +C:\cygwin\tmp\ccDEkqGh.s:161 .text.chEvtAddFlags:00000000 $t +C:\cygwin\tmp\ccDEkqGh.s:167 .text.chEvtAddFlags:00000000 chEvtAddFlags +C:\cygwin\tmp\ccDEkqGh.s:200 .text.chEvtSignalFlagsI:00000000 $t +C:\cygwin\tmp\ccDEkqGh.s:206 .text.chEvtSignalFlagsI:00000000 chEvtSignalFlagsI +C:\cygwin\tmp\ccDEkqGh.s:267 .text.chEvtSignalFlags:00000000 $t +C:\cygwin\tmp\ccDEkqGh.s:273 .text.chEvtSignalFlags:00000000 chEvtSignalFlags +C:\cygwin\tmp\ccDEkqGh.s:306 .text.chEvtBroadcastFlagsI:00000000 $t +C:\cygwin\tmp\ccDEkqGh.s:312 .text.chEvtBroadcastFlagsI:00000000 chEvtBroadcastFlagsI +C:\cygwin\tmp\ccDEkqGh.s:357 .text.chEvtBroadcastFlags:00000000 $t +C:\cygwin\tmp\ccDEkqGh.s:363 .text.chEvtBroadcastFlags:00000000 chEvtBroadcastFlags +C:\cygwin\tmp\ccDEkqGh.s:396 .text.chEvtDispatch:00000000 $t +C:\cygwin\tmp\ccDEkqGh.s:402 .text.chEvtDispatch:00000000 chEvtDispatch +C:\cygwin\tmp\ccDEkqGh.s:462 .text.chEvtWaitOne:00000000 $t +C:\cygwin\tmp\ccDEkqGh.s:468 .text.chEvtWaitOne:00000000 chEvtWaitOne +C:\cygwin\tmp\ccDEkqGh.s:529 .text.chEvtWaitOne:00000030 $d +C:\cygwin\tmp\ccDEkqGh.s:534 .text.chEvtWaitAny:00000000 $t +C:\cygwin\tmp\ccDEkqGh.s:540 .text.chEvtWaitAny:00000000 chEvtWaitAny +C:\cygwin\tmp\ccDEkqGh.s:598 .text.chEvtWaitAny:00000028 $d +C:\cygwin\tmp\ccDEkqGh.s:603 .text.chEvtWaitAll:00000000 $t +C:\cygwin\tmp\ccDEkqGh.s:609 .text.chEvtWaitAll:00000000 chEvtWaitAll +C:\cygwin\tmp\ccDEkqGh.s:663 .text.chEvtWaitAll:0000002c $d +C:\cygwin\tmp\ccDEkqGh.s:668 .text.chEvtWaitOneTimeout:00000000 $t +C:\cygwin\tmp\ccDEkqGh.s:674 .text.chEvtWaitOneTimeout:00000000 chEvtWaitOneTimeout +C:\cygwin\tmp\ccDEkqGh.s:746 .text.chEvtWaitOneTimeout:00000038 $d +C:\cygwin\tmp\ccDEkqGh.s:751 .text.chEvtWaitAnyTimeout:00000000 $t +C:\cygwin\tmp\ccDEkqGh.s:757 .text.chEvtWaitAnyTimeout:00000000 chEvtWaitAnyTimeout +C:\cygwin\tmp\ccDEkqGh.s:825 .text.chEvtWaitAnyTimeout:00000034 $d +C:\cygwin\tmp\ccDEkqGh.s:830 .text.chEvtWaitAllTimeout:00000000 $t +C:\cygwin\tmp\ccDEkqGh.s:836 .text.chEvtWaitAllTimeout:00000000 chEvtWaitAllTimeout +C:\cygwin\tmp\ccDEkqGh.s:921 .text.chEvtWaitAllTimeout:0000003c $d + .debug_frame:00000010 $d +C:\cygwin\tmp\ccDEkqGh.s:533 .text.chEvtWaitOne:00000034 $t +C:\cygwin\tmp\ccDEkqGh.s:602 .text.chEvtWaitAny:0000002c $t +C:\cygwin\tmp\ccDEkqGh.s:750 .text.chEvtWaitOneTimeout:0000003c $t +C:\cygwin\tmp\ccDEkqGh.s:829 .text.chEvtWaitAnyTimeout:00000038 $t + +UNDEFINED SYMBOLS +rlist +chSchReadyI +chSchRescheduleS +chSchGoSleepS +chSchGoSleepTimeoutS diff --git a/Project/applications/smartcities/build/lst/chheap.lst b/Project/applications/smartcities/build/lst/chheap.lst new file mode 100644 index 0000000..ccf5d59 --- /dev/null +++ b/Project/applications/smartcities/build/lst/chheap.lst @@ -0,0 +1,3102 @@ +ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "chheap.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text._heap_init,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .global _heap_init + 22 .thumb + 23 .thumb_func + 24 .type _heap_init, %function + 25 _heap_init: + 26 .LFB7: + 27 .file 1 "../..//os/kernel/src/chheap.c" + 28 .loc 1 75 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .loc 1 76 0 + 34 0000 40F20003 movw r3, #:lower16:.LANCHOR0 + 35 0004 C0F20003 movt r3, #:upper16:.LANCHOR0 + 36 0008 40F20001 movw r1, #:lower16:chCoreAlloc + 37 .loc 1 77 0 + 38 000c 0022 movs r2, #0 + 39 .loc 1 76 0 + 40 000e C0F20001 movt r1, #:upper16:chCoreAlloc + 41 .loc 1 80 0 + 42 0012 03F11000 add r0, r3, #16 + 43 .loc 1 76 0 + 44 0016 1960 str r1, [r3, #0] + 45 .loc 1 77 0 + 46 0018 9A60 str r2, [r3, #8] + 47 .loc 1 78 0 + 48 001a DA60 str r2, [r3, #12] + 49 .loc 1 84 0 + 50 .loc 1 80 0 + 51 001c FFF7FEBF b chMtxInit + 52 .LVL0: + 53 .cfi_endproc + 54 .LFE7: + 55 .size _heap_init, .-_heap_init + 56 .section .text.chHeapInit,"ax",%progbits + 57 .align 2 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 2 + + + 58 .p2align 4,,15 + 59 .global chHeapInit + 60 .thumb + 61 .thumb_func + 62 .type chHeapInit, %function + 63 chHeapInit: + 64 .LFB8: + 65 .loc 1 99 0 + 66 .cfi_startproc + 67 @ args = 0, pretend = 0, frame = 0 + 68 @ frame_needed = 0, uses_anonymous_args = 0 + 69 @ link register save eliminated. + 70 .LVL1: + 71 .loc 1 104 0 + 72 0000 0023 movs r3, #0 + 73 0002 0360 str r3, [r0, #0] + 74 .LVL2: + 75 .loc 1 105 0 + 76 0004 8160 str r1, [r0, #8] + 77 .loc 1 106 0 + 78 0006 C360 str r3, [r0, #12] + 79 .loc 1 108 0 + 80 0008 083A subs r2, r2, #8 + 81 .LVL3: + 82 .loc 1 110 0 + 83 000a 1030 adds r0, r0, #16 + 84 .LVL4: + 85 .loc 1 107 0 + 86 000c 0B60 str r3, [r1, #0] + 87 .loc 1 108 0 + 88 000e 4A60 str r2, [r1, #4] + 89 .loc 1 114 0 + 90 .loc 1 110 0 + 91 0010 FFF7FEBF b chMtxInit + 92 .LVL5: + 93 .cfi_endproc + 94 .LFE8: + 95 .size chHeapInit, .-chHeapInit + 96 0014 AFF30080 .section .text.chHeapAlloc,"ax",%progbits + 96 AFF30080 + 96 AFF30080 + 97 .align 2 + 98 .p2align 4,,15 + 99 .global chHeapAlloc + 100 .thumb + 101 .thumb_func + 102 .type chHeapAlloc, %function + 103 chHeapAlloc: + 104 .LFB9: + 105 .loc 1 132 0 + 106 .cfi_startproc + 107 @ args = 0, pretend = 0, frame = 0 + 108 @ frame_needed = 0, uses_anonymous_args = 0 + 109 .LVL6: + 110 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 111 .LCFI0: + 112 .cfi_def_cfa_offset 24 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 3 + + + 113 .cfi_offset 3, -24 + 114 .cfi_offset 4, -20 + 115 .cfi_offset 5, -16 + 116 .cfi_offset 6, -12 + 117 .cfi_offset 7, -8 + 118 .cfi_offset 14, -4 + 119 .loc 1 136 0 + 120 0002 1F4E ldr r6, .L20 + 121 .loc 1 138 0 + 122 0004 0731 adds r1, r1, #7 + 123 .LVL7: + 124 .loc 1 136 0 + 125 0006 0028 cmp r0, #0 + 126 0008 18BF it ne + 127 000a 0646 movne r6, r0 + 128 .LVL8: + 129 .loc 1 140 0 + 130 000c 06F11000 add r0, r6, #16 + 131 .loc 1 138 0 + 132 0010 21F00705 bic r5, r1, #7 + 133 .LVL9: + 134 .loc 1 139 0 + 135 0014 06F10804 add r4, r6, #8 + 136 .LVL10: + 137 .loc 1 140 0 + 138 0018 FFF7FEFF bl chMtxLock + 139 .LVL11: + 140 .loc 1 142 0 + 141 001c 00E0 b .L5 + 142 .LVL12: + 143 .L13: + 144 .loc 1 144 0 + 145 001e 1C46 mov r4, r3 + 146 .LVL13: + 147 .L5: + 148 .loc 1 142 0 discriminator 1 + 149 0020 2368 ldr r3, [r4, #0] + 150 .LVL14: + 151 0022 E3B1 cbz r3, .L18 + 152 .loc 1 144 0 + 153 0024 5A68 ldr r2, [r3, #4] + 154 0026 9542 cmp r5, r2 + 155 0028 F9D8 bhi .L13 + 156 .loc 1 145 0 + 157 002a 05F10801 add r1, r5, #8 + 158 002e 9142 cmp r1, r2 + 159 0030 12D8 bhi .L19 + 160 .loc 1 155 0 + 161 0032 4FF6F870 movw r0, #65528 + 162 0036 CFF6FF70 movt r0, 65535 + 163 003a 401B subs r0, r0, r5 + 164 003c 8218 adds r2, r0, r2 + 165 .loc 1 154 0 + 166 003e 1868 ldr r0, [r3, #0] + 167 .loc 1 153 0 + 168 0040 5F18 adds r7, r3, r1 + 169 .LVL15: + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 4 + + + 170 .loc 1 154 0 + 171 0042 5850 str r0, [r3, r1] + 172 .loc 1 155 0 + 173 0044 7A60 str r2, [r7, #4] + 174 .loc 1 156 0 + 175 0046 2760 str r7, [r4, #0] + 176 .loc 1 157 0 + 177 0048 5D60 str r5, [r3, #4] + 178 .LVL16: + 179 .L7: + 180 .loc 1 159 0 + 181 004a 1C46 mov r4, r3 + 182 .LVL17: + 183 004c 44F8086B str r6, [r4], #8 + 184 .loc 1 161 0 + 185 0050 FFF7FEFF bl chMtxUnlock + 186 .LVL18: + 187 .L8: + 188 .loc 1 181 0 + 189 0054 2046 mov r0, r4 + 190 0056 F8BD pop {r3, r4, r5, r6, r7, pc} + 191 .LVL19: + 192 .L19: + 193 .loc 1 149 0 + 194 0058 1A68 ldr r2, [r3, #0] + 195 005a 2260 str r2, [r4, #0] + 196 005c F5E7 b .L7 + 197 .L18: + 198 .loc 1 167 0 + 199 005e FFF7FEFF bl chMtxUnlock + 200 .LVL20: + 201 .loc 1 171 0 + 202 0062 3368 ldr r3, [r6, #0] + 203 0064 4BB1 cbz r3, .L11 + 204 .loc 1 172 0 + 205 0066 05F10800 add r0, r5, #8 + 206 006a 9847 blx r3 + 207 .LVL21: + 208 .loc 1 173 0 + 209 006c 28B1 cbz r0, .L11 + 210 .loc 1 177 0 + 211 006e 00F10804 add r4, r0, #8 + 212 .LVL22: + 213 .loc 1 174 0 + 214 0072 0660 str r6, [r0, #0] + 215 .loc 1 175 0 + 216 0074 4560 str r5, [r0, #4] + 217 .LVL23: + 218 .loc 1 181 0 + 219 0076 2046 mov r0, r4 + 220 0078 F8BD pop {r3, r4, r5, r6, r7, pc} + 221 .LVL24: + 222 .L11: + 223 .loc 1 180 0 + 224 007a 0024 movs r4, #0 + 225 .LVL25: + 226 007c EAE7 b .L8 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 5 + + + 227 .L21: + 228 007e 00BF .align 2 + 229 .L20: + 230 0080 00000000 .word .LANCHOR0 + 231 .cfi_endproc + 232 .LFE9: + 233 .size chHeapAlloc, .-chHeapAlloc + 234 0084 AFF30080 .section .text.chHeapFree,"ax",%progbits + 234 AFF30080 + 234 AFF30080 + 235 .align 2 + 236 .p2align 4,,15 + 237 .global chHeapFree + 238 .thumb + 239 .thumb_func + 240 .type chHeapFree, %function + 241 chHeapFree: + 242 .LFB10: + 243 .loc 1 194 0 + 244 .cfi_startproc + 245 @ args = 0, pretend = 0, frame = 0 + 246 @ frame_needed = 0, uses_anonymous_args = 0 + 247 .LVL26: + 248 0000 70B5 push {r4, r5, r6, lr} + 249 .LCFI1: + 250 .cfi_def_cfa_offset 16 + 251 .cfi_offset 4, -16 + 252 .cfi_offset 5, -12 + 253 .cfi_offset 6, -8 + 254 .cfi_offset 14, -4 + 255 .loc 1 194 0 + 256 0002 0646 mov r6, r0 + 257 .loc 1 201 0 + 258 0004 50F8080C ldr r0, [r0, #-8] + 259 .LVL27: + 260 .loc 1 200 0 + 261 0008 A6F10804 sub r4, r6, #8 + 262 .LVL28: + 263 .loc 1 202 0 + 264 000c 00F10805 add r5, r0, #8 + 265 .LVL29: + 266 .loc 1 203 0 + 267 0010 1030 adds r0, r0, #16 + 268 .LVL30: + 269 0012 FFF7FEFF bl chMtxLock + 270 .LVL31: + 271 .loc 1 202 0 + 272 0016 2B46 mov r3, r5 + 273 .LVL32: + 274 .L29: + 275 .loc 1 210 0 + 276 0018 AB42 cmp r3, r5 + 277 .loc 1 211 0 + 278 001a 1A68 ldr r2, [r3, #0] + 279 .loc 1 210 0 + 280 001c 01D0 beq .L23 + 281 .loc 1 210 0 is_stmt 0 discriminator 2 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 6 + + + 282 001e A342 cmp r3, r4 + 283 0020 02D2 bcs .L26 + 284 .L23: + 285 .loc 1 210 0 discriminator 1 + 286 0022 1AB1 cbz r2, .L25 + 287 .loc 1 211 0 is_stmt 1 + 288 0024 9442 cmp r4, r2 + 289 0026 01D3 bcc .L25 + 290 .L26: + 291 .LVL33: + 292 .loc 1 228 0 + 293 0028 1346 mov r3, r2 + 294 .loc 1 229 0 + 295 002a F5E7 b .L29 + 296 .LVL34: + 297 .L25: + 298 .loc 1 216 0 + 299 002c 56F8041C ldr r1, [r6, #-4] + 300 .loc 1 213 0 + 301 0030 46F8082C str r2, [r6, #-8] + 302 .loc 1 214 0 + 303 0034 1C60 str r4, [r3, #0] + 304 .loc 1 216 0 + 305 0036 01F10802 add r2, r1, #8 + 306 003a 56F8085C ldr r5, [r6, #-8] + 307 .LVL35: + 308 003e A018 adds r0, r4, r2 + 309 0040 A842 cmp r0, r5 + 310 0042 09D0 beq .L33 + 311 .loc 1 221 0 + 312 0044 5A68 ldr r2, [r3, #4] + 313 0046 02F10801 add r1, r2, #8 + 314 004a 5918 adds r1, r3, r1 + 315 004c 8C42 cmp r4, r1 + 316 004e 11D0 beq .L34 + 317 .L28: + 318 .loc 1 233 0 + 319 0050 BDE87040 pop {r4, r5, r6, lr} + 320 .loc 1 231 0 + 321 0054 FFF7FEBF b chMtxUnlock + 322 .LVL36: + 323 .L33: + 324 .loc 1 218 0 + 325 0058 4068 ldr r0, [r0, #4] + 326 .loc 1 219 0 + 327 005a A258 ldr r2, [r4, r2] + 328 .loc 1 218 0 + 329 005c 0918 adds r1, r1, r0 + 330 005e 0831 adds r1, r1, #8 + 331 0060 46F8041C str r1, [r6, #-4] + 332 .loc 1 219 0 + 333 0064 46F8082C str r2, [r6, #-8] + 334 .loc 1 221 0 + 335 0068 5A68 ldr r2, [r3, #4] + 336 006a 02F10801 add r1, r2, #8 + 337 006e 5918 adds r1, r3, r1 + 338 0070 8C42 cmp r4, r1 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 7 + + + 339 0072 EDD1 bne .L28 + 340 .L34: + 341 .loc 1 223 0 + 342 0074 56F8040C ldr r0, [r6, #-4] + 343 .loc 1 224 0 + 344 0078 56F8081C ldr r1, [r6, #-8] + 345 .loc 1 223 0 + 346 007c 1218 adds r2, r2, r0 + 347 007e 0832 adds r2, r2, #8 + 348 .loc 1 224 0 + 349 0080 83E80600 stmia r3, {r1, r2} + 350 0084 E4E7 b .L28 + 351 .cfi_endproc + 352 .LFE10: + 353 .size chHeapFree, .-chHeapFree + 354 0086 00BFAFF3 .section .text.chHeapStatus,"ax",%progbits + 354 0080AFF3 + 354 0080 + 355 .align 2 + 356 .p2align 4,,15 + 357 .global chHeapStatus + 358 .thumb + 359 .thumb_func + 360 .type chHeapStatus, %function + 361 chHeapStatus: + 362 .LFB11: + 363 .loc 1 250 0 + 364 .cfi_startproc + 365 @ args = 0, pretend = 0, frame = 0 + 366 @ frame_needed = 0, uses_anonymous_args = 0 + 367 .LVL37: + 368 0000 38B5 push {r3, r4, r5, lr} + 369 .LCFI2: + 370 .cfi_def_cfa_offset 16 + 371 .cfi_offset 3, -16 + 372 .cfi_offset 4, -12 + 373 .cfi_offset 5, -8 + 374 .cfi_offset 14, -4 + 375 .loc 1 255 0 + 376 0002 0E4C ldr r4, .L46 + 377 .loc 1 250 0 + 378 0004 0D46 mov r5, r1 + 379 .loc 1 255 0 + 380 0006 0028 cmp r0, #0 + 381 0008 18BF it ne + 382 000a 0446 movne r4, r0 + 383 .LVL38: + 384 .loc 1 257 0 + 385 000c 04F11000 add r0, r4, #16 + 386 0010 FFF7FEFF bl chMtxLock + 387 .LVL39: + 388 .loc 1 260 0 + 389 0014 A368 ldr r3, [r4, #8] + 390 0016 6BB1 cbz r3, .L41 + 391 0018 0022 movs r2, #0 + 392 001a 1446 mov r4, r2 + 393 .LVL40: + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 8 + + + 394 .L38: + 395 .loc 1 261 0 discriminator 2 + 396 001c 5868 ldr r0, [r3, #4] + 397 .loc 1 260 0 discriminator 2 + 398 001e 1B68 ldr r3, [r3, #0] + 399 .loc 1 261 0 discriminator 2 + 400 0020 1218 adds r2, r2, r0 + 401 .LVL41: + 402 .loc 1 260 0 discriminator 2 + 403 0022 0134 adds r4, r4, #1 + 404 .LVL42: + 405 0024 002B cmp r3, #0 + 406 0026 F9D1 bne .L38 + 407 .LVL43: + 408 .L37: + 409 .loc 1 262 0 + 410 0028 05B1 cbz r5, .L39 + 411 .loc 1 263 0 + 412 002a 2A60 str r2, [r5, #0] + 413 .L39: + 414 .loc 1 265 0 + 415 002c FFF7FEFF bl chMtxUnlock + 416 .LVL44: + 417 .loc 1 267 0 + 418 0030 2046 mov r0, r4 + 419 0032 38BD pop {r3, r4, r5, pc} + 420 .LVL45: + 421 .L41: + 422 .loc 1 259 0 + 423 0034 1A46 mov r2, r3 + 424 .loc 1 260 0 + 425 0036 1C46 mov r4, r3 + 426 .LVL46: + 427 0038 F6E7 b .L37 + 428 .L47: + 429 003a 00BF .align 2 + 430 .L46: + 431 003c 00000000 .word .LANCHOR0 + 432 .cfi_endproc + 433 .LFE11: + 434 .size chHeapStatus, .-chHeapStatus + 435 .section .text.chHeapMaxMinFraq,"ax",%progbits + 436 .align 2 + 437 .p2align 4,,15 + 438 .global chHeapMaxMinFraq + 439 .thumb + 440 .thumb_func + 441 .type chHeapMaxMinFraq, %function + 442 chHeapMaxMinFraq: + 443 .LFB12: + 444 .loc 1 282 0 + 445 .cfi_startproc + 446 @ args = 0, pretend = 0, frame = 0 + 447 @ frame_needed = 0, uses_anonymous_args = 0 + 448 .LVL47: + 449 0000 70B5 push {r4, r5, r6, lr} + 450 .LCFI3: + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 9 + + + 451 .cfi_def_cfa_offset 16 + 452 .cfi_offset 4, -16 + 453 .cfi_offset 5, -12 + 454 .cfi_offset 6, -8 + 455 .cfi_offset 14, -4 + 456 .loc 1 289 0 + 457 0002 124E ldr r6, .L56 + 458 .loc 1 285 0 + 459 0004 0023 movs r3, #0 + 460 .loc 1 289 0 + 461 0006 0028 cmp r0, #0 + 462 0008 18BF it ne + 463 000a 0646 movne r6, r0 + 464 .LVL48: + 465 .loc 1 285 0 + 466 000c 0B60 str r3, [r1, #0] + 467 .loc 1 291 0 + 468 000e 06F11000 add r0, r6, #16 + 469 .loc 1 286 0 + 470 0012 1360 str r3, [r2, #0] + 471 .loc 1 282 0 + 472 0014 0C46 mov r4, r1 + 473 0016 1546 mov r5, r2 + 474 .loc 1 291 0 + 475 0018 FFF7FEFF bl chMtxLock + 476 .LVL49: + 477 .loc 1 293 0 + 478 001c B368 ldr r3, [r6, #8] + 479 001e 06F10800 add r0, r6, #8 + 480 .LVL50: + 481 0022 73B1 cbz r3, .L52 + 482 .L54: + 483 .loc 1 294 0 + 484 0024 5B68 ldr r3, [r3, #4] + 485 .LVL51: + 486 0026 2268 ldr r2, [r4, #0] + 487 0028 9A42 cmp r2, r3 + 488 002a 94BF ite ls + 489 002c 2260 strls r2, [r4, #0] + 490 002e 2360 strhi r3, [r4, #0] + 491 0030 2A68 ldr r2, [r5, #0] + 492 0032 9A42 cmp r2, r3 + 493 0034 2CBF ite cs + 494 0036 2A60 strcs r2, [r5, #0] + 495 0038 2B60 strcc r3, [r5, #0] + 496 .loc 1 293 0 + 497 003a 0068 ldr r0, [r0, #0] + 498 .LVL52: + 499 003c 0368 ldr r3, [r0, #0] + 500 .LVL53: + 501 003e 002B cmp r3, #0 + 502 0040 F0D1 bne .L54 + 503 .L52: + 504 .loc 1 302 0 + 505 0042 BDE87040 pop {r4, r5, r6, lr} + 506 .loc 1 301 0 + 507 0046 FFF7FEBF b chMtxUnlock + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 10 + + + 508 .LVL54: + 509 .L57: + 510 004a 00BF .align 2 + 511 .L56: + 512 004c 00000000 .word .LANCHOR0 + 513 .cfi_endproc + 514 .LFE12: + 515 .size chHeapMaxMinFraq, .-chHeapMaxMinFraq + 516 .section .bss.default_heap,"aw",%nobits + 517 .align 3 + 518 .set .LANCHOR0,. + 0 + 519 .type default_heap, %object + 520 .size default_heap, 32 + 521 default_heap: + 522 0000 00000000 .space 32 + 522 00000000 + 522 00000000 + 522 00000000 + 522 00000000 + 523 .text + 524 .Letext0: + 525 .file 2 "c:\\yagarto\\bin\\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h" + 526 .file 3 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 527 .file 4 "../..//os/ports/GCC/ARMCMx/chtypes.h" + 528 .file 5 "../..//os/kernel/include/chlists.h" + 529 .file 6 "../..//os/kernel/include/chthreads.h" + 530 .file 7 "../..//os/ports/GCC/ARMCMx/chcore_v7m.h" + 531 .file 8 "../..//os/kernel/include/chmtx.h" + 532 .file 9 "../..//os/kernel/include/chmemcore.h" + 533 .file 10 "../..//os/kernel/include/chheap.h" + 534 .section .debug_info,"",%progbits + 535 .Ldebug_info0: + 536 0000 AA070000 .4byte 0x7aa + 537 0004 0200 .2byte 0x2 + 538 0006 00000000 .4byte .Ldebug_abbrev0 + 539 000a 04 .byte 0x4 + 540 000b 01 .uleb128 0x1 + 541 000c EE010000 .4byte .LASF77 + 542 0010 01 .byte 0x1 + 543 0011 41000000 .4byte .LASF78 + 544 0015 9E010000 .4byte .LASF79 + 545 0019 00000000 .4byte .Ldebug_ranges0+0 + 546 001d 00000000 .4byte 0 + 547 0021 00000000 .4byte 0 + 548 0025 00000000 .4byte .Ldebug_line0 + 549 0029 02 .uleb128 0x2 + 550 002a 04 .byte 0x4 + 551 002b 05 .byte 0x5 + 552 002c 696E7400 .ascii "int\000" + 553 0030 03 .uleb128 0x3 + 554 0031 06000000 .4byte .LASF2 + 555 0035 02 .byte 0x2 + 556 0036 D5 .byte 0xd5 + 557 0037 3B000000 .4byte 0x3b + 558 003b 04 .uleb128 0x4 + 559 003c 04 .byte 0x4 + 560 003d 07 .byte 0x7 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 11 + + + 561 003e 0D010000 .4byte .LASF0 + 562 0042 04 .uleb128 0x4 + 563 0043 01 .byte 0x1 + 564 0044 06 .byte 0x6 + 565 0045 B7000000 .4byte .LASF1 + 566 0049 03 .uleb128 0x3 + 567 004a 0C030000 .4byte .LASF3 + 568 004e 03 .byte 0x3 + 569 004f 2A .byte 0x2a + 570 0050 54000000 .4byte 0x54 + 571 0054 04 .uleb128 0x4 + 572 0055 01 .byte 0x1 + 573 0056 08 .byte 0x8 + 574 0057 24020000 .4byte .LASF4 + 575 005b 04 .uleb128 0x4 + 576 005c 02 .byte 0x2 + 577 005d 05 .byte 0x5 + 578 005e 47020000 .4byte .LASF5 + 579 0062 04 .uleb128 0x4 + 580 0063 02 .byte 0x2 + 581 0064 07 .byte 0x7 + 582 0065 39010000 .4byte .LASF6 + 583 0069 03 .uleb128 0x3 + 584 006a 1C020000 .4byte .LASF7 + 585 006e 03 .byte 0x3 + 586 006f 4F .byte 0x4f + 587 0070 74000000 .4byte 0x74 + 588 0074 04 .uleb128 0x4 + 589 0075 04 .byte 0x4 + 590 0076 05 .byte 0x5 + 591 0077 E4000000 .4byte .LASF8 + 592 007b 03 .uleb128 0x3 + 593 007c 99020000 .4byte .LASF9 + 594 0080 03 .byte 0x3 + 595 0081 50 .byte 0x50 + 596 0082 86000000 .4byte 0x86 + 597 0086 04 .uleb128 0x4 + 598 0087 04 .byte 0x4 + 599 0088 07 .byte 0x7 + 600 0089 1A010000 .4byte .LASF10 + 601 008d 04 .uleb128 0x4 + 602 008e 08 .byte 0x8 + 603 008f 05 .byte 0x5 + 604 0090 A9000000 .4byte .LASF11 + 605 0094 03 .uleb128 0x3 + 606 0095 14000000 .4byte .LASF12 + 607 0099 03 .byte 0x3 + 608 009a 78 .byte 0x78 + 609 009b 9F000000 .4byte 0x9f + 610 009f 04 .uleb128 0x4 + 611 00a0 08 .byte 0x8 + 612 00a1 07 .byte 0x7 + 613 00a2 2A000000 .4byte .LASF13 + 614 00a6 03 .uleb128 0x3 + 615 00a7 52010000 .4byte .LASF14 + 616 00ab 04 .byte 0x4 + 617 00ac 2F .byte 0x2f + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 12 + + + 618 00ad 49000000 .4byte 0x49 + 619 00b1 03 .uleb128 0x3 + 620 00b2 ED000000 .4byte .LASF15 + 621 00b6 04 .byte 0x4 + 622 00b7 30 .byte 0x30 + 623 00b8 49000000 .4byte 0x49 + 624 00bc 03 .uleb128 0x3 + 625 00bd 05020000 .4byte .LASF16 + 626 00c1 04 .byte 0x4 + 627 00c2 31 .byte 0x31 + 628 00c3 49000000 .4byte 0x49 + 629 00c7 03 .uleb128 0x3 + 630 00c8 14020000 .4byte .LASF17 + 631 00cc 04 .byte 0x4 + 632 00cd 32 .byte 0x32 + 633 00ce 7B000000 .4byte 0x7b + 634 00d2 03 .uleb128 0x3 + 635 00d3 4C010000 .4byte .LASF18 + 636 00d7 04 .byte 0x4 + 637 00d8 33 .byte 0x33 + 638 00d9 69000000 .4byte 0x69 + 639 00dd 03 .uleb128 0x3 + 640 00de 66010000 .4byte .LASF19 + 641 00e2 04 .byte 0x4 + 642 00e3 35 .byte 0x35 + 643 00e4 7B000000 .4byte 0x7b + 644 00e8 03 .uleb128 0x3 + 645 00e9 CD020000 .4byte .LASF20 + 646 00ed 04 .byte 0x4 + 647 00ee 36 .byte 0x36 + 648 00ef 7B000000 .4byte 0x7b + 649 00f3 03 .uleb128 0x3 + 650 00f4 7B020000 .4byte .LASF21 + 651 00f8 05 .byte 0x5 + 652 00f9 2A .byte 0x2a + 653 00fa FE000000 .4byte 0xfe + 654 00fe 05 .uleb128 0x5 + 655 00ff 7B020000 .4byte .LASF21 + 656 0103 48 .byte 0x48 + 657 0104 06 .byte 0x6 + 658 0105 5E .byte 0x5e + 659 0106 15020000 .4byte 0x215 + 660 010a 06 .uleb128 0x6 + 661 010b 6C020000 .4byte .LASF22 + 662 010f 06 .byte 0x6 + 663 0110 5F .byte 0x5f + 664 0111 3A020000 .4byte 0x23a + 665 0115 02 .byte 0x2 + 666 0116 23 .byte 0x23 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.4byte .LASF27 + 702 0155 06 .byte 0x6 + 703 0156 67 .byte 0x67 + 704 0157 3A020000 .4byte 0x23a + 705 015b 02 .byte 0x2 + 706 015c 23 .byte 0x23 + 707 015d 14 .uleb128 0x14 + 708 015e 06 .uleb128 0x6 + 709 015f 21030000 .4byte .LASF28 + 710 0163 06 .byte 0x6 + 711 0164 6E .byte 0x6e + 712 0165 90040000 .4byte 0x490 + 713 0169 02 .byte 0x2 + 714 016a 23 .byte 0x23 + 715 016b 18 .uleb128 0x18 + 716 016c 06 .uleb128 0x6 + 717 016d 51020000 .4byte .LASF29 + 718 0171 06 .byte 0x6 + 719 0172 79 .byte 0x79 + 720 0173 B1000000 .4byte 0xb1 + 721 0177 02 .byte 0x2 + 722 0178 23 .byte 0x23 + 723 0179 1C .uleb128 0x1c + 724 017a 06 .uleb128 0x6 + 725 017b 73020000 .4byte .LASF30 + 726 017f 06 .byte 0x6 + 727 0180 7D .byte 0x7d + 728 0181 A6000000 .4byte 0xa6 + 729 0185 02 .byte 0x2 + 730 0186 23 .byte 0x23 + 731 0187 1D .uleb128 0x1d + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 14 + + + 732 0188 06 .uleb128 0x6 + 733 0189 05030000 .4byte .LASF31 + 734 018d 06 .byte 0x6 + 735 018e 82 .byte 0x82 + 736 018f BC000000 .4byte 0xbc + 737 0193 02 .byte 0x2 + 738 0194 23 .byte 0x23 + 739 0195 1E .uleb128 0x1e + 740 0196 06 .uleb128 0x6 + 741 0197 E2020000 .4byte .LASF32 + 742 019b 06 .byte 0x6 + 743 019c 89 .byte 0x89 + 744 019d 3C030000 .4byte 0x33c + 745 01a1 02 .byte 0x2 + 746 01a2 23 .byte 0x23 + 747 01a3 20 .uleb128 0x20 + 748 01a4 07 .uleb128 0x7 + 749 01a5 705F7500 .ascii "p_u\000" + 750 01a9 06 .byte 0x6 + 751 01aa AE .byte 0xae + 752 01ab 5B040000 .4byte 0x45b + 753 01af 02 .byte 0x2 + 754 01b0 23 .byte 0x23 + 755 01b1 24 .uleb128 0x24 + 756 01b2 06 .uleb128 0x6 + 757 01b3 41030000 .4byte .LASF33 + 758 01b7 06 .byte 0x6 + 759 01b8 B3 .byte 0xb3 + 760 01b9 62020000 .4byte 0x262 + 761 01bd 02 .byte 0x2 + 762 01be 23 .byte 0x23 + 763 01bf 28 .uleb128 0x28 + 764 01c0 06 .uleb128 0x6 + 765 01c1 F0020000 .4byte .LASF34 + 766 01c5 06 .byte 0x6 + 767 01c6 B9 .byte 0xb9 + 768 01c7 40020000 .4byte 0x240 + 769 01cb 02 .byte 0x2 + 770 01cc 23 .byte 0x23 + 771 01cd 2C .uleb128 0x2c + 772 01ce 06 .uleb128 0x6 + 773 01cf 00000000 .4byte .LASF35 + 774 01d3 06 .byte 0x6 + 775 01d4 BD .byte 0xbd + 776 01d5 D2000000 .4byte 0xd2 + 777 01d9 02 .byte 0x2 + 778 01da 23 .byte 0x23 + 779 01db 34 .uleb128 0x34 + 780 01dc 06 .uleb128 0x6 + 781 01dd 8E020000 .4byte .LASF36 + 782 01e1 06 .byte 0x6 + 783 01e2 C3 .byte 0xc3 + 784 01e3 DD000000 .4byte 0xdd + 785 01e7 02 .byte 0x2 + 786 01e8 23 .byte 0x23 + 787 01e9 38 .uleb128 0x38 + 788 01ea 06 .uleb128 0x6 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 15 + + + 789 01eb 3D020000 .4byte .LASF37 + 790 01ef 06 .byte 0x6 + 791 01f0 CA .byte 0xca + 792 01f1 A2040000 .4byte 0x4a2 + 793 01f5 02 .byte 0x2 + 794 01f6 23 .byte 0x23 + 795 01f7 3C .uleb128 0x3c + 796 01f8 06 .uleb128 0x6 + 797 01f9 D7020000 .4byte .LASF38 + 798 01fd 06 .byte 0x6 + 799 01fe CE .byte 0xce + 800 01ff C7000000 .4byte 0xc7 + 801 0203 02 .byte 0x2 + 802 0204 23 .byte 0x23 + 803 0205 40 .uleb128 0x40 + 804 0206 06 .uleb128 0x6 + 805 0207 C9000000 .4byte .LASF39 + 806 020b 06 .byte 0x6 + 807 020c D4 .byte 0xd4 + 808 020d 78020000 .4byte 0x278 + 809 0211 02 .byte 0x2 + 810 0212 23 .byte 0x23 + 811 0213 44 .uleb128 0x44 + 812 0214 00 .byte 0 + 813 0215 08 .uleb128 0x8 + 814 0216 08 .byte 0x8 + 815 0217 05 .byte 0x5 + 816 0218 61 .byte 0x61 + 817 0219 3A020000 .4byte 0x23a + 818 021d 06 .uleb128 0x6 + 819 021e 6C020000 .4byte .LASF22 + 820 0222 05 .byte 0x5 + 821 0223 62 .byte 0x62 + 822 0224 3A020000 .4byte 0x23a + 823 0228 02 .byte 0x2 + 824 0229 23 .byte 0x23 + 825 022a 00 .uleb128 0 + 826 022b 06 .uleb128 0x6 + 827 022c 0D020000 .4byte .LASF23 + 828 0230 05 .byte 0x5 + 829 0231 64 .byte 0x64 + 830 0232 3A020000 .4byte 0x23a + 831 0236 02 .byte 0x2 + 832 0237 23 .byte 0x23 + 833 0238 04 .uleb128 0x4 + 834 0239 00 .byte 0 + 835 023a 09 .uleb128 0x9 + 836 023b 04 .byte 0x4 + 837 023c F3000000 .4byte 0xf3 + 838 0240 03 .uleb128 0x3 + 839 0241 E1010000 .4byte .LASF40 + 840 0245 05 .byte 0x5 + 841 0246 66 .byte 0x66 + 842 0247 15020000 .4byte 0x215 + 843 024b 08 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044b 00 .uleb128 0 + 1119 044c 06 .uleb128 0x6 + 1120 044d 34010000 .4byte .LASF60 + 1121 0451 0A .byte 0xa + 1122 0452 40 .byte 0x40 + 1123 0453 30000000 .4byte 0x30 + 1124 0457 02 .byte 0x2 + 1125 0458 23 .byte 0x23 + 1126 0459 04 .uleb128 0x4 + 1127 045a 00 .byte 0 + 1128 045b 10 .uleb128 0x10 + 1129 045c 04 .byte 0x4 + 1130 045d 06 .byte 0x6 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 21 + + + 1131 045e 90 .byte 0x90 + 1132 045f 90040000 .4byte 0x490 + 1133 0463 11 .uleb128 0x11 + 1134 0464 0D000000 .4byte .LASF61 + 1135 0468 06 .byte 0x6 + 1136 0469 97 .byte 0x97 + 1137 046a D2000000 .4byte 0xd2 + 1138 046e 11 .uleb128 0x11 + 1139 046f 5F000000 .4byte .LASF62 + 1140 0473 06 .byte 0x6 + 1141 0474 9E .byte 0x9e + 1142 0475 D2000000 .4byte 0xd2 + 1143 0479 11 .uleb128 0x11 + 1144 047a 14030000 .4byte .LASF63 + 1145 047e 06 .byte 0x6 + 1146 047f A5 .byte 0xa5 + 1147 0480 78020000 .4byte 0x278 + 1148 0484 11 .uleb128 0x11 + 1149 0485 65020000 .4byte .LASF64 + 1150 0489 06 .byte 0x6 + 1151 048a AC .byte 0xac + 1152 048b DD000000 .4byte 0xdd + 1153 048f 00 .byte 0 + 1154 0490 09 .uleb128 0x9 + 1155 0491 04 .byte 0x4 + 1156 0492 96040000 .4byte 0x496 + 1157 0496 14 .uleb128 0x14 + 1158 0497 9B040000 .4byte 0x49b + 1159 049b 04 .uleb128 0x4 + 1160 049c 01 .byte 0x1 + 1161 049d 08 .byte 0x8 + 1162 049e B4020000 .4byte .LASF65 + 1163 04a2 09 .uleb128 0x9 + 1164 04a3 04 .byte 0x4 + 1165 04a4 7E030000 .4byte 0x37e + 1166 04a8 15 .uleb128 0x15 + 1167 04a9 01 .byte 0x1 + 1168 04aa 28030000 .4byte .LASF66 + 1169 04ae 01 .byte 0x1 + 1170 04af 4B .byte 0x4b + 1171 04b0 01 .byte 0x1 + 1172 04b1 00000000 .4byte .LFB7 + 1173 04b5 20000000 .4byte .LFE7 + 1174 04b9 02 .byte 0x2 + 1175 04ba 7D .byte 0x7d + 1176 04bb 00 .sleb128 0 + 1177 04bc 01 .byte 0x1 + 1178 04bd D6040000 .4byte 0x4d6 + 1179 04c1 16 .uleb128 0x16 + 1180 04c2 20000000 .4byte .LVL0 + 1181 04c6 01 .byte 0x1 + 1182 04c7 77070000 .4byte 0x777 + 1183 04cb 17 .uleb128 0x17 + 1184 04cc 01 .byte 0x1 + 1185 04cd 50 .byte 0x50 + 1186 04ce 05 .byte 0x5 + 1187 04cf 03 .byte 0x3 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 22 + + + 1188 04d0 10000000 .4byte .LANCHOR0+16 + 1189 04d4 00 .byte 0 + 1190 04d5 00 .byte 0 + 1191 04d6 15 .uleb128 0x15 + 1192 04d7 01 .byte 0x1 + 1193 04d8 81000000 .4byte .LASF67 + 1194 04dc 01 .byte 0x1 + 1195 04dd 63 .byte 0x63 + 1196 04de 01 .byte 0x1 + 1197 04df 00000000 .4byte .LFB8 + 1198 04e3 14000000 .4byte .LFE8 + 1199 04e7 02 .byte 0x2 + 1200 04e8 7D .byte 0x7d + 1201 04e9 00 .sleb128 0 + 1202 04ea 01 .byte 0x1 + 1203 04eb 3F050000 .4byte 0x53f + 1204 04ef 18 .uleb128 0x18 + 1205 04f0 6F000000 .4byte .LASF68 + 1206 04f4 01 .byte 0x1 + 1207 04f5 63 .byte 0x63 + 1208 04f6 32040000 .4byte 0x432 + 1209 04fa 00000000 .4byte .LLST0 + 1210 04fe 19 .uleb128 0x19 + 1211 04ff 62756600 .ascii "buf\000" + 1212 0503 01 .byte 0x1 + 1213 0504 63 .byte 0x63 + 1214 0505 78020000 .4byte 0x278 + 1215 0509 2E000000 .4byte .LLST1 + 1216 050d 18 .uleb128 0x18 + 1217 050e 34010000 .4byte .LASF60 + 1218 0512 01 .byte 0x1 + 1219 0513 63 .byte 0x63 + 1220 0514 30000000 .4byte 0x30 + 1221 0518 4F000000 .4byte .LLST2 + 1222 051c 1A .uleb128 0x1a + 1223 051d 687000 .ascii "hp\000" + 1224 0520 01 .byte 0x1 + 1225 0521 64 .byte 0x64 + 1226 0522 2C040000 .4byte 0x42c + 1227 0526 7D000000 .4byte .LLST3 + 1228 052a 16 .uleb128 0x16 + 1229 052b 14000000 .4byte .LVL5 + 1230 052f 01 .byte 0x1 + 1231 0530 77070000 .4byte 0x777 + 1232 0534 17 .uleb128 0x17 + 1233 0535 01 .byte 0x1 + 1234 0536 50 .byte 0x50 + 1235 0537 05 .byte 0x5 + 1236 0538 F3 .byte 0xf3 + 1237 0539 01 .uleb128 0x1 + 1238 053a 50 .byte 0x50 + 1239 053b 23 .byte 0x23 + 1240 053c 10 .uleb128 0x10 + 1241 053d 00 .byte 0 + 1242 053e 00 .byte 0 + 1243 053f 1B .uleb128 0x1b + 1244 0540 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 23 + + + 1245 0541 82020000 .4byte .LASF70 + 1246 0545 01 .byte 0x1 + 1247 0546 84 .byte 0x84 + 1248 0547 01 .byte 0x1 + 1249 0548 78020000 .4byte 0x278 + 1250 054c 00000000 .4byte .LFB9 + 1251 0550 84000000 .4byte .LFE9 + 1252 0554 9E000000 .4byte .LLST4 + 1253 0558 01 .byte 0x1 + 1254 0559 D8050000 .4byte 0x5d8 + 1255 055d 18 .uleb128 0x18 + 1256 055e 6F000000 .4byte .LASF68 + 1257 0562 01 .byte 0x1 + 1258 0563 84 .byte 0x84 + 1259 0564 32040000 .4byte 0x432 + 1260 0568 BE000000 .4byte .LLST5 + 1261 056c 18 .uleb128 0x18 + 1262 056d 34010000 .4byte .LASF60 + 1263 0571 01 .byte 0x1 + 1264 0572 84 .byte 0x84 + 1265 0573 30000000 .4byte 0x30 + 1266 0577 DC000000 .4byte .LLST6 + 1267 057b 1A .uleb128 0x1a + 1268 057c 717000 .ascii "qp\000" + 1269 057f 01 .byte 0x1 + 1270 0580 85 .byte 0x85 + 1271 0581 2C040000 .4byte 0x42c + 1272 0585 07010000 .4byte .LLST7 + 1273 0589 1A .uleb128 0x1a + 1274 058a 687000 .ascii "hp\000" + 1275 058d 01 .byte 0x1 + 1276 058e 85 .byte 0x85 + 1277 058f 2C040000 .4byte 0x42c + 1278 0593 30010000 .4byte .LLST8 + 1279 0597 1A .uleb128 0x1a + 1280 0598 667000 .ascii "fp\000" + 1281 059b 01 .byte 0x1 + 1282 059c 85 .byte 0x85 + 1283 059d 2C040000 .4byte 0x42c + 1284 05a1 7C010000 .4byte .LLST9 + 1285 05a5 1C .uleb128 0x1c + 1286 05a6 1C000000 .4byte .LVL11 + 1287 05aa 8B070000 .4byte 0x78b + 1288 05ae B9050000 .4byte 0x5b9 + 1289 05b2 17 .uleb128 0x17 + 1290 05b3 01 .byte 0x1 + 1291 05b4 50 .byte 0x50 + 1292 05b5 02 .byte 0x2 + 1293 05b6 76 .byte 0x76 + 1294 05b7 10 .sleb128 16 + 1295 05b8 00 .byte 0 + 1296 05b9 1D .uleb128 0x1d + 1297 05ba 54000000 .4byte .LVL18 + 1298 05be 9F070000 .4byte 0x79f + 1299 05c2 1D .uleb128 0x1d + 1300 05c3 62000000 .4byte .LVL20 + 1301 05c7 9F070000 .4byte 0x79f + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 24 + + + 1302 05cb 1E .uleb128 0x1e + 1303 05cc 6C000000 .4byte .LVL21 + 1304 05d0 17 .uleb128 0x17 + 1305 05d1 01 .byte 0x1 + 1306 05d2 50 .byte 0x50 + 1307 05d3 02 .byte 0x2 + 1308 05d4 75 .byte 0x75 + 1309 05d5 08 .sleb128 8 + 1310 05d6 00 .byte 0 + 1311 05d7 00 .byte 0 + 1312 05d8 1F .uleb128 0x1f + 1313 05d9 01 .byte 0x1 + 1314 05da D9000000 .4byte .LASF69 + 1315 05de 01 .byte 0x1 + 1316 05df C2 .byte 0xc2 + 1317 05e0 01 .byte 0x1 + 1318 05e1 00000000 .4byte .LFB10 + 1319 05e5 86000000 .4byte .LFE10 + 1320 05e9 8F010000 .4byte .LLST10 + 1321 05ed 01 .byte 0x1 + 1322 05ee 47060000 .4byte 0x647 + 1323 05f2 19 .uleb128 0x19 + 1324 05f3 7000 .ascii "p\000" + 1325 05f5 01 .byte 0x1 + 1326 05f6 C2 .byte 0xc2 + 1327 05f7 78020000 .4byte 0x278 + 1328 05fb AF010000 .4byte .LLST11 + 1329 05ff 1A .uleb128 0x1a + 1330 0600 717000 .ascii "qp\000" + 1331 0603 01 .byte 0x1 + 1332 0604 C3 .byte 0xc3 + 1333 0605 2C040000 .4byte 0x42c + 1334 0609 CD010000 .4byte .LLST12 + 1335 060d 20 .uleb128 0x20 + 1336 060e 687000 .ascii "hp\000" + 1337 0611 01 .byte 0x1 + 1338 0612 C3 .byte 0xc3 + 1339 0613 2C040000 .4byte 0x42c + 1340 0617 01 .byte 0x1 + 1341 0618 54 .byte 0x54 + 1342 0619 21 .uleb128 0x21 + 1343 061a 6F000000 .4byte .LASF68 + 1344 061e 01 .byte 0x1 + 1345 061f C4 .byte 0xc4 + 1346 0620 32040000 .4byte 0x432 + 1347 0624 0C020000 .4byte .LLST13 + 1348 0628 1C .uleb128 0x1c + 1349 0629 16000000 .4byte .LVL31 + 1350 062d 8B070000 .4byte 0x78b + 1351 0631 3C060000 .4byte 0x63c + 1352 0635 17 .uleb128 0x17 + 1353 0636 01 .byte 0x1 + 1354 0637 50 .byte 0x50 + 1355 0638 02 .byte 0x2 + 1356 0639 75 .byte 0x75 + 1357 063a 08 .sleb128 8 + 1358 063b 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 25 + + + 1359 063c 22 .uleb128 0x22 + 1360 063d 58000000 .4byte .LVL36 + 1361 0641 01 .byte 0x1 + 1362 0642 9F070000 .4byte 0x79f + 1363 0646 00 .byte 0 + 1364 0647 1B .uleb128 0x1b + 1365 0648 01 .byte 0x1 + 1366 0649 B9020000 .4byte .LASF71 + 1367 064d 01 .byte 0x1 + 1368 064e FA .byte 0xfa + 1369 064f 01 .byte 0x1 + 1370 0650 30000000 .4byte 0x30 + 1371 0654 00000000 .4byte .LFB11 + 1372 0658 40000000 .4byte .LFE11 + 1373 065c 38020000 .4byte .LLST14 + 1374 0660 01 .byte 0x1 + 1375 0661 CA060000 .4byte 0x6ca + 1376 0665 18 .uleb128 0x18 + 1377 0666 6F000000 .4byte .LASF68 + 1378 066a 01 .byte 0x1 + 1379 066b FA .byte 0xfa + 1380 066c 32040000 .4byte 0x432 + 1381 0670 58020000 .4byte .LLST15 + 1382 0674 18 .uleb128 0x18 + 1383 0675 1B030000 .4byte .LASF72 + 1384 0679 01 .byte 0x1 + 1385 067a FA .byte 0xfa + 1386 067b CA060000 .4byte 0x6ca + 1387 067f BB020000 .4byte .LLST16 + 1388 0683 1A .uleb128 0x1a + 1389 0684 717000 .ascii "qp\000" + 1390 0687 01 .byte 0x1 + 1391 0688 FB .byte 0xfb + 1392 0689 2C040000 .4byte 0x42c + 1393 068d D9020000 .4byte .LLST17 + 1394 0691 1A .uleb128 0x1a + 1395 0692 6E00 .ascii "n\000" + 1396 0694 01 .byte 0x1 + 1397 0695 FC .byte 0xfc + 1398 0696 30000000 .4byte 0x30 + 1399 069a 1A030000 .4byte .LLST18 + 1400 069e 1A .uleb128 0x1a + 1401 069f 737A00 .ascii "sz\000" + 1402 06a2 01 .byte 0x1 + 1403 06a3 FC .byte 0xfc + 1404 06a4 30000000 .4byte 0x30 + 1405 06a8 45030000 .4byte .LLST19 + 1406 06ac 1C .uleb128 0x1c + 1407 06ad 14000000 .4byte .LVL39 + 1408 06b1 8B070000 .4byte 0x78b + 1409 06b5 C0060000 .4byte 0x6c0 + 1410 06b9 17 .uleb128 0x17 + 1411 06ba 01 .byte 0x1 + 1412 06bb 50 .byte 0x50 + 1413 06bc 02 .byte 0x2 + 1414 06bd 74 .byte 0x74 + 1415 06be 10 .sleb128 16 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 26 + + + 1416 06bf 00 .byte 0 + 1417 06c0 1D .uleb128 0x1d + 1418 06c1 30000000 .4byte .LVL44 + 1419 06c5 9F070000 .4byte 0x79f + 1420 06c9 00 .byte 0 + 1421 06ca 09 .uleb128 0x9 + 1422 06cb 04 .byte 0x4 + 1423 06cc 30000000 .4byte 0x30 + 1424 06d0 23 .uleb128 0x23 + 1425 06d1 01 .byte 0x1 + 1426 06d2 98000000 .4byte .LASF73 + 1427 06d6 01 .byte 0x1 + 1428 06d7 1A01 .2byte 0x11a + 1429 06d9 01 .byte 0x1 + 1430 06da 00000000 .4byte .LFB12 + 1431 06de 50000000 .4byte .LFE12 + 1432 06e2 70030000 .4byte .LLST20 + 1433 06e6 01 .byte 0x1 + 1434 06e7 66070000 .4byte 0x766 + 1435 06eb 24 .uleb128 0x24 + 1436 06ec 6F000000 .4byte .LASF68 + 1437 06f0 01 .byte 0x1 + 1438 06f1 1A01 .2byte 0x11a + 1439 06f3 32040000 .4byte 0x432 + 1440 06f7 90030000 .4byte .LLST21 + 1441 06fb 25 .uleb128 0x25 + 1442 06fc 6D696E00 .ascii "min\000" + 1443 0700 01 .byte 0x1 + 1444 0701 1A01 .2byte 0x11a + 1445 0703 CA060000 .4byte 0x6ca + 1446 0707 AE030000 .4byte .LLST22 + 1447 070b 25 .uleb128 0x25 + 1448 070c 6D617800 .ascii "max\000" + 1449 0710 01 .byte 0x1 + 1450 0711 1A01 .2byte 0x11a + 1451 0713 CA060000 .4byte 0x6ca + 1452 0717 CC030000 .4byte .LLST23 + 1453 071b 26 .uleb128 0x26 + 1454 071c 717000 .ascii "qp\000" + 1455 071f 01 .byte 0x1 + 1456 0720 1B01 .2byte 0x11b + 1457 0722 2C040000 .4byte 0x42c + 1458 0726 EA030000 .4byte .LLST24 + 1459 072a 26 .uleb128 0x26 + 1460 072b 6E00 .ascii "n\000" + 1461 072d 01 .byte 0x1 + 1462 072e 1C01 .2byte 0x11c + 1463 0730 30000000 .4byte 0x30 + 1464 0734 FD030000 .4byte .LLST25 + 1465 0738 26 .uleb128 0x26 + 1466 0739 737A00 .ascii "sz\000" + 1467 073c 01 .byte 0x1 + 1468 073d 1C01 .2byte 0x11c + 1469 073f 30000000 .4byte 0x30 + 1470 0743 11040000 .4byte .LLST26 + 1471 0747 1C .uleb128 0x1c + 1472 0748 1C000000 .4byte .LVL49 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 27 + + + 1473 074c 8B070000 .4byte 0x78b + 1474 0750 5B070000 .4byte 0x75b + 1475 0754 17 .uleb128 0x17 + 1476 0755 01 .byte 0x1 + 1477 0756 50 .byte 0x50 + 1478 0757 02 .byte 0x2 + 1479 0758 76 .byte 0x76 + 1480 0759 10 .sleb128 16 + 1481 075a 00 .byte 0 + 1482 075b 22 .uleb128 0x22 + 1483 075c 4A000000 .4byte .LVL54 + 1484 0760 01 .byte 0x1 + 1485 0761 9F070000 .4byte 0x79f + 1486 0765 00 .byte 0 + 1487 0766 27 .uleb128 0x27 + 1488 0767 A7020000 .4byte .LASF74 + 1489 076b 01 .byte 0x1 + 1490 076c 44 .byte 0x44 + 1491 076d AA030000 .4byte 0x3aa + 1492 0771 05 .byte 0x5 + 1493 0772 03 .byte 0x3 + 1494 0773 00000000 .4byte default_heap + 1495 0777 28 .uleb128 0x28 + 1496 0778 01 .byte 0x1 + 1497 0779 FB020000 .4byte .LASF75 + 1498 077d 08 .byte 0x8 + 1499 077e 38 .byte 0x38 + 1500 077f 01 .byte 0x1 + 1501 0780 01 .byte 0x1 + 1502 0781 8B070000 .4byte 0x78b + 1503 0785 0F .uleb128 0xf + 1504 0786 A2040000 .4byte 0x4a2 + 1505 078a 00 .byte 0 + 1506 078b 28 .uleb128 0x28 + 1507 078c 01 .byte 0x1 + 1508 078d 8C010000 .4byte .LASF76 + 1509 0791 08 .byte 0x8 + 1510 0792 39 .byte 0x39 + 1511 0793 01 .byte 0x1 + 1512 0794 01 .byte 0x1 + 1513 0795 9F070000 .4byte 0x79f + 1514 0799 0F .uleb128 0xf + 1515 079a A2040000 .4byte 0x4a2 + 1516 079e 00 .byte 0 + 1517 079f 29 .uleb128 0x29 + 1518 07a0 01 .byte 0x1 + 1519 07a1 75000000 .4byte .LASF81 + 1520 07a5 08 .byte 0x8 + 1521 07a6 3D .byte 0x3d + 1522 07a7 01 .byte 0x1 + 1523 07a8 A2040000 .4byte 0x4a2 + 1524 07ac 01 .byte 0x1 + 1525 07ad 00 .byte 0 + 1526 .section .debug_abbrev,"",%progbits + 1527 .Ldebug_abbrev0: + 1528 0000 01 .uleb128 0x1 + 1529 0001 11 .uleb128 0x11 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 28 + + + 1530 0002 01 .byte 0x1 + 1531 0003 25 .uleb128 0x25 + 1532 0004 0E .uleb128 0xe + 1533 0005 13 .uleb128 0x13 + 1534 0006 0B .uleb128 0xb + 1535 0007 03 .uleb128 0x3 + 1536 0008 0E .uleb128 0xe + 1537 0009 1B .uleb128 0x1b + 1538 000a 0E .uleb128 0xe + 1539 000b 55 .uleb128 0x55 + 1540 000c 06 .uleb128 0x6 + 1541 000d 11 .uleb128 0x11 + 1542 000e 01 .uleb128 0x1 + 1543 000f 52 .uleb128 0x52 + 1544 0010 01 .uleb128 0x1 + 1545 0011 10 .uleb128 0x10 + 1546 0012 06 .uleb128 0x6 + 1547 0013 00 .byte 0 + 1548 0014 00 .byte 0 + 1549 0015 02 .uleb128 0x2 + 1550 0016 24 .uleb128 0x24 + 1551 0017 00 .byte 0 + 1552 0018 0B .uleb128 0xb + 1553 0019 0B .uleb128 0xb + 1554 001a 3E .uleb128 0x3e + 1555 001b 0B .uleb128 0xb + 1556 001c 03 .uleb128 0x3 + 1557 001d 08 .uleb128 0x8 + 1558 001e 00 .byte 0 + 1559 001f 00 .byte 0 + 1560 0020 03 .uleb128 0x3 + 1561 0021 16 .uleb128 0x16 + 1562 0022 00 .byte 0 + 1563 0023 03 .uleb128 0x3 + 1564 0024 0E .uleb128 0xe + 1565 0025 3A .uleb128 0x3a + 1566 0026 0B .uleb128 0xb + 1567 0027 3B .uleb128 0x3b + 1568 0028 0B .uleb128 0xb + 1569 0029 49 .uleb128 0x49 + 1570 002a 13 .uleb128 0x13 + 1571 002b 00 .byte 0 + 1572 002c 00 .byte 0 + 1573 002d 04 .uleb128 0x4 + 1574 002e 24 .uleb128 0x24 + 1575 002f 00 .byte 0 + 1576 0030 0B .uleb128 0xb + 1577 0031 0B .uleb128 0xb + 1578 0032 3E .uleb128 0x3e + 1579 0033 0B .uleb128 0xb + 1580 0034 03 .uleb128 0x3 + 1581 0035 0E .uleb128 0xe + 1582 0036 00 .byte 0 + 1583 0037 00 .byte 0 + 1584 0038 05 .uleb128 0x5 + 1585 0039 13 .uleb128 0x13 + 1586 003a 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 29 + + + 1587 003b 03 .uleb128 0x3 + 1588 003c 0E .uleb128 0xe + 1589 003d 0B .uleb128 0xb + 1590 003e 0B .uleb128 0xb + 1591 003f 3A .uleb128 0x3a + 1592 0040 0B .uleb128 0xb + 1593 0041 3B .uleb128 0x3b + 1594 0042 0B .uleb128 0xb + 1595 0043 01 .uleb128 0x1 + 1596 0044 13 .uleb128 0x13 + 1597 0045 00 .byte 0 + 1598 0046 00 .byte 0 + 1599 0047 06 .uleb128 0x6 + 1600 0048 0D .uleb128 0xd + 1601 0049 00 .byte 0 + 1602 004a 03 .uleb128 0x3 + 1603 004b 0E .uleb128 0xe + 1604 004c 3A .uleb128 0x3a + 1605 004d 0B .uleb128 0xb + 1606 004e 3B .uleb128 0x3b + 1607 004f 0B .uleb128 0xb + 1608 0050 49 .uleb128 0x49 + 1609 0051 13 .uleb128 0x13 + 1610 0052 38 .uleb128 0x38 + 1611 0053 0A .uleb128 0xa + 1612 0054 00 .byte 0 + 1613 0055 00 .byte 0 + 1614 0056 07 .uleb128 0x7 + 1615 0057 0D .uleb128 0xd + 1616 0058 00 .byte 0 + 1617 0059 03 .uleb128 0x3 + 1618 005a 08 .uleb128 0x8 + 1619 005b 3A .uleb128 0x3a + 1620 005c 0B .uleb128 0xb + 1621 005d 3B .uleb128 0x3b + 1622 005e 0B .uleb128 0xb + 1623 005f 49 .uleb128 0x49 + 1624 0060 13 .uleb128 0x13 + 1625 0061 38 .uleb128 0x38 + 1626 0062 0A .uleb128 0xa + 1627 0063 00 .byte 0 + 1628 0064 00 .byte 0 + 1629 0065 08 .uleb128 0x8 + 1630 0066 13 .uleb128 0x13 + 1631 0067 01 .byte 0x1 + 1632 0068 0B .uleb128 0xb + 1633 0069 0B .uleb128 0xb + 1634 006a 3A .uleb128 0x3a + 1635 006b 0B .uleb128 0xb + 1636 006c 3B .uleb128 0x3b + 1637 006d 0B .uleb128 0xb + 1638 006e 01 .uleb128 0x1 + 1639 006f 13 .uleb128 0x13 + 1640 0070 00 .byte 0 + 1641 0071 00 .byte 0 + 1642 0072 09 .uleb128 0x9 + 1643 0073 0F .uleb128 0xf + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 30 + + + 1644 0074 00 .byte 0 + 1645 0075 0B .uleb128 0xb + 1646 0076 0B .uleb128 0xb + 1647 0077 49 .uleb128 0x49 + 1648 0078 13 .uleb128 0x13 + 1649 0079 00 .byte 0 + 1650 007a 00 .byte 0 + 1651 007b 0A .uleb128 0xa + 1652 007c 0F .uleb128 0xf + 1653 007d 00 .byte 0 + 1654 007e 0B .uleb128 0xb + 1655 007f 0B .uleb128 0xb + 1656 0080 00 .byte 0 + 1657 0081 00 .byte 0 + 1658 0082 0B .uleb128 0xb + 1659 0083 0D .uleb128 0xd + 1660 0084 00 .byte 0 + 1661 0085 03 .uleb128 0x3 + 1662 0086 08 .uleb128 0x8 + 1663 0087 3A .uleb128 0x3a + 1664 0088 0B .uleb128 0xb + 1665 0089 3B .uleb128 0x3b + 1666 008a 05 .uleb128 0x5 + 1667 008b 49 .uleb128 0x49 + 1668 008c 13 .uleb128 0x13 + 1669 008d 38 .uleb128 0x38 + 1670 008e 0A .uleb128 0xa + 1671 008f 00 .byte 0 + 1672 0090 00 .byte 0 + 1673 0091 0C .uleb128 0xc + 1674 0092 13 .uleb128 0x13 + 1675 0093 01 .byte 0x1 + 1676 0094 03 .uleb128 0x3 + 1677 0095 0E .uleb128 0xe + 1678 0096 0B .uleb128 0xb + 1679 0097 0B .uleb128 0xb + 1680 0098 3A .uleb128 0x3a + 1681 0099 0B .uleb128 0xb + 1682 009a 3B .uleb128 0x3b + 1683 009b 05 .uleb128 0x5 + 1684 009c 01 .uleb128 0x1 + 1685 009d 13 .uleb128 0x13 + 1686 009e 00 .byte 0 + 1687 009f 00 .byte 0 + 1688 00a0 0D .uleb128 0xd + 1689 00a1 35 .uleb128 0x35 + 1690 00a2 00 .byte 0 + 1691 00a3 49 .uleb128 0x49 + 1692 00a4 13 .uleb128 0x13 + 1693 00a5 00 .byte 0 + 1694 00a6 00 .byte 0 + 1695 00a7 0E .uleb128 0xe + 1696 00a8 15 .uleb128 0x15 + 1697 00a9 01 .byte 0x1 + 1698 00aa 27 .uleb128 0x27 + 1699 00ab 0C .uleb128 0xc + 1700 00ac 49 .uleb128 0x49 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 31 + + + 1701 00ad 13 .uleb128 0x13 + 1702 00ae 01 .uleb128 0x1 + 1703 00af 13 .uleb128 0x13 + 1704 00b0 00 .byte 0 + 1705 00b1 00 .byte 0 + 1706 00b2 0F .uleb128 0xf + 1707 00b3 05 .uleb128 0x5 + 1708 00b4 00 .byte 0 + 1709 00b5 49 .uleb128 0x49 + 1710 00b6 13 .uleb128 0x13 + 1711 00b7 00 .byte 0 + 1712 00b8 00 .byte 0 + 1713 00b9 10 .uleb128 0x10 + 1714 00ba 17 .uleb128 0x17 + 1715 00bb 01 .byte 0x1 + 1716 00bc 0B .uleb128 0xb + 1717 00bd 0B .uleb128 0xb + 1718 00be 3A .uleb128 0x3a + 1719 00bf 0B .uleb128 0xb + 1720 00c0 3B .uleb128 0x3b + 1721 00c1 0B .uleb128 0xb + 1722 00c2 01 .uleb128 0x1 + 1723 00c3 13 .uleb128 0x13 + 1724 00c4 00 .byte 0 + 1725 00c5 00 .byte 0 + 1726 00c6 11 .uleb128 0x11 + 1727 00c7 0D .uleb128 0xd + 1728 00c8 00 .byte 0 + 1729 00c9 03 .uleb128 0x3 + 1730 00ca 0E .uleb128 0xe + 1731 00cb 3A .uleb128 0x3a + 1732 00cc 0B .uleb128 0xb + 1733 00cd 3B .uleb128 0x3b + 1734 00ce 0B .uleb128 0xb + 1735 00cf 49 .uleb128 0x49 + 1736 00d0 13 .uleb128 0x13 + 1737 00d1 00 .byte 0 + 1738 00d2 00 .byte 0 + 1739 00d3 12 .uleb128 0x12 + 1740 00d4 17 .uleb128 0x17 + 1741 00d5 01 .byte 0x1 + 1742 00d6 03 .uleb128 0x3 + 1743 00d7 0E .uleb128 0xe + 1744 00d8 0B .uleb128 0xb + 1745 00d9 0B .uleb128 0xb + 1746 00da 3A .uleb128 0x3a + 1747 00db 0B .uleb128 0xb + 1748 00dc 3B .uleb128 0x3b + 1749 00dd 0B .uleb128 0xb + 1750 00de 01 .uleb128 0x1 + 1751 00df 13 .uleb128 0x13 + 1752 00e0 00 .byte 0 + 1753 00e1 00 .byte 0 + 1754 00e2 13 .uleb128 0x13 + 1755 00e3 0D .uleb128 0xd + 1756 00e4 00 .byte 0 + 1757 00e5 03 .uleb128 0x3 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 32 + + + 1758 00e6 08 .uleb128 0x8 + 1759 00e7 3A .uleb128 0x3a + 1760 00e8 0B .uleb128 0xb + 1761 00e9 3B .uleb128 0x3b + 1762 00ea 0B .uleb128 0xb + 1763 00eb 49 .uleb128 0x49 + 1764 00ec 13 .uleb128 0x13 + 1765 00ed 00 .byte 0 + 1766 00ee 00 .byte 0 + 1767 00ef 14 .uleb128 0x14 + 1768 00f0 26 .uleb128 0x26 + 1769 00f1 00 .byte 0 + 1770 00f2 49 .uleb128 0x49 + 1771 00f3 13 .uleb128 0x13 + 1772 00f4 00 .byte 0 + 1773 00f5 00 .byte 0 + 1774 00f6 15 .uleb128 0x15 + 1775 00f7 2E .uleb128 0x2e + 1776 00f8 01 .byte 0x1 + 1777 00f9 3F .uleb128 0x3f + 1778 00fa 0C .uleb128 0xc + 1779 00fb 03 .uleb128 0x3 + 1780 00fc 0E .uleb128 0xe + 1781 00fd 3A .uleb128 0x3a + 1782 00fe 0B .uleb128 0xb + 1783 00ff 3B .uleb128 0x3b + 1784 0100 0B .uleb128 0xb + 1785 0101 27 .uleb128 0x27 + 1786 0102 0C .uleb128 0xc + 1787 0103 11 .uleb128 0x11 + 1788 0104 01 .uleb128 0x1 + 1789 0105 12 .uleb128 0x12 + 1790 0106 01 .uleb128 0x1 + 1791 0107 40 .uleb128 0x40 + 1792 0108 0A .uleb128 0xa + 1793 0109 9742 .uleb128 0x2117 + 1794 010b 0C .uleb128 0xc + 1795 010c 01 .uleb128 0x1 + 1796 010d 13 .uleb128 0x13 + 1797 010e 00 .byte 0 + 1798 010f 00 .byte 0 + 1799 0110 16 .uleb128 0x16 + 1800 0111 898201 .uleb128 0x4109 + 1801 0114 01 .byte 0x1 + 1802 0115 11 .uleb128 0x11 + 1803 0116 01 .uleb128 0x1 + 1804 0117 9542 .uleb128 0x2115 + 1805 0119 0C .uleb128 0xc + 1806 011a 31 .uleb128 0x31 + 1807 011b 13 .uleb128 0x13 + 1808 011c 00 .byte 0 + 1809 011d 00 .byte 0 + 1810 011e 17 .uleb128 0x17 + 1811 011f 8A8201 .uleb128 0x410a + 1812 0122 00 .byte 0 + 1813 0123 02 .uleb128 0x2 + 1814 0124 0A .uleb128 0xa + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 33 + + + 1815 0125 9142 .uleb128 0x2111 + 1816 0127 0A .uleb128 0xa + 1817 0128 00 .byte 0 + 1818 0129 00 .byte 0 + 1819 012a 18 .uleb128 0x18 + 1820 012b 05 .uleb128 0x5 + 1821 012c 00 .byte 0 + 1822 012d 03 .uleb128 0x3 + 1823 012e 0E .uleb128 0xe + 1824 012f 3A .uleb128 0x3a + 1825 0130 0B .uleb128 0xb + 1826 0131 3B .uleb128 0x3b + 1827 0132 0B .uleb128 0xb + 1828 0133 49 .uleb128 0x49 + 1829 0134 13 .uleb128 0x13 + 1830 0135 02 .uleb128 0x2 + 1831 0136 06 .uleb128 0x6 + 1832 0137 00 .byte 0 + 1833 0138 00 .byte 0 + 1834 0139 19 .uleb128 0x19 + 1835 013a 05 .uleb128 0x5 + 1836 013b 00 .byte 0 + 1837 013c 03 .uleb128 0x3 + 1838 013d 08 .uleb128 0x8 + 1839 013e 3A .uleb128 0x3a + 1840 013f 0B .uleb128 0xb + 1841 0140 3B .uleb128 0x3b + 1842 0141 0B .uleb128 0xb + 1843 0142 49 .uleb128 0x49 + 1844 0143 13 .uleb128 0x13 + 1845 0144 02 .uleb128 0x2 + 1846 0145 06 .uleb128 0x6 + 1847 0146 00 .byte 0 + 1848 0147 00 .byte 0 + 1849 0148 1A .uleb128 0x1a + 1850 0149 34 .uleb128 0x34 + 1851 014a 00 .byte 0 + 1852 014b 03 .uleb128 0x3 + 1853 014c 08 .uleb128 0x8 + 1854 014d 3A .uleb128 0x3a + 1855 014e 0B .uleb128 0xb + 1856 014f 3B .uleb128 0x3b + 1857 0150 0B .uleb128 0xb + 1858 0151 49 .uleb128 0x49 + 1859 0152 13 .uleb128 0x13 + 1860 0153 02 .uleb128 0x2 + 1861 0154 06 .uleb128 0x6 + 1862 0155 00 .byte 0 + 1863 0156 00 .byte 0 + 1864 0157 1B .uleb128 0x1b + 1865 0158 2E .uleb128 0x2e + 1866 0159 01 .byte 0x1 + 1867 015a 3F .uleb128 0x3f + 1868 015b 0C .uleb128 0xc + 1869 015c 03 .uleb128 0x3 + 1870 015d 0E .uleb128 0xe + 1871 015e 3A .uleb128 0x3a + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 34 + + + 1872 015f 0B .uleb128 0xb + 1873 0160 3B .uleb128 0x3b + 1874 0161 0B .uleb128 0xb + 1875 0162 27 .uleb128 0x27 + 1876 0163 0C .uleb128 0xc + 1877 0164 49 .uleb128 0x49 + 1878 0165 13 .uleb128 0x13 + 1879 0166 11 .uleb128 0x11 + 1880 0167 01 .uleb128 0x1 + 1881 0168 12 .uleb128 0x12 + 1882 0169 01 .uleb128 0x1 + 1883 016a 40 .uleb128 0x40 + 1884 016b 06 .uleb128 0x6 + 1885 016c 9742 .uleb128 0x2117 + 1886 016e 0C .uleb128 0xc + 1887 016f 01 .uleb128 0x1 + 1888 0170 13 .uleb128 0x13 + 1889 0171 00 .byte 0 + 1890 0172 00 .byte 0 + 1891 0173 1C .uleb128 0x1c + 1892 0174 898201 .uleb128 0x4109 + 1893 0177 01 .byte 0x1 + 1894 0178 11 .uleb128 0x11 + 1895 0179 01 .uleb128 0x1 + 1896 017a 31 .uleb128 0x31 + 1897 017b 13 .uleb128 0x13 + 1898 017c 01 .uleb128 0x1 + 1899 017d 13 .uleb128 0x13 + 1900 017e 00 .byte 0 + 1901 017f 00 .byte 0 + 1902 0180 1D .uleb128 0x1d + 1903 0181 898201 .uleb128 0x4109 + 1904 0184 00 .byte 0 + 1905 0185 11 .uleb128 0x11 + 1906 0186 01 .uleb128 0x1 + 1907 0187 31 .uleb128 0x31 + 1908 0188 13 .uleb128 0x13 + 1909 0189 00 .byte 0 + 1910 018a 00 .byte 0 + 1911 018b 1E .uleb128 0x1e + 1912 018c 898201 .uleb128 0x4109 + 1913 018f 01 .byte 0x1 + 1914 0190 11 .uleb128 0x11 + 1915 0191 01 .uleb128 0x1 + 1916 0192 00 .byte 0 + 1917 0193 00 .byte 0 + 1918 0194 1F .uleb128 0x1f + 1919 0195 2E .uleb128 0x2e + 1920 0196 01 .byte 0x1 + 1921 0197 3F .uleb128 0x3f + 1922 0198 0C .uleb128 0xc + 1923 0199 03 .uleb128 0x3 + 1924 019a 0E .uleb128 0xe + 1925 019b 3A .uleb128 0x3a + 1926 019c 0B .uleb128 0xb + 1927 019d 3B .uleb128 0x3b + 1928 019e 0B .uleb128 0xb + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 35 + + + 1929 019f 27 .uleb128 0x27 + 1930 01a0 0C .uleb128 0xc + 1931 01a1 11 .uleb128 0x11 + 1932 01a2 01 .uleb128 0x1 + 1933 01a3 12 .uleb128 0x12 + 1934 01a4 01 .uleb128 0x1 + 1935 01a5 40 .uleb128 0x40 + 1936 01a6 06 .uleb128 0x6 + 1937 01a7 9742 .uleb128 0x2117 + 1938 01a9 0C .uleb128 0xc + 1939 01aa 01 .uleb128 0x1 + 1940 01ab 13 .uleb128 0x13 + 1941 01ac 00 .byte 0 + 1942 01ad 00 .byte 0 + 1943 01ae 20 .uleb128 0x20 + 1944 01af 34 .uleb128 0x34 + 1945 01b0 00 .byte 0 + 1946 01b1 03 .uleb128 0x3 + 1947 01b2 08 .uleb128 0x8 + 1948 01b3 3A .uleb128 0x3a + 1949 01b4 0B .uleb128 0xb + 1950 01b5 3B .uleb128 0x3b + 1951 01b6 0B .uleb128 0xb + 1952 01b7 49 .uleb128 0x49 + 1953 01b8 13 .uleb128 0x13 + 1954 01b9 02 .uleb128 0x2 + 1955 01ba 0A .uleb128 0xa + 1956 01bb 00 .byte 0 + 1957 01bc 00 .byte 0 + 1958 01bd 21 .uleb128 0x21 + 1959 01be 34 .uleb128 0x34 + 1960 01bf 00 .byte 0 + 1961 01c0 03 .uleb128 0x3 + 1962 01c1 0E .uleb128 0xe + 1963 01c2 3A .uleb128 0x3a + 1964 01c3 0B .uleb128 0xb + 1965 01c4 3B .uleb128 0x3b + 1966 01c5 0B .uleb128 0xb + 1967 01c6 49 .uleb128 0x49 + 1968 01c7 13 .uleb128 0x13 + 1969 01c8 02 .uleb128 0x2 + 1970 01c9 06 .uleb128 0x6 + 1971 01ca 00 .byte 0 + 1972 01cb 00 .byte 0 + 1973 01cc 22 .uleb128 0x22 + 1974 01cd 898201 .uleb128 0x4109 + 1975 01d0 00 .byte 0 + 1976 01d1 11 .uleb128 0x11 + 1977 01d2 01 .uleb128 0x1 + 1978 01d3 9542 .uleb128 0x2115 + 1979 01d5 0C .uleb128 0xc + 1980 01d6 31 .uleb128 0x31 + 1981 01d7 13 .uleb128 0x13 + 1982 01d8 00 .byte 0 + 1983 01d9 00 .byte 0 + 1984 01da 23 .uleb128 0x23 + 1985 01db 2E .uleb128 0x2e + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 36 + + + 1986 01dc 01 .byte 0x1 + 1987 01dd 3F .uleb128 0x3f + 1988 01de 0C .uleb128 0xc + 1989 01df 03 .uleb128 0x3 + 1990 01e0 0E .uleb128 0xe + 1991 01e1 3A .uleb128 0x3a + 1992 01e2 0B .uleb128 0xb + 1993 01e3 3B .uleb128 0x3b + 1994 01e4 05 .uleb128 0x5 + 1995 01e5 27 .uleb128 0x27 + 1996 01e6 0C .uleb128 0xc + 1997 01e7 11 .uleb128 0x11 + 1998 01e8 01 .uleb128 0x1 + 1999 01e9 12 .uleb128 0x12 + 2000 01ea 01 .uleb128 0x1 + 2001 01eb 40 .uleb128 0x40 + 2002 01ec 06 .uleb128 0x6 + 2003 01ed 9742 .uleb128 0x2117 + 2004 01ef 0C .uleb128 0xc + 2005 01f0 01 .uleb128 0x1 + 2006 01f1 13 .uleb128 0x13 + 2007 01f2 00 .byte 0 + 2008 01f3 00 .byte 0 + 2009 01f4 24 .uleb128 0x24 + 2010 01f5 05 .uleb128 0x5 + 2011 01f6 00 .byte 0 + 2012 01f7 03 .uleb128 0x3 + 2013 01f8 0E .uleb128 0xe + 2014 01f9 3A .uleb128 0x3a + 2015 01fa 0B .uleb128 0xb + 2016 01fb 3B .uleb128 0x3b + 2017 01fc 05 .uleb128 0x5 + 2018 01fd 49 .uleb128 0x49 + 2019 01fe 13 .uleb128 0x13 + 2020 01ff 02 .uleb128 0x2 + 2021 0200 06 .uleb128 0x6 + 2022 0201 00 .byte 0 + 2023 0202 00 .byte 0 + 2024 0203 25 .uleb128 0x25 + 2025 0204 05 .uleb128 0x5 + 2026 0205 00 .byte 0 + 2027 0206 03 .uleb128 0x3 + 2028 0207 08 .uleb128 0x8 + 2029 0208 3A .uleb128 0x3a + 2030 0209 0B .uleb128 0xb + 2031 020a 3B .uleb128 0x3b + 2032 020b 05 .uleb128 0x5 + 2033 020c 49 .uleb128 0x49 + 2034 020d 13 .uleb128 0x13 + 2035 020e 02 .uleb128 0x2 + 2036 020f 06 .uleb128 0x6 + 2037 0210 00 .byte 0 + 2038 0211 00 .byte 0 + 2039 0212 26 .uleb128 0x26 + 2040 0213 34 .uleb128 0x34 + 2041 0214 00 .byte 0 + 2042 0215 03 .uleb128 0x3 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 37 + + + 2043 0216 08 .uleb128 0x8 + 2044 0217 3A .uleb128 0x3a + 2045 0218 0B .uleb128 0xb + 2046 0219 3B .uleb128 0x3b + 2047 021a 05 .uleb128 0x5 + 2048 021b 49 .uleb128 0x49 + 2049 021c 13 .uleb128 0x13 + 2050 021d 02 .uleb128 0x2 + 2051 021e 06 .uleb128 0x6 + 2052 021f 00 .byte 0 + 2053 0220 00 .byte 0 + 2054 0221 27 .uleb128 0x27 + 2055 0222 34 .uleb128 0x34 + 2056 0223 00 .byte 0 + 2057 0224 03 .uleb128 0x3 + 2058 0225 0E .uleb128 0xe + 2059 0226 3A .uleb128 0x3a + 2060 0227 0B .uleb128 0xb + 2061 0228 3B .uleb128 0x3b + 2062 0229 0B .uleb128 0xb + 2063 022a 49 .uleb128 0x49 + 2064 022b 13 .uleb128 0x13 + 2065 022c 02 .uleb128 0x2 + 2066 022d 0A .uleb128 0xa + 2067 022e 00 .byte 0 + 2068 022f 00 .byte 0 + 2069 0230 28 .uleb128 0x28 + 2070 0231 2E .uleb128 0x2e + 2071 0232 01 .byte 0x1 + 2072 0233 3F .uleb128 0x3f + 2073 0234 0C .uleb128 0xc + 2074 0235 03 .uleb128 0x3 + 2075 0236 0E .uleb128 0xe + 2076 0237 3A .uleb128 0x3a + 2077 0238 0B .uleb128 0xb + 2078 0239 3B .uleb128 0x3b + 2079 023a 0B .uleb128 0xb + 2080 023b 27 .uleb128 0x27 + 2081 023c 0C .uleb128 0xc + 2082 023d 3C .uleb128 0x3c + 2083 023e 0C .uleb128 0xc + 2084 023f 01 .uleb128 0x1 + 2085 0240 13 .uleb128 0x13 + 2086 0241 00 .byte 0 + 2087 0242 00 .byte 0 + 2088 0243 29 .uleb128 0x29 + 2089 0244 2E .uleb128 0x2e + 2090 0245 00 .byte 0 + 2091 0246 3F .uleb128 0x3f + 2092 0247 0C .uleb128 0xc + 2093 0248 03 .uleb128 0x3 + 2094 0249 0E .uleb128 0xe + 2095 024a 3A .uleb128 0x3a + 2096 024b 0B .uleb128 0xb + 2097 024c 3B .uleb128 0x3b + 2098 024d 0B .uleb128 0xb + 2099 024e 27 .uleb128 0x27 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 38 + + + 2100 024f 0C .uleb128 0xc + 2101 0250 49 .uleb128 0x49 + 2102 0251 13 .uleb128 0x13 + 2103 0252 3C .uleb128 0x3c + 2104 0253 0C .uleb128 0xc + 2105 0254 00 .byte 0 + 2106 0255 00 .byte 0 + 2107 0256 00 .byte 0 + 2108 .section .debug_loc,"",%progbits + 2109 .Ldebug_loc0: + 2110 .LLST0: + 2111 0000 00000000 .4byte .LVL1 + 2112 0004 0C000000 .4byte .LVL4 + 2113 0008 0100 .2byte 0x1 + 2114 000a 50 .byte 0x50 + 2115 000b 0C000000 .4byte .LVL4 + 2116 000f 13000000 .4byte .LVL5-1 + 2117 0013 0300 .2byte 0x3 + 2118 0015 70 .byte 0x70 + 2119 0016 70 .sleb128 -16 + 2120 0017 9F .byte 0x9f + 2121 0018 13000000 .4byte .LVL5-1 + 2122 001c 14000000 .4byte .LFE8 + 2123 0020 0400 .2byte 0x4 + 2124 0022 F3 .byte 0xf3 + 2125 0023 01 .uleb128 0x1 + 2126 0024 50 .byte 0x50 + 2127 0025 9F .byte 0x9f + 2128 0026 00000000 .4byte 0 + 2129 002a 00000000 .4byte 0 + 2130 .LLST1: + 2131 002e 00000000 .4byte .LVL1 + 2132 0032 13000000 .4byte .LVL5-1 + 2133 0036 0100 .2byte 0x1 + 2134 0038 51 .byte 0x51 + 2135 0039 13000000 .4byte .LVL5-1 + 2136 003d 14000000 .4byte .LFE8 + 2137 0041 0400 .2byte 0x4 + 2138 0043 F3 .byte 0xf3 + 2139 0044 01 .uleb128 0x1 + 2140 0045 51 .byte 0x51 + 2141 0046 9F .byte 0x9f + 2142 0047 00000000 .4byte 0 + 2143 004b 00000000 .4byte 0 + 2144 .LLST2: + 2145 004f 00000000 .4byte .LVL1 + 2146 0053 0A000000 .4byte .LVL3 + 2147 0057 0100 .2byte 0x1 + 2148 0059 52 .byte 0x52 + 2149 005a 0A000000 .4byte .LVL3 + 2150 005e 13000000 .4byte .LVL5-1 + 2151 0062 0300 .2byte 0x3 + 2152 0064 72 .byte 0x72 + 2153 0065 08 .sleb128 8 + 2154 0066 9F .byte 0x9f + 2155 0067 13000000 .4byte .LVL5-1 + 2156 006b 14000000 .4byte .LFE8 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 39 + + + 2157 006f 0400 .2byte 0x4 + 2158 0071 F3 .byte 0xf3 + 2159 0072 01 .uleb128 0x1 + 2160 0073 52 .byte 0x52 + 2161 0074 9F .byte 0x9f + 2162 0075 00000000 .4byte 0 + 2163 0079 00000000 .4byte 0 + 2164 .LLST3: + 2165 007d 04000000 .4byte .LVL2 + 2166 0081 13000000 .4byte .LVL5-1 + 2167 0085 0100 .2byte 0x1 + 2168 0087 51 .byte 0x51 + 2169 0088 13000000 .4byte .LVL5-1 + 2170 008c 14000000 .4byte .LFE8 + 2171 0090 0400 .2byte 0x4 + 2172 0092 F3 .byte 0xf3 + 2173 0093 01 .uleb128 0x1 + 2174 0094 51 .byte 0x51 + 2175 0095 9F .byte 0x9f + 2176 0096 00000000 .4byte 0 + 2177 009a 00000000 .4byte 0 + 2178 .LLST4: + 2179 009e 00000000 .4byte .LFB9 + 2180 00a2 02000000 .4byte .LCFI0 + 2181 00a6 0200 .2byte 0x2 + 2182 00a8 7D .byte 0x7d + 2183 00a9 00 .sleb128 0 + 2184 00aa 02000000 .4byte .LCFI0 + 2185 00ae 84000000 .4byte .LFE9 + 2186 00b2 0200 .2byte 0x2 + 2187 00b4 7D .byte 0x7d + 2188 00b5 18 .sleb128 24 + 2189 00b6 00000000 .4byte 0 + 2190 00ba 00000000 .4byte 0 + 2191 .LLST5: + 2192 00be 00000000 .4byte .LVL6 + 2193 00c2 0C000000 .4byte .LVL8 + 2194 00c6 0100 .2byte 0x1 + 2195 00c8 50 .byte 0x50 + 2196 00c9 0C000000 .4byte .LVL8 + 2197 00cd 84000000 .4byte .LFE9 + 2198 00d1 0100 .2byte 0x1 + 2199 00d3 56 .byte 0x56 + 2200 00d4 00000000 .4byte 0 + 2201 00d8 00000000 .4byte 0 + 2202 .LLST6: + 2203 00dc 00000000 .4byte .LVL6 + 2204 00e0 06000000 .4byte .LVL7 + 2205 00e4 0100 .2byte 0x1 + 2206 00e6 51 .byte 0x51 + 2207 00e7 06000000 .4byte .LVL7 + 2208 00eb 14000000 .4byte .LVL9 + 2209 00ef 0300 .2byte 0x3 + 2210 00f1 71 .byte 0x71 + 2211 00f2 79 .sleb128 -7 + 2212 00f3 9F .byte 0x9f + 2213 00f4 14000000 .4byte .LVL9 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 40 + + + 2214 00f8 84000000 .4byte .LFE9 + 2215 00fc 0100 .2byte 0x1 + 2216 00fe 55 .byte 0x55 + 2217 00ff 00000000 .4byte 0 + 2218 0103 00000000 .4byte 0 + 2219 .LLST7: + 2220 0107 18000000 .4byte .LVL10 + 2221 010b 4C000000 .4byte .LVL17 + 2222 010f 0100 .2byte 0x1 + 2223 0111 54 .byte 0x54 + 2224 0112 58000000 .4byte .LVL19 + 2225 0116 72000000 .4byte .LVL22 + 2226 011a 0100 .2byte 0x1 + 2227 011c 54 .byte 0x54 + 2228 011d 7A000000 .4byte .LVL24 + 2229 0121 7C000000 .4byte .LVL25 + 2230 0125 0100 .2byte 0x1 + 2231 0127 54 .byte 0x54 + 2232 0128 00000000 .4byte 0 + 2233 012c 00000000 .4byte 0 + 2234 .LLST8: + 2235 0130 1E000000 .4byte .LVL12 + 2236 0134 20000000 .4byte .LVL13 + 2237 0138 0100 .2byte 0x1 + 2238 013a 53 .byte 0x53 + 2239 013b 22000000 .4byte .LVL14 + 2240 013f 53000000 .4byte .LVL18-1 + 2241 0143 0100 .2byte 0x1 + 2242 0145 53 .byte 0x53 + 2243 0146 53000000 .4byte .LVL18-1 + 2244 014a 54000000 .4byte .LVL18 + 2245 014e 0300 .2byte 0x3 + 2246 0150 74 .byte 0x74 + 2247 0151 78 .sleb128 -8 + 2248 0152 9F .byte 0x9f + 2249 0153 58000000 .4byte .LVL19 + 2250 0157 61000000 .4byte .LVL20-1 + 2251 015b 0100 .2byte 0x1 + 2252 015d 53 .byte 0x53 + 2253 015e 6C000000 .4byte .LVL21 + 2254 0162 76000000 .4byte .LVL23 + 2255 0166 0100 .2byte 0x1 + 2256 0168 50 .byte 0x50 + 2257 0169 76000000 .4byte .LVL23 + 2258 016d 7A000000 .4byte .LVL24 + 2259 0171 0100 .2byte 0x1 + 2260 0173 54 .byte 0x54 + 2261 0174 00000000 .4byte 0 + 2262 0178 00000000 .4byte 0 + 2263 .LLST9: + 2264 017c 42000000 .4byte .LVL15 + 2265 0180 4A000000 .4byte .LVL16 + 2266 0184 0100 .2byte 0x1 + 2267 0186 57 .byte 0x57 + 2268 0187 00000000 .4byte 0 + 2269 018b 00000000 .4byte 0 + 2270 .LLST10: + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 41 + + + 2271 018f 00000000 .4byte .LFB10 + 2272 0193 02000000 .4byte .LCFI1 + 2273 0197 0200 .2byte 0x2 + 2274 0199 7D .byte 0x7d + 2275 019a 00 .sleb128 0 + 2276 019b 02000000 .4byte .LCFI1 + 2277 019f 86000000 .4byte .LFE10 + 2278 01a3 0200 .2byte 0x2 + 2279 01a5 7D .byte 0x7d + 2280 01a6 10 .sleb128 16 + 2281 01a7 00000000 .4byte 0 + 2282 01ab 00000000 .4byte 0 + 2283 .LLST11: + 2284 01af 00000000 .4byte .LVL26 + 2285 01b3 08000000 .4byte .LVL27 + 2286 01b7 0100 .2byte 0x1 + 2287 01b9 50 .byte 0x50 + 2288 01ba 08000000 .4byte .LVL27 + 2289 01be 86000000 .4byte .LFE10 + 2290 01c2 0100 .2byte 0x1 + 2291 01c4 56 .byte 0x56 + 2292 01c5 00000000 .4byte 0 + 2293 01c9 00000000 .4byte 0 + 2294 .LLST12: + 2295 01cd 10000000 .4byte .LVL29 + 2296 01d1 18000000 .4byte .LVL32 + 2297 01d5 0100 .2byte 0x1 + 2298 01d7 55 .byte 0x55 + 2299 01d8 18000000 .4byte .LVL32 + 2300 01dc 28000000 .4byte .LVL33 + 2301 01e0 0100 .2byte 0x1 + 2302 01e2 53 .byte 0x53 + 2303 01e3 28000000 .4byte .LVL33 + 2304 01e7 2C000000 .4byte .LVL34 + 2305 01eb 0100 .2byte 0x1 + 2306 01ed 52 .byte 0x52 + 2307 01ee 2C000000 .4byte .LVL34 + 2308 01f2 57000000 .4byte .LVL36-1 + 2309 01f6 0100 .2byte 0x1 + 2310 01f8 53 .byte 0x53 + 2311 01f9 58000000 .4byte .LVL36 + 2312 01fd 86000000 .4byte .LFE10 + 2313 0201 0100 .2byte 0x1 + 2314 0203 53 .byte 0x53 + 2315 0204 00000000 .4byte 0 + 2316 0208 00000000 .4byte 0 + 2317 .LLST13: + 2318 020c 0C000000 .4byte .LVL28 + 2319 0210 12000000 .4byte .LVL30 + 2320 0214 0100 .2byte 0x1 + 2321 0216 50 .byte 0x50 + 2322 0217 12000000 .4byte .LVL30 + 2323 021b 15000000 .4byte .LVL31-1 + 2324 021f 0200 .2byte 0x2 + 2325 0221 74 .byte 0x74 + 2326 0222 00 .sleb128 0 + 2327 0223 15000000 .4byte .LVL31-1 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 42 + + + 2328 0227 3E000000 .4byte .LVL35 + 2329 022b 0300 .2byte 0x3 + 2330 022d 75 .byte 0x75 + 2331 022e 78 .sleb128 -8 + 2332 022f 9F .byte 0x9f + 2333 0230 00000000 .4byte 0 + 2334 0234 00000000 .4byte 0 + 2335 .LLST14: + 2336 0238 00000000 .4byte .LFB11 + 2337 023c 02000000 .4byte .LCFI2 + 2338 0240 0200 .2byte 0x2 + 2339 0242 7D .byte 0x7d + 2340 0243 00 .sleb128 0 + 2341 0244 02000000 .4byte .LCFI2 + 2342 0248 40000000 .4byte .LFE11 + 2343 024c 0200 .2byte 0x2 + 2344 024e 7D .byte 0x7d + 2345 024f 10 .sleb128 16 + 2346 0250 00000000 .4byte 0 + 2347 0254 00000000 .4byte 0 + 2348 .LLST15: + 2349 0258 00000000 .4byte .LVL37 + 2350 025c 0C000000 .4byte .LVL38 + 2351 0260 0100 .2byte 0x1 + 2352 0262 50 .byte 0x50 + 2353 0263 0C000000 .4byte .LVL38 + 2354 0267 1C000000 .4byte .LVL40 + 2355 026b 0100 .2byte 0x1 + 2356 026d 54 .byte 0x54 + 2357 026e 1C000000 .4byte .LVL40 + 2358 0272 34000000 .4byte .LVL45 + 2359 0276 1300 .2byte 0x13 + 2360 0278 F3 .byte 0xf3 + 2361 0279 01 .uleb128 0x1 + 2362 027a 50 .byte 0x50 + 2363 027b 03 .byte 0x3 + 2364 027c 00000000 .4byte .LANCHOR0 + 2365 0280 F3 .byte 0xf3 + 2366 0281 01 .uleb128 0x1 + 2367 0282 50 .byte 0x50 + 2368 0283 30 .byte 0x30 + 2369 0284 2E .byte 0x2e + 2370 0285 28 .byte 0x28 + 2371 0286 0100 .2byte 0x1 + 2372 0288 16 .byte 0x16 + 2373 0289 13 .byte 0x13 + 2374 028a 9F .byte 0x9f + 2375 028b 34000000 .4byte .LVL45 + 2376 028f 38000000 .4byte .LVL46 + 2377 0293 0100 .2byte 0x1 + 2378 0295 54 .byte 0x54 + 2379 0296 38000000 .4byte .LVL46 + 2380 029a 40000000 .4byte .LFE11 + 2381 029e 1300 .2byte 0x13 + 2382 02a0 F3 .byte 0xf3 + 2383 02a1 01 .uleb128 0x1 + 2384 02a2 50 .byte 0x50 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 43 + + + 2385 02a3 03 .byte 0x3 + 2386 02a4 00000000 .4byte .LANCHOR0 + 2387 02a8 F3 .byte 0xf3 + 2388 02a9 01 .uleb128 0x1 + 2389 02aa 50 .byte 0x50 + 2390 02ab 30 .byte 0x30 + 2391 02ac 2E .byte 0x2e + 2392 02ad 28 .byte 0x28 + 2393 02ae 0100 .2byte 0x1 + 2394 02b0 16 .byte 0x16 + 2395 02b1 13 .byte 0x13 + 2396 02b2 9F .byte 0x9f + 2397 02b3 00000000 .4byte 0 + 2398 02b7 00000000 .4byte 0 + 2399 .LLST16: + 2400 02bb 00000000 .4byte .LVL37 + 2401 02bf 13000000 .4byte .LVL39-1 + 2402 02c3 0100 .2byte 0x1 + 2403 02c5 51 .byte 0x51 + 2404 02c6 13000000 .4byte .LVL39-1 + 2405 02ca 40000000 .4byte .LFE11 + 2406 02ce 0100 .2byte 0x1 + 2407 02d0 55 .byte 0x55 + 2408 02d1 00000000 .4byte 0 + 2409 02d5 00000000 .4byte 0 + 2410 .LLST17: + 2411 02d9 14000000 .4byte .LVL39 + 2412 02dd 1C000000 .4byte .LVL40 + 2413 02e1 0300 .2byte 0x3 + 2414 02e3 74 .byte 0x74 + 2415 02e4 08 .sleb128 8 + 2416 02e5 9F .byte 0x9f + 2417 02e6 34000000 .4byte .LVL45 + 2418 02ea 38000000 .4byte .LVL46 + 2419 02ee 0300 .2byte 0x3 + 2420 02f0 74 .byte 0x74 + 2421 02f1 08 .sleb128 8 + 2422 02f2 9F .byte 0x9f + 2423 02f3 38000000 .4byte .LVL46 + 2424 02f7 40000000 .4byte .LFE11 + 2425 02fb 1500 .2byte 0x15 + 2426 02fd F3 .byte 0xf3 + 2427 02fe 01 .uleb128 0x1 + 2428 02ff 50 .byte 0x50 + 2429 0300 03 .byte 0x3 + 2430 0301 00000000 .4byte .LANCHOR0 + 2431 0305 F3 .byte 0xf3 + 2432 0306 01 .uleb128 0x1 + 2433 0307 50 .byte 0x50 + 2434 0308 30 .byte 0x30 + 2435 0309 2E .byte 0x2e + 2436 030a 28 .byte 0x28 + 2437 030b 0100 .2byte 0x1 + 2438 030d 16 .byte 0x16 + 2439 030e 13 .byte 0x13 + 2440 030f 23 .byte 0x23 + 2441 0310 08 .uleb128 0x8 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 44 + + + 2442 0311 9F .byte 0x9f + 2443 0312 00000000 .4byte 0 + 2444 0316 00000000 .4byte 0 + 2445 .LLST18: + 2446 031a 14000000 .4byte .LVL39 + 2447 031e 1C000000 .4byte .LVL40 + 2448 0322 0200 .2byte 0x2 + 2449 0324 30 .byte 0x30 + 2450 0325 9F .byte 0x9f + 2451 0326 24000000 .4byte .LVL42 + 2452 032a 28000000 .4byte .LVL43 + 2453 032e 0100 .2byte 0x1 + 2454 0330 54 .byte 0x54 + 2455 0331 34000000 .4byte .LVL45 + 2456 0335 40000000 .4byte .LFE11 + 2457 0339 0200 .2byte 0x2 + 2458 033b 30 .byte 0x30 + 2459 033c 9F .byte 0x9f + 2460 033d 00000000 .4byte 0 + 2461 0341 00000000 .4byte 0 + 2462 .LLST19: + 2463 0345 14000000 .4byte .LVL39 + 2464 0349 1C000000 .4byte .LVL40 + 2465 034d 0200 .2byte 0x2 + 2466 034f 30 .byte 0x30 + 2467 0350 9F .byte 0x9f + 2468 0351 22000000 .4byte .LVL41 + 2469 0355 28000000 .4byte .LVL43 + 2470 0359 0100 .2byte 0x1 + 2471 035b 52 .byte 0x52 + 2472 035c 34000000 .4byte .LVL45 + 2473 0360 40000000 .4byte .LFE11 + 2474 0364 0200 .2byte 0x2 + 2475 0366 30 .byte 0x30 + 2476 0367 9F .byte 0x9f + 2477 0368 00000000 .4byte 0 + 2478 036c 00000000 .4byte 0 + 2479 .LLST20: + 2480 0370 00000000 .4byte .LFB12 + 2481 0374 02000000 .4byte .LCFI3 + 2482 0378 0200 .2byte 0x2 + 2483 037a 7D .byte 0x7d + 2484 037b 00 .sleb128 0 + 2485 037c 02000000 .4byte .LCFI3 + 2486 0380 50000000 .4byte .LFE12 + 2487 0384 0200 .2byte 0x2 + 2488 0386 7D .byte 0x7d + 2489 0387 10 .sleb128 16 + 2490 0388 00000000 .4byte 0 + 2491 038c 00000000 .4byte 0 + 2492 .LLST21: + 2493 0390 00000000 .4byte .LVL47 + 2494 0394 0C000000 .4byte .LVL48 + 2495 0398 0100 .2byte 0x1 + 2496 039a 50 .byte 0x50 + 2497 039b 0C000000 .4byte .LVL48 + 2498 039f 50000000 .4byte .LFE12 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 45 + + + 2499 03a3 0100 .2byte 0x1 + 2500 03a5 56 .byte 0x56 + 2501 03a6 00000000 .4byte 0 + 2502 03aa 00000000 .4byte 0 + 2503 .LLST22: + 2504 03ae 00000000 .4byte .LVL47 + 2505 03b2 1B000000 .4byte .LVL49-1 + 2506 03b6 0100 .2byte 0x1 + 2507 03b8 51 .byte 0x51 + 2508 03b9 1B000000 .4byte .LVL49-1 + 2509 03bd 50000000 .4byte .LFE12 + 2510 03c1 0100 .2byte 0x1 + 2511 03c3 54 .byte 0x54 + 2512 03c4 00000000 .4byte 0 + 2513 03c8 00000000 .4byte 0 + 2514 .LLST23: + 2515 03cc 00000000 .4byte .LVL47 + 2516 03d0 1B000000 .4byte .LVL49-1 + 2517 03d4 0100 .2byte 0x1 + 2518 03d6 52 .byte 0x52 + 2519 03d7 1B000000 .4byte .LVL49-1 + 2520 03db 50000000 .4byte .LFE12 + 2521 03df 0100 .2byte 0x1 + 2522 03e1 55 .byte 0x55 + 2523 03e2 00000000 .4byte 0 + 2524 03e6 00000000 .4byte 0 + 2525 .LLST24: + 2526 03ea 22000000 .4byte .LVL50 + 2527 03ee 49000000 .4byte .LVL54-1 + 2528 03f2 0100 .2byte 0x1 + 2529 03f4 50 .byte 0x50 + 2530 03f5 00000000 .4byte 0 + 2531 03f9 00000000 .4byte 0 + 2532 .LLST25: + 2533 03fd 1C000000 .4byte .LVL49 + 2534 0401 22000000 .4byte .LVL50 + 2535 0405 0200 .2byte 0x2 + 2536 0407 30 .byte 0x30 + 2537 0408 9F .byte 0x9f + 2538 0409 00000000 .4byte 0 + 2539 040d 00000000 .4byte 0 + 2540 .LLST26: + 2541 0411 26000000 .4byte .LVL51 + 2542 0415 3E000000 .4byte .LVL53 + 2543 0419 0100 .2byte 0x1 + 2544 041b 53 .byte 0x53 + 2545 041c 00000000 .4byte 0 + 2546 0420 00000000 .4byte 0 + 2547 .section .debug_aranges,"",%progbits + 2548 0000 44000000 .4byte 0x44 + 2549 0004 0200 .2byte 0x2 + 2550 0006 00000000 .4byte .Ldebug_info0 + 2551 000a 04 .byte 0x4 + 2552 000b 00 .byte 0 + 2553 000c 0000 .2byte 0 + 2554 000e 0000 .2byte 0 + 2555 0010 00000000 .4byte .LFB7 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 46 + + + 2556 0014 20000000 .4byte .LFE7-.LFB7 + 2557 0018 00000000 .4byte .LFB8 + 2558 001c 14000000 .4byte .LFE8-.LFB8 + 2559 0020 00000000 .4byte .LFB9 + 2560 0024 84000000 .4byte .LFE9-.LFB9 + 2561 0028 00000000 .4byte .LFB10 + 2562 002c 86000000 .4byte .LFE10-.LFB10 + 2563 0030 00000000 .4byte .LFB11 + 2564 0034 40000000 .4byte .LFE11-.LFB11 + 2565 0038 00000000 .4byte .LFB12 + 2566 003c 50000000 .4byte .LFE12-.LFB12 + 2567 0040 00000000 .4byte 0 + 2568 0044 00000000 .4byte 0 + 2569 .section .debug_ranges,"",%progbits + 2570 .Ldebug_ranges0: + 2571 0000 00000000 .4byte .LFB7 + 2572 0004 20000000 .4byte .LFE7 + 2573 0008 00000000 .4byte .LFB8 + 2574 000c 14000000 .4byte .LFE8 + 2575 0010 00000000 .4byte .LFB9 + 2576 0014 84000000 .4byte .LFE9 + 2577 0018 00000000 .4byte .LFB10 + 2578 001c 86000000 .4byte .LFE10 + 2579 0020 00000000 .4byte .LFB11 + 2580 0024 40000000 .4byte .LFE11 + 2581 0028 00000000 .4byte .LFB12 + 2582 002c 50000000 .4byte .LFE12 + 2583 0030 00000000 .4byte 0 + 2584 0034 00000000 .4byte 0 + 2585 .section .debug_line,"",%progbits + 2586 .Ldebug_line0: + 2587 0000 4E020000 .section .debug_str,"MS",%progbits,1 + 2587 02004801 + 2587 00000201 + 2587 FB0E0D00 + 2587 01010101 + 2588 .LASF35: + 2589 0000 705F6D73 .ascii "p_msg\000" + 2589 6700 + 2590 .LASF2: + 2591 0006 73697A65 .ascii "size_t\000" + 2591 5F7400 + 2592 .LASF61: + 2593 000d 7264796D .ascii "rdymsg\000" + 2593 736700 + 2594 .LASF12: + 2595 0014 75696E74 .ascii "uint64_t\000" + 2595 36345F74 + 2595 00 + 2596 .LASF51: + 2597 001d 6D656D67 .ascii "memgetfunc_t\000" + 2597 65746675 + 2597 6E635F74 + 2597 00 + 2598 .LASF13: + 2599 002a 6C6F6E67 .ascii "long long unsigned int\000" + 2599 206C6F6E + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 47 + + + 2599 6720756E + 2599 7369676E + 2599 65642069 + 2600 .LASF78: + 2601 0041 2E2E2F2E .ascii "../..//os/kernel/src/chheap.c\000" + 2601 2E2F2F6F + 2601 732F6B65 + 2601 726E656C + 2601 2F737263 + 2602 .LASF62: + 2603 005f 65786974 .ascii "exitcode\000" + 2603 636F6465 + 2603 00 + 2604 .LASF55: + 2605 0068 685F6672 .ascii "h_free\000" + 2605 656500 + 2606 .LASF68: + 2607 006f 68656170 .ascii "heapp\000" + 2607 7000 + 2608 .LASF81: + 2609 0075 63684D74 .ascii "chMtxUnlock\000" + 2609 78556E6C + 2609 6F636B00 + 2610 .LASF67: + 2611 0081 63684865 .ascii "chHeapInit\000" + 2611 6170496E + 2611 697400 + 2612 .LASF57: + 2613 008c 6E657874 .ascii "next\000" + 2613 00 + 2614 .LASF24: + 2615 0091 705F7072 .ascii "p_prio\000" + 2615 696F00 + 2616 .LASF73: + 2617 0098 63684865 .ascii "chHeapMaxMinFraq\000" + 2617 61704D61 + 2617 784D696E + 2617 46726171 + 2617 00 + 2618 .LASF11: + 2619 00a9 6C6F6E67 .ascii "long long int\000" + 2619 206C6F6E + 2619 6720696E + 2619 7400 + 2620 .LASF1: + 2621 00b7 7369676E .ascii "signed char\000" + 2621 65642063 + 2621 68617200 + 2622 .LASF56: + 2623 00c3 685F6D74 .ascii "h_mtx\000" + 2623 7800 + 2624 .LASF39: + 2625 00c9 705F6D70 .ascii "p_mpool\000" + 2625 6F6F6C00 + 2626 .LASF48: + 2627 00d1 6D5F7175 .ascii "m_queue\000" + 2627 65756500 + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 48 + + + 2628 .LASF69: + 2629 00d9 63684865 .ascii "chHeapFree\000" + 2629 61704672 + 2629 656500 + 2630 .LASF8: + 2631 00e4 6C6F6E67 .ascii "long int\000" + 2631 20696E74 + 2631 00 + 2632 .LASF15: + 2633 00ed 74737461 .ascii "tstate_t\000" + 2633 74655F74 + 2633 00 + 2634 .LASF26: + 2635 00f6 705F6E65 .ascii "p_newer\000" + 2635 77657200 + 2636 .LASF42: + 2637 00fe 72656761 .ascii "regarm_t\000" + 2637 726D5F74 + 2637 00 + 2638 .LASF59: + 2639 0107 616C6967 .ascii "align\000" + 2639 6E00 + 2640 .LASF0: + 2641 010d 756E7369 .ascii "unsigned int\000" + 2641 676E6564 + 2641 20696E74 + 2641 00 + 2642 .LASF10: + 2643 011a 6C6F6E67 .ascii "long unsigned int\000" + 2643 20756E73 + 2643 69676E65 + 2643 6420696E + 2643 7400 + 2644 .LASF45: + 2645 012c 636F6E74 .ascii "context\000" + 2645 65787400 + 2646 .LASF60: + 2647 0134 73697A65 .ascii "size\000" + 2647 00 + 2648 .LASF6: + 2649 0139 73686F72 .ascii "short unsigned int\000" + 2649 7420756E + 2649 7369676E + 2649 65642069 + 2649 6E7400 + 2650 .LASF18: + 2651 014c 6D73675F .ascii "msg_t\000" + 2651 7400 + 2652 .LASF14: + 2653 0152 746D6F64 .ascii "tmode_t\000" + 2653 655F7400 + 2654 .LASF41: + 2655 015a 54687265 .ascii "ThreadsList\000" + 2655 6164734C + 2655 69737400 + 2656 .LASF19: + 2657 0166 6576656E .ascii "eventmask_t\000" + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 49 + + + 2657 746D6173 + 2657 6B5F7400 + 2658 .LASF47: + 2659 0172 4D757465 .ascii "Mutex\000" + 2659 7800 + 2660 .LASF43: + 2661 0178 73746B61 .ascii "stkalign_t\000" + 2661 6C69676E + 2661 5F7400 + 2662 .LASF46: + 2663 0183 73697A65 .ascii "sizetype\000" + 2663 74797065 + 2663 00 + 2664 .LASF76: + 2665 018c 63684D74 .ascii "chMtxLock\000" + 2665 784C6F63 + 2665 6B00 + 2666 .LASF27: + 2667 0196 705F6F6C .ascii "p_older\000" + 2667 64657200 + 2668 .LASF79: + 2669 019e 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 2669 73657273 + 2669 5C496D61 + 2669 6E6F6C5C + 2669 64657665 + 2670 01cb 6C696361 .ascii "lications\\smartcities\000" + 2670 74696F6E + 2670 735C736D + 2670 61727463 + 2670 69746965 + 2671 .LASF40: + 2672 01e1 54687265 .ascii "ThreadsQueue\000" + 2672 61647351 + 2672 75657565 + 2672 00 + 2673 .LASF77: + 2674 01ee 474E5520 .ascii "GNU C 4.7.2\000" + 2674 4320342E + 2674 372E3200 + 2675 .LASF52: + 2676 01fa 4D656D6F .ascii "MemoryHeap\000" + 2676 72794865 + 2676 617000 + 2677 .LASF16: + 2678 0205 74726566 .ascii "trefs_t\000" + 2678 735F7400 + 2679 .LASF23: + 2680 020d 705F7072 .ascii "p_prev\000" + 2680 657600 + 2681 .LASF17: + 2682 0214 74707269 .ascii "tprio_t\000" + 2682 6F5F7400 + 2683 .LASF7: + 2684 021c 696E7433 .ascii "int32_t\000" + 2684 325F7400 + 2685 .LASF4: + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 50 + + + 2686 0224 756E7369 .ascii "unsigned char\000" + 2686 676E6564 + 2686 20636861 + 2686 7200 + 2687 .LASF54: + 2688 0232 685F7072 .ascii "h_provider\000" + 2688 6F766964 + 2688 657200 + 2689 .LASF37: + 2690 023d 705F6D74 .ascii "p_mtxlist\000" + 2690 786C6973 + 2690 7400 + 2691 .LASF5: + 2692 0247 73686F72 .ascii "short int\000" + 2692 7420696E + 2692 7400 + 2693 .LASF29: + 2694 0251 705F7374 .ascii "p_state\000" + 2694 61746500 + 2695 .LASF80: + 2696 0259 68656170 .ascii "heap_header\000" + 2696 5F686561 + 2696 64657200 + 2697 .LASF64: + 2698 0265 65776D61 .ascii "ewmask\000" + 2698 736B00 + 2699 .LASF22: + 2700 026c 705F6E65 .ascii "p_next\000" + 2700 787400 + 2701 .LASF30: + 2702 0273 705F666C .ascii "p_flags\000" + 2702 61677300 + 2703 .LASF21: + 2704 027b 54687265 .ascii "Thread\000" + 2704 616400 + 2705 .LASF70: + 2706 0282 63684865 .ascii "chHeapAlloc\000" + 2706 6170416C + 2706 6C6F6300 + 2707 .LASF36: + 2708 028e 705F6570 .ascii "p_epending\000" + 2708 656E6469 + 2708 6E6700 + 2709 .LASF9: + 2710 0299 75696E74 .ascii "uint32_t\000" + 2710 33325F74 + 2710 00 + 2711 .LASF58: + 2712 02a2 68656170 .ascii "heap\000" + 2712 00 + 2713 .LASF74: + 2714 02a7 64656661 .ascii "default_heap\000" + 2714 756C745F + 2714 68656170 + 2714 00 + 2715 .LASF65: + 2716 02b4 63686172 .ascii "char\000" + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 51 + + + 2716 00 + 2717 .LASF71: + 2718 02b9 63684865 .ascii "chHeapStatus\000" + 2718 61705374 + 2718 61747573 + 2718 00 + 2719 .LASF50: + 2720 02c6 6D5F6E65 .ascii "m_next\000" + 2720 787400 + 2721 .LASF20: + 2722 02cd 73797374 .ascii "systime_t\000" + 2722 696D655F + 2722 7400 + 2723 .LASF38: + 2724 02d7 705F7265 .ascii "p_realprio\000" + 2724 616C7072 + 2724 696F00 + 2725 .LASF32: + 2726 02e2 705F7469 .ascii "p_time\000" + 2726 6D6500 + 2727 .LASF44: + 2728 02e9 696E7463 .ascii "intctx\000" + 2728 747800 + 2729 .LASF34: + 2730 02f0 705F6D73 .ascii "p_msgqueue\000" + 2730 67717565 + 2730 756500 + 2731 .LASF75: + 2732 02fb 63684D74 .ascii "chMtxInit\000" + 2732 78496E69 + 2732 7400 + 2733 .LASF31: + 2734 0305 705F7265 .ascii "p_refs\000" + 2734 667300 + 2735 .LASF3: + 2736 030c 75696E74 .ascii "uint8_t\000" + 2736 385F7400 + 2737 .LASF63: + 2738 0314 77746F62 .ascii "wtobjp\000" + 2738 6A7000 + 2739 .LASF72: + 2740 031b 73697A65 .ascii "sizep\000" + 2740 7000 + 2741 .LASF28: + 2742 0321 705F6E61 .ascii "p_name\000" + 2742 6D6500 + 2743 .LASF66: + 2744 0328 5F686561 .ascii "_heap_init\000" + 2744 705F696E + 2744 697400 + 2745 .LASF49: + 2746 0333 6D5F6F77 .ascii "m_owner\000" + 2746 6E657200 + 2747 .LASF25: + 2748 033b 705F6374 .ascii "p_ctx\000" + 2748 7800 + 2749 .LASF33: + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 52 + + + 2750 0341 705F7761 .ascii "p_waiting\000" + 2750 6974696E + 2750 6700 + 2751 .LASF53: + 2752 034b 6D656D6F .ascii "memory_heap\000" + 2752 72795F68 + 2752 65617000 + 2753 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\ccMy1ZtK.s page 53 + + +DEFINED SYMBOLS + *ABS*:00000000 chheap.c +C:\cygwin\tmp\ccMy1ZtK.s:19 .text._heap_init:00000000 $t +C:\cygwin\tmp\ccMy1ZtK.s:25 .text._heap_init:00000000 _heap_init +C:\cygwin\tmp\ccMy1ZtK.s:518 .bss.default_heap:00000000 .LANCHOR0 +C:\cygwin\tmp\ccMy1ZtK.s:57 .text.chHeapInit:00000000 $t +C:\cygwin\tmp\ccMy1ZtK.s:63 .text.chHeapInit:00000000 chHeapInit +C:\cygwin\tmp\ccMy1ZtK.s:97 .text.chHeapAlloc:00000000 $t +C:\cygwin\tmp\ccMy1ZtK.s:103 .text.chHeapAlloc:00000000 chHeapAlloc +C:\cygwin\tmp\ccMy1ZtK.s:230 .text.chHeapAlloc:00000080 $d +C:\cygwin\tmp\ccMy1ZtK.s:235 .text.chHeapFree:00000000 $t +C:\cygwin\tmp\ccMy1ZtK.s:241 .text.chHeapFree:00000000 chHeapFree +C:\cygwin\tmp\ccMy1ZtK.s:355 .text.chHeapStatus:00000000 $t +C:\cygwin\tmp\ccMy1ZtK.s:361 .text.chHeapStatus:00000000 chHeapStatus +C:\cygwin\tmp\ccMy1ZtK.s:431 .text.chHeapStatus:0000003c $d +C:\cygwin\tmp\ccMy1ZtK.s:436 .text.chHeapMaxMinFraq:00000000 $t +C:\cygwin\tmp\ccMy1ZtK.s:442 .text.chHeapMaxMinFraq:00000000 chHeapMaxMinFraq +C:\cygwin\tmp\ccMy1ZtK.s:512 .text.chHeapMaxMinFraq:0000004c $d +C:\cygwin\tmp\ccMy1ZtK.s:517 .bss.default_heap:00000000 $d +C:\cygwin\tmp\ccMy1ZtK.s:521 .bss.default_heap:00000000 default_heap + .debug_frame:00000010 $d +C:\cygwin\tmp\ccMy1ZtK.s:234 .text.chHeapAlloc:00000084 $t + +UNDEFINED SYMBOLS +chCoreAlloc +chMtxInit +chMtxLock +chMtxUnlock diff --git a/Project/applications/smartcities/build/lst/chlists.lst b/Project/applications/smartcities/build/lst/chlists.lst new file mode 100644 index 0000000..e84a3a0 --- /dev/null +++ b/Project/applications/smartcities/build/lst/chlists.lst @@ -0,0 +1,229 @@ +ARM GAS C:\cygwin\tmp\ccEUEnD7.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "chlists.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .Letext0: + 19 .section .debug_info,"",%progbits + 20 .Ldebug_info0: + 21 0000 6E000000 .4byte 0x6e + 22 0004 0200 .2byte 0x2 + 23 0006 00000000 .4byte .Ldebug_abbrev0 + 24 000a 04 .byte 0x4 + 25 000b 01 .uleb128 0x1 + 26 000c 3E000000 .4byte .LASF11 + 27 0010 01 .byte 0x1 + 28 0011 8B000000 .4byte .LASF12 + 29 0015 AA000000 .4byte .LASF13 + 30 0019 00000000 .4byte .Ldebug_line0 + 31 001d 02 .uleb128 0x2 + 32 001e 04 .byte 0x4 + 33 001f 05 .byte 0x5 + 34 0020 696E7400 .ascii "int\000" + 35 0024 03 .uleb128 0x3 + 36 0025 04 .byte 0x4 + 37 0026 07 .byte 0x7 + 38 0027 00000000 .4byte .LASF0 + 39 002b 03 .uleb128 0x3 + 40 002c 01 .byte 0x1 + 41 002d 06 .byte 0x6 + 42 002e 1F000000 .4byte .LASF1 + 43 0032 03 .uleb128 0x3 + 44 0033 01 .byte 0x1 + 45 0034 08 .byte 0x8 + 46 0035 6B000000 .4byte .LASF2 + 47 0039 03 .uleb128 0x3 + 48 003a 02 .byte 0x2 + 49 003b 05 .byte 0x5 + 50 003c 4A000000 .4byte .LASF3 + 51 0040 03 .uleb128 0x3 + 52 0041 02 .byte 0x2 + 53 0042 07 .byte 0x7 + 54 0043 2B000000 .4byte .LASF4 + 55 0047 03 .uleb128 0x3 + 56 0048 04 .byte 0x4 + 57 0049 05 .byte 0x5 + ARM GAS C:\cygwin\tmp\ccEUEnD7.s page 2 + + + 58 004a 79000000 .4byte .LASF5 + 59 004e 03 .uleb128 0x3 + 60 004f 04 .byte 0x4 + 61 0050 07 .byte 0x7 + 62 0051 0D000000 .4byte .LASF6 + 63 0055 03 .uleb128 0x3 + 64 0056 08 .byte 0x8 + 65 0057 05 .byte 0x5 + 66 0058 F2000000 .4byte .LASF7 + 67 005c 03 .uleb128 0x3 + 68 005d 08 .byte 0x8 + 69 005e 07 .byte 0x7 + 70 005f 54000000 .4byte .LASF8 + 71 0063 03 .uleb128 0x3 + 72 0064 04 .byte 0x4 + 73 0065 07 .byte 0x7 + 74 0066 82000000 .4byte .LASF9 + 75 006a 03 .uleb128 0x3 + 76 006b 01 .byte 0x1 + 77 006c 08 .byte 0x8 + 78 006d ED000000 .4byte .LASF10 + 79 0071 00 .byte 0 + 80 .section .debug_abbrev,"",%progbits + 81 .Ldebug_abbrev0: + 82 0000 01 .uleb128 0x1 + 83 0001 11 .uleb128 0x11 + 84 0002 01 .byte 0x1 + 85 0003 25 .uleb128 0x25 + 86 0004 0E .uleb128 0xe + 87 0005 13 .uleb128 0x13 + 88 0006 0B .uleb128 0xb + 89 0007 03 .uleb128 0x3 + 90 0008 0E .uleb128 0xe + 91 0009 1B .uleb128 0x1b + 92 000a 0E .uleb128 0xe + 93 000b 10 .uleb128 0x10 + 94 000c 06 .uleb128 0x6 + 95 000d 00 .byte 0 + 96 000e 00 .byte 0 + 97 000f 02 .uleb128 0x2 + 98 0010 24 .uleb128 0x24 + 99 0011 00 .byte 0 + 100 0012 0B .uleb128 0xb + 101 0013 0B .uleb128 0xb + 102 0014 3E .uleb128 0x3e + 103 0015 0B .uleb128 0xb + 104 0016 03 .uleb128 0x3 + 105 0017 08 .uleb128 0x8 + 106 0018 00 .byte 0 + 107 0019 00 .byte 0 + 108 001a 03 .uleb128 0x3 + 109 001b 24 .uleb128 0x24 + 110 001c 00 .byte 0 + 111 001d 0B .uleb128 0xb + 112 001e 0B .uleb128 0xb + 113 001f 3E .uleb128 0x3e + 114 0020 0B .uleb128 0xb + ARM GAS C:\cygwin\tmp\ccEUEnD7.s page 3 + + + 115 0021 03 .uleb128 0x3 + 116 0022 0E .uleb128 0xe + 117 0023 00 .byte 0 + 118 0024 00 .byte 0 + 119 0025 00 .byte 0 + 120 .section .debug_aranges,"",%progbits + 121 0000 14000000 .4byte 0x14 + 122 0004 0200 .2byte 0x2 + 123 0006 00000000 .4byte .Ldebug_info0 + 124 000a 04 .byte 0x4 + 125 000b 00 .byte 0 + 126 000c 0000 .2byte 0 + 127 000e 0000 .2byte 0 + 128 0010 00000000 .4byte 0 + 129 0014 00000000 .4byte 0 + 130 .section .debug_line,"",%progbits + 131 .Ldebug_line0: + 132 0000 19000000 .section .debug_str,"MS",%progbits,1 + 132 02001300 + 132 00000201 + 132 FB0E0D00 + 132 01010101 + 133 .LASF0: + 134 0000 756E7369 .ascii "unsigned int\000" + 134 676E6564 + 134 20696E74 + 134 00 + 135 .LASF6: + 136 000d 6C6F6E67 .ascii "long unsigned int\000" + 136 20756E73 + 136 69676E65 + 136 6420696E + 136 7400 + 137 .LASF1: + 138 001f 7369676E .ascii "signed char\000" + 138 65642063 + 138 68617200 + 139 .LASF4: + 140 002b 73686F72 .ascii "short unsigned int\000" + 140 7420756E + 140 7369676E + 140 65642069 + 140 6E7400 + 141 .LASF11: + 142 003e 474E5520 .ascii "GNU C 4.7.2\000" + 142 4320342E + 142 372E3200 + 143 .LASF3: + 144 004a 73686F72 .ascii "short int\000" + 144 7420696E + 144 7400 + 145 .LASF8: + 146 0054 6C6F6E67 .ascii "long long unsigned int\000" + 146 206C6F6E + 146 6720756E + 146 7369676E + 146 65642069 + ARM GAS C:\cygwin\tmp\ccEUEnD7.s page 4 + + + 147 .LASF2: + 148 006b 756E7369 .ascii "unsigned char\000" + 148 676E6564 + 148 20636861 + 148 7200 + 149 .LASF5: + 150 0079 6C6F6E67 .ascii "long int\000" + 150 20696E74 + 150 00 + 151 .LASF9: + 152 0082 73697A65 .ascii "sizetype\000" + 152 74797065 + 152 00 + 153 .LASF12: + 154 008b 2E2E2F2E .ascii "../..//os/kernel/src/chlists.c\000" + 154 2E2F2F6F + 154 732F6B65 + 154 726E656C + 154 2F737263 + 155 .LASF13: + 156 00aa 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 156 73657273 + 156 5C496D61 + 156 6E6F6C5C + 156 64657665 + 157 00d7 6C696361 .ascii "lications\\smartcities\000" + 157 74696F6E + 157 735C736D + 157 61727463 + 157 69746965 + 158 .LASF10: + 159 00ed 63686172 .ascii "char\000" + 159 00 + 160 .LASF7: + 161 00f2 6C6F6E67 .ascii "long long int\000" + 161 206C6F6E + 161 6720696E + 161 7400 + 162 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\ccEUEnD7.s page 5 + + +DEFINED SYMBOLS + *ABS*:00000000 chlists.c + +NO UNDEFINED SYMBOLS diff --git a/Project/applications/smartcities/build/lst/chmboxes.lst b/Project/applications/smartcities/build/lst/chmboxes.lst new file mode 100644 index 0000000..30ece7e --- /dev/null +++ b/Project/applications/smartcities/build/lst/chmboxes.lst @@ -0,0 +1,3686 @@ +ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "chmboxes.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text.chMBInit,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .global chMBInit + 22 .thumb + 23 .thumb_func + 24 .type chMBInit, %function + 25 chMBInit: + 26 .LFB7: + 27 .file 1 "../..//os/kernel/src/chmboxes.c" + 28 .loc 1 72 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 .LVL0: + 33 0000 38B5 push {r3, r4, r5, lr} + 34 .LCFI0: + 35 .cfi_def_cfa_offset 16 + 36 .cfi_offset 3, -16 + 37 .cfi_offset 4, -12 + 38 .cfi_offset 5, -8 + 39 .cfi_offset 14, -4 + 40 .loc 1 72 0 + 41 0002 0B46 mov r3, r1 + 42 0004 0446 mov r4, r0 + 43 .loc 1 77 0 + 44 0006 01EB8205 add r5, r1, r2, lsl #2 + 45 .loc 1 78 0 + 46 000a 00F11C00 add r0, r0, #28 + 47 .LVL1: + 48 000e 1146 mov r1, r2 + 49 .LVL2: + 50 .loc 1 76 0 + 51 0010 E360 str r3, [r4, #12] + 52 0012 A360 str r3, [r4, #8] + 53 .loc 1 77 0 + 54 0014 84E82800 stmia r4, {r3, r5} + 55 .loc 1 78 0 + 56 0018 FFF7FEFF bl chSemInit + 57 .LVL3: + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 2 + + + 58 .loc 1 79 0 + 59 001c 04F11000 add r0, r4, #16 + 60 0020 0021 movs r1, #0 + 61 .loc 1 80 0 + 62 0022 BDE83840 pop {r3, r4, r5, lr} + 63 .loc 1 79 0 + 64 0026 FFF7FEBF b chSemInit + 65 .LVL4: + 66 .cfi_endproc + 67 .LFE7: + 68 .size chMBInit, .-chMBInit + 69 002a 00BFAFF3 .section .text.chMBReset,"ax",%progbits + 69 0080 + 70 .align 2 + 71 .p2align 4,,15 + 72 .global chMBReset + 73 .thumb + 74 .thumb_func + 75 .type chMBReset, %function + 76 chMBReset: + 77 .LFB8: + 78 .loc 1 91 0 + 79 .cfi_startproc + 80 @ args = 0, pretend = 0, frame = 0 + 81 @ frame_needed = 0, uses_anonymous_args = 0 + 82 .LVL5: + 83 0000 10B5 push {r4, lr} + 84 .LCFI1: + 85 .cfi_def_cfa_offset 8 + 86 .cfi_offset 4, -8 + 87 .cfi_offset 14, -4 + 88 .loc 1 91 0 + 89 0002 0446 mov r4, r0 + 90 .loc 1 95 0 + 91 @ 95 "../..//os/kernel/src/chmboxes.c" 1 + 92 0004 72B6 cpsid i + 93 @ 0 "" 2 + 94 .loc 1 96 0 + 95 .thumb + 96 0006 0368 ldr r3, [r0, #0] + 97 .loc 1 97 0 + 98 0008 4168 ldr r1, [r0, #4] + 99 .loc 1 96 0 + 100 000a E360 str r3, [r4, #12] + 101 .loc 1 97 0 + 102 000c C91A subs r1, r1, r3 + 103 .loc 1 96 0 + 104 000e A360 str r3, [r4, #8] + 105 .loc 1 97 0 + 106 0010 8910 asrs r1, r1, #2 + 107 0012 00F11C00 add r0, r0, #28 + 108 .LVL6: + 109 0016 FFF7FEFF bl chSemResetI + 110 .LVL7: + 111 .loc 1 98 0 + 112 001a 04F11000 add r0, r4, #16 + 113 001e 0021 movs r1, #0 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 3 + + + 114 0020 FFF7FEFF bl chSemResetI + 115 .LVL8: + 116 .loc 1 99 0 + 117 0024 FFF7FEFF bl chSchRescheduleS + 118 .LVL9: + 119 .loc 1 100 0 + 120 @ 100 "../..//os/kernel/src/chmboxes.c" 1 + 121 0028 62B6 cpsie i + 122 @ 0 "" 2 + 123 .thumb + 124 002a 10BD pop {r4, pc} + 125 .cfi_endproc + 126 .LFE8: + 127 .size chMBReset, .-chMBReset + 128 002c AFF30080 .section .text.chMBPostS,"ax",%progbits + 129 .align 2 + 130 .p2align 4,,15 + 131 .global chMBPostS + 132 .thumb + 133 .thumb_func + 134 .type chMBPostS, %function + 135 chMBPostS: + 136 .LFB10: + 137 .loc 1 150 0 + 138 .cfi_startproc + 139 @ args = 0, pretend = 0, frame = 0 + 140 @ frame_needed = 0, uses_anonymous_args = 0 + 141 .LVL10: + 142 0000 70B5 push {r4, r5, r6, lr} + 143 .LCFI2: + 144 .cfi_def_cfa_offset 16 + 145 .cfi_offset 4, -16 + 146 .cfi_offset 5, -12 + 147 .cfi_offset 6, -8 + 148 .cfi_offset 14, -4 + 149 .loc 1 150 0 + 150 0002 0446 mov r4, r0 + 151 0004 0E46 mov r6, r1 + 152 .loc 1 156 0 + 153 0006 00F11C00 add r0, r0, #28 + 154 .LVL11: + 155 000a 1146 mov r1, r2 + 156 .LVL12: + 157 000c FFF7FEFF bl chSemWaitTimeoutS + 158 .LVL13: + 159 .loc 1 157 0 + 160 0010 0546 mov r5, r0 + 161 0012 78B9 cbnz r0, .L4 + 162 .loc 1 158 0 + 163 0014 A368 ldr r3, [r4, #8] + 164 .loc 1 159 0 + 165 0016 6268 ldr r2, [r4, #4] + 166 .loc 1 158 0 + 167 0018 43F8046B str r6, [r3], #4 + 168 .loc 1 159 0 + 169 001c 9342 cmp r3, r2 + 170 .loc 1 158 0 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 4 + + + 171 001e A360 str r3, [r4, #8] + 172 .loc 1 160 0 + 173 0020 28BF it cs + 174 0022 2368 ldrcs r3, [r4, #0] + 175 .loc 1 161 0 + 176 0024 04F11000 add r0, r4, #16 + 177 .LVL14: + 178 .loc 1 160 0 + 179 0028 28BF it cs + 180 002a A360 strcs r3, [r4, #8] + 181 .loc 1 161 0 + 182 002c FFF7FEFF bl chSemSignalI + 183 .LVL15: + 184 .loc 1 162 0 + 185 0030 FFF7FEFF bl chSchRescheduleS + 186 .LVL16: + 187 .L4: + 188 .loc 1 165 0 + 189 0034 2846 mov r0, r5 + 190 0036 70BD pop {r4, r5, r6, pc} + 191 .cfi_endproc + 192 .LFE10: + 193 .size chMBPostS, .-chMBPostS + 194 0038 AFF30080 .section .text.chMBPost,"ax",%progbits + 194 AFF30080 + 195 .align 2 + 196 .p2align 4,,15 + 197 .global chMBPost + 198 .thumb + 199 .thumb_func + 200 .type chMBPost, %function + 201 chMBPost: + 202 .LFB9: + 203 .loc 1 122 0 + 204 .cfi_startproc + 205 @ args = 0, pretend = 0, frame = 0 + 206 @ frame_needed = 0, uses_anonymous_args = 0 + 207 .LVL17: + 208 0000 08B5 push {r3, lr} + 209 .LCFI3: + 210 .cfi_def_cfa_offset 8 + 211 .cfi_offset 3, -8 + 212 .cfi_offset 14, -4 + 213 .loc 1 125 0 + 214 @ 125 "../..//os/kernel/src/chmboxes.c" 1 + 215 0002 72B6 cpsid i + 216 @ 0 "" 2 + 217 .loc 1 126 0 + 218 .thumb + 219 0004 FFF7FEFF bl chMBPostS + 220 .LVL18: + 221 .loc 1 127 0 + 222 @ 127 "../..//os/kernel/src/chmboxes.c" 1 + 223 0008 62B6 cpsie i + 224 @ 0 "" 2 + 225 .loc 1 129 0 + 226 .thumb + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 5 + + + 227 000a 08BD pop {r3, pc} + 228 .cfi_endproc + 229 .LFE9: + 230 .size chMBPost, .-chMBPost + 231 000c AFF30080 .section .text.chMBPostI,"ax",%progbits + 232 .align 2 + 233 .p2align 4,,15 + 234 .global chMBPostI + 235 .thumb + 236 .thumb_func + 237 .type chMBPostI, %function + 238 chMBPostI: + 239 .LFB11: + 240 .loc 1 181 0 + 241 .cfi_startproc + 242 @ args = 0, pretend = 0, frame = 0 + 243 @ frame_needed = 0, uses_anonymous_args = 0 + 244 .LVL19: + 245 .loc 1 186 0 + 246 0000 426A ldr r2, [r0, #36] + 247 .loc 1 181 0 + 248 0002 10B5 push {r4, lr} + 249 .LCFI4: + 250 .cfi_def_cfa_offset 8 + 251 .cfi_offset 4, -8 + 252 .cfi_offset 14, -4 + 253 .loc 1 186 0 + 254 0004 002A cmp r2, #0 + 255 0006 0FDD ble .L11 + 256 .loc 1 189 0 + 257 0008 8368 ldr r3, [r0, #8] + 258 .loc 1 190 0 + 259 000a 4468 ldr r4, [r0, #4] + 260 .loc 1 188 0 + 261 000c 013A subs r2, r2, #1 + 262 000e 4262 str r2, [r0, #36] + 263 .loc 1 189 0 + 264 0010 43F8041B str r1, [r3], #4 + 265 .loc 1 190 0 + 266 0014 A342 cmp r3, r4 + 267 .loc 1 189 0 + 268 0016 8360 str r3, [r0, #8] + 269 .loc 1 191 0 + 270 0018 24BF itt cs + 271 001a 0368 ldrcs r3, [r0, #0] + 272 001c 8360 strcs r3, [r0, #8] + 273 .loc 1 192 0 + 274 001e 1030 adds r0, r0, #16 + 275 .LVL20: + 276 0020 FFF7FEFF bl chSemSignalI + 277 .LVL21: + 278 .loc 1 193 0 + 279 0024 0020 movs r0, #0 + 280 0026 10BD pop {r4, pc} + 281 .LVL22: + 282 .L11: + 283 .loc 1 187 0 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 6 + + + 284 0028 4FF0FF30 mov r0, #-1 + 285 .LVL23: + 286 .loc 1 194 0 + 287 002c 10BD pop {r4, pc} + 288 .cfi_endproc + 289 .LFE11: + 290 .size chMBPostI, .-chMBPostI + 291 002e 00BF .section .text.chMBPostAheadS,"ax",%progbits + 292 .align 2 + 293 .p2align 4,,15 + 294 .global chMBPostAheadS + 295 .thumb + 296 .thumb_func + 297 .type chMBPostAheadS, %function + 298 chMBPostAheadS: + 299 .LFB13: + 300 .loc 1 243 0 + 301 .cfi_startproc + 302 @ args = 0, pretend = 0, frame = 0 + 303 @ frame_needed = 0, uses_anonymous_args = 0 + 304 .LVL24: + 305 0000 70B5 push {r4, r5, r6, lr} + 306 .LCFI5: + 307 .cfi_def_cfa_offset 16 + 308 .cfi_offset 4, -16 + 309 .cfi_offset 5, -12 + 310 .cfi_offset 6, -8 + 311 .cfi_offset 14, -4 + 312 .loc 1 243 0 + 313 0002 0446 mov r4, r0 + 314 0004 0E46 mov r6, r1 + 315 .loc 1 249 0 + 316 0006 00F11C00 add r0, r0, #28 + 317 .LVL25: + 318 000a 1146 mov r1, r2 + 319 .LVL26: + 320 000c FFF7FEFF bl chSemWaitTimeoutS + 321 .LVL27: + 322 .loc 1 250 0 + 323 0010 0546 mov r5, r0 + 324 0012 60B9 cbnz r0, .L13 + 325 .loc 1 251 0 + 326 0014 E368 ldr r3, [r4, #12] + 327 0016 2268 ldr r2, [r4, #0] + 328 0018 043B subs r3, r3, #4 + 329 001a 9342 cmp r3, r2 + 330 001c E360 str r3, [r4, #12] + 331 001e 08D3 bcc .L15 + 332 .L14: + 333 .loc 1 254 0 + 334 0020 04F11000 add r0, r4, #16 + 335 .LVL28: + 336 .loc 1 253 0 + 337 0024 1E60 str r6, [r3, #0] + 338 .loc 1 254 0 + 339 0026 FFF7FEFF bl chSemSignalI + 340 .LVL29: + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 7 + + + 341 .loc 1 255 0 + 342 002a FFF7FEFF bl chSchRescheduleS + 343 .LVL30: + 344 .L13: + 345 .loc 1 258 0 + 346 002e 2846 mov r0, r5 + 347 0030 70BD pop {r4, r5, r6, pc} + 348 .LVL31: + 349 .L15: + 350 .loc 1 252 0 + 351 0032 6368 ldr r3, [r4, #4] + 352 0034 043B subs r3, r3, #4 + 353 0036 E360 str r3, [r4, #12] + 354 0038 F2E7 b .L14 + 355 .cfi_endproc + 356 .LFE13: + 357 .size chMBPostAheadS, .-chMBPostAheadS + 358 003a 00BFAFF3 .section .text.chMBPostAhead,"ax",%progbits + 358 0080 + 359 .align 2 + 360 .p2align 4,,15 + 361 .global chMBPostAhead + 362 .thumb + 363 .thumb_func + 364 .type chMBPostAhead, %function + 365 chMBPostAhead: + 366 .LFB12: + 367 .loc 1 215 0 + 368 .cfi_startproc + 369 @ args = 0, pretend = 0, frame = 0 + 370 @ frame_needed = 0, uses_anonymous_args = 0 + 371 .LVL32: + 372 0000 08B5 push {r3, lr} + 373 .LCFI6: + 374 .cfi_def_cfa_offset 8 + 375 .cfi_offset 3, -8 + 376 .cfi_offset 14, -4 + 377 .loc 1 218 0 + 378 @ 218 "../..//os/kernel/src/chmboxes.c" 1 + 379 0002 72B6 cpsid i + 380 @ 0 "" 2 + 381 .loc 1 219 0 + 382 .thumb + 383 0004 FFF7FEFF bl chMBPostAheadS + 384 .LVL33: + 385 .loc 1 220 0 + 386 @ 220 "../..//os/kernel/src/chmboxes.c" 1 + 387 0008 62B6 cpsie i + 388 @ 0 "" 2 + 389 .loc 1 222 0 + 390 .thumb + 391 000a 08BD pop {r3, pc} + 392 .cfi_endproc + 393 .LFE12: + 394 .size chMBPostAhead, .-chMBPostAhead + 395 000c AFF30080 .section .text.chMBPostAheadI,"ax",%progbits + 396 .align 2 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 8 + + + 397 .p2align 4,,15 + 398 .global chMBPostAheadI + 399 .thumb + 400 .thumb_func + 401 .type chMBPostAheadI, %function + 402 chMBPostAheadI: + 403 .LFB14: + 404 .loc 1 274 0 + 405 .cfi_startproc + 406 @ args = 0, pretend = 0, frame = 0 + 407 @ frame_needed = 0, uses_anonymous_args = 0 + 408 .LVL34: + 409 .loc 1 279 0 + 410 0000 426A ldr r2, [r0, #36] + 411 .loc 1 274 0 + 412 0002 10B5 push {r4, lr} + 413 .LCFI7: + 414 .cfi_def_cfa_offset 8 + 415 .cfi_offset 4, -8 + 416 .cfi_offset 14, -4 + 417 .loc 1 279 0 + 418 0004 002A cmp r2, #0 + 419 0006 10DD ble .L20 + 420 .loc 1 282 0 + 421 0008 C368 ldr r3, [r0, #12] + 422 000a 0468 ldr r4, [r0, #0] + 423 000c 043B subs r3, r3, #4 + 424 .loc 1 281 0 + 425 000e 013A subs r2, r2, #1 + 426 .loc 1 282 0 + 427 0010 A342 cmp r3, r4 + 428 .loc 1 281 0 + 429 0012 4262 str r2, [r0, #36] + 430 .loc 1 282 0 + 431 0014 C360 str r3, [r0, #12] + 432 0016 02D2 bcs .L19 + 433 .loc 1 283 0 + 434 0018 4368 ldr r3, [r0, #4] + 435 001a 043B subs r3, r3, #4 + 436 001c C360 str r3, [r0, #12] + 437 .L19: + 438 .loc 1 285 0 + 439 001e 1030 adds r0, r0, #16 + 440 .LVL35: + 441 .loc 1 284 0 + 442 0020 1960 str r1, [r3, #0] + 443 .loc 1 285 0 + 444 0022 FFF7FEFF bl chSemSignalI + 445 .LVL36: + 446 .loc 1 286 0 + 447 0026 0020 movs r0, #0 + 448 0028 10BD pop {r4, pc} + 449 .LVL37: + 450 .L20: + 451 .loc 1 280 0 + 452 002a 4FF0FF30 mov r0, #-1 + 453 .LVL38: + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 9 + + + 454 .loc 1 287 0 + 455 002e 10BD pop {r4, pc} + 456 .cfi_endproc + 457 .LFE14: + 458 .size chMBPostAheadI, .-chMBPostAheadI + 459 .section .text.chMBFetchS,"ax",%progbits + 460 .align 2 + 461 .p2align 4,,15 + 462 .global chMBFetchS + 463 .thumb + 464 .thumb_func + 465 .type chMBFetchS, %function + 466 chMBFetchS: + 467 .LFB16: + 468 .loc 1 336 0 + 469 .cfi_startproc + 470 @ args = 0, pretend = 0, frame = 0 + 471 @ frame_needed = 0, uses_anonymous_args = 0 + 472 .LVL39: + 473 0000 70B5 push {r4, r5, r6, lr} + 474 .LCFI8: + 475 .cfi_def_cfa_offset 16 + 476 .cfi_offset 4, -16 + 477 .cfi_offset 5, -12 + 478 .cfi_offset 6, -8 + 479 .cfi_offset 14, -4 + 480 .loc 1 336 0 + 481 0002 0446 mov r4, r0 + 482 0004 0E46 mov r6, r1 + 483 .loc 1 342 0 + 484 0006 00F11000 add r0, r0, #16 + 485 .LVL40: + 486 000a 1146 mov r1, r2 + 487 .LVL41: + 488 000c FFF7FEFF bl chSemWaitTimeoutS + 489 .LVL42: + 490 .loc 1 343 0 + 491 0010 0546 mov r5, r0 + 492 0012 78B9 cbnz r0, .L22 + 493 .loc 1 344 0 + 494 0014 E368 ldr r3, [r4, #12] + 495 .loc 1 345 0 + 496 0016 6268 ldr r2, [r4, #4] + 497 .loc 1 344 0 + 498 0018 53F8041B ldr r1, [r3], #4 + 499 .loc 1 347 0 + 500 001c 04F11C00 add r0, r4, #28 + 501 .LVL43: + 502 .loc 1 345 0 + 503 0020 9342 cmp r3, r2 + 504 .loc 1 344 0 + 505 0022 3160 str r1, [r6, #0] + 506 0024 E360 str r3, [r4, #12] + 507 .loc 1 346 0 + 508 0026 24BF itt cs + 509 0028 2368 ldrcs r3, [r4, #0] + 510 002a E360 strcs r3, [r4, #12] + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 10 + + + 511 .loc 1 347 0 + 512 002c FFF7FEFF bl chSemSignalI + 513 .LVL44: + 514 .loc 1 348 0 + 515 0030 FFF7FEFF bl chSchRescheduleS + 516 .LVL45: + 517 .L22: + 518 .loc 1 351 0 + 519 0034 2846 mov r0, r5 + 520 0036 70BD pop {r4, r5, r6, pc} + 521 .cfi_endproc + 522 .LFE16: + 523 .size chMBFetchS, .-chMBFetchS + 524 0038 AFF30080 .section .text.chMBFetch,"ax",%progbits + 524 AFF30080 + 525 .align 2 + 526 .p2align 4,,15 + 527 .global chMBFetch + 528 .thumb + 529 .thumb_func + 530 .type chMBFetch, %function + 531 chMBFetch: + 532 .LFB15: + 533 .loc 1 308 0 + 534 .cfi_startproc + 535 @ args = 0, pretend = 0, frame = 0 + 536 @ frame_needed = 0, uses_anonymous_args = 0 + 537 .LVL46: + 538 0000 08B5 push {r3, lr} + 539 .LCFI9: + 540 .cfi_def_cfa_offset 8 + 541 .cfi_offset 3, -8 + 542 .cfi_offset 14, -4 + 543 .loc 1 311 0 + 544 @ 311 "../..//os/kernel/src/chmboxes.c" 1 + 545 0002 72B6 cpsid i + 546 @ 0 "" 2 + 547 .loc 1 312 0 + 548 .thumb + 549 0004 FFF7FEFF bl chMBFetchS + 550 .LVL47: + 551 .loc 1 313 0 + 552 @ 313 "../..//os/kernel/src/chmboxes.c" 1 + 553 0008 62B6 cpsie i + 554 @ 0 "" 2 + 555 .loc 1 315 0 + 556 .thumb + 557 000a 08BD pop {r3, pc} + 558 .cfi_endproc + 559 .LFE15: + 560 .size chMBFetch, .-chMBFetch + 561 000c AFF30080 .section .text.chMBFetchI,"ax",%progbits + 562 .align 2 + 563 .p2align 4,,15 + 564 .global chMBFetchI + 565 .thumb + 566 .thumb_func + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 11 + + + 567 .type chMBFetchI, %function + 568 chMBFetchI: + 569 .LFB17: + 570 .loc 1 367 0 + 571 .cfi_startproc + 572 @ args = 0, pretend = 0, frame = 0 + 573 @ frame_needed = 0, uses_anonymous_args = 0 + 574 .LVL48: + 575 .loc 1 372 0 + 576 0000 8269 ldr r2, [r0, #24] + 577 .loc 1 367 0 + 578 0002 10B5 push {r4, lr} + 579 .LCFI10: + 580 .cfi_def_cfa_offset 8 + 581 .cfi_offset 4, -8 + 582 .cfi_offset 14, -4 + 583 .loc 1 372 0 + 584 0004 002A cmp r2, #0 + 585 0006 10DD ble .L28 + 586 .loc 1 375 0 + 587 0008 C368 ldr r3, [r0, #12] + 588 .loc 1 374 0 + 589 000a 013A subs r2, r2, #1 + 590 000c 8261 str r2, [r0, #24] + 591 .loc 1 375 0 + 592 000e 53F8044B ldr r4, [r3], #4 + 593 .loc 1 376 0 + 594 0012 4268 ldr r2, [r0, #4] + 595 .loc 1 375 0 + 596 0014 0C60 str r4, [r1, #0] + 597 .loc 1 376 0 + 598 0016 9342 cmp r3, r2 + 599 .loc 1 375 0 + 600 0018 C360 str r3, [r0, #12] + 601 .loc 1 377 0 + 602 001a 24BF itt cs + 603 001c 0368 ldrcs r3, [r0, #0] + 604 001e C360 strcs r3, [r0, #12] + 605 .loc 1 378 0 + 606 0020 1C30 adds r0, r0, #28 + 607 .LVL49: + 608 0022 FFF7FEFF bl chSemSignalI + 609 .LVL50: + 610 .loc 1 379 0 + 611 0026 0020 movs r0, #0 + 612 0028 10BD pop {r4, pc} + 613 .LVL51: + 614 .L28: + 615 .loc 1 373 0 + 616 002a 4FF0FF30 mov r0, #-1 + 617 .LVL52: + 618 .loc 1 380 0 + 619 002e 10BD pop {r4, pc} + 620 .cfi_endproc + 621 .LFE17: + 622 .size chMBFetchI, .-chMBFetchI + 623 .text + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 12 + + + 624 .Letext0: + 625 .file 2 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 626 .file 3 "../..//os/ports/GCC/ARMCMx/chtypes.h" + 627 .file 4 "../..//os/kernel/include/chlists.h" + 628 .file 5 "../..//os/kernel/include/chthreads.h" + 629 .file 6 "../..//os/ports/GCC/ARMCMx/chcore_v7m.h" + 630 .file 7 "../..//os/kernel/include/chsem.h" + 631 .file 8 "../..//os/kernel/include/chmtx.h" + 632 .file 9 "../..//os/kernel/include/chmboxes.h" + 633 .file 10 "../..//os/kernel/include/chschd.h" + 634 .section .debug_info,"",%progbits + 635 .Ldebug_info0: + 636 0000 CC090000 .4byte 0x9cc + 637 0004 0200 .2byte 0x2 + 638 0006 00000000 .4byte .Ldebug_abbrev0 + 639 000a 04 .byte 0x4 + 640 000b 01 .uleb128 0x1 + 641 000c 0F020000 .4byte .LASF79 + 642 0010 01 .byte 0x1 + 643 0011 39030000 .4byte .LASF80 + 644 0015 B0010000 .4byte .LASF81 + 645 0019 00000000 .4byte .Ldebug_ranges0+0 + 646 001d 00000000 .4byte 0 + 647 0021 00000000 .4byte 0 + 648 0025 00000000 .4byte .Ldebug_line0 + 649 0029 02 .uleb128 0x2 + 650 002a 04 .byte 0x4 + 651 002b 05 .byte 0x5 + 652 002c 696E7400 .ascii "int\000" + 653 0030 03 .uleb128 0x3 + 654 0031 04 .byte 0x4 + 655 0032 07 .byte 0x7 + 656 0033 F0000000 .4byte .LASF0 + 657 0037 03 .uleb128 0x3 + 658 0038 01 .byte 0x1 + 659 0039 06 .byte 0x6 + 660 003a 92000000 .4byte .LASF1 + 661 003e 04 .uleb128 0x4 + 662 003f 31030000 .4byte .LASF5 + 663 0043 02 .byte 0x2 + 664 0044 2A .byte 0x2a + 665 0045 49000000 .4byte 0x49 + 666 0049 03 .uleb128 0x3 + 667 004a 01 .byte 0x1 + 668 004b 08 .byte 0x8 + 669 004c 3A020000 .4byte .LASF2 + 670 0050 03 .uleb128 0x3 + 671 0051 02 .byte 0x2 + 672 0052 05 .byte 0x5 + 673 0053 59020000 .4byte .LASF3 + 674 0057 03 .uleb128 0x3 + 675 0058 02 .byte 0x2 + 676 0059 07 .byte 0x7 + 677 005a 32010000 .4byte .LASF4 + 678 005e 04 .uleb128 0x4 + 679 005f 32020000 .4byte .LASF6 + 680 0063 02 .byte 0x2 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 13 + + + 681 0064 4F .byte 0x4f + 682 0065 69000000 .4byte 0x69 + 683 0069 03 .uleb128 0x3 + 684 006a 04 .byte 0x4 + 685 006b 05 .byte 0x5 + 686 006c AE000000 .4byte .LASF7 + 687 0070 04 .uleb128 0x4 + 688 0071 9C020000 .4byte .LASF8 + 689 0075 02 .byte 0x2 + 690 0076 50 .byte 0x50 + 691 0077 7B000000 .4byte 0x7b + 692 007b 03 .uleb128 0x3 + 693 007c 04 .byte 0x4 + 694 007d 07 .byte 0x7 + 695 007e 06010000 .4byte .LASF9 + 696 0082 03 .uleb128 0x3 + 697 0083 08 .byte 0x8 + 698 0084 05 .byte 0x5 + 699 0085 84000000 .4byte .LASF10 + 700 0089 03 .uleb128 0x3 + 701 008a 08 .byte 0x8 + 702 008b 07 .byte 0x7 + 703 008c 45000000 .4byte .LASF11 + 704 0090 04 .uleb128 0x4 + 705 0091 61010000 .4byte .LASF12 + 706 0095 03 .byte 0x3 + 707 0096 2F .byte 0x2f + 708 0097 3E000000 .4byte 0x3e + 709 009b 04 .uleb128 0x4 + 710 009c B7000000 .4byte .LASF13 + 711 00a0 03 .byte 0x3 + 712 00a1 30 .byte 0x30 + 713 00a2 3E000000 .4byte 0x3e + 714 00a6 04 .uleb128 0x4 + 715 00a7 1B020000 .4byte .LASF14 + 716 00ab 03 .byte 0x3 + 717 00ac 31 .byte 0x31 + 718 00ad 3E000000 .4byte 0x3e + 719 00b1 04 .uleb128 0x4 + 720 00b2 2A020000 .4byte .LASF15 + 721 00b6 03 .byte 0x3 + 722 00b7 32 .byte 0x32 + 723 00b8 70000000 .4byte 0x70 + 724 00bc 04 .uleb128 0x4 + 725 00bd 50010000 .4byte .LASF16 + 726 00c1 03 .byte 0x3 + 727 00c2 33 .byte 0x33 + 728 00c3 5E000000 .4byte 0x5e + 729 00c7 04 .uleb128 0x4 + 730 00c8 75010000 .4byte .LASF17 + 731 00cc 03 .byte 0x3 + 732 00cd 35 .byte 0x35 + 733 00ce 70000000 .4byte 0x70 + 734 00d2 04 .uleb128 0x4 + 735 00d3 C3020000 .4byte .LASF18 + 736 00d7 03 .byte 0x3 + 737 00d8 36 .byte 0x36 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 14 + + + 738 00d9 70000000 .4byte 0x70 + 739 00dd 04 .uleb128 0x4 + 740 00de EA000000 .4byte .LASF19 + 741 00e2 03 .byte 0x3 + 742 00e3 37 .byte 0x37 + 743 00e4 5E000000 .4byte 0x5e + 744 00e8 04 .uleb128 0x4 + 745 00e9 8A020000 .4byte .LASF20 + 746 00ed 04 .byte 0x4 + 747 00ee 2A .byte 0x2a + 748 00ef F3000000 .4byte 0xf3 + 749 00f3 05 .uleb128 0x5 + 750 00f4 8A020000 .4byte .LASF20 + 751 00f8 48 .byte 0x48 + 752 00f9 05 .byte 0x5 + 753 00fa 5E .byte 0x5e + 754 00fb 0A020000 .4byte 0x20a + 755 00ff 06 .uleb128 0x6 + 756 0100 72020000 .4byte .LASF21 + 757 0104 05 .byte 0x5 + 758 0105 5F .byte 0x5f + 759 0106 2F020000 .4byte 0x22f + 760 010a 02 .byte 0x2 + 761 010b 23 .byte 0x23 + 762 010c 00 .uleb128 0 + 763 010d 06 .uleb128 0x6 + 764 010e 23020000 .4byte .LASF22 + 765 0112 05 .byte 0x5 + 766 0113 61 .byte 0x61 + 767 0114 2F020000 .4byte 0x22f + 768 0118 02 .byte 0x2 + 769 0119 23 .byte 0x23 + 770 011a 04 .uleb128 0x4 + 771 011b 06 .uleb128 0x6 + 772 011c 7D000000 .4byte .LASF23 + 773 0120 05 .byte 0x5 + 774 0121 63 .byte 0x63 + 775 0122 B1000000 .4byte 0xb1 + 776 0126 02 .byte 0x2 + 777 0127 23 .byte 0x23 + 778 0128 08 .uleb128 0x8 + 779 0129 06 .uleb128 0x6 + 780 012a 6F030000 .4byte .LASF24 + 781 012e 05 .byte 0x5 + 782 012f 64 .byte 0x64 + 783 0130 FC020000 .4byte 0x2fc + 784 0134 02 .byte 0x2 + 785 0135 23 .byte 0x23 + 786 0136 0C .uleb128 0xc + 787 0137 06 .uleb128 0x6 + 788 0138 C0000000 .4byte .LASF25 + 789 013c 05 .byte 0x5 + 790 013d 66 .byte 0x66 + 791 013e 2F020000 .4byte 0x22f + 792 0142 02 .byte 0x2 + 793 0143 23 .byte 0x23 + 794 0144 10 .uleb128 0x10 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 15 + + + 795 0145 06 .uleb128 0x6 + 796 0146 A8010000 .4byte .LASF26 + 797 014a 05 .byte 0x5 + 798 014b 67 .byte 0x67 + 799 014c 2F020000 .4byte 0x22f + 800 0150 02 .byte 0x2 + 801 0151 23 .byte 0x23 + 802 0152 14 .uleb128 0x14 + 803 0153 06 .uleb128 0x6 + 804 0154 60030000 .4byte .LASF27 + 805 0158 05 .byte 0x5 + 806 0159 6E .byte 0x6e + 807 015a 4A040000 .4byte 0x44a + 808 015e 02 .byte 0x2 + 809 015f 23 .byte 0x23 + 810 0160 18 .uleb128 0x18 + 811 0161 06 .uleb128 0x6 + 812 0162 63020000 .4byte .LASF28 + 813 0166 05 .byte 0x5 + 814 0167 79 .byte 0x79 + 815 0168 9B000000 .4byte 0x9b + 816 016c 02 .byte 0x2 + 817 016d 23 .byte 0x23 + 818 016e 1C .uleb128 0x1c + 819 016f 06 .uleb128 0x6 + 820 0170 79020000 .4byte .LASF29 + 821 0174 05 .byte 0x5 + 822 0175 7D .byte 0x7d + 823 0176 90000000 .4byte 0x90 + 824 017a 02 .byte 0x2 + 825 017b 23 .byte 0x23 + 826 017c 1D .uleb128 0x1d + 827 017d 06 .uleb128 0x6 + 828 017e 1E030000 .4byte .LASF30 + 829 0182 05 .byte 0x5 + 830 0183 82 .byte 0x82 + 831 0184 A6000000 .4byte 0xa6 + 832 0188 02 .byte 0x2 + 833 0189 23 .byte 0x23 + 834 018a 1E .uleb128 0x1e + 835 018b 06 .uleb128 0x6 + 836 018c D8020000 .4byte .LASF31 + 837 0190 05 .byte 0x5 + 838 0191 89 .byte 0x89 + 839 0192 26030000 .4byte 0x326 + 840 0196 02 .byte 0x2 + 841 0197 23 .byte 0x23 + 842 0198 20 .uleb128 0x20 + 843 0199 07 .uleb128 0x7 + 844 019a 705F7500 .ascii "p_u\000" + 845 019e 05 .byte 0x5 + 846 019f AE .byte 0xae + 847 01a0 15040000 .4byte 0x415 + 848 01a4 02 .byte 0x2 + 849 01a5 23 .byte 0x23 + 850 01a6 24 .uleb128 0x24 + 851 01a7 06 .uleb128 0x6 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 16 + + + 852 01a8 75030000 .4byte .LASF32 + 853 01ac 05 .byte 0x5 + 854 01ad B3 .byte 0xb3 + 855 01ae 57020000 .4byte 0x257 + 856 01b2 02 .byte 0x2 + 857 01b3 23 .byte 0x23 + 858 01b4 28 .uleb128 0x28 + 859 01b5 06 .uleb128 0x6 + 860 01b6 F4020000 .4byte .LASF33 + 861 01ba 05 .byte 0x5 + 862 01bb B9 .byte 0xb9 + 863 01bc 35020000 .4byte 0x235 + 864 01c0 02 .byte 0x2 + 865 01c1 23 .byte 0x23 + 866 01c2 2C .uleb128 0x2c + 867 01c3 06 .uleb128 0x6 + 868 01c4 00000000 .4byte .LASF34 + 869 01c8 05 .byte 0x5 + 870 01c9 BD .byte 0xbd + 871 01ca BC000000 .4byte 0xbc + 872 01ce 02 .byte 0x2 + 873 01cf 23 .byte 0x23 + 874 01d0 34 .uleb128 0x34 + 875 01d1 06 .uleb128 0x6 + 876 01d2 91020000 .4byte .LASF35 + 877 01d6 05 .byte 0x5 + 878 01d7 C3 .byte 0xc3 + 879 01d8 C7000000 .4byte 0xc7 + 880 01dc 02 .byte 0x2 + 881 01dd 23 .byte 0x23 + 882 01de 38 .uleb128 0x38 + 883 01df 06 .uleb128 0x6 + 884 01e0 4F020000 .4byte .LASF36 + 885 01e4 05 .byte 0x5 + 886 01e5 CA .byte 0xca + 887 01e6 5C040000 .4byte 0x45c + 888 01ea 02 .byte 0x2 + 889 01eb 23 .byte 0x23 + 890 01ec 3C .uleb128 0x3c + 891 01ed 06 .uleb128 0x6 + 892 01ee CD020000 .4byte .LASF37 + 893 01f2 05 .byte 0x5 + 894 01f3 CE .byte 0xce + 895 01f4 B1000000 .4byte 0xb1 + 896 01f8 02 .byte 0x2 + 897 01f9 23 .byte 0x23 + 898 01fa 40 .uleb128 0x40 + 899 01fb 06 .uleb128 0x6 + 900 01fc 9E000000 .4byte .LASF38 + 901 0200 05 .byte 0x5 + 902 0201 D4 .byte 0xd4 + 903 0202 6D020000 .4byte 0x26d + 904 0206 02 .byte 0x2 + 905 0207 23 .byte 0x23 + 906 0208 44 .uleb128 0x44 + 907 0209 00 .byte 0 + 908 020a 08 .uleb128 0x8 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 17 + + + 909 020b 08 .byte 0x8 + 910 020c 04 .byte 0x4 + 911 020d 61 .byte 0x61 + 912 020e 2F020000 .4byte 0x22f + 913 0212 06 .uleb128 0x6 + 914 0213 72020000 .4byte .LASF21 + 915 0217 04 .byte 0x4 + 916 0218 62 .byte 0x62 + 917 0219 2F020000 .4byte 0x22f + 918 021d 02 .byte 0x2 + 919 021e 23 .byte 0x23 + 920 021f 00 .uleb128 0 + 921 0220 06 .uleb128 0x6 + 922 0221 23020000 .4byte .LASF22 + 923 0225 04 .byte 0x4 + 924 0226 64 .byte 0x64 + 925 0227 2F020000 .4byte 0x22f + 926 022b 02 .byte 0x2 + 927 022c 23 .byte 0x23 + 928 022d 04 .uleb128 0x4 + 929 022e 00 .byte 0 + 930 022f 09 .uleb128 0x9 + 931 0230 04 .byte 0x4 + 932 0231 E8000000 .4byte 0xe8 + 933 0235 04 .uleb128 0x4 + 934 0236 F3010000 .4byte .LASF39 + 935 023a 04 .byte 0x4 + 936 023b 66 .byte 0x66 + 937 023c 0A020000 .4byte 0x20a + 938 0240 08 .uleb128 0x8 + 939 0241 04 .byte 0x4 + 940 0242 04 .byte 0x4 + 941 0243 6B .byte 0x6b + 942 0244 57020000 .4byte 0x257 + 943 0248 06 .uleb128 0x6 + 944 0249 72020000 .4byte .LASF21 + 945 024d 04 .byte 0x4 + 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19030000 .4byte 0x319 + 1049 0309 0B .uleb128 0xb + 1050 030a 72313300 .ascii "r13\000" + 1051 030e 06 .byte 0x6 + 1052 030f 2401 .2byte 0x124 + 1053 0311 19030000 .4byte 0x319 + 1054 0315 02 .byte 0x2 + 1055 0316 23 .byte 0x23 + 1056 0317 00 .uleb128 0 + 1057 0318 00 .byte 0 + 1058 0319 09 .uleb128 0x9 + 1059 031a 04 .byte 0x4 + 1060 031b 6F020000 .4byte 0x26f + 1061 031f 03 .uleb128 0x3 + 1062 0320 04 .byte 0x4 + 1063 0321 07 .byte 0x7 + 1064 0322 8C010000 .4byte .LASF44 + 1065 0326 0D .uleb128 0xd + 1066 0327 D2000000 .4byte 0xd2 + 1067 032b 05 .uleb128 0x5 + 1068 032c 09030000 .4byte .LASF45 + 1069 0330 0C .byte 0xc + 1070 0331 07 .byte 0x7 + 1071 0332 2C .byte 0x2c + 1072 0333 54030000 .4byte 0x354 + 1073 0337 06 .uleb128 0x6 + 1074 0338 C8000000 .4byte .LASF46 + 1075 033c 07 .byte 0x7 + 1076 033d 2D .byte 0x2d + 1077 033e 35020000 .4byte 0x235 + 1078 0342 02 .byte 0x2 + 1079 0343 23 .byte 0x23 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 20 + + + 1080 0344 00 .uleb128 0 + 1081 0345 06 .uleb128 0x6 + 1082 0346 24010000 .4byte .LASF47 + 1083 034a 07 .byte 0x7 + 1084 034b 2F .byte 0x2f + 1085 034c DD000000 .4byte 0xdd + 1086 0350 02 .byte 0x2 + 1087 0351 23 .byte 0x23 + 1088 0352 08 .uleb128 0x8 + 1089 0353 00 .byte 0 + 1090 0354 04 .uleb128 0x4 + 1091 0355 09030000 .4byte .LASF45 + 1092 0359 07 .byte 0x7 + 1093 035a 30 .byte 0x30 + 1094 035b 2B030000 .4byte 0x32b + 1095 035f 05 .uleb128 0x5 + 1096 0360 81010000 .4byte .LASF48 + 1097 0364 10 .byte 0x10 + 1098 0365 08 .byte 0x8 + 1099 0366 2C .byte 0x2c + 1100 0367 96030000 .4byte 0x396 + 1101 036b 06 .uleb128 0x6 + 1102 036c A6000000 .4byte .LASF49 + 1103 0370 08 .byte 0x8 + 1104 0371 2D .byte 0x2d + 1105 0372 35020000 .4byte 0x235 + 1106 0376 02 .byte 0x2 + 1107 0377 23 .byte 0x23 + 1108 0378 00 .uleb128 0 + 1109 0379 06 .uleb128 0x6 + 1110 037a 67030000 .4byte .LASF50 + 1111 037e 08 .byte 0x8 + 1112 037f 2F .byte 0x2f + 1113 0380 2F020000 .4byte 0x22f + 1114 0384 02 .byte 0x2 + 1115 0385 23 .byte 0x23 + 1116 0386 08 .uleb128 0x8 + 1117 0387 06 .uleb128 0x6 + 1118 0388 BC020000 .4byte .LASF51 + 1119 038c 08 .byte 0x8 + 1120 038d 31 .byte 0x31 + 1121 038e 96030000 .4byte 0x396 + 1122 0392 02 .byte 0x2 + 1123 0393 23 .byte 0x23 + 1124 0394 0C .uleb128 0xc + 1125 0395 00 .byte 0 + 1126 0396 09 .uleb128 0x9 + 1127 0397 04 .byte 0x4 + 1128 0398 5F030000 .4byte 0x35f + 1129 039c 04 .uleb128 0x4 + 1130 039d 81010000 .4byte .LASF48 + 1131 03a1 08 .byte 0x8 + 1132 03a2 33 .byte 0x33 + 1133 03a3 5F030000 .4byte 0x35f + 1134 03a7 08 .uleb128 0x8 + 1135 03a8 28 .byte 0x28 + 1136 03a9 09 .byte 0x9 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 21 + + + 1137 03aa 33 .byte 0x33 + 1138 03ab 04040000 .4byte 0x404 + 1139 03af 06 .uleb128 0x6 + 1140 03b0 00020000 .4byte .LASF52 + 1141 03b4 09 .byte 0x9 + 1142 03b5 34 .byte 0x34 + 1143 03b6 04040000 .4byte 0x404 + 1144 03ba 02 .byte 0x2 + 1145 03bb 23 .byte 0x23 + 1146 03bc 00 .uleb128 0 + 1147 03bd 06 .uleb128 0x6 + 1148 03be 48020000 .4byte .LASF53 + 1149 03c2 09 .byte 0x9 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1185 0401 23 .byte 0x23 + 1186 0402 1C .uleb128 0x1c + 1187 0403 00 .byte 0 + 1188 0404 09 .uleb128 0x9 + 1189 0405 04 .byte 0x4 + 1190 0406 BC000000 .4byte 0xbc + 1191 040a 04 .uleb128 0x4 + 1192 040b 2E000000 .4byte .LASF58 + 1193 040f 09 .byte 0x9 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 22 + + + 1194 0410 3E .byte 0x3e + 1195 0411 A7030000 .4byte 0x3a7 + 1196 0415 0E .uleb128 0xe + 1197 0416 04 .byte 0x4 + 1198 0417 05 .byte 0x5 + 1199 0418 90 .byte 0x90 + 1200 0419 4A040000 .4byte 0x44a + 1201 041d 0F .uleb128 0xf + 1202 041e 13000000 .4byte .LASF59 + 1203 0422 05 .byte 0x5 + 1204 0423 97 .byte 0x97 + 1205 0424 BC000000 .4byte 0xbc + 1206 0428 0F .uleb128 0xf + 1207 0429 5C000000 .4byte .LASF60 + 1208 042d 05 .byte 0x5 + 1209 042e 9E .byte 0x9e + 1210 042f BC000000 .4byte 0xbc + 1211 0433 0F .uleb128 0xf + 1212 0434 59030000 .4byte .LASF61 + 1213 0438 05 .byte 0x5 + 1214 0439 A5 .byte 0xa5 + 1215 043a 6D020000 .4byte 0x26d + 1216 043e 0F .uleb128 0xf + 1217 043f 6B020000 .4byte .LASF62 + 1218 0443 05 .byte 0x5 + 1219 0444 AC .byte 0xac + 1220 0445 C7000000 .4byte 0xc7 + 1221 0449 00 .byte 0 + 1222 044a 09 .uleb128 0x9 + 1223 044b 04 .byte 0x4 + 1224 044c 50040000 .4byte 0x450 + 1225 0450 10 .uleb128 0x10 + 1226 0451 55040000 .4byte 0x455 + 1227 0455 03 .uleb128 0x3 + 1228 0456 01 .byte 0x1 + 1229 0457 08 .byte 0x8 + 1230 0458 A5020000 .4byte .LASF63 + 1231 045c 09 .uleb128 0x9 + 1232 045d 04 .byte 0x4 + 1233 045e 9C030000 .4byte 0x39c + 1234 0462 11 .uleb128 0x11 + 1235 0463 01 .byte 0x1 + 1236 0464 FD000000 .4byte .LASF64 + 1237 0468 01 .byte 0x1 + 1238 0469 48 .byte 0x48 + 1239 046a 01 .byte 0x1 + 1240 046b 00000000 .4byte .LFB7 + 1241 046f 2A000000 .4byte .LFE7 + 1242 0473 00000000 .4byte .LLST0 + 1243 0477 01 .byte 0x1 + 1244 0478 D9040000 .4byte 0x4d9 + 1245 047c 12 .uleb128 0x12 + 1246 047d 6D627000 .ascii "mbp\000" + 1247 0481 01 .byte 0x1 + 1248 0482 48 .byte 0x48 + 1249 0483 D9040000 .4byte 0x4d9 + 1250 0487 20000000 .4byte .LLST1 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 23 + + + 1251 048b 12 .uleb128 0x12 + 1252 048c 62756600 .ascii "buf\000" + 1253 0490 01 .byte 0x1 + 1254 0491 48 .byte 0x48 + 1255 0492 04040000 .4byte 0x404 + 1256 0496 3E000000 .4byte .LLST2 + 1257 049a 12 .uleb128 0x12 + 1258 049b 6E00 .ascii "n\000" + 1259 049d 01 .byte 0x1 + 1260 049e 48 .byte 0x48 + 1261 049f DD000000 .4byte 0xdd + 1262 04a3 6A000000 .4byte .LLST3 + 1263 04a7 13 .uleb128 0x13 + 1264 04a8 1C000000 .4byte .LVL3 + 1265 04ac 60090000 .4byte 0x960 + 1266 04b0 C2040000 .4byte 0x4c2 + 1267 04b4 14 .uleb128 0x14 + 1268 04b5 01 .byte 0x1 + 1269 04b6 51 .byte 0x51 + 1270 04b7 03 .byte 0x3 + 1271 04b8 F3 .byte 0xf3 + 1272 04b9 01 .uleb128 0x1 + 1273 04ba 52 .byte 0x52 + 1274 04bb 14 .uleb128 0x14 + 1275 04bc 01 .byte 0x1 + 1276 04bd 50 .byte 0x50 + 1277 04be 02 .byte 0x2 + 1278 04bf 74 .byte 0x74 + 1279 04c0 1C .sleb128 28 + 1280 04c1 00 .byte 0 + 1281 04c2 15 .uleb128 0x15 + 1282 04c3 2A000000 .4byte .LVL4 + 1283 04c7 01 .byte 0x1 + 1284 04c8 60090000 .4byte 0x960 + 1285 04cc 14 .uleb128 0x14 + 1286 04cd 01 .byte 0x1 + 1287 04ce 51 .byte 0x51 + 1288 04cf 01 .byte 0x1 + 1289 04d0 30 .byte 0x30 + 1290 04d1 14 .uleb128 0x14 + 1291 04d2 01 .byte 0x1 + 1292 04d3 50 .byte 0x50 + 1293 04d4 02 .byte 0x2 + 1294 04d5 74 .byte 0x74 + 1295 04d6 10 .sleb128 16 + 1296 04d7 00 .byte 0 + 1297 04d8 00 .byte 0 + 1298 04d9 09 .uleb128 0x9 + 1299 04da 04 .byte 0x4 + 1300 04db 0A040000 .4byte 0x40a + 1301 04df 11 .uleb128 0x11 + 1302 04e0 01 .byte 0x1 + 1303 04e1 9E010000 .4byte .LASF65 + 1304 04e5 01 .byte 0x1 + 1305 04e6 5B .byte 0x5b + 1306 04e7 01 .byte 0x1 + 1307 04e8 00000000 .4byte .LFB8 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 24 + + + 1308 04ec 2C000000 .4byte .LFE8 + 1309 04f0 8B000000 .4byte .LLST4 + 1310 04f4 01 .byte 0x1 + 1311 04f5 3F050000 .4byte 0x53f + 1312 04f9 12 .uleb128 0x12 + 1313 04fa 6D627000 .ascii "mbp\000" + 1314 04fe 01 .byte 0x1 + 1315 04ff 5B .byte 0x5b + 1316 0500 D9040000 .4byte 0x4d9 + 1317 0504 AB000000 .4byte .LLST5 + 1318 0508 13 .uleb128 0x13 + 1319 0509 1A000000 .4byte .LVL7 + 1320 050d 7F090000 .4byte 0x97f + 1321 0511 1C050000 .4byte 0x51c + 1322 0515 14 .uleb128 0x14 + 1323 0516 01 .byte 0x1 + 1324 0517 50 .byte 0x50 + 1325 0518 02 .byte 0x2 + 1326 0519 74 .byte 0x74 + 1327 051a 1C .sleb128 28 + 1328 051b 00 .byte 0 + 1329 051c 13 .uleb128 0x13 + 1330 051d 24000000 .4byte .LVL8 + 1331 0521 7F090000 .4byte 0x97f + 1332 0525 35050000 .4byte 0x535 + 1333 0529 14 .uleb128 0x14 + 1334 052a 01 .byte 0x1 + 1335 052b 51 .byte 0x51 + 1336 052c 01 .byte 0x1 + 1337 052d 30 .byte 0x30 + 1338 052e 14 .uleb128 0x14 + 1339 052f 01 .byte 0x1 + 1340 0530 50 .byte 0x50 + 1341 0531 02 .byte 0x2 + 1342 0532 74 .byte 0x74 + 1343 0533 10 .sleb128 16 + 1344 0534 00 .byte 0 + 1345 0535 16 .uleb128 0x16 + 1346 0536 28000000 .4byte .LVL9 + 1347 053a 98090000 .4byte 0x998 + 1348 053e 00 .byte 0 + 1349 053f 17 .uleb128 0x17 + 1350 0540 01 .byte 0x1 + 1351 0541 24000000 .4byte .LASF67 + 1352 0545 01 .byte 0x1 + 1353 0546 96 .byte 0x96 + 1354 0547 01 .byte 0x1 + 1355 0548 BC000000 .4byte 0xbc + 1356 054c 00000000 .4byte .LFB10 + 1357 0550 38000000 .4byte .LFE10 + 1358 0554 C9000000 .4byte .LLST6 + 1359 0558 01 .byte 0x1 + 1360 0559 D2050000 .4byte 0x5d2 + 1361 055d 12 .uleb128 0x12 + 1362 055e 6D627000 .ascii "mbp\000" + 1363 0562 01 .byte 0x1 + 1364 0563 96 .byte 0x96 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 25 + + + 1365 0564 D9040000 .4byte 0x4d9 + 1366 0568 E9000000 .4byte .LLST7 + 1367 056c 12 .uleb128 0x12 + 1368 056d 6D736700 .ascii "msg\000" + 1369 0571 01 .byte 0x1 + 1370 0572 96 .byte 0x96 + 1371 0573 BC000000 .4byte 0xbc + 1372 0577 07010000 .4byte .LLST8 + 1373 057b 18 .uleb128 0x18 + 1374 057c 0A020000 .4byte .LASF66 + 1375 0580 01 .byte 0x1 + 1376 0581 96 .byte 0x96 + 1377 0582 D2000000 .4byte 0xd2 + 1378 0586 25010000 .4byte .LLST9 + 1379 058a 19 .uleb128 0x19 + 1380 058b 13000000 .4byte .LASF59 + 1381 058f 01 .byte 0x1 + 1382 0590 97 .byte 0x97 + 1383 0591 BC000000 .4byte 0xbc + 1384 0595 46010000 .4byte .LLST10 + 1385 0599 13 .uleb128 0x13 + 1386 059a 10000000 .4byte .LVL13 + 1387 059e A2090000 .4byte 0x9a2 + 1388 05a2 B4050000 .4byte 0x5b4 + 1389 05a6 14 .uleb128 0x14 + 1390 05a7 01 .byte 0x1 + 1391 05a8 51 .byte 0x51 + 1392 05a9 03 .byte 0x3 + 1393 05aa F3 .byte 0xf3 + 1394 05ab 01 .uleb128 0x1 + 1395 05ac 52 .byte 0x52 + 1396 05ad 14 .uleb128 0x14 + 1397 05ae 01 .byte 0x1 + 1398 05af 50 .byte 0x50 + 1399 05b0 02 .byte 0x2 + 1400 05b1 74 .byte 0x74 + 1401 05b2 1C .sleb128 28 + 1402 05b3 00 .byte 0 + 1403 05b4 13 .uleb128 0x13 + 1404 05b5 30000000 .4byte .LVL15 + 1405 05b9 BF090000 .4byte 0x9bf + 1406 05bd C8050000 .4byte 0x5c8 + 1407 05c1 14 .uleb128 0x14 + 1408 05c2 01 .byte 0x1 + 1409 05c3 50 .byte 0x50 + 1410 05c4 02 .byte 0x2 + 1411 05c5 74 .byte 0x74 + 1412 05c6 10 .sleb128 16 + 1413 05c7 00 .byte 0 + 1414 05c8 16 .uleb128 0x16 + 1415 05c9 34000000 .4byte .LVL16 + 1416 05cd 98090000 .4byte 0x998 + 1417 05d1 00 .byte 0 + 1418 05d2 17 .uleb128 0x17 + 1419 05d3 01 .byte 0x1 + 1420 05d4 81020000 .4byte .LASF68 + 1421 05d8 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 26 + + + 1422 05d9 7A .byte 0x7a + 1423 05da 01 .byte 0x1 + 1424 05db BC000000 .4byte 0xbc + 1425 05df 00000000 .4byte .LFB9 + 1426 05e3 0C000000 .4byte .LFE9 + 1427 05e7 64010000 .4byte .LLST11 + 1428 05eb 01 .byte 0x1 + 1429 05ec 4A060000 .4byte 0x64a + 1430 05f0 12 .uleb128 0x12 + 1431 05f1 6D627000 .ascii "mbp\000" + 1432 05f5 01 .byte 0x1 + 1433 05f6 7A .byte 0x7a + 1434 05f7 D9040000 .4byte 0x4d9 + 1435 05fb 84010000 .4byte .LLST12 + 1436 05ff 12 .uleb128 0x12 + 1437 0600 6D736700 .ascii "msg\000" + 1438 0604 01 .byte 0x1 + 1439 0605 7A .byte 0x7a + 1440 0606 BC000000 .4byte 0xbc + 1441 060a A5010000 .4byte .LLST13 + 1442 060e 18 .uleb128 0x18 + 1443 060f 0A020000 .4byte .LASF66 + 1444 0613 01 .byte 0x1 + 1445 0614 7A .byte 0x7a + 1446 0615 D2000000 .4byte 0xd2 + 1447 0619 C6010000 .4byte .LLST14 + 1448 061d 1A .uleb128 0x1a + 1449 061e 13000000 .4byte .LASF59 + 1450 0622 01 .byte 0x1 + 1451 0623 7B .byte 0x7b + 1452 0624 BC000000 .4byte 0xbc + 1453 0628 01 .byte 0x1 + 1454 0629 50 .byte 0x50 + 1455 062a 1B .uleb128 0x1b + 1456 062b 08000000 .4byte .LVL18 + 1457 062f 3F050000 .4byte 0x53f + 1458 0633 14 .uleb128 0x14 + 1459 0634 01 .byte 0x1 + 1460 0635 52 .byte 0x52 + 1461 0636 03 .byte 0x3 + 1462 0637 F3 .byte 0xf3 + 1463 0638 01 .uleb128 0x1 + 1464 0639 52 .byte 0x52 + 1465 063a 14 .uleb128 0x14 + 1466 063b 01 .byte 0x1 + 1467 063c 51 .byte 0x51 + 1468 063d 03 .byte 0x3 + 1469 063e F3 .byte 0xf3 + 1470 063f 01 .uleb128 0x1 + 1471 0640 51 .byte 0x51 + 1472 0641 14 .uleb128 0x14 + 1473 0642 01 .byte 0x1 + 1474 0643 50 .byte 0x50 + 1475 0644 03 .byte 0x3 + 1476 0645 F3 .byte 0xf3 + 1477 0646 01 .uleb128 0x1 + 1478 0647 50 .byte 0x50 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 27 + + + 1479 0648 00 .byte 0 + 1480 0649 00 .byte 0 + 1481 064a 17 .uleb128 0x17 + 1482 064b 01 .byte 0x1 + 1483 064c 1A000000 .4byte .LASF69 + 1484 0650 01 .byte 0x1 + 1485 0651 B5 .byte 0xb5 + 1486 0652 01 .byte 0x1 + 1487 0653 BC000000 .4byte 0xbc + 1488 0657 00000000 .4byte .LFB11 + 1489 065b 2E000000 .4byte .LFE11 + 1490 065f E7010000 .4byte .LLST15 + 1491 0663 01 .byte 0x1 + 1492 0664 9A060000 .4byte 0x69a + 1493 0668 12 .uleb128 0x12 + 1494 0669 6D627000 .ascii "mbp\000" + 1495 066d 01 .byte 0x1 + 1496 066e B5 .byte 0xb5 + 1497 066f D9040000 .4byte 0x4d9 + 1498 0673 07020000 .4byte .LLST16 + 1499 0677 12 .uleb128 0x12 + 1500 0678 6D736700 .ascii "msg\000" + 1501 067c 01 .byte 0x1 + 1502 067d B5 .byte 0xb5 + 1503 067e BC000000 .4byte 0xbc + 1504 0682 4E020000 .4byte .LLST17 + 1505 0686 1B .uleb128 0x1b + 1506 0687 24000000 .4byte .LVL21 + 1507 068b BF090000 .4byte 0x9bf + 1508 068f 14 .uleb128 0x14 + 1509 0690 01 .byte 0x1 + 1510 0691 50 .byte 0x50 + 1511 0692 05 .byte 0x5 + 1512 0693 F3 .byte 0xf3 + 1513 0694 01 .uleb128 0x1 + 1514 0695 50 .byte 0x50 + 1515 0696 23 .byte 0x23 + 1516 0697 10 .uleb128 0x10 + 1517 0698 00 .byte 0 + 1518 0699 00 .byte 0 + 1519 069a 17 .uleb128 0x17 + 1520 069b 01 .byte 0x1 + 1521 069c 65000000 .4byte .LASF70 + 1522 06a0 01 .byte 0x1 + 1523 06a1 F3 .byte 0xf3 + 1524 06a2 01 .byte 0x1 + 1525 06a3 BC000000 .4byte 0xbc + 1526 06a7 00000000 .4byte .LFB13 + 1527 06ab 3A000000 .4byte .LFE13 + 1528 06af 7A020000 .4byte .LLST18 + 1529 06b3 01 .byte 0x1 + 1530 06b4 2D070000 .4byte 0x72d + 1531 06b8 12 .uleb128 0x12 + 1532 06b9 6D627000 .ascii "mbp\000" + 1533 06bd 01 .byte 0x1 + 1534 06be F3 .byte 0xf3 + 1535 06bf D9040000 .4byte 0x4d9 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 28 + + + 1536 06c3 9A020000 .4byte .LLST19 + 1537 06c7 12 .uleb128 0x12 + 1538 06c8 6D736700 .ascii "msg\000" + 1539 06cc 01 .byte 0x1 + 1540 06cd F3 .byte 0xf3 + 1541 06ce BC000000 .4byte 0xbc + 1542 06d2 B8020000 .4byte .LLST20 + 1543 06d6 18 .uleb128 0x18 + 1544 06d7 0A020000 .4byte .LASF66 + 1545 06db 01 .byte 0x1 + 1546 06dc F3 .byte 0xf3 + 1547 06dd D2000000 .4byte 0xd2 + 1548 06e1 D6020000 .4byte .LLST21 + 1549 06e5 19 .uleb128 0x19 + 1550 06e6 13000000 .4byte .LASF59 + 1551 06ea 01 .byte 0x1 + 1552 06eb F4 .byte 0xf4 + 1553 06ec BC000000 .4byte 0xbc + 1554 06f0 F7020000 .4byte .LLST22 + 1555 06f4 13 .uleb128 0x13 + 1556 06f5 10000000 .4byte .LVL27 + 1557 06f9 A2090000 .4byte 0x9a2 + 1558 06fd 0F070000 .4byte 0x70f + 1559 0701 14 .uleb128 0x14 + 1560 0702 01 .byte 0x1 + 1561 0703 51 .byte 0x51 + 1562 0704 03 .byte 0x3 + 1563 0705 F3 .byte 0xf3 + 1564 0706 01 .uleb128 0x1 + 1565 0707 52 .byte 0x52 + 1566 0708 14 .uleb128 0x14 + 1567 0709 01 .byte 0x1 + 1568 070a 50 .byte 0x50 + 1569 070b 02 .byte 0x2 + 1570 070c 74 .byte 0x74 + 1571 070d 1C .sleb128 28 + 1572 070e 00 .byte 0 + 1573 070f 13 .uleb128 0x13 + 1574 0710 2A000000 .4byte .LVL29 + 1575 0714 BF090000 .4byte 0x9bf + 1576 0718 23070000 .4byte 0x723 + 1577 071c 14 .uleb128 0x14 + 1578 071d 01 .byte 0x1 + 1579 071e 50 .byte 0x50 + 1580 071f 02 .byte 0x2 + 1581 0720 74 .byte 0x74 + 1582 0721 10 .sleb128 16 + 1583 0722 00 .byte 0 + 1584 0723 16 .uleb128 0x16 + 1585 0724 2E000000 .4byte .LVL30 + 1586 0728 98090000 .4byte 0x998 + 1587 072c 00 .byte 0 + 1588 072d 17 .uleb128 0x17 + 1589 072e 01 .byte 0x1 + 1590 072f DF020000 .4byte .LASF71 + 1591 0733 01 .byte 0x1 + 1592 0734 D7 .byte 0xd7 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 29 + + + 1593 0735 01 .byte 0x1 + 1594 0736 BC000000 .4byte 0xbc + 1595 073a 00000000 .4byte .LFB12 + 1596 073e 0C000000 .4byte .LFE12 + 1597 0742 20030000 .4byte .LLST23 + 1598 0746 01 .byte 0x1 + 1599 0747 A5070000 .4byte 0x7a5 + 1600 074b 12 .uleb128 0x12 + 1601 074c 6D627000 .ascii "mbp\000" + 1602 0750 01 .byte 0x1 + 1603 0751 D7 .byte 0xd7 + 1604 0752 D9040000 .4byte 0x4d9 + 1605 0756 40030000 .4byte .LLST24 + 1606 075a 12 .uleb128 0x12 + 1607 075b 6D736700 .ascii "msg\000" + 1608 075f 01 .byte 0x1 + 1609 0760 D7 .byte 0xd7 + 1610 0761 BC000000 .4byte 0xbc + 1611 0765 61030000 .4byte .LLST25 + 1612 0769 18 .uleb128 0x18 + 1613 076a 0A020000 .4byte .LASF66 + 1614 076e 01 .byte 0x1 + 1615 076f D7 .byte 0xd7 + 1616 0770 D2000000 .4byte 0xd2 + 1617 0774 82030000 .4byte .LLST26 + 1618 0778 1A .uleb128 0x1a + 1619 0779 13000000 .4byte .LASF59 + 1620 077d 01 .byte 0x1 + 1621 077e D8 .byte 0xd8 + 1622 077f BC000000 .4byte 0xbc + 1623 0783 01 .byte 0x1 + 1624 0784 50 .byte 0x50 + 1625 0785 1B .uleb128 0x1b + 1626 0786 08000000 .4byte .LVL33 + 1627 078a 9A060000 .4byte 0x69a + 1628 078e 14 .uleb128 0x14 + 1629 078f 01 .byte 0x1 + 1630 0790 52 .byte 0x52 + 1631 0791 03 .byte 0x3 + 1632 0792 F3 .byte 0xf3 + 1633 0793 01 .uleb128 0x1 + 1634 0794 52 .byte 0x52 + 1635 0795 14 .uleb128 0x14 + 1636 0796 01 .byte 0x1 + 1637 0797 51 .byte 0x51 + 1638 0798 03 .byte 0x3 + 1639 0799 F3 .byte 0xf3 + 1640 079a 01 .uleb128 0x1 + 1641 079b 51 .byte 0x51 + 1642 079c 14 .uleb128 0x14 + 1643 079d 01 .byte 0x1 + 1644 079e 50 .byte 0x50 + 1645 079f 03 .byte 0x3 + 1646 07a0 F3 .byte 0xf3 + 1647 07a1 01 .uleb128 0x1 + 1648 07a2 50 .byte 0x50 + 1649 07a3 00 .byte 0 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 30 + + + 1650 07a4 00 .byte 0 + 1651 07a5 1C .uleb128 0x1c + 1652 07a6 01 .byte 0x1 + 1653 07a7 36000000 .4byte .LASF72 + 1654 07ab 01 .byte 0x1 + 1655 07ac 1201 .2byte 0x112 + 1656 07ae 01 .byte 0x1 + 1657 07af BC000000 .4byte 0xbc + 1658 07b3 00000000 .4byte .LFB14 + 1659 07b7 30000000 .4byte .LFE14 + 1660 07bb A3030000 .4byte .LLST27 + 1661 07bf 01 .byte 0x1 + 1662 07c0 F8070000 .4byte 0x7f8 + 1663 07c4 1D .uleb128 0x1d + 1664 07c5 6D627000 .ascii "mbp\000" + 1665 07c9 01 .byte 0x1 + 1666 07ca 1201 .2byte 0x112 + 1667 07cc D9040000 .4byte 0x4d9 + 1668 07d0 C3030000 .4byte .LLST28 + 1669 07d4 1D .uleb128 0x1d + 1670 07d5 6D736700 .ascii "msg\000" + 1671 07d9 01 .byte 0x1 + 1672 07da 1201 .2byte 0x112 + 1673 07dc BC000000 .4byte 0xbc + 1674 07e0 0A040000 .4byte .LLST29 + 1675 07e4 1B .uleb128 0x1b + 1676 07e5 26000000 .4byte .LVL36 + 1677 07e9 BF090000 .4byte 0x9bf + 1678 07ed 14 .uleb128 0x14 + 1679 07ee 01 .byte 0x1 + 1680 07ef 50 .byte 0x50 + 1681 07f0 05 .byte 0x5 + 1682 07f1 F3 .byte 0xf3 + 1683 07f2 01 .uleb128 0x1 + 1684 07f3 50 .byte 0x50 + 1685 07f4 23 .byte 0x23 + 1686 07f5 10 .uleb128 0x10 + 1687 07f6 00 .byte 0 + 1688 07f7 00 .byte 0 + 1689 07f8 1C .uleb128 0x1c + 1690 07f9 01 .byte 0x1 + 1691 07fa 56010000 .4byte .LASF73 + 1692 07fe 01 .byte 0x1 + 1693 07ff 5001 .2byte 0x150 + 1694 0801 01 .byte 0x1 + 1695 0802 BC000000 .4byte 0xbc + 1696 0806 00000000 .4byte .LFB16 + 1697 080a 38000000 .4byte .LFE16 + 1698 080e 36040000 .4byte .LLST30 + 1699 0812 01 .byte 0x1 + 1700 0813 90080000 .4byte 0x890 + 1701 0817 1D .uleb128 0x1d + 1702 0818 6D627000 .ascii "mbp\000" + 1703 081c 01 .byte 0x1 + 1704 081d 5001 .2byte 0x150 + 1705 081f D9040000 .4byte 0x4d9 + 1706 0823 56040000 .4byte .LLST31 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 31 + + + 1707 0827 1E .uleb128 0x1e + 1708 0828 87010000 .4byte .LASF74 + 1709 082c 01 .byte 0x1 + 1710 082d 5001 .2byte 0x150 + 1711 082f 04040000 .4byte 0x404 + 1712 0833 74040000 .4byte .LLST32 + 1713 0837 1E .uleb128 0x1e + 1714 0838 0A020000 .4byte .LASF66 + 1715 083c 01 .byte 0x1 + 1716 083d 5001 .2byte 0x150 + 1717 083f D2000000 .4byte 0xd2 + 1718 0843 92040000 .4byte .LLST33 + 1719 0847 1F .uleb128 0x1f + 1720 0848 13000000 .4byte .LASF59 + 1721 084c 01 .byte 0x1 + 1722 084d 5101 .2byte 0x151 + 1723 084f BC000000 .4byte 0xbc + 1724 0853 B3040000 .4byte .LLST34 + 1725 0857 13 .uleb128 0x13 + 1726 0858 10000000 .4byte .LVL42 + 1727 085c A2090000 .4byte 0x9a2 + 1728 0860 72080000 .4byte 0x872 + 1729 0864 14 .uleb128 0x14 + 1730 0865 01 .byte 0x1 + 1731 0866 51 .byte 0x51 + 1732 0867 03 .byte 0x3 + 1733 0868 F3 .byte 0xf3 + 1734 0869 01 .uleb128 0x1 + 1735 086a 52 .byte 0x52 + 1736 086b 14 .uleb128 0x14 + 1737 086c 01 .byte 0x1 + 1738 086d 50 .byte 0x50 + 1739 086e 02 .byte 0x2 + 1740 086f 74 .byte 0x74 + 1741 0870 10 .sleb128 16 + 1742 0871 00 .byte 0 + 1743 0872 13 .uleb128 0x13 + 1744 0873 30000000 .4byte .LVL44 + 1745 0877 BF090000 .4byte 0x9bf + 1746 087b 86080000 .4byte 0x886 + 1747 087f 14 .uleb128 0x14 + 1748 0880 01 .byte 0x1 + 1749 0881 50 .byte 0x50 + 1750 0882 02 .byte 0x2 + 1751 0883 74 .byte 0x74 + 1752 0884 1C .sleb128 28 + 1753 0885 00 .byte 0 + 1754 0886 16 .uleb128 0x16 + 1755 0887 34000000 .4byte .LVL45 + 1756 088b 98090000 .4byte 0x998 + 1757 088f 00 .byte 0 + 1758 0890 1C .uleb128 0x1c + 1759 0891 01 .byte 0x1 + 1760 0892 FF020000 .4byte .LASF75 + 1761 0896 01 .byte 0x1 + 1762 0897 3401 .2byte 0x134 + 1763 0899 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 32 + + + 1764 089a BC000000 .4byte 0xbc + 1765 089e 00000000 .4byte .LFB15 + 1766 08a2 0C000000 .4byte .LFE15 + 1767 08a6 D1040000 .4byte .LLST35 + 1768 08aa 01 .byte 0x1 + 1769 08ab 0D090000 .4byte 0x90d + 1770 08af 1D .uleb128 0x1d + 1771 08b0 6D627000 .ascii "mbp\000" + 1772 08b4 01 .byte 0x1 + 1773 08b5 3401 .2byte 0x134 + 1774 08b7 D9040000 .4byte 0x4d9 + 1775 08bb F1040000 .4byte .LLST36 + 1776 08bf 1E .uleb128 0x1e + 1777 08c0 87010000 .4byte .LASF74 + 1778 08c4 01 .byte 0x1 + 1779 08c5 3401 .2byte 0x134 + 1780 08c7 04040000 .4byte 0x404 + 1781 08cb 12050000 .4byte .LLST37 + 1782 08cf 1E .uleb128 0x1e + 1783 08d0 0A020000 .4byte .LASF66 + 1784 08d4 01 .byte 0x1 + 1785 08d5 3401 .2byte 0x134 + 1786 08d7 D2000000 .4byte 0xd2 + 1787 08db 33050000 .4byte .LLST38 + 1788 08df 20 .uleb128 0x20 + 1789 08e0 13000000 .4byte .LASF59 + 1790 08e4 01 .byte 0x1 + 1791 08e5 3501 .2byte 0x135 + 1792 08e7 BC000000 .4byte 0xbc + 1793 08eb 01 .byte 0x1 + 1794 08ec 50 .byte 0x50 + 1795 08ed 1B .uleb128 0x1b + 1796 08ee 08000000 .4byte .LVL47 + 1797 08f2 F8070000 .4byte 0x7f8 + 1798 08f6 14 .uleb128 0x14 + 1799 08f7 01 .byte 0x1 + 1800 08f8 52 .byte 0x52 + 1801 08f9 03 .byte 0x3 + 1802 08fa F3 .byte 0xf3 + 1803 08fb 01 .uleb128 0x1 + 1804 08fc 52 .byte 0x52 + 1805 08fd 14 .uleb128 0x14 + 1806 08fe 01 .byte 0x1 + 1807 08ff 51 .byte 0x51 + 1808 0900 03 .byte 0x3 + 1809 0901 F3 .byte 0xf3 + 1810 0902 01 .uleb128 0x1 + 1811 0903 51 .byte 0x51 + 1812 0904 14 .uleb128 0x14 + 1813 0905 01 .byte 0x1 + 1814 0906 50 .byte 0x50 + 1815 0907 03 .byte 0x3 + 1816 0908 F3 .byte 0xf3 + 1817 0909 01 .uleb128 0x1 + 1818 090a 50 .byte 0x50 + 1819 090b 00 .byte 0 + 1820 090c 00 .byte 0 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 33 + + + 1821 090d 1C .uleb128 0x1c + 1822 090e 01 .byte 0x1 + 1823 090f 45010000 .4byte .LASF76 + 1824 0913 01 .byte 0x1 + 1825 0914 6F01 .2byte 0x16f + 1826 0916 01 .byte 0x1 + 1827 0917 BC000000 .4byte 0xbc + 1828 091b 00000000 .4byte .LFB17 + 1829 091f 30000000 .4byte .LFE17 + 1830 0923 54050000 .4byte .LLST39 + 1831 0927 01 .byte 0x1 + 1832 0928 60090000 .4byte 0x960 + 1833 092c 1D .uleb128 0x1d + 1834 092d 6D627000 .ascii "mbp\000" + 1835 0931 01 .byte 0x1 + 1836 0932 6F01 .2byte 0x16f + 1837 0934 D9040000 .4byte 0x4d9 + 1838 0938 74050000 .4byte .LLST40 + 1839 093c 1E .uleb128 0x1e + 1840 093d 87010000 .4byte .LASF74 + 1841 0941 01 .byte 0x1 + 1842 0942 6F01 .2byte 0x16f + 1843 0944 04040000 .4byte 0x404 + 1844 0948 BB050000 .4byte .LLST41 + 1845 094c 1B .uleb128 0x1b + 1846 094d 26000000 .4byte .LVL50 + 1847 0951 BF090000 .4byte 0x9bf + 1848 0955 14 .uleb128 0x14 + 1849 0956 01 .byte 0x1 + 1850 0957 50 .byte 0x50 + 1851 0958 05 .byte 0x5 + 1852 0959 F3 .byte 0xf3 + 1853 095a 01 .uleb128 0x1 + 1854 095b 50 .byte 0x50 + 1855 095c 23 .byte 0x23 + 1856 095d 1C .uleb128 0x1c + 1857 095e 00 .byte 0 + 1858 095f 00 .byte 0 + 1859 0960 21 .uleb128 0x21 + 1860 0961 01 .byte 0x1 + 1861 0962 7F030000 .4byte .LASF77 + 1862 0966 07 .byte 0x7 + 1863 0967 35 .byte 0x35 + 1864 0968 01 .byte 0x1 + 1865 0969 01 .byte 0x1 + 1866 096a 79090000 .4byte 0x979 + 1867 096e 22 .uleb128 0x22 + 1868 096f 79090000 .4byte 0x979 + 1869 0973 22 .uleb128 0x22 + 1870 0974 DD000000 .4byte 0xdd + 1871 0978 00 .byte 0 + 1872 0979 09 .uleb128 0x9 + 1873 097a 04 .byte 0x4 + 1874 097b 54030000 .4byte 0x354 + 1875 097f 21 .uleb128 0x21 + 1876 0980 01 .byte 0x1 + 1877 0981 25030000 .4byte .LASF78 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 34 + + + 1878 0985 07 .byte 0x7 + 1879 0986 37 .byte 0x37 + 1880 0987 01 .byte 0x1 + 1881 0988 01 .byte 0x1 + 1882 0989 98090000 .4byte 0x998 + 1883 098d 22 .uleb128 0x22 + 1884 098e 79090000 .4byte 0x979 + 1885 0992 22 .uleb128 0x22 + 1886 0993 DD000000 .4byte 0xdd + 1887 0997 00 .byte 0 + 1888 0998 23 .uleb128 0x23 + 1889 0999 01 .byte 0x1 + 1890 099a D0000000 .4byte .LASF82 + 1891 099e 0A .byte 0xa + 1892 099f 9F .byte 0x9f + 1893 09a0 01 .byte 0x1 + 1894 09a1 01 .byte 0x1 + 1895 09a2 24 .uleb128 0x24 + 1896 09a3 01 .byte 0x1 + 1897 09a4 AA020000 .4byte .LASF83 + 1898 09a8 07 .byte 0x7 + 1899 09a9 3B .byte 0x3b + 1900 09aa 01 .byte 0x1 + 1901 09ab BC000000 .4byte 0xbc + 1902 09af 01 .byte 0x1 + 1903 09b0 BF090000 .4byte 0x9bf + 1904 09b4 22 .uleb128 0x22 + 1905 09b5 79090000 .4byte 0x979 + 1906 09b9 22 .uleb128 0x22 + 1907 09ba D2000000 .4byte 0xd2 + 1908 09be 00 .byte 0 + 1909 09bf 25 .uleb128 0x25 + 1910 09c0 01 .byte 0x1 + 1911 09c1 06000000 .4byte .LASF84 + 1912 09c5 07 .byte 0x7 + 1913 09c6 3D .byte 0x3d + 1914 09c7 01 .byte 0x1 + 1915 09c8 01 .byte 0x1 + 1916 09c9 22 .uleb128 0x22 + 1917 09ca 79090000 .4byte 0x979 + 1918 09ce 00 .byte 0 + 1919 09cf 00 .byte 0 + 1920 .section .debug_abbrev,"",%progbits + 1921 .Ldebug_abbrev0: + 1922 0000 01 .uleb128 0x1 + 1923 0001 11 .uleb128 0x11 + 1924 0002 01 .byte 0x1 + 1925 0003 25 .uleb128 0x25 + 1926 0004 0E .uleb128 0xe + 1927 0005 13 .uleb128 0x13 + 1928 0006 0B .uleb128 0xb + 1929 0007 03 .uleb128 0x3 + 1930 0008 0E .uleb128 0xe + 1931 0009 1B .uleb128 0x1b + 1932 000a 0E .uleb128 0xe + 1933 000b 55 .uleb128 0x55 + 1934 000c 06 .uleb128 0x6 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 35 + + + 1935 000d 11 .uleb128 0x11 + 1936 000e 01 .uleb128 0x1 + 1937 000f 52 .uleb128 0x52 + 1938 0010 01 .uleb128 0x1 + 1939 0011 10 .uleb128 0x10 + 1940 0012 06 .uleb128 0x6 + 1941 0013 00 .byte 0 + 1942 0014 00 .byte 0 + 1943 0015 02 .uleb128 0x2 + 1944 0016 24 .uleb128 0x24 + 1945 0017 00 .byte 0 + 1946 0018 0B .uleb128 0xb + 1947 0019 0B .uleb128 0xb + 1948 001a 3E .uleb128 0x3e + 1949 001b 0B .uleb128 0xb + 1950 001c 03 .uleb128 0x3 + 1951 001d 08 .uleb128 0x8 + 1952 001e 00 .byte 0 + 1953 001f 00 .byte 0 + 1954 0020 03 .uleb128 0x3 + 1955 0021 24 .uleb128 0x24 + 1956 0022 00 .byte 0 + 1957 0023 0B .uleb128 0xb + 1958 0024 0B .uleb128 0xb + 1959 0025 3E .uleb128 0x3e + 1960 0026 0B .uleb128 0xb + 1961 0027 03 .uleb128 0x3 + 1962 0028 0E .uleb128 0xe + 1963 0029 00 .byte 0 + 1964 002a 00 .byte 0 + 1965 002b 04 .uleb128 0x4 + 1966 002c 16 .uleb128 0x16 + 1967 002d 00 .byte 0 + 1968 002e 03 .uleb128 0x3 + 1969 002f 0E .uleb128 0xe + 1970 0030 3A .uleb128 0x3a + 1971 0031 0B .uleb128 0xb + 1972 0032 3B .uleb128 0x3b + 1973 0033 0B .uleb128 0xb + 1974 0034 49 .uleb128 0x49 + 1975 0035 13 .uleb128 0x13 + 1976 0036 00 .byte 0 + 1977 0037 00 .byte 0 + 1978 0038 05 .uleb128 0x5 + 1979 0039 13 .uleb128 0x13 + 1980 003a 01 .byte 0x1 + 1981 003b 03 .uleb128 0x3 + 1982 003c 0E .uleb128 0xe + 1983 003d 0B .uleb128 0xb + 1984 003e 0B .uleb128 0xb + 1985 003f 3A .uleb128 0x3a + 1986 0040 0B .uleb128 0xb + 1987 0041 3B .uleb128 0x3b + 1988 0042 0B .uleb128 0xb + 1989 0043 01 .uleb128 0x1 + 1990 0044 13 .uleb128 0x13 + 1991 0045 00 .byte 0 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 36 + + + 1992 0046 00 .byte 0 + 1993 0047 06 .uleb128 0x6 + 1994 0048 0D .uleb128 0xd + 1995 0049 00 .byte 0 + 1996 004a 03 .uleb128 0x3 + 1997 004b 0E .uleb128 0xe + 1998 004c 3A .uleb128 0x3a + 1999 004d 0B .uleb128 0xb + 2000 004e 3B .uleb128 0x3b + 2001 004f 0B .uleb128 0xb + 2002 0050 49 .uleb128 0x49 + 2003 0051 13 .uleb128 0x13 + 2004 0052 38 .uleb128 0x38 + 2005 0053 0A .uleb128 0xa + 2006 0054 00 .byte 0 + 2007 0055 00 .byte 0 + 2008 0056 07 .uleb128 0x7 + 2009 0057 0D .uleb128 0xd + 2010 0058 00 .byte 0 + 2011 0059 03 .uleb128 0x3 + 2012 005a 08 .uleb128 0x8 + 2013 005b 3A .uleb128 0x3a + 2014 005c 0B .uleb128 0xb + 2015 005d 3B .uleb128 0x3b + 2016 005e 0B .uleb128 0xb + 2017 005f 49 .uleb128 0x49 + 2018 0060 13 .uleb128 0x13 + 2019 0061 38 .uleb128 0x38 + 2020 0062 0A .uleb128 0xa + 2021 0063 00 .byte 0 + 2022 0064 00 .byte 0 + 2023 0065 08 .uleb128 0x8 + 2024 0066 13 .uleb128 0x13 + 2025 0067 01 .byte 0x1 + 2026 0068 0B .uleb128 0xb + 2027 0069 0B .uleb128 0xb + 2028 006a 3A .uleb128 0x3a + 2029 006b 0B .uleb128 0xb + 2030 006c 3B .uleb128 0x3b + 2031 006d 0B .uleb128 0xb + 2032 006e 01 .uleb128 0x1 + 2033 006f 13 .uleb128 0x13 + 2034 0070 00 .byte 0 + 2035 0071 00 .byte 0 + 2036 0072 09 .uleb128 0x9 + 2037 0073 0F .uleb128 0xf + 2038 0074 00 .byte 0 + 2039 0075 0B .uleb128 0xb + 2040 0076 0B .uleb128 0xb + 2041 0077 49 .uleb128 0x49 + 2042 0078 13 .uleb128 0x13 + 2043 0079 00 .byte 0 + 2044 007a 00 .byte 0 + 2045 007b 0A .uleb128 0xa + 2046 007c 0F .uleb128 0xf + 2047 007d 00 .byte 0 + 2048 007e 0B .uleb128 0xb + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 37 + + + 2049 007f 0B .uleb128 0xb + 2050 0080 00 .byte 0 + 2051 0081 00 .byte 0 + 2052 0082 0B .uleb128 0xb + 2053 0083 0D .uleb128 0xd + 2054 0084 00 .byte 0 + 2055 0085 03 .uleb128 0x3 + 2056 0086 08 .uleb128 0x8 + 2057 0087 3A .uleb128 0x3a + 2058 0088 0B .uleb128 0xb + 2059 0089 3B .uleb128 0x3b + 2060 008a 05 .uleb128 0x5 + 2061 008b 49 .uleb128 0x49 + 2062 008c 13 .uleb128 0x13 + 2063 008d 38 .uleb128 0x38 + 2064 008e 0A .uleb128 0xa + 2065 008f 00 .byte 0 + 2066 0090 00 .byte 0 + 2067 0091 0C .uleb128 0xc + 2068 0092 13 .uleb128 0x13 + 2069 0093 01 .byte 0x1 + 2070 0094 03 .uleb128 0x3 + 2071 0095 0E .uleb128 0xe + 2072 0096 0B .uleb128 0xb + 2073 0097 0B .uleb128 0xb + 2074 0098 3A .uleb128 0x3a + 2075 0099 0B .uleb128 0xb + 2076 009a 3B .uleb128 0x3b + 2077 009b 05 .uleb128 0x5 + 2078 009c 01 .uleb128 0x1 + 2079 009d 13 .uleb128 0x13 + 2080 009e 00 .byte 0 + 2081 009f 00 .byte 0 + 2082 00a0 0D .uleb128 0xd + 2083 00a1 35 .uleb128 0x35 + 2084 00a2 00 .byte 0 + 2085 00a3 49 .uleb128 0x49 + 2086 00a4 13 .uleb128 0x13 + 2087 00a5 00 .byte 0 + 2088 00a6 00 .byte 0 + 2089 00a7 0E .uleb128 0xe + 2090 00a8 17 .uleb128 0x17 + 2091 00a9 01 .byte 0x1 + 2092 00aa 0B .uleb128 0xb + 2093 00ab 0B .uleb128 0xb + 2094 00ac 3A .uleb128 0x3a + 2095 00ad 0B .uleb128 0xb + 2096 00ae 3B .uleb128 0x3b + 2097 00af 0B .uleb128 0xb + 2098 00b0 01 .uleb128 0x1 + 2099 00b1 13 .uleb128 0x13 + 2100 00b2 00 .byte 0 + 2101 00b3 00 .byte 0 + 2102 00b4 0F .uleb128 0xf + 2103 00b5 0D .uleb128 0xd + 2104 00b6 00 .byte 0 + 2105 00b7 03 .uleb128 0x3 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 38 + + + 2106 00b8 0E .uleb128 0xe + 2107 00b9 3A .uleb128 0x3a + 2108 00ba 0B .uleb128 0xb + 2109 00bb 3B .uleb128 0x3b + 2110 00bc 0B .uleb128 0xb + 2111 00bd 49 .uleb128 0x49 + 2112 00be 13 .uleb128 0x13 + 2113 00bf 00 .byte 0 + 2114 00c0 00 .byte 0 + 2115 00c1 10 .uleb128 0x10 + 2116 00c2 26 .uleb128 0x26 + 2117 00c3 00 .byte 0 + 2118 00c4 49 .uleb128 0x49 + 2119 00c5 13 .uleb128 0x13 + 2120 00c6 00 .byte 0 + 2121 00c7 00 .byte 0 + 2122 00c8 11 .uleb128 0x11 + 2123 00c9 2E .uleb128 0x2e + 2124 00ca 01 .byte 0x1 + 2125 00cb 3F .uleb128 0x3f + 2126 00cc 0C .uleb128 0xc + 2127 00cd 03 .uleb128 0x3 + 2128 00ce 0E .uleb128 0xe + 2129 00cf 3A .uleb128 0x3a + 2130 00d0 0B .uleb128 0xb + 2131 00d1 3B .uleb128 0x3b + 2132 00d2 0B .uleb128 0xb + 2133 00d3 27 .uleb128 0x27 + 2134 00d4 0C .uleb128 0xc + 2135 00d5 11 .uleb128 0x11 + 2136 00d6 01 .uleb128 0x1 + 2137 00d7 12 .uleb128 0x12 + 2138 00d8 01 .uleb128 0x1 + 2139 00d9 40 .uleb128 0x40 + 2140 00da 06 .uleb128 0x6 + 2141 00db 9742 .uleb128 0x2117 + 2142 00dd 0C .uleb128 0xc + 2143 00de 01 .uleb128 0x1 + 2144 00df 13 .uleb128 0x13 + 2145 00e0 00 .byte 0 + 2146 00e1 00 .byte 0 + 2147 00e2 12 .uleb128 0x12 + 2148 00e3 05 .uleb128 0x5 + 2149 00e4 00 .byte 0 + 2150 00e5 03 .uleb128 0x3 + 2151 00e6 08 .uleb128 0x8 + 2152 00e7 3A .uleb128 0x3a + 2153 00e8 0B .uleb128 0xb + 2154 00e9 3B .uleb128 0x3b + 2155 00ea 0B .uleb128 0xb + 2156 00eb 49 .uleb128 0x49 + 2157 00ec 13 .uleb128 0x13 + 2158 00ed 02 .uleb128 0x2 + 2159 00ee 06 .uleb128 0x6 + 2160 00ef 00 .byte 0 + 2161 00f0 00 .byte 0 + 2162 00f1 13 .uleb128 0x13 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 39 + + + 2163 00f2 898201 .uleb128 0x4109 + 2164 00f5 01 .byte 0x1 + 2165 00f6 11 .uleb128 0x11 + 2166 00f7 01 .uleb128 0x1 + 2167 00f8 31 .uleb128 0x31 + 2168 00f9 13 .uleb128 0x13 + 2169 00fa 01 .uleb128 0x1 + 2170 00fb 13 .uleb128 0x13 + 2171 00fc 00 .byte 0 + 2172 00fd 00 .byte 0 + 2173 00fe 14 .uleb128 0x14 + 2174 00ff 8A8201 .uleb128 0x410a + 2175 0102 00 .byte 0 + 2176 0103 02 .uleb128 0x2 + 2177 0104 0A .uleb128 0xa + 2178 0105 9142 .uleb128 0x2111 + 2179 0107 0A .uleb128 0xa + 2180 0108 00 .byte 0 + 2181 0109 00 .byte 0 + 2182 010a 15 .uleb128 0x15 + 2183 010b 898201 .uleb128 0x4109 + 2184 010e 01 .byte 0x1 + 2185 010f 11 .uleb128 0x11 + 2186 0110 01 .uleb128 0x1 + 2187 0111 9542 .uleb128 0x2115 + 2188 0113 0C .uleb128 0xc + 2189 0114 31 .uleb128 0x31 + 2190 0115 13 .uleb128 0x13 + 2191 0116 00 .byte 0 + 2192 0117 00 .byte 0 + 2193 0118 16 .uleb128 0x16 + 2194 0119 898201 .uleb128 0x4109 + 2195 011c 00 .byte 0 + 2196 011d 11 .uleb128 0x11 + 2197 011e 01 .uleb128 0x1 + 2198 011f 31 .uleb128 0x31 + 2199 0120 13 .uleb128 0x13 + 2200 0121 00 .byte 0 + 2201 0122 00 .byte 0 + 2202 0123 17 .uleb128 0x17 + 2203 0124 2E .uleb128 0x2e + 2204 0125 01 .byte 0x1 + 2205 0126 3F .uleb128 0x3f + 2206 0127 0C .uleb128 0xc + 2207 0128 03 .uleb128 0x3 + 2208 0129 0E .uleb128 0xe + 2209 012a 3A .uleb128 0x3a + 2210 012b 0B .uleb128 0xb + 2211 012c 3B .uleb128 0x3b + 2212 012d 0B .uleb128 0xb + 2213 012e 27 .uleb128 0x27 + 2214 012f 0C .uleb128 0xc + 2215 0130 49 .uleb128 0x49 + 2216 0131 13 .uleb128 0x13 + 2217 0132 11 .uleb128 0x11 + 2218 0133 01 .uleb128 0x1 + 2219 0134 12 .uleb128 0x12 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 40 + + + 2220 0135 01 .uleb128 0x1 + 2221 0136 40 .uleb128 0x40 + 2222 0137 06 .uleb128 0x6 + 2223 0138 9742 .uleb128 0x2117 + 2224 013a 0C .uleb128 0xc + 2225 013b 01 .uleb128 0x1 + 2226 013c 13 .uleb128 0x13 + 2227 013d 00 .byte 0 + 2228 013e 00 .byte 0 + 2229 013f 18 .uleb128 0x18 + 2230 0140 05 .uleb128 0x5 + 2231 0141 00 .byte 0 + 2232 0142 03 .uleb128 0x3 + 2233 0143 0E .uleb128 0xe + 2234 0144 3A .uleb128 0x3a + 2235 0145 0B .uleb128 0xb + 2236 0146 3B .uleb128 0x3b + 2237 0147 0B .uleb128 0xb + 2238 0148 49 .uleb128 0x49 + 2239 0149 13 .uleb128 0x13 + 2240 014a 02 .uleb128 0x2 + 2241 014b 06 .uleb128 0x6 + 2242 014c 00 .byte 0 + 2243 014d 00 .byte 0 + 2244 014e 19 .uleb128 0x19 + 2245 014f 34 .uleb128 0x34 + 2246 0150 00 .byte 0 + 2247 0151 03 .uleb128 0x3 + 2248 0152 0E .uleb128 0xe + 2249 0153 3A .uleb128 0x3a + 2250 0154 0B .uleb128 0xb + 2251 0155 3B .uleb128 0x3b + 2252 0156 0B .uleb128 0xb + 2253 0157 49 .uleb128 0x49 + 2254 0158 13 .uleb128 0x13 + 2255 0159 02 .uleb128 0x2 + 2256 015a 06 .uleb128 0x6 + 2257 015b 00 .byte 0 + 2258 015c 00 .byte 0 + 2259 015d 1A .uleb128 0x1a + 2260 015e 34 .uleb128 0x34 + 2261 015f 00 .byte 0 + 2262 0160 03 .uleb128 0x3 + 2263 0161 0E .uleb128 0xe + 2264 0162 3A .uleb128 0x3a + 2265 0163 0B .uleb128 0xb + 2266 0164 3B .uleb128 0x3b + 2267 0165 0B .uleb128 0xb + 2268 0166 49 .uleb128 0x49 + 2269 0167 13 .uleb128 0x13 + 2270 0168 02 .uleb128 0x2 + 2271 0169 0A .uleb128 0xa + 2272 016a 00 .byte 0 + 2273 016b 00 .byte 0 + 2274 016c 1B .uleb128 0x1b + 2275 016d 898201 .uleb128 0x4109 + 2276 0170 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 41 + + + 2277 0171 11 .uleb128 0x11 + 2278 0172 01 .uleb128 0x1 + 2279 0173 31 .uleb128 0x31 + 2280 0174 13 .uleb128 0x13 + 2281 0175 00 .byte 0 + 2282 0176 00 .byte 0 + 2283 0177 1C .uleb128 0x1c + 2284 0178 2E .uleb128 0x2e + 2285 0179 01 .byte 0x1 + 2286 017a 3F .uleb128 0x3f + 2287 017b 0C .uleb128 0xc + 2288 017c 03 .uleb128 0x3 + 2289 017d 0E .uleb128 0xe + 2290 017e 3A .uleb128 0x3a + 2291 017f 0B .uleb128 0xb + 2292 0180 3B .uleb128 0x3b + 2293 0181 05 .uleb128 0x5 + 2294 0182 27 .uleb128 0x27 + 2295 0183 0C .uleb128 0xc + 2296 0184 49 .uleb128 0x49 + 2297 0185 13 .uleb128 0x13 + 2298 0186 11 .uleb128 0x11 + 2299 0187 01 .uleb128 0x1 + 2300 0188 12 .uleb128 0x12 + 2301 0189 01 .uleb128 0x1 + 2302 018a 40 .uleb128 0x40 + 2303 018b 06 .uleb128 0x6 + 2304 018c 9742 .uleb128 0x2117 + 2305 018e 0C .uleb128 0xc + 2306 018f 01 .uleb128 0x1 + 2307 0190 13 .uleb128 0x13 + 2308 0191 00 .byte 0 + 2309 0192 00 .byte 0 + 2310 0193 1D .uleb128 0x1d + 2311 0194 05 .uleb128 0x5 + 2312 0195 00 .byte 0 + 2313 0196 03 .uleb128 0x3 + 2314 0197 08 .uleb128 0x8 + 2315 0198 3A .uleb128 0x3a + 2316 0199 0B .uleb128 0xb + 2317 019a 3B .uleb128 0x3b + 2318 019b 05 .uleb128 0x5 + 2319 019c 49 .uleb128 0x49 + 2320 019d 13 .uleb128 0x13 + 2321 019e 02 .uleb128 0x2 + 2322 019f 06 .uleb128 0x6 + 2323 01a0 00 .byte 0 + 2324 01a1 00 .byte 0 + 2325 01a2 1E .uleb128 0x1e + 2326 01a3 05 .uleb128 0x5 + 2327 01a4 00 .byte 0 + 2328 01a5 03 .uleb128 0x3 + 2329 01a6 0E .uleb128 0xe + 2330 01a7 3A .uleb128 0x3a + 2331 01a8 0B .uleb128 0xb + 2332 01a9 3B .uleb128 0x3b + 2333 01aa 05 .uleb128 0x5 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 42 + + + 2334 01ab 49 .uleb128 0x49 + 2335 01ac 13 .uleb128 0x13 + 2336 01ad 02 .uleb128 0x2 + 2337 01ae 06 .uleb128 0x6 + 2338 01af 00 .byte 0 + 2339 01b0 00 .byte 0 + 2340 01b1 1F .uleb128 0x1f + 2341 01b2 34 .uleb128 0x34 + 2342 01b3 00 .byte 0 + 2343 01b4 03 .uleb128 0x3 + 2344 01b5 0E .uleb128 0xe + 2345 01b6 3A .uleb128 0x3a + 2346 01b7 0B .uleb128 0xb + 2347 01b8 3B .uleb128 0x3b + 2348 01b9 05 .uleb128 0x5 + 2349 01ba 49 .uleb128 0x49 + 2350 01bb 13 .uleb128 0x13 + 2351 01bc 02 .uleb128 0x2 + 2352 01bd 06 .uleb128 0x6 + 2353 01be 00 .byte 0 + 2354 01bf 00 .byte 0 + 2355 01c0 20 .uleb128 0x20 + 2356 01c1 34 .uleb128 0x34 + 2357 01c2 00 .byte 0 + 2358 01c3 03 .uleb128 0x3 + 2359 01c4 0E .uleb128 0xe + 2360 01c5 3A .uleb128 0x3a + 2361 01c6 0B .uleb128 0xb + 2362 01c7 3B .uleb128 0x3b + 2363 01c8 05 .uleb128 0x5 + 2364 01c9 49 .uleb128 0x49 + 2365 01ca 13 .uleb128 0x13 + 2366 01cb 02 .uleb128 0x2 + 2367 01cc 0A .uleb128 0xa + 2368 01cd 00 .byte 0 + 2369 01ce 00 .byte 0 + 2370 01cf 21 .uleb128 0x21 + 2371 01d0 2E .uleb128 0x2e + 2372 01d1 01 .byte 0x1 + 2373 01d2 3F .uleb128 0x3f + 2374 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0xc + 2409 01f6 3C .uleb128 0x3c + 2410 01f7 0C .uleb128 0xc + 2411 01f8 00 .byte 0 + 2412 01f9 00 .byte 0 + 2413 01fa 24 .uleb128 0x24 + 2414 01fb 2E .uleb128 0x2e + 2415 01fc 01 .byte 0x1 + 2416 01fd 3F .uleb128 0x3f + 2417 01fe 0C .uleb128 0xc + 2418 01ff 03 .uleb128 0x3 + 2419 0200 0E .uleb128 0xe + 2420 0201 3A .uleb128 0x3a + 2421 0202 0B .uleb128 0xb + 2422 0203 3B .uleb128 0x3b + 2423 0204 0B .uleb128 0xb + 2424 0205 27 .uleb128 0x27 + 2425 0206 0C .uleb128 0xc + 2426 0207 49 .uleb128 0x49 + 2427 0208 13 .uleb128 0x13 + 2428 0209 3C .uleb128 0x3c + 2429 020a 0C .uleb128 0xc + 2430 020b 01 .uleb128 0x1 + 2431 020c 13 .uleb128 0x13 + 2432 020d 00 .byte 0 + 2433 020e 00 .byte 0 + 2434 020f 25 .uleb128 0x25 + 2435 0210 2E .uleb128 0x2e + 2436 0211 01 .byte 0x1 + 2437 0212 3F .uleb128 0x3f + 2438 0213 0C .uleb128 0xc + 2439 0214 03 .uleb128 0x3 + 2440 0215 0E .uleb128 0xe + 2441 0216 3A .uleb128 0x3a + 2442 0217 0B .uleb128 0xb + 2443 0218 3B .uleb128 0x3b + 2444 0219 0B .uleb128 0xb + 2445 021a 27 .uleb128 0x27 + 2446 021b 0C .uleb128 0xc + 2447 021c 3C .uleb128 0x3c + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 44 + + + 2448 021d 0C .uleb128 0xc + 2449 021e 00 .byte 0 + 2450 021f 00 .byte 0 + 2451 0220 00 .byte 0 + 2452 .section .debug_loc,"",%progbits + 2453 .Ldebug_loc0: + 2454 .LLST0: + 2455 0000 00000000 .4byte .LFB7 + 2456 0004 02000000 .4byte .LCFI0 + 2457 0008 0200 .2byte 0x2 + 2458 000a 7D .byte 0x7d + 2459 000b 00 .sleb128 0 + 2460 000c 02000000 .4byte .LCFI0 + 2461 0010 2A000000 .4byte .LFE7 + 2462 0014 0200 .2byte 0x2 + 2463 0016 7D .byte 0x7d + 2464 0017 10 .sleb128 16 + 2465 0018 00000000 .4byte 0 + 2466 001c 00000000 .4byte 0 + 2467 .LLST1: + 2468 0020 00000000 .4byte .LVL0 + 2469 0024 0E000000 .4byte .LVL1 + 2470 0028 0100 .2byte 0x1 + 2471 002a 50 .byte 0x50 + 2472 002b 0E000000 .4byte .LVL1 + 2473 002f 2A000000 .4byte .LFE7 + 2474 0033 0100 .2byte 0x1 + 2475 0035 54 .byte 0x54 + 2476 0036 00000000 .4byte 0 + 2477 003a 00000000 .4byte 0 + 2478 .LLST2: + 2479 003e 00000000 .4byte .LVL0 + 2480 0042 10000000 .4byte .LVL2 + 2481 0046 0100 .2byte 0x1 + 2482 0048 51 .byte 0x51 + 2483 0049 10000000 .4byte .LVL2 + 2484 004d 1B000000 .4byte .LVL3-1 + 2485 0051 0100 .2byte 0x1 + 2486 0053 53 .byte 0x53 + 2487 0054 1B000000 .4byte .LVL3-1 + 2488 0058 2A000000 .4byte .LFE7 + 2489 005c 0400 .2byte 0x4 + 2490 005e F3 .byte 0xf3 + 2491 005f 01 .uleb128 0x1 + 2492 0060 51 .byte 0x51 + 2493 0061 9F .byte 0x9f + 2494 0062 00000000 .4byte 0 + 2495 0066 00000000 .4byte 0 + 2496 .LLST3: + 2497 006a 00000000 .4byte .LVL0 + 2498 006e 1B000000 .4byte .LVL3-1 + 2499 0072 0100 .2byte 0x1 + 2500 0074 52 .byte 0x52 + 2501 0075 1B000000 .4byte .LVL3-1 + 2502 0079 2A000000 .4byte .LFE7 + 2503 007d 0400 .2byte 0x4 + 2504 007f F3 .byte 0xf3 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 45 + + + 2505 0080 01 .uleb128 0x1 + 2506 0081 52 .byte 0x52 + 2507 0082 9F .byte 0x9f + 2508 0083 00000000 .4byte 0 + 2509 0087 00000000 .4byte 0 + 2510 .LLST4: + 2511 008b 00000000 .4byte .LFB8 + 2512 008f 02000000 .4byte .LCFI1 + 2513 0093 0200 .2byte 0x2 + 2514 0095 7D .byte 0x7d + 2515 0096 00 .sleb128 0 + 2516 0097 02000000 .4byte .LCFI1 + 2517 009b 2C000000 .4byte .LFE8 + 2518 009f 0200 .2byte 0x2 + 2519 00a1 7D .byte 0x7d + 2520 00a2 08 .sleb128 8 + 2521 00a3 00000000 .4byte 0 + 2522 00a7 00000000 .4byte 0 + 2523 .LLST5: + 2524 00ab 00000000 .4byte .LVL5 + 2525 00af 16000000 .4byte .LVL6 + 2526 00b3 0100 .2byte 0x1 + 2527 00b5 50 .byte 0x50 + 2528 00b6 16000000 .4byte .LVL6 + 2529 00ba 2C000000 .4byte .LFE8 + 2530 00be 0100 .2byte 0x1 + 2531 00c0 54 .byte 0x54 + 2532 00c1 00000000 .4byte 0 + 2533 00c5 00000000 .4byte 0 + 2534 .LLST6: + 2535 00c9 00000000 .4byte .LFB10 + 2536 00cd 02000000 .4byte .LCFI2 + 2537 00d1 0200 .2byte 0x2 + 2538 00d3 7D .byte 0x7d + 2539 00d4 00 .sleb128 0 + 2540 00d5 02000000 .4byte .LCFI2 + 2541 00d9 38000000 .4byte .LFE10 + 2542 00dd 0200 .2byte 0x2 + 2543 00df 7D .byte 0x7d + 2544 00e0 10 .sleb128 16 + 2545 00e1 00000000 .4byte 0 + 2546 00e5 00000000 .4byte 0 + 2547 .LLST7: + 2548 00e9 00000000 .4byte .LVL10 + 2549 00ed 0A000000 .4byte .LVL11 + 2550 00f1 0100 .2byte 0x1 + 2551 00f3 50 .byte 0x50 + 2552 00f4 0A000000 .4byte .LVL11 + 2553 00f8 38000000 .4byte .LFE10 + 2554 00fc 0100 .2byte 0x1 + 2555 00fe 54 .byte 0x54 + 2556 00ff 00000000 .4byte 0 + 2557 0103 00000000 .4byte 0 + 2558 .LLST8: + 2559 0107 00000000 .4byte .LVL10 + 2560 010b 0C000000 .4byte .LVL12 + 2561 010f 0100 .2byte 0x1 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 46 + + + 2562 0111 51 .byte 0x51 + 2563 0112 0C000000 .4byte .LVL12 + 2564 0116 38000000 .4byte .LFE10 + 2565 011a 0100 .2byte 0x1 + 2566 011c 56 .byte 0x56 + 2567 011d 00000000 .4byte 0 + 2568 0121 00000000 .4byte 0 + 2569 .LLST9: + 2570 0125 00000000 .4byte .LVL10 + 2571 0129 0F000000 .4byte .LVL13-1 + 2572 012d 0100 .2byte 0x1 + 2573 012f 52 .byte 0x52 + 2574 0130 0F000000 .4byte .LVL13-1 + 2575 0134 38000000 .4byte .LFE10 + 2576 0138 0400 .2byte 0x4 + 2577 013a F3 .byte 0xf3 + 2578 013b 01 .uleb128 0x1 + 2579 013c 52 .byte 0x52 + 2580 013d 9F .byte 0x9f + 2581 013e 00000000 .4byte 0 + 2582 0142 00000000 .4byte 0 + 2583 .LLST10: + 2584 0146 10000000 .4byte .LVL13 + 2585 014a 28000000 .4byte .LVL14 + 2586 014e 0100 .2byte 0x1 + 2587 0150 50 .byte 0x50 + 2588 0151 28000000 .4byte .LVL14 + 2589 0155 38000000 .4byte .LFE10 + 2590 0159 0100 .2byte 0x1 + 2591 015b 55 .byte 0x55 + 2592 015c 00000000 .4byte 0 + 2593 0160 00000000 .4byte 0 + 2594 .LLST11: + 2595 0164 00000000 .4byte .LFB9 + 2596 0168 02000000 .4byte .LCFI3 + 2597 016c 0200 .2byte 0x2 + 2598 016e 7D .byte 0x7d + 2599 016f 00 .sleb128 0 + 2600 0170 02000000 .4byte .LCFI3 + 2601 0174 0C000000 .4byte .LFE9 + 2602 0178 0200 .2byte 0x2 + 2603 017a 7D .byte 0x7d + 2604 017b 08 .sleb128 8 + 2605 017c 00000000 .4byte 0 + 2606 0180 00000000 .4byte 0 + 2607 .LLST12: + 2608 0184 00000000 .4byte .LVL17 + 2609 0188 07000000 .4byte .LVL18-1 + 2610 018c 0100 .2byte 0x1 + 2611 018e 50 .byte 0x50 + 2612 018f 07000000 .4byte .LVL18-1 + 2613 0193 0C000000 .4byte .LFE9 + 2614 0197 0400 .2byte 0x4 + 2615 0199 F3 .byte 0xf3 + 2616 019a 01 .uleb128 0x1 + 2617 019b 50 .byte 0x50 + 2618 019c 9F .byte 0x9f + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 47 + + + 2619 019d 00000000 .4byte 0 + 2620 01a1 00000000 .4byte 0 + 2621 .LLST13: + 2622 01a5 00000000 .4byte .LVL17 + 2623 01a9 07000000 .4byte .LVL18-1 + 2624 01ad 0100 .2byte 0x1 + 2625 01af 51 .byte 0x51 + 2626 01b0 07000000 .4byte .LVL18-1 + 2627 01b4 0C000000 .4byte .LFE9 + 2628 01b8 0400 .2byte 0x4 + 2629 01ba F3 .byte 0xf3 + 2630 01bb 01 .uleb128 0x1 + 2631 01bc 51 .byte 0x51 + 2632 01bd 9F .byte 0x9f + 2633 01be 00000000 .4byte 0 + 2634 01c2 00000000 .4byte 0 + 2635 .LLST14: + 2636 01c6 00000000 .4byte .LVL17 + 2637 01ca 07000000 .4byte .LVL18-1 + 2638 01ce 0100 .2byte 0x1 + 2639 01d0 52 .byte 0x52 + 2640 01d1 07000000 .4byte .LVL18-1 + 2641 01d5 0C000000 .4byte .LFE9 + 2642 01d9 0400 .2byte 0x4 + 2643 01db F3 .byte 0xf3 + 2644 01dc 01 .uleb128 0x1 + 2645 01dd 52 .byte 0x52 + 2646 01de 9F .byte 0x9f + 2647 01df 00000000 .4byte 0 + 2648 01e3 00000000 .4byte 0 + 2649 .LLST15: + 2650 01e7 00000000 .4byte .LFB11 + 2651 01eb 04000000 .4byte .LCFI4 + 2652 01ef 0200 .2byte 0x2 + 2653 01f1 7D .byte 0x7d + 2654 01f2 00 .sleb128 0 + 2655 01f3 04000000 .4byte .LCFI4 + 2656 01f7 2E000000 .4byte .LFE11 + 2657 01fb 0200 .2byte 0x2 + 2658 01fd 7D .byte 0x7d + 2659 01fe 08 .sleb128 8 + 2660 01ff 00000000 .4byte 0 + 2661 0203 00000000 .4byte 0 + 2662 .LLST16: + 2663 0207 00000000 .4byte .LVL19 + 2664 020b 20000000 .4byte .LVL20 + 2665 020f 0100 .2byte 0x1 + 2666 0211 50 .byte 0x50 + 2667 0212 20000000 .4byte .LVL20 + 2668 0216 23000000 .4byte .LVL21-1 + 2669 021a 0300 .2byte 0x3 + 2670 021c 70 .byte 0x70 + 2671 021d 70 .sleb128 -16 + 2672 021e 9F .byte 0x9f + 2673 021f 23000000 .4byte .LVL21-1 + 2674 0223 28000000 .4byte .LVL22 + 2675 0227 0400 .2byte 0x4 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 48 + + + 2676 0229 F3 .byte 0xf3 + 2677 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.LLST18: + 2712 027a 00000000 .4byte .LFB13 + 2713 027e 02000000 .4byte .LCFI5 + 2714 0282 0200 .2byte 0x2 + 2715 0284 7D .byte 0x7d + 2716 0285 00 .sleb128 0 + 2717 0286 02000000 .4byte .LCFI5 + 2718 028a 3A000000 .4byte .LFE13 + 2719 028e 0200 .2byte 0x2 + 2720 0290 7D .byte 0x7d + 2721 0291 10 .sleb128 16 + 2722 0292 00000000 .4byte 0 + 2723 0296 00000000 .4byte 0 + 2724 .LLST19: + 2725 029a 00000000 .4byte .LVL24 + 2726 029e 0A000000 .4byte .LVL25 + 2727 02a2 0100 .2byte 0x1 + 2728 02a4 50 .byte 0x50 + 2729 02a5 0A000000 .4byte .LVL25 + 2730 02a9 3A000000 .4byte .LFE13 + 2731 02ad 0100 .2byte 0x1 + 2732 02af 54 .byte 0x54 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 49 + + + 2733 02b0 00000000 .4byte 0 + 2734 02b4 00000000 .4byte 0 + 2735 .LLST20: + 2736 02b8 00000000 .4byte .LVL24 + 2737 02bc 0C000000 .4byte .LVL26 + 2738 02c0 0100 .2byte 0x1 + 2739 02c2 51 .byte 0x51 + 2740 02c3 0C000000 .4byte .LVL26 + 2741 02c7 3A000000 .4byte .LFE13 + 2742 02cb 0100 .2byte 0x1 + 2743 02cd 56 .byte 0x56 + 2744 02ce 00000000 .4byte 0 + 2745 02d2 00000000 .4byte 0 + 2746 .LLST21: + 2747 02d6 00000000 .4byte .LVL24 + 2748 02da 0F000000 .4byte .LVL27-1 + 2749 02de 0100 .2byte 0x1 + 2750 02e0 52 .byte 0x52 + 2751 02e1 0F000000 .4byte .LVL27-1 + 2752 02e5 3A000000 .4byte .LFE13 + 2753 02e9 0400 .2byte 0x4 + 2754 02eb F3 .byte 0xf3 + 2755 02ec 01 .uleb128 0x1 + 2756 02ed 52 .byte 0x52 + 2757 02ee 9F .byte 0x9f + 2758 02ef 00000000 .4byte 0 + 2759 02f3 00000000 .4byte 0 + 2760 .LLST22: + 2761 02f7 10000000 .4byte .LVL27 + 2762 02fb 24000000 .4byte .LVL28 + 2763 02ff 0100 .2byte 0x1 + 2764 0301 50 .byte 0x50 + 2765 0302 24000000 .4byte .LVL28 + 2766 0306 32000000 .4byte .LVL31 + 2767 030a 0100 .2byte 0x1 + 2768 030c 55 .byte 0x55 + 2769 030d 32000000 .4byte .LVL31 + 2770 0311 3A000000 .4byte .LFE13 + 2771 0315 0100 .2byte 0x1 + 2772 0317 50 .byte 0x50 + 2773 0318 00000000 .4byte 0 + 2774 031c 00000000 .4byte 0 + 2775 .LLST23: + 2776 0320 00000000 .4byte .LFB12 + 2777 0324 02000000 .4byte .LCFI6 + 2778 0328 0200 .2byte 0x2 + 2779 032a 7D .byte 0x7d + 2780 032b 00 .sleb128 0 + 2781 032c 02000000 .4byte .LCFI6 + 2782 0330 0C000000 .4byte .LFE12 + 2783 0334 0200 .2byte 0x2 + 2784 0336 7D .byte 0x7d + 2785 0337 08 .sleb128 8 + 2786 0338 00000000 .4byte 0 + 2787 033c 00000000 .4byte 0 + 2788 .LLST24: + 2789 0340 00000000 .4byte .LVL32 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 50 + + + 2790 0344 07000000 .4byte .LVL33-1 + 2791 0348 0100 .2byte 0x1 + 2792 034a 50 .byte 0x50 + 2793 034b 07000000 .4byte .LVL33-1 + 2794 034f 0C000000 .4byte .LFE12 + 2795 0353 0400 .2byte 0x4 + 2796 0355 F3 .byte 0xf3 + 2797 0356 01 .uleb128 0x1 + 2798 0357 50 .byte 0x50 + 2799 0358 9F .byte 0x9f + 2800 0359 00000000 .4byte 0 + 2801 035d 00000000 .4byte 0 + 2802 .LLST25: + 2803 0361 00000000 .4byte .LVL32 + 2804 0365 07000000 .4byte .LVL33-1 + 2805 0369 0100 .2byte 0x1 + 2806 036b 51 .byte 0x51 + 2807 036c 07000000 .4byte .LVL33-1 + 2808 0370 0C000000 .4byte .LFE12 + 2809 0374 0400 .2byte 0x4 + 2810 0376 F3 .byte 0xf3 + 2811 0377 01 .uleb128 0x1 + 2812 0378 51 .byte 0x51 + 2813 0379 9F .byte 0x9f + 2814 037a 00000000 .4byte 0 + 2815 037e 00000000 .4byte 0 + 2816 .LLST26: + 2817 0382 00000000 .4byte .LVL32 + 2818 0386 07000000 .4byte .LVL33-1 + 2819 038a 0100 .2byte 0x1 + 2820 038c 52 .byte 0x52 + 2821 038d 07000000 .4byte .LVL33-1 + 2822 0391 0C000000 .4byte .LFE12 + 2823 0395 0400 .2byte 0x4 + 2824 0397 F3 .byte 0xf3 + 2825 0398 01 .uleb128 0x1 + 2826 0399 52 .byte 0x52 + 2827 039a 9F .byte 0x9f + 2828 039b 00000000 .4byte 0 + 2829 039f 00000000 .4byte 0 + 2830 .LLST27: + 2831 03a3 00000000 .4byte .LFB14 + 2832 03a7 04000000 .4byte .LCFI7 + 2833 03ab 0200 .2byte 0x2 + 2834 03ad 7D .byte 0x7d + 2835 03ae 00 .sleb128 0 + 2836 03af 04000000 .4byte .LCFI7 + 2837 03b3 30000000 .4byte .LFE14 + 2838 03b7 0200 .2byte 0x2 + 2839 03b9 7D .byte 0x7d + 2840 03ba 08 .sleb128 8 + 2841 03bb 00000000 .4byte 0 + 2842 03bf 00000000 .4byte 0 + 2843 .LLST28: + 2844 03c3 00000000 .4byte .LVL34 + 2845 03c7 20000000 .4byte .LVL35 + 2846 03cb 0100 .2byte 0x1 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 51 + + + 2847 03cd 50 .byte 0x50 + 2848 03ce 20000000 .4byte .LVL35 + 2849 03d2 25000000 .4byte .LVL36-1 + 2850 03d6 0300 .2byte 0x3 + 2851 03d8 70 .byte 0x70 + 2852 03d9 70 .sleb128 -16 + 2853 03da 9F .byte 0x9f + 2854 03db 25000000 .4byte .LVL36-1 + 2855 03df 2A000000 .4byte .LVL37 + 2856 03e3 0400 .2byte 0x4 + 2857 03e5 F3 .byte 0xf3 + 2858 03e6 01 .uleb128 0x1 + 2859 03e7 50 .byte 0x50 + 2860 03e8 9F .byte 0x9f + 2861 03e9 2A000000 .4byte .LVL37 + 2862 03ed 2E000000 .4byte .LVL38 + 2863 03f1 0100 .2byte 0x1 + 2864 03f3 50 .byte 0x50 + 2865 03f4 2E000000 .4byte .LVL38 + 2866 03f8 30000000 .4byte .LFE14 + 2867 03fc 0400 .2byte 0x4 + 2868 03fe F3 .byte 0xf3 + 2869 03ff 01 .uleb128 0x1 + 2870 0400 50 .byte 0x50 + 2871 0401 9F .byte 0x9f + 2872 0402 00000000 .4byte 0 + 2873 0406 00000000 .4byte 0 + 2874 .LLST29: + 2875 040a 00000000 .4byte .LVL34 + 2876 040e 25000000 .4byte .LVL36-1 + 2877 0412 0100 .2byte 0x1 + 2878 0414 51 .byte 0x51 + 2879 0415 25000000 .4byte .LVL36-1 + 2880 0419 2A000000 .4byte .LVL37 + 2881 041d 0400 .2byte 0x4 + 2882 041f F3 .byte 0xf3 + 2883 0420 01 .uleb128 0x1 + 2884 0421 51 .byte 0x51 + 2885 0422 9F .byte 0x9f + 2886 0423 2A000000 .4byte .LVL37 + 2887 0427 30000000 .4byte .LFE14 + 2888 042b 0100 .2byte 0x1 + 2889 042d 51 .byte 0x51 + 2890 042e 00000000 .4byte 0 + 2891 0432 00000000 .4byte 0 + 2892 .LLST30: + 2893 0436 00000000 .4byte .LFB16 + 2894 043a 02000000 .4byte .LCFI8 + 2895 043e 0200 .2byte 0x2 + 2896 0440 7D .byte 0x7d + 2897 0441 00 .sleb128 0 + 2898 0442 02000000 .4byte .LCFI8 + 2899 0446 38000000 .4byte .LFE16 + 2900 044a 0200 .2byte 0x2 + 2901 044c 7D .byte 0x7d + 2902 044d 10 .sleb128 16 + 2903 044e 00000000 .4byte 0 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 52 + + + 2904 0452 00000000 .4byte 0 + 2905 .LLST31: + 2906 0456 00000000 .4byte .LVL39 + 2907 045a 0A000000 .4byte .LVL40 + 2908 045e 0100 .2byte 0x1 + 2909 0460 50 .byte 0x50 + 2910 0461 0A000000 .4byte .LVL40 + 2911 0465 38000000 .4byte .LFE16 + 2912 0469 0100 .2byte 0x1 + 2913 046b 54 .byte 0x54 + 2914 046c 00000000 .4byte 0 + 2915 0470 00000000 .4byte 0 + 2916 .LLST32: + 2917 0474 00000000 .4byte .LVL39 + 2918 0478 0C000000 .4byte .LVL41 + 2919 047c 0100 .2byte 0x1 + 2920 047e 51 .byte 0x51 + 2921 047f 0C000000 .4byte .LVL41 + 2922 0483 38000000 .4byte .LFE16 + 2923 0487 0100 .2byte 0x1 + 2924 0489 56 .byte 0x56 + 2925 048a 00000000 .4byte 0 + 2926 048e 00000000 .4byte 0 + 2927 .LLST33: + 2928 0492 00000000 .4byte .LVL39 + 2929 0496 0F000000 .4byte .LVL42-1 + 2930 049a 0100 .2byte 0x1 + 2931 049c 52 .byte 0x52 + 2932 049d 0F000000 .4byte .LVL42-1 + 2933 04a1 38000000 .4byte .LFE16 + 2934 04a5 0400 .2byte 0x4 + 2935 04a7 F3 .byte 0xf3 + 2936 04a8 01 .uleb128 0x1 + 2937 04a9 52 .byte 0x52 + 2938 04aa 9F .byte 0x9f + 2939 04ab 00000000 .4byte 0 + 2940 04af 00000000 .4byte 0 + 2941 .LLST34: + 2942 04b3 10000000 .4byte .LVL42 + 2943 04b7 20000000 .4byte .LVL43 + 2944 04bb 0100 .2byte 0x1 + 2945 04bd 50 .byte 0x50 + 2946 04be 20000000 .4byte .LVL43 + 2947 04c2 38000000 .4byte .LFE16 + 2948 04c6 0100 .2byte 0x1 + 2949 04c8 55 .byte 0x55 + 2950 04c9 00000000 .4byte 0 + 2951 04cd 00000000 .4byte 0 + 2952 .LLST35: + 2953 04d1 00000000 .4byte .LFB15 + 2954 04d5 02000000 .4byte .LCFI9 + 2955 04d9 0200 .2byte 0x2 + 2956 04db 7D .byte 0x7d + 2957 04dc 00 .sleb128 0 + 2958 04dd 02000000 .4byte .LCFI9 + 2959 04e1 0C000000 .4byte .LFE15 + 2960 04e5 0200 .2byte 0x2 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 53 + + + 2961 04e7 7D .byte 0x7d + 2962 04e8 08 .sleb128 8 + 2963 04e9 00000000 .4byte 0 + 2964 04ed 00000000 .4byte 0 + 2965 .LLST36: + 2966 04f1 00000000 .4byte .LVL46 + 2967 04f5 07000000 .4byte .LVL47-1 + 2968 04f9 0100 .2byte 0x1 + 2969 04fb 50 .byte 0x50 + 2970 04fc 07000000 .4byte .LVL47-1 + 2971 0500 0C000000 .4byte .LFE15 + 2972 0504 0400 .2byte 0x4 + 2973 0506 F3 .byte 0xf3 + 2974 0507 01 .uleb128 0x1 + 2975 0508 50 .byte 0x50 + 2976 0509 9F .byte 0x9f + 2977 050a 00000000 .4byte 0 + 2978 050e 00000000 .4byte 0 + 2979 .LLST37: + 2980 0512 00000000 .4byte .LVL46 + 2981 0516 07000000 .4byte .LVL47-1 + 2982 051a 0100 .2byte 0x1 + 2983 051c 51 .byte 0x51 + 2984 051d 07000000 .4byte .LVL47-1 + 2985 0521 0C000000 .4byte .LFE15 + 2986 0525 0400 .2byte 0x4 + 2987 0527 F3 .byte 0xf3 + 2988 0528 01 .uleb128 0x1 + 2989 0529 51 .byte 0x51 + 2990 052a 9F .byte 0x9f + 2991 052b 00000000 .4byte 0 + 2992 052f 00000000 .4byte 0 + 2993 .LLST38: + 2994 0533 00000000 .4byte .LVL46 + 2995 0537 07000000 .4byte .LVL47-1 + 2996 053b 0100 .2byte 0x1 + 2997 053d 52 .byte 0x52 + 2998 053e 07000000 .4byte .LVL47-1 + 2999 0542 0C000000 .4byte .LFE15 + 3000 0546 0400 .2byte 0x4 + 3001 0548 F3 .byte 0xf3 + 3002 0549 01 .uleb128 0x1 + 3003 054a 52 .byte 0x52 + 3004 054b 9F .byte 0x9f + 3005 054c 00000000 .4byte 0 + 3006 0550 00000000 .4byte 0 + 3007 .LLST39: + 3008 0554 00000000 .4byte .LFB17 + 3009 0558 04000000 .4byte .LCFI10 + 3010 055c 0200 .2byte 0x2 + 3011 055e 7D .byte 0x7d + 3012 055f 00 .sleb128 0 + 3013 0560 04000000 .4byte .LCFI10 + 3014 0564 30000000 .4byte .LFE17 + 3015 0568 0200 .2byte 0x2 + 3016 056a 7D .byte 0x7d + 3017 056b 08 .sleb128 8 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 54 + + + 3018 056c 00000000 .4byte 0 + 3019 0570 00000000 .4byte 0 + 3020 .LLST40: + 3021 0574 00000000 .4byte .LVL48 + 3022 0578 22000000 .4byte .LVL49 + 3023 057c 0100 .2byte 0x1 + 3024 057e 50 .byte 0x50 + 3025 057f 22000000 .4byte .LVL49 + 3026 0583 25000000 .4byte .LVL50-1 + 3027 0587 0300 .2byte 0x3 + 3028 0589 70 .byte 0x70 + 3029 058a 64 .sleb128 -28 + 3030 058b 9F .byte 0x9f + 3031 058c 25000000 .4byte .LVL50-1 + 3032 0590 2A000000 .4byte .LVL51 + 3033 0594 0400 .2byte 0x4 + 3034 0596 F3 .byte 0xf3 + 3035 0597 01 .uleb128 0x1 + 3036 0598 50 .byte 0x50 + 3037 0599 9F .byte 0x9f + 3038 059a 2A000000 .4byte .LVL51 + 3039 059e 2E000000 .4byte .LVL52 + 3040 05a2 0100 .2byte 0x1 + 3041 05a4 50 .byte 0x50 + 3042 05a5 2E000000 .4byte .LVL52 + 3043 05a9 30000000 .4byte .LFE17 + 3044 05ad 0400 .2byte 0x4 + 3045 05af F3 .byte 0xf3 + 3046 05b0 01 .uleb128 0x1 + 3047 05b1 50 .byte 0x50 + 3048 05b2 9F .byte 0x9f + 3049 05b3 00000000 .4byte 0 + 3050 05b7 00000000 .4byte 0 + 3051 .LLST41: + 3052 05bb 00000000 .4byte .LVL48 + 3053 05bf 25000000 .4byte .LVL50-1 + 3054 05c3 0100 .2byte 0x1 + 3055 05c5 51 .byte 0x51 + 3056 05c6 25000000 .4byte .LVL50-1 + 3057 05ca 2A000000 .4byte .LVL51 + 3058 05ce 0400 .2byte 0x4 + 3059 05d0 F3 .byte 0xf3 + 3060 05d1 01 .uleb128 0x1 + 3061 05d2 51 .byte 0x51 + 3062 05d3 9F .byte 0x9f + 3063 05d4 2A000000 .4byte .LVL51 + 3064 05d8 30000000 .4byte .LFE17 + 3065 05dc 0100 .2byte 0x1 + 3066 05de 51 .byte 0x51 + 3067 05df 00000000 .4byte 0 + 3068 05e3 00000000 .4byte 0 + 3069 .section .debug_aranges,"",%progbits + 3070 0000 6C000000 .4byte 0x6c + 3071 0004 0200 .2byte 0x2 + 3072 0006 00000000 .4byte .Ldebug_info0 + 3073 000a 04 .byte 0x4 + 3074 000b 00 .byte 0 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 55 + + + 3075 000c 0000 .2byte 0 + 3076 000e 0000 .2byte 0 + 3077 0010 00000000 .4byte .LFB7 + 3078 0014 2A000000 .4byte .LFE7-.LFB7 + 3079 0018 00000000 .4byte .LFB8 + 3080 001c 2C000000 .4byte .LFE8-.LFB8 + 3081 0020 00000000 .4byte .LFB10 + 3082 0024 38000000 .4byte .LFE10-.LFB10 + 3083 0028 00000000 .4byte .LFB9 + 3084 002c 0C000000 .4byte .LFE9-.LFB9 + 3085 0030 00000000 .4byte .LFB11 + 3086 0034 2E000000 .4byte .LFE11-.LFB11 + 3087 0038 00000000 .4byte .LFB13 + 3088 003c 3A000000 .4byte .LFE13-.LFB13 + 3089 0040 00000000 .4byte .LFB12 + 3090 0044 0C000000 .4byte .LFE12-.LFB12 + 3091 0048 00000000 .4byte .LFB14 + 3092 004c 30000000 .4byte .LFE14-.LFB14 + 3093 0050 00000000 .4byte .LFB16 + 3094 0054 38000000 .4byte .LFE16-.LFB16 + 3095 0058 00000000 .4byte .LFB15 + 3096 005c 0C000000 .4byte .LFE15-.LFB15 + 3097 0060 00000000 .4byte .LFB17 + 3098 0064 30000000 .4byte .LFE17-.LFB17 + 3099 0068 00000000 .4byte 0 + 3100 006c 00000000 .4byte 0 + 3101 .section .debug_ranges,"",%progbits + 3102 .Ldebug_ranges0: + 3103 0000 00000000 .4byte .LFB7 + 3104 0004 2A000000 .4byte .LFE7 + 3105 0008 00000000 .4byte .LFB8 + 3106 000c 2C000000 .4byte .LFE8 + 3107 0010 00000000 .4byte .LFB10 + 3108 0014 38000000 .4byte .LFE10 + 3109 0018 00000000 .4byte .LFB9 + 3110 001c 0C000000 .4byte .LFE9 + 3111 0020 00000000 .4byte .LFB11 + 3112 0024 2E000000 .4byte .LFE11 + 3113 0028 00000000 .4byte .LFB13 + 3114 002c 3A000000 .4byte .LFE13 + 3115 0030 00000000 .4byte .LFB12 + 3116 0034 0C000000 .4byte .LFE12 + 3117 0038 00000000 .4byte .LFB14 + 3118 003c 30000000 .4byte .LFE14 + 3119 0040 00000000 .4byte .LFB16 + 3120 0044 38000000 .4byte .LFE16 + 3121 0048 00000000 .4byte .LFB15 + 3122 004c 0C000000 .4byte .LFE15 + 3123 0050 00000000 .4byte .LFB17 + 3124 0054 30000000 .4byte .LFE17 + 3125 0058 00000000 .4byte 0 + 3126 005c 00000000 .4byte 0 + 3127 .section .debug_line,"",%progbits + 3128 .Ldebug_line0: + 3129 0000 41020000 .section .debug_str,"MS",%progbits,1 + 3129 02001201 + 3129 00000201 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 56 + + + 3129 FB0E0D00 + 3129 01010101 + 3130 .LASF34: + 3131 0000 705F6D73 .ascii "p_msg\000" + 3131 6700 + 3132 .LASF84: + 3133 0006 63685365 .ascii "chSemSignalI\000" + 3133 6D536967 + 3133 6E616C49 + 3133 00 + 3134 .LASF59: + 3135 0013 7264796D .ascii "rdymsg\000" + 3135 736700 + 3136 .LASF69: + 3137 001a 63684D42 .ascii "chMBPostI\000" + 3137 506F7374 + 3137 4900 + 3138 .LASF67: + 3139 0024 63684D42 .ascii "chMBPostS\000" + 3139 506F7374 + 3139 5300 + 3140 .LASF58: + 3141 002e 4D61696C .ascii "Mailbox\000" + 3141 626F7800 + 3142 .LASF72: + 3143 0036 63684D42 .ascii "chMBPostAheadI\000" + 3143 506F7374 + 3143 41686561 + 3143 644900 + 3144 .LASF11: + 3145 0045 6C6F6E67 .ascii "long long unsigned int\000" + 3145 206C6F6E + 3145 6720756E + 3145 7369676E + 3145 65642069 + 3146 .LASF60: + 3147 005c 65786974 .ascii "exitcode\000" + 3147 636F6465 + 3147 00 + 3148 .LASF70: + 3149 0065 63684D42 .ascii "chMBPostAheadS\000" + 3149 506F7374 + 3149 41686561 + 3149 645300 + 3150 .LASF54: + 3151 0074 6D625F77 .ascii "mb_wrptr\000" + 3151 72707472 + 3151 00 + 3152 .LASF23: + 3153 007d 705F7072 .ascii "p_prio\000" + 3153 696F00 + 3154 .LASF10: + 3155 0084 6C6F6E67 .ascii "long long int\000" + 3155 206C6F6E + 3155 6720696E + 3155 7400 + 3156 .LASF1: + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 57 + + + 3157 0092 7369676E .ascii "signed char\000" + 3157 65642063 + 3157 68617200 + 3158 .LASF38: + 3159 009e 705F6D70 .ascii "p_mpool\000" + 3159 6F6F6C00 + 3160 .LASF49: + 3161 00a6 6D5F7175 .ascii "m_queue\000" + 3161 65756500 + 3162 .LASF7: + 3163 00ae 6C6F6E67 .ascii "long int\000" + 3163 20696E74 + 3163 00 + 3164 .LASF13: + 3165 00b7 74737461 .ascii "tstate_t\000" + 3165 74655F74 + 3165 00 + 3166 .LASF25: + 3167 00c0 705F6E65 .ascii "p_newer\000" + 3167 77657200 + 3168 .LASF46: + 3169 00c8 735F7175 .ascii "s_queue\000" + 3169 65756500 + 3170 .LASF82: + 3171 00d0 63685363 .ascii "chSchRescheduleS\000" + 3171 68526573 + 3171 63686564 + 3171 756C6553 + 3171 00 + 3172 .LASF41: + 3173 00e1 72656761 .ascii "regarm_t\000" + 3173 726D5F74 + 3173 00 + 3174 .LASF19: + 3175 00ea 636E745F .ascii "cnt_t\000" + 3175 7400 + 3176 .LASF0: + 3177 00f0 756E7369 .ascii "unsigned int\000" + 3177 676E6564 + 3177 20696E74 + 3177 00 + 3178 .LASF64: + 3179 00fd 63684D42 .ascii "chMBInit\000" + 3179 496E6974 + 3179 00 + 3180 .LASF9: + 3181 0106 6C6F6E67 .ascii "long unsigned int\000" + 3181 20756E73 + 3181 69676E65 + 3181 6420696E + 3181 7400 + 3182 .LASF57: + 3183 0118 6D625F65 .ascii "mb_emptysem\000" + 3183 6D707479 + 3183 73656D00 + 3184 .LASF47: + 3185 0124 735F636E .ascii "s_cnt\000" + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 58 + + + 3185 7400 + 3186 .LASF43: + 3187 012a 636F6E74 .ascii "context\000" + 3187 65787400 + 3188 .LASF4: + 3189 0132 73686F72 .ascii "short unsigned int\000" + 3189 7420756E + 3189 7369676E + 3189 65642069 + 3189 6E7400 + 3190 .LASF76: + 3191 0145 63684D42 .ascii "chMBFetchI\000" + 3191 46657463 + 3191 684900 + 3192 .LASF16: + 3193 0150 6D73675F .ascii "msg_t\000" + 3193 7400 + 3194 .LASF73: + 3195 0156 63684D42 .ascii "chMBFetchS\000" + 3195 46657463 + 3195 685300 + 3196 .LASF12: + 3197 0161 746D6F64 .ascii "tmode_t\000" + 3197 655F7400 + 3198 .LASF40: + 3199 0169 54687265 .ascii "ThreadsList\000" + 3199 6164734C + 3199 69737400 + 3200 .LASF17: + 3201 0175 6576656E .ascii "eventmask_t\000" + 3201 746D6173 + 3201 6B5F7400 + 3202 .LASF48: + 3203 0181 4D757465 .ascii "Mutex\000" + 3203 7800 + 3204 .LASF74: + 3205 0187 6D736770 .ascii "msgp\000" + 3205 00 + 3206 .LASF44: + 3207 018c 73697A65 .ascii "sizetype\000" + 3207 74797065 + 3207 00 + 3208 .LASF55: + 3209 0195 6D625F72 .ascii "mb_rdptr\000" + 3209 64707472 + 3209 00 + 3210 .LASF65: + 3211 019e 63684D42 .ascii "chMBReset\000" + 3211 52657365 + 3211 7400 + 3212 .LASF26: + 3213 01a8 705F6F6C .ascii "p_older\000" + 3213 64657200 + 3214 .LASF81: + 3215 01b0 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 3215 73657273 + 3215 5C496D61 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 59 + + + 3215 6E6F6C5C + 3215 64657665 + 3216 01dd 6C696361 .ascii "lications\\smartcities\000" + 3216 74696F6E + 3216 735C736D + 3216 61727463 + 3216 69746965 + 3217 .LASF39: + 3218 01f3 54687265 .ascii "ThreadsQueue\000" + 3218 61647351 + 3218 75657565 + 3218 00 + 3219 .LASF52: + 3220 0200 6D625F62 .ascii "mb_buffer\000" + 3220 75666665 + 3220 7200 + 3221 .LASF66: + 3222 020a 74696D65 .ascii "time\000" + 3222 00 + 3223 .LASF79: + 3224 020f 474E5520 .ascii "GNU C 4.7.2\000" + 3224 4320342E + 3224 372E3200 + 3225 .LASF14: + 3226 021b 74726566 .ascii "trefs_t\000" + 3226 735F7400 + 3227 .LASF22: + 3228 0223 705F7072 .ascii "p_prev\000" + 3228 657600 + 3229 .LASF15: + 3230 022a 74707269 .ascii "tprio_t\000" + 3230 6F5F7400 + 3231 .LASF6: + 3232 0232 696E7433 .ascii "int32_t\000" + 3232 325F7400 + 3233 .LASF2: + 3234 023a 756E7369 .ascii "unsigned char\000" + 3234 676E6564 + 3234 20636861 + 3234 7200 + 3235 .LASF53: + 3236 0248 6D625F74 .ascii "mb_top\000" + 3236 6F7000 + 3237 .LASF36: + 3238 024f 705F6D74 .ascii "p_mtxlist\000" + 3238 786C6973 + 3238 7400 + 3239 .LASF3: + 3240 0259 73686F72 .ascii "short int\000" + 3240 7420696E + 3240 7400 + 3241 .LASF28: + 3242 0263 705F7374 .ascii "p_state\000" + 3242 61746500 + 3243 .LASF62: + 3244 026b 65776D61 .ascii "ewmask\000" + 3244 736B00 + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 60 + + + 3245 .LASF21: + 3246 0272 705F6E65 .ascii "p_next\000" + 3246 787400 + 3247 .LASF29: + 3248 0279 705F666C .ascii "p_flags\000" + 3248 61677300 + 3249 .LASF68: + 3250 0281 63684D42 .ascii "chMBPost\000" + 3250 506F7374 + 3250 00 + 3251 .LASF20: + 3252 028a 54687265 .ascii "Thread\000" + 3252 616400 + 3253 .LASF35: + 3254 0291 705F6570 .ascii "p_epending\000" + 3254 656E6469 + 3254 6E6700 + 3255 .LASF8: + 3256 029c 75696E74 .ascii "uint32_t\000" + 3256 33325F74 + 3256 00 + 3257 .LASF63: + 3258 02a5 63686172 .ascii "char\000" + 3258 00 + 3259 .LASF83: + 3260 02aa 63685365 .ascii "chSemWaitTimeoutS\000" + 3260 6D576169 + 3260 7454696D + 3260 656F7574 + 3260 5300 + 3261 .LASF51: + 3262 02bc 6D5F6E65 .ascii "m_next\000" + 3262 787400 + 3263 .LASF18: + 3264 02c3 73797374 .ascii "systime_t\000" + 3264 696D655F + 3264 7400 + 3265 .LASF37: + 3266 02cd 705F7265 .ascii "p_realprio\000" + 3266 616C7072 + 3266 696F00 + 3267 .LASF31: + 3268 02d8 705F7469 .ascii "p_time\000" + 3268 6D6500 + 3269 .LASF71: + 3270 02df 63684D42 .ascii "chMBPostAhead\000" + 3270 506F7374 + 3270 41686561 + 3270 6400 + 3271 .LASF42: + 3272 02ed 696E7463 .ascii "intctx\000" + 3272 747800 + 3273 .LASF33: + 3274 02f4 705F6D73 .ascii "p_msgqueue\000" + 3274 67717565 + 3274 756500 + 3275 .LASF75: + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 61 + + + 3276 02ff 63684D42 .ascii "chMBFetch\000" + 3276 46657463 + 3276 6800 + 3277 .LASF45: + 3278 0309 53656D61 .ascii "Semaphore\000" + 3278 70686F72 + 3278 6500 + 3279 .LASF56: + 3280 0313 6D625F66 .ascii "mb_fullsem\000" + 3280 756C6C73 + 3280 656D00 + 3281 .LASF30: + 3282 031e 705F7265 .ascii "p_refs\000" + 3282 667300 + 3283 .LASF78: + 3284 0325 63685365 .ascii "chSemResetI\000" + 3284 6D526573 + 3284 65744900 + 3285 .LASF5: + 3286 0331 75696E74 .ascii "uint8_t\000" + 3286 385F7400 + 3287 .LASF80: + 3288 0339 2E2E2F2E .ascii "../..//os/kernel/src/chmboxes.c\000" + 3288 2E2F2F6F + 3288 732F6B65 + 3288 726E656C + 3288 2F737263 + 3289 .LASF61: + 3290 0359 77746F62 .ascii "wtobjp\000" + 3290 6A7000 + 3291 .LASF27: + 3292 0360 705F6E61 .ascii "p_name\000" + 3292 6D6500 + 3293 .LASF50: + 3294 0367 6D5F6F77 .ascii "m_owner\000" + 3294 6E657200 + 3295 .LASF24: + 3296 036f 705F6374 .ascii "p_ctx\000" + 3296 7800 + 3297 .LASF32: + 3298 0375 705F7761 .ascii "p_waiting\000" + 3298 6974696E + 3298 6700 + 3299 .LASF77: + 3300 037f 63685365 .ascii "chSemInit\000" + 3300 6D496E69 + 3300 7400 + 3301 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\cc9uz7bX.s page 62 + + +DEFINED SYMBOLS + *ABS*:00000000 chmboxes.c +C:\cygwin\tmp\cc9uz7bX.s:19 .text.chMBInit:00000000 $t +C:\cygwin\tmp\cc9uz7bX.s:25 .text.chMBInit:00000000 chMBInit +C:\cygwin\tmp\cc9uz7bX.s:70 .text.chMBReset:00000000 $t +C:\cygwin\tmp\cc9uz7bX.s:76 .text.chMBReset:00000000 chMBReset +C:\cygwin\tmp\cc9uz7bX.s:129 .text.chMBPostS:00000000 $t +C:\cygwin\tmp\cc9uz7bX.s:135 .text.chMBPostS:00000000 chMBPostS +C:\cygwin\tmp\cc9uz7bX.s:195 .text.chMBPost:00000000 $t +C:\cygwin\tmp\cc9uz7bX.s:201 .text.chMBPost:00000000 chMBPost +C:\cygwin\tmp\cc9uz7bX.s:232 .text.chMBPostI:00000000 $t +C:\cygwin\tmp\cc9uz7bX.s:238 .text.chMBPostI:00000000 chMBPostI +C:\cygwin\tmp\cc9uz7bX.s:292 .text.chMBPostAheadS:00000000 $t +C:\cygwin\tmp\cc9uz7bX.s:298 .text.chMBPostAheadS:00000000 chMBPostAheadS +C:\cygwin\tmp\cc9uz7bX.s:359 .text.chMBPostAhead:00000000 $t +C:\cygwin\tmp\cc9uz7bX.s:365 .text.chMBPostAhead:00000000 chMBPostAhead +C:\cygwin\tmp\cc9uz7bX.s:396 .text.chMBPostAheadI:00000000 $t +C:\cygwin\tmp\cc9uz7bX.s:402 .text.chMBPostAheadI:00000000 chMBPostAheadI +C:\cygwin\tmp\cc9uz7bX.s:460 .text.chMBFetchS:00000000 $t +C:\cygwin\tmp\cc9uz7bX.s:466 .text.chMBFetchS:00000000 chMBFetchS +C:\cygwin\tmp\cc9uz7bX.s:525 .text.chMBFetch:00000000 $t +C:\cygwin\tmp\cc9uz7bX.s:531 .text.chMBFetch:00000000 chMBFetch +C:\cygwin\tmp\cc9uz7bX.s:562 .text.chMBFetchI:00000000 $t +C:\cygwin\tmp\cc9uz7bX.s:568 .text.chMBFetchI:00000000 chMBFetchI + .debug_frame:00000010 $d + +UNDEFINED SYMBOLS +chSemInit +chSemResetI +chSchRescheduleS +chSemWaitTimeoutS +chSemSignalI diff --git a/Project/applications/smartcities/build/lst/chmemcore.lst b/Project/applications/smartcities/build/lst/chmemcore.lst new file mode 100644 index 0000000..46c977c --- /dev/null +++ b/Project/applications/smartcities/build/lst/chmemcore.lst @@ -0,0 +1,1131 @@ +ARM GAS C:\cygwin\tmp\cc60iRDy.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "chmemcore.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text._core_init,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .global _core_init + 22 .thumb + 23 .thumb_func + 24 .type _core_init, %function + 25 _core_init: + 26 .LFB7: + 27 .file 1 "../..//os/kernel/src/chmemcore.c" + 28 .loc 1 66 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .loc 1 71 0 + 34 0000 40F20001 movw r1, #:lower16:__heap_end__ + 35 .loc 1 70 0 + 36 0004 0848 ldr r0, .L2 + 37 0006 40F20002 movw r2, #:lower16:.LANCHOR0 + 38 .loc 1 71 0 + 39 000a 40F20003 movw r3, #:lower16:.LANCHOR1 + 40 000e C0F20001 movt r1, #:upper16:__heap_end__ + 41 .loc 1 70 0 + 42 0012 C0F20002 movt r2, #:upper16:.LANCHOR0 + 43 0016 20F00700 bic r0, r0, #7 + 44 .loc 1 71 0 + 45 001a C0F20003 movt r3, #:upper16:.LANCHOR1 + 46 001e 21F00701 bic r1, r1, #7 + 47 .loc 1 70 0 + 48 0022 1060 str r0, [r2, #0] + 49 .loc 1 71 0 + 50 0024 1960 str r1, [r3, #0] + 51 0026 7047 bx lr + 52 .L3: + 53 .align 2 + 54 .L2: + 55 0028 07000000 .word __heap_base__+7 + 56 .cfi_endproc + 57 .LFE7: + ARM GAS C:\cygwin\tmp\cc60iRDy.s page 2 + + + 58 .size _core_init, .-_core_init + 59 002c AFF30080 .section .text.chCoreAlloc,"ax",%progbits + 60 .align 2 + 61 .p2align 4,,15 + 62 .global chCoreAlloc + 63 .thumb + 64 .thumb_func + 65 .type chCoreAlloc, %function + 66 chCoreAlloc: + 67 .LFB8: + 68 .loc 1 91 0 + 69 .cfi_startproc + 70 @ args = 0, pretend = 0, frame = 0 + 71 @ frame_needed = 0, uses_anonymous_args = 0 + 72 @ link register save eliminated. + 73 .LVL0: + 74 .loc 1 94 0 + 75 @ 94 "../..//os/kernel/src/chmemcore.c" 1 + 76 0000 72B6 cpsid i + 77 @ 0 "" 2 + 78 .LVL1: + 79 .thumb + 80 .LBB4: + 81 .LBB5: + 82 .loc 1 118 0 + 83 0002 084A ldr r2, .L7 + 84 0004 0849 ldr r1, .L7+4 + 85 0006 1368 ldr r3, [r2, #0] + 86 0008 0968 ldr r1, [r1, #0] + 87 .loc 1 117 0 + 88 000a 0730 adds r0, r0, #7 + 89 .LVL2: + 90 000c 20F00700 bic r0, r0, #7 + 91 .LVL3: + 92 .loc 1 118 0 + 93 0010 C91A subs r1, r1, r3 + 94 0012 8842 cmp r0, r1 + 95 .LVL4: + 96 .loc 1 121 0 + 97 0014 9ABF itte ls + 98 0016 1818 addls r0, r3, r0 + 99 .LVL5: + 100 0018 1060 strls r0, [r2, #0] + 101 .loc 1 119 0 + 102 001a 0023 movhi r3, #0 + 103 .LVL6: + 104 .LBE5: + 105 .LBE4: + 106 .loc 1 96 0 + 107 @ 96 "../..//os/kernel/src/chmemcore.c" 1 + 108 001c 62B6 cpsie i + 109 @ 0 "" 2 + 110 .loc 1 98 0 + 111 .thumb + 112 001e 1846 mov r0, r3 + 113 0020 7047 bx lr + 114 .L8: + ARM GAS C:\cygwin\tmp\cc60iRDy.s page 3 + + + 115 0022 00BF .align 2 + 116 .L7: + 117 0024 00000000 .word .LANCHOR0 + 118 0028 00000000 .word .LANCHOR1 + 119 .cfi_endproc + 120 .LFE8: + 121 .size chCoreAlloc, .-chCoreAlloc + 122 002c AFF30080 .section .text.chCoreAllocI,"ax",%progbits + 123 .align 2 + 124 .p2align 4,,15 + 125 .global chCoreAllocI + 126 .thumb + 127 .thumb_func + 128 .type chCoreAllocI, %function + 129 chCoreAllocI: + 130 .LFB9: + 131 .loc 1 112 0 + 132 .cfi_startproc + 133 @ args = 0, pretend = 0, frame = 0 + 134 @ frame_needed = 0, uses_anonymous_args = 0 + 135 @ link register save eliminated. + 136 .LVL7: + 137 .loc 1 118 0 + 138 0000 074A ldr r2, .L12 + 139 0002 0849 ldr r1, .L12+4 + 140 0004 1368 ldr r3, [r2, #0] + 141 0006 0968 ldr r1, [r1, #0] + 142 .loc 1 117 0 + 143 0008 0730 adds r0, r0, #7 + 144 .LVL8: + 145 000a 20F00700 bic r0, r0, #7 + 146 .LVL9: + 147 .loc 1 118 0 + 148 000e C91A subs r1, r1, r3 + 149 0010 8842 cmp r0, r1 + 150 .LVL10: + 151 .loc 1 121 0 + 152 0012 9ABF itte ls + 153 0014 1818 addls r0, r3, r0 + 154 .LVL11: + 155 0016 1060 strls r0, [r2, #0] + 156 .loc 1 119 0 + 157 0018 0023 movhi r3, #0 + 158 .LVL12: + 159 .loc 1 123 0 + 160 001a 1846 mov r0, r3 + 161 001c 7047 bx lr + 162 .L13: + 163 001e 00BF .align 2 + 164 .L12: + 165 0020 00000000 .word .LANCHOR0 + 166 0024 00000000 .word .LANCHOR1 + 167 .cfi_endproc + 168 .LFE9: + 169 .size chCoreAllocI, .-chCoreAllocI + 170 0028 AFF30080 .section .text.chCoreStatus,"ax",%progbits + 170 AFF30080 + ARM GAS C:\cygwin\tmp\cc60iRDy.s page 4 + + + 171 .align 2 + 172 .p2align 4,,15 + 173 .global chCoreStatus + 174 .thumb + 175 .thumb_func + 176 .type chCoreStatus, %function + 177 chCoreStatus: + 178 .LFB10: + 179 .loc 1 132 0 + 180 .cfi_startproc + 181 @ args = 0, pretend = 0, frame = 0 + 182 @ frame_needed = 0, uses_anonymous_args = 0 + 183 @ link register save eliminated. + 184 .loc 1 134 0 + 185 0000 40F20002 movw r2, #:lower16:.LANCHOR1 + 186 0004 40F20003 movw r3, #:lower16:.LANCHOR0 + 187 0008 C0F20002 movt r2, #:upper16:.LANCHOR1 + 188 000c C0F20003 movt r3, #:upper16:.LANCHOR0 + 189 0010 1068 ldr r0, [r2, #0] + 190 0012 1B68 ldr r3, [r3, #0] + 191 .loc 1 135 0 + 192 0014 C01A subs r0, r0, r3 + 193 0016 7047 bx lr + 194 .cfi_endproc + 195 .LFE10: + 196 .size chCoreStatus, .-chCoreStatus + 197 0018 AFF30080 .section .bss.endmem,"aw",%nobits + 197 AFF30080 + 198 .align 2 + 199 .set .LANCHOR1,. + 0 + 200 .type endmem, %object + 201 .size endmem, 4 + 202 endmem: + 203 0000 00000000 .space 4 + 204 .section .bss.nextmem,"aw",%nobits + 205 .align 2 + 206 .set .LANCHOR0,. + 0 + 207 .type nextmem, %object + 208 .size nextmem, 4 + 209 nextmem: + 210 0000 00000000 .space 4 + 211 .text + 212 .Letext0: + 213 .file 2 "c:\\yagarto\\bin\\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h" + 214 .file 3 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 215 .section .debug_info,"",%progbits + 216 .Ldebug_info0: + 217 0000 DF010000 .4byte 0x1df + 218 0004 0200 .2byte 0x2 + 219 0006 00000000 .4byte .Ldebug_abbrev0 + 220 000a 04 .byte 0x4 + 221 000b 01 .uleb128 0x1 + 222 000c 8E000000 .4byte .LASF17 + 223 0010 01 .byte 0x1 + 224 0011 C3000000 .4byte .LASF18 + 225 0015 4B000000 .4byte .LASF19 + 226 0019 00000000 .4byte .Ldebug_ranges0+0 + ARM GAS C:\cygwin\tmp\cc60iRDy.s page 5 + + + 227 001d 00000000 .4byte 0 + 228 0021 00000000 .4byte 0 + 229 0025 00000000 .4byte .Ldebug_line0 + 230 0029 02 .uleb128 0x2 + 231 002a 04 .byte 0x4 + 232 002b 05 .byte 0x5 + 233 002c 696E7400 .ascii "int\000" + 234 0030 03 .uleb128 0x3 + 235 0031 21000000 .4byte .LASF2 + 236 0035 02 .byte 0x2 + 237 0036 D5 .byte 0xd5 + 238 0037 3B000000 .4byte 0x3b + 239 003b 04 .uleb128 0x4 + 240 003c 04 .byte 0x4 + 241 003d 07 .byte 0x7 + 242 003e 4E010000 .4byte .LASF0 + 243 0042 04 .uleb128 0x4 + 244 0043 01 .byte 0x1 + 245 0044 06 .byte 0x6 + 246 0045 28010000 .4byte .LASF1 + 247 0049 03 .uleb128 0x3 + 248 004a E4000000 .4byte .LASF3 + 249 004e 03 .byte 0x3 + 250 004f 2A .byte 0x2a + 251 0050 54000000 .4byte 0x54 + 252 0054 04 .uleb128 0x4 + 253 0055 01 .byte 0x1 + 254 0056 08 .byte 0x8 + 255 0057 EC000000 .4byte .LASF4 + 256 005b 04 .uleb128 0x4 + 257 005c 02 .byte 0x2 + 258 005d 05 .byte 0x5 + 259 005e 44010000 .4byte .LASF5 + 260 0062 04 .uleb128 0x4 + 261 0063 02 .byte 0x2 + 262 0064 07 .byte 0x7 + 263 0065 0E000000 .4byte .LASF6 + 264 0069 04 .uleb128 0x4 + 265 006a 04 .byte 0x4 + 266 006b 05 .byte 0x5 + 267 006c 0B010000 .4byte .LASF7 + 268 0070 04 .uleb128 0x4 + 269 0071 04 .byte 0x4 + 270 0072 07 .byte 0x7 + 271 0073 9A000000 .4byte .LASF8 + 272 0077 04 .uleb128 0x4 + 273 0078 08 .byte 0x8 + 274 0079 05 .byte 0x5 + 275 007a 00000000 .4byte .LASF9 + 276 007e 04 .uleb128 0x4 + 277 007f 08 .byte 0x8 + 278 0080 07 .byte 0x7 + 279 0081 AC000000 .4byte .LASF10 + 280 0085 05 .uleb128 0x5 + 281 0086 04 .byte 0x4 + 282 0087 04 .uleb128 0x4 + 283 0088 04 .byte 0x4 + ARM GAS C:\cygwin\tmp\cc60iRDy.s page 6 + + + 284 0089 07 .byte 0x7 + 285 008a 5B010000 .4byte .LASF11 + 286 008e 04 .uleb128 0x4 + 287 008f 01 .byte 0x1 + 288 0090 08 .byte 0x8 + 289 0091 FA000000 .4byte .LASF12 + 290 0095 06 .uleb128 0x6 + 291 0096 04 .byte 0x4 + 292 0097 49000000 .4byte 0x49 + 293 009b 07 .uleb128 0x7 + 294 009c 01 .byte 0x1 + 295 009d 1B010000 .4byte .LASF20 + 296 00a1 01 .byte 0x1 + 297 00a2 70 .byte 0x70 + 298 00a3 01 .byte 0x1 + 299 00a4 85000000 .4byte 0x85 + 300 00a8 01 .byte 0x1 + 301 00a9 C2000000 .4byte 0xc2 + 302 00ad 08 .uleb128 0x8 + 303 00ae 34010000 .4byte .LASF21 + 304 00b2 01 .byte 0x1 + 305 00b3 70 .byte 0x70 + 306 00b4 30000000 .4byte 0x30 + 307 00b8 09 .uleb128 0x9 + 308 00b9 7000 .ascii "p\000" + 309 00bb 01 .byte 0x1 + 310 00bc 71 .byte 0x71 + 311 00bd 85000000 .4byte 0x85 + 312 00c1 00 .byte 0 + 313 00c2 0A .uleb128 0xa + 314 00c3 01 .byte 0x1 + 315 00c4 39010000 .4byte .LASF22 + 316 00c8 01 .byte 0x1 + 317 00c9 42 .byte 0x42 + 318 00ca 01 .byte 0x1 + 319 00cb 00000000 .4byte .LFB7 + 320 00cf 2C000000 .4byte .LFE7 + 321 00d3 02 .byte 0x2 + 322 00d4 7D .byte 0x7d + 323 00d5 00 .sleb128 0 + 324 00d6 01 .byte 0x1 + 325 00d7 F6000000 .4byte 0xf6 + 326 00db 0B .uleb128 0xb + 327 00dc 3D000000 .4byte .LASF13 + 328 00e0 01 .byte 0x1 + 329 00e1 44 .byte 0x44 + 330 00e2 F6000000 .4byte 0xf6 + 331 00e6 01 .byte 0x1 + 332 00e7 01 .byte 0x1 + 333 00e8 0B .uleb128 0xb + 334 00e9 30000000 .4byte .LASF14 + 335 00ed 01 .byte 0x1 + 336 00ee 45 .byte 0x45 + 337 00ef F6000000 .4byte 0xf6 + 338 00f3 01 .byte 0x1 + 339 00f4 01 .byte 0x1 + 340 00f5 00 .byte 0 + ARM GAS C:\cygwin\tmp\cc60iRDy.s page 7 + + + 341 00f6 0C .uleb128 0xc + 342 00f7 49000000 .4byte 0x49 + 343 00fb 01010000 .4byte 0x101 + 344 00ff 0D .uleb128 0xd + 345 0100 00 .byte 0 + 346 0101 0E .uleb128 0xe + 347 0102 01 .byte 0x1 + 348 0103 FF000000 .4byte .LASF23 + 349 0107 01 .byte 0x1 + 350 0108 5B .byte 0x5b + 351 0109 01 .byte 0x1 + 352 010a 85000000 .4byte 0x85 + 353 010e 00000000 .4byte .LFB8 + 354 0112 2C000000 .4byte .LFE8 + 355 0116 02 .byte 0x2 + 356 0117 7D .byte 0x7d + 357 0118 00 .sleb128 0 + 358 0119 01 .byte 0x1 + 359 011a 65010000 .4byte 0x165 + 360 011e 0F .uleb128 0xf + 361 011f 34010000 .4byte .LASF21 + 362 0123 01 .byte 0x1 + 363 0124 5B .byte 0x5b + 364 0125 30000000 .4byte 0x30 + 365 0129 00000000 .4byte .LLST0 + 366 012d 10 .uleb128 0x10 + 367 012e 7000 .ascii "p\000" + 368 0130 01 .byte 0x1 + 369 0131 5C .byte 0x5c + 370 0132 85000000 .4byte 0x85 + 371 0136 01 .byte 0x1 + 372 0137 53 .byte 0x53 + 373 0138 11 .uleb128 0x11 + 374 0139 9B000000 .4byte 0x9b + 375 013d 02000000 .4byte .LBB4 + 376 0141 1C000000 .4byte .LBE4 + 377 0145 01 .byte 0x1 + 378 0146 5F .byte 0x5f + 379 0147 12 .uleb128 0x12 + 380 0148 AD000000 .4byte 0xad + 381 014c 2E000000 .4byte .LLST1 + 382 0150 13 .uleb128 0x13 + 383 0151 02000000 .4byte .LBB5 + 384 0155 1C000000 .4byte .LBE5 + 385 0159 14 .uleb128 0x14 + 386 015a B8000000 .4byte 0xb8 + 387 015e 6C000000 .4byte .LLST2 + 388 0162 00 .byte 0 + 389 0163 00 .byte 0 + 390 0164 00 .byte 0 + 391 0165 15 .uleb128 0x15 + 392 0166 9B000000 .4byte 0x9b + 393 016a 00000000 .4byte .LFB9 + 394 016e 28000000 .4byte .LFE9 + 395 0172 02 .byte 0x2 + 396 0173 7D .byte 0x7d + 397 0174 00 .sleb128 0 + ARM GAS C:\cygwin\tmp\cc60iRDy.s page 8 + + + 398 0175 01 .byte 0x1 + 399 0176 8D010000 .4byte 0x18d + 400 017a 12 .uleb128 0x12 + 401 017b AD000000 .4byte 0xad + 402 017f 8E000000 .4byte .LLST3 + 403 0183 14 .uleb128 0x14 + 404 0184 B8000000 .4byte 0xb8 + 405 0188 CC000000 .4byte .LLST4 + 406 018c 00 .byte 0 + 407 018d 16 .uleb128 0x16 + 408 018e 01 .byte 0x1 + 409 018f 64010000 .4byte .LASF24 + 410 0193 01 .byte 0x1 + 411 0194 84 .byte 0x84 + 412 0195 01 .byte 0x1 + 413 0196 30000000 .4byte 0x30 + 414 019a 00000000 .4byte .LFB10 + 415 019e 18000000 .4byte .LFE10 + 416 01a2 02 .byte 0x2 + 417 01a3 7D .byte 0x7d + 418 01a4 00 .sleb128 0 + 419 01a5 01 .byte 0x1 + 420 01a6 17 .uleb128 0x17 + 421 01a7 28000000 .4byte .LASF15 + 422 01ab 01 .byte 0x1 + 423 01ac 3A .byte 0x3a + 424 01ad 95000000 .4byte 0x95 + 425 01b1 05 .byte 0x5 + 426 01b2 03 .byte 0x3 + 427 01b3 00000000 .4byte nextmem + 428 01b7 17 .uleb128 0x17 + 429 01b8 14010000 .4byte .LASF16 + 430 01bc 01 .byte 0x1 + 431 01bd 3B .byte 0x3b + 432 01be 95000000 .4byte 0x95 + 433 01c2 05 .byte 0x5 + 434 01c3 03 .byte 0x3 + 435 01c4 00000000 .4byte endmem + 436 01c8 0B .uleb128 0xb + 437 01c9 3D000000 .4byte .LASF13 + 438 01cd 01 .byte 0x1 + 439 01ce 44 .byte 0x44 + 440 01cf F6000000 .4byte 0xf6 + 441 01d3 01 .byte 0x1 + 442 01d4 01 .byte 0x1 + 443 01d5 0B .uleb128 0xb + 444 01d6 30000000 .4byte .LASF14 + 445 01da 01 .byte 0x1 + 446 01db 45 .byte 0x45 + 447 01dc F6000000 .4byte 0xf6 + 448 01e0 01 .byte 0x1 + 449 01e1 01 .byte 0x1 + 450 01e2 00 .byte 0 + 451 .section .debug_abbrev,"",%progbits + 452 .Ldebug_abbrev0: + 453 0000 01 .uleb128 0x1 + 454 0001 11 .uleb128 0x11 + ARM GAS C:\cygwin\tmp\cc60iRDy.s page 9 + + + 455 0002 01 .byte 0x1 + 456 0003 25 .uleb128 0x25 + 457 0004 0E .uleb128 0xe + 458 0005 13 .uleb128 0x13 + 459 0006 0B .uleb128 0xb + 460 0007 03 .uleb128 0x3 + 461 0008 0E .uleb128 0xe + 462 0009 1B .uleb128 0x1b + 463 000a 0E .uleb128 0xe + 464 000b 55 .uleb128 0x55 + 465 000c 06 .uleb128 0x6 + 466 000d 11 .uleb128 0x11 + 467 000e 01 .uleb128 0x1 + 468 000f 52 .uleb128 0x52 + 469 0010 01 .uleb128 0x1 + 470 0011 10 .uleb128 0x10 + 471 0012 06 .uleb128 0x6 + 472 0013 00 .byte 0 + 473 0014 00 .byte 0 + 474 0015 02 .uleb128 0x2 + 475 0016 24 .uleb128 0x24 + 476 0017 00 .byte 0 + 477 0018 0B .uleb128 0xb + 478 0019 0B .uleb128 0xb + 479 001a 3E .uleb128 0x3e + 480 001b 0B .uleb128 0xb + 481 001c 03 .uleb128 0x3 + 482 001d 08 .uleb128 0x8 + 483 001e 00 .byte 0 + 484 001f 00 .byte 0 + 485 0020 03 .uleb128 0x3 + 486 0021 16 .uleb128 0x16 + 487 0022 00 .byte 0 + 488 0023 03 .uleb128 0x3 + 489 0024 0E .uleb128 0xe + 490 0025 3A .uleb128 0x3a + 491 0026 0B .uleb128 0xb + 492 0027 3B .uleb128 0x3b + 493 0028 0B .uleb128 0xb + 494 0029 49 .uleb128 0x49 + 495 002a 13 .uleb128 0x13 + 496 002b 00 .byte 0 + 497 002c 00 .byte 0 + 498 002d 04 .uleb128 0x4 + 499 002e 24 .uleb128 0x24 + 500 002f 00 .byte 0 + 501 0030 0B .uleb128 0xb + 502 0031 0B .uleb128 0xb + 503 0032 3E .uleb128 0x3e + 504 0033 0B .uleb128 0xb + 505 0034 03 .uleb128 0x3 + 506 0035 0E .uleb128 0xe + 507 0036 00 .byte 0 + 508 0037 00 .byte 0 + 509 0038 05 .uleb128 0x5 + 510 0039 0F .uleb128 0xf + 511 003a 00 .byte 0 + ARM GAS C:\cygwin\tmp\cc60iRDy.s page 10 + + + 512 003b 0B .uleb128 0xb + 513 003c 0B .uleb128 0xb + 514 003d 00 .byte 0 + 515 003e 00 .byte 0 + 516 003f 06 .uleb128 0x6 + 517 0040 0F .uleb128 0xf + 518 0041 00 .byte 0 + 519 0042 0B .uleb128 0xb + 520 0043 0B .uleb128 0xb + 521 0044 49 .uleb128 0x49 + 522 0045 13 .uleb128 0x13 + 523 0046 00 .byte 0 + 524 0047 00 .byte 0 + 525 0048 07 .uleb128 0x7 + 526 0049 2E .uleb128 0x2e + 527 004a 01 .byte 0x1 + 528 004b 3F .uleb128 0x3f + 529 004c 0C .uleb128 0xc + 530 004d 03 .uleb128 0x3 + 531 004e 0E .uleb128 0xe + 532 004f 3A .uleb128 0x3a + 533 0050 0B .uleb128 0xb + 534 0051 3B .uleb128 0x3b + 535 0052 0B .uleb128 0xb + 536 0053 27 .uleb128 0x27 + 537 0054 0C .uleb128 0xc + 538 0055 49 .uleb128 0x49 + 539 0056 13 .uleb128 0x13 + 540 0057 20 .uleb128 0x20 + 541 0058 0B .uleb128 0xb + 542 0059 01 .uleb128 0x1 + 543 005a 13 .uleb128 0x13 + 544 005b 00 .byte 0 + 545 005c 00 .byte 0 + 546 005d 08 .uleb128 0x8 + 547 005e 05 .uleb128 0x5 + 548 005f 00 .byte 0 + 549 0060 03 .uleb128 0x3 + 550 0061 0E .uleb128 0xe + 551 0062 3A .uleb128 0x3a + 552 0063 0B .uleb128 0xb + 553 0064 3B .uleb128 0x3b + 554 0065 0B .uleb128 0xb + 555 0066 49 .uleb128 0x49 + 556 0067 13 .uleb128 0x13 + 557 0068 00 .byte 0 + 558 0069 00 .byte 0 + 559 006a 09 .uleb128 0x9 + 560 006b 34 .uleb128 0x34 + 561 006c 00 .byte 0 + 562 006d 03 .uleb128 0x3 + 563 006e 08 .uleb128 0x8 + 564 006f 3A .uleb128 0x3a + 565 0070 0B .uleb128 0xb + 566 0071 3B .uleb128 0x3b + 567 0072 0B .uleb128 0xb + 568 0073 49 .uleb128 0x49 + ARM GAS C:\cygwin\tmp\cc60iRDy.s page 11 + + + 569 0074 13 .uleb128 0x13 + 570 0075 00 .byte 0 + 571 0076 00 .byte 0 + 572 0077 0A .uleb128 0xa + 573 0078 2E .uleb128 0x2e + 574 0079 01 .byte 0x1 + 575 007a 3F .uleb128 0x3f + 576 007b 0C .uleb128 0xc + 577 007c 03 .uleb128 0x3 + 578 007d 0E .uleb128 0xe + 579 007e 3A .uleb128 0x3a + 580 007f 0B .uleb128 0xb + 581 0080 3B .uleb128 0x3b + 582 0081 0B .uleb128 0xb + 583 0082 27 .uleb128 0x27 + 584 0083 0C .uleb128 0xc + 585 0084 11 .uleb128 0x11 + 586 0085 01 .uleb128 0x1 + 587 0086 12 .uleb128 0x12 + 588 0087 01 .uleb128 0x1 + 589 0088 40 .uleb128 0x40 + 590 0089 0A .uleb128 0xa + 591 008a 9742 .uleb128 0x2117 + 592 008c 0C .uleb128 0xc + 593 008d 01 .uleb128 0x1 + 594 008e 13 .uleb128 0x13 + 595 008f 00 .byte 0 + 596 0090 00 .byte 0 + 597 0091 0B .uleb128 0xb + 598 0092 34 .uleb128 0x34 + 599 0093 00 .byte 0 + 600 0094 03 .uleb128 0x3 + 601 0095 0E .uleb128 0xe + 602 0096 3A .uleb128 0x3a + 603 0097 0B .uleb128 0xb + 604 0098 3B .uleb128 0x3b + 605 0099 0B .uleb128 0xb + 606 009a 49 .uleb128 0x49 + 607 009b 13 .uleb128 0x13 + 608 009c 3F .uleb128 0x3f + 609 009d 0C .uleb128 0xc + 610 009e 3C .uleb128 0x3c + 611 009f 0C .uleb128 0xc + 612 00a0 00 .byte 0 + 613 00a1 00 .byte 0 + 614 00a2 0C .uleb128 0xc + 615 00a3 01 .uleb128 0x1 + 616 00a4 01 .byte 0x1 + 617 00a5 49 .uleb128 0x49 + 618 00a6 13 .uleb128 0x13 + 619 00a7 01 .uleb128 0x1 + 620 00a8 13 .uleb128 0x13 + 621 00a9 00 .byte 0 + 622 00aa 00 .byte 0 + 623 00ab 0D .uleb128 0xd + 624 00ac 21 .uleb128 0x21 + 625 00ad 00 .byte 0 + ARM GAS C:\cygwin\tmp\cc60iRDy.s page 12 + + + 626 00ae 00 .byte 0 + 627 00af 00 .byte 0 + 628 00b0 0E .uleb128 0xe + 629 00b1 2E .uleb128 0x2e + 630 00b2 01 .byte 0x1 + 631 00b3 3F .uleb128 0x3f + 632 00b4 0C .uleb128 0xc + 633 00b5 03 .uleb128 0x3 + 634 00b6 0E .uleb128 0xe + 635 00b7 3A .uleb128 0x3a + 636 00b8 0B .uleb128 0xb + 637 00b9 3B .uleb128 0x3b + 638 00ba 0B .uleb128 0xb + 639 00bb 27 .uleb128 0x27 + 640 00bc 0C .uleb128 0xc + 641 00bd 49 .uleb128 0x49 + 642 00be 13 .uleb128 0x13 + 643 00bf 11 .uleb128 0x11 + 644 00c0 01 .uleb128 0x1 + 645 00c1 12 .uleb128 0x12 + 646 00c2 01 .uleb128 0x1 + 647 00c3 40 .uleb128 0x40 + 648 00c4 0A .uleb128 0xa + 649 00c5 9742 .uleb128 0x2117 + 650 00c7 0C .uleb128 0xc + 651 00c8 01 .uleb128 0x1 + 652 00c9 13 .uleb128 0x13 + 653 00ca 00 .byte 0 + 654 00cb 00 .byte 0 + 655 00cc 0F .uleb128 0xf + 656 00cd 05 .uleb128 0x5 + 657 00ce 00 .byte 0 + 658 00cf 03 .uleb128 0x3 + 659 00d0 0E .uleb128 0xe + 660 00d1 3A .uleb128 0x3a + 661 00d2 0B .uleb128 0xb + 662 00d3 3B .uleb128 0x3b + 663 00d4 0B .uleb128 0xb + 664 00d5 49 .uleb128 0x49 + 665 00d6 13 .uleb128 0x13 + 666 00d7 02 .uleb128 0x2 + 667 00d8 06 .uleb128 0x6 + 668 00d9 00 .byte 0 + 669 00da 00 .byte 0 + 670 00db 10 .uleb128 0x10 + 671 00dc 34 .uleb128 0x34 + 672 00dd 00 .byte 0 + 673 00de 03 .uleb128 0x3 + 674 00df 08 .uleb128 0x8 + 675 00e0 3A .uleb128 0x3a + 676 00e1 0B .uleb128 0xb + 677 00e2 3B .uleb128 0x3b + 678 00e3 0B .uleb128 0xb + 679 00e4 49 .uleb128 0x49 + 680 00e5 13 .uleb128 0x13 + 681 00e6 02 .uleb128 0x2 + 682 00e7 0A .uleb128 0xa + ARM GAS C:\cygwin\tmp\cc60iRDy.s page 13 + + + 683 00e8 00 .byte 0 + 684 00e9 00 .byte 0 + 685 00ea 11 .uleb128 0x11 + 686 00eb 1D .uleb128 0x1d + 687 00ec 01 .byte 0x1 + 688 00ed 31 .uleb128 0x31 + 689 00ee 13 .uleb128 0x13 + 690 00ef 11 .uleb128 0x11 + 691 00f0 01 .uleb128 0x1 + 692 00f1 12 .uleb128 0x12 + 693 00f2 01 .uleb128 0x1 + 694 00f3 58 .uleb128 0x58 + 695 00f4 0B .uleb128 0xb + 696 00f5 59 .uleb128 0x59 + 697 00f6 0B .uleb128 0xb + 698 00f7 00 .byte 0 + 699 00f8 00 .byte 0 + 700 00f9 12 .uleb128 0x12 + 701 00fa 05 .uleb128 0x5 + 702 00fb 00 .byte 0 + 703 00fc 31 .uleb128 0x31 + 704 00fd 13 .uleb128 0x13 + 705 00fe 02 .uleb128 0x2 + 706 00ff 06 .uleb128 0x6 + 707 0100 00 .byte 0 + 708 0101 00 .byte 0 + 709 0102 13 .uleb128 0x13 + 710 0103 0B .uleb128 0xb + 711 0104 01 .byte 0x1 + 712 0105 11 .uleb128 0x11 + 713 0106 01 .uleb128 0x1 + 714 0107 12 .uleb128 0x12 + 715 0108 01 .uleb128 0x1 + 716 0109 00 .byte 0 + 717 010a 00 .byte 0 + 718 010b 14 .uleb128 0x14 + 719 010c 34 .uleb128 0x34 + 720 010d 00 .byte 0 + 721 010e 31 .uleb128 0x31 + 722 010f 13 .uleb128 0x13 + 723 0110 02 .uleb128 0x2 + 724 0111 06 .uleb128 0x6 + 725 0112 00 .byte 0 + 726 0113 00 .byte 0 + 727 0114 15 .uleb128 0x15 + 728 0115 2E .uleb128 0x2e + 729 0116 01 .byte 0x1 + 730 0117 31 .uleb128 0x31 + 731 0118 13 .uleb128 0x13 + 732 0119 11 .uleb128 0x11 + 733 011a 01 .uleb128 0x1 + 734 011b 12 .uleb128 0x12 + 735 011c 01 .uleb128 0x1 + 736 011d 40 .uleb128 0x40 + 737 011e 0A .uleb128 0xa + 738 011f 9742 .uleb128 0x2117 + 739 0121 0C .uleb128 0xc + ARM GAS C:\cygwin\tmp\cc60iRDy.s page 14 + + + 740 0122 01 .uleb128 0x1 + 741 0123 13 .uleb128 0x13 + 742 0124 00 .byte 0 + 743 0125 00 .byte 0 + 744 0126 16 .uleb128 0x16 + 745 0127 2E .uleb128 0x2e + 746 0128 00 .byte 0 + 747 0129 3F .uleb128 0x3f + 748 012a 0C .uleb128 0xc + 749 012b 03 .uleb128 0x3 + 750 012c 0E .uleb128 0xe + 751 012d 3A .uleb128 0x3a + 752 012e 0B .uleb128 0xb + 753 012f 3B .uleb128 0x3b + 754 0130 0B .uleb128 0xb + 755 0131 27 .uleb128 0x27 + 756 0132 0C .uleb128 0xc + 757 0133 49 .uleb128 0x49 + 758 0134 13 .uleb128 0x13 + 759 0135 11 .uleb128 0x11 + 760 0136 01 .uleb128 0x1 + 761 0137 12 .uleb128 0x12 + 762 0138 01 .uleb128 0x1 + 763 0139 40 .uleb128 0x40 + 764 013a 0A .uleb128 0xa + 765 013b 9742 .uleb128 0x2117 + 766 013d 0C .uleb128 0xc + 767 013e 00 .byte 0 + 768 013f 00 .byte 0 + 769 0140 17 .uleb128 0x17 + 770 0141 34 .uleb128 0x34 + 771 0142 00 .byte 0 + 772 0143 03 .uleb128 0x3 + 773 0144 0E .uleb128 0xe + 774 0145 3A .uleb128 0x3a + 775 0146 0B .uleb128 0xb + 776 0147 3B .uleb128 0x3b + 777 0148 0B .uleb128 0xb + 778 0149 49 .uleb128 0x49 + 779 014a 13 .uleb128 0x13 + 780 014b 02 .uleb128 0x2 + 781 014c 0A .uleb128 0xa + 782 014d 00 .byte 0 + 783 014e 00 .byte 0 + 784 014f 00 .byte 0 + 785 .section .debug_loc,"",%progbits + 786 .Ldebug_loc0: + 787 .LLST0: + 788 0000 00000000 .4byte .LVL0 + 789 0004 0C000000 .4byte .LVL2 + 790 0008 0100 .2byte 0x1 + 791 000a 50 .byte 0x50 + 792 000b 0C000000 .4byte .LVL2 + 793 000f 10000000 .4byte .LVL3 + 794 0013 0300 .2byte 0x3 + 795 0015 70 .byte 0x70 + 796 0016 79 .sleb128 -7 + ARM GAS C:\cygwin\tmp\cc60iRDy.s page 15 + + + 797 0017 9F .byte 0x9f + 798 0018 10000000 .4byte .LVL3 + 799 001c 2C000000 .4byte .LFE8 + 800 0020 0400 .2byte 0x4 + 801 0022 F3 .byte 0xf3 + 802 0023 01 .uleb128 0x1 + 803 0024 50 .byte 0x50 + 804 0025 9F .byte 0x9f + 805 0026 00000000 .4byte 0 + 806 002a 00000000 .4byte 0 + 807 .LLST1: + 808 002e 02000000 .4byte .LVL1 + 809 0032 0C000000 .4byte .LVL2 + 810 0036 0100 .2byte 0x1 + 811 0038 50 .byte 0x50 + 812 0039 0C000000 .4byte .LVL2 + 813 003d 10000000 .4byte .LVL3 + 814 0041 0300 .2byte 0x3 + 815 0043 70 .byte 0x70 + 816 0044 79 .sleb128 -7 + 817 0045 9F .byte 0x9f + 818 0046 10000000 .4byte .LVL3 + 819 004a 18000000 .4byte .LVL5 + 820 004e 0100 .2byte 0x1 + 821 0050 50 .byte 0x50 + 822 0051 18000000 .4byte .LVL5 + 823 0055 2C000000 .4byte .LFE8 + 824 0059 0900 .2byte 0x9 + 825 005b F3 .byte 0xf3 + 826 005c 01 .uleb128 0x1 + 827 005d 50 .byte 0x50 + 828 005e 23 .byte 0x23 + 829 005f 07 .uleb128 0x7 + 830 0060 09 .byte 0x9 + 831 0061 F8 .byte 0xf8 + 832 0062 1A .byte 0x1a + 833 0063 9F .byte 0x9f + 834 0064 00000000 .4byte 0 + 835 0068 00000000 .4byte 0 + 836 .LLST2: + 837 006c 14000000 .4byte .LVL4 + 838 0070 1C000000 .4byte .LVL6 + 839 0074 0100 .2byte 0x1 + 840 0076 53 .byte 0x53 + 841 0077 1C000000 .4byte .LVL6 + 842 007b 2C000000 .4byte .LFE8 + 843 007f 0500 .2byte 0x5 + 844 0081 03 .byte 0x3 + 845 0082 00000000 .4byte nextmem + 846 0086 00000000 .4byte 0 + 847 008a 00000000 .4byte 0 + 848 .LLST3: + 849 008e 00000000 .4byte .LVL7 + 850 0092 0A000000 .4byte .LVL8 + 851 0096 0100 .2byte 0x1 + 852 0098 50 .byte 0x50 + 853 0099 0A000000 .4byte .LVL8 + ARM GAS C:\cygwin\tmp\cc60iRDy.s page 16 + + + 854 009d 0E000000 .4byte .LVL9 + 855 00a1 0300 .2byte 0x3 + 856 00a3 70 .byte 0x70 + 857 00a4 79 .sleb128 -7 + 858 00a5 9F .byte 0x9f + 859 00a6 0E000000 .4byte .LVL9 + 860 00aa 16000000 .4byte .LVL11 + 861 00ae 0100 .2byte 0x1 + 862 00b0 50 .byte 0x50 + 863 00b1 16000000 .4byte .LVL11 + 864 00b5 28000000 .4byte .LFE9 + 865 00b9 0900 .2byte 0x9 + 866 00bb F3 .byte 0xf3 + 867 00bc 01 .uleb128 0x1 + 868 00bd 50 .byte 0x50 + 869 00be 23 .byte 0x23 + 870 00bf 07 .uleb128 0x7 + 871 00c0 09 .byte 0x9 + 872 00c1 F8 .byte 0xf8 + 873 00c2 1A .byte 0x1a + 874 00c3 9F .byte 0x9f + 875 00c4 00000000 .4byte 0 + 876 00c8 00000000 .4byte 0 + 877 .LLST4: + 878 00cc 12000000 .4byte .LVL10 + 879 00d0 1A000000 .4byte .LVL12 + 880 00d4 0100 .2byte 0x1 + 881 00d6 53 .byte 0x53 + 882 00d7 1A000000 .4byte .LVL12 + 883 00db 28000000 .4byte .LFE9 + 884 00df 0500 .2byte 0x5 + 885 00e1 03 .byte 0x3 + 886 00e2 00000000 .4byte nextmem + 887 00e6 00000000 .4byte 0 + 888 00ea 00000000 .4byte 0 + 889 .section .debug_aranges,"",%progbits + 890 0000 34000000 .4byte 0x34 + 891 0004 0200 .2byte 0x2 + 892 0006 00000000 .4byte .Ldebug_info0 + 893 000a 04 .byte 0x4 + 894 000b 00 .byte 0 + 895 000c 0000 .2byte 0 + 896 000e 0000 .2byte 0 + 897 0010 00000000 .4byte .LFB7 + 898 0014 2C000000 .4byte .LFE7-.LFB7 + 899 0018 00000000 .4byte .LFB8 + 900 001c 2C000000 .4byte .LFE8-.LFB8 + 901 0020 00000000 .4byte .LFB9 + 902 0024 28000000 .4byte .LFE9-.LFB9 + 903 0028 00000000 .4byte .LFB10 + 904 002c 18000000 .4byte .LFE10-.LFB10 + 905 0030 00000000 .4byte 0 + 906 0034 00000000 .4byte 0 + 907 .section .debug_ranges,"",%progbits + 908 .Ldebug_ranges0: + 909 0000 00000000 .4byte .LFB7 + 910 0004 2C000000 .4byte .LFE7 + ARM GAS C:\cygwin\tmp\cc60iRDy.s page 17 + + + 911 0008 00000000 .4byte .LFB8 + 912 000c 2C000000 .4byte .LFE8 + 913 0010 00000000 .4byte .LFB9 + 914 0014 28000000 .4byte .LFE9 + 915 0018 00000000 .4byte .LFB10 + 916 001c 18000000 .4byte .LFE10 + 917 0020 00000000 .4byte 0 + 918 0024 00000000 .4byte 0 + 919 .section .debug_line,"",%progbits + 920 .Ldebug_line0: + 921 0000 19010000 .section .debug_str,"MS",%progbits,1 + 921 0200B800 + 921 00000201 + 921 FB0E0D00 + 921 01010101 + 922 .LASF9: + 923 0000 6C6F6E67 .ascii "long long int\000" + 923 206C6F6E + 923 6720696E + 923 7400 + 924 .LASF6: + 925 000e 73686F72 .ascii "short unsigned int\000" + 925 7420756E + 925 7369676E + 925 65642069 + 925 6E7400 + 926 .LASF2: + 927 0021 73697A65 .ascii "size_t\000" + 927 5F7400 + 928 .LASF15: + 929 0028 6E657874 .ascii "nextmem\000" + 929 6D656D00 + 930 .LASF14: + 931 0030 5F5F6865 .ascii "__heap_end__\000" + 931 61705F65 + 931 6E645F5F + 931 00 + 932 .LASF13: + 933 003d 5F5F6865 .ascii "__heap_base__\000" + 933 61705F62 + 933 6173655F + 933 5F00 + 934 .LASF19: + 935 004b 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 935 73657273 + 935 5C496D61 + 935 6E6F6C5C + 935 64657665 + 936 0078 6C696361 .ascii "lications\\smartcities\000" + 936 74696F6E + 936 735C736D + 936 61727463 + 936 69746965 + 937 .LASF17: + 938 008e 474E5520 .ascii "GNU C 4.7.2\000" + 938 4320342E + 938 372E3200 + ARM GAS C:\cygwin\tmp\cc60iRDy.s page 18 + + + 939 .LASF8: + 940 009a 6C6F6E67 .ascii "long unsigned int\000" + 940 20756E73 + 940 69676E65 + 940 6420696E + 940 7400 + 941 .LASF10: + 942 00ac 6C6F6E67 .ascii "long long unsigned int\000" + 942 206C6F6E + 942 6720756E + 942 7369676E + 942 65642069 + 943 .LASF18: + 944 00c3 2E2E2F2E .ascii "../..//os/kernel/src/chmemcore.c\000" + 944 2E2F2F6F + 944 732F6B65 + 944 726E656C + 944 2F737263 + 945 .LASF3: + 946 00e4 75696E74 .ascii "uint8_t\000" + 946 385F7400 + 947 .LASF4: + 948 00ec 756E7369 .ascii "unsigned char\000" + 948 676E6564 + 948 20636861 + 948 7200 + 949 .LASF12: + 950 00fa 63686172 .ascii "char\000" + 950 00 + 951 .LASF23: + 952 00ff 6368436F .ascii "chCoreAlloc\000" + 952 7265416C + 952 6C6F6300 + 953 .LASF7: + 954 010b 6C6F6E67 .ascii "long int\000" + 954 20696E74 + 954 00 + 955 .LASF16: + 956 0114 656E646D .ascii "endmem\000" + 956 656D00 + 957 .LASF20: + 958 011b 6368436F .ascii "chCoreAllocI\000" + 958 7265416C + 958 6C6F6349 + 958 00 + 959 .LASF1: + 960 0128 7369676E .ascii "signed char\000" + 960 65642063 + 960 68617200 + 961 .LASF21: + 962 0134 73697A65 .ascii "size\000" + 962 00 + 963 .LASF22: + 964 0139 5F636F72 .ascii "_core_init\000" + 964 655F696E + 964 697400 + 965 .LASF5: + ARM GAS C:\cygwin\tmp\cc60iRDy.s page 19 + + + 966 0144 73686F72 .ascii "short int\000" + 966 7420696E + 966 7400 + 967 .LASF0: + 968 014e 756E7369 .ascii "unsigned int\000" + 968 676E6564 + 968 20696E74 + 968 00 + 969 .LASF11: + 970 015b 73697A65 .ascii "sizetype\000" + 970 74797065 + 970 00 + 971 .LASF24: + 972 0164 6368436F .ascii "chCoreStatus\000" + 972 72655374 + 972 61747573 + 972 00 + 973 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\cc60iRDy.s page 20 + + +DEFINED SYMBOLS + *ABS*:00000000 chmemcore.c +C:\cygwin\tmp\cc60iRDy.s:19 .text._core_init:00000000 $t +C:\cygwin\tmp\cc60iRDy.s:25 .text._core_init:00000000 _core_init +C:\cygwin\tmp\cc60iRDy.s:206 .bss.nextmem:00000000 .LANCHOR0 +C:\cygwin\tmp\cc60iRDy.s:199 .bss.endmem:00000000 .LANCHOR1 +C:\cygwin\tmp\cc60iRDy.s:55 .text._core_init:00000028 $d +C:\cygwin\tmp\cc60iRDy.s:60 .text.chCoreAlloc:00000000 $t +C:\cygwin\tmp\cc60iRDy.s:66 .text.chCoreAlloc:00000000 chCoreAlloc +C:\cygwin\tmp\cc60iRDy.s:117 .text.chCoreAlloc:00000024 $d +C:\cygwin\tmp\cc60iRDy.s:123 .text.chCoreAllocI:00000000 $t +C:\cygwin\tmp\cc60iRDy.s:129 .text.chCoreAllocI:00000000 chCoreAllocI +C:\cygwin\tmp\cc60iRDy.s:165 .text.chCoreAllocI:00000020 $d +C:\cygwin\tmp\cc60iRDy.s:171 .text.chCoreStatus:00000000 $t +C:\cygwin\tmp\cc60iRDy.s:177 .text.chCoreStatus:00000000 chCoreStatus +C:\cygwin\tmp\cc60iRDy.s:198 .bss.endmem:00000000 $d +C:\cygwin\tmp\cc60iRDy.s:202 .bss.endmem:00000000 endmem +C:\cygwin\tmp\cc60iRDy.s:205 .bss.nextmem:00000000 $d +C:\cygwin\tmp\cc60iRDy.s:209 .bss.nextmem:00000000 nextmem + .debug_frame:00000010 $d +C:\cygwin\tmp\cc60iRDy.s:59 .text._core_init:0000002c $t +C:\cygwin\tmp\cc60iRDy.s:122 .text.chCoreAlloc:0000002c $t +C:\cygwin\tmp\cc60iRDy.s:170 .text.chCoreAllocI:00000028 $t + +UNDEFINED SYMBOLS +__heap_end__ +__heap_base__ diff --git a/Project/applications/smartcities/build/lst/chmempools.lst b/Project/applications/smartcities/build/lst/chmempools.lst new file mode 100644 index 0000000..afb12d7 --- /dev/null +++ b/Project/applications/smartcities/build/lst/chmempools.lst @@ -0,0 +1,1492 @@ +ARM GAS C:\cygwin\tmp\ccqnx457.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "chmempools.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text.chPoolInit,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .global chPoolInit + 22 .thumb + 23 .thumb_func + 24 .type chPoolInit, %function + 25 chPoolInit: + 26 .LFB7: + 27 .file 1 "../..//os/kernel/src/chmempools.c" + 28 .loc 1 61 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .LVL0: + 34 .loc 1 66 0 + 35 0000 0731 adds r1, r1, #7 + 36 .LVL1: + 37 0002 21F00701 bic r1, r1, #7 + 38 .LVL2: + 39 .loc 1 65 0 + 40 0006 0023 movs r3, #0 + 41 0008 0360 str r3, [r0, #0] + 42 .loc 1 66 0 + 43 000a 4160 str r1, [r0, #4] + 44 .loc 1 67 0 + 45 000c 8260 str r2, [r0, #8] + 46 000e 7047 bx lr + 47 .cfi_endproc + 48 .LFE7: + 49 .size chPoolInit, .-chPoolInit + 50 .section .text.chPoolAllocI,"ax",%progbits + 51 .align 2 + 52 .p2align 4,,15 + 53 .global chPoolAllocI + 54 .thumb + 55 .thumb_func + 56 .type chPoolAllocI, %function + 57 chPoolAllocI: + ARM GAS C:\cygwin\tmp\ccqnx457.s page 2 + + + 58 .LFB8: + 59 .loc 1 79 0 + 60 .cfi_startproc + 61 @ args = 0, pretend = 0, frame = 0 + 62 @ frame_needed = 0, uses_anonymous_args = 0 + 63 .LVL3: + 64 0000 08B5 push {r3, lr} + 65 .LCFI0: + 66 .cfi_def_cfa_offset 8 + 67 .cfi_offset 3, -8 + 68 .cfi_offset 14, -4 + 69 .loc 1 79 0 + 70 0002 0346 mov r3, r0 + 71 .loc 1 85 0 + 72 0004 0068 ldr r0, [r0, #0] + 73 .LVL4: + 74 0006 10B1 cbz r0, .L3 + 75 .loc 1 86 0 + 76 0008 0268 ldr r2, [r0, #0] + 77 000a 1A60 str r2, [r3, #0] + 78 000c 08BD pop {r3, pc} + 79 .L3: + 80 .loc 1 87 0 + 81 000e 9A68 ldr r2, [r3, #8] + 82 0010 0AB1 cbz r2, .L4 + 83 .loc 1 88 0 + 84 0012 5868 ldr r0, [r3, #4] + 85 .LVL5: + 86 0014 9047 blx r2 + 87 .LVL6: + 88 .L4: + 89 .loc 1 90 0 + 90 0016 08BD pop {r3, pc} + 91 .cfi_endproc + 92 .LFE8: + 93 .size chPoolAllocI, .-chPoolAllocI + 94 0018 AFF30080 .section .text.chPoolAlloc,"ax",%progbits + 94 AFF30080 + 95 .align 2 + 96 .p2align 4,,15 + 97 .global chPoolAlloc + 98 .thumb + 99 .thumb_func + 100 .type chPoolAlloc, %function + 101 chPoolAlloc: + 102 .LFB9: + 103 .loc 1 101 0 + 104 .cfi_startproc + 105 @ args = 0, pretend = 0, frame = 0 + 106 @ frame_needed = 0, uses_anonymous_args = 0 + 107 .LVL7: + 108 0000 08B5 push {r3, lr} + 109 .LCFI1: + 110 .cfi_def_cfa_offset 8 + 111 .cfi_offset 3, -8 + 112 .cfi_offset 14, -4 + 113 .loc 1 101 0 + ARM GAS C:\cygwin\tmp\ccqnx457.s page 3 + + + 114 0002 0346 mov r3, r0 + 115 .loc 1 104 0 + 116 @ 104 "../..//os/kernel/src/chmempools.c" 1 + 117 0004 72B6 cpsid i + 118 @ 0 "" 2 + 119 .LVL8: + 120 .thumb + 121 .LBB6: + 122 .LBB7: + 123 .loc 1 85 0 + 124 0006 0068 ldr r0, [r0, #0] + 125 .LVL9: + 126 0008 18B1 cbz r0, .L10 + 127 .loc 1 86 0 + 128 000a 0268 ldr r2, [r0, #0] + 129 000c 1A60 str r2, [r3, #0] + 130 .L11: + 131 .LBE7: + 132 .LBE6: + 133 .loc 1 106 0 + 134 @ 106 "../..//os/kernel/src/chmempools.c" 1 + 135 000e 62B6 cpsie i + 136 @ 0 "" 2 + 137 .loc 1 108 0 + 138 .thumb + 139 0010 08BD pop {r3, pc} + 140 .L10: + 141 .LBB9: + 142 .LBB8: + 143 .loc 1 87 0 + 144 0012 9A68 ldr r2, [r3, #8] + 145 0014 002A cmp r2, #0 + 146 0016 FAD0 beq .L11 + 147 .loc 1 88 0 + 148 0018 5868 ldr r0, [r3, #4] + 149 .LVL10: + 150 001a 9047 blx r2 + 151 .LVL11: + 152 .LBE8: + 153 .LBE9: + 154 .loc 1 106 0 + 155 @ 106 "../..//os/kernel/src/chmempools.c" 1 + 156 001c 62B6 cpsie i + 157 @ 0 "" 2 + 158 .loc 1 108 0 + 159 .thumb + 160 001e 08BD pop {r3, pc} + 161 .cfi_endproc + 162 .LFE9: + 163 .size chPoolAlloc, .-chPoolAlloc + 164 .section .text.chPoolFreeI,"ax",%progbits + 165 .align 2 + 166 .p2align 4,,15 + 167 .global chPoolFreeI + 168 .thumb + 169 .thumb_func + 170 .type chPoolFreeI, %function + ARM GAS C:\cygwin\tmp\ccqnx457.s page 4 + + + 171 chPoolFreeI: + 172 .LFB10: + 173 .loc 1 122 0 + 174 .cfi_startproc + 175 @ args = 0, pretend = 0, frame = 0 + 176 @ frame_needed = 0, uses_anonymous_args = 0 + 177 @ link register save eliminated. + 178 .LVL12: + 179 .loc 1 129 0 + 180 0000 0368 ldr r3, [r0, #0] + 181 .LVL13: + 182 0002 0B60 str r3, [r1, #0] + 183 .loc 1 130 0 + 184 0004 0160 str r1, [r0, #0] + 185 0006 7047 bx lr + 186 .cfi_endproc + 187 .LFE10: + 188 .size chPoolFreeI, .-chPoolFreeI + 189 0008 AFF30080 .section .text.chPoolFree,"ax",%progbits + 189 AFF30080 + 190 .align 2 + 191 .p2align 4,,15 + 192 .global chPoolFree + 193 .thumb + 194 .thumb_func + 195 .type chPoolFree, %function + 196 chPoolFree: + 197 .LFB11: + 198 .loc 1 145 0 + 199 .cfi_startproc + 200 @ args = 0, pretend = 0, frame = 0 + 201 @ frame_needed = 0, uses_anonymous_args = 0 + 202 @ link register save eliminated. + 203 .LVL14: + 204 .loc 1 147 0 + 205 @ 147 "../..//os/kernel/src/chmempools.c" 1 + 206 0000 72B6 cpsid i + 207 @ 0 "" 2 + 208 .LVL15: + 209 .thumb + 210 .LBB10: + 211 .LBB11: + 212 .loc 1 129 0 + 213 0002 0368 ldr r3, [r0, #0] + 214 0004 0B60 str r3, [r1, #0] + 215 .loc 1 130 0 + 216 0006 0160 str r1, [r0, #0] + 217 .LBE11: + 218 .LBE10: + 219 .loc 1 149 0 + 220 @ 149 "../..//os/kernel/src/chmempools.c" 1 + 221 0008 62B6 cpsie i + 222 @ 0 "" 2 + 223 .thumb + 224 000a 7047 bx lr + 225 .cfi_endproc + 226 .LFE11: + ARM GAS C:\cygwin\tmp\ccqnx457.s page 5 + + + 227 .size chPoolFree, .-chPoolFree + 228 000c AFF30080 .text + 229 .Letext0: + 230 .file 2 "c:\\yagarto\\bin\\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h" + 231 .file 3 "../..//os/kernel/include/chmemcore.h" + 232 .file 4 "../..//os/kernel/include/chmempools.h" + 233 .section .debug_info,"",%progbits + 234 .Ldebug_info0: + 235 0000 BA020000 .4byte 0x2ba + 236 0004 0200 .2byte 0x2 + 237 0006 00000000 .4byte .Ldebug_abbrev0 + 238 000a 04 .byte 0x4 + 239 000b 01 .uleb128 0x1 + 240 000c 22010000 .4byte .LASF21 + 241 0010 01 .byte 0x1 + 242 0011 5D010000 .4byte .LASF22 + 243 0015 00000000 .4byte .LASF23 + 244 0019 30000000 .4byte .Ldebug_ranges0+0x30 + 245 001d 00000000 .4byte 0 + 246 0021 00000000 .4byte 0 + 247 0025 00000000 .4byte .Ldebug_line0 + 248 0029 02 .uleb128 0x2 + 249 002a 04 .byte 0x4 + 250 002b 05 .byte 0x5 + 251 002c 696E7400 .ascii "int\000" + 252 0030 03 .uleb128 0x3 + 253 0031 43000000 .4byte .LASF10 + 254 0035 02 .byte 0x2 + 255 0036 D5 .byte 0xd5 + 256 0037 3B000000 .4byte 0x3b + 257 003b 04 .uleb128 0x4 + 258 003c 04 .byte 0x4 + 259 003d 07 .byte 0x7 + 260 003e DA000000 .4byte .LASF0 + 261 0042 04 .uleb128 0x4 + 262 0043 01 .byte 0x1 + 263 0044 06 .byte 0x6 + 264 0045 88010000 .4byte .LASF1 + 265 0049 04 .uleb128 0x4 + 266 004a 01 .byte 0x1 + 267 004b 08 .byte 0x8 + 268 004c A4000000 .4byte .LASF2 + 269 0050 04 .uleb128 0x4 + 270 0051 02 .byte 0x2 + 271 0052 05 .byte 0x5 + 272 0053 47010000 .4byte .LASF3 + 273 0057 04 .uleb128 0x4 + 274 0058 02 .byte 0x2 + 275 0059 07 .byte 0x7 + 276 005a 7C000000 .4byte .LASF4 + 277 005e 04 .uleb128 0x4 + 278 005f 04 .byte 0x4 + 279 0060 05 .byte 0x5 + 280 0061 7F010000 .4byte .LASF5 + 281 0065 04 .uleb128 0x4 + 282 0066 04 .byte 0x4 + 283 0067 07 .byte 0x7 + ARM GAS C:\cygwin\tmp\ccqnx457.s page 6 + + + 284 0068 6A000000 .4byte .LASF6 + 285 006c 04 .uleb128 0x4 + 286 006d 08 .byte 0x8 + 287 006e 05 .byte 0x5 + 288 006f 0F010000 .4byte .LASF7 + 289 0073 04 .uleb128 0x4 + 290 0074 08 .byte 0x8 + 291 0075 07 .byte 0x7 + 292 0076 E7000000 .4byte .LASF8 + 293 007a 05 .uleb128 0x5 + 294 007b 04 .byte 0x4 + 295 007c 04 .uleb128 0x4 + 296 007d 04 .byte 0x4 + 297 007e 07 .byte 0x7 + 298 007f 06010000 .4byte .LASF9 + 299 0083 03 .uleb128 0x3 + 300 0084 2E010000 .4byte .LASF11 + 301 0088 03 .byte 0x3 + 302 0089 2C .byte 0x2c + 303 008a 8E000000 .4byte 0x8e + 304 008e 06 .uleb128 0x6 + 305 008f 04 .byte 0x4 + 306 0090 94000000 .4byte 0x94 + 307 0094 07 .uleb128 0x7 + 308 0095 01 .byte 0x1 + 309 0096 7A000000 .4byte 0x7a + 310 009a A4000000 .4byte 0xa4 + 311 009e 08 .uleb128 0x8 + 312 009f 30000000 .4byte 0x30 + 313 00a3 00 .byte 0 + 314 00a4 09 .uleb128 0x9 + 315 00a5 59000000 .4byte .LASF24 + 316 00a9 04 .byte 0x4 + 317 00aa 04 .byte 0x4 + 318 00ab 2C .byte 0x2c + 319 00ac BF000000 .4byte 0xbf + 320 00b0 0A .uleb128 0xa + 321 00b1 FE000000 .4byte .LASF12 + 322 00b5 04 .byte 0x4 + 323 00b6 2D .byte 0x2d + 324 00b7 BF000000 .4byte 0xbf + 325 00bb 02 .byte 0x2 + 326 00bc 23 .byte 0x23 + 327 00bd 00 .uleb128 0 + 328 00be 00 .byte 0 + 329 00bf 06 .uleb128 0x6 + 330 00c0 04 .byte 0x4 + 331 00c1 A4000000 .4byte 0xa4 + 332 00c5 0B .uleb128 0xb + 333 00c6 0C .byte 0xc + 334 00c7 04 .byte 0x4 + 335 00c8 34 .byte 0x34 + 336 00c9 F8000000 .4byte 0xf8 + 337 00cd 0A .uleb128 0xa + 338 00ce 94010000 .4byte .LASF13 + 339 00d2 04 .byte 0x4 + 340 00d3 35 .byte 0x35 + ARM GAS C:\cygwin\tmp\ccqnx457.s page 7 + + + 341 00d4 BF000000 .4byte 0xbf + 342 00d8 02 .byte 0x2 + 343 00d9 23 .byte 0x23 + 344 00da 00 .uleb128 0 + 345 00db 0A .uleb128 0xa + 346 00dc 4A000000 .4byte .LASF14 + 347 00e0 04 .byte 0x4 + 348 00e1 36 .byte 0x36 + 349 00e2 30000000 .4byte 0x30 + 350 00e6 02 .byte 0x2 + 351 00e7 23 .byte 0x23 + 352 00e8 04 .uleb128 0x4 + 353 00e9 0A .uleb128 0xa + 354 00ea 3B010000 .4byte .LASF15 + 355 00ee 04 .byte 0x4 + 356 00ef 38 .byte 0x38 + 357 00f0 83000000 .4byte 0x83 + 358 00f4 02 .byte 0x2 + 359 00f5 23 .byte 0x23 + 360 00f6 08 .uleb128 0x8 + 361 00f7 00 .byte 0 + 362 00f8 03 .uleb128 0x3 + 363 00f9 BD000000 .4byte .LASF16 + 364 00fd 04 .byte 0x4 + 365 00fe 3A .byte 0x3a + 366 00ff C5000000 .4byte 0xc5 + 367 0103 04 .uleb128 0x4 + 368 0104 01 .byte 0x1 + 369 0105 08 .byte 0x8 + 370 0106 1D010000 .4byte .LASF17 + 371 010a 0C .uleb128 0xc + 372 010b 01 .byte 0x1 + 373 010c CD000000 .4byte .LASF25 + 374 0110 01 .byte 0x1 + 375 0111 4F .byte 0x4f + 376 0112 01 .byte 0x1 + 377 0113 7A000000 .4byte 0x7a + 378 0117 01 .byte 0x1 + 379 0118 32010000 .4byte 0x132 + 380 011c 0D .uleb128 0xd + 381 011d 6D7000 .ascii "mp\000" + 382 0120 01 .byte 0x1 + 383 0121 4F .byte 0x4f + 384 0122 32010000 .4byte 0x132 + 385 0126 0E .uleb128 0xe + 386 0127 C8000000 .4byte .LASF18 + 387 012b 01 .byte 0x1 + 388 012c 50 .byte 0x50 + 389 012d 7A000000 .4byte 0x7a + 390 0131 00 .byte 0 + 391 0132 06 .uleb128 0x6 + 392 0133 04 .byte 0x4 + 393 0134 F8000000 .4byte 0xf8 + 394 0138 0F .uleb128 0xf + 395 0139 01 .byte 0x1 + 396 013a 98000000 .4byte .LASF26 + 397 013e 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccqnx457.s page 8 + + + 398 013f 7A .byte 0x7a + 399 0140 01 .byte 0x1 + 400 0141 01 .byte 0x1 + 401 0142 67010000 .4byte 0x167 + 402 0146 0D .uleb128 0xd + 403 0147 6D7000 .ascii "mp\000" + 404 014a 01 .byte 0x1 + 405 014b 7A .byte 0x7a + 406 014c 32010000 .4byte 0x132 + 407 0150 10 .uleb128 0x10 + 408 0151 C8000000 .4byte .LASF18 + 409 0155 01 .byte 0x1 + 410 0156 7A .byte 0x7a + 411 0157 7A000000 .4byte 0x7a + 412 015b 11 .uleb128 0x11 + 413 015c 70687000 .ascii "php\000" + 414 0160 01 .byte 0x1 + 415 0161 7B .byte 0x7b + 416 0162 BF000000 .4byte 0xbf + 417 0166 00 .byte 0 + 418 0167 12 .uleb128 0x12 + 419 0168 01 .byte 0x1 + 420 0169 9C010000 .4byte .LASF27 + 421 016d 01 .byte 0x1 + 422 016e 3D .byte 0x3d + 423 016f 01 .byte 0x1 + 424 0170 00000000 .4byte .LFB7 + 425 0174 10000000 .4byte .LFE7 + 426 0178 02 .byte 0x2 + 427 0179 7D .byte 0x7d + 428 017a 00 .sleb128 0 + 429 017b 01 .byte 0x1 + 430 017c A9010000 .4byte 0x1a9 + 431 0180 13 .uleb128 0x13 + 432 0181 6D7000 .ascii "mp\000" + 433 0184 01 .byte 0x1 + 434 0185 3D .byte 0x3d + 435 0186 32010000 .4byte 0x132 + 436 018a 01 .byte 0x1 + 437 018b 50 .byte 0x50 + 438 018c 14 .uleb128 0x14 + 439 018d 65000000 .4byte .LASF19 + 440 0191 01 .byte 0x1 + 441 0192 3D .byte 0x3d + 442 0193 30000000 .4byte 0x30 + 443 0197 00000000 .4byte .LLST0 + 444 019b 15 .uleb128 0x15 + 445 019c 8F000000 .4byte .LASF20 + 446 01a0 01 .byte 0x1 + 447 01a1 3D .byte 0x3d + 448 01a2 83000000 .4byte 0x83 + 449 01a6 01 .byte 0x1 + 450 01a7 52 .byte 0x52 + 451 01a8 00 .byte 0 + 452 01a9 16 .uleb128 0x16 + 453 01aa 0A010000 .4byte 0x10a + 454 01ae 00000000 .4byte .LFB8 + ARM GAS C:\cygwin\tmp\ccqnx457.s page 9 + + + 455 01b2 18000000 .4byte .LFE8 + 456 01b6 2E000000 .4byte .LLST1 + 457 01ba 01 .byte 0x1 + 458 01bb D2010000 .4byte 0x1d2 + 459 01bf 17 .uleb128 0x17 + 460 01c0 1C010000 .4byte 0x11c + 461 01c4 4E000000 .4byte .LLST2 + 462 01c8 18 .uleb128 0x18 + 463 01c9 26010000 .4byte 0x126 + 464 01cd 7A000000 .4byte .LLST3 + 465 01d1 00 .byte 0 + 466 01d2 19 .uleb128 0x19 + 467 01d3 01 .byte 0x1 + 468 01d4 51010000 .4byte .LASF28 + 469 01d8 01 .byte 0x1 + 470 01d9 65 .byte 0x65 + 471 01da 01 .byte 0x1 + 472 01db 7A000000 .4byte 0x7a + 473 01df 00000000 .4byte .LFB9 + 474 01e3 20000000 .4byte .LFE9 + 475 01e7 A4000000 .4byte .LLST4 + 476 01eb 01 .byte 0x1 + 477 01ec 34020000 .4byte 0x234 + 478 01f0 1A .uleb128 0x1a + 479 01f1 6D7000 .ascii "mp\000" + 480 01f4 01 .byte 0x1 + 481 01f5 65 .byte 0x65 + 482 01f6 32010000 .4byte 0x132 + 483 01fa C4000000 .4byte .LLST5 + 484 01fe 1B .uleb128 0x1b + 485 01ff C8000000 .4byte .LASF18 + 486 0203 01 .byte 0x1 + 487 0204 66 .byte 0x66 + 488 0205 7A000000 .4byte 0x7a + 489 0209 01 .byte 0x1 + 490 020a 50 .byte 0x50 + 491 020b 1C .uleb128 0x1c + 492 020c 0A010000 .4byte 0x10a + 493 0210 06000000 .4byte .LBB6 + 494 0214 00000000 .4byte .Ldebug_ranges0+0 + 495 0218 01 .byte 0x1 + 496 0219 69 .byte 0x69 + 497 021a 17 .uleb128 0x17 + 498 021b 1C010000 .4byte 0x11c + 499 021f F0000000 .4byte .LLST6 + 500 0223 1D .uleb128 0x1d + 501 0224 18000000 .4byte .Ldebug_ranges0+0x18 + 502 0228 18 .uleb128 0x18 + 503 0229 26010000 .4byte 0x126 + 504 022d 1C010000 .4byte .LLST7 + 505 0231 00 .byte 0 + 506 0232 00 .byte 0 + 507 0233 00 .byte 0 + 508 0234 1E .uleb128 0x1e + 509 0235 38010000 .4byte 0x138 + 510 0239 00000000 .4byte .LFB10 + 511 023d 08000000 .4byte .LFE10 + ARM GAS C:\cygwin\tmp\ccqnx457.s page 10 + + + 512 0241 02 .byte 0x2 + 513 0242 7D .byte 0x7d + 514 0243 00 .sleb128 0 + 515 0244 01 .byte 0x1 + 516 0245 5F020000 .4byte 0x25f + 517 0249 1F .uleb128 0x1f + 518 024a 46010000 .4byte 0x146 + 519 024e 01 .byte 0x1 + 520 024f 50 .byte 0x50 + 521 0250 1F .uleb128 0x1f + 522 0251 50010000 .4byte 0x150 + 523 0255 01 .byte 0x1 + 524 0256 51 .byte 0x51 + 525 0257 20 .uleb128 0x20 + 526 0258 5B010000 .4byte 0x15b + 527 025c 01 .byte 0x1 + 528 025d 51 .byte 0x51 + 529 025e 00 .byte 0 + 530 025f 21 .uleb128 0x21 + 531 0260 01 .byte 0x1 + 532 0261 B2000000 .4byte .LASF29 + 533 0265 01 .byte 0x1 + 534 0266 91 .byte 0x91 + 535 0267 01 .byte 0x1 + 536 0268 00000000 .4byte .LFB11 + 537 026c 0C000000 .4byte .LFE11 + 538 0270 02 .byte 0x2 + 539 0271 7D .byte 0x7d + 540 0272 00 .sleb128 0 + 541 0273 01 .byte 0x1 + 542 0274 13 .uleb128 0x13 + 543 0275 6D7000 .ascii "mp\000" + 544 0278 01 .byte 0x1 + 545 0279 91 .byte 0x91 + 546 027a 32010000 .4byte 0x132 + 547 027e 01 .byte 0x1 + 548 027f 50 .byte 0x50 + 549 0280 15 .uleb128 0x15 + 550 0281 C8000000 .4byte .LASF18 + 551 0285 01 .byte 0x1 + 552 0286 91 .byte 0x91 + 553 0287 7A000000 .4byte 0x7a + 554 028b 01 .byte 0x1 + 555 028c 51 .byte 0x51 + 556 028d 22 .uleb128 0x22 + 557 028e 38010000 .4byte 0x138 + 558 0292 02000000 .4byte .LBB10 + 559 0296 08000000 .4byte .LBE10 + 560 029a 01 .byte 0x1 + 561 029b 94 .byte 0x94 + 562 029c 1F .uleb128 0x1f + 563 029d 50010000 .4byte 0x150 + 564 02a1 01 .byte 0x1 + 565 02a2 51 .byte 0x51 + 566 02a3 1F .uleb128 0x1f + 567 02a4 46010000 .4byte 0x146 + 568 02a8 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccqnx457.s page 11 + + + 569 02a9 50 .byte 0x50 + 570 02aa 23 .uleb128 0x23 + 571 02ab 02000000 .4byte .LBB11 + 572 02af 08000000 .4byte .LBE11 + 573 02b3 20 .uleb128 0x20 + 574 02b4 5B010000 .4byte 0x15b + 575 02b8 01 .byte 0x1 + 576 02b9 51 .byte 0x51 + 577 02ba 00 .byte 0 + 578 02bb 00 .byte 0 + 579 02bc 00 .byte 0 + 580 02bd 00 .byte 0 + 581 .section .debug_abbrev,"",%progbits + 582 .Ldebug_abbrev0: + 583 0000 01 .uleb128 0x1 + 584 0001 11 .uleb128 0x11 + 585 0002 01 .byte 0x1 + 586 0003 25 .uleb128 0x25 + 587 0004 0E .uleb128 0xe + 588 0005 13 .uleb128 0x13 + 589 0006 0B .uleb128 0xb + 590 0007 03 .uleb128 0x3 + 591 0008 0E .uleb128 0xe + 592 0009 1B .uleb128 0x1b + 593 000a 0E .uleb128 0xe + 594 000b 55 .uleb128 0x55 + 595 000c 06 .uleb128 0x6 + 596 000d 11 .uleb128 0x11 + 597 000e 01 .uleb128 0x1 + 598 000f 52 .uleb128 0x52 + 599 0010 01 .uleb128 0x1 + 600 0011 10 .uleb128 0x10 + 601 0012 06 .uleb128 0x6 + 602 0013 00 .byte 0 + 603 0014 00 .byte 0 + 604 0015 02 .uleb128 0x2 + 605 0016 24 .uleb128 0x24 + 606 0017 00 .byte 0 + 607 0018 0B .uleb128 0xb + 608 0019 0B .uleb128 0xb + 609 001a 3E .uleb128 0x3e + 610 001b 0B .uleb128 0xb + 611 001c 03 .uleb128 0x3 + 612 001d 08 .uleb128 0x8 + 613 001e 00 .byte 0 + 614 001f 00 .byte 0 + 615 0020 03 .uleb128 0x3 + 616 0021 16 .uleb128 0x16 + 617 0022 00 .byte 0 + 618 0023 03 .uleb128 0x3 + 619 0024 0E .uleb128 0xe + 620 0025 3A .uleb128 0x3a + 621 0026 0B .uleb128 0xb + 622 0027 3B .uleb128 0x3b + 623 0028 0B .uleb128 0xb + 624 0029 49 .uleb128 0x49 + 625 002a 13 .uleb128 0x13 + ARM GAS C:\cygwin\tmp\ccqnx457.s page 12 + + + 626 002b 00 .byte 0 + 627 002c 00 .byte 0 + 628 002d 04 .uleb128 0x4 + 629 002e 24 .uleb128 0x24 + 630 002f 00 .byte 0 + 631 0030 0B .uleb128 0xb + 632 0031 0B .uleb128 0xb + 633 0032 3E .uleb128 0x3e + 634 0033 0B .uleb128 0xb + 635 0034 03 .uleb128 0x3 + 636 0035 0E .uleb128 0xe + 637 0036 00 .byte 0 + 638 0037 00 .byte 0 + 639 0038 05 .uleb128 0x5 + 640 0039 0F .uleb128 0xf + 641 003a 00 .byte 0 + 642 003b 0B .uleb128 0xb + 643 003c 0B .uleb128 0xb + 644 003d 00 .byte 0 + 645 003e 00 .byte 0 + 646 003f 06 .uleb128 0x6 + 647 0040 0F .uleb128 0xf + 648 0041 00 .byte 0 + 649 0042 0B .uleb128 0xb + 650 0043 0B .uleb128 0xb + 651 0044 49 .uleb128 0x49 + 652 0045 13 .uleb128 0x13 + 653 0046 00 .byte 0 + 654 0047 00 .byte 0 + 655 0048 07 .uleb128 0x7 + 656 0049 15 .uleb128 0x15 + 657 004a 01 .byte 0x1 + 658 004b 27 .uleb128 0x27 + 659 004c 0C .uleb128 0xc + 660 004d 49 .uleb128 0x49 + 661 004e 13 .uleb128 0x13 + 662 004f 01 .uleb128 0x1 + 663 0050 13 .uleb128 0x13 + 664 0051 00 .byte 0 + 665 0052 00 .byte 0 + 666 0053 08 .uleb128 0x8 + 667 0054 05 .uleb128 0x5 + 668 0055 00 .byte 0 + 669 0056 49 .uleb128 0x49 + 670 0057 13 .uleb128 0x13 + 671 0058 00 .byte 0 + 672 0059 00 .byte 0 + 673 005a 09 .uleb128 0x9 + 674 005b 13 .uleb128 0x13 + 675 005c 01 .byte 0x1 + 676 005d 03 .uleb128 0x3 + 677 005e 0E .uleb128 0xe + 678 005f 0B .uleb128 0xb + 679 0060 0B .uleb128 0xb + 680 0061 3A .uleb128 0x3a + 681 0062 0B .uleb128 0xb + 682 0063 3B .uleb128 0x3b + ARM GAS C:\cygwin\tmp\ccqnx457.s page 13 + + + 683 0064 0B .uleb128 0xb + 684 0065 01 .uleb128 0x1 + 685 0066 13 .uleb128 0x13 + 686 0067 00 .byte 0 + 687 0068 00 .byte 0 + 688 0069 0A .uleb128 0xa + 689 006a 0D .uleb128 0xd + 690 006b 00 .byte 0 + 691 006c 03 .uleb128 0x3 + 692 006d 0E .uleb128 0xe + 693 006e 3A .uleb128 0x3a + 694 006f 0B .uleb128 0xb + 695 0070 3B .uleb128 0x3b + 696 0071 0B .uleb128 0xb + 697 0072 49 .uleb128 0x49 + 698 0073 13 .uleb128 0x13 + 699 0074 38 .uleb128 0x38 + 700 0075 0A .uleb128 0xa + 701 0076 00 .byte 0 + 702 0077 00 .byte 0 + 703 0078 0B .uleb128 0xb + 704 0079 13 .uleb128 0x13 + 705 007a 01 .byte 0x1 + 706 007b 0B .uleb128 0xb + 707 007c 0B .uleb128 0xb + 708 007d 3A .uleb128 0x3a + 709 007e 0B .uleb128 0xb + 710 007f 3B .uleb128 0x3b + 711 0080 0B .uleb128 0xb + 712 0081 01 .uleb128 0x1 + 713 0082 13 .uleb128 0x13 + 714 0083 00 .byte 0 + 715 0084 00 .byte 0 + 716 0085 0C .uleb128 0xc + 717 0086 2E .uleb128 0x2e + 718 0087 01 .byte 0x1 + 719 0088 3F .uleb128 0x3f + 720 0089 0C .uleb128 0xc + 721 008a 03 .uleb128 0x3 + 722 008b 0E .uleb128 0xe + 723 008c 3A .uleb128 0x3a + 724 008d 0B .uleb128 0xb + 725 008e 3B .uleb128 0x3b + 726 008f 0B .uleb128 0xb + 727 0090 27 .uleb128 0x27 + 728 0091 0C .uleb128 0xc + 729 0092 49 .uleb128 0x49 + 730 0093 13 .uleb128 0x13 + 731 0094 20 .uleb128 0x20 + 732 0095 0B .uleb128 0xb + 733 0096 01 .uleb128 0x1 + 734 0097 13 .uleb128 0x13 + 735 0098 00 .byte 0 + 736 0099 00 .byte 0 + 737 009a 0D .uleb128 0xd + 738 009b 05 .uleb128 0x5 + 739 009c 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccqnx457.s page 14 + + + 740 009d 03 .uleb128 0x3 + 741 009e 08 .uleb128 0x8 + 742 009f 3A .uleb128 0x3a + 743 00a0 0B .uleb128 0xb + 744 00a1 3B .uleb128 0x3b + 745 00a2 0B .uleb128 0xb + 746 00a3 49 .uleb128 0x49 + 747 00a4 13 .uleb128 0x13 + 748 00a5 00 .byte 0 + 749 00a6 00 .byte 0 + 750 00a7 0E .uleb128 0xe + 751 00a8 34 .uleb128 0x34 + 752 00a9 00 .byte 0 + 753 00aa 03 .uleb128 0x3 + 754 00ab 0E .uleb128 0xe + 755 00ac 3A .uleb128 0x3a + 756 00ad 0B .uleb128 0xb + 757 00ae 3B .uleb128 0x3b + 758 00af 0B .uleb128 0xb + 759 00b0 49 .uleb128 0x49 + 760 00b1 13 .uleb128 0x13 + 761 00b2 00 .byte 0 + 762 00b3 00 .byte 0 + 763 00b4 0F .uleb128 0xf + 764 00b5 2E .uleb128 0x2e + 765 00b6 01 .byte 0x1 + 766 00b7 3F .uleb128 0x3f + 767 00b8 0C .uleb128 0xc + 768 00b9 03 .uleb128 0x3 + 769 00ba 0E .uleb128 0xe + 770 00bb 3A .uleb128 0x3a + 771 00bc 0B .uleb128 0xb + 772 00bd 3B .uleb128 0x3b + 773 00be 0B .uleb128 0xb + 774 00bf 27 .uleb128 0x27 + 775 00c0 0C .uleb128 0xc + 776 00c1 20 .uleb128 0x20 + 777 00c2 0B .uleb128 0xb + 778 00c3 01 .uleb128 0x1 + 779 00c4 13 .uleb128 0x13 + 780 00c5 00 .byte 0 + 781 00c6 00 .byte 0 + 782 00c7 10 .uleb128 0x10 + 783 00c8 05 .uleb128 0x5 + 784 00c9 00 .byte 0 + 785 00ca 03 .uleb128 0x3 + 786 00cb 0E .uleb128 0xe + 787 00cc 3A .uleb128 0x3a + 788 00cd 0B .uleb128 0xb + 789 00ce 3B .uleb128 0x3b + 790 00cf 0B .uleb128 0xb + 791 00d0 49 .uleb128 0x49 + 792 00d1 13 .uleb128 0x13 + 793 00d2 00 .byte 0 + 794 00d3 00 .byte 0 + 795 00d4 11 .uleb128 0x11 + 796 00d5 34 .uleb128 0x34 + ARM GAS C:\cygwin\tmp\ccqnx457.s page 15 + + + 797 00d6 00 .byte 0 + 798 00d7 03 .uleb128 0x3 + 799 00d8 08 .uleb128 0x8 + 800 00d9 3A .uleb128 0x3a + 801 00da 0B .uleb128 0xb + 802 00db 3B .uleb128 0x3b + 803 00dc 0B .uleb128 0xb + 804 00dd 49 .uleb128 0x49 + 805 00de 13 .uleb128 0x13 + 806 00df 00 .byte 0 + 807 00e0 00 .byte 0 + 808 00e1 12 .uleb128 0x12 + 809 00e2 2E .uleb128 0x2e + 810 00e3 01 .byte 0x1 + 811 00e4 3F .uleb128 0x3f + 812 00e5 0C .uleb128 0xc + 813 00e6 03 .uleb128 0x3 + 814 00e7 0E .uleb128 0xe + 815 00e8 3A .uleb128 0x3a + 816 00e9 0B .uleb128 0xb + 817 00ea 3B .uleb128 0x3b + 818 00eb 0B .uleb128 0xb + 819 00ec 27 .uleb128 0x27 + 820 00ed 0C .uleb128 0xc + 821 00ee 11 .uleb128 0x11 + 822 00ef 01 .uleb128 0x1 + 823 00f0 12 .uleb128 0x12 + 824 00f1 01 .uleb128 0x1 + 825 00f2 40 .uleb128 0x40 + 826 00f3 0A .uleb128 0xa + 827 00f4 9742 .uleb128 0x2117 + 828 00f6 0C .uleb128 0xc + 829 00f7 01 .uleb128 0x1 + 830 00f8 13 .uleb128 0x13 + 831 00f9 00 .byte 0 + 832 00fa 00 .byte 0 + 833 00fb 13 .uleb128 0x13 + 834 00fc 05 .uleb128 0x5 + 835 00fd 00 .byte 0 + 836 00fe 03 .uleb128 0x3 + 837 00ff 08 .uleb128 0x8 + 838 0100 3A .uleb128 0x3a + 839 0101 0B .uleb128 0xb + 840 0102 3B .uleb128 0x3b + 841 0103 0B .uleb128 0xb + 842 0104 49 .uleb128 0x49 + 843 0105 13 .uleb128 0x13 + 844 0106 02 .uleb128 0x2 + 845 0107 0A .uleb128 0xa + 846 0108 00 .byte 0 + 847 0109 00 .byte 0 + 848 010a 14 .uleb128 0x14 + 849 010b 05 .uleb128 0x5 + 850 010c 00 .byte 0 + 851 010d 03 .uleb128 0x3 + 852 010e 0E .uleb128 0xe + 853 010f 3A .uleb128 0x3a + ARM GAS C:\cygwin\tmp\ccqnx457.s page 16 + + + 854 0110 0B .uleb128 0xb + 855 0111 3B .uleb128 0x3b + 856 0112 0B .uleb128 0xb + 857 0113 49 .uleb128 0x49 + 858 0114 13 .uleb128 0x13 + 859 0115 02 .uleb128 0x2 + 860 0116 06 .uleb128 0x6 + 861 0117 00 .byte 0 + 862 0118 00 .byte 0 + 863 0119 15 .uleb128 0x15 + 864 011a 05 .uleb128 0x5 + 865 011b 00 .byte 0 + 866 011c 03 .uleb128 0x3 + 867 011d 0E .uleb128 0xe + 868 011e 3A .uleb128 0x3a + 869 011f 0B .uleb128 0xb + 870 0120 3B .uleb128 0x3b + 871 0121 0B .uleb128 0xb + 872 0122 49 .uleb128 0x49 + 873 0123 13 .uleb128 0x13 + 874 0124 02 .uleb128 0x2 + 875 0125 0A .uleb128 0xa + 876 0126 00 .byte 0 + 877 0127 00 .byte 0 + 878 0128 16 .uleb128 0x16 + 879 0129 2E .uleb128 0x2e + 880 012a 01 .byte 0x1 + 881 012b 31 .uleb128 0x31 + 882 012c 13 .uleb128 0x13 + 883 012d 11 .uleb128 0x11 + 884 012e 01 .uleb128 0x1 + 885 012f 12 .uleb128 0x12 + 886 0130 01 .uleb128 0x1 + 887 0131 40 .uleb128 0x40 + 888 0132 06 .uleb128 0x6 + 889 0133 9642 .uleb128 0x2116 + 890 0135 0C .uleb128 0xc + 891 0136 01 .uleb128 0x1 + 892 0137 13 .uleb128 0x13 + 893 0138 00 .byte 0 + 894 0139 00 .byte 0 + 895 013a 17 .uleb128 0x17 + 896 013b 05 .uleb128 0x5 + 897 013c 00 .byte 0 + 898 013d 31 .uleb128 0x31 + 899 013e 13 .uleb128 0x13 + 900 013f 02 .uleb128 0x2 + 901 0140 06 .uleb128 0x6 + 902 0141 00 .byte 0 + 903 0142 00 .byte 0 + 904 0143 18 .uleb128 0x18 + 905 0144 34 .uleb128 0x34 + 906 0145 00 .byte 0 + 907 0146 31 .uleb128 0x31 + 908 0147 13 .uleb128 0x13 + 909 0148 02 .uleb128 0x2 + 910 0149 06 .uleb128 0x6 + ARM GAS C:\cygwin\tmp\ccqnx457.s page 17 + + + 911 014a 00 .byte 0 + 912 014b 00 .byte 0 + 913 014c 19 .uleb128 0x19 + 914 014d 2E .uleb128 0x2e + 915 014e 01 .byte 0x1 + 916 014f 3F .uleb128 0x3f + 917 0150 0C .uleb128 0xc + 918 0151 03 .uleb128 0x3 + 919 0152 0E .uleb128 0xe + 920 0153 3A .uleb128 0x3a + 921 0154 0B .uleb128 0xb + 922 0155 3B .uleb128 0x3b + 923 0156 0B .uleb128 0xb + 924 0157 27 .uleb128 0x27 + 925 0158 0C .uleb128 0xc + 926 0159 49 .uleb128 0x49 + 927 015a 13 .uleb128 0x13 + 928 015b 11 .uleb128 0x11 + 929 015c 01 .uleb128 0x1 + 930 015d 12 .uleb128 0x12 + 931 015e 01 .uleb128 0x1 + 932 015f 40 .uleb128 0x40 + 933 0160 06 .uleb128 0x6 + 934 0161 9642 .uleb128 0x2116 + 935 0163 0C .uleb128 0xc + 936 0164 01 .uleb128 0x1 + 937 0165 13 .uleb128 0x13 + 938 0166 00 .byte 0 + 939 0167 00 .byte 0 + 940 0168 1A .uleb128 0x1a + 941 0169 05 .uleb128 0x5 + 942 016a 00 .byte 0 + 943 016b 03 .uleb128 0x3 + 944 016c 08 .uleb128 0x8 + 945 016d 3A .uleb128 0x3a + 946 016e 0B .uleb128 0xb + 947 016f 3B .uleb128 0x3b + 948 0170 0B .uleb128 0xb + 949 0171 49 .uleb128 0x49 + 950 0172 13 .uleb128 0x13 + 951 0173 02 .uleb128 0x2 + 952 0174 06 .uleb128 0x6 + 953 0175 00 .byte 0 + 954 0176 00 .byte 0 + 955 0177 1B .uleb128 0x1b + 956 0178 34 .uleb128 0x34 + 957 0179 00 .byte 0 + 958 017a 03 .uleb128 0x3 + 959 017b 0E .uleb128 0xe + 960 017c 3A .uleb128 0x3a + 961 017d 0B .uleb128 0xb + 962 017e 3B .uleb128 0x3b + 963 017f 0B .uleb128 0xb + 964 0180 49 .uleb128 0x49 + 965 0181 13 .uleb128 0x13 + 966 0182 02 .uleb128 0x2 + 967 0183 0A .uleb128 0xa + ARM GAS C:\cygwin\tmp\ccqnx457.s page 18 + + + 968 0184 00 .byte 0 + 969 0185 00 .byte 0 + 970 0186 1C .uleb128 0x1c + 971 0187 1D .uleb128 0x1d + 972 0188 01 .byte 0x1 + 973 0189 31 .uleb128 0x31 + 974 018a 13 .uleb128 0x13 + 975 018b 52 .uleb128 0x52 + 976 018c 01 .uleb128 0x1 + 977 018d 55 .uleb128 0x55 + 978 018e 06 .uleb128 0x6 + 979 018f 58 .uleb128 0x58 + 980 0190 0B .uleb128 0xb + 981 0191 59 .uleb128 0x59 + 982 0192 0B .uleb128 0xb + 983 0193 00 .byte 0 + 984 0194 00 .byte 0 + 985 0195 1D .uleb128 0x1d + 986 0196 0B .uleb128 0xb + 987 0197 01 .byte 0x1 + 988 0198 55 .uleb128 0x55 + 989 0199 06 .uleb128 0x6 + 990 019a 00 .byte 0 + 991 019b 00 .byte 0 + 992 019c 1E .uleb128 0x1e + 993 019d 2E .uleb128 0x2e + 994 019e 01 .byte 0x1 + 995 019f 31 .uleb128 0x31 + 996 01a0 13 .uleb128 0x13 + 997 01a1 11 .uleb128 0x11 + 998 01a2 01 .uleb128 0x1 + 999 01a3 12 .uleb128 0x12 + 1000 01a4 01 .uleb128 0x1 + 1001 01a5 40 .uleb128 0x40 + 1002 01a6 0A .uleb128 0xa + 1003 01a7 9742 .uleb128 0x2117 + 1004 01a9 0C .uleb128 0xc + 1005 01aa 01 .uleb128 0x1 + 1006 01ab 13 .uleb128 0x13 + 1007 01ac 00 .byte 0 + 1008 01ad 00 .byte 0 + 1009 01ae 1F .uleb128 0x1f + 1010 01af 05 .uleb128 0x5 + 1011 01b0 00 .byte 0 + 1012 01b1 31 .uleb128 0x31 + 1013 01b2 13 .uleb128 0x13 + 1014 01b3 02 .uleb128 0x2 + 1015 01b4 0A .uleb128 0xa + 1016 01b5 00 .byte 0 + 1017 01b6 00 .byte 0 + 1018 01b7 20 .uleb128 0x20 + 1019 01b8 34 .uleb128 0x34 + 1020 01b9 00 .byte 0 + 1021 01ba 31 .uleb128 0x31 + 1022 01bb 13 .uleb128 0x13 + 1023 01bc 02 .uleb128 0x2 + 1024 01bd 0A .uleb128 0xa + ARM GAS C:\cygwin\tmp\ccqnx457.s page 19 + + + 1025 01be 00 .byte 0 + 1026 01bf 00 .byte 0 + 1027 01c0 21 .uleb128 0x21 + 1028 01c1 2E .uleb128 0x2e + 1029 01c2 01 .byte 0x1 + 1030 01c3 3F .uleb128 0x3f + 1031 01c4 0C .uleb128 0xc + 1032 01c5 03 .uleb128 0x3 + 1033 01c6 0E .uleb128 0xe + 1034 01c7 3A .uleb128 0x3a + 1035 01c8 0B .uleb128 0xb + 1036 01c9 3B .uleb128 0x3b + 1037 01ca 0B .uleb128 0xb + 1038 01cb 27 .uleb128 0x27 + 1039 01cc 0C .uleb128 0xc + 1040 01cd 11 .uleb128 0x11 + 1041 01ce 01 .uleb128 0x1 + 1042 01cf 12 .uleb128 0x12 + 1043 01d0 01 .uleb128 0x1 + 1044 01d1 40 .uleb128 0x40 + 1045 01d2 0A .uleb128 0xa + 1046 01d3 9742 .uleb128 0x2117 + 1047 01d5 0C .uleb128 0xc + 1048 01d6 00 .byte 0 + 1049 01d7 00 .byte 0 + 1050 01d8 22 .uleb128 0x22 + 1051 01d9 1D .uleb128 0x1d + 1052 01da 01 .byte 0x1 + 1053 01db 31 .uleb128 0x31 + 1054 01dc 13 .uleb128 0x13 + 1055 01dd 11 .uleb128 0x11 + 1056 01de 01 .uleb128 0x1 + 1057 01df 12 .uleb128 0x12 + 1058 01e0 01 .uleb128 0x1 + 1059 01e1 58 .uleb128 0x58 + 1060 01e2 0B .uleb128 0xb + 1061 01e3 59 .uleb128 0x59 + 1062 01e4 0B .uleb128 0xb + 1063 01e5 00 .byte 0 + 1064 01e6 00 .byte 0 + 1065 01e7 23 .uleb128 0x23 + 1066 01e8 0B .uleb128 0xb + 1067 01e9 01 .byte 0x1 + 1068 01ea 11 .uleb128 0x11 + 1069 01eb 01 .uleb128 0x1 + 1070 01ec 12 .uleb128 0x12 + 1071 01ed 01 .uleb128 0x1 + 1072 01ee 00 .byte 0 + 1073 01ef 00 .byte 0 + 1074 01f0 00 .byte 0 + 1075 .section .debug_loc,"",%progbits + 1076 .Ldebug_loc0: + 1077 .LLST0: + 1078 0000 00000000 .4byte .LVL0 + 1079 0004 02000000 .4byte .LVL1 + 1080 0008 0100 .2byte 0x1 + 1081 000a 51 .byte 0x51 + ARM GAS C:\cygwin\tmp\ccqnx457.s page 20 + + + 1082 000b 02000000 .4byte .LVL1 + 1083 000f 06000000 .4byte .LVL2 + 1084 0013 0300 .2byte 0x3 + 1085 0015 71 .byte 0x71 + 1086 0016 79 .sleb128 -7 + 1087 0017 9F .byte 0x9f + 1088 0018 06000000 .4byte .LVL2 + 1089 001c 10000000 .4byte .LFE7 + 1090 0020 0400 .2byte 0x4 + 1091 0022 F3 .byte 0xf3 + 1092 0023 01 .uleb128 0x1 + 1093 0024 51 .byte 0x51 + 1094 0025 9F .byte 0x9f + 1095 0026 00000000 .4byte 0 + 1096 002a 00000000 .4byte 0 + 1097 .LLST1: + 1098 002e 00000000 .4byte .LFB8 + 1099 0032 02000000 .4byte .LCFI0 + 1100 0036 0200 .2byte 0x2 + 1101 0038 7D .byte 0x7d + 1102 0039 00 .sleb128 0 + 1103 003a 02000000 .4byte .LCFI0 + 1104 003e 18000000 .4byte .LFE8 + 1105 0042 0200 .2byte 0x2 + 1106 0044 7D .byte 0x7d + 1107 0045 08 .sleb128 8 + 1108 0046 00000000 .4byte 0 + 1109 004a 00000000 .4byte 0 + 1110 .LLST2: + 1111 004e 00000000 .4byte .LVL3 + 1112 0052 06000000 .4byte .LVL4 + 1113 0056 0100 .2byte 0x1 + 1114 0058 50 .byte 0x50 + 1115 0059 06000000 .4byte .LVL4 + 1116 005d 15000000 .4byte .LVL6-1 + 1117 0061 0100 .2byte 0x1 + 1118 0063 53 .byte 0x53 + 1119 0064 15000000 .4byte .LVL6-1 + 1120 0068 18000000 .4byte .LFE8 + 1121 006c 0400 .2byte 0x4 + 1122 006e F3 .byte 0xf3 + 1123 006f 01 .uleb128 0x1 + 1124 0070 50 .byte 0x50 + 1125 0071 9F .byte 0x9f + 1126 0072 00000000 .4byte 0 + 1127 0076 00000000 .4byte 0 + 1128 .LLST3: + 1129 007a 06000000 .4byte .LVL4 + 1130 007e 14000000 .4byte .LVL5 + 1131 0082 0100 .2byte 0x1 + 1132 0084 50 .byte 0x50 + 1133 0085 14000000 .4byte .LVL5 + 1134 0089 15000000 .4byte .LVL6-1 + 1135 008d 0200 .2byte 0x2 + 1136 008f 73 .byte 0x73 + 1137 0090 00 .sleb128 0 + 1138 0091 16000000 .4byte .LVL6 + ARM GAS C:\cygwin\tmp\ccqnx457.s page 21 + + + 1139 0095 18000000 .4byte .LFE8 + 1140 0099 0100 .2byte 0x1 + 1141 009b 50 .byte 0x50 + 1142 009c 00000000 .4byte 0 + 1143 00a0 00000000 .4byte 0 + 1144 .LLST4: + 1145 00a4 00000000 .4byte .LFB9 + 1146 00a8 02000000 .4byte .LCFI1 + 1147 00ac 0200 .2byte 0x2 + 1148 00ae 7D .byte 0x7d + 1149 00af 00 .sleb128 0 + 1150 00b0 02000000 .4byte .LCFI1 + 1151 00b4 20000000 .4byte .LFE9 + 1152 00b8 0200 .2byte 0x2 + 1153 00ba 7D .byte 0x7d + 1154 00bb 08 .sleb128 8 + 1155 00bc 00000000 .4byte 0 + 1156 00c0 00000000 .4byte 0 + 1157 .LLST5: + 1158 00c4 00000000 .4byte .LVL7 + 1159 00c8 08000000 .4byte .LVL9 + 1160 00cc 0100 .2byte 0x1 + 1161 00ce 50 .byte 0x50 + 1162 00cf 08000000 .4byte .LVL9 + 1163 00d3 1B000000 .4byte .LVL11-1 + 1164 00d7 0100 .2byte 0x1 + 1165 00d9 53 .byte 0x53 + 1166 00da 1B000000 .4byte .LVL11-1 + 1167 00de 20000000 .4byte .LFE9 + 1168 00e2 0400 .2byte 0x4 + 1169 00e4 F3 .byte 0xf3 + 1170 00e5 01 .uleb128 0x1 + 1171 00e6 50 .byte 0x50 + 1172 00e7 9F .byte 0x9f + 1173 00e8 00000000 .4byte 0 + 1174 00ec 00000000 .4byte 0 + 1175 .LLST6: + 1176 00f0 06000000 .4byte .LVL8 + 1177 00f4 08000000 .4byte .LVL9 + 1178 00f8 0100 .2byte 0x1 + 1179 00fa 50 .byte 0x50 + 1180 00fb 08000000 .4byte .LVL9 + 1181 00ff 1B000000 .4byte .LVL11-1 + 1182 0103 0100 .2byte 0x1 + 1183 0105 53 .byte 0x53 + 1184 0106 1B000000 .4byte .LVL11-1 + 1185 010a 20000000 .4byte .LFE9 + 1186 010e 0400 .2byte 0x4 + 1187 0110 F3 .byte 0xf3 + 1188 0111 01 .uleb128 0x1 + 1189 0112 50 .byte 0x50 + 1190 0113 9F .byte 0x9f + 1191 0114 00000000 .4byte 0 + 1192 0118 00000000 .4byte 0 + 1193 .LLST7: + 1194 011c 08000000 .4byte .LVL9 + 1195 0120 1A000000 .4byte .LVL10 + ARM GAS C:\cygwin\tmp\ccqnx457.s page 22 + + + 1196 0124 0100 .2byte 0x1 + 1197 0126 50 .byte 0x50 + 1198 0127 1A000000 .4byte .LVL10 + 1199 012b 1B000000 .4byte .LVL11-1 + 1200 012f 0200 .2byte 0x2 + 1201 0131 73 .byte 0x73 + 1202 0132 00 .sleb128 0 + 1203 0133 1C000000 .4byte .LVL11 + 1204 0137 20000000 .4byte .LFE9 + 1205 013b 0100 .2byte 0x1 + 1206 013d 50 .byte 0x50 + 1207 013e 00000000 .4byte 0 + 1208 0142 00000000 .4byte 0 + 1209 .section .debug_aranges,"",%progbits + 1210 0000 3C000000 .4byte 0x3c + 1211 0004 0200 .2byte 0x2 + 1212 0006 00000000 .4byte .Ldebug_info0 + 1213 000a 04 .byte 0x4 + 1214 000b 00 .byte 0 + 1215 000c 0000 .2byte 0 + 1216 000e 0000 .2byte 0 + 1217 0010 00000000 .4byte .LFB7 + 1218 0014 10000000 .4byte .LFE7-.LFB7 + 1219 0018 00000000 .4byte .LFB8 + 1220 001c 18000000 .4byte .LFE8-.LFB8 + 1221 0020 00000000 .4byte .LFB9 + 1222 0024 20000000 .4byte .LFE9-.LFB9 + 1223 0028 00000000 .4byte .LFB10 + 1224 002c 08000000 .4byte .LFE10-.LFB10 + 1225 0030 00000000 .4byte .LFB11 + 1226 0034 0C000000 .4byte .LFE11-.LFB11 + 1227 0038 00000000 .4byte 0 + 1228 003c 00000000 .4byte 0 + 1229 .section .debug_ranges,"",%progbits + 1230 .Ldebug_ranges0: + 1231 0000 06000000 .4byte .LBB6 + 1232 0004 0E000000 .4byte .LBE6 + 1233 0008 12000000 .4byte .LBB9 + 1234 000c 1C000000 .4byte .LBE9 + 1235 0010 00000000 .4byte 0 + 1236 0014 00000000 .4byte 0 + 1237 0018 06000000 .4byte .LBB7 + 1238 001c 0E000000 .4byte .LBE7 + 1239 0020 12000000 .4byte .LBB8 + 1240 0024 1C000000 .4byte .LBE8 + 1241 0028 00000000 .4byte 0 + 1242 002c 00000000 .4byte 0 + 1243 0030 00000000 .4byte .LFB7 + 1244 0034 10000000 .4byte .LFE7 + 1245 0038 00000000 .4byte .LFB8 + 1246 003c 18000000 .4byte .LFE8 + 1247 0040 00000000 .4byte .LFB9 + 1248 0044 20000000 .4byte .LFE9 + 1249 0048 00000000 .4byte .LFB10 + 1250 004c 08000000 .4byte .LFE10 + 1251 0050 00000000 .4byte .LFB11 + 1252 0054 0C000000 .4byte .LFE11 + ARM GAS C:\cygwin\tmp\ccqnx457.s page 23 + + + 1253 0058 00000000 .4byte 0 + 1254 005c 00000000 .4byte 0 + 1255 .section .debug_line,"",%progbits + 1256 .Ldebug_line0: + 1257 0000 2D010000 .section .debug_str,"MS",%progbits,1 + 1257 0200B200 + 1257 00000201 + 1257 FB0E0D00 + 1257 01010101 + 1258 .LASF23: + 1259 0000 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 1259 73657273 + 1259 5C496D61 + 1259 6E6F6C5C + 1259 64657665 + 1260 002d 6C696361 .ascii "lications\\smartcities\000" + 1260 74696F6E + 1260 735C736D + 1260 61727463 + 1260 69746965 + 1261 .LASF10: + 1262 0043 73697A65 .ascii "size_t\000" + 1262 5F7400 + 1263 .LASF14: + 1264 004a 6D705F6F .ascii "mp_object_size\000" + 1264 626A6563 + 1264 745F7369 + 1264 7A6500 + 1265 .LASF24: + 1266 0059 706F6F6C .ascii "pool_header\000" + 1266 5F686561 + 1266 64657200 + 1267 .LASF19: + 1268 0065 73697A65 .ascii "size\000" + 1268 00 + 1269 .LASF6: + 1270 006a 6C6F6E67 .ascii "long unsigned int\000" + 1270 20756E73 + 1270 69676E65 + 1270 6420696E + 1270 7400 + 1271 .LASF4: + 1272 007c 73686F72 .ascii "short unsigned int\000" + 1272 7420756E + 1272 7369676E + 1272 65642069 + 1272 6E7400 + 1273 .LASF20: + 1274 008f 70726F76 .ascii "provider\000" + 1274 69646572 + 1274 00 + 1275 .LASF26: + 1276 0098 6368506F .ascii "chPoolFreeI\000" + 1276 6F6C4672 + 1276 65654900 + 1277 .LASF2: + 1278 00a4 756E7369 .ascii "unsigned char\000" + ARM GAS C:\cygwin\tmp\ccqnx457.s page 24 + + + 1278 676E6564 + 1278 20636861 + 1278 7200 + 1279 .LASF29: + 1280 00b2 6368506F .ascii "chPoolFree\000" + 1280 6F6C4672 + 1280 656500 + 1281 .LASF16: + 1282 00bd 4D656D6F .ascii "MemoryPool\000" + 1282 7279506F + 1282 6F6C00 + 1283 .LASF18: + 1284 00c8 6F626A70 .ascii "objp\000" + 1284 00 + 1285 .LASF25: + 1286 00cd 6368506F .ascii "chPoolAllocI\000" + 1286 6F6C416C + 1286 6C6F6349 + 1286 00 + 1287 .LASF0: + 1288 00da 756E7369 .ascii "unsigned int\000" + 1288 676E6564 + 1288 20696E74 + 1288 00 + 1289 .LASF8: + 1290 00e7 6C6F6E67 .ascii "long long unsigned int\000" + 1290 206C6F6E + 1290 6720756E + 1290 7369676E + 1290 65642069 + 1291 .LASF12: + 1292 00fe 70685F6E .ascii "ph_next\000" + 1292 65787400 + 1293 .LASF9: + 1294 0106 73697A65 .ascii "sizetype\000" + 1294 74797065 + 1294 00 + 1295 .LASF7: + 1296 010f 6C6F6E67 .ascii "long long int\000" + 1296 206C6F6E + 1296 6720696E + 1296 7400 + 1297 .LASF17: + 1298 011d 63686172 .ascii "char\000" + 1298 00 + 1299 .LASF21: + 1300 0122 474E5520 .ascii "GNU C 4.7.2\000" + 1300 4320342E + 1300 372E3200 + 1301 .LASF11: + 1302 012e 6D656D67 .ascii "memgetfunc_t\000" + 1302 65746675 + 1302 6E635F74 + 1302 00 + 1303 .LASF15: + 1304 013b 6D705F70 .ascii "mp_provider\000" + 1304 726F7669 + ARM GAS C:\cygwin\tmp\ccqnx457.s page 25 + + + 1304 64657200 + 1305 .LASF3: + 1306 0147 73686F72 .ascii "short int\000" + 1306 7420696E + 1306 7400 + 1307 .LASF28: + 1308 0151 6368506F .ascii "chPoolAlloc\000" + 1308 6F6C416C + 1308 6C6F6300 + 1309 .LASF22: + 1310 015d 2E2E2F2E .ascii "../..//os/kernel/src/chmempools.c\000" + 1310 2E2F2F6F + 1310 732F6B65 + 1310 726E656C + 1310 2F737263 + 1311 .LASF5: + 1312 017f 6C6F6E67 .ascii "long int\000" + 1312 20696E74 + 1312 00 + 1313 .LASF1: + 1314 0188 7369676E .ascii "signed char\000" + 1314 65642063 + 1314 68617200 + 1315 .LASF13: + 1316 0194 6D705F6E .ascii "mp_next\000" + 1316 65787400 + 1317 .LASF27: + 1318 019c 6368506F .ascii "chPoolInit\000" + 1318 6F6C496E + 1318 697400 + 1319 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\ccqnx457.s page 26 + + +DEFINED SYMBOLS + *ABS*:00000000 chmempools.c +C:\cygwin\tmp\ccqnx457.s:19 .text.chPoolInit:00000000 $t +C:\cygwin\tmp\ccqnx457.s:25 .text.chPoolInit:00000000 chPoolInit +C:\cygwin\tmp\ccqnx457.s:51 .text.chPoolAllocI:00000000 $t +C:\cygwin\tmp\ccqnx457.s:57 .text.chPoolAllocI:00000000 chPoolAllocI +C:\cygwin\tmp\ccqnx457.s:95 .text.chPoolAlloc:00000000 $t +C:\cygwin\tmp\ccqnx457.s:101 .text.chPoolAlloc:00000000 chPoolAlloc +C:\cygwin\tmp\ccqnx457.s:165 .text.chPoolFreeI:00000000 $t +C:\cygwin\tmp\ccqnx457.s:171 .text.chPoolFreeI:00000000 chPoolFreeI +C:\cygwin\tmp\ccqnx457.s:190 .text.chPoolFree:00000000 $t +C:\cygwin\tmp\ccqnx457.s:196 .text.chPoolFree:00000000 chPoolFree + .debug_frame:00000010 $d + +NO UNDEFINED SYMBOLS diff --git a/Project/applications/smartcities/build/lst/chmsg.lst b/Project/applications/smartcities/build/lst/chmsg.lst new file mode 100644 index 0000000..322710e --- /dev/null +++ b/Project/applications/smartcities/build/lst/chmsg.lst @@ -0,0 +1,2161 @@ +ARM GAS C:\cygwin\tmp\cc1efFDI.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "chmsg.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text.chMsgSend,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .global chMsgSend + 22 .thumb + 23 .thumb_func + 24 .type chMsgSend, %function + 25 chMsgSend: + 26 .LFB7: + 27 .file 1 "../..//os/kernel/src/chmsg.c" + 28 .loc 1 75 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 .LVL0: + 33 0000 70B5 push {r4, r5, r6, lr} + 34 .LCFI0: + 35 .cfi_def_cfa_offset 16 + 36 .cfi_offset 4, -16 + 37 .cfi_offset 5, -12 + 38 .cfi_offset 6, -8 + 39 .cfi_offset 14, -4 + 40 .loc 1 76 0 + 41 0002 0C4A ldr r2, .L5 + 42 0004 D469 ldr r4, [r2, #28] + 43 .LVL1: + 44 .loc 1 80 0 + 45 @ 80 "../..//os/kernel/src/chmsg.c" 1 + 46 0006 72B6 cpsid i + 47 @ 0 "" 2 + 48 .loc 1 82 0 + 49 .thumb + 50 0008 00F12C05 add r5, r0, #44 + 51 000c 6562 str r5, [r4, #36] + 52 .LVL2: + 53 .loc 1 84 0 + 54 000e 067F ldrb r6, [r0, #28] @ zero_extendqisi2 + 55 .LBB6: + 56 .LBB7: + 57 .file 2 "../..//os/kernel/include/chinline.h" + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 2 + + + 58 .loc 2 55 0 + 59 0010 026B ldr r2, [r0, #48] + 60 .LBE7: + 61 .LBE6: + 62 .loc 1 84 0 + 63 0012 0C2E cmp r6, #12 + 64 .LBB10: + 65 .LBB8: + 66 .loc 2 54 0 + 67 0014 2560 str r5, [r4, #0] + 68 .LBE8: + 69 .LBE10: + 70 .loc 1 81 0 + 71 0016 6163 str r1, [r4, #52] + 72 .LBB11: + 73 .LBB9: + 74 .loc 2 55 0 + 75 0018 6260 str r2, [r4, #4] + 76 .loc 2 56 0 + 77 001a 0463 str r4, [r0, #48] + 78 001c 1460 str r4, [r2, #0] + 79 .LBE9: + 80 .LBE11: + 81 .loc 1 84 0 + 82 001e 05D0 beq .L4 + 83 .LVL3: + 84 .L2: + 85 .loc 1 86 0 + 86 0020 0A20 movs r0, #10 + 87 0022 FFF7FEFF bl chSchGoSleepS + 88 .LVL4: + 89 .loc 1 87 0 + 90 0026 606A ldr r0, [r4, #36] + 91 .LVL5: + 92 .loc 1 88 0 + 93 @ 88 "../..//os/kernel/src/chmsg.c" 1 + 94 0028 62B6 cpsie i + 95 @ 0 "" 2 + 96 .loc 1 90 0 + 97 .thumb + 98 002a 70BD pop {r4, r5, r6, pc} + 99 .LVL6: + 100 .L4: + 101 .loc 1 85 0 + 102 002c FFF7FEFF bl chSchReadyI + 103 .LVL7: + 104 0030 F6E7 b .L2 + 105 .L6: + 106 0032 00BF .align 2 + 107 .L5: + 108 0034 00000000 .word rlist + 109 .cfi_endproc + 110 .LFE7: + 111 .size chMsgSend, .-chMsgSend + 112 0038 AFF30080 .section .text.chMsgWait,"ax",%progbits + 112 AFF30080 + 113 .align 2 + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 3 + + + 114 .p2align 4,,15 + 115 .global chMsgWait + 116 .thumb + 117 .thumb_func + 118 .type chMsgWait, %function + 119 chMsgWait: + 120 .LFB8: + 121 .loc 1 106 0 + 122 .cfi_startproc + 123 @ args = 0, pretend = 0, frame = 0 + 124 @ frame_needed = 0, uses_anonymous_args = 0 + 125 0000 10B5 push {r4, lr} + 126 .LCFI1: + 127 .cfi_def_cfa_offset 8 + 128 .cfi_offset 4, -8 + 129 .cfi_offset 14, -4 + 130 .loc 1 109 0 + 131 @ 109 "../..//os/kernel/src/chmsg.c" 1 + 132 0002 72B6 cpsid i + 133 @ 0 "" 2 + 134 .loc 1 110 0 + 135 .thumb + 136 0004 0A4C ldr r4, .L10 + 137 0006 E269 ldr r2, [r4, #28] + 138 0008 1346 mov r3, r2 + 139 000a 53F82C0F ldr r0, [r3, #44]! + 140 000e 9842 cmp r0, r3 + 141 0010 06D0 beq .L9 + 142 .L8: + 143 .LVL8: + 144 .LBB12: + 145 .LBB13: + 146 .loc 2 62 0 + 147 0012 0168 ldr r1, [r0, #0] + 148 0014 D162 str r1, [r2, #44] + 149 0016 4B60 str r3, [r1, #4] + 150 .LBE13: + 151 .LBE12: + 152 .loc 1 113 0 + 153 0018 0B23 movs r3, #11 + 154 001a 0377 strb r3, [r0, #28] + 155 .loc 1 114 0 + 156 @ 114 "../..//os/kernel/src/chmsg.c" 1 + 157 001c 62B6 cpsie i + 158 @ 0 "" 2 + 159 .loc 1 116 0 + 160 .thumb + 161 001e 10BD pop {r4, pc} + 162 .LVL9: + 163 .L9: + 164 .loc 1 111 0 + 165 0020 0C20 movs r0, #12 + 166 0022 FFF7FEFF bl chSchGoSleepS + 167 .LVL10: + 168 0026 E269 ldr r2, [r4, #28] + 169 0028 1346 mov r3, r2 + 170 002a 53F82C0F ldr r0, [r3, #44]! + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 4 + + + 171 002e F0E7 b .L8 + 172 .L11: + 173 .align 2 + 174 .L10: + 175 0030 00000000 .word rlist + 176 .cfi_endproc + 177 .LFE8: + 178 .size chMsgWait, .-chMsgWait + 179 0034 AFF30080 .section .text.chMsgRelease,"ax",%progbits + 179 AFF30080 + 179 AFF30080 + 180 .align 2 + 181 .p2align 4,,15 + 182 .global chMsgRelease + 183 .thumb + 184 .thumb_func + 185 .type chMsgRelease, %function + 186 chMsgRelease: + 187 .LFB9: + 188 .loc 1 128 0 + 189 .cfi_startproc + 190 @ args = 0, pretend = 0, frame = 0 + 191 @ frame_needed = 0, uses_anonymous_args = 0 + 192 .LVL11: + 193 0000 08B5 push {r3, lr} + 194 .LCFI2: + 195 .cfi_def_cfa_offset 8 + 196 .cfi_offset 3, -8 + 197 .cfi_offset 14, -4 + 198 .loc 1 130 0 + 199 @ 130 "../..//os/kernel/src/chmsg.c" 1 + 200 0002 72B6 cpsid i + 201 @ 0 "" 2 + 202 .loc 1 133 0 + 203 .thumb + 204 0004 FFF7FEFF bl chSchWakeupS + 205 .LVL12: + 206 .loc 1 134 0 + 207 @ 134 "../..//os/kernel/src/chmsg.c" 1 + 208 0008 62B6 cpsie i + 209 @ 0 "" 2 + 210 .thumb + 211 000a 08BD pop {r3, pc} + 212 .cfi_endproc + 213 .LFE9: + 214 .size chMsgRelease, .-chMsgRelease + 215 000c AFF30080 .text + 216 .Letext0: + 217 .file 3 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 218 .file 4 "../..//os/ports/GCC/ARMCMx/chtypes.h" + 219 .file 5 "../..//os/kernel/include/chlists.h" + 220 .file 6 "../..//os/kernel/include/chthreads.h" + 221 .file 7 "../..//os/ports/GCC/ARMCMx/chcore_v7m.h" + 222 .file 8 "../..//os/kernel/include/chschd.h" + 223 .file 9 "../..//os/kernel/include/chmtx.h" + 224 .section .debug_info,"",%progbits + 225 .Ldebug_info0: + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 5 + + + 226 0000 10060000 .4byte 0x610 + 227 0004 0200 .2byte 0x2 + 228 0006 00000000 .4byte .Ldebug_abbrev0 + 229 000a 04 .byte 0x4 + 230 000b 01 .uleb128 0x1 + 231 000c 8A010000 .4byte .LASF64 + 232 0010 01 .byte 0x1 + 233 0011 6B000000 .4byte .LASF65 + 234 0015 3A010000 .4byte .LASF66 + 235 0019 20000000 .4byte .Ldebug_ranges0+0x20 + 236 001d 00000000 .4byte 0 + 237 0021 00000000 .4byte 0 + 238 0025 00000000 .4byte .Ldebug_line0 + 239 0029 02 .uleb128 0x2 + 240 002a 04 .byte 0x4 + 241 002b 05 .byte 0x5 + 242 002c 696E7400 .ascii "int\000" + 243 0030 03 .uleb128 0x3 + 244 0031 04 .byte 0x4 + 245 0032 07 .byte 0x7 + 246 0033 C3000000 .4byte .LASF0 + 247 0037 03 .uleb128 0x3 + 248 0038 01 .byte 0x1 + 249 0039 06 .byte 0x6 + 250 003a 4F000000 .4byte .LASF1 + 251 003e 04 .uleb128 0x4 + 252 003f D2020000 .4byte .LASF5 + 253 0043 03 .byte 0x3 + 254 0044 2A .byte 0x2a + 255 0045 49000000 .4byte 0x49 + 256 0049 03 .uleb128 0x3 + 257 004a 01 .byte 0x1 + 258 004b 08 .byte 0x8 + 259 004c C7010000 .4byte .LASF2 + 260 0050 03 .uleb128 0x3 + 261 0051 02 .byte 0x2 + 262 0052 05 .byte 0x5 + 263 0053 DF010000 .4byte .LASF3 + 264 0057 03 .uleb128 0x3 + 265 0058 02 .byte 0x2 + 266 0059 07 .byte 0x7 + 267 005a EA000000 .4byte .LASF4 + 268 005e 04 .uleb128 0x4 + 269 005f BF010000 .4byte .LASF6 + 270 0063 03 .byte 0x3 + 271 0064 4F .byte 0x4f + 272 0065 69000000 .4byte 0x69 + 273 0069 03 .uleb128 0x3 + 274 006a 04 .byte 0x4 + 275 006b 05 .byte 0x5 + 276 006c 88000000 .4byte .LASF7 + 277 0070 04 .uleb128 0x4 + 278 0071 3B020000 .4byte .LASF8 + 279 0075 03 .byte 0x3 + 280 0076 50 .byte 0x50 + 281 0077 7B000000 .4byte 0x7b + 282 007b 03 .uleb128 0x3 + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 6 + + + 283 007c 04 .byte 0x4 + 284 007d 07 .byte 0x7 + 285 007e D0000000 .4byte .LASF9 + 286 0082 03 .uleb128 0x3 + 287 0083 08 .byte 0x8 + 288 0084 05 .byte 0x5 + 289 0085 41000000 .4byte .LASF10 + 290 0089 03 .uleb128 0x3 + 291 008a 08 .byte 0x8 + 292 008b 07 .byte 0x7 + 293 008c 1A000000 .4byte .LASF11 + 294 0090 04 .uleb128 0x4 + 295 0091 03010000 .4byte .LASF12 + 296 0095 04 .byte 0x4 + 297 0096 2F .byte 0x2f + 298 0097 3E000000 .4byte 0x3e + 299 009b 04 .uleb128 0x4 + 300 009c 9B000000 .4byte .LASF13 + 301 00a0 04 .byte 0x4 + 302 00a1 30 .byte 0x30 + 303 00a2 3E000000 .4byte 0x3e + 304 00a6 04 .uleb128 0x4 + 305 00a7 A8010000 .4byte .LASF14 + 306 00ab 04 .byte 0x4 + 307 00ac 31 .byte 0x31 + 308 00ad 3E000000 .4byte 0x3e + 309 00b1 04 .uleb128 0x4 + 310 00b2 B7010000 .4byte .LASF15 + 311 00b6 04 .byte 0x4 + 312 00b7 32 .byte 0x32 + 313 00b8 70000000 .4byte 0x70 + 314 00bc 04 .uleb128 0x4 + 315 00bd FD000000 .4byte .LASF16 + 316 00c1 04 .byte 0x4 + 317 00c2 33 .byte 0x33 + 318 00c3 5E000000 .4byte 0x5e + 319 00c7 04 .uleb128 0x4 + 320 00c8 17010000 .4byte .LASF17 + 321 00cc 04 .byte 0x4 + 322 00cd 35 .byte 0x35 + 323 00ce 70000000 .4byte 0x70 + 324 00d2 04 .uleb128 0x4 + 325 00d3 70020000 .4byte .LASF18 + 326 00d7 04 .byte 0x4 + 327 00d8 36 .byte 0x36 + 328 00d9 70000000 .4byte 0x70 + 329 00dd 04 .uleb128 0x4 + 330 00de BD000000 .4byte .LASF19 + 331 00e2 04 .byte 0x4 + 332 00e3 37 .byte 0x37 + 333 00e4 5E000000 .4byte 0x5e + 334 00e8 04 .uleb128 0x4 + 335 00e9 0E020000 .4byte .LASF20 + 336 00ed 05 .byte 0x5 + 337 00ee 2A .byte 0x2a + 338 00ef F3000000 .4byte 0xf3 + 339 00f3 05 .uleb128 0x5 + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 7 + + + 340 00f4 0E020000 .4byte .LASF20 + 341 00f8 48 .byte 0x48 + 342 00f9 06 .byte 0x6 + 343 00fa 5E .byte 0x5e + 344 00fb 0A020000 .4byte 0x20a + 345 00ff 06 .uleb128 0x6 + 346 0100 FF010000 .4byte .LASF21 + 347 0104 06 .byte 0x6 + 348 0105 5F .byte 0x5f + 349 0106 2F020000 .4byte 0x22f + 350 010a 02 .byte 0x2 + 351 010b 23 .byte 0x23 + 352 010c 00 .uleb128 0 + 353 010d 06 .uleb128 0x6 + 354 010e B0010000 .4byte .LASF22 + 355 0112 06 .byte 0x6 + 356 0113 61 .byte 0x61 + 357 0114 2F020000 .4byte 0x22f + 358 0118 02 .byte 0x2 + 359 0119 23 .byte 0x23 + 360 011a 04 .uleb128 0x4 + 361 011b 06 .uleb128 0x6 + 362 011c 3A000000 .4byte .LASF23 + 363 0120 06 .byte 0x6 + 364 0121 63 .byte 0x63 + 365 0122 B1000000 .4byte 0xb1 + 366 0126 02 .byte 0x2 + 367 0127 23 .byte 0x23 + 368 0128 08 .uleb128 0x8 + 369 0129 06 .uleb128 0x6 + 370 012a FA020000 .4byte .LASF24 + 371 012e 06 .byte 0x6 + 372 012f 64 .byte 0x64 + 373 0130 FC020000 .4byte 0x2fc + 374 0134 02 .byte 0x2 + 375 0135 23 .byte 0x23 + 376 0136 0C .uleb128 0xc + 377 0137 06 .uleb128 0x6 + 378 0138 A4000000 .4byte .LASF25 + 379 013c 06 .byte 0x6 + 380 013d 66 .byte 0x66 + 381 013e 2F020000 .4byte 0x22f + 382 0142 02 .byte 0x2 + 383 0143 23 .byte 0x23 + 384 0144 10 .uleb128 0x10 + 385 0145 06 .uleb128 0x6 + 386 0146 32010000 .4byte .LASF26 + 387 014a 06 .byte 0x6 + 388 014b 67 .byte 0x67 + 389 014c 2F020000 .4byte 0x22f + 390 0150 02 .byte 0x2 + 391 0151 23 .byte 0x23 + 392 0152 14 .uleb128 0x14 + 393 0153 06 .uleb128 0x6 + 394 0154 E1020000 .4byte .LASF27 + 395 0158 06 .byte 0x6 + 396 0159 6E .byte 0x6e + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 8 + + + 397 015a 1E040000 .4byte 0x41e + 398 015e 02 .byte 0x2 + 399 015f 23 .byte 0x23 + 400 0160 18 .uleb128 0x18 + 401 0161 06 .uleb128 0x6 + 402 0162 E9010000 .4byte .LASF28 + 403 0166 06 .byte 0x6 + 404 0167 79 .byte 0x79 + 405 0168 9B000000 .4byte 0x9b + 406 016c 02 .byte 0x2 + 407 016d 23 .byte 0x23 + 408 016e 1C .uleb128 0x1c + 409 016f 06 .uleb128 0x6 + 410 0170 06020000 .4byte .LASF29 + 411 0174 06 .byte 0x6 + 412 0175 7D .byte 0x7d + 413 0176 90000000 .4byte 0x90 + 414 017a 02 .byte 0x2 + 415 017b 23 .byte 0x23 + 416 017c 1D .uleb128 0x1d + 417 017d 06 .uleb128 0x6 + 418 017e BB020000 .4byte .LASF30 + 419 0182 06 .byte 0x6 + 420 0183 82 .byte 0x82 + 421 0184 A6000000 .4byte 0xa6 + 422 0188 02 .byte 0x2 + 423 0189 23 .byte 0x23 + 424 018a 1E .uleb128 0x1e + 425 018b 06 .uleb128 0x6 + 426 018c 85020000 .4byte .LASF31 + 427 0190 06 .byte 0x6 + 428 0191 89 .byte 0x89 + 429 0192 26030000 .4byte 0x326 + 430 0196 02 .byte 0x2 + 431 0197 23 .byte 0x23 + 432 0198 20 .uleb128 0x20 + 433 0199 07 .uleb128 0x7 + 434 019a 705F7500 .ascii "p_u\000" + 435 019e 06 .byte 0x6 + 436 019f AE .byte 0xae + 437 01a0 E9030000 .4byte 0x3e9 + 438 01a4 02 .byte 0x2 + 439 01a5 23 .byte 0x23 + 440 01a6 24 .uleb128 0x24 + 441 01a7 06 .uleb128 0x6 + 442 01a8 00030000 .4byte .LASF32 + 443 01ac 06 .byte 0x6 + 444 01ad B3 .byte 0xb3 + 445 01ae 57020000 .4byte 0x257 + 446 01b2 02 .byte 0x2 + 447 01b3 23 .byte 0x23 + 448 01b4 28 .uleb128 0x28 + 449 01b5 06 .uleb128 0x6 + 450 01b6 99020000 .4byte .LASF33 + 451 01ba 06 .byte 0x6 + 452 01bb B9 .byte 0xb9 + 453 01bc 35020000 .4byte 0x235 + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 9 + + + 454 01c0 02 .byte 0x2 + 455 01c1 23 .byte 0x23 + 456 01c2 2C .uleb128 0x2c + 457 01c3 06 .uleb128 0x6 + 458 01c4 00000000 .4byte .LASF34 + 459 01c8 06 .byte 0x6 + 460 01c9 BD .byte 0xbd + 461 01ca BC000000 .4byte 0xbc + 462 01ce 02 .byte 0x2 + 463 01cf 23 .byte 0x23 + 464 01d0 34 .uleb128 0x34 + 465 01d1 06 .uleb128 0x6 + 466 01d2 30020000 .4byte .LASF35 + 467 01d6 06 .byte 0x6 + 468 01d7 C3 .byte 0xc3 + 469 01d8 C7000000 .4byte 0xc7 + 470 01dc 02 .byte 0x2 + 471 01dd 23 .byte 0x23 + 472 01de 38 .uleb128 0x38 + 473 01df 06 .uleb128 0x6 + 474 01e0 D5010000 .4byte .LASF36 + 475 01e4 06 .byte 0x6 + 476 01e5 CA .byte 0xca + 477 01e6 30040000 .4byte 0x430 + 478 01ea 02 .byte 0x2 + 479 01eb 23 .byte 0x23 + 480 01ec 3C .uleb128 0x3c + 481 01ed 06 .uleb128 0x6 + 482 01ee 7A020000 .4byte .LASF37 + 483 01f2 06 .byte 0x6 + 484 01f3 CE .byte 0xce + 485 01f4 B1000000 .4byte 0xb1 + 486 01f8 02 .byte 0x2 + 487 01f9 23 .byte 0x23 + 488 01fa 40 .uleb128 0x40 + 489 01fb 06 .uleb128 0x6 + 490 01fc 5B000000 .4byte .LASF38 + 491 0200 06 .byte 0x6 + 492 0201 D4 .byte 0xd4 + 493 0202 6D020000 .4byte 0x26d + 494 0206 02 .byte 0x2 + 495 0207 23 .byte 0x23 + 496 0208 44 .uleb128 0x44 + 497 0209 00 .byte 0 + 498 020a 08 .uleb128 0x8 + 499 020b 08 .byte 0x8 + 500 020c 05 .byte 0x5 + 501 020d 61 .byte 0x61 + 502 020e 2F020000 .4byte 0x22f + 503 0212 06 .uleb128 0x6 + 504 0213 FF010000 .4byte .LASF21 + 505 0217 05 .byte 0x5 + 506 0218 62 .byte 0x62 + 507 0219 2F020000 .4byte 0x22f + 508 021d 02 .byte 0x2 + 509 021e 23 .byte 0x23 + 510 021f 00 .uleb128 0 + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 10 + + + 511 0220 06 .uleb128 0x6 + 512 0221 B0010000 .4byte .LASF22 + 513 0225 05 .byte 0x5 + 514 0226 64 .byte 0x64 + 515 0227 2F020000 .4byte 0x22f + 516 022b 02 .byte 0x2 + 517 022c 23 .byte 0x23 + 518 022d 04 .uleb128 0x4 + 519 022e 00 .byte 0 + 520 022f 09 .uleb128 0x9 + 521 0230 04 .byte 0x4 + 522 0231 E8000000 .4byte 0xe8 + 523 0235 04 .uleb128 0x4 + 524 0236 7D010000 .4byte .LASF39 + 525 023a 05 .byte 0x5 + 526 023b 66 .byte 0x66 + 527 023c 0A020000 .4byte 0x20a + 528 0240 08 .uleb128 0x8 + 529 0241 04 .byte 0x4 + 530 0242 05 .byte 0x5 + 531 0243 6B .byte 0x6b + 532 0244 57020000 .4byte 0x257 + 533 0248 06 .uleb128 0x6 + 534 0249 FF010000 .4byte .LASF21 + 535 024d 05 .byte 0x5 + 536 024e 6D .byte 0x6d + 537 024f 2F020000 .4byte 0x22f + 538 0253 02 .byte 0x2 + 539 0254 23 .byte 0x23 + 540 0255 00 .uleb128 0 + 541 0256 00 .byte 0 + 542 0257 04 .uleb128 0x4 + 543 0258 0B010000 .4byte .LASF40 + 544 025c 05 .byte 0x5 + 545 025d 70 .byte 0x70 + 546 025e 40020000 .4byte 0x240 + 547 0262 04 .uleb128 0x4 + 548 0263 B4000000 .4byte .LASF41 + 549 0267 07 .byte 0x7 + 550 0268 D7 .byte 0xd7 + 551 0269 6D020000 .4byte 0x26d + 552 026d 0A .uleb128 0xa + 553 026e 04 .byte 0x4 + 554 026f 05 .uleb128 0x5 + 555 0270 92020000 .4byte .LASF42 + 556 0274 24 .byte 0x24 + 557 0275 07 .byte 0x7 + 558 0276 FE .byte 0xfe + 559 0277 FC020000 .4byte 0x2fc + 560 027b 0B .uleb128 0xb + 561 027c 723400 .ascii "r4\000" + 562 027f 07 .byte 0x7 + 563 0280 1101 .2byte 0x111 + 564 0282 62020000 .4byte 0x262 + 565 0286 02 .byte 0x2 + 566 0287 23 .byte 0x23 + 567 0288 00 .uleb128 0 + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 11 + + + 568 0289 0B .uleb128 0xb + 569 028a 723500 .ascii "r5\000" + 570 028d 07 .byte 0x7 + 571 028e 1201 .2byte 0x112 + 572 0290 62020000 .4byte 0x262 + 573 0294 02 .byte 0x2 + 574 0295 23 .byte 0x23 + 575 0296 04 .uleb128 0x4 + 576 0297 0B .uleb128 0xb + 577 0298 723600 .ascii "r6\000" + 578 029b 07 .byte 0x7 + 579 029c 1301 .2byte 0x113 + 580 029e 62020000 .4byte 0x262 + 581 02a2 02 .byte 0x2 + 582 02a3 23 .byte 0x23 + 583 02a4 08 .uleb128 0x8 + 584 02a5 0B .uleb128 0xb + 585 02a6 723700 .ascii "r7\000" + 586 02a9 07 .byte 0x7 + 587 02aa 1401 .2byte 0x114 + 588 02ac 62020000 .4byte 0x262 + 589 02b0 02 .byte 0x2 + 590 02b1 23 .byte 0x23 + 591 02b2 0C .uleb128 0xc + 592 02b3 0B .uleb128 0xb + 593 02b4 723800 .ascii "r8\000" + 594 02b7 07 .byte 0x7 + 595 02b8 1501 .2byte 0x115 + 596 02ba 62020000 .4byte 0x262 + 597 02be 02 .byte 0x2 + 598 02bf 23 .byte 0x23 + 599 02c0 10 .uleb128 0x10 + 600 02c1 0B .uleb128 0xb + 601 02c2 723900 .ascii "r9\000" + 602 02c5 07 .byte 0x7 + 603 02c6 1601 .2byte 0x116 + 604 02c8 62020000 .4byte 0x262 + 605 02cc 02 .byte 0x2 + 606 02cd 23 .byte 0x23 + 607 02ce 14 .uleb128 0x14 + 608 02cf 0B .uleb128 0xb + 609 02d0 72313000 .ascii "r10\000" + 610 02d4 07 .byte 0x7 + 611 02d5 1701 .2byte 0x117 + 612 02d7 62020000 .4byte 0x262 + 613 02db 02 .byte 0x2 + 614 02dc 23 .byte 0x23 + 615 02dd 18 .uleb128 0x18 + 616 02de 0B .uleb128 0xb + 617 02df 72313100 .ascii "r11\000" + 618 02e3 07 .byte 0x7 + 619 02e4 1801 .2byte 0x118 + 620 02e6 62020000 .4byte 0x262 + 621 02ea 02 .byte 0x2 + 622 02eb 23 .byte 0x23 + 623 02ec 1C .uleb128 0x1c + 624 02ed 0B .uleb128 0xb + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 12 + + + 625 02ee 6C7200 .ascii "lr\000" + 626 02f1 07 .byte 0x7 + 627 02f2 1901 .2byte 0x119 + 628 02f4 62020000 .4byte 0x262 + 629 02f8 02 .byte 0x2 + 630 02f9 23 .byte 0x23 + 631 02fa 20 .uleb128 0x20 + 632 02fb 00 .byte 0 + 633 02fc 0C .uleb128 0xc + 634 02fd E2000000 .4byte .LASF43 + 635 0301 04 .byte 0x4 + 636 0302 07 .byte 0x7 + 637 0303 2301 .2byte 0x123 + 638 0305 19030000 .4byte 0x319 + 639 0309 0B .uleb128 0xb + 640 030a 72313300 .ascii "r13\000" + 641 030e 07 .byte 0x7 + 642 030f 2401 .2byte 0x124 + 643 0311 19030000 .4byte 0x319 + 644 0315 02 .byte 0x2 + 645 0316 23 .byte 0x23 + 646 0317 00 .uleb128 0 + 647 0318 00 .byte 0 + 648 0319 09 .uleb128 0x9 + 649 031a 04 .byte 0x4 + 650 031b 6F020000 .4byte 0x26f + 651 031f 03 .uleb128 0x3 + 652 0320 04 .byte 0x4 + 653 0321 07 .byte 0x7 + 654 0322 29010000 .4byte .LASF44 + 655 0326 0D .uleb128 0xd + 656 0327 D2000000 .4byte 0xd2 + 657 032b 08 .uleb128 0x8 + 658 032c 20 .byte 0x20 + 659 032d 08 .byte 0x8 + 660 032e 5E .byte 0x5e + 661 032f 96030000 .4byte 0x396 + 662 0333 06 .uleb128 0x6 + 663 0334 44020000 .4byte .LASF45 + 664 0338 08 .byte 0x8 + 665 0339 5F .byte 0x5f + 666 033a 35020000 .4byte 0x235 + 667 033e 02 .byte 0x2 + 668 033f 23 .byte 0x23 + 669 0340 00 .uleb128 0 + 670 0341 06 .uleb128 0x6 + 671 0342 F1010000 .4byte .LASF46 + 672 0346 08 .byte 0x8 + 673 0347 60 .byte 0x60 + 674 0348 B1000000 .4byte 0xb1 + 675 034c 02 .byte 0x2 + 676 034d 23 .byte 0x23 + 677 034e 08 .uleb128 0x8 + 678 034f 06 .uleb128 0x6 + 679 0350 8C020000 .4byte .LASF47 + 680 0354 08 .byte 0x8 + 681 0355 62 .byte 0x62 + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 13 + + + 682 0356 FC020000 .4byte 0x2fc + 683 035a 02 .byte 0x2 + 684 035b 23 .byte 0x23 + 685 035c 0C .uleb128 0xc + 686 035d 06 .uleb128 0x6 + 687 035e AC000000 .4byte .LASF48 + 688 0362 08 .byte 0x8 + 689 0363 65 .byte 0x65 + 690 0364 2F020000 .4byte 0x22f + 691 0368 02 .byte 0x2 + 692 0369 23 .byte 0x23 + 693 036a 10 .uleb128 0x10 + 694 036b 06 .uleb128 0x6 + 695 036c A0010000 .4byte .LASF49 + 696 0370 08 .byte 0x8 + 697 0371 66 .byte 0x66 + 698 0372 2F020000 .4byte 0x22f + 699 0376 02 .byte 0x2 + 700 0377 23 .byte 0x23 + 701 0378 14 .uleb128 0x14 + 702 0379 06 .uleb128 0x6 + 703 037a E8020000 .4byte .LASF50 + 704 037e 08 .byte 0x8 + 705 037f 6A .byte 0x6a + 706 0380 DD000000 .4byte 0xdd + 707 0384 02 .byte 0x2 + 708 0385 23 .byte 0x23 + 709 0386 18 .uleb128 0x18 + 710 0387 06 .uleb128 0x6 + 711 0388 96010000 .4byte .LASF51 + 712 038c 08 .byte 0x8 + 713 038d 6C .byte 0x6c + 714 038e 2F020000 .4byte 0x22f + 715 0392 02 .byte 0x2 + 716 0393 23 .byte 0x23 + 717 0394 1C .uleb128 0x1c + 718 0395 00 .byte 0 + 719 0396 04 .uleb128 0x4 + 720 0397 C2020000 .4byte .LASF52 + 721 039b 08 .byte 0x8 + 722 039c 6E .byte 0x6e + 723 039d 2B030000 .4byte 0x32b + 724 03a1 05 .uleb128 0x5 + 725 03a2 23010000 .4byte .LASF53 + 726 03a6 10 .byte 0x10 + 727 03a7 09 .byte 0x9 + 728 03a8 2C .byte 0x2c + 729 03a9 D8030000 .4byte 0x3d8 + 730 03ad 06 .uleb128 0x6 + 731 03ae 63000000 .4byte .LASF54 + 732 03b2 09 .byte 0x9 + 733 03b3 2D .byte 0x2d + 734 03b4 35020000 .4byte 0x235 + 735 03b8 02 .byte 0x2 + 736 03b9 23 .byte 0x23 + 737 03ba 00 .uleb128 0 + 738 03bb 06 .uleb128 0x6 + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 14 + + + 739 03bc F2020000 .4byte .LASF55 + 740 03c0 09 .byte 0x9 + 741 03c1 2F .byte 0x2f + 742 03c2 2F020000 .4byte 0x22f + 743 03c6 02 .byte 0x2 + 744 03c7 23 .byte 0x23 + 745 03c8 08 .uleb128 0x8 + 746 03c9 06 .uleb128 0x6 + 747 03ca 69020000 .4byte .LASF56 + 748 03ce 09 .byte 0x9 + 749 03cf 31 .byte 0x31 + 750 03d0 D8030000 .4byte 0x3d8 + 751 03d4 02 .byte 0x2 + 752 03d5 23 .byte 0x23 + 753 03d6 0C .uleb128 0xc + 754 03d7 00 .byte 0 + 755 03d8 09 .uleb128 0x9 + 756 03d9 04 .byte 0x4 + 757 03da A1030000 .4byte 0x3a1 + 758 03de 04 .uleb128 0x4 + 759 03df 23010000 .4byte .LASF53 + 760 03e3 09 .byte 0x9 + 761 03e4 33 .byte 0x33 + 762 03e5 A1030000 .4byte 0x3a1 + 763 03e9 0E .uleb128 0xe + 764 03ea 04 .byte 0x4 + 765 03eb 06 .byte 0x6 + 766 03ec 90 .byte 0x90 + 767 03ed 1E040000 .4byte 0x41e + 768 03f1 0F .uleb128 0xf + 769 03f2 13000000 .4byte .LASF57 + 770 03f6 06 .byte 0x6 + 771 03f7 97 .byte 0x97 + 772 03f8 BC000000 .4byte 0xbc + 773 03fc 0F .uleb128 0xf + 774 03fd 31000000 .4byte .LASF58 + 775 0401 06 .byte 0x6 + 776 0402 9E .byte 0x9e + 777 0403 BC000000 .4byte 0xbc + 778 0407 0F .uleb128 0xf + 779 0408 DA020000 .4byte .LASF59 + 780 040c 06 .byte 0x6 + 781 040d A5 .byte 0xa5 + 782 040e 6D020000 .4byte 0x26d + 783 0412 0F .uleb128 0xf + 784 0413 F8010000 .4byte .LASF60 + 785 0417 06 .byte 0x6 + 786 0418 AC .byte 0xac + 787 0419 C7000000 .4byte 0xc7 + 788 041d 00 .byte 0 + 789 041e 09 .uleb128 0x9 + 790 041f 04 .byte 0x4 + 791 0420 24040000 .4byte 0x424 + 792 0424 10 .uleb128 0x10 + 793 0425 29040000 .4byte 0x429 + 794 0429 03 .uleb128 0x3 + 795 042a 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 15 + + + 796 042b 08 .byte 0x8 + 797 042c 58020000 .4byte .LASF61 + 798 0430 09 .uleb128 0x9 + 799 0431 04 .byte 0x4 + 800 0432 DE030000 .4byte 0x3de + 801 0436 11 .uleb128 0x11 + 802 0437 06000000 .4byte .LASF67 + 803 043b 02 .byte 0x2 + 804 043c 34 .byte 0x34 + 805 043d 01 .byte 0x1 + 806 043e 03 .byte 0x3 + 807 043f 59040000 .4byte 0x459 + 808 0443 12 .uleb128 0x12 + 809 0444 747000 .ascii "tp\000" + 810 0447 02 .byte 0x2 + 811 0448 34 .byte 0x34 + 812 0449 2F020000 .4byte 0x22f + 813 044d 12 .uleb128 0x12 + 814 044e 74717000 .ascii "tqp\000" + 815 0452 02 .byte 0x2 + 816 0453 34 .byte 0x34 + 817 0454 59040000 .4byte 0x459 + 818 0458 00 .byte 0 + 819 0459 09 .uleb128 0x9 + 820 045a 04 .byte 0x4 + 821 045b 35020000 .4byte 0x235 + 822 045f 13 .uleb128 0x13 + 823 0460 5D020000 .4byte .LASF68 + 824 0464 02 .byte 0x2 + 825 0465 3B .byte 0x3b + 826 0466 01 .byte 0x1 + 827 0467 2F020000 .4byte 0x22f + 828 046b 03 .byte 0x3 + 829 046c 86040000 .4byte 0x486 + 830 0470 12 .uleb128 0x12 + 831 0471 74717000 .ascii "tqp\000" + 832 0475 02 .byte 0x2 + 833 0476 3B .byte 0x3b + 834 0477 59040000 .4byte 0x459 + 835 047b 14 .uleb128 0x14 + 836 047c 747000 .ascii "tp\000" + 837 047f 02 .byte 0x2 + 838 0480 3C .byte 0x3c + 839 0481 2F020000 .4byte 0x22f + 840 0485 00 .byte 0 + 841 0486 15 .uleb128 0x15 + 842 0487 01 .byte 0x1 + 843 0488 91000000 .4byte .LASF62 + 844 048c 01 .byte 0x1 + 845 048d 4B .byte 0x4b + 846 048e 01 .byte 0x1 + 847 048f BC000000 .4byte 0xbc + 848 0493 00000000 .4byte .LFB7 + 849 0497 38000000 .4byte .LFE7 + 850 049b 00000000 .4byte .LLST0 + 851 049f 01 .byte 0x1 + 852 04a0 0D050000 .4byte 0x50d + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 16 + + + 853 04a4 16 .uleb128 0x16 + 854 04a5 747000 .ascii "tp\000" + 855 04a8 01 .byte 0x1 + 856 04a9 4B .byte 0x4b + 857 04aa 2F020000 .4byte 0x22f + 858 04ae 20000000 .4byte .LLST1 + 859 04b2 16 .uleb128 0x16 + 860 04b3 6D736700 .ascii "msg\000" + 861 04b7 01 .byte 0x1 + 862 04b8 4B .byte 0x4b + 863 04b9 BC000000 .4byte 0xbc + 864 04bd 58000000 .4byte .LLST2 + 865 04c1 17 .uleb128 0x17 + 866 04c2 63747000 .ascii "ctp\000" + 867 04c6 01 .byte 0x1 + 868 04c7 4C .byte 0x4c + 869 04c8 2F020000 .4byte 0x22f + 870 04cc 01 .byte 0x1 + 871 04cd 54 .byte 0x54 + 872 04ce 18 .uleb128 0x18 + 873 04cf 36040000 .4byte 0x436 + 874 04d3 10000000 .4byte .LBB6 + 875 04d7 00000000 .4byte .Ldebug_ranges0+0 + 876 04db 01 .byte 0x1 + 877 04dc 53 .byte 0x53 + 878 04dd F0040000 .4byte 0x4f0 + 879 04e1 19 .uleb128 0x19 + 880 04e2 4D040000 .4byte 0x44d + 881 04e6 01 .byte 0x1 + 882 04e7 55 .byte 0x55 + 883 04e8 19 .uleb128 0x19 + 884 04e9 43040000 .4byte 0x443 + 885 04ed 01 .byte 0x1 + 886 04ee 54 .byte 0x54 + 887 04ef 00 .byte 0 + 888 04f0 1A .uleb128 0x1a + 889 04f1 26000000 .4byte .LVL4 + 890 04f5 D2050000 .4byte 0x5d2 + 891 04f9 03050000 .4byte 0x503 + 892 04fd 1B .uleb128 0x1b + 893 04fe 01 .byte 0x1 + 894 04ff 50 .byte 0x50 + 895 0500 01 .byte 0x1 + 896 0501 3A .byte 0x3a + 897 0502 00 .byte 0 + 898 0503 1C .uleb128 0x1c + 899 0504 30000000 .4byte .LVL7 + 900 0508 E6050000 .4byte 0x5e6 + 901 050c 00 .byte 0 + 902 050d 15 .uleb128 0x15 + 903 050e 01 .byte 0x1 + 904 050f B1020000 .4byte .LASF63 + 905 0513 01 .byte 0x1 + 906 0514 6A .byte 0x6a + 907 0515 01 .byte 0x1 + 908 0516 2F020000 .4byte 0x22f + 909 051a 00000000 .4byte .LFB8 + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 17 + + + 910 051e 34000000 .4byte .LFE8 + 911 0522 9D000000 .4byte .LLST3 + 912 0526 01 .byte 0x1 + 913 0527 75050000 .4byte 0x575 + 914 052b 14 .uleb128 0x14 + 915 052c 747000 .ascii "tp\000" + 916 052f 01 .byte 0x1 + 917 0530 6B .byte 0x6b + 918 0531 2F020000 .4byte 0x22f + 919 0535 1D .uleb128 0x1d + 920 0536 5F040000 .4byte 0x45f + 921 053a 12000000 .4byte .LBB12 + 922 053e 18000000 .4byte .LBE12 + 923 0542 01 .byte 0x1 + 924 0543 70 .byte 0x70 + 925 0544 65050000 .4byte 0x565 + 926 0548 1E .uleb128 0x1e + 927 0549 70040000 .4byte 0x470 + 928 054d BD000000 .4byte .LLST4 + 929 0551 1F .uleb128 0x1f + 930 0552 12000000 .4byte .LBB13 + 931 0556 18000000 .4byte .LBE13 + 932 055a 20 .uleb128 0x20 + 933 055b 7B040000 .4byte 0x47b + 934 055f D2000000 .4byte .LLST5 + 935 0563 00 .byte 0 + 936 0564 00 .byte 0 + 937 0565 21 .uleb128 0x21 + 938 0566 26000000 .4byte .LVL10 + 939 056a D2050000 .4byte 0x5d2 + 940 056e 1B .uleb128 0x1b + 941 056f 01 .byte 0x1 + 942 0570 50 .byte 0x50 + 943 0571 01 .byte 0x1 + 944 0572 3C .byte 0x3c + 945 0573 00 .byte 0 + 946 0574 00 .byte 0 + 947 0575 22 .uleb128 0x22 + 948 0576 01 .byte 0x1 + 949 0577 15020000 .4byte .LASF69 + 950 057b 01 .byte 0x1 + 951 057c 80 .byte 0x80 + 952 057d 01 .byte 0x1 + 953 057e 00000000 .4byte .LFB9 + 954 0582 0C000000 .4byte .LFE9 + 955 0586 E5000000 .4byte .LLST6 + 956 058a 01 .byte 0x1 + 957 058b C5050000 .4byte 0x5c5 + 958 058f 16 .uleb128 0x16 + 959 0590 747000 .ascii "tp\000" + 960 0593 01 .byte 0x1 + 961 0594 80 .byte 0x80 + 962 0595 2F020000 .4byte 0x22f + 963 0599 05010000 .4byte .LLST7 + 964 059d 16 .uleb128 0x16 + 965 059e 6D736700 .ascii "msg\000" + 966 05a2 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 18 + + + 967 05a3 80 .byte 0x80 + 968 05a4 BC000000 .4byte 0xbc + 969 05a8 26010000 .4byte .LLST8 + 970 05ac 21 .uleb128 0x21 + 971 05ad 08000000 .4byte .LVL12 + 972 05b1 FE050000 .4byte 0x5fe + 973 05b5 1B .uleb128 0x1b + 974 05b6 01 .byte 0x1 + 975 05b7 51 .byte 0x51 + 976 05b8 03 .byte 0x3 + 977 05b9 F3 .byte 0xf3 + 978 05ba 01 .uleb128 0x1 + 979 05bb 51 .byte 0x51 + 980 05bc 1B .uleb128 0x1b + 981 05bd 01 .byte 0x1 + 982 05be 50 .byte 0x50 + 983 05bf 03 .byte 0x3 + 984 05c0 F3 .byte 0xf3 + 985 05c1 01 .uleb128 0x1 + 986 05c2 50 .byte 0x50 + 987 05c3 00 .byte 0 + 988 05c4 00 .byte 0 + 989 05c5 23 .uleb128 0x23 + 990 05c6 CC020000 .4byte .LASF70 + 991 05ca 08 .byte 0x8 + 992 05cb 72 .byte 0x72 + 993 05cc 96030000 .4byte 0x396 + 994 05d0 01 .byte 0x1 + 995 05d1 01 .byte 0x1 + 996 05d2 24 .uleb128 0x24 + 997 05d3 01 .byte 0x1 + 998 05d4 22020000 .4byte .LASF71 + 999 05d8 08 .byte 0x8 + 1000 05d9 96 .byte 0x96 + 1001 05da 01 .byte 0x1 + 1002 05db 01 .byte 0x1 + 1003 05dc E6050000 .4byte 0x5e6 + 1004 05e0 25 .uleb128 0x25 + 1005 05e1 9B000000 .4byte 0x9b + 1006 05e5 00 .byte 0 + 1007 05e6 26 .uleb128 0x26 + 1008 05e7 01 .byte 0x1 + 1009 05e8 4C020000 .4byte .LASF72 + 1010 05ec 08 .byte 0x8 + 1011 05ed 93 .byte 0x93 + 1012 05ee 01 .byte 0x1 + 1013 05ef 2F020000 .4byte 0x22f + 1014 05f3 01 .byte 0x1 + 1015 05f4 FE050000 .4byte 0x5fe + 1016 05f8 25 .uleb128 0x25 + 1017 05f9 2F020000 .4byte 0x22f + 1018 05fd 00 .byte 0 + 1019 05fe 27 .uleb128 0x27 + 1020 05ff 01 .byte 0x1 + 1021 0600 A4020000 .4byte .LASF73 + 1022 0604 08 .byte 0x8 + 1023 0605 9C .byte 0x9c + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 19 + + + 1024 0606 01 .byte 0x1 + 1025 0607 01 .byte 0x1 + 1026 0608 25 .uleb128 0x25 + 1027 0609 2F020000 .4byte 0x22f + 1028 060d 25 .uleb128 0x25 + 1029 060e BC000000 .4byte 0xbc + 1030 0612 00 .byte 0 + 1031 0613 00 .byte 0 + 1032 .section .debug_abbrev,"",%progbits + 1033 .Ldebug_abbrev0: + 1034 0000 01 .uleb128 0x1 + 1035 0001 11 .uleb128 0x11 + 1036 0002 01 .byte 0x1 + 1037 0003 25 .uleb128 0x25 + 1038 0004 0E .uleb128 0xe + 1039 0005 13 .uleb128 0x13 + 1040 0006 0B .uleb128 0xb + 1041 0007 03 .uleb128 0x3 + 1042 0008 0E .uleb128 0xe + 1043 0009 1B .uleb128 0x1b + 1044 000a 0E .uleb128 0xe + 1045 000b 55 .uleb128 0x55 + 1046 000c 06 .uleb128 0x6 + 1047 000d 11 .uleb128 0x11 + 1048 000e 01 .uleb128 0x1 + 1049 000f 52 .uleb128 0x52 + 1050 0010 01 .uleb128 0x1 + 1051 0011 10 .uleb128 0x10 + 1052 0012 06 .uleb128 0x6 + 1053 0013 00 .byte 0 + 1054 0014 00 .byte 0 + 1055 0015 02 .uleb128 0x2 + 1056 0016 24 .uleb128 0x24 + 1057 0017 00 .byte 0 + 1058 0018 0B .uleb128 0xb + 1059 0019 0B .uleb128 0xb + 1060 001a 3E .uleb128 0x3e + 1061 001b 0B .uleb128 0xb + 1062 001c 03 .uleb128 0x3 + 1063 001d 08 .uleb128 0x8 + 1064 001e 00 .byte 0 + 1065 001f 00 .byte 0 + 1066 0020 03 .uleb128 0x3 + 1067 0021 24 .uleb128 0x24 + 1068 0022 00 .byte 0 + 1069 0023 0B .uleb128 0xb + 1070 0024 0B .uleb128 0xb + 1071 0025 3E .uleb128 0x3e + 1072 0026 0B .uleb128 0xb + 1073 0027 03 .uleb128 0x3 + 1074 0028 0E .uleb128 0xe + 1075 0029 00 .byte 0 + 1076 002a 00 .byte 0 + 1077 002b 04 .uleb128 0x4 + 1078 002c 16 .uleb128 0x16 + 1079 002d 00 .byte 0 + 1080 002e 03 .uleb128 0x3 + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 20 + + + 1081 002f 0E .uleb128 0xe + 1082 0030 3A .uleb128 0x3a + 1083 0031 0B .uleb128 0xb + 1084 0032 3B .uleb128 0x3b + 1085 0033 0B .uleb128 0xb + 1086 0034 49 .uleb128 0x49 + 1087 0035 13 .uleb128 0x13 + 1088 0036 00 .byte 0 + 1089 0037 00 .byte 0 + 1090 0038 05 .uleb128 0x5 + 1091 0039 13 .uleb128 0x13 + 1092 003a 01 .byte 0x1 + 1093 003b 03 .uleb128 0x3 + 1094 003c 0E .uleb128 0xe + 1095 003d 0B .uleb128 0xb + 1096 003e 0B .uleb128 0xb + 1097 003f 3A .uleb128 0x3a + 1098 0040 0B .uleb128 0xb + 1099 0041 3B .uleb128 0x3b + 1100 0042 0B .uleb128 0xb + 1101 0043 01 .uleb128 0x1 + 1102 0044 13 .uleb128 0x13 + 1103 0045 00 .byte 0 + 1104 0046 00 .byte 0 + 1105 0047 06 .uleb128 0x6 + 1106 0048 0D .uleb128 0xd + 1107 0049 00 .byte 0 + 1108 004a 03 .uleb128 0x3 + 1109 004b 0E .uleb128 0xe + 1110 004c 3A .uleb128 0x3a + 1111 004d 0B .uleb128 0xb + 1112 004e 3B .uleb128 0x3b + 1113 004f 0B .uleb128 0xb + 1114 0050 49 .uleb128 0x49 + 1115 0051 13 .uleb128 0x13 + 1116 0052 38 .uleb128 0x38 + 1117 0053 0A .uleb128 0xa + 1118 0054 00 .byte 0 + 1119 0055 00 .byte 0 + 1120 0056 07 .uleb128 0x7 + 1121 0057 0D .uleb128 0xd + 1122 0058 00 .byte 0 + 1123 0059 03 .uleb128 0x3 + 1124 005a 08 .uleb128 0x8 + 1125 005b 3A .uleb128 0x3a + 1126 005c 0B .uleb128 0xb + 1127 005d 3B .uleb128 0x3b + 1128 005e 0B .uleb128 0xb + 1129 005f 49 .uleb128 0x49 + 1130 0060 13 .uleb128 0x13 + 1131 0061 38 .uleb128 0x38 + 1132 0062 0A .uleb128 0xa + 1133 0063 00 .byte 0 + 1134 0064 00 .byte 0 + 1135 0065 08 .uleb128 0x8 + 1136 0066 13 .uleb128 0x13 + 1137 0067 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 21 + + + 1138 0068 0B .uleb128 0xb + 1139 0069 0B .uleb128 0xb + 1140 006a 3A .uleb128 0x3a + 1141 006b 0B .uleb128 0xb + 1142 006c 3B .uleb128 0x3b + 1143 006d 0B .uleb128 0xb + 1144 006e 01 .uleb128 0x1 + 1145 006f 13 .uleb128 0x13 + 1146 0070 00 .byte 0 + 1147 0071 00 .byte 0 + 1148 0072 09 .uleb128 0x9 + 1149 0073 0F .uleb128 0xf + 1150 0074 00 .byte 0 + 1151 0075 0B .uleb128 0xb + 1152 0076 0B .uleb128 0xb + 1153 0077 49 .uleb128 0x49 + 1154 0078 13 .uleb128 0x13 + 1155 0079 00 .byte 0 + 1156 007a 00 .byte 0 + 1157 007b 0A .uleb128 0xa + 1158 007c 0F .uleb128 0xf + 1159 007d 00 .byte 0 + 1160 007e 0B .uleb128 0xb + 1161 007f 0B .uleb128 0xb + 1162 0080 00 .byte 0 + 1163 0081 00 .byte 0 + 1164 0082 0B .uleb128 0xb + 1165 0083 0D .uleb128 0xd + 1166 0084 00 .byte 0 + 1167 0085 03 .uleb128 0x3 + 1168 0086 08 .uleb128 0x8 + 1169 0087 3A .uleb128 0x3a + 1170 0088 0B .uleb128 0xb + 1171 0089 3B .uleb128 0x3b + 1172 008a 05 .uleb128 0x5 + 1173 008b 49 .uleb128 0x49 + 1174 008c 13 .uleb128 0x13 + 1175 008d 38 .uleb128 0x38 + 1176 008e 0A .uleb128 0xa + 1177 008f 00 .byte 0 + 1178 0090 00 .byte 0 + 1179 0091 0C .uleb128 0xc + 1180 0092 13 .uleb128 0x13 + 1181 0093 01 .byte 0x1 + 1182 0094 03 .uleb128 0x3 + 1183 0095 0E .uleb128 0xe + 1184 0096 0B .uleb128 0xb + 1185 0097 0B .uleb128 0xb + 1186 0098 3A .uleb128 0x3a + 1187 0099 0B .uleb128 0xb + 1188 009a 3B .uleb128 0x3b + 1189 009b 05 .uleb128 0x5 + 1190 009c 01 .uleb128 0x1 + 1191 009d 13 .uleb128 0x13 + 1192 009e 00 .byte 0 + 1193 009f 00 .byte 0 + 1194 00a0 0D .uleb128 0xd + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 22 + + + 1195 00a1 35 .uleb128 0x35 + 1196 00a2 00 .byte 0 + 1197 00a3 49 .uleb128 0x49 + 1198 00a4 13 .uleb128 0x13 + 1199 00a5 00 .byte 0 + 1200 00a6 00 .byte 0 + 1201 00a7 0E .uleb128 0xe + 1202 00a8 17 .uleb128 0x17 + 1203 00a9 01 .byte 0x1 + 1204 00aa 0B .uleb128 0xb + 1205 00ab 0B .uleb128 0xb + 1206 00ac 3A .uleb128 0x3a + 1207 00ad 0B .uleb128 0xb + 1208 00ae 3B .uleb128 0x3b + 1209 00af 0B .uleb128 0xb + 1210 00b0 01 .uleb128 0x1 + 1211 00b1 13 .uleb128 0x13 + 1212 00b2 00 .byte 0 + 1213 00b3 00 .byte 0 + 1214 00b4 0F .uleb128 0xf + 1215 00b5 0D .uleb128 0xd + 1216 00b6 00 .byte 0 + 1217 00b7 03 .uleb128 0x3 + 1218 00b8 0E .uleb128 0xe + 1219 00b9 3A .uleb128 0x3a + 1220 00ba 0B .uleb128 0xb + 1221 00bb 3B .uleb128 0x3b + 1222 00bc 0B .uleb128 0xb + 1223 00bd 49 .uleb128 0x49 + 1224 00be 13 .uleb128 0x13 + 1225 00bf 00 .byte 0 + 1226 00c0 00 .byte 0 + 1227 00c1 10 .uleb128 0x10 + 1228 00c2 26 .uleb128 0x26 + 1229 00c3 00 .byte 0 + 1230 00c4 49 .uleb128 0x49 + 1231 00c5 13 .uleb128 0x13 + 1232 00c6 00 .byte 0 + 1233 00c7 00 .byte 0 + 1234 00c8 11 .uleb128 0x11 + 1235 00c9 2E .uleb128 0x2e + 1236 00ca 01 .byte 0x1 + 1237 00cb 03 .uleb128 0x3 + 1238 00cc 0E .uleb128 0xe + 1239 00cd 3A .uleb128 0x3a + 1240 00ce 0B .uleb128 0xb + 1241 00cf 3B .uleb128 0x3b + 1242 00d0 0B .uleb128 0xb + 1243 00d1 27 .uleb128 0x27 + 1244 00d2 0C .uleb128 0xc + 1245 00d3 20 .uleb128 0x20 + 1246 00d4 0B .uleb128 0xb + 1247 00d5 01 .uleb128 0x1 + 1248 00d6 13 .uleb128 0x13 + 1249 00d7 00 .byte 0 + 1250 00d8 00 .byte 0 + 1251 00d9 12 .uleb128 0x12 + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 23 + + + 1252 00da 05 .uleb128 0x5 + 1253 00db 00 .byte 0 + 1254 00dc 03 .uleb128 0x3 + 1255 00dd 08 .uleb128 0x8 + 1256 00de 3A .uleb128 0x3a + 1257 00df 0B .uleb128 0xb + 1258 00e0 3B .uleb128 0x3b + 1259 00e1 0B .uleb128 0xb + 1260 00e2 49 .uleb128 0x49 + 1261 00e3 13 .uleb128 0x13 + 1262 00e4 00 .byte 0 + 1263 00e5 00 .byte 0 + 1264 00e6 13 .uleb128 0x13 + 1265 00e7 2E .uleb128 0x2e + 1266 00e8 01 .byte 0x1 + 1267 00e9 03 .uleb128 0x3 + 1268 00ea 0E .uleb128 0xe + 1269 00eb 3A .uleb128 0x3a + 1270 00ec 0B .uleb128 0xb + 1271 00ed 3B .uleb128 0x3b + 1272 00ee 0B .uleb128 0xb + 1273 00ef 27 .uleb128 0x27 + 1274 00f0 0C .uleb128 0xc + 1275 00f1 49 .uleb128 0x49 + 1276 00f2 13 .uleb128 0x13 + 1277 00f3 20 .uleb128 0x20 + 1278 00f4 0B .uleb128 0xb + 1279 00f5 01 .uleb128 0x1 + 1280 00f6 13 .uleb128 0x13 + 1281 00f7 00 .byte 0 + 1282 00f8 00 .byte 0 + 1283 00f9 14 .uleb128 0x14 + 1284 00fa 34 .uleb128 0x34 + 1285 00fb 00 .byte 0 + 1286 00fc 03 .uleb128 0x3 + 1287 00fd 08 .uleb128 0x8 + 1288 00fe 3A .uleb128 0x3a + 1289 00ff 0B .uleb128 0xb + 1290 0100 3B .uleb128 0x3b + 1291 0101 0B .uleb128 0xb + 1292 0102 49 .uleb128 0x49 + 1293 0103 13 .uleb128 0x13 + 1294 0104 00 .byte 0 + 1295 0105 00 .byte 0 + 1296 0106 15 .uleb128 0x15 + 1297 0107 2E .uleb128 0x2e + 1298 0108 01 .byte 0x1 + 1299 0109 3F .uleb128 0x3f + 1300 010a 0C .uleb128 0xc + 1301 010b 03 .uleb128 0x3 + 1302 010c 0E .uleb128 0xe + 1303 010d 3A .uleb128 0x3a + 1304 010e 0B .uleb128 0xb + 1305 010f 3B .uleb128 0x3b + 1306 0110 0B .uleb128 0xb + 1307 0111 27 .uleb128 0x27 + 1308 0112 0C .uleb128 0xc + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 24 + + + 1309 0113 49 .uleb128 0x49 + 1310 0114 13 .uleb128 0x13 + 1311 0115 11 .uleb128 0x11 + 1312 0116 01 .uleb128 0x1 + 1313 0117 12 .uleb128 0x12 + 1314 0118 01 .uleb128 0x1 + 1315 0119 40 .uleb128 0x40 + 1316 011a 06 .uleb128 0x6 + 1317 011b 9742 .uleb128 0x2117 + 1318 011d 0C .uleb128 0xc + 1319 011e 01 .uleb128 0x1 + 1320 011f 13 .uleb128 0x13 + 1321 0120 00 .byte 0 + 1322 0121 00 .byte 0 + 1323 0122 16 .uleb128 0x16 + 1324 0123 05 .uleb128 0x5 + 1325 0124 00 .byte 0 + 1326 0125 03 .uleb128 0x3 + 1327 0126 08 .uleb128 0x8 + 1328 0127 3A .uleb128 0x3a + 1329 0128 0B .uleb128 0xb + 1330 0129 3B .uleb128 0x3b + 1331 012a 0B .uleb128 0xb + 1332 012b 49 .uleb128 0x49 + 1333 012c 13 .uleb128 0x13 + 1334 012d 02 .uleb128 0x2 + 1335 012e 06 .uleb128 0x6 + 1336 012f 00 .byte 0 + 1337 0130 00 .byte 0 + 1338 0131 17 .uleb128 0x17 + 1339 0132 34 .uleb128 0x34 + 1340 0133 00 .byte 0 + 1341 0134 03 .uleb128 0x3 + 1342 0135 08 .uleb128 0x8 + 1343 0136 3A .uleb128 0x3a + 1344 0137 0B .uleb128 0xb + 1345 0138 3B .uleb128 0x3b + 1346 0139 0B .uleb128 0xb + 1347 013a 49 .uleb128 0x49 + 1348 013b 13 .uleb128 0x13 + 1349 013c 02 .uleb128 0x2 + 1350 013d 0A .uleb128 0xa + 1351 013e 00 .byte 0 + 1352 013f 00 .byte 0 + 1353 0140 18 .uleb128 0x18 + 1354 0141 1D .uleb128 0x1d + 1355 0142 01 .byte 0x1 + 1356 0143 31 .uleb128 0x31 + 1357 0144 13 .uleb128 0x13 + 1358 0145 52 .uleb128 0x52 + 1359 0146 01 .uleb128 0x1 + 1360 0147 55 .uleb128 0x55 + 1361 0148 06 .uleb128 0x6 + 1362 0149 58 .uleb128 0x58 + 1363 014a 0B .uleb128 0xb + 1364 014b 59 .uleb128 0x59 + 1365 014c 0B .uleb128 0xb + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 25 + + + 1366 014d 01 .uleb128 0x1 + 1367 014e 13 .uleb128 0x13 + 1368 014f 00 .byte 0 + 1369 0150 00 .byte 0 + 1370 0151 19 .uleb128 0x19 + 1371 0152 05 .uleb128 0x5 + 1372 0153 00 .byte 0 + 1373 0154 31 .uleb128 0x31 + 1374 0155 13 .uleb128 0x13 + 1375 0156 02 .uleb128 0x2 + 1376 0157 0A .uleb128 0xa + 1377 0158 00 .byte 0 + 1378 0159 00 .byte 0 + 1379 015a 1A .uleb128 0x1a + 1380 015b 898201 .uleb128 0x4109 + 1381 015e 01 .byte 0x1 + 1382 015f 11 .uleb128 0x11 + 1383 0160 01 .uleb128 0x1 + 1384 0161 31 .uleb128 0x31 + 1385 0162 13 .uleb128 0x13 + 1386 0163 01 .uleb128 0x1 + 1387 0164 13 .uleb128 0x13 + 1388 0165 00 .byte 0 + 1389 0166 00 .byte 0 + 1390 0167 1B .uleb128 0x1b + 1391 0168 8A8201 .uleb128 0x410a + 1392 016b 00 .byte 0 + 1393 016c 02 .uleb128 0x2 + 1394 016d 0A .uleb128 0xa + 1395 016e 9142 .uleb128 0x2111 + 1396 0170 0A .uleb128 0xa + 1397 0171 00 .byte 0 + 1398 0172 00 .byte 0 + 1399 0173 1C .uleb128 0x1c + 1400 0174 898201 .uleb128 0x4109 + 1401 0177 00 .byte 0 + 1402 0178 11 .uleb128 0x11 + 1403 0179 01 .uleb128 0x1 + 1404 017a 31 .uleb128 0x31 + 1405 017b 13 .uleb128 0x13 + 1406 017c 00 .byte 0 + 1407 017d 00 .byte 0 + 1408 017e 1D .uleb128 0x1d + 1409 017f 1D .uleb128 0x1d + 1410 0180 01 .byte 0x1 + 1411 0181 31 .uleb128 0x31 + 1412 0182 13 .uleb128 0x13 + 1413 0183 11 .uleb128 0x11 + 1414 0184 01 .uleb128 0x1 + 1415 0185 12 .uleb128 0x12 + 1416 0186 01 .uleb128 0x1 + 1417 0187 58 .uleb128 0x58 + 1418 0188 0B .uleb128 0xb + 1419 0189 59 .uleb128 0x59 + 1420 018a 0B .uleb128 0xb + 1421 018b 01 .uleb128 0x1 + 1422 018c 13 .uleb128 0x13 + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 26 + + + 1423 018d 00 .byte 0 + 1424 018e 00 .byte 0 + 1425 018f 1E .uleb128 0x1e + 1426 0190 05 .uleb128 0x5 + 1427 0191 00 .byte 0 + 1428 0192 31 .uleb128 0x31 + 1429 0193 13 .uleb128 0x13 + 1430 0194 02 .uleb128 0x2 + 1431 0195 06 .uleb128 0x6 + 1432 0196 00 .byte 0 + 1433 0197 00 .byte 0 + 1434 0198 1F .uleb128 0x1f + 1435 0199 0B .uleb128 0xb + 1436 019a 01 .byte 0x1 + 1437 019b 11 .uleb128 0x11 + 1438 019c 01 .uleb128 0x1 + 1439 019d 12 .uleb128 0x12 + 1440 019e 01 .uleb128 0x1 + 1441 019f 00 .byte 0 + 1442 01a0 00 .byte 0 + 1443 01a1 20 .uleb128 0x20 + 1444 01a2 34 .uleb128 0x34 + 1445 01a3 00 .byte 0 + 1446 01a4 31 .uleb128 0x31 + 1447 01a5 13 .uleb128 0x13 + 1448 01a6 02 .uleb128 0x2 + 1449 01a7 06 .uleb128 0x6 + 1450 01a8 00 .byte 0 + 1451 01a9 00 .byte 0 + 1452 01aa 21 .uleb128 0x21 + 1453 01ab 898201 .uleb128 0x4109 + 1454 01ae 01 .byte 0x1 + 1455 01af 11 .uleb128 0x11 + 1456 01b0 01 .uleb128 0x1 + 1457 01b1 31 .uleb128 0x31 + 1458 01b2 13 .uleb128 0x13 + 1459 01b3 00 .byte 0 + 1460 01b4 00 .byte 0 + 1461 01b5 22 .uleb128 0x22 + 1462 01b6 2E .uleb128 0x2e + 1463 01b7 01 .byte 0x1 + 1464 01b8 3F .uleb128 0x3f + 1465 01b9 0C .uleb128 0xc + 1466 01ba 03 .uleb128 0x3 + 1467 01bb 0E .uleb128 0xe + 1468 01bc 3A .uleb128 0x3a + 1469 01bd 0B .uleb128 0xb + 1470 01be 3B .uleb128 0x3b + 1471 01bf 0B .uleb128 0xb + 1472 01c0 27 .uleb128 0x27 + 1473 01c1 0C .uleb128 0xc + 1474 01c2 11 .uleb128 0x11 + 1475 01c3 01 .uleb128 0x1 + 1476 01c4 12 .uleb128 0x12 + 1477 01c5 01 .uleb128 0x1 + 1478 01c6 40 .uleb128 0x40 + 1479 01c7 06 .uleb128 0x6 + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 27 + + + 1480 01c8 9742 .uleb128 0x2117 + 1481 01ca 0C .uleb128 0xc + 1482 01cb 01 .uleb128 0x1 + 1483 01cc 13 .uleb128 0x13 + 1484 01cd 00 .byte 0 + 1485 01ce 00 .byte 0 + 1486 01cf 23 .uleb128 0x23 + 1487 01d0 34 .uleb128 0x34 + 1488 01d1 00 .byte 0 + 1489 01d2 03 .uleb128 0x3 + 1490 01d3 0E .uleb128 0xe + 1491 01d4 3A .uleb128 0x3a + 1492 01d5 0B .uleb128 0xb + 1493 01d6 3B .uleb128 0x3b + 1494 01d7 0B .uleb128 0xb + 1495 01d8 49 .uleb128 0x49 + 1496 01d9 13 .uleb128 0x13 + 1497 01da 3F .uleb128 0x3f + 1498 01db 0C .uleb128 0xc + 1499 01dc 3C .uleb128 0x3c + 1500 01dd 0C .uleb128 0xc + 1501 01de 00 .byte 0 + 1502 01df 00 .byte 0 + 1503 01e0 24 .uleb128 0x24 + 1504 01e1 2E .uleb128 0x2e + 1505 01e2 01 .byte 0x1 + 1506 01e3 3F .uleb128 0x3f + 1507 01e4 0C .uleb128 0xc + 1508 01e5 03 .uleb128 0x3 + 1509 01e6 0E .uleb128 0xe + 1510 01e7 3A .uleb128 0x3a + 1511 01e8 0B .uleb128 0xb + 1512 01e9 3B .uleb128 0x3b + 1513 01ea 0B .uleb128 0xb + 1514 01eb 27 .uleb128 0x27 + 1515 01ec 0C .uleb128 0xc + 1516 01ed 3C .uleb128 0x3c + 1517 01ee 0C .uleb128 0xc + 1518 01ef 01 .uleb128 0x1 + 1519 01f0 13 .uleb128 0x13 + 1520 01f1 00 .byte 0 + 1521 01f2 00 .byte 0 + 1522 01f3 25 .uleb128 0x25 + 1523 01f4 05 .uleb128 0x5 + 1524 01f5 00 .byte 0 + 1525 01f6 49 .uleb128 0x49 + 1526 01f7 13 .uleb128 0x13 + 1527 01f8 00 .byte 0 + 1528 01f9 00 .byte 0 + 1529 01fa 26 .uleb128 0x26 + 1530 01fb 2E .uleb128 0x2e + 1531 01fc 01 .byte 0x1 + 1532 01fd 3F .uleb128 0x3f + 1533 01fe 0C .uleb128 0xc + 1534 01ff 03 .uleb128 0x3 + 1535 0200 0E .uleb128 0xe + 1536 0201 3A .uleb128 0x3a + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 28 + + + 1537 0202 0B .uleb128 0xb + 1538 0203 3B .uleb128 0x3b + 1539 0204 0B .uleb128 0xb + 1540 0205 27 .uleb128 0x27 + 1541 0206 0C .uleb128 0xc + 1542 0207 49 .uleb128 0x49 + 1543 0208 13 .uleb128 0x13 + 1544 0209 3C .uleb128 0x3c + 1545 020a 0C .uleb128 0xc + 1546 020b 01 .uleb128 0x1 + 1547 020c 13 .uleb128 0x13 + 1548 020d 00 .byte 0 + 1549 020e 00 .byte 0 + 1550 020f 27 .uleb128 0x27 + 1551 0210 2E .uleb128 0x2e + 1552 0211 01 .byte 0x1 + 1553 0212 3F .uleb128 0x3f + 1554 0213 0C .uleb128 0xc + 1555 0214 03 .uleb128 0x3 + 1556 0215 0E .uleb128 0xe + 1557 0216 3A .uleb128 0x3a + 1558 0217 0B .uleb128 0xb + 1559 0218 3B .uleb128 0x3b + 1560 0219 0B .uleb128 0xb + 1561 021a 27 .uleb128 0x27 + 1562 021b 0C .uleb128 0xc + 1563 021c 3C .uleb128 0x3c + 1564 021d 0C .uleb128 0xc + 1565 021e 00 .byte 0 + 1566 021f 00 .byte 0 + 1567 0220 00 .byte 0 + 1568 .section .debug_loc,"",%progbits + 1569 .Ldebug_loc0: + 1570 .LLST0: + 1571 0000 00000000 .4byte .LFB7 + 1572 0004 02000000 .4byte .LCFI0 + 1573 0008 0200 .2byte 0x2 + 1574 000a 7D .byte 0x7d + 1575 000b 00 .sleb128 0 + 1576 000c 02000000 .4byte .LCFI0 + 1577 0010 38000000 .4byte .LFE7 + 1578 0014 0200 .2byte 0x2 + 1579 0016 7D .byte 0x7d + 1580 0017 10 .sleb128 16 + 1581 0018 00000000 .4byte 0 + 1582 001c 00000000 .4byte 0 + 1583 .LLST1: + 1584 0020 00000000 .4byte .LVL0 + 1585 0024 20000000 .4byte .LVL3 + 1586 0028 0100 .2byte 0x1 + 1587 002a 50 .byte 0x50 + 1588 002b 20000000 .4byte .LVL3 + 1589 002f 2C000000 .4byte .LVL6 + 1590 0033 0300 .2byte 0x3 + 1591 0035 75 .byte 0x75 + 1592 0036 54 .sleb128 -44 + 1593 0037 9F .byte 0x9f + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 29 + + + 1594 0038 2C000000 .4byte .LVL6 + 1595 003c 2F000000 .4byte .LVL7-1 + 1596 0040 0100 .2byte 0x1 + 1597 0042 50 .byte 0x50 + 1598 0043 2F000000 .4byte .LVL7-1 + 1599 0047 38000000 .4byte .LFE7 + 1600 004b 0300 .2byte 0x3 + 1601 004d 75 .byte 0x75 + 1602 004e 54 .sleb128 -44 + 1603 004f 9F .byte 0x9f + 1604 0050 00000000 .4byte 0 + 1605 0054 00000000 .4byte 0 + 1606 .LLST2: + 1607 0058 00000000 .4byte .LVL0 + 1608 005c 20000000 .4byte .LVL3 + 1609 0060 0100 .2byte 0x1 + 1610 0062 51 .byte 0x51 + 1611 0063 20000000 .4byte .LVL3 + 1612 0067 28000000 .4byte .LVL5 + 1613 006b 0400 .2byte 0x4 + 1614 006d F3 .byte 0xf3 + 1615 006e 01 .uleb128 0x1 + 1616 006f 51 .byte 0x51 + 1617 0070 9F .byte 0x9f + 1618 0071 28000000 .4byte .LVL5 + 1619 0075 2C000000 .4byte .LVL6 + 1620 0079 0100 .2byte 0x1 + 1621 007b 50 .byte 0x50 + 1622 007c 2C000000 .4byte .LVL6 + 1623 0080 2F000000 .4byte .LVL7-1 + 1624 0084 0100 .2byte 0x1 + 1625 0086 51 .byte 0x51 + 1626 0087 2F000000 .4byte .LVL7-1 + 1627 008b 38000000 .4byte .LFE7 + 1628 008f 0400 .2byte 0x4 + 1629 0091 F3 .byte 0xf3 + 1630 0092 01 .uleb128 0x1 + 1631 0093 51 .byte 0x51 + 1632 0094 9F .byte 0x9f + 1633 0095 00000000 .4byte 0 + 1634 0099 00000000 .4byte 0 + 1635 .LLST3: + 1636 009d 00000000 .4byte .LFB8 + 1637 00a1 02000000 .4byte .LCFI1 + 1638 00a5 0200 .2byte 0x2 + 1639 00a7 7D .byte 0x7d + 1640 00a8 00 .sleb128 0 + 1641 00a9 02000000 .4byte .LCFI1 + 1642 00ad 34000000 .4byte .LFE8 + 1643 00b1 0200 .2byte 0x2 + 1644 00b3 7D .byte 0x7d + 1645 00b4 08 .sleb128 8 + 1646 00b5 00000000 .4byte 0 + 1647 00b9 00000000 .4byte 0 + 1648 .LLST4: + 1649 00bd 12000000 .4byte .LVL8 + 1650 00c1 20000000 .4byte .LVL9 + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 30 + + + 1651 00c5 0300 .2byte 0x3 + 1652 00c7 72 .byte 0x72 + 1653 00c8 2C .sleb128 44 + 1654 00c9 9F .byte 0x9f + 1655 00ca 00000000 .4byte 0 + 1656 00ce 00000000 .4byte 0 + 1657 .LLST5: + 1658 00d2 12000000 .4byte .LVL8 + 1659 00d6 20000000 .4byte .LVL9 + 1660 00da 0100 .2byte 0x1 + 1661 00dc 50 .byte 0x50 + 1662 00dd 00000000 .4byte 0 + 1663 00e1 00000000 .4byte 0 + 1664 .LLST6: + 1665 00e5 00000000 .4byte .LFB9 + 1666 00e9 02000000 .4byte .LCFI2 + 1667 00ed 0200 .2byte 0x2 + 1668 00ef 7D .byte 0x7d + 1669 00f0 00 .sleb128 0 + 1670 00f1 02000000 .4byte .LCFI2 + 1671 00f5 0C000000 .4byte .LFE9 + 1672 00f9 0200 .2byte 0x2 + 1673 00fb 7D .byte 0x7d + 1674 00fc 08 .sleb128 8 + 1675 00fd 00000000 .4byte 0 + 1676 0101 00000000 .4byte 0 + 1677 .LLST7: + 1678 0105 00000000 .4byte .LVL11 + 1679 0109 07000000 .4byte .LVL12-1 + 1680 010d 0100 .2byte 0x1 + 1681 010f 50 .byte 0x50 + 1682 0110 07000000 .4byte .LVL12-1 + 1683 0114 0C000000 .4byte .LFE9 + 1684 0118 0400 .2byte 0x4 + 1685 011a F3 .byte 0xf3 + 1686 011b 01 .uleb128 0x1 + 1687 011c 50 .byte 0x50 + 1688 011d 9F .byte 0x9f + 1689 011e 00000000 .4byte 0 + 1690 0122 00000000 .4byte 0 + 1691 .LLST8: + 1692 0126 00000000 .4byte .LVL11 + 1693 012a 07000000 .4byte .LVL12-1 + 1694 012e 0100 .2byte 0x1 + 1695 0130 51 .byte 0x51 + 1696 0131 07000000 .4byte .LVL12-1 + 1697 0135 0C000000 .4byte .LFE9 + 1698 0139 0400 .2byte 0x4 + 1699 013b F3 .byte 0xf3 + 1700 013c 01 .uleb128 0x1 + 1701 013d 51 .byte 0x51 + 1702 013e 9F .byte 0x9f + 1703 013f 00000000 .4byte 0 + 1704 0143 00000000 .4byte 0 + 1705 .section .debug_aranges,"",%progbits + 1706 0000 2C000000 .4byte 0x2c + 1707 0004 0200 .2byte 0x2 + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 31 + + + 1708 0006 00000000 .4byte .Ldebug_info0 + 1709 000a 04 .byte 0x4 + 1710 000b 00 .byte 0 + 1711 000c 0000 .2byte 0 + 1712 000e 0000 .2byte 0 + 1713 0010 00000000 .4byte .LFB7 + 1714 0014 38000000 .4byte .LFE7-.LFB7 + 1715 0018 00000000 .4byte .LFB8 + 1716 001c 34000000 .4byte .LFE8-.LFB8 + 1717 0020 00000000 .4byte .LFB9 + 1718 0024 0C000000 .4byte .LFE9-.LFB9 + 1719 0028 00000000 .4byte 0 + 1720 002c 00000000 .4byte 0 + 1721 .section .debug_ranges,"",%progbits + 1722 .Ldebug_ranges0: + 1723 0000 10000000 .4byte .LBB6 + 1724 0004 12000000 .4byte .LBE6 + 1725 0008 14000000 .4byte .LBB10 + 1726 000c 16000000 .4byte .LBE10 + 1727 0010 18000000 .4byte .LBB11 + 1728 0014 1E000000 .4byte .LBE11 + 1729 0018 00000000 .4byte 0 + 1730 001c 00000000 .4byte 0 + 1731 0020 00000000 .4byte .LFB7 + 1732 0024 38000000 .4byte .LFE7 + 1733 0028 00000000 .4byte .LFB8 + 1734 002c 34000000 .4byte .LFE8 + 1735 0030 00000000 .4byte .LFB9 + 1736 0034 0C000000 .4byte .LFE9 + 1737 0038 00000000 .4byte 0 + 1738 003c 00000000 .4byte 0 + 1739 .section .debug_line,"",%progbits + 1740 .Ldebug_line0: + 1741 0000 74010000 .section .debug_str,"MS",%progbits,1 + 1741 02000401 + 1741 00000201 + 1741 FB0E0D00 + 1741 01010101 + 1742 .LASF34: + 1743 0000 705F6D73 .ascii "p_msg\000" + 1743 6700 + 1744 .LASF67: + 1745 0006 71756575 .ascii "queue_insert\000" + 1745 655F696E + 1745 73657274 + 1745 00 + 1746 .LASF57: + 1747 0013 7264796D .ascii "rdymsg\000" + 1747 736700 + 1748 .LASF11: + 1749 001a 6C6F6E67 .ascii "long long unsigned int\000" + 1749 206C6F6E + 1749 6720756E + 1749 7369676E + 1749 65642069 + 1750 .LASF58: + 1751 0031 65786974 .ascii "exitcode\000" + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 32 + + + 1751 636F6465 + 1751 00 + 1752 .LASF23: + 1753 003a 705F7072 .ascii "p_prio\000" + 1753 696F00 + 1754 .LASF10: + 1755 0041 6C6F6E67 .ascii "long long int\000" + 1755 206C6F6E + 1755 6720696E + 1755 7400 + 1756 .LASF1: + 1757 004f 7369676E .ascii "signed char\000" + 1757 65642063 + 1757 68617200 + 1758 .LASF38: + 1759 005b 705F6D70 .ascii "p_mpool\000" + 1759 6F6F6C00 + 1760 .LASF54: + 1761 0063 6D5F7175 .ascii "m_queue\000" + 1761 65756500 + 1762 .LASF65: + 1763 006b 2E2E2F2E .ascii "../..//os/kernel/src/chmsg.c\000" + 1763 2E2F2F6F + 1763 732F6B65 + 1763 726E656C + 1763 2F737263 + 1764 .LASF7: + 1765 0088 6C6F6E67 .ascii "long int\000" + 1765 20696E74 + 1765 00 + 1766 .LASF62: + 1767 0091 63684D73 .ascii "chMsgSend\000" + 1767 6753656E + 1767 6400 + 1768 .LASF13: + 1769 009b 74737461 .ascii "tstate_t\000" + 1769 74655F74 + 1769 00 + 1770 .LASF25: + 1771 00a4 705F6E65 .ascii "p_newer\000" + 1771 77657200 + 1772 .LASF48: + 1773 00ac 725F6E65 .ascii "r_newer\000" + 1773 77657200 + 1774 .LASF41: + 1775 00b4 72656761 .ascii "regarm_t\000" + 1775 726D5F74 + 1775 00 + 1776 .LASF19: + 1777 00bd 636E745F .ascii "cnt_t\000" + 1777 7400 + 1778 .LASF0: + 1779 00c3 756E7369 .ascii "unsigned int\000" + 1779 676E6564 + 1779 20696E74 + 1779 00 + 1780 .LASF9: + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 33 + + + 1781 00d0 6C6F6E67 .ascii "long unsigned int\000" + 1781 20756E73 + 1781 69676E65 + 1781 6420696E + 1781 7400 + 1782 .LASF43: + 1783 00e2 636F6E74 .ascii "context\000" + 1783 65787400 + 1784 .LASF4: + 1785 00ea 73686F72 .ascii "short unsigned int\000" + 1785 7420756E + 1785 7369676E + 1785 65642069 + 1785 6E7400 + 1786 .LASF16: + 1787 00fd 6D73675F .ascii "msg_t\000" + 1787 7400 + 1788 .LASF12: + 1789 0103 746D6F64 .ascii "tmode_t\000" + 1789 655F7400 + 1790 .LASF40: + 1791 010b 54687265 .ascii "ThreadsList\000" + 1791 6164734C + 1791 69737400 + 1792 .LASF17: + 1793 0117 6576656E .ascii "eventmask_t\000" + 1793 746D6173 + 1793 6B5F7400 + 1794 .LASF53: + 1795 0123 4D757465 .ascii "Mutex\000" + 1795 7800 + 1796 .LASF44: + 1797 0129 73697A65 .ascii "sizetype\000" + 1797 74797065 + 1797 00 + 1798 .LASF26: + 1799 0132 705F6F6C .ascii "p_older\000" + 1799 64657200 + 1800 .LASF66: + 1801 013a 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 1801 73657273 + 1801 5C496D61 + 1801 6E6F6C5C + 1801 64657665 + 1802 0167 6C696361 .ascii "lications\\smartcities\000" + 1802 74696F6E + 1802 735C736D + 1802 61727463 + 1802 69746965 + 1803 .LASF39: + 1804 017d 54687265 .ascii "ThreadsQueue\000" + 1804 61647351 + 1804 75657565 + 1804 00 + 1805 .LASF64: + 1806 018a 474E5520 .ascii "GNU C 4.7.2\000" + 1806 4320342E + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 34 + + + 1806 372E3200 + 1807 .LASF51: + 1808 0196 725F6375 .ascii "r_current\000" + 1808 7272656E + 1808 7400 + 1809 .LASF49: + 1810 01a0 725F6F6C .ascii "r_older\000" + 1810 64657200 + 1811 .LASF14: + 1812 01a8 74726566 .ascii "trefs_t\000" + 1812 735F7400 + 1813 .LASF22: + 1814 01b0 705F7072 .ascii "p_prev\000" + 1814 657600 + 1815 .LASF15: + 1816 01b7 74707269 .ascii "tprio_t\000" + 1816 6F5F7400 + 1817 .LASF6: + 1818 01bf 696E7433 .ascii "int32_t\000" + 1818 325F7400 + 1819 .LASF2: + 1820 01c7 756E7369 .ascii "unsigned char\000" + 1820 676E6564 + 1820 20636861 + 1820 7200 + 1821 .LASF36: + 1822 01d5 705F6D74 .ascii "p_mtxlist\000" + 1822 786C6973 + 1822 7400 + 1823 .LASF3: + 1824 01df 73686F72 .ascii "short int\000" + 1824 7420696E + 1824 7400 + 1825 .LASF28: + 1826 01e9 705F7374 .ascii "p_state\000" + 1826 61746500 + 1827 .LASF46: + 1828 01f1 725F7072 .ascii "r_prio\000" + 1828 696F00 + 1829 .LASF60: + 1830 01f8 65776D61 .ascii "ewmask\000" + 1830 736B00 + 1831 .LASF21: + 1832 01ff 705F6E65 .ascii "p_next\000" + 1832 787400 + 1833 .LASF29: + 1834 0206 705F666C .ascii "p_flags\000" + 1834 61677300 + 1835 .LASF20: + 1836 020e 54687265 .ascii "Thread\000" + 1836 616400 + 1837 .LASF69: + 1838 0215 63684D73 .ascii "chMsgRelease\000" + 1838 6752656C + 1838 65617365 + 1838 00 + 1839 .LASF71: + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 35 + + + 1840 0222 63685363 .ascii "chSchGoSleepS\000" + 1840 68476F53 + 1840 6C656570 + 1840 5300 + 1841 .LASF35: + 1842 0230 705F6570 .ascii "p_epending\000" + 1842 656E6469 + 1842 6E6700 + 1843 .LASF8: + 1844 023b 75696E74 .ascii "uint32_t\000" + 1844 33325F74 + 1844 00 + 1845 .LASF45: + 1846 0244 725F7175 .ascii "r_queue\000" + 1846 65756500 + 1847 .LASF72: + 1848 024c 63685363 .ascii "chSchReadyI\000" + 1848 68526561 + 1848 64794900 + 1849 .LASF61: + 1850 0258 63686172 .ascii "char\000" + 1850 00 + 1851 .LASF68: + 1852 025d 6669666F .ascii "fifo_remove\000" + 1852 5F72656D + 1852 6F766500 + 1853 .LASF56: + 1854 0269 6D5F6E65 .ascii "m_next\000" + 1854 787400 + 1855 .LASF18: + 1856 0270 73797374 .ascii "systime_t\000" + 1856 696D655F + 1856 7400 + 1857 .LASF37: + 1858 027a 705F7265 .ascii "p_realprio\000" + 1858 616C7072 + 1858 696F00 + 1859 .LASF31: + 1860 0285 705F7469 .ascii "p_time\000" + 1860 6D6500 + 1861 .LASF47: + 1862 028c 725F6374 .ascii "r_ctx\000" + 1862 7800 + 1863 .LASF42: + 1864 0292 696E7463 .ascii "intctx\000" + 1864 747800 + 1865 .LASF33: + 1866 0299 705F6D73 .ascii "p_msgqueue\000" + 1866 67717565 + 1866 756500 + 1867 .LASF73: + 1868 02a4 63685363 .ascii "chSchWakeupS\000" + 1868 6857616B + 1868 65757053 + 1868 00 + 1869 .LASF63: + 1870 02b1 63684D73 .ascii "chMsgWait\000" + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 36 + + + 1870 67576169 + 1870 7400 + 1871 .LASF30: + 1872 02bb 705F7265 .ascii "p_refs\000" + 1872 667300 + 1873 .LASF52: + 1874 02c2 52656164 .ascii "ReadyList\000" + 1874 794C6973 + 1874 7400 + 1875 .LASF70: + 1876 02cc 726C6973 .ascii "rlist\000" + 1876 7400 + 1877 .LASF5: + 1878 02d2 75696E74 .ascii "uint8_t\000" + 1878 385F7400 + 1879 .LASF59: + 1880 02da 77746F62 .ascii "wtobjp\000" + 1880 6A7000 + 1881 .LASF27: + 1882 02e1 705F6E61 .ascii "p_name\000" + 1882 6D6500 + 1883 .LASF50: + 1884 02e8 725F7072 .ascii "r_preempt\000" + 1884 65656D70 + 1884 7400 + 1885 .LASF55: + 1886 02f2 6D5F6F77 .ascii "m_owner\000" + 1886 6E657200 + 1887 .LASF24: + 1888 02fa 705F6374 .ascii "p_ctx\000" + 1888 7800 + 1889 .LASF32: + 1890 0300 705F7761 .ascii "p_waiting\000" + 1890 6974696E + 1890 6700 + 1891 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\cc1efFDI.s page 37 + + +DEFINED SYMBOLS + *ABS*:00000000 chmsg.c +C:\cygwin\tmp\cc1efFDI.s:19 .text.chMsgSend:00000000 $t +C:\cygwin\tmp\cc1efFDI.s:25 .text.chMsgSend:00000000 chMsgSend +C:\cygwin\tmp\cc1efFDI.s:108 .text.chMsgSend:00000034 $d +C:\cygwin\tmp\cc1efFDI.s:113 .text.chMsgWait:00000000 $t +C:\cygwin\tmp\cc1efFDI.s:119 .text.chMsgWait:00000000 chMsgWait +C:\cygwin\tmp\cc1efFDI.s:175 .text.chMsgWait:00000030 $d +C:\cygwin\tmp\cc1efFDI.s:180 .text.chMsgRelease:00000000 $t +C:\cygwin\tmp\cc1efFDI.s:186 .text.chMsgRelease:00000000 chMsgRelease + .debug_frame:00000010 $d +C:\cygwin\tmp\cc1efFDI.s:112 .text.chMsgSend:00000038 $t +C:\cygwin\tmp\cc1efFDI.s:179 .text.chMsgWait:00000034 $t + +UNDEFINED SYMBOLS +chSchGoSleepS +chSchReadyI +rlist +chSchWakeupS diff --git a/Project/applications/smartcities/build/lst/chmtx.lst b/Project/applications/smartcities/build/lst/chmtx.lst new file mode 100644 index 0000000..5a6397c --- /dev/null +++ b/Project/applications/smartcities/build/lst/chmtx.lst @@ -0,0 +1,3896 @@ +ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "chmtx.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text.chMtxInit,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .global chMtxInit + 22 .thumb + 23 .thumb_func + 24 .type chMtxInit, %function + 25 chMtxInit: + 26 .LFB7: + 27 .file 1 "../..//os/kernel/src/chmtx.c" + 28 .loc 1 86 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .LVL0: + 34 .loc 1 91 0 + 35 0000 0023 movs r3, #0 + 36 .loc 1 90 0 + 37 0002 4060 str r0, [r0, #4] + 38 0004 0060 str r0, [r0, #0] + 39 .loc 1 91 0 + 40 0006 8360 str r3, [r0, #8] + 41 0008 7047 bx lr + 42 .cfi_endproc + 43 .LFE7: + 44 .size chMtxInit, .-chMtxInit + 45 000a 00BFAFF3 .section .text.chMtxLockS,"ax",%progbits + 45 0080 + 46 .align 2 + 47 .p2align 4,,15 + 48 .global chMtxLockS + 49 .thumb + 50 .thumb_func + 51 .type chMtxLockS, %function + 52 chMtxLockS: + 53 .LFB9: + 54 .loc 1 121 0 + 55 .cfi_startproc + 56 @ args = 0, pretend = 0, frame = 0 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 2 + + + 57 @ frame_needed = 0, uses_anonymous_args = 0 + 58 .LVL1: + 59 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 60 .LCFI0: + 61 .cfi_def_cfa_offset 24 + 62 .cfi_offset 3, -24 + 63 .cfi_offset 4, -20 + 64 .cfi_offset 5, -16 + 65 .cfi_offset 6, -12 + 66 .cfi_offset 7, -8 + 67 .cfi_offset 14, -4 + 68 .loc 1 122 0 + 69 0002 2F4A ldr r2, .L27 + 70 .loc 1 128 0 + 71 0004 8368 ldr r3, [r0, #8] + 72 .loc 1 121 0 + 73 0006 0546 mov r5, r0 + 74 .loc 1 122 0 + 75 0008 D469 ldr r4, [r2, #28] + 76 .LVL2: + 77 .loc 1 128 0 + 78 000a 002B cmp r3, #0 + 79 000c 51D0 beq .L3 + 80 .LVL3: + 81 .LBB27: + 82 .loc 1 135 0 discriminator 1 + 83 000e A168 ldr r1, [r4, #8] + 84 0010 9A68 ldr r2, [r3, #8] + 85 0012 9142 cmp r1, r2 + 86 0014 06D9 bls .L5 + 87 .LVL4: + 88 .L20: + 89 .loc 1 139 0 + 90 0016 1A7F ldrb r2, [r3, #28] @ zero_extendqisi2 + 91 .loc 1 137 0 + 92 0018 9960 str r1, [r3, #8] + 93 .loc 1 139 0 + 94 001a 042A cmp r2, #4 + 95 001c 31D0 beq .L7 + 96 001e 052A cmp r2, #5 + 97 0020 1CD0 beq .L8 + 98 0022 92B1 cbz r2, .L6 + 99 .LVL5: + 100 .L5: + 101 .file 2 "../..//os/kernel/include/chinline.h" + 102 .loc 2 43 0 + 103 0024 2B46 mov r3, r5 + 104 .LVL6: + 105 .L18: + 106 .LBB28: + 107 .LBB29: + 108 .loc 2 45 0 + 109 0026 1B68 ldr r3, [r3, #0] + 110 .LVL7: + 111 .loc 2 46 0 + 112 0028 9D42 cmp r5, r3 + 113 002a 03D0 beq .L19 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 3 + + + 114 002c 9968 ldr r1, [r3, #8] + 115 002e A268 ldr r2, [r4, #8] + 116 0030 9142 cmp r1, r2 + 117 0032 F8D2 bcs .L18 + 118 .L19: + 119 .loc 2 48 0 + 120 0034 5A68 ldr r2, [r3, #4] + 121 .LBE29: + 122 .LBE28: + 123 .loc 1 175 0 + 124 0036 0420 movs r0, #4 + 125 .LBB31: + 126 .LBB30: + 127 .loc 2 47 0 + 128 0038 2360 str r3, [r4, #0] + 129 .loc 2 48 0 + 130 003a 6260 str r2, [r4, #4] + 131 .loc 2 49 0 + 132 003c 1460 str r4, [r2, #0] + 133 003e 5C60 str r4, [r3, #4] + 134 .LBE30: + 135 .LBE31: + 136 .loc 1 174 0 + 137 0040 6562 str r5, [r4, #36] + 138 .LBE27: + 139 .loc 1 187 0 + 140 0042 BDE8F840 pop {r3, r4, r5, r6, r7, lr} + 141 .LBB54: + 142 .loc 1 175 0 + 143 0046 FFF7FEBF b chSchGoSleepS + 144 .LVL8: + 145 .L6: + 146 .LBB32: + 147 .LBB33: + 148 .loc 2 75 0 + 149 004a 93E80600 ldmia r3, {r1, r2} + 150 004e 1160 str r1, [r2, #0] + 151 .LBE33: + 152 .LBE32: + 153 .loc 1 167 0 + 154 0050 1846 mov r0, r3 + 155 .LBB35: + 156 .LBB34: + 157 .loc 2 76 0 + 158 0052 1B68 ldr r3, [r3, #0] + 159 .LVL9: + 160 0054 5A60 str r2, [r3, #4] + 161 .LBE34: + 162 .LBE35: + 163 .loc 1 167 0 + 164 0056 FFF7FEFF bl chSchReadyI + 165 .LVL10: + 166 .loc 1 168 0 + 167 005a E3E7 b .L5 + 168 .LVL11: + 169 .L8: + 170 .LBB36: + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 4 + + + 171 .LBB37: + 172 .loc 2 75 0 + 173 005c 5868 ldr r0, [r3, #4] + 174 005e 1A68 ldr r2, [r3, #0] + 175 .LBE37: + 176 .LBE36: + 177 .loc 1 158 0 + 178 0060 5E6A ldr r6, [r3, #36] + 179 .LVL12: + 180 .LBB40: + 181 .LBB38: + 182 .loc 2 75 0 + 183 0062 0260 str r2, [r0, #0] + 184 .loc 2 76 0 + 185 0064 1F68 ldr r7, [r3, #0] + 186 .LBE38: + 187 .LBE40: + 188 .loc 2 43 0 + 189 0066 3246 mov r2, r6 + 190 .LBB41: + 191 .LBB39: + 192 .loc 2 76 0 + 193 0068 7860 str r0, [r7, #4] + 194 .LVL13: + 195 .L15: + 196 .LBE39: + 197 .LBE41: + 198 .LBB42: + 199 .LBB43: + 200 .loc 2 45 0 + 201 006a 1268 ldr r2, [r2, #0] + 202 .LVL14: + 203 .loc 2 46 0 + 204 006c 9642 cmp r6, r2 + 205 006e 02D0 beq .L16 + 206 0070 9068 ldr r0, [r2, #8] + 207 0072 8842 cmp r0, r1 + 208 0074 F9D2 bcs .L15 + 209 .L16: + 210 .loc 2 48 0 + 211 0076 5168 ldr r1, [r2, #4] + 212 .loc 2 47 0 + 213 0078 1A60 str r2, [r3, #0] + 214 .loc 2 48 0 + 215 007a 5960 str r1, [r3, #4] + 216 .loc 2 49 0 + 217 007c 0B60 str r3, [r1, #0] + 218 007e 5360 str r3, [r2, #4] + 219 0080 D0E7 b .L5 + 220 .LVL15: + 221 .L7: + 222 .LBE43: + 223 .LBE42: + 224 .LBB44: + 225 .LBB45: + 226 .loc 2 75 0 + 227 0082 5868 ldr r0, [r3, #4] + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 5 + + + 228 0084 1A68 ldr r2, [r3, #0] + 229 .LBE45: + 230 .LBE44: + 231 .loc 1 142 0 + 232 0086 5E6A ldr r6, [r3, #36] + 233 .LVL16: + 234 .LBB48: + 235 .LBB46: + 236 .loc 2 75 0 + 237 0088 0260 str r2, [r0, #0] + 238 .loc 2 76 0 + 239 008a 1F68 ldr r7, [r3, #0] + 240 .LBE46: + 241 .LBE48: + 242 .loc 1 142 0 + 243 008c 3246 mov r2, r6 + 244 .LBB49: + 245 .LBB47: + 246 .loc 2 76 0 + 247 008e 7860 str r0, [r7, #4] + 248 .LVL17: + 249 .L12: + 250 .LBE47: + 251 .LBE49: + 252 .LBB50: + 253 .LBB51: + 254 .loc 2 45 0 + 255 0090 1268 ldr r2, [r2, #0] + 256 .LVL18: + 257 .loc 2 46 0 + 258 0092 9642 cmp r6, r2 + 259 0094 12D0 beq .L26 + 260 0096 9068 ldr r0, [r2, #8] + 261 0098 8842 cmp r0, r1 + 262 009a F9D2 bcs .L12 + 263 .LVL19: + 264 .L13: + 265 .loc 2 48 0 + 266 009c 5168 ldr r1, [r2, #4] + 267 .loc 2 47 0 + 268 009e 1A60 str r2, [r3, #0] + 269 .loc 2 48 0 + 270 00a0 5960 str r1, [r3, #4] + 271 .loc 2 49 0 + 272 00a2 0B60 str r3, [r1, #0] + 273 00a4 5360 str r3, [r2, #4] + 274 .LBE51: + 275 .LBE50: + 276 .loc 1 143 0 + 277 00a6 B368 ldr r3, [r6, #8] + 278 .LVL20: + 279 .loc 1 135 0 + 280 00a8 A168 ldr r1, [r4, #8] + 281 00aa 9A68 ldr r2, [r3, #8] + 282 .LVL21: + 283 00ac 8A42 cmp r2, r1 + 284 00ae B2D3 bcc .L20 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 6 + + + 285 00b0 B8E7 b .L5 + 286 .LVL22: + 287 .L3: + 288 .LBE54: + 289 .loc 1 184 0 + 290 00b2 E36B ldr r3, [r4, #60] + 291 .loc 1 183 0 + 292 00b4 8460 str r4, [r0, #8] + 293 .loc 1 184 0 + 294 00b6 C360 str r3, [r0, #12] + 295 .loc 1 185 0 + 296 00b8 E063 str r0, [r4, #60] + 297 00ba F8BD pop {r3, r4, r5, r6, r7, pc} + 298 .LVL23: + 299 .L26: + 300 .LBB55: + 301 .LBB53: + 302 .LBB52: + 303 .loc 2 46 0 + 304 00bc 3246 mov r2, r6 + 305 .LVL24: + 306 00be EDE7 b .L13 + 307 .L28: + 308 .align 2 + 309 .L27: + 310 00c0 00000000 .word rlist + 311 .LBE52: + 312 .LBE53: + 313 .LBE55: + 314 .cfi_endproc + 315 .LFE9: + 316 .size chMtxLockS, .-chMtxLockS + 317 00c4 AFF30080 .section .text.chMtxLock,"ax",%progbits + 317 AFF30080 + 317 AFF30080 + 318 .align 2 + 319 .p2align 4,,15 + 320 .global chMtxLock + 321 .thumb + 322 .thumb_func + 323 .type chMtxLock, %function + 324 chMtxLock: + 325 .LFB8: + 326 .loc 1 103 0 + 327 .cfi_startproc + 328 @ args = 0, pretend = 0, frame = 0 + 329 @ frame_needed = 0, uses_anonymous_args = 0 + 330 .LVL25: + 331 0000 08B5 push {r3, lr} + 332 .LCFI1: + 333 .cfi_def_cfa_offset 8 + 334 .cfi_offset 3, -8 + 335 .cfi_offset 14, -4 + 336 .loc 1 105 0 + 337 @ 105 "../..//os/kernel/src/chmtx.c" 1 + 338 0002 72B6 cpsid i + 339 @ 0 "" 2 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 7 + + + 340 .loc 1 107 0 + 341 .thumb + 342 0004 FFF7FEFF bl chMtxLockS + 343 .LVL26: + 344 .loc 1 109 0 + 345 @ 109 "../..//os/kernel/src/chmtx.c" 1 + 346 0008 62B6 cpsie i + 347 @ 0 "" 2 + 348 .thumb + 349 000a 08BD pop {r3, pc} + 350 .cfi_endproc + 351 .LFE8: + 352 .size chMtxLock, .-chMtxLock + 353 000c AFF30080 .section .text.chMtxTryLock,"ax",%progbits + 354 .align 2 + 355 .p2align 4,,15 + 356 .global chMtxTryLock + 357 .thumb + 358 .thumb_func + 359 .type chMtxTryLock, %function + 360 chMtxTryLock: + 361 .LFB10: + 362 .loc 1 206 0 + 363 .cfi_startproc + 364 @ args = 0, pretend = 0, frame = 0 + 365 @ frame_needed = 0, uses_anonymous_args = 0 + 366 @ link register save eliminated. + 367 .LVL27: + 368 .loc 1 206 0 + 369 0000 0346 mov r3, r0 + 370 .loc 1 209 0 + 371 @ 209 "../..//os/kernel/src/chmtx.c" 1 + 372 0002 72B6 cpsid i + 373 @ 0 "" 2 + 374 .LVL28: + 375 .thumb + 376 .LBB56: + 377 .LBB57: + 378 .loc 1 239 0 + 379 0004 8268 ldr r2, [r0, #8] + 380 .loc 1 240 0 + 381 0006 0020 movs r0, #0 + 382 .LVL29: + 383 .loc 1 239 0 + 384 0008 0AB1 cbz r2, .L33 + 385 .LBE57: + 386 .LBE56: + 387 .loc 1 213 0 + 388 @ 213 "../..//os/kernel/src/chmtx.c" 1 + 389 000a 62B6 cpsie i + 390 @ 0 "" 2 + 391 .loc 1 215 0 + 392 .thumb + 393 000c 7047 bx lr + 394 .L33: + 395 .LBB59: + 396 .LBB58: + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 8 + + + 397 .loc 1 241 0 + 398 000e 044A ldr r2, .L34 + 399 .loc 1 244 0 + 400 0010 0120 movs r0, #1 + 401 .loc 1 241 0 + 402 0012 D269 ldr r2, [r2, #28] + 403 .loc 1 242 0 + 404 0014 D16B ldr r1, [r2, #60] + 405 .loc 1 241 0 + 406 0016 9A60 str r2, [r3, #8] + 407 .loc 1 242 0 + 408 0018 D960 str r1, [r3, #12] + 409 .loc 1 243 0 + 410 001a D363 str r3, [r2, #60] + 411 .LBE58: + 412 .LBE59: + 413 .loc 1 213 0 + 414 @ 213 "../..//os/kernel/src/chmtx.c" 1 + 415 001c 62B6 cpsie i + 416 @ 0 "" 2 + 417 .loc 1 215 0 + 418 .thumb + 419 001e 7047 bx lr + 420 .L35: + 421 .align 2 + 422 .L34: + 423 0020 00000000 .word rlist + 424 .cfi_endproc + 425 .LFE10: + 426 .size chMtxTryLock, .-chMtxTryLock + 427 0024 AFF30080 .section .text.chMtxTryLockS,"ax",%progbits + 427 AFF30080 + 427 AFF30080 + 428 .align 2 + 429 .p2align 4,,15 + 430 .global chMtxTryLockS + 431 .thumb + 432 .thumb_func + 433 .type chMtxTryLockS, %function + 434 chMtxTryLockS: + 435 .LFB11: + 436 .loc 1 234 0 + 437 .cfi_startproc + 438 @ args = 0, pretend = 0, frame = 0 + 439 @ frame_needed = 0, uses_anonymous_args = 0 + 440 @ link register save eliminated. + 441 .LVL30: + 442 .loc 1 239 0 + 443 0000 8268 ldr r2, [r0, #8] + 444 .loc 1 234 0 + 445 0002 0346 mov r3, r0 + 446 .loc 1 239 0 + 447 0004 0AB1 cbz r2, .L39 + 448 .loc 1 240 0 + 449 0006 0020 movs r0, #0 + 450 .LVL31: + 451 .loc 1 245 0 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 9 + + + 452 0008 7047 bx lr + 453 .LVL32: + 454 .L39: + 455 .loc 1 241 0 + 456 000a 044A ldr r2, .L40 + 457 .loc 1 244 0 + 458 000c 0120 movs r0, #1 + 459 .LVL33: + 460 .loc 1 241 0 + 461 000e D269 ldr r2, [r2, #28] + 462 .loc 1 242 0 + 463 0010 D16B ldr r1, [r2, #60] + 464 .loc 1 241 0 + 465 0012 9A60 str r2, [r3, #8] + 466 .loc 1 242 0 + 467 0014 D960 str r1, [r3, #12] + 468 .loc 1 243 0 + 469 0016 D363 str r3, [r2, #60] + 470 .loc 1 244 0 + 471 0018 7047 bx lr + 472 .L41: + 473 001a 00BF .align 2 + 474 .L40: + 475 001c 00000000 .word rlist + 476 .cfi_endproc + 477 .LFE11: + 478 .size chMtxTryLockS, .-chMtxTryLockS + 479 .section .text.chMtxUnlock,"ax",%progbits + 480 .align 2 + 481 .p2align 4,,15 + 482 .global chMtxUnlock + 483 .thumb + 484 .thumb_func + 485 .type chMtxUnlock, %function + 486 chMtxUnlock: + 487 .LFB12: + 488 .loc 1 257 0 + 489 .cfi_startproc + 490 @ args = 0, pretend = 0, frame = 0 + 491 @ frame_needed = 0, uses_anonymous_args = 0 + 492 0000 38B5 push {r3, r4, r5, lr} + 493 .LCFI2: + 494 .cfi_def_cfa_offset 16 + 495 .cfi_offset 3, -16 + 496 .cfi_offset 4, -12 + 497 .cfi_offset 5, -8 + 498 .cfi_offset 14, -4 + 499 .loc 1 258 0 + 500 0002 134B ldr r3, .L53 + 501 0004 D869 ldr r0, [r3, #28] + 502 .LVL34: + 503 .loc 1 261 0 + 504 @ 261 "../..//os/kernel/src/chmtx.c" 1 + 505 0006 72B6 cpsid i + 506 @ 0 "" 2 + 507 .loc 1 270 0 + 508 .thumb + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 10 + + + 509 0008 C46B ldr r4, [r0, #60] + 510 .LVL35: + 511 .loc 1 273 0 + 512 000a 2568 ldr r5, [r4, #0] + 513 .loc 1 271 0 + 514 000c E368 ldr r3, [r4, #12] + 515 .loc 1 273 0 + 516 000e A542 cmp r5, r4 + 517 .loc 1 271 0 + 518 0010 C363 str r3, [r0, #60] + 519 .loc 1 273 0 + 520 0012 1AD0 beq .L43 + 521 .LBB60: + 522 .loc 1 278 0 + 523 0014 016C ldr r1, [r0, #64] + 524 .LVL36: + 525 .loc 1 280 0 + 526 0016 4BB1 cbz r3, .L44 + 527 .L50: + 528 .loc 1 284 0 + 529 0018 1A68 ldr r2, [r3, #0] + 530 001a 9A42 cmp r2, r3 + 531 001c 03D0 beq .L45 + 532 .loc 1 284 0 is_stmt 0 discriminator 1 + 533 001e 9268 ldr r2, [r2, #8] + 534 0020 9142 cmp r1, r2 + 535 0022 38BF it cc + 536 0024 1146 movcc r1, r2 + 537 .LVL37: + 538 .L45: + 539 .loc 1 286 0 is_stmt 1 + 540 0026 DB68 ldr r3, [r3, #12] + 541 .LVL38: + 542 .loc 1 280 0 + 543 0028 002B cmp r3, #0 + 544 002a F5D1 bne .L50 + 545 .L44: + 546 .LBB61: + 547 .LBB62: + 548 .loc 2 62 0 + 549 002c 2B68 ldr r3, [r5, #0] + 550 .LVL39: + 551 .LBE62: + 552 .LBE61: + 553 .loc 1 295 0 + 554 002e EA6B ldr r2, [r5, #60] + 555 .loc 1 290 0 + 556 0030 8160 str r1, [r0, #8] + 557 .LVL40: + 558 .LBB65: + 559 .LBB63: + 560 .loc 2 62 0 + 561 0032 2360 str r3, [r4, #0] + 562 .LBE63: + 563 .LBE65: + 564 .loc 1 297 0 + 565 0034 2846 mov r0, r5 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 11 + + + 566 .LVL41: + 567 .LBB66: + 568 .LBB64: + 569 .loc 2 62 0 + 570 0036 5C60 str r4, [r3, #4] + 571 .LBE64: + 572 .LBE66: + 573 .loc 1 297 0 + 574 0038 0021 movs r1, #0 + 575 .LVL42: + 576 .loc 1 294 0 + 577 003a A560 str r5, [r4, #8] + 578 .loc 1 295 0 + 579 003c E260 str r2, [r4, #12] + 580 .loc 1 296 0 + 581 003e EC63 str r4, [r5, #60] + 582 .loc 1 297 0 + 583 0040 FFF7FEFF bl chSchWakeupS + 584 .LVL43: + 585 .L47: + 586 .LBE60: + 587 .loc 1 301 0 + 588 @ 301 "../..//os/kernel/src/chmtx.c" 1 + 589 0044 62B6 cpsie i + 590 @ 0 "" 2 + 591 .loc 1 303 0 + 592 .thumb + 593 0046 2046 mov r0, r4 + 594 0048 38BD pop {r3, r4, r5, pc} + 595 .LVL44: + 596 .L43: + 597 .loc 1 300 0 + 598 004a 0023 movs r3, #0 + 599 004c A360 str r3, [r4, #8] + 600 004e F9E7 b .L47 + 601 .L54: + 602 .align 2 + 603 .L53: + 604 0050 00000000 .word rlist + 605 .cfi_endproc + 606 .LFE12: + 607 .size chMtxUnlock, .-chMtxUnlock + 608 0054 AFF30080 .section .text.chMtxUnlockS,"ax",%progbits + 608 AFF30080 + 608 AFF30080 + 609 .align 2 + 610 .p2align 4,,15 + 611 .global chMtxUnlockS + 612 .thumb + 613 .thumb_func + 614 .type chMtxUnlockS, %function + 615 chMtxUnlockS: + 616 .LFB13: + 617 .loc 1 317 0 + 618 .cfi_startproc + 619 @ args = 0, pretend = 0, frame = 0 + 620 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 12 + + + 621 0000 38B5 push {r3, r4, r5, lr} + 622 .LCFI3: + 623 .cfi_def_cfa_offset 16 + 624 .cfi_offset 3, -16 + 625 .cfi_offset 4, -12 + 626 .cfi_offset 5, -8 + 627 .cfi_offset 14, -4 + 628 .loc 1 318 0 + 629 0002 124B ldr r3, .L66 + 630 0004 D869 ldr r0, [r3, #28] + 631 .LVL45: + 632 .loc 1 331 0 + 633 0006 C46B ldr r4, [r0, #60] + 634 .LVL46: + 635 .loc 1 334 0 + 636 0008 2568 ldr r5, [r4, #0] + 637 .loc 1 332 0 + 638 000a E368 ldr r3, [r4, #12] + 639 .loc 1 334 0 + 640 000c A542 cmp r5, r4 + 641 .loc 1 332 0 + 642 000e C363 str r3, [r0, #60] + 643 .loc 1 334 0 + 644 0010 18D0 beq .L56 + 645 .LBB67: + 646 .loc 1 339 0 + 647 0012 016C ldr r1, [r0, #64] + 648 .LVL47: + 649 .loc 1 341 0 + 650 0014 4BB1 cbz r3, .L57 + 651 .L63: + 652 .loc 1 345 0 + 653 0016 1A68 ldr r2, [r3, #0] + 654 0018 9A42 cmp r2, r3 + 655 001a 03D0 beq .L58 + 656 .loc 1 345 0 is_stmt 0 discriminator 1 + 657 001c 9268 ldr r2, [r2, #8] + 658 001e 9142 cmp r1, r2 + 659 0020 38BF it cc + 660 0022 1146 movcc r1, r2 + 661 .LVL48: + 662 .L58: + 663 .loc 1 347 0 is_stmt 1 + 664 0024 DB68 ldr r3, [r3, #12] + 665 .LVL49: + 666 .loc 1 341 0 + 667 0026 002B cmp r3, #0 + 668 0028 F5D1 bne .L63 + 669 .L57: + 670 .LBB68: + 671 .LBB69: + 672 .loc 2 62 0 + 673 002a 2B68 ldr r3, [r5, #0] + 674 .LVL50: + 675 .LBE69: + 676 .LBE68: + 677 .loc 1 354 0 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 13 + + + 678 002c EA6B ldr r2, [r5, #60] + 679 .loc 1 349 0 + 680 002e 8160 str r1, [r0, #8] + 681 .LVL51: + 682 .LBB72: + 683 .LBB70: + 684 .loc 2 62 0 + 685 0030 2360 str r3, [r4, #0] + 686 .LBE70: + 687 .LBE72: + 688 .loc 1 356 0 + 689 0032 2846 mov r0, r5 + 690 .LVL52: + 691 .LBB73: + 692 .LBB71: + 693 .loc 2 62 0 + 694 0034 5C60 str r4, [r3, #4] + 695 .LBE71: + 696 .LBE73: + 697 .loc 1 353 0 + 698 0036 A560 str r5, [r4, #8] + 699 .loc 1 354 0 + 700 0038 E260 str r2, [r4, #12] + 701 .loc 1 355 0 + 702 003a EC63 str r4, [r5, #60] + 703 .loc 1 356 0 + 704 003c FFF7FEFF bl chSchReadyI + 705 .LVL53: + 706 .LBE67: + 707 .loc 1 361 0 + 708 0040 2046 mov r0, r4 + 709 0042 38BD pop {r3, r4, r5, pc} + 710 .LVL54: + 711 .L56: + 712 .loc 1 359 0 + 713 0044 0023 movs r3, #0 + 714 0046 A360 str r3, [r4, #8] + 715 .loc 1 361 0 + 716 0048 2046 mov r0, r4 + 717 .LVL55: + 718 004a 38BD pop {r3, r4, r5, pc} + 719 .L67: + 720 .align 2 + 721 .L66: + 722 004c 00000000 .word rlist + 723 .cfi_endproc + 724 .LFE13: + 725 .size chMtxUnlockS, .-chMtxUnlockS + 726 .section .text.chMtxUnlockAll,"ax",%progbits + 727 .align 2 + 728 .p2align 4,,15 + 729 .global chMtxUnlockAll + 730 .thumb + 731 .thumb_func + 732 .type chMtxUnlockAll, %function + 733 chMtxUnlockAll: + 734 .LFB14: + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 14 + + + 735 .loc 1 374 0 + 736 .cfi_startproc + 737 @ args = 0, pretend = 0, frame = 0 + 738 @ frame_needed = 0, uses_anonymous_args = 0 + 739 .loc 1 375 0 + 740 0000 104B ldr r3, .L78 + 741 .loc 1 374 0 + 742 0002 70B5 push {r4, r5, r6, lr} + 743 .LCFI4: + 744 .cfi_def_cfa_offset 16 + 745 .cfi_offset 4, -16 + 746 .cfi_offset 5, -12 + 747 .cfi_offset 6, -8 + 748 .cfi_offset 14, -4 + 749 .loc 1 375 0 + 750 0004 DC69 ldr r4, [r3, #28] + 751 .LVL56: + 752 .loc 1 377 0 + 753 @ 377 "../..//os/kernel/src/chmtx.c" 1 + 754 0006 72B6 cpsid i + 755 @ 0 "" 2 + 756 .loc 1 378 0 + 757 .thumb + 758 0008 E36B ldr r3, [r4, #60] + 759 000a C3B1 cbz r3, .L69 + 760 .LBB74: + 761 .loc 1 390 0 + 762 000c 0026 movs r6, #0 + 763 .L75: + 764 .LVL57: + 765 .loc 1 382 0 + 766 000e 1A68 ldr r2, [r3, #0] + 767 .LVL58: + 768 .loc 1 381 0 + 769 0010 D968 ldr r1, [r3, #12] + 770 .loc 1 382 0 + 771 0012 9A42 cmp r2, r3 + 772 .loc 1 381 0 + 773 0014 E163 str r1, [r4, #60] + 774 .LBB75: + 775 .loc 1 387 0 + 776 0016 1046 mov r0, r2 + 777 .LBE75: + 778 .loc 1 390 0 + 779 0018 08BF it eq + 780 001a 9E60 streq r6, [r3, #8] + 781 .loc 1 382 0 + 782 001c 08D0 beq .L71 + 783 .LBB80: + 784 .LBB76: + 785 .LBB77: + 786 .loc 2 62 0 + 787 001e 1168 ldr r1, [r2, #0] + 788 .LBE77: + 789 .LBE76: + 790 .loc 1 385 0 + 791 0020 D56B ldr r5, [r2, #60] + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 15 + + + 792 .LBB79: + 793 .LBB78: + 794 .loc 2 62 0 + 795 0022 1960 str r1, [r3, #0] + 796 0024 4B60 str r3, [r1, #4] + 797 .LBE78: + 798 .LBE79: + 799 .loc 1 384 0 + 800 0026 9A60 str r2, [r3, #8] + 801 .loc 1 385 0 + 802 0028 DD60 str r5, [r3, #12] + 803 .loc 1 386 0 + 804 002a D363 str r3, [r2, #60] + 805 .loc 1 387 0 + 806 002c FFF7FEFF bl chSchReadyI + 807 .LVL59: + 808 .L71: + 809 .LBE80: + 810 .LBE74: + 811 .loc 1 391 0 + 812 0030 E36B ldr r3, [r4, #60] + 813 0032 002B cmp r3, #0 + 814 0034 EBD1 bne .L75 + 815 .loc 1 392 0 + 816 0036 236C ldr r3, [r4, #64] + 817 0038 A360 str r3, [r4, #8] + 818 .loc 1 393 0 + 819 003a FFF7FEFF bl chSchRescheduleS + 820 .LVL60: + 821 .L69: + 822 .loc 1 395 0 + 823 @ 395 "../..//os/kernel/src/chmtx.c" 1 + 824 003e 62B6 cpsie i + 825 @ 0 "" 2 + 826 .thumb + 827 0040 70BD pop {r4, r5, r6, pc} + 828 .L79: + 829 0042 00BF .align 2 + 830 .L78: + 831 0044 00000000 .word rlist + 832 .cfi_endproc + 833 .LFE14: + 834 .size chMtxUnlockAll, .-chMtxUnlockAll + 835 0048 AFF30080 .text + 835 AFF30080 + 836 .Letext0: + 837 .file 3 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 838 .file 4 "../..//os/ports/GCC/ARMCMx/chtypes.h" + 839 .file 5 "../..//os/kernel/include/chlists.h" + 840 .file 6 "../..//os/kernel/include/chthreads.h" + 841 .file 7 "../..//os/ports/GCC/ARMCMx/chcore_v7m.h" + 842 .file 8 "../..//os/kernel/include/chschd.h" + 843 .file 9 "../..//os/kernel/include/chmtx.h" + 844 .section .debug_info,"",%progbits + 845 .Ldebug_info0: + 846 0000 58090000 .4byte 0x958 + 847 0004 0200 .2byte 0x2 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 16 + + + 848 0006 00000000 .4byte .Ldebug_abbrev0 + 849 000a 04 .byte 0x4 + 850 000b 01 .uleb128 0x1 + 851 000c E2010000 .4byte .LASF77 + 852 0010 01 .byte 0x1 + 853 0011 55030000 .4byte .LASF78 + 854 0015 8A010000 .4byte .LASF79 + 855 0019 B8010000 .4byte .Ldebug_ranges0+0x1b8 + 856 001d 00000000 .4byte 0 + 857 0021 00000000 .4byte 0 + 858 0025 00000000 .4byte .Ldebug_line0 + 859 0029 02 .uleb128 0x2 + 860 002a 04 .byte 0x4 + 861 002b 05 .byte 0x5 + 862 002c 696E7400 .ascii "int\000" + 863 0030 03 .uleb128 0x3 + 864 0031 04 .byte 0x4 + 865 0032 07 .byte 0x7 + 866 0033 D9000000 .4byte .LASF0 + 867 0037 03 .uleb128 0x3 + 868 0038 01 .byte 0x1 + 869 0039 06 .byte 0x6 + 870 003a 4E000000 .4byte .LASF1 + 871 003e 04 .uleb128 0x4 + 872 003f 1D030000 .4byte .LASF5 + 873 0043 03 .byte 0x3 + 874 0044 2A .byte 0x2a + 875 0045 49000000 .4byte 0x49 + 876 0049 03 .uleb128 0x3 + 877 004a 01 .byte 0x1 + 878 004b 08 .byte 0x8 + 879 004c 1F020000 .4byte .LASF2 + 880 0050 03 .uleb128 0x3 + 881 0051 02 .byte 0x2 + 882 0052 05 .byte 0x5 + 883 0053 37020000 .4byte .LASF3 + 884 0057 03 .uleb128 0x3 + 885 0058 02 .byte 0x2 + 886 0059 07 .byte 0x7 + 887 005a 00010000 .4byte .LASF4 + 888 005e 04 .uleb128 0x4 + 889 005f 17020000 .4byte .LASF6 + 890 0063 03 .byte 0x3 + 891 0064 4F .byte 0x4f + 892 0065 69000000 .4byte 0x69 + 893 0069 03 .uleb128 0x3 + 894 006a 04 .byte 0x4 + 895 006b 05 .byte 0x5 + 896 006c 71000000 .4byte .LASF7 + 897 0070 04 .uleb128 0x4 + 898 0071 86020000 .4byte .LASF8 + 899 0075 03 .byte 0x3 + 900 0076 50 .byte 0x50 + 901 0077 7B000000 .4byte 0x7b + 902 007b 03 .uleb128 0x3 + 903 007c 04 .byte 0x4 + 904 007d 07 .byte 0x7 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 17 + + + 905 007e E6000000 .4byte .LASF9 + 906 0082 03 .uleb128 0x3 + 907 0083 08 .byte 0x8 + 908 0084 05 .byte 0x5 + 909 0085 40000000 .4byte .LASF10 + 910 0089 03 .uleb128 0x3 + 911 008a 08 .byte 0x8 + 912 008b 07 .byte 0x7 + 913 008c 0D000000 .4byte .LASF11 + 914 0090 04 .uleb128 0x4 + 915 0091 62000000 .4byte .LASF12 + 916 0095 04 .byte 0x4 + 917 0096 2E .byte 0x2e + 918 0097 5E000000 .4byte 0x5e + 919 009b 04 .uleb128 0x4 + 920 009c 3C010000 .4byte .LASF13 + 921 00a0 04 .byte 0x4 + 922 00a1 2F .byte 0x2f + 923 00a2 3E000000 .4byte 0x3e + 924 00a6 04 .uleb128 0x4 + 925 00a7 7A000000 .4byte .LASF14 + 926 00ab 04 .byte 0x4 + 927 00ac 30 .byte 0x30 + 928 00ad 3E000000 .4byte 0x3e + 929 00b1 04 .uleb128 0x4 + 930 00b2 00020000 .4byte .LASF15 + 931 00b6 04 .byte 0x4 + 932 00b7 31 .byte 0x31 + 933 00b8 3E000000 .4byte 0x3e + 934 00bc 04 .uleb128 0x4 + 935 00bd 0F020000 .4byte .LASF16 + 936 00c1 04 .byte 0x4 + 937 00c2 32 .byte 0x32 + 938 00c3 70000000 .4byte 0x70 + 939 00c7 04 .uleb128 0x4 + 940 00c8 13010000 .4byte .LASF17 + 941 00cc 04 .byte 0x4 + 942 00cd 33 .byte 0x33 + 943 00ce 5E000000 .4byte 0x5e + 944 00d2 04 .uleb128 0x4 + 945 00d3 50010000 .4byte .LASF18 + 946 00d7 04 .byte 0x4 + 947 00d8 35 .byte 0x35 + 948 00d9 70000000 .4byte 0x70 + 949 00dd 04 .uleb128 0x4 + 950 00de BB020000 .4byte .LASF19 + 951 00e2 04 .byte 0x4 + 952 00e3 36 .byte 0x36 + 953 00e4 70000000 .4byte 0x70 + 954 00e8 04 .uleb128 0x4 + 955 00e9 C6000000 .4byte .LASF20 + 956 00ed 04 .byte 0x4 + 957 00ee 37 .byte 0x37 + 958 00ef 5E000000 .4byte 0x5e + 959 00f3 04 .uleb128 0x4 + 960 00f4 66020000 .4byte .LASF21 + 961 00f8 05 .byte 0x5 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 18 + + + 962 00f9 2A .byte 0x2a + 963 00fa FE000000 .4byte 0xfe + 964 00fe 05 .uleb128 0x5 + 965 00ff 66020000 .4byte .LASF21 + 966 0103 48 .byte 0x48 + 967 0104 06 .byte 0x6 + 968 0105 5E .byte 0x5e + 969 0106 15020000 .4byte 0x215 + 970 010a 06 .uleb128 0x6 + 971 010b 57020000 .4byte .LASF22 + 972 010f 06 .byte 0x6 + 973 0110 5F .byte 0x5f + 974 0111 3A020000 .4byte 0x23a + 975 0115 02 .byte 0x2 + 976 0116 23 .byte 0x23 + 977 0117 00 .uleb128 0 + 978 0118 06 .uleb128 0x6 + 979 0119 08020000 .4byte .LASF23 + 980 011d 06 .byte 0x6 + 981 011e 61 .byte 0x61 + 982 011f 3A020000 .4byte 0x23a + 983 0123 02 .byte 0x2 + 984 0124 23 .byte 0x23 + 985 0125 04 .uleb128 0x4 + 986 0126 06 .uleb128 0x6 + 987 0127 39000000 .4byte .LASF24 + 988 012b 06 .byte 0x6 + 989 012c 63 .byte 0x63 + 990 012d BC000000 .4byte 0xbc + 991 0131 02 .byte 0x2 + 992 0132 23 .byte 0x23 + 993 0133 08 .uleb128 0x8 + 994 0134 06 .uleb128 0x6 + 995 0135 45030000 .4byte .LASF25 + 996 0139 06 .byte 0x6 + 997 013a 64 .byte 0x64 + 998 013b 07030000 .4byte 0x307 + 999 013f 02 .byte 0x2 + 1000 0140 23 .byte 0x23 + 1001 0141 0C .uleb128 0xc + 1002 0142 06 .uleb128 0x6 + 1003 0143 9C000000 .4byte .LASF26 + 1004 0147 06 .byte 0x6 + 1005 0148 66 .byte 0x66 + 1006 0149 3A020000 .4byte 0x23a + 1007 014d 02 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.uleb128 0x12 + 1448 046b 747000 .ascii "tp\000" + 1449 046e 02 .byte 0x2 + 1450 046f 29 .byte 0x29 + 1451 0470 3A020000 .4byte 0x23a + 1452 0474 12 .uleb128 0x12 + 1453 0475 74717000 .ascii "tqp\000" + 1454 0479 02 .byte 0x2 + 1455 047a 29 .byte 0x29 + 1456 047b 8A040000 .4byte 0x48a + 1457 047f 14 .uleb128 0x14 + 1458 0480 637000 .ascii "cp\000" + 1459 0483 02 .byte 0x2 + 1460 0484 2B .byte 0x2b + 1461 0485 3A020000 .4byte 0x23a + 1462 0489 00 .byte 0 + 1463 048a 09 .uleb128 0x9 + 1464 048b 04 .byte 0x4 + 1465 048c 40020000 .4byte 0x240 + 1466 0490 15 .uleb128 0x15 + 1467 0491 01 .byte 0x1 + 1468 0492 8E000000 .4byte .LASF73 + 1469 0496 01 .byte 0x1 + 1470 0497 EA .byte 0xea + 1471 0498 01 .byte 0x1 + 1472 0499 90000000 .4byte 0x90 + 1473 049d 01 .byte 0x1 + 1474 049e AD040000 .4byte 0x4ad + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 27 + + + 1475 04a2 12 .uleb128 0x12 + 1476 04a3 6D7000 .ascii "mp\000" + 1477 04a6 01 .byte 0x1 + 1478 04a7 EA .byte 0xea + 1479 04a8 3B040000 .4byte 0x43b + 1480 04ac 00 .byte 0 + 1481 04ad 11 .uleb128 0x11 + 1482 04ae A8020000 .4byte .LASF64 + 1483 04b2 02 .byte 0x2 + 1484 04b3 3B .byte 0x3b + 1485 04b4 01 .byte 0x1 + 1486 04b5 3A020000 .4byte 0x23a + 1487 04b9 03 .byte 0x3 + 1488 04ba D4040000 .4byte 0x4d4 + 1489 04be 12 .uleb128 0x12 + 1490 04bf 74717000 .ascii "tqp\000" + 1491 04c3 02 .byte 0x2 + 1492 04c4 3B .byte 0x3b + 1493 04c5 8A040000 .4byte 0x48a + 1494 04c9 14 .uleb128 0x14 + 1495 04ca 747000 .ascii "tp\000" + 1496 04cd 02 .byte 0x2 + 1497 04ce 3C .byte 0x3c + 1498 04cf 3A020000 .4byte 0x23a + 1499 04d3 00 .byte 0 + 1500 04d4 16 .uleb128 0x16 + 1501 04d5 01 .byte 0x1 + 1502 04d6 FC020000 .4byte .LASF65 + 1503 04da 01 .byte 0x1 + 1504 04db 56 .byte 0x56 + 1505 04dc 01 .byte 0x1 + 1506 04dd 00000000 .4byte .LFB7 + 1507 04e1 0A000000 .4byte .LFE7 + 1508 04e5 02 .byte 0x2 + 1509 04e6 7D .byte 0x7d + 1510 04e7 00 .sleb128 0 + 1511 04e8 01 .byte 0x1 + 1512 04e9 FA040000 .4byte 0x4fa + 1513 04ed 17 .uleb128 0x17 + 1514 04ee 6D7000 .ascii "mp\000" + 1515 04f1 01 .byte 0x1 + 1516 04f2 56 .byte 0x56 + 1517 04f3 3B040000 .4byte 0x43b + 1518 04f7 01 .byte 0x1 + 1519 04f8 50 .byte 0x50 + 1520 04f9 00 .byte 0 + 1521 04fa 18 .uleb128 0x18 + 1522 04fb 01 .byte 0x1 + 1523 04fc 83000000 .4byte .LASF66 + 1524 0500 01 .byte 0x1 + 1525 0501 79 .byte 0x79 + 1526 0502 01 .byte 0x1 + 1527 0503 00000000 .4byte .LFB9 + 1528 0507 C4000000 .4byte .LFE9 + 1529 050b 00000000 .4byte .LLST0 + 1530 050f 01 .byte 0x1 + 1531 0510 5B060000 .4byte 0x65b + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 28 + + + 1532 0514 19 .uleb128 0x19 + 1533 0515 6D7000 .ascii "mp\000" + 1534 0518 01 .byte 0x1 + 1535 0519 79 .byte 0x79 + 1536 051a 3B040000 .4byte 0x43b + 1537 051e 20000000 .4byte .LLST1 + 1538 0522 1A .uleb128 0x1a + 1539 0523 63747000 .ascii "ctp\000" + 1540 0527 01 .byte 0x1 + 1541 0528 7A .byte 0x7a + 1542 0529 3A020000 .4byte 0x23a + 1543 052d 01 .byte 0x1 + 1544 052e 54 .byte 0x54 + 1545 052f 1B .uleb128 0x1b + 1546 0530 00000000 .4byte .Ldebug_ranges0+0 + 1547 0534 1C .uleb128 0x1c + 1548 0535 747000 .ascii "tp\000" + 1549 0538 01 .byte 0x1 + 1550 0539 84 .byte 0x84 + 1551 053a 3A020000 .4byte 0x23a + 1552 053e 54000000 .4byte .LLST2 + 1553 0542 1D .uleb128 0x1d + 1554 0543 5D040000 .4byte 0x45d + 1555 0547 26000000 .4byte .LBB28 + 1556 054b 20000000 .4byte .Ldebug_ranges0+0x20 + 1557 054f 01 .byte 0x1 + 1558 0550 AD .byte 0xad + 1559 0551 77050000 .4byte 0x577 + 1560 0555 1E .uleb128 0x1e + 1561 0556 74040000 .4byte 0x474 + 1562 055a 93000000 .4byte .LLST3 + 1563 055e 1E .uleb128 0x1e + 1564 055f 6A040000 .4byte 0x46a + 1565 0563 A6000000 .4byte .LLST4 + 1566 0567 1B .uleb128 0x1b + 1567 0568 38000000 .4byte .Ldebug_ranges0+0x38 + 1568 056c 1F .uleb128 0x1f + 1569 056d 7F040000 .4byte 0x47f + 1570 0571 B9000000 .4byte .LLST5 + 1571 0575 00 .byte 0 + 1572 0576 00 .byte 0 + 1573 0577 1D .uleb128 0x1d + 1574 0578 41040000 .4byte 0x441 + 1575 057c 4A000000 .4byte .LBB32 + 1576 0580 50000000 .4byte .Ldebug_ranges0+0x50 + 1577 0584 01 .byte 0x1 + 1578 0585 A7 .byte 0xa7 + 1579 0586 94050000 .4byte 0x594 + 1580 058a 1E .uleb128 0x1e + 1581 058b 52040000 .4byte 0x452 + 1582 058f D7000000 .4byte .LLST6 + 1583 0593 00 .byte 0 + 1584 0594 1D .uleb128 0x1d + 1585 0595 41040000 .4byte 0x441 + 1586 0599 5C000000 .4byte .LBB36 + 1587 059d 68000000 .4byte .Ldebug_ranges0+0x68 + 1588 05a1 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 29 + + + 1589 05a2 9E .byte 0x9e + 1590 05a3 B1050000 .4byte 0x5b1 + 1591 05a7 1E .uleb128 0x1e + 1592 05a8 52040000 .4byte 0x452 + 1593 05ac F5000000 .4byte .LLST7 + 1594 05b0 00 .byte 0 + 1595 05b1 20 .uleb128 0x20 + 1596 05b2 5D040000 .4byte 0x45d + 1597 05b6 6A000000 .4byte .LBB42 + 1598 05ba 82000000 .4byte .LBE42 + 1599 05be 01 .byte 0x1 + 1600 05bf 9E .byte 0x9e + 1601 05c0 EA050000 .4byte 0x5ea + 1602 05c4 1E .uleb128 0x1e + 1603 05c5 74040000 .4byte 0x474 + 1604 05c9 08010000 .4byte .LLST8 + 1605 05cd 1E .uleb128 0x1e + 1606 05ce 6A040000 .4byte 0x46a + 1607 05d2 1B010000 .4byte .LLST9 + 1608 05d6 21 .uleb128 0x21 + 1609 05d7 6A000000 .4byte .LBB43 + 1610 05db 82000000 .4byte .LBE43 + 1611 05df 1F .uleb128 0x1f + 1612 05e0 7F040000 .4byte 0x47f + 1613 05e4 2E010000 .4byte .LLST10 + 1614 05e8 00 .byte 0 + 1615 05e9 00 .byte 0 + 1616 05ea 1D .uleb128 0x1d + 1617 05eb 41040000 .4byte 0x441 + 1618 05ef 82000000 .4byte .LBB44 + 1619 05f3 88000000 .4byte .Ldebug_ranges0+0x88 + 1620 05f7 01 .byte 0x1 + 1621 05f8 8E .byte 0x8e + 1622 05f9 07060000 .4byte 0x607 + 1623 05fd 1E .uleb128 0x1e + 1624 05fe 52040000 .4byte 0x452 + 1625 0602 4C010000 .4byte .LLST11 + 1626 0606 00 .byte 0 + 1627 0607 1D .uleb128 0x1d + 1628 0608 5D040000 .4byte 0x45d + 1629 060c 90000000 .4byte .LBB50 + 1630 0610 A8000000 .4byte .Ldebug_ranges0+0xa8 + 1631 0614 01 .byte 0x1 + 1632 0615 8E .byte 0x8e + 1633 0616 3C060000 .4byte 0x63c + 1634 061a 1E .uleb128 0x1e + 1635 061b 74040000 .4byte 0x474 + 1636 061f 76010000 .4byte .LLST12 + 1637 0623 1E .uleb128 0x1e + 1638 0624 6A040000 .4byte 0x46a + 1639 0628 94010000 .4byte .LLST13 + 1640 062c 1B .uleb128 0x1b + 1641 062d C0000000 .4byte .Ldebug_ranges0+0xc0 + 1642 0631 1F .uleb128 0x1f + 1643 0632 7F040000 .4byte 0x47f + 1644 0636 BE010000 .4byte .LLST14 + 1645 063a 00 .byte 0 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 30 + + + 1646 063b 00 .byte 0 + 1647 063c 22 .uleb128 0x22 + 1648 063d 4A000000 .4byte .LVL8 + 1649 0641 01 .byte 0x1 + 1650 0642 0C090000 .4byte 0x90c + 1651 0646 50060000 .4byte 0x650 + 1652 064a 23 .uleb128 0x23 + 1653 064b 01 .byte 0x1 + 1654 064c 50 .byte 0x50 + 1655 064d 01 .byte 0x1 + 1656 064e 34 .byte 0x34 + 1657 064f 00 .byte 0 + 1658 0650 24 .uleb128 0x24 + 1659 0651 5A000000 .4byte .LVL10 + 1660 0655 20090000 .4byte 0x920 + 1661 0659 00 .byte 0 + 1662 065a 00 .byte 0 + 1663 065b 18 .uleb128 0x18 + 1664 065c 01 .byte 0x1 + 1665 065d 78010000 .4byte .LASF67 + 1666 0661 01 .byte 0x1 + 1667 0662 67 .byte 0x67 + 1668 0663 01 .byte 0x1 + 1669 0664 00000000 .4byte .LFB8 + 1670 0668 0C000000 .4byte .LFE8 + 1671 066c E7010000 .4byte .LLST15 + 1672 0670 01 .byte 0x1 + 1673 0671 95060000 .4byte 0x695 + 1674 0675 19 .uleb128 0x19 + 1675 0676 6D7000 .ascii "mp\000" + 1676 0679 01 .byte 0x1 + 1677 067a 67 .byte 0x67 + 1678 067b 3B040000 .4byte 0x43b + 1679 067f 07020000 .4byte .LLST16 + 1680 0683 25 .uleb128 0x25 + 1681 0684 08000000 .4byte .LVL26 + 1682 0688 FA040000 .4byte 0x4fa + 1683 068c 23 .uleb128 0x23 + 1684 068d 01 .byte 0x1 + 1685 068e 50 .byte 0x50 + 1686 068f 03 .byte 0x3 + 1687 0690 F3 .byte 0xf3 + 1688 0691 01 .uleb128 0x1 + 1689 0692 50 .byte 0x50 + 1690 0693 00 .byte 0 + 1691 0694 00 .byte 0 + 1692 0695 26 .uleb128 0x26 + 1693 0696 01 .byte 0x1 + 1694 0697 5C010000 .4byte .LASF68 + 1695 069b 01 .byte 0x1 + 1696 069c CE .byte 0xce + 1697 069d 01 .byte 0x1 + 1698 069e 90000000 .4byte 0x90 + 1699 06a2 00000000 .4byte .LFB10 + 1700 06a6 24000000 .4byte .LFE10 + 1701 06aa 02 .byte 0x2 + 1702 06ab 7D .byte 0x7d + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 31 + + + 1703 06ac 00 .sleb128 0 + 1704 06ad 01 .byte 0x1 + 1705 06ae E5060000 .4byte 0x6e5 + 1706 06b2 19 .uleb128 0x19 + 1707 06b3 6D7000 .ascii "mp\000" + 1708 06b6 01 .byte 0x1 + 1709 06b7 CE .byte 0xce + 1710 06b8 3B040000 .4byte 0x43b + 1711 06bc 28020000 .4byte .LLST17 + 1712 06c0 1A .uleb128 0x1a + 1713 06c1 6200 .ascii "b\000" + 1714 06c3 01 .byte 0x1 + 1715 06c4 CF .byte 0xcf + 1716 06c5 90000000 .4byte 0x90 + 1717 06c9 01 .byte 0x1 + 1718 06ca 50 .byte 0x50 + 1719 06cb 27 .uleb128 0x27 + 1720 06cc 90040000 .4byte 0x490 + 1721 06d0 04000000 .4byte .LBB56 + 1722 06d4 D8000000 .4byte .Ldebug_ranges0+0xd8 + 1723 06d8 01 .byte 0x1 + 1724 06d9 D3 .byte 0xd3 + 1725 06da 1E .uleb128 0x1e + 1726 06db A2040000 .4byte 0x4a2 + 1727 06df 46020000 .4byte .LLST18 + 1728 06e3 00 .byte 0 + 1729 06e4 00 .byte 0 + 1730 06e5 28 .uleb128 0x28 + 1731 06e6 90040000 .4byte 0x490 + 1732 06ea 00000000 .4byte .LFB11 + 1733 06ee 20000000 .4byte .LFE11 + 1734 06f2 02 .byte 0x2 + 1735 06f3 7D .byte 0x7d + 1736 06f4 00 .sleb128 0 + 1737 06f5 01 .byte 0x1 + 1738 06f6 04070000 .4byte 0x704 + 1739 06fa 1E .uleb128 0x1e + 1740 06fb A2040000 .4byte 0x4a2 + 1741 06ff 64020000 .4byte .LLST19 + 1742 0703 00 .byte 0 + 1743 0704 29 .uleb128 0x29 + 1744 0705 01 .byte 0x1 + 1745 0706 2D000000 .4byte .LASF69 + 1746 070a 01 .byte 0x1 + 1747 070b 0101 .2byte 0x101 + 1748 070d 01 .byte 0x1 + 1749 070e 3B040000 .4byte 0x43b + 1750 0712 00000000 .4byte .LFB12 + 1751 0716 54000000 .4byte .LFE12 + 1752 071a 98020000 .4byte .LLST20 + 1753 071e 01 .byte 0x1 + 1754 071f B8070000 .4byte 0x7b8 + 1755 0723 2A .uleb128 0x2a + 1756 0724 63747000 .ascii "ctp\000" + 1757 0728 01 .byte 0x1 + 1758 0729 0201 .2byte 0x102 + 1759 072b 3A020000 .4byte 0x23a + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 32 + + + 1760 072f B8020000 .4byte .LLST21 + 1761 0733 2B .uleb128 0x2b + 1762 0734 756D7000 .ascii "ump\000" + 1763 0738 01 .byte 0x1 + 1764 0739 0301 .2byte 0x103 + 1765 073b 3B040000 .4byte 0x43b + 1766 073f 01 .byte 0x1 + 1767 0740 54 .byte 0x54 + 1768 0741 2A .uleb128 0x2a + 1769 0742 6D7000 .ascii "mp\000" + 1770 0745 01 .byte 0x1 + 1771 0746 0301 .2byte 0x103 + 1772 0748 3B040000 .4byte 0x43b + 1773 074c D6020000 .4byte .LLST22 + 1774 0750 21 .uleb128 0x21 + 1775 0751 14000000 .4byte .LBB60 + 1776 0755 44000000 .4byte .LBE60 + 1777 0759 2C .uleb128 0x2c + 1778 075a 747000 .ascii "tp\000" + 1779 075d 01 .byte 0x1 + 1780 075e 1201 .2byte 0x112 + 1781 0760 3A020000 .4byte 0x23a + 1782 0764 2D .uleb128 0x2d + 1783 0765 34010000 .4byte .LASF70 + 1784 0769 01 .byte 0x1 + 1785 076a 1601 .2byte 0x116 + 1786 076c BC000000 .4byte 0xbc + 1787 0770 E9020000 .4byte .LLST23 + 1788 0774 2E .uleb128 0x2e + 1789 0775 AD040000 .4byte 0x4ad + 1790 0779 2C000000 .4byte .LBB61 + 1791 077d F0000000 .4byte .Ldebug_ranges0+0xf0 + 1792 0781 01 .byte 0x1 + 1793 0782 2501 .2byte 0x125 + 1794 0784 A1070000 .4byte 0x7a1 + 1795 0788 1E .uleb128 0x1e + 1796 0789 BE040000 .4byte 0x4be + 1797 078d FC020000 .4byte .LLST24 + 1798 0791 1B .uleb128 0x1b + 1799 0792 10010000 .4byte .Ldebug_ranges0+0x110 + 1800 0796 1F .uleb128 0x1f + 1801 0797 C9040000 .4byte 0x4c9 + 1802 079b 0F030000 .4byte .LLST25 + 1803 079f 00 .byte 0 + 1804 07a0 00 .byte 0 + 1805 07a1 25 .uleb128 0x25 + 1806 07a2 44000000 .4byte .LVL43 + 1807 07a6 38090000 .4byte 0x938 + 1808 07aa 23 .uleb128 0x23 + 1809 07ab 01 .byte 0x1 + 1810 07ac 51 .byte 0x51 + 1811 07ad 01 .byte 0x1 + 1812 07ae 30 .byte 0x30 + 1813 07af 23 .uleb128 0x23 + 1814 07b0 01 .byte 0x1 + 1815 07b1 50 .byte 0x50 + 1816 07b2 02 .byte 0x2 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 33 + + + 1817 07b3 75 .byte 0x75 + 1818 07b4 00 .sleb128 0 + 1819 07b5 00 .byte 0 + 1820 07b6 00 .byte 0 + 1821 07b7 00 .byte 0 + 1822 07b8 29 .uleb128 0x29 + 1823 07b9 01 .byte 0x1 + 1824 07ba CC000000 .4byte .LASF71 + 1825 07be 01 .byte 0x1 + 1826 07bf 3D01 .2byte 0x13d + 1827 07c1 01 .byte 0x1 + 1828 07c2 3B040000 .4byte 0x43b + 1829 07c6 00000000 .4byte .LFB13 + 1830 07ca 50000000 .4byte .LFE13 + 1831 07ce 22030000 .4byte .LLST26 + 1832 07d2 01 .byte 0x1 + 1833 07d3 67080000 .4byte 0x867 + 1834 07d7 2A .uleb128 0x2a + 1835 07d8 63747000 .ascii "ctp\000" + 1836 07dc 01 .byte 0x1 + 1837 07dd 3E01 .2byte 0x13e + 1838 07df 3A020000 .4byte 0x23a + 1839 07e3 42030000 .4byte .LLST27 + 1840 07e7 2B .uleb128 0x2b + 1841 07e8 756D7000 .ascii "ump\000" + 1842 07ec 01 .byte 0x1 + 1843 07ed 3F01 .2byte 0x13f + 1844 07ef 3B040000 .4byte 0x43b + 1845 07f3 01 .byte 0x1 + 1846 07f4 54 .byte 0x54 + 1847 07f5 2A .uleb128 0x2a + 1848 07f6 6D7000 .ascii "mp\000" + 1849 07f9 01 .byte 0x1 + 1850 07fa 3F01 .2byte 0x13f + 1851 07fc 3B040000 .4byte 0x43b + 1852 0800 60030000 .4byte .LLST28 + 1853 0804 21 .uleb128 0x21 + 1854 0805 12000000 .4byte .LBB67 + 1855 0809 40000000 .4byte .LBE67 + 1856 080d 2C .uleb128 0x2c + 1857 080e 747000 .ascii "tp\000" + 1858 0811 01 .byte 0x1 + 1859 0812 4F01 .2byte 0x14f + 1860 0814 3A020000 .4byte 0x23a + 1861 0818 2D .uleb128 0x2d + 1862 0819 34010000 .4byte .LASF70 + 1863 081d 01 .byte 0x1 + 1864 081e 5301 .2byte 0x153 + 1865 0820 BC000000 .4byte 0xbc + 1866 0824 73030000 .4byte .LLST29 + 1867 0828 2E .uleb128 0x2e + 1868 0829 AD040000 .4byte 0x4ad + 1869 082d 2A000000 .4byte .LBB68 + 1870 0831 30010000 .4byte .Ldebug_ranges0+0x130 + 1871 0835 01 .byte 0x1 + 1872 0836 6001 .2byte 0x160 + 1873 0838 55080000 .4byte 0x855 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 34 + + + 1874 083c 1E .uleb128 0x1e + 1875 083d BE040000 .4byte 0x4be + 1876 0841 86030000 .4byte .LLST30 + 1877 0845 1B .uleb128 0x1b + 1878 0846 50010000 .4byte .Ldebug_ranges0+0x150 + 1879 084a 1F .uleb128 0x1f + 1880 084b C9040000 .4byte 0x4c9 + 1881 084f 99030000 .4byte .LLST31 + 1882 0853 00 .byte 0 + 1883 0854 00 .byte 0 + 1884 0855 25 .uleb128 0x25 + 1885 0856 40000000 .4byte .LVL53 + 1886 085a 20090000 .4byte 0x920 + 1887 085e 23 .uleb128 0x23 + 1888 085f 01 .byte 0x1 + 1889 0860 50 .byte 0x50 + 1890 0861 02 .byte 0x2 + 1891 0862 75 .byte 0x75 + 1892 0863 00 .sleb128 0 + 1893 0864 00 .byte 0 + 1894 0865 00 .byte 0 + 1895 0866 00 .byte 0 + 1896 0867 2F .uleb128 0x2f + 1897 0868 01 .byte 0x1 + 1898 0869 25010000 .4byte .LASF72 + 1899 086d 01 .byte 0x1 + 1900 086e 7601 .2byte 0x176 + 1901 0870 01 .byte 0x1 + 1902 0871 00000000 .4byte .LFB14 + 1903 0875 48000000 .4byte .LFE14 + 1904 0879 AC030000 .4byte .LLST32 + 1905 087d 01 .byte 0x1 + 1906 087e FF080000 .4byte 0x8ff + 1907 0882 2B .uleb128 0x2b + 1908 0883 63747000 .ascii "ctp\000" + 1909 0887 01 .byte 0x1 + 1910 0888 7701 .2byte 0x177 + 1911 088a 3A020000 .4byte 0x23a + 1912 088e 01 .byte 0x1 + 1913 088f 54 .byte 0x54 + 1914 0890 30 .uleb128 0x30 + 1915 0891 0C000000 .4byte .LBB74 + 1916 0895 30000000 .4byte .LBE74 + 1917 0899 F5080000 .4byte 0x8f5 + 1918 089d 2A .uleb128 0x2a + 1919 089e 756D7000 .ascii "ump\000" + 1920 08a2 01 .byte 0x1 + 1921 08a3 7C01 .2byte 0x17c + 1922 08a5 3B040000 .4byte 0x43b + 1923 08a9 CC030000 .4byte .LLST33 + 1924 08ad 1B .uleb128 0x1b + 1925 08ae 70010000 .4byte .Ldebug_ranges0+0x170 + 1926 08b2 2C .uleb128 0x2c + 1927 08b3 747000 .ascii "tp\000" + 1928 08b6 01 .byte 0x1 + 1929 08b7 7F01 .2byte 0x17f + 1930 08b9 3A020000 .4byte 0x23a + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 35 + + + 1931 08bd 2E .uleb128 0x2e + 1932 08be AD040000 .4byte 0x4ad + 1933 08c2 1E000000 .4byte .LBB76 + 1934 08c6 88010000 .4byte .Ldebug_ranges0+0x188 + 1935 08ca 01 .byte 0x1 + 1936 08cb 7F01 .2byte 0x17f + 1937 08cd EA080000 .4byte 0x8ea + 1938 08d1 1E .uleb128 0x1e + 1939 08d2 BE040000 .4byte 0x4be + 1940 08d6 CC030000 .4byte .LLST33 + 1941 08da 1B .uleb128 0x1b + 1942 08db A0010000 .4byte .Ldebug_ranges0+0x1a0 + 1943 08df 1F .uleb128 0x1f + 1944 08e0 C9040000 .4byte 0x4c9 + 1945 08e4 DF030000 .4byte .LLST35 + 1946 08e8 00 .byte 0 + 1947 08e9 00 .byte 0 + 1948 08ea 24 .uleb128 0x24 + 1949 08eb 30000000 .4byte .LVL59 + 1950 08ef 20090000 .4byte 0x920 + 1951 08f3 00 .byte 0 + 1952 08f4 00 .byte 0 + 1953 08f5 24 .uleb128 0x24 + 1954 08f6 3E000000 .4byte .LVL60 + 1955 08fa 51090000 .4byte 0x951 + 1956 08fe 00 .byte 0 + 1957 08ff 31 .uleb128 0x31 + 1958 0900 17030000 .4byte .LASF81 + 1959 0904 08 .byte 0x8 + 1960 0905 72 .byte 0x72 + 1961 0906 A1030000 .4byte 0x3a1 + 1962 090a 01 .byte 0x1 + 1963 090b 01 .byte 0x1 + 1964 090c 32 .uleb128 0x32 + 1965 090d 01 .byte 0x1 + 1966 090e 6D020000 .4byte .LASF75 + 1967 0912 08 .byte 0x8 + 1968 0913 96 .byte 0x96 + 1969 0914 01 .byte 0x1 + 1970 0915 01 .byte 0x1 + 1971 0916 20090000 .4byte 0x920 + 1972 091a 33 .uleb128 0x33 + 1973 091b A6000000 .4byte 0xa6 + 1974 091f 00 .byte 0 + 1975 0920 34 .uleb128 0x34 + 1976 0921 01 .byte 0x1 + 1977 0922 97020000 .4byte .LASF74 + 1978 0926 08 .byte 0x8 + 1979 0927 93 .byte 0x93 + 1980 0928 01 .byte 0x1 + 1981 0929 3A020000 .4byte 0x23a + 1982 092d 01 .byte 0x1 + 1983 092e 38090000 .4byte 0x938 + 1984 0932 33 .uleb128 0x33 + 1985 0933 3A020000 .4byte 0x23a + 1986 0937 00 .byte 0 + 1987 0938 32 .uleb128 0x32 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 36 + + + 1988 0939 01 .byte 0x1 + 1989 093a EF020000 .4byte .LASF76 + 1990 093e 08 .byte 0x8 + 1991 093f 9C .byte 0x9c + 1992 0940 01 .byte 0x1 + 1993 0941 01 .byte 0x1 + 1994 0942 51090000 .4byte 0x951 + 1995 0946 33 .uleb128 0x33 + 1996 0947 3A020000 .4byte 0x23a + 1997 094b 33 .uleb128 0x33 + 1998 094c C7000000 .4byte 0xc7 + 1999 0950 00 .byte 0 + 2000 0951 35 .uleb128 0x35 + 2001 0952 01 .byte 0x1 + 2002 0953 A4000000 .4byte .LASF82 + 2003 0957 08 .byte 0x8 + 2004 0958 9F .byte 0x9f + 2005 0959 01 .byte 0x1 + 2006 095a 01 .byte 0x1 + 2007 095b 00 .byte 0 + 2008 .section .debug_abbrev,"",%progbits + 2009 .Ldebug_abbrev0: + 2010 0000 01 .uleb128 0x1 + 2011 0001 11 .uleb128 0x11 + 2012 0002 01 .byte 0x1 + 2013 0003 25 .uleb128 0x25 + 2014 0004 0E .uleb128 0xe + 2015 0005 13 .uleb128 0x13 + 2016 0006 0B .uleb128 0xb + 2017 0007 03 .uleb128 0x3 + 2018 0008 0E .uleb128 0xe + 2019 0009 1B .uleb128 0x1b + 2020 000a 0E .uleb128 0xe + 2021 000b 55 .uleb128 0x55 + 2022 000c 06 .uleb128 0x6 + 2023 000d 11 .uleb128 0x11 + 2024 000e 01 .uleb128 0x1 + 2025 000f 52 .uleb128 0x52 + 2026 0010 01 .uleb128 0x1 + 2027 0011 10 .uleb128 0x10 + 2028 0012 06 .uleb128 0x6 + 2029 0013 00 .byte 0 + 2030 0014 00 .byte 0 + 2031 0015 02 .uleb128 0x2 + 2032 0016 24 .uleb128 0x24 + 2033 0017 00 .byte 0 + 2034 0018 0B .uleb128 0xb + 2035 0019 0B .uleb128 0xb + 2036 001a 3E .uleb128 0x3e + 2037 001b 0B .uleb128 0xb + 2038 001c 03 .uleb128 0x3 + 2039 001d 08 .uleb128 0x8 + 2040 001e 00 .byte 0 + 2041 001f 00 .byte 0 + 2042 0020 03 .uleb128 0x3 + 2043 0021 24 .uleb128 0x24 + 2044 0022 00 .byte 0 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 37 + + + 2045 0023 0B .uleb128 0xb + 2046 0024 0B .uleb128 0xb + 2047 0025 3E .uleb128 0x3e + 2048 0026 0B .uleb128 0xb + 2049 0027 03 .uleb128 0x3 + 2050 0028 0E .uleb128 0xe + 2051 0029 00 .byte 0 + 2052 002a 00 .byte 0 + 2053 002b 04 .uleb128 0x4 + 2054 002c 16 .uleb128 0x16 + 2055 002d 00 .byte 0 + 2056 002e 03 .uleb128 0x3 + 2057 002f 0E .uleb128 0xe + 2058 0030 3A .uleb128 0x3a + 2059 0031 0B .uleb128 0xb + 2060 0032 3B .uleb128 0x3b + 2061 0033 0B .uleb128 0xb + 2062 0034 49 .uleb128 0x49 + 2063 0035 13 .uleb128 0x13 + 2064 0036 00 .byte 0 + 2065 0037 00 .byte 0 + 2066 0038 05 .uleb128 0x5 + 2067 0039 13 .uleb128 0x13 + 2068 003a 01 .byte 0x1 + 2069 003b 03 .uleb128 0x3 + 2070 003c 0E .uleb128 0xe + 2071 003d 0B .uleb128 0xb + 2072 003e 0B .uleb128 0xb + 2073 003f 3A .uleb128 0x3a + 2074 0040 0B .uleb128 0xb + 2075 0041 3B .uleb128 0x3b + 2076 0042 0B .uleb128 0xb + 2077 0043 01 .uleb128 0x1 + 2078 0044 13 .uleb128 0x13 + 2079 0045 00 .byte 0 + 2080 0046 00 .byte 0 + 2081 0047 06 .uleb128 0x6 + 2082 0048 0D .uleb128 0xd + 2083 0049 00 .byte 0 + 2084 004a 03 .uleb128 0x3 + 2085 004b 0E .uleb128 0xe + 2086 004c 3A .uleb128 0x3a + 2087 004d 0B .uleb128 0xb + 2088 004e 3B .uleb128 0x3b + 2089 004f 0B .uleb128 0xb + 2090 0050 49 .uleb128 0x49 + 2091 0051 13 .uleb128 0x13 + 2092 0052 38 .uleb128 0x38 + 2093 0053 0A .uleb128 0xa + 2094 0054 00 .byte 0 + 2095 0055 00 .byte 0 + 2096 0056 07 .uleb128 0x7 + 2097 0057 0D .uleb128 0xd + 2098 0058 00 .byte 0 + 2099 0059 03 .uleb128 0x3 + 2100 005a 08 .uleb128 0x8 + 2101 005b 3A .uleb128 0x3a + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 38 + + + 2102 005c 0B .uleb128 0xb + 2103 005d 3B .uleb128 0x3b + 2104 005e 0B .uleb128 0xb + 2105 005f 49 .uleb128 0x49 + 2106 0060 13 .uleb128 0x13 + 2107 0061 38 .uleb128 0x38 + 2108 0062 0A .uleb128 0xa + 2109 0063 00 .byte 0 + 2110 0064 00 .byte 0 + 2111 0065 08 .uleb128 0x8 + 2112 0066 13 .uleb128 0x13 + 2113 0067 01 .byte 0x1 + 2114 0068 0B .uleb128 0xb + 2115 0069 0B .uleb128 0xb + 2116 006a 3A .uleb128 0x3a + 2117 006b 0B .uleb128 0xb + 2118 006c 3B .uleb128 0x3b + 2119 006d 0B .uleb128 0xb + 2120 006e 01 .uleb128 0x1 + 2121 006f 13 .uleb128 0x13 + 2122 0070 00 .byte 0 + 2123 0071 00 .byte 0 + 2124 0072 09 .uleb128 0x9 + 2125 0073 0F .uleb128 0xf + 2126 0074 00 .byte 0 + 2127 0075 0B .uleb128 0xb + 2128 0076 0B .uleb128 0xb + 2129 0077 49 .uleb128 0x49 + 2130 0078 13 .uleb128 0x13 + 2131 0079 00 .byte 0 + 2132 007a 00 .byte 0 + 2133 007b 0A .uleb128 0xa + 2134 007c 0F .uleb128 0xf + 2135 007d 00 .byte 0 + 2136 007e 0B .uleb128 0xb + 2137 007f 0B .uleb128 0xb + 2138 0080 00 .byte 0 + 2139 0081 00 .byte 0 + 2140 0082 0B .uleb128 0xb + 2141 0083 0D .uleb128 0xd + 2142 0084 00 .byte 0 + 2143 0085 03 .uleb128 0x3 + 2144 0086 08 .uleb128 0x8 + 2145 0087 3A .uleb128 0x3a + 2146 0088 0B .uleb128 0xb + 2147 0089 3B .uleb128 0x3b + 2148 008a 05 .uleb128 0x5 + 2149 008b 49 .uleb128 0x49 + 2150 008c 13 .uleb128 0x13 + 2151 008d 38 .uleb128 0x38 + 2152 008e 0A .uleb128 0xa + 2153 008f 00 .byte 0 + 2154 0090 00 .byte 0 + 2155 0091 0C .uleb128 0xc + 2156 0092 13 .uleb128 0x13 + 2157 0093 01 .byte 0x1 + 2158 0094 03 .uleb128 0x3 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 39 + + + 2159 0095 0E .uleb128 0xe + 2160 0096 0B .uleb128 0xb + 2161 0097 0B .uleb128 0xb + 2162 0098 3A .uleb128 0x3a + 2163 0099 0B .uleb128 0xb + 2164 009a 3B .uleb128 0x3b + 2165 009b 05 .uleb128 0x5 + 2166 009c 01 .uleb128 0x1 + 2167 009d 13 .uleb128 0x13 + 2168 009e 00 .byte 0 + 2169 009f 00 .byte 0 + 2170 00a0 0D .uleb128 0xd + 2171 00a1 35 .uleb128 0x35 + 2172 00a2 00 .byte 0 + 2173 00a3 49 .uleb128 0x49 + 2174 00a4 13 .uleb128 0x13 + 2175 00a5 00 .byte 0 + 2176 00a6 00 .byte 0 + 2177 00a7 0E .uleb128 0xe + 2178 00a8 17 .uleb128 0x17 + 2179 00a9 01 .byte 0x1 + 2180 00aa 0B .uleb128 0xb + 2181 00ab 0B .uleb128 0xb + 2182 00ac 3A .uleb128 0x3a + 2183 00ad 0B .uleb128 0xb + 2184 00ae 3B .uleb128 0x3b + 2185 00af 0B .uleb128 0xb + 2186 00b0 01 .uleb128 0x1 + 2187 00b1 13 .uleb128 0x13 + 2188 00b2 00 .byte 0 + 2189 00b3 00 .byte 0 + 2190 00b4 0F .uleb128 0xf + 2191 00b5 0D .uleb128 0xd + 2192 00b6 00 .byte 0 + 2193 00b7 03 .uleb128 0x3 + 2194 00b8 0E .uleb128 0xe + 2195 00b9 3A .uleb128 0x3a + 2196 00ba 0B .uleb128 0xb + 2197 00bb 3B .uleb128 0x3b + 2198 00bc 0B .uleb128 0xb + 2199 00bd 49 .uleb128 0x49 + 2200 00be 13 .uleb128 0x13 + 2201 00bf 00 .byte 0 + 2202 00c0 00 .byte 0 + 2203 00c1 10 .uleb128 0x10 + 2204 00c2 26 .uleb128 0x26 + 2205 00c3 00 .byte 0 + 2206 00c4 49 .uleb128 0x49 + 2207 00c5 13 .uleb128 0x13 + 2208 00c6 00 .byte 0 + 2209 00c7 00 .byte 0 + 2210 00c8 11 .uleb128 0x11 + 2211 00c9 2E .uleb128 0x2e + 2212 00ca 01 .byte 0x1 + 2213 00cb 03 .uleb128 0x3 + 2214 00cc 0E .uleb128 0xe + 2215 00cd 3A .uleb128 0x3a + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 40 + + + 2216 00ce 0B .uleb128 0xb + 2217 00cf 3B .uleb128 0x3b + 2218 00d0 0B .uleb128 0xb + 2219 00d1 27 .uleb128 0x27 + 2220 00d2 0C .uleb128 0xc + 2221 00d3 49 .uleb128 0x49 + 2222 00d4 13 .uleb128 0x13 + 2223 00d5 20 .uleb128 0x20 + 2224 00d6 0B .uleb128 0xb + 2225 00d7 01 .uleb128 0x1 + 2226 00d8 13 .uleb128 0x13 + 2227 00d9 00 .byte 0 + 2228 00da 00 .byte 0 + 2229 00db 12 .uleb128 0x12 + 2230 00dc 05 .uleb128 0x5 + 2231 00dd 00 .byte 0 + 2232 00de 03 .uleb128 0x3 + 2233 00df 08 .uleb128 0x8 + 2234 00e0 3A .uleb128 0x3a + 2235 00e1 0B .uleb128 0xb + 2236 00e2 3B .uleb128 0x3b + 2237 00e3 0B .uleb128 0xb + 2238 00e4 49 .uleb128 0x49 + 2239 00e5 13 .uleb128 0x13 + 2240 00e6 00 .byte 0 + 2241 00e7 00 .byte 0 + 2242 00e8 13 .uleb128 0x13 + 2243 00e9 2E .uleb128 0x2e + 2244 00ea 01 .byte 0x1 + 2245 00eb 03 .uleb128 0x3 + 2246 00ec 0E .uleb128 0xe + 2247 00ed 3A .uleb128 0x3a + 2248 00ee 0B .uleb128 0xb + 2249 00ef 3B .uleb128 0x3b + 2250 00f0 0B .uleb128 0xb + 2251 00f1 27 .uleb128 0x27 + 2252 00f2 0C .uleb128 0xc + 2253 00f3 20 .uleb128 0x20 + 2254 00f4 0B .uleb128 0xb + 2255 00f5 01 .uleb128 0x1 + 2256 00f6 13 .uleb128 0x13 + 2257 00f7 00 .byte 0 + 2258 00f8 00 .byte 0 + 2259 00f9 14 .uleb128 0x14 + 2260 00fa 34 .uleb128 0x34 + 2261 00fb 00 .byte 0 + 2262 00fc 03 .uleb128 0x3 + 2263 00fd 08 .uleb128 0x8 + 2264 00fe 3A .uleb128 0x3a + 2265 00ff 0B .uleb128 0xb + 2266 0100 3B .uleb128 0x3b + 2267 0101 0B .uleb128 0xb + 2268 0102 49 .uleb128 0x49 + 2269 0103 13 .uleb128 0x13 + 2270 0104 00 .byte 0 + 2271 0105 00 .byte 0 + 2272 0106 15 .uleb128 0x15 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 41 + + + 2273 0107 2E .uleb128 0x2e + 2274 0108 01 .byte 0x1 + 2275 0109 3F .uleb128 0x3f + 2276 010a 0C .uleb128 0xc + 2277 010b 03 .uleb128 0x3 + 2278 010c 0E .uleb128 0xe + 2279 010d 3A .uleb128 0x3a + 2280 010e 0B .uleb128 0xb + 2281 010f 3B .uleb128 0x3b + 2282 0110 0B .uleb128 0xb + 2283 0111 27 .uleb128 0x27 + 2284 0112 0C .uleb128 0xc + 2285 0113 49 .uleb128 0x49 + 2286 0114 13 .uleb128 0x13 + 2287 0115 20 .uleb128 0x20 + 2288 0116 0B .uleb128 0xb + 2289 0117 01 .uleb128 0x1 + 2290 0118 13 .uleb128 0x13 + 2291 0119 00 .byte 0 + 2292 011a 00 .byte 0 + 2293 011b 16 .uleb128 0x16 + 2294 011c 2E .uleb128 0x2e + 2295 011d 01 .byte 0x1 + 2296 011e 3F .uleb128 0x3f + 2297 011f 0C .uleb128 0xc + 2298 0120 03 .uleb128 0x3 + 2299 0121 0E .uleb128 0xe + 2300 0122 3A .uleb128 0x3a + 2301 0123 0B .uleb128 0xb + 2302 0124 3B .uleb128 0x3b + 2303 0125 0B .uleb128 0xb + 2304 0126 27 .uleb128 0x27 + 2305 0127 0C .uleb128 0xc + 2306 0128 11 .uleb128 0x11 + 2307 0129 01 .uleb128 0x1 + 2308 012a 12 .uleb128 0x12 + 2309 012b 01 .uleb128 0x1 + 2310 012c 40 .uleb128 0x40 + 2311 012d 0A .uleb128 0xa + 2312 012e 9742 .uleb128 0x2117 + 2313 0130 0C .uleb128 0xc + 2314 0131 01 .uleb128 0x1 + 2315 0132 13 .uleb128 0x13 + 2316 0133 00 .byte 0 + 2317 0134 00 .byte 0 + 2318 0135 17 .uleb128 0x17 + 2319 0136 05 .uleb128 0x5 + 2320 0137 00 .byte 0 + 2321 0138 03 .uleb128 0x3 + 2322 0139 08 .uleb128 0x8 + 2323 013a 3A .uleb128 0x3a + 2324 013b 0B .uleb128 0xb + 2325 013c 3B .uleb128 0x3b + 2326 013d 0B .uleb128 0xb + 2327 013e 49 .uleb128 0x49 + 2328 013f 13 .uleb128 0x13 + 2329 0140 02 .uleb128 0x2 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 42 + + + 2330 0141 0A .uleb128 0xa + 2331 0142 00 .byte 0 + 2332 0143 00 .byte 0 + 2333 0144 18 .uleb128 0x18 + 2334 0145 2E .uleb128 0x2e + 2335 0146 01 .byte 0x1 + 2336 0147 3F .uleb128 0x3f + 2337 0148 0C .uleb128 0xc + 2338 0149 03 .uleb128 0x3 + 2339 014a 0E .uleb128 0xe + 2340 014b 3A .uleb128 0x3a + 2341 014c 0B .uleb128 0xb + 2342 014d 3B .uleb128 0x3b + 2343 014e 0B .uleb128 0xb + 2344 014f 27 .uleb128 0x27 + 2345 0150 0C .uleb128 0xc + 2346 0151 11 .uleb128 0x11 + 2347 0152 01 .uleb128 0x1 + 2348 0153 12 .uleb128 0x12 + 2349 0154 01 .uleb128 0x1 + 2350 0155 40 .uleb128 0x40 + 2351 0156 06 .uleb128 0x6 + 2352 0157 9742 .uleb128 0x2117 + 2353 0159 0C .uleb128 0xc + 2354 015a 01 .uleb128 0x1 + 2355 015b 13 .uleb128 0x13 + 2356 015c 00 .byte 0 + 2357 015d 00 .byte 0 + 2358 015e 19 .uleb128 0x19 + 2359 015f 05 .uleb128 0x5 + 2360 0160 00 .byte 0 + 2361 0161 03 .uleb128 0x3 + 2362 0162 08 .uleb128 0x8 + 2363 0163 3A .uleb128 0x3a + 2364 0164 0B .uleb128 0xb + 2365 0165 3B .uleb128 0x3b + 2366 0166 0B .uleb128 0xb + 2367 0167 49 .uleb128 0x49 + 2368 0168 13 .uleb128 0x13 + 2369 0169 02 .uleb128 0x2 + 2370 016a 06 .uleb128 0x6 + 2371 016b 00 .byte 0 + 2372 016c 00 .byte 0 + 2373 016d 1A .uleb128 0x1a + 2374 016e 34 .uleb128 0x34 + 2375 016f 00 .byte 0 + 2376 0170 03 .uleb128 0x3 + 2377 0171 08 .uleb128 0x8 + 2378 0172 3A .uleb128 0x3a + 2379 0173 0B .uleb128 0xb + 2380 0174 3B .uleb128 0x3b + 2381 0175 0B .uleb128 0xb + 2382 0176 49 .uleb128 0x49 + 2383 0177 13 .uleb128 0x13 + 2384 0178 02 .uleb128 0x2 + 2385 0179 0A .uleb128 0xa + 2386 017a 00 .byte 0 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 43 + + + 2387 017b 00 .byte 0 + 2388 017c 1B .uleb128 0x1b + 2389 017d 0B .uleb128 0xb + 2390 017e 01 .byte 0x1 + 2391 017f 55 .uleb128 0x55 + 2392 0180 06 .uleb128 0x6 + 2393 0181 00 .byte 0 + 2394 0182 00 .byte 0 + 2395 0183 1C .uleb128 0x1c + 2396 0184 34 .uleb128 0x34 + 2397 0185 00 .byte 0 + 2398 0186 03 .uleb128 0x3 + 2399 0187 08 .uleb128 0x8 + 2400 0188 3A .uleb128 0x3a + 2401 0189 0B .uleb128 0xb + 2402 018a 3B .uleb128 0x3b + 2403 018b 0B .uleb128 0xb + 2404 018c 49 .uleb128 0x49 + 2405 018d 13 .uleb128 0x13 + 2406 018e 02 .uleb128 0x2 + 2407 018f 06 .uleb128 0x6 + 2408 0190 00 .byte 0 + 2409 0191 00 .byte 0 + 2410 0192 1D .uleb128 0x1d + 2411 0193 1D .uleb128 0x1d + 2412 0194 01 .byte 0x1 + 2413 0195 31 .uleb128 0x31 + 2414 0196 13 .uleb128 0x13 + 2415 0197 52 .uleb128 0x52 + 2416 0198 01 .uleb128 0x1 + 2417 0199 55 .uleb128 0x55 + 2418 019a 06 .uleb128 0x6 + 2419 019b 58 .uleb128 0x58 + 2420 019c 0B .uleb128 0xb + 2421 019d 59 .uleb128 0x59 + 2422 019e 0B .uleb128 0xb + 2423 019f 01 .uleb128 0x1 + 2424 01a0 13 .uleb128 0x13 + 2425 01a1 00 .byte 0 + 2426 01a2 00 .byte 0 + 2427 01a3 1E .uleb128 0x1e + 2428 01a4 05 .uleb128 0x5 + 2429 01a5 00 .byte 0 + 2430 01a6 31 .uleb128 0x31 + 2431 01a7 13 .uleb128 0x13 + 2432 01a8 02 .uleb128 0x2 + 2433 01a9 06 .uleb128 0x6 + 2434 01aa 00 .byte 0 + 2435 01ab 00 .byte 0 + 2436 01ac 1F .uleb128 0x1f + 2437 01ad 34 .uleb128 0x34 + 2438 01ae 00 .byte 0 + 2439 01af 31 .uleb128 0x31 + 2440 01b0 13 .uleb128 0x13 + 2441 01b1 02 .uleb128 0x2 + 2442 01b2 06 .uleb128 0x6 + 2443 01b3 00 .byte 0 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 44 + + + 2444 01b4 00 .byte 0 + 2445 01b5 20 .uleb128 0x20 + 2446 01b6 1D .uleb128 0x1d + 2447 01b7 01 .byte 0x1 + 2448 01b8 31 .uleb128 0x31 + 2449 01b9 13 .uleb128 0x13 + 2450 01ba 11 .uleb128 0x11 + 2451 01bb 01 .uleb128 0x1 + 2452 01bc 12 .uleb128 0x12 + 2453 01bd 01 .uleb128 0x1 + 2454 01be 58 .uleb128 0x58 + 2455 01bf 0B .uleb128 0xb + 2456 01c0 59 .uleb128 0x59 + 2457 01c1 0B .uleb128 0xb + 2458 01c2 01 .uleb128 0x1 + 2459 01c3 13 .uleb128 0x13 + 2460 01c4 00 .byte 0 + 2461 01c5 00 .byte 0 + 2462 01c6 21 .uleb128 0x21 + 2463 01c7 0B .uleb128 0xb + 2464 01c8 01 .byte 0x1 + 2465 01c9 11 .uleb128 0x11 + 2466 01ca 01 .uleb128 0x1 + 2467 01cb 12 .uleb128 0x12 + 2468 01cc 01 .uleb128 0x1 + 2469 01cd 00 .byte 0 + 2470 01ce 00 .byte 0 + 2471 01cf 22 .uleb128 0x22 + 2472 01d0 898201 .uleb128 0x4109 + 2473 01d3 01 .byte 0x1 + 2474 01d4 11 .uleb128 0x11 + 2475 01d5 01 .uleb128 0x1 + 2476 01d6 9542 .uleb128 0x2115 + 2477 01d8 0C .uleb128 0xc + 2478 01d9 31 .uleb128 0x31 + 2479 01da 13 .uleb128 0x13 + 2480 01db 01 .uleb128 0x1 + 2481 01dc 13 .uleb128 0x13 + 2482 01dd 00 .byte 0 + 2483 01de 00 .byte 0 + 2484 01df 23 .uleb128 0x23 + 2485 01e0 8A8201 .uleb128 0x410a + 2486 01e3 00 .byte 0 + 2487 01e4 02 .uleb128 0x2 + 2488 01e5 0A .uleb128 0xa + 2489 01e6 9142 .uleb128 0x2111 + 2490 01e8 0A .uleb128 0xa + 2491 01e9 00 .byte 0 + 2492 01ea 00 .byte 0 + 2493 01eb 24 .uleb128 0x24 + 2494 01ec 898201 .uleb128 0x4109 + 2495 01ef 00 .byte 0 + 2496 01f0 11 .uleb128 0x11 + 2497 01f1 01 .uleb128 0x1 + 2498 01f2 31 .uleb128 0x31 + 2499 01f3 13 .uleb128 0x13 + 2500 01f4 00 .byte 0 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 45 + + + 2501 01f5 00 .byte 0 + 2502 01f6 25 .uleb128 0x25 + 2503 01f7 898201 .uleb128 0x4109 + 2504 01fa 01 .byte 0x1 + 2505 01fb 11 .uleb128 0x11 + 2506 01fc 01 .uleb128 0x1 + 2507 01fd 31 .uleb128 0x31 + 2508 01fe 13 .uleb128 0x13 + 2509 01ff 00 .byte 0 + 2510 0200 00 .byte 0 + 2511 0201 26 .uleb128 0x26 + 2512 0202 2E .uleb128 0x2e + 2513 0203 01 .byte 0x1 + 2514 0204 3F .uleb128 0x3f + 2515 0205 0C .uleb128 0xc + 2516 0206 03 .uleb128 0x3 + 2517 0207 0E .uleb128 0xe + 2518 0208 3A .uleb128 0x3a + 2519 0209 0B .uleb128 0xb + 2520 020a 3B .uleb128 0x3b + 2521 020b 0B .uleb128 0xb + 2522 020c 27 .uleb128 0x27 + 2523 020d 0C .uleb128 0xc + 2524 020e 49 .uleb128 0x49 + 2525 020f 13 .uleb128 0x13 + 2526 0210 11 .uleb128 0x11 + 2527 0211 01 .uleb128 0x1 + 2528 0212 12 .uleb128 0x12 + 2529 0213 01 .uleb128 0x1 + 2530 0214 40 .uleb128 0x40 + 2531 0215 0A .uleb128 0xa + 2532 0216 9742 .uleb128 0x2117 + 2533 0218 0C .uleb128 0xc + 2534 0219 01 .uleb128 0x1 + 2535 021a 13 .uleb128 0x13 + 2536 021b 00 .byte 0 + 2537 021c 00 .byte 0 + 2538 021d 27 .uleb128 0x27 + 2539 021e 1D .uleb128 0x1d + 2540 021f 01 .byte 0x1 + 2541 0220 31 .uleb128 0x31 + 2542 0221 13 .uleb128 0x13 + 2543 0222 52 .uleb128 0x52 + 2544 0223 01 .uleb128 0x1 + 2545 0224 55 .uleb128 0x55 + 2546 0225 06 .uleb128 0x6 + 2547 0226 58 .uleb128 0x58 + 2548 0227 0B .uleb128 0xb + 2549 0228 59 .uleb128 0x59 + 2550 0229 0B .uleb128 0xb + 2551 022a 00 .byte 0 + 2552 022b 00 .byte 0 + 2553 022c 28 .uleb128 0x28 + 2554 022d 2E .uleb128 0x2e + 2555 022e 01 .byte 0x1 + 2556 022f 31 .uleb128 0x31 + 2557 0230 13 .uleb128 0x13 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 46 + + + 2558 0231 11 .uleb128 0x11 + 2559 0232 01 .uleb128 0x1 + 2560 0233 12 .uleb128 0x12 + 2561 0234 01 .uleb128 0x1 + 2562 0235 40 .uleb128 0x40 + 2563 0236 0A .uleb128 0xa + 2564 0237 9742 .uleb128 0x2117 + 2565 0239 0C .uleb128 0xc + 2566 023a 01 .uleb128 0x1 + 2567 023b 13 .uleb128 0x13 + 2568 023c 00 .byte 0 + 2569 023d 00 .byte 0 + 2570 023e 29 .uleb128 0x29 + 2571 023f 2E .uleb128 0x2e + 2572 0240 01 .byte 0x1 + 2573 0241 3F .uleb128 0x3f + 2574 0242 0C .uleb128 0xc + 2575 0243 03 .uleb128 0x3 + 2576 0244 0E .uleb128 0xe + 2577 0245 3A .uleb128 0x3a + 2578 0246 0B .uleb128 0xb + 2579 0247 3B .uleb128 0x3b + 2580 0248 05 .uleb128 0x5 + 2581 0249 27 .uleb128 0x27 + 2582 024a 0C .uleb128 0xc + 2583 024b 49 .uleb128 0x49 + 2584 024c 13 .uleb128 0x13 + 2585 024d 11 .uleb128 0x11 + 2586 024e 01 .uleb128 0x1 + 2587 024f 12 .uleb128 0x12 + 2588 0250 01 .uleb128 0x1 + 2589 0251 40 .uleb128 0x40 + 2590 0252 06 .uleb128 0x6 + 2591 0253 9742 .uleb128 0x2117 + 2592 0255 0C .uleb128 0xc + 2593 0256 01 .uleb128 0x1 + 2594 0257 13 .uleb128 0x13 + 2595 0258 00 .byte 0 + 2596 0259 00 .byte 0 + 2597 025a 2A .uleb128 0x2a + 2598 025b 34 .uleb128 0x34 + 2599 025c 00 .byte 0 + 2600 025d 03 .uleb128 0x3 + 2601 025e 08 .uleb128 0x8 + 2602 025f 3A .uleb128 0x3a + 2603 0260 0B .uleb128 0xb + 2604 0261 3B .uleb128 0x3b + 2605 0262 05 .uleb128 0x5 + 2606 0263 49 .uleb128 0x49 + 2607 0264 13 .uleb128 0x13 + 2608 0265 02 .uleb128 0x2 + 2609 0266 06 .uleb128 0x6 + 2610 0267 00 .byte 0 + 2611 0268 00 .byte 0 + 2612 0269 2B .uleb128 0x2b + 2613 026a 34 .uleb128 0x34 + 2614 026b 00 .byte 0 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 47 + + + 2615 026c 03 .uleb128 0x3 + 2616 026d 08 .uleb128 0x8 + 2617 026e 3A .uleb128 0x3a + 2618 026f 0B .uleb128 0xb + 2619 0270 3B .uleb128 0x3b + 2620 0271 05 .uleb128 0x5 + 2621 0272 49 .uleb128 0x49 + 2622 0273 13 .uleb128 0x13 + 2623 0274 02 .uleb128 0x2 + 2624 0275 0A .uleb128 0xa + 2625 0276 00 .byte 0 + 2626 0277 00 .byte 0 + 2627 0278 2C .uleb128 0x2c + 2628 0279 34 .uleb128 0x34 + 2629 027a 00 .byte 0 + 2630 027b 03 .uleb128 0x3 + 2631 027c 08 .uleb128 0x8 + 2632 027d 3A .uleb128 0x3a + 2633 027e 0B .uleb128 0xb + 2634 027f 3B .uleb128 0x3b + 2635 0280 05 .uleb128 0x5 + 2636 0281 49 .uleb128 0x49 + 2637 0282 13 .uleb128 0x13 + 2638 0283 00 .byte 0 + 2639 0284 00 .byte 0 + 2640 0285 2D .uleb128 0x2d + 2641 0286 34 .uleb128 0x34 + 2642 0287 00 .byte 0 + 2643 0288 03 .uleb128 0x3 + 2644 0289 0E .uleb128 0xe + 2645 028a 3A .uleb128 0x3a + 2646 028b 0B .uleb128 0xb + 2647 028c 3B .uleb128 0x3b + 2648 028d 05 .uleb128 0x5 + 2649 028e 49 .uleb128 0x49 + 2650 028f 13 .uleb128 0x13 + 2651 0290 02 .uleb128 0x2 + 2652 0291 06 .uleb128 0x6 + 2653 0292 00 .byte 0 + 2654 0293 00 .byte 0 + 2655 0294 2E .uleb128 0x2e + 2656 0295 1D .uleb128 0x1d + 2657 0296 01 .byte 0x1 + 2658 0297 31 .uleb128 0x31 + 2659 0298 13 .uleb128 0x13 + 2660 0299 52 .uleb128 0x52 + 2661 029a 01 .uleb128 0x1 + 2662 029b 55 .uleb128 0x55 + 2663 029c 06 .uleb128 0x6 + 2664 029d 58 .uleb128 0x58 + 2665 029e 0B .uleb128 0xb + 2666 029f 59 .uleb128 0x59 + 2667 02a0 05 .uleb128 0x5 + 2668 02a1 01 .uleb128 0x1 + 2669 02a2 13 .uleb128 0x13 + 2670 02a3 00 .byte 0 + 2671 02a4 00 .byte 0 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 48 + + + 2672 02a5 2F .uleb128 0x2f + 2673 02a6 2E .uleb128 0x2e + 2674 02a7 01 .byte 0x1 + 2675 02a8 3F .uleb128 0x3f + 2676 02a9 0C .uleb128 0xc + 2677 02aa 03 .uleb128 0x3 + 2678 02ab 0E .uleb128 0xe + 2679 02ac 3A .uleb128 0x3a + 2680 02ad 0B .uleb128 0xb + 2681 02ae 3B .uleb128 0x3b + 2682 02af 05 .uleb128 0x5 + 2683 02b0 27 .uleb128 0x27 + 2684 02b1 0C .uleb128 0xc + 2685 02b2 11 .uleb128 0x11 + 2686 02b3 01 .uleb128 0x1 + 2687 02b4 12 .uleb128 0x12 + 2688 02b5 01 .uleb128 0x1 + 2689 02b6 40 .uleb128 0x40 + 2690 02b7 06 .uleb128 0x6 + 2691 02b8 9742 .uleb128 0x2117 + 2692 02ba 0C .uleb128 0xc + 2693 02bb 01 .uleb128 0x1 + 2694 02bc 13 .uleb128 0x13 + 2695 02bd 00 .byte 0 + 2696 02be 00 .byte 0 + 2697 02bf 30 .uleb128 0x30 + 2698 02c0 0B .uleb128 0xb + 2699 02c1 01 .byte 0x1 + 2700 02c2 11 .uleb128 0x11 + 2701 02c3 01 .uleb128 0x1 + 2702 02c4 12 .uleb128 0x12 + 2703 02c5 01 .uleb128 0x1 + 2704 02c6 01 .uleb128 0x1 + 2705 02c7 13 .uleb128 0x13 + 2706 02c8 00 .byte 0 + 2707 02c9 00 .byte 0 + 2708 02ca 31 .uleb128 0x31 + 2709 02cb 34 .uleb128 0x34 + 2710 02cc 00 .byte 0 + 2711 02cd 03 .uleb128 0x3 + 2712 02ce 0E .uleb128 0xe + 2713 02cf 3A .uleb128 0x3a + 2714 02d0 0B .uleb128 0xb + 2715 02d1 3B .uleb128 0x3b + 2716 02d2 0B .uleb128 0xb + 2717 02d3 49 .uleb128 0x49 + 2718 02d4 13 .uleb128 0x13 + 2719 02d5 3F .uleb128 0x3f + 2720 02d6 0C .uleb128 0xc + 2721 02d7 3C .uleb128 0x3c + 2722 02d8 0C .uleb128 0xc + 2723 02d9 00 .byte 0 + 2724 02da 00 .byte 0 + 2725 02db 32 .uleb128 0x32 + 2726 02dc 2E .uleb128 0x2e + 2727 02dd 01 .byte 0x1 + 2728 02de 3F .uleb128 0x3f + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 49 + + + 2729 02df 0C .uleb128 0xc + 2730 02e0 03 .uleb128 0x3 + 2731 02e1 0E .uleb128 0xe + 2732 02e2 3A .uleb128 0x3a + 2733 02e3 0B .uleb128 0xb + 2734 02e4 3B .uleb128 0x3b + 2735 02e5 0B .uleb128 0xb + 2736 02e6 27 .uleb128 0x27 + 2737 02e7 0C .uleb128 0xc + 2738 02e8 3C .uleb128 0x3c + 2739 02e9 0C .uleb128 0xc + 2740 02ea 01 .uleb128 0x1 + 2741 02eb 13 .uleb128 0x13 + 2742 02ec 00 .byte 0 + 2743 02ed 00 .byte 0 + 2744 02ee 33 .uleb128 0x33 + 2745 02ef 05 .uleb128 0x5 + 2746 02f0 00 .byte 0 + 2747 02f1 49 .uleb128 0x49 + 2748 02f2 13 .uleb128 0x13 + 2749 02f3 00 .byte 0 + 2750 02f4 00 .byte 0 + 2751 02f5 34 .uleb128 0x34 + 2752 02f6 2E .uleb128 0x2e + 2753 02f7 01 .byte 0x1 + 2754 02f8 3F .uleb128 0x3f + 2755 02f9 0C .uleb128 0xc + 2756 02fa 03 .uleb128 0x3 + 2757 02fb 0E .uleb128 0xe + 2758 02fc 3A .uleb128 0x3a + 2759 02fd 0B .uleb128 0xb + 2760 02fe 3B .uleb128 0x3b + 2761 02ff 0B .uleb128 0xb + 2762 0300 27 .uleb128 0x27 + 2763 0301 0C .uleb128 0xc + 2764 0302 49 .uleb128 0x49 + 2765 0303 13 .uleb128 0x13 + 2766 0304 3C .uleb128 0x3c + 2767 0305 0C .uleb128 0xc + 2768 0306 01 .uleb128 0x1 + 2769 0307 13 .uleb128 0x13 + 2770 0308 00 .byte 0 + 2771 0309 00 .byte 0 + 2772 030a 35 .uleb128 0x35 + 2773 030b 2E .uleb128 0x2e + 2774 030c 00 .byte 0 + 2775 030d 3F .uleb128 0x3f + 2776 030e 0C .uleb128 0xc + 2777 030f 03 .uleb128 0x3 + 2778 0310 0E .uleb128 0xe + 2779 0311 3A .uleb128 0x3a + 2780 0312 0B .uleb128 0xb + 2781 0313 3B .uleb128 0x3b + 2782 0314 0B .uleb128 0xb + 2783 0315 27 .uleb128 0x27 + 2784 0316 0C .uleb128 0xc + 2785 0317 3C .uleb128 0x3c + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 50 + + + 2786 0318 0C .uleb128 0xc + 2787 0319 00 .byte 0 + 2788 031a 00 .byte 0 + 2789 031b 00 .byte 0 + 2790 .section .debug_loc,"",%progbits + 2791 .Ldebug_loc0: + 2792 .LLST0: + 2793 0000 00000000 .4byte .LFB9 + 2794 0004 02000000 .4byte .LCFI0 + 2795 0008 0200 .2byte 0x2 + 2796 000a 7D .byte 0x7d + 2797 000b 00 .sleb128 0 + 2798 000c 02000000 .4byte .LCFI0 + 2799 0010 C4000000 .4byte .LFE9 + 2800 0014 0200 .2byte 0x2 + 2801 0016 7D .byte 0x7d + 2802 0017 18 .sleb128 24 + 2803 0018 00000000 .4byte 0 + 2804 001c 00000000 .4byte 0 + 2805 .LLST1: + 2806 0020 00000000 .4byte .LVL1 + 2807 0024 16000000 .4byte .LVL4 + 2808 0028 0100 .2byte 0x1 + 2809 002a 50 .byte 0x50 + 2810 002b 16000000 .4byte .LVL4 + 2811 002f B2000000 .4byte .LVL22 + 2812 0033 0100 .2byte 0x1 + 2813 0035 55 .byte 0x55 + 2814 0036 B2000000 .4byte .LVL22 + 2815 003a BC000000 .4byte .LVL23 + 2816 003e 0100 .2byte 0x1 + 2817 0040 50 .byte 0x50 + 2818 0041 BC000000 .4byte .LVL23 + 2819 0045 C4000000 .4byte .LFE9 + 2820 0049 0100 .2byte 0x1 + 2821 004b 55 .byte 0x55 + 2822 004c 00000000 .4byte 0 + 2823 0050 00000000 .4byte 0 + 2824 .LLST2: + 2825 0054 0E000000 .4byte .LVL3 + 2826 0058 24000000 .4byte .LVL5 + 2827 005c 0100 .2byte 0x1 + 2828 005e 53 .byte 0x53 + 2829 005f 4A000000 .4byte .LVL8 + 2830 0063 54000000 .4byte .LVL9 + 2831 0067 0100 .2byte 0x1 + 2832 0069 53 .byte 0x53 + 2833 006a 54000000 .4byte .LVL9 + 2834 006e 59000000 .4byte .LVL10-1 + 2835 0072 0100 .2byte 0x1 + 2836 0074 50 .byte 0x50 + 2837 0075 5C000000 .4byte .LVL11 + 2838 0079 B2000000 .4byte .LVL22 + 2839 007d 0100 .2byte 0x1 + 2840 007f 53 .byte 0x53 + 2841 0080 BC000000 .4byte .LVL23 + 2842 0084 C4000000 .4byte .LFE9 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 51 + + + 2843 0088 0100 .2byte 0x1 + 2844 008a 53 .byte 0x53 + 2845 008b 00000000 .4byte 0 + 2846 008f 00000000 .4byte 0 + 2847 .LLST3: + 2848 0093 24000000 .4byte .LVL5 + 2849 0097 4A000000 .4byte .LVL8 + 2850 009b 0100 .2byte 0x1 + 2851 009d 55 .byte 0x55 + 2852 009e 00000000 .4byte 0 + 2853 00a2 00000000 .4byte 0 + 2854 .LLST4: + 2855 00a6 24000000 .4byte .LVL5 + 2856 00aa 4A000000 .4byte .LVL8 + 2857 00ae 0100 .2byte 0x1 + 2858 00b0 54 .byte 0x54 + 2859 00b1 00000000 .4byte 0 + 2860 00b5 00000000 .4byte 0 + 2861 .LLST5: + 2862 00b9 24000000 .4byte .LVL5 + 2863 00bd 26000000 .4byte .LVL6 + 2864 00c1 0100 .2byte 0x1 + 2865 00c3 55 .byte 0x55 + 2866 00c4 26000000 .4byte .LVL6 + 2867 00c8 49000000 .4byte .LVL8-1 + 2868 00cc 0100 .2byte 0x1 + 2869 00ce 53 .byte 0x53 + 2870 00cf 00000000 .4byte 0 + 2871 00d3 00000000 .4byte 0 + 2872 .LLST6: + 2873 00d7 4A000000 .4byte .LVL8 + 2874 00db 54000000 .4byte .LVL9 + 2875 00df 0100 .2byte 0x1 + 2876 00e1 53 .byte 0x53 + 2877 00e2 54000000 .4byte .LVL9 + 2878 00e6 59000000 .4byte .LVL10-1 + 2879 00ea 0100 .2byte 0x1 + 2880 00ec 50 .byte 0x50 + 2881 00ed 00000000 .4byte 0 + 2882 00f1 00000000 .4byte 0 + 2883 .LLST7: + 2884 00f5 5C000000 .4byte .LVL11 + 2885 00f9 82000000 .4byte .LVL15 + 2886 00fd 0100 .2byte 0x1 + 2887 00ff 53 .byte 0x53 + 2888 0100 00000000 .4byte 0 + 2889 0104 00000000 .4byte 0 + 2890 .LLST8: + 2891 0108 62000000 .4byte .LVL12 + 2892 010c 82000000 .4byte .LVL15 + 2893 0110 0100 .2byte 0x1 + 2894 0112 56 .byte 0x56 + 2895 0113 00000000 .4byte 0 + 2896 0117 00000000 .4byte 0 + 2897 .LLST9: + 2898 011b 62000000 .4byte .LVL12 + 2899 011f 82000000 .4byte .LVL15 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 52 + + + 2900 0123 0100 .2byte 0x1 + 2901 0125 53 .byte 0x53 + 2902 0126 00000000 .4byte 0 + 2903 012a 00000000 .4byte 0 + 2904 .LLST10: + 2905 012e 62000000 .4byte .LVL12 + 2906 0132 6A000000 .4byte .LVL13 + 2907 0136 0100 .2byte 0x1 + 2908 0138 56 .byte 0x56 + 2909 0139 6A000000 .4byte .LVL13 + 2910 013d 82000000 .4byte .LVL15 + 2911 0141 0100 .2byte 0x1 + 2912 0143 52 .byte 0x52 + 2913 0144 00000000 .4byte 0 + 2914 0148 00000000 .4byte 0 + 2915 .LLST11: + 2916 014c 82000000 .4byte .LVL15 + 2917 0150 A8000000 .4byte .LVL20 + 2918 0154 0100 .2byte 0x1 + 2919 0156 53 .byte 0x53 + 2920 0157 A8000000 .4byte .LVL20 + 2921 015b AC000000 .4byte .LVL21 + 2922 015f 0200 .2byte 0x2 + 2923 0161 72 .byte 0x72 + 2924 0162 04 .sleb128 4 + 2925 0163 BC000000 .4byte .LVL23 + 2926 0167 C4000000 .4byte .LFE9 + 2927 016b 0100 .2byte 0x1 + 2928 016d 53 .byte 0x53 + 2929 016e 00000000 .4byte 0 + 2930 0172 00000000 .4byte 0 + 2931 .LLST12: + 2932 0176 88000000 .4byte .LVL16 + 2933 017a B2000000 .4byte .LVL22 + 2934 017e 0100 .2byte 0x1 + 2935 0180 56 .byte 0x56 + 2936 0181 BC000000 .4byte .LVL23 + 2937 0185 C4000000 .4byte .LFE9 + 2938 0189 0100 .2byte 0x1 + 2939 018b 56 .byte 0x56 + 2940 018c 00000000 .4byte 0 + 2941 0190 00000000 .4byte 0 + 2942 .LLST13: + 2943 0194 88000000 .4byte .LVL16 + 2944 0198 A8000000 .4byte .LVL20 + 2945 019c 0100 .2byte 0x1 + 2946 019e 53 .byte 0x53 + 2947 019f A8000000 .4byte .LVL20 + 2948 01a3 AC000000 .4byte .LVL21 + 2949 01a7 0200 .2byte 0x2 + 2950 01a9 72 .byte 0x72 + 2951 01aa 04 .sleb128 4 + 2952 01ab BC000000 .4byte .LVL23 + 2953 01af C4000000 .4byte .LFE9 + 2954 01b3 0100 .2byte 0x1 + 2955 01b5 53 .byte 0x53 + 2956 01b6 00000000 .4byte 0 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 53 + + + 2957 01ba 00000000 .4byte 0 + 2958 .LLST14: + 2959 01be 88000000 .4byte .LVL16 + 2960 01c2 90000000 .4byte .LVL17 + 2961 01c6 0100 .2byte 0x1 + 2962 01c8 56 .byte 0x56 + 2963 01c9 90000000 .4byte .LVL17 + 2964 01cd 9C000000 .4byte .LVL19 + 2965 01d1 0100 .2byte 0x1 + 2966 01d3 52 .byte 0x52 + 2967 01d4 BC000000 .4byte .LVL23 + 2968 01d8 BE000000 .4byte .LVL24 + 2969 01dc 0100 .2byte 0x1 + 2970 01de 52 .byte 0x52 + 2971 01df 00000000 .4byte 0 + 2972 01e3 00000000 .4byte 0 + 2973 .LLST15: + 2974 01e7 00000000 .4byte .LFB8 + 2975 01eb 02000000 .4byte .LCFI1 + 2976 01ef 0200 .2byte 0x2 + 2977 01f1 7D .byte 0x7d + 2978 01f2 00 .sleb128 0 + 2979 01f3 02000000 .4byte .LCFI1 + 2980 01f7 0C000000 .4byte .LFE8 + 2981 01fb 0200 .2byte 0x2 + 2982 01fd 7D .byte 0x7d + 2983 01fe 08 .sleb128 8 + 2984 01ff 00000000 .4byte 0 + 2985 0203 00000000 .4byte 0 + 2986 .LLST16: + 2987 0207 00000000 .4byte .LVL25 + 2988 020b 07000000 .4byte .LVL26-1 + 2989 020f 0100 .2byte 0x1 + 2990 0211 50 .byte 0x50 + 2991 0212 07000000 .4byte .LVL26-1 + 2992 0216 0C000000 .4byte .LFE8 + 2993 021a 0400 .2byte 0x4 + 2994 021c F3 .byte 0xf3 + 2995 021d 01 .uleb128 0x1 + 2996 021e 50 .byte 0x50 + 2997 021f 9F .byte 0x9f + 2998 0220 00000000 .4byte 0 + 2999 0224 00000000 .4byte 0 + 3000 .LLST17: + 3001 0228 00000000 .4byte .LVL27 + 3002 022c 08000000 .4byte .LVL29 + 3003 0230 0100 .2byte 0x1 + 3004 0232 50 .byte 0x50 + 3005 0233 08000000 .4byte .LVL29 + 3006 0237 24000000 .4byte .LFE10 + 3007 023b 0100 .2byte 0x1 + 3008 023d 53 .byte 0x53 + 3009 023e 00000000 .4byte 0 + 3010 0242 00000000 .4byte 0 + 3011 .LLST18: + 3012 0246 04000000 .4byte .LVL28 + 3013 024a 08000000 .4byte .LVL29 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 54 + + + 3014 024e 0100 .2byte 0x1 + 3015 0250 50 .byte 0x50 + 3016 0251 08000000 .4byte .LVL29 + 3017 0255 24000000 .4byte .LFE10 + 3018 0259 0100 .2byte 0x1 + 3019 025b 53 .byte 0x53 + 3020 025c 00000000 .4byte 0 + 3021 0260 00000000 .4byte 0 + 3022 .LLST19: + 3023 0264 00000000 .4byte .LVL30 + 3024 0268 08000000 .4byte .LVL31 + 3025 026c 0100 .2byte 0x1 + 3026 026e 50 .byte 0x50 + 3027 026f 08000000 .4byte .LVL31 + 3028 0273 0A000000 .4byte .LVL32 + 3029 0277 0100 .2byte 0x1 + 3030 0279 53 .byte 0x53 + 3031 027a 0A000000 .4byte .LVL32 + 3032 027e 0E000000 .4byte .LVL33 + 3033 0282 0100 .2byte 0x1 + 3034 0284 50 .byte 0x50 + 3035 0285 0E000000 .4byte .LVL33 + 3036 0289 20000000 .4byte .LFE11 + 3037 028d 0100 .2byte 0x1 + 3038 028f 53 .byte 0x53 + 3039 0290 00000000 .4byte 0 + 3040 0294 00000000 .4byte 0 + 3041 .LLST20: + 3042 0298 00000000 .4byte .LFB12 + 3043 029c 02000000 .4byte .LCFI2 + 3044 02a0 0200 .2byte 0x2 + 3045 02a2 7D .byte 0x7d + 3046 02a3 00 .sleb128 0 + 3047 02a4 02000000 .4byte .LCFI2 + 3048 02a8 54000000 .4byte .LFE12 + 3049 02ac 0200 .2byte 0x2 + 3050 02ae 7D .byte 0x7d + 3051 02af 10 .sleb128 16 + 3052 02b0 00000000 .4byte 0 + 3053 02b4 00000000 .4byte 0 + 3054 .LLST21: + 3055 02b8 06000000 .4byte .LVL34 + 3056 02bc 36000000 .4byte .LVL41 + 3057 02c0 0100 .2byte 0x1 + 3058 02c2 50 .byte 0x50 + 3059 02c3 4A000000 .4byte .LVL44 + 3060 02c7 54000000 .4byte .LFE12 + 3061 02cb 0100 .2byte 0x1 + 3062 02cd 50 .byte 0x50 + 3063 02ce 00000000 .4byte 0 + 3064 02d2 00000000 .4byte 0 + 3065 .LLST22: + 3066 02d6 16000000 .4byte .LVL36 + 3067 02da 2E000000 .4byte .LVL39 + 3068 02de 0100 .2byte 0x1 + 3069 02e0 53 .byte 0x53 + 3070 02e1 00000000 .4byte 0 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 55 + + + 3071 02e5 00000000 .4byte 0 + 3072 .LLST23: + 3073 02e9 16000000 .4byte .LVL36 + 3074 02ed 3A000000 .4byte .LVL42 + 3075 02f1 0100 .2byte 0x1 + 3076 02f3 51 .byte 0x51 + 3077 02f4 00000000 .4byte 0 + 3078 02f8 00000000 .4byte 0 + 3079 .LLST24: + 3080 02fc 32000000 .4byte .LVL40 + 3081 0300 44000000 .4byte .LVL43 + 3082 0304 0100 .2byte 0x1 + 3083 0306 54 .byte 0x54 + 3084 0307 00000000 .4byte 0 + 3085 030b 00000000 .4byte 0 + 3086 .LLST25: + 3087 030f 32000000 .4byte .LVL40 + 3088 0313 44000000 .4byte .LVL43 + 3089 0317 0100 .2byte 0x1 + 3090 0319 55 .byte 0x55 + 3091 031a 00000000 .4byte 0 + 3092 031e 00000000 .4byte 0 + 3093 .LLST26: + 3094 0322 00000000 .4byte .LFB13 + 3095 0326 02000000 .4byte .LCFI3 + 3096 032a 0200 .2byte 0x2 + 3097 032c 7D .byte 0x7d + 3098 032d 00 .sleb128 0 + 3099 032e 02000000 .4byte .LCFI3 + 3100 0332 50000000 .4byte .LFE13 + 3101 0336 0200 .2byte 0x2 + 3102 0338 7D .byte 0x7d + 3103 0339 10 .sleb128 16 + 3104 033a 00000000 .4byte 0 + 3105 033e 00000000 .4byte 0 + 3106 .LLST27: + 3107 0342 06000000 .4byte .LVL45 + 3108 0346 34000000 .4byte .LVL52 + 3109 034a 0100 .2byte 0x1 + 3110 034c 50 .byte 0x50 + 3111 034d 44000000 .4byte .LVL54 + 3112 0351 4A000000 .4byte .LVL55 + 3113 0355 0100 .2byte 0x1 + 3114 0357 50 .byte 0x50 + 3115 0358 00000000 .4byte 0 + 3116 035c 00000000 .4byte 0 + 3117 .LLST28: + 3118 0360 14000000 .4byte .LVL47 + 3119 0364 2C000000 .4byte .LVL50 + 3120 0368 0100 .2byte 0x1 + 3121 036a 53 .byte 0x53 + 3122 036b 00000000 .4byte 0 + 3123 036f 00000000 .4byte 0 + 3124 .LLST29: + 3125 0373 14000000 .4byte .LVL47 + 3126 0377 3F000000 .4byte .LVL53-1 + 3127 037b 0100 .2byte 0x1 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 56 + + + 3128 037d 51 .byte 0x51 + 3129 037e 00000000 .4byte 0 + 3130 0382 00000000 .4byte 0 + 3131 .LLST30: + 3132 0386 30000000 .4byte .LVL51 + 3133 038a 44000000 .4byte .LVL54 + 3134 038e 0100 .2byte 0x1 + 3135 0390 54 .byte 0x54 + 3136 0391 00000000 .4byte 0 + 3137 0395 00000000 .4byte 0 + 3138 .LLST31: + 3139 0399 30000000 .4byte .LVL51 + 3140 039d 44000000 .4byte .LVL54 + 3141 03a1 0100 .2byte 0x1 + 3142 03a3 55 .byte 0x55 + 3143 03a4 00000000 .4byte 0 + 3144 03a8 00000000 .4byte 0 + 3145 .LLST32: + 3146 03ac 00000000 .4byte .LFB14 + 3147 03b0 04000000 .4byte .LCFI4 + 3148 03b4 0200 .2byte 0x2 + 3149 03b6 7D .byte 0x7d + 3150 03b7 00 .sleb128 0 + 3151 03b8 04000000 .4byte .LCFI4 + 3152 03bc 48000000 .4byte .LFE14 + 3153 03c0 0200 .2byte 0x2 + 3154 03c2 7D .byte 0x7d + 3155 03c3 10 .sleb128 16 + 3156 03c4 00000000 .4byte 0 + 3157 03c8 00000000 .4byte 0 + 3158 .LLST33: + 3159 03cc 0E000000 .4byte .LVL57 + 3160 03d0 2F000000 .4byte .LVL59-1 + 3161 03d4 0100 .2byte 0x1 + 3162 03d6 53 .byte 0x53 + 3163 03d7 00000000 .4byte 0 + 3164 03db 00000000 .4byte 0 + 3165 .LLST35: + 3166 03df 10000000 .4byte .LVL58 + 3167 03e3 2F000000 .4byte .LVL59-1 + 3168 03e7 0100 .2byte 0x1 + 3169 03e9 52 .byte 0x52 + 3170 03ea 00000000 .4byte 0 + 3171 03ee 00000000 .4byte 0 + 3172 .section .debug_aranges,"",%progbits + 3173 0000 54000000 .4byte 0x54 + 3174 0004 0200 .2byte 0x2 + 3175 0006 00000000 .4byte .Ldebug_info0 + 3176 000a 04 .byte 0x4 + 3177 000b 00 .byte 0 + 3178 000c 0000 .2byte 0 + 3179 000e 0000 .2byte 0 + 3180 0010 00000000 .4byte .LFB7 + 3181 0014 0A000000 .4byte .LFE7-.LFB7 + 3182 0018 00000000 .4byte .LFB9 + 3183 001c C4000000 .4byte .LFE9-.LFB9 + 3184 0020 00000000 .4byte .LFB8 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 57 + + + 3185 0024 0C000000 .4byte .LFE8-.LFB8 + 3186 0028 00000000 .4byte .LFB10 + 3187 002c 24000000 .4byte .LFE10-.LFB10 + 3188 0030 00000000 .4byte .LFB11 + 3189 0034 20000000 .4byte .LFE11-.LFB11 + 3190 0038 00000000 .4byte .LFB12 + 3191 003c 54000000 .4byte .LFE12-.LFB12 + 3192 0040 00000000 .4byte .LFB13 + 3193 0044 50000000 .4byte .LFE13-.LFB13 + 3194 0048 00000000 .4byte .LFB14 + 3195 004c 48000000 .4byte .LFE14-.LFB14 + 3196 0050 00000000 .4byte 0 + 3197 0054 00000000 .4byte 0 + 3198 .section .debug_ranges,"",%progbits + 3199 .Ldebug_ranges0: + 3200 0000 0E000000 .4byte .LBB27 + 3201 0004 42000000 .4byte .LBE27 + 3202 0008 46000000 .4byte .LBB54 + 3203 000c B2000000 .4byte .LBE54 + 3204 0010 BC000000 .4byte .LBB55 + 3205 0014 C4000000 .4byte .LBE55 + 3206 0018 00000000 .4byte 0 + 3207 001c 00000000 .4byte 0 + 3208 0020 26000000 .4byte .LBB28 + 3209 0024 36000000 .4byte .LBE28 + 3210 0028 38000000 .4byte .LBB31 + 3211 002c 40000000 .4byte .LBE31 + 3212 0030 00000000 .4byte 0 + 3213 0034 00000000 .4byte 0 + 3214 0038 26000000 .4byte .LBB29 + 3215 003c 36000000 .4byte .LBE29 + 3216 0040 38000000 .4byte .LBB30 + 3217 0044 40000000 .4byte .LBE30 + 3218 0048 00000000 .4byte 0 + 3219 004c 00000000 .4byte 0 + 3220 0050 4A000000 .4byte .LBB32 + 3221 0054 50000000 .4byte .LBE32 + 3222 0058 52000000 .4byte .LBB35 + 3223 005c 56000000 .4byte .LBE35 + 3224 0060 00000000 .4byte 0 + 3225 0064 00000000 .4byte 0 + 3226 0068 5C000000 .4byte .LBB36 + 3227 006c 60000000 .4byte .LBE36 + 3228 0070 62000000 .4byte .LBB40 + 3229 0074 66000000 .4byte .LBE40 + 3230 0078 68000000 .4byte .LBB41 + 3231 007c 6A000000 .4byte .LBE41 + 3232 0080 00000000 .4byte 0 + 3233 0084 00000000 .4byte 0 + 3234 0088 82000000 .4byte .LBB44 + 3235 008c 86000000 .4byte .LBE44 + 3236 0090 88000000 .4byte .LBB48 + 3237 0094 8C000000 .4byte .LBE48 + 3238 0098 8E000000 .4byte .LBB49 + 3239 009c 90000000 .4byte .LBE49 + 3240 00a0 00000000 .4byte 0 + 3241 00a4 00000000 .4byte 0 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 58 + + + 3242 00a8 90000000 .4byte .LBB50 + 3243 00ac A6000000 .4byte .LBE50 + 3244 00b0 BC000000 .4byte .LBB53 + 3245 00b4 C4000000 .4byte .LBE53 + 3246 00b8 00000000 .4byte 0 + 3247 00bc 00000000 .4byte 0 + 3248 00c0 90000000 .4byte .LBB51 + 3249 00c4 A6000000 .4byte .LBE51 + 3250 00c8 BC000000 .4byte .LBB52 + 3251 00cc C4000000 .4byte .LBE52 + 3252 00d0 00000000 .4byte 0 + 3253 00d4 00000000 .4byte 0 + 3254 00d8 04000000 .4byte .LBB56 + 3255 00dc 0A000000 .4byte .LBE56 + 3256 00e0 0E000000 .4byte .LBB59 + 3257 00e4 1C000000 .4byte .LBE59 + 3258 00e8 00000000 .4byte 0 + 3259 00ec 00000000 .4byte 0 + 3260 00f0 2C000000 .4byte .LBB61 + 3261 00f4 2E000000 .4byte .LBE61 + 3262 00f8 32000000 .4byte .LBB65 + 3263 00fc 34000000 .4byte .LBE65 + 3264 0100 36000000 .4byte .LBB66 + 3265 0104 38000000 .4byte .LBE66 + 3266 0108 00000000 .4byte 0 + 3267 010c 00000000 .4byte 0 + 3268 0110 2C000000 .4byte .LBB62 + 3269 0114 2E000000 .4byte .LBE62 + 3270 0118 32000000 .4byte .LBB63 + 3271 011c 34000000 .4byte .LBE63 + 3272 0120 36000000 .4byte .LBB64 + 3273 0124 38000000 .4byte .LBE64 + 3274 0128 00000000 .4byte 0 + 3275 012c 00000000 .4byte 0 + 3276 0130 2A000000 .4byte .LBB68 + 3277 0134 2C000000 .4byte .LBE68 + 3278 0138 30000000 .4byte .LBB72 + 3279 013c 32000000 .4byte .LBE72 + 3280 0140 34000000 .4byte .LBB73 + 3281 0144 36000000 .4byte .LBE73 + 3282 0148 00000000 .4byte 0 + 3283 014c 00000000 .4byte 0 + 3284 0150 2A000000 .4byte .LBB69 + 3285 0154 2C000000 .4byte .LBE69 + 3286 0158 30000000 .4byte .LBB70 + 3287 015c 32000000 .4byte .LBE70 + 3288 0160 34000000 .4byte .LBB71 + 3289 0164 36000000 .4byte .LBE71 + 3290 0168 00000000 .4byte 0 + 3291 016c 00000000 .4byte 0 + 3292 0170 16000000 .4byte .LBB75 + 3293 0174 18000000 .4byte .LBE75 + 3294 0178 1E000000 .4byte .LBB80 + 3295 017c 30000000 .4byte .LBE80 + 3296 0180 00000000 .4byte 0 + 3297 0184 00000000 .4byte 0 + 3298 0188 1E000000 .4byte .LBB76 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 59 + + + 3299 018c 20000000 .4byte .LBE76 + 3300 0190 22000000 .4byte .LBB79 + 3301 0194 26000000 .4byte .LBE79 + 3302 0198 00000000 .4byte 0 + 3303 019c 00000000 .4byte 0 + 3304 01a0 1E000000 .4byte .LBB77 + 3305 01a4 20000000 .4byte .LBE77 + 3306 01a8 22000000 .4byte .LBB78 + 3307 01ac 26000000 .4byte .LBE78 + 3308 01b0 00000000 .4byte 0 + 3309 01b4 00000000 .4byte 0 + 3310 01b8 00000000 .4byte .LFB7 + 3311 01bc 0A000000 .4byte .LFE7 + 3312 01c0 00000000 .4byte .LFB9 + 3313 01c4 C4000000 .4byte .LFE9 + 3314 01c8 00000000 .4byte .LFB8 + 3315 01cc 0C000000 .4byte .LFE8 + 3316 01d0 00000000 .4byte .LFB10 + 3317 01d4 24000000 .4byte .LFE10 + 3318 01d8 00000000 .4byte .LFB11 + 3319 01dc 20000000 .4byte .LFE11 + 3320 01e0 00000000 .4byte .LFB12 + 3321 01e4 54000000 .4byte .LFE12 + 3322 01e8 00000000 .4byte .LFB13 + 3323 01ec 50000000 .4byte .LFE13 + 3324 01f0 00000000 .4byte .LFB14 + 3325 01f4 48000000 .4byte .LFE14 + 3326 01f8 00000000 .4byte 0 + 3327 01fc 00000000 .4byte 0 + 3328 .section .debug_line,"",%progbits + 3329 .Ldebug_line0: + 3330 0000 12030000 .section .debug_str,"MS",%progbits,1 + 3330 02000401 + 3330 00000201 + 3330 FB0E0D00 + 3330 01010101 + 3331 .LASF35: + 3332 0000 705F6D73 .ascii "p_msg\000" + 3332 6700 + 3333 .LASF58: + 3334 0006 7264796D .ascii "rdymsg\000" + 3334 736700 + 3335 .LASF11: + 3336 000d 6C6F6E67 .ascii "long long unsigned int\000" + 3336 206C6F6E + 3336 6720756E + 3336 7369676E + 3336 65642069 + 3337 .LASF59: + 3338 0024 65786974 .ascii "exitcode\000" + 3338 636F6465 + 3338 00 + 3339 .LASF69: + 3340 002d 63684D74 .ascii "chMtxUnlock\000" + 3340 78556E6C + 3340 6F636B00 + 3341 .LASF24: + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 60 + + + 3342 0039 705F7072 .ascii "p_prio\000" + 3342 696F00 + 3343 .LASF10: + 3344 0040 6C6F6E67 .ascii "long long int\000" + 3344 206C6F6E + 3344 6720696E + 3344 7400 + 3345 .LASF1: + 3346 004e 7369676E .ascii "signed char\000" + 3346 65642063 + 3346 68617200 + 3347 .LASF39: + 3348 005a 705F6D70 .ascii "p_mpool\000" + 3348 6F6F6C00 + 3349 .LASF12: + 3350 0062 626F6F6C .ascii "bool_t\000" + 3350 5F7400 + 3351 .LASF55: + 3352 0069 6D5F7175 .ascii "m_queue\000" + 3352 65756500 + 3353 .LASF7: + 3354 0071 6C6F6E67 .ascii "long int\000" + 3354 20696E74 + 3354 00 + 3355 .LASF14: + 3356 007a 74737461 .ascii "tstate_t\000" + 3356 74655F74 + 3356 00 + 3357 .LASF66: + 3358 0083 63684D74 .ascii "chMtxLockS\000" + 3358 784C6F63 + 3358 6B5300 + 3359 .LASF73: + 3360 008e 63684D74 .ascii "chMtxTryLockS\000" + 3360 78547279 + 3360 4C6F636B + 3360 5300 + 3361 .LASF26: + 3362 009c 705F6E65 .ascii "p_newer\000" + 3362 77657200 + 3363 .LASF82: + 3364 00a4 63685363 .ascii "chSchRescheduleS\000" + 3364 68526573 + 3364 63686564 + 3364 756C6553 + 3364 00 + 3365 .LASF49: + 3366 00b5 725F6E65 .ascii "r_newer\000" + 3366 77657200 + 3367 .LASF42: + 3368 00bd 72656761 .ascii "regarm_t\000" + 3368 726D5F74 + 3368 00 + 3369 .LASF20: + 3370 00c6 636E745F .ascii "cnt_t\000" + 3370 7400 + 3371 .LASF71: + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 61 + + + 3372 00cc 63684D74 .ascii "chMtxUnlockS\000" + 3372 78556E6C + 3372 6F636B53 + 3372 00 + 3373 .LASF0: + 3374 00d9 756E7369 .ascii "unsigned int\000" + 3374 676E6564 + 3374 20696E74 + 3374 00 + 3375 .LASF9: + 3376 00e6 6C6F6E67 .ascii "long unsigned int\000" + 3376 20756E73 + 3376 69676E65 + 3376 6420696E + 3376 7400 + 3377 .LASF44: + 3378 00f8 636F6E74 .ascii "context\000" + 3378 65787400 + 3379 .LASF4: + 3380 0100 73686F72 .ascii "short unsigned int\000" + 3380 7420756E + 3380 7369676E + 3380 65642069 + 3380 6E7400 + 3381 .LASF17: + 3382 0113 6D73675F .ascii "msg_t\000" + 3382 7400 + 3383 .LASF80: + 3384 0119 7072696F .ascii "prio_insert\000" + 3384 5F696E73 + 3384 65727400 + 3385 .LASF72: + 3386 0125 63684D74 .ascii "chMtxUnlockAll\000" + 3386 78556E6C + 3386 6F636B41 + 3386 6C6C00 + 3387 .LASF70: + 3388 0134 6E657770 .ascii "newprio\000" + 3388 72696F00 + 3389 .LASF13: + 3390 013c 746D6F64 .ascii "tmode_t\000" + 3390 655F7400 + 3391 .LASF41: + 3392 0144 54687265 .ascii "ThreadsList\000" + 3392 6164734C + 3392 69737400 + 3393 .LASF18: + 3394 0150 6576656E .ascii "eventmask_t\000" + 3394 746D6173 + 3394 6B5F7400 + 3395 .LASF68: + 3396 015c 63684D74 .ascii "chMtxTryLock\000" + 3396 78547279 + 3396 4C6F636B + 3396 00 + 3397 .LASF54: + 3398 0169 4D757465 .ascii "Mutex\000" + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 62 + + + 3398 7800 + 3399 .LASF45: + 3400 016f 73697A65 .ascii "sizetype\000" + 3400 74797065 + 3400 00 + 3401 .LASF67: + 3402 0178 63684D74 .ascii "chMtxLock\000" + 3402 784C6F63 + 3402 6B00 + 3403 .LASF27: + 3404 0182 705F6F6C .ascii "p_older\000" + 3404 64657200 + 3405 .LASF79: + 3406 018a 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 3406 73657273 + 3406 5C496D61 + 3406 6E6F6C5C + 3406 64657665 + 3407 01b7 6C696361 .ascii "lications\\smartcities\000" + 3407 74696F6E + 3407 735C736D + 3407 61727463 + 3407 69746965 + 3408 .LASF40: + 3409 01cd 54687265 .ascii "ThreadsQueue\000" + 3409 61647351 + 3409 75657565 + 3409 00 + 3410 .LASF63: + 3411 01da 64657175 .ascii "dequeue\000" + 3411 65756500 + 3412 .LASF77: + 3413 01e2 474E5520 .ascii "GNU C 4.7.2\000" + 3413 4320342E + 3413 372E3200 + 3414 .LASF52: + 3415 01ee 725F6375 .ascii "r_current\000" + 3415 7272656E + 3415 7400 + 3416 .LASF50: + 3417 01f8 725F6F6C .ascii "r_older\000" + 3417 64657200 + 3418 .LASF15: + 3419 0200 74726566 .ascii "trefs_t\000" + 3419 735F7400 + 3420 .LASF23: + 3421 0208 705F7072 .ascii "p_prev\000" + 3421 657600 + 3422 .LASF16: + 3423 020f 74707269 .ascii "tprio_t\000" + 3423 6F5F7400 + 3424 .LASF6: + 3425 0217 696E7433 .ascii "int32_t\000" + 3425 325F7400 + 3426 .LASF2: + 3427 021f 756E7369 .ascii "unsigned char\000" + 3427 676E6564 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 63 + + + 3427 20636861 + 3427 7200 + 3428 .LASF37: + 3429 022d 705F6D74 .ascii "p_mtxlist\000" + 3429 786C6973 + 3429 7400 + 3430 .LASF3: + 3431 0237 73686F72 .ascii "short int\000" + 3431 7420696E + 3431 7400 + 3432 .LASF29: + 3433 0241 705F7374 .ascii "p_state\000" + 3433 61746500 + 3434 .LASF47: + 3435 0249 725F7072 .ascii "r_prio\000" + 3435 696F00 + 3436 .LASF61: + 3437 0250 65776D61 .ascii "ewmask\000" + 3437 736B00 + 3438 .LASF22: + 3439 0257 705F6E65 .ascii "p_next\000" + 3439 787400 + 3440 .LASF30: + 3441 025e 705F666C .ascii "p_flags\000" + 3441 61677300 + 3442 .LASF21: + 3443 0266 54687265 .ascii "Thread\000" + 3443 616400 + 3444 .LASF75: + 3445 026d 63685363 .ascii "chSchGoSleepS\000" + 3445 68476F53 + 3445 6C656570 + 3445 5300 + 3446 .LASF36: + 3447 027b 705F6570 .ascii "p_epending\000" + 3447 656E6469 + 3447 6E6700 + 3448 .LASF8: + 3449 0286 75696E74 .ascii "uint32_t\000" + 3449 33325F74 + 3449 00 + 3450 .LASF46: + 3451 028f 725F7175 .ascii "r_queue\000" + 3451 65756500 + 3452 .LASF74: + 3453 0297 63685363 .ascii "chSchReadyI\000" + 3453 68526561 + 3453 64794900 + 3454 .LASF62: + 3455 02a3 63686172 .ascii "char\000" + 3455 00 + 3456 .LASF64: + 3457 02a8 6669666F .ascii "fifo_remove\000" + 3457 5F72656D + 3457 6F766500 + 3458 .LASF57: + 3459 02b4 6D5F6E65 .ascii "m_next\000" + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 64 + + + 3459 787400 + 3460 .LASF19: + 3461 02bb 73797374 .ascii "systime_t\000" + 3461 696D655F + 3461 7400 + 3462 .LASF38: + 3463 02c5 705F7265 .ascii "p_realprio\000" + 3463 616C7072 + 3463 696F00 + 3464 .LASF32: + 3465 02d0 705F7469 .ascii "p_time\000" + 3465 6D6500 + 3466 .LASF48: + 3467 02d7 725F6374 .ascii "r_ctx\000" + 3467 7800 + 3468 .LASF43: + 3469 02dd 696E7463 .ascii "intctx\000" + 3469 747800 + 3470 .LASF34: + 3471 02e4 705F6D73 .ascii "p_msgqueue\000" + 3471 67717565 + 3471 756500 + 3472 .LASF76: + 3473 02ef 63685363 .ascii "chSchWakeupS\000" + 3473 6857616B + 3473 65757053 + 3473 00 + 3474 .LASF65: + 3475 02fc 63684D74 .ascii "chMtxInit\000" + 3475 78496E69 + 3475 7400 + 3476 .LASF31: + 3477 0306 705F7265 .ascii "p_refs\000" + 3477 667300 + 3478 .LASF53: + 3479 030d 52656164 .ascii "ReadyList\000" + 3479 794C6973 + 3479 7400 + 3480 .LASF81: + 3481 0317 726C6973 .ascii "rlist\000" + 3481 7400 + 3482 .LASF5: + 3483 031d 75696E74 .ascii "uint8_t\000" + 3483 385F7400 + 3484 .LASF60: + 3485 0325 77746F62 .ascii "wtobjp\000" + 3485 6A7000 + 3486 .LASF28: + 3487 032c 705F6E61 .ascii "p_name\000" + 3487 6D6500 + 3488 .LASF51: + 3489 0333 725F7072 .ascii "r_preempt\000" + 3489 65656D70 + 3489 7400 + 3490 .LASF56: + 3491 033d 6D5F6F77 .ascii "m_owner\000" + 3491 6E657200 + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 65 + + + 3492 .LASF25: + 3493 0345 705F6374 .ascii "p_ctx\000" + 3493 7800 + 3494 .LASF33: + 3495 034b 705F7761 .ascii "p_waiting\000" + 3495 6974696E + 3495 6700 + 3496 .LASF78: + 3497 0355 2E2E2F2E .ascii "../..//os/kernel/src/chmtx.c\000" + 3497 2E2F2F6F + 3497 732F6B65 + 3497 726E656C + 3497 2F737263 + 3498 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\cci4eaLJ.s page 66 + + +DEFINED SYMBOLS + *ABS*:00000000 chmtx.c +C:\cygwin\tmp\cci4eaLJ.s:19 .text.chMtxInit:00000000 $t +C:\cygwin\tmp\cci4eaLJ.s:25 .text.chMtxInit:00000000 chMtxInit +C:\cygwin\tmp\cci4eaLJ.s:46 .text.chMtxLockS:00000000 $t +C:\cygwin\tmp\cci4eaLJ.s:52 .text.chMtxLockS:00000000 chMtxLockS +C:\cygwin\tmp\cci4eaLJ.s:310 .text.chMtxLockS:000000c0 $d +C:\cygwin\tmp\cci4eaLJ.s:318 .text.chMtxLock:00000000 $t +C:\cygwin\tmp\cci4eaLJ.s:324 .text.chMtxLock:00000000 chMtxLock +C:\cygwin\tmp\cci4eaLJ.s:354 .text.chMtxTryLock:00000000 $t +C:\cygwin\tmp\cci4eaLJ.s:360 .text.chMtxTryLock:00000000 chMtxTryLock +C:\cygwin\tmp\cci4eaLJ.s:423 .text.chMtxTryLock:00000020 $d +C:\cygwin\tmp\cci4eaLJ.s:428 .text.chMtxTryLockS:00000000 $t +C:\cygwin\tmp\cci4eaLJ.s:434 .text.chMtxTryLockS:00000000 chMtxTryLockS +C:\cygwin\tmp\cci4eaLJ.s:475 .text.chMtxTryLockS:0000001c $d +C:\cygwin\tmp\cci4eaLJ.s:480 .text.chMtxUnlock:00000000 $t +C:\cygwin\tmp\cci4eaLJ.s:486 .text.chMtxUnlock:00000000 chMtxUnlock +C:\cygwin\tmp\cci4eaLJ.s:604 .text.chMtxUnlock:00000050 $d +C:\cygwin\tmp\cci4eaLJ.s:609 .text.chMtxUnlockS:00000000 $t +C:\cygwin\tmp\cci4eaLJ.s:615 .text.chMtxUnlockS:00000000 chMtxUnlockS +C:\cygwin\tmp\cci4eaLJ.s:722 .text.chMtxUnlockS:0000004c $d +C:\cygwin\tmp\cci4eaLJ.s:727 .text.chMtxUnlockAll:00000000 $t +C:\cygwin\tmp\cci4eaLJ.s:733 .text.chMtxUnlockAll:00000000 chMtxUnlockAll +C:\cygwin\tmp\cci4eaLJ.s:831 .text.chMtxUnlockAll:00000044 $d + .debug_frame:00000010 $d +C:\cygwin\tmp\cci4eaLJ.s:317 .text.chMtxLockS:000000c4 $t +C:\cygwin\tmp\cci4eaLJ.s:427 .text.chMtxTryLock:00000024 $t +C:\cygwin\tmp\cci4eaLJ.s:608 .text.chMtxUnlock:00000054 $t +C:\cygwin\tmp\cci4eaLJ.s:835 .text.chMtxUnlockAll:00000048 $t + +UNDEFINED SYMBOLS +chSchGoSleepS +chSchReadyI +rlist +chSchWakeupS +chSchRescheduleS diff --git a/Project/applications/smartcities/build/lst/chqueues.lst b/Project/applications/smartcities/build/lst/chqueues.lst new file mode 100644 index 0000000..34cefe0 --- /dev/null +++ b/Project/applications/smartcities/build/lst/chqueues.lst @@ -0,0 +1,4485 @@ +ARM GAS C:\cygwin\tmp\cchfGMii.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "chqueues.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text.qwait,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .thumb + 22 .thumb_func + 23 .type qwait, %function + 24 qwait: + 25 .LFB7: + 26 .file 1 "../..//os/kernel/src/chqueues.c" + 27 .loc 1 72 0 + 28 .cfi_startproc + 29 @ args = 0, pretend = 0, frame = 0 + 30 @ frame_needed = 0, uses_anonymous_args = 0 + 31 @ link register save eliminated. + 32 .LVL0: + 33 0000 10B4 push {r4} + 34 .LCFI0: + 35 .cfi_def_cfa_offset 4 + 36 .cfi_offset 4, -4 + 37 .loc 1 72 0 + 38 0002 0246 mov r2, r0 + 39 .loc 1 74 0 + 40 0004 59B1 cbz r1, .L2 + 41 .loc 1 76 0 + 42 0006 084B ldr r3, .L4 + 43 .loc 1 78 0 + 44 0008 0D20 movs r0, #13 + 45 .LVL1: + 46 .loc 1 76 0 + 47 000a DB69 ldr r3, [r3, #28] + 48 000c 5A62 str r2, [r3, #36] + 49 .LVL2: + 50 .LBB12: + 51 .LBB13: + 52 .file 2 "../..//os/kernel/include/chinline.h" + 53 .loc 2 55 0 + 54 000e 5468 ldr r4, [r2, #4] + 55 0010 83E81400 stmia r3, {r2, r4} + 56 .loc 2 56 0 + 57 0014 5360 str r3, [r2, #4] + ARM GAS C:\cygwin\tmp\cchfGMii.s page 2 + + + 58 0016 2360 str r3, [r4, #0] + 59 .LBE13: + 60 .LBE12: + 61 .loc 1 79 0 + 62 0018 10BC pop {r4} + 63 .loc 1 78 0 + 64 001a FFF7FEBF b chSchGoSleepTimeoutS + 65 .LVL3: + 66 .L2: + 67 .loc 1 79 0 + 68 001e 4FF0FF30 mov r0, #-1 + 69 .LVL4: + 70 0022 10BC pop {r4} + 71 0024 7047 bx lr + 72 .L5: + 73 0026 00BF .align 2 + 74 .L4: + 75 0028 00000000 .word rlist + 76 .cfi_endproc + 77 .LFE7: + 78 .size qwait, .-qwait + 79 002c AFF30080 .section .text.chIQInit,"ax",%progbits + 80 .align 2 + 81 .p2align 4,,15 + 82 .global chIQInit + 83 .thumb + 84 .thumb_func + 85 .type chIQInit, %function + 86 chIQInit: + 87 .LFB8: + 88 .loc 1 96 0 + 89 .cfi_startproc + 90 @ args = 0, pretend = 0, frame = 0 + 91 @ frame_needed = 0, uses_anonymous_args = 0 + 92 @ link register save eliminated. + 93 .LVL5: + 94 0000 10B4 push {r4} + 95 .LCFI1: + 96 .cfi_def_cfa_offset 4 + 97 .cfi_offset 4, -4 + 98 .loc 1 101 0 + 99 0002 8A18 adds r2, r1, r2 + 100 .LVL6: + 101 .loc 1 99 0 + 102 0004 0024 movs r4, #0 + 103 .loc 1 98 0 + 104 0006 4060 str r0, [r0, #4] + 105 0008 0060 str r0, [r0, #0] + 106 .loc 1 99 0 + 107 000a 8460 str r4, [r0, #8] + 108 .loc 1 100 0 + 109 000c 4161 str r1, [r0, #20] + 110 000e 8161 str r1, [r0, #24] + 111 0010 C160 str r1, [r0, #12] + 112 .loc 1 101 0 + 113 0012 0261 str r2, [r0, #16] + 114 .loc 1 102 0 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 3 + + + 115 0014 C361 str r3, [r0, #28] + 116 .loc 1 103 0 + 117 0016 10BC pop {r4} + 118 0018 7047 bx lr + 119 .cfi_endproc + 120 .LFE8: + 121 .size chIQInit, .-chIQInit + 122 .section .text.chIQResetI,"ax",%progbits + 123 .align 2 + 124 .p2align 4,,15 + 125 .global chIQResetI + 126 .thumb + 127 .thumb_func + 128 .type chIQResetI, %function + 129 chIQResetI: + 130 .LFB9: + 131 .loc 1 116 0 + 132 .cfi_startproc + 133 @ args = 0, pretend = 0, frame = 0 + 134 @ frame_needed = 0, uses_anonymous_args = 0 + 135 .LVL7: + 136 0000 38B5 push {r3, r4, r5, lr} + 137 .LCFI2: + 138 .cfi_def_cfa_offset 16 + 139 .cfi_offset 3, -16 + 140 .cfi_offset 4, -12 + 141 .cfi_offset 5, -8 + 142 .cfi_offset 14, -4 + 143 .loc 1 116 0 + 144 0002 0446 mov r4, r0 + 145 .loc 1 120 0 + 146 0004 C368 ldr r3, [r0, #12] + 147 .loc 1 122 0 + 148 0006 0068 ldr r0, [r0, #0] + 149 .LVL8: + 150 .loc 1 120 0 + 151 0008 6361 str r3, [r4, #20] + 152 000a A361 str r3, [r4, #24] + 153 .loc 1 121 0 + 154 000c 0023 movs r3, #0 + 155 .loc 1 122 0 + 156 000e A042 cmp r0, r4 + 157 .loc 1 121 0 + 158 0010 A360 str r3, [r4, #8] + 159 .loc 1 122 0 + 160 0012 0AD0 beq .L7 + 161 .loc 1 123 0 + 162 0014 6FF00105 mvn r5, #1 + 163 .L11: + 164 .LVL9: + 165 .LBB14: + 166 .LBB15: + 167 .loc 2 62 0 + 168 0018 0368 ldr r3, [r0, #0] + 169 001a 2360 str r3, [r4, #0] + 170 001c 5C60 str r4, [r3, #4] + 171 .LBE15: + ARM GAS C:\cygwin\tmp\cchfGMii.s page 4 + + + 172 .LBE14: + 173 .loc 1 123 0 + 174 001e FFF7FEFF bl chSchReadyI + 175 .LVL10: + 176 0022 4562 str r5, [r0, #36] + 177 .loc 1 122 0 + 178 0024 2068 ldr r0, [r4, #0] + 179 0026 A042 cmp r0, r4 + 180 0028 F6D1 bne .L11 + 181 .LVL11: + 182 .L7: + 183 002a 38BD pop {r3, r4, r5, pc} + 184 .cfi_endproc + 185 .LFE9: + 186 .size chIQResetI, .-chIQResetI + 187 002c AFF30080 .section .text.chIQPutI,"ax",%progbits + 188 .align 2 + 189 .p2align 4,,15 + 190 .global chIQPutI + 191 .thumb + 192 .thumb_func + 193 .type chIQPutI, %function + 194 chIQPutI: + 195 .LFB10: + 196 .loc 1 139 0 + 197 .cfi_startproc + 198 @ args = 0, pretend = 0, frame = 0 + 199 @ frame_needed = 0, uses_anonymous_args = 0 + 200 .LVL12: + 201 .loc 1 143 0 + 202 0000 4269 ldr r2, [r0, #20] + 203 .loc 1 139 0 + 204 0002 08B5 push {r3, lr} + 205 .LCFI3: + 206 .cfi_def_cfa_offset 8 + 207 .cfi_offset 3, -8 + 208 .cfi_offset 14, -4 + 209 .loc 1 139 0 + 210 0004 0346 mov r3, r0 + 211 .loc 1 143 0 + 212 0006 8069 ldr r0, [r0, #24] + 213 .LVL13: + 214 0008 8242 cmp r2, r0 + 215 000a 9868 ldr r0, [r3, #8] + 216 000c 18D0 beq .L14 + 217 .L15: + 218 .loc 1 146 0 + 219 000e 0130 adds r0, r0, #1 + 220 0010 9860 str r0, [r3, #8] + 221 .loc 1 147 0 + 222 0012 02F8011B strb r1, [r2], #1 + 223 .loc 1 148 0 + 224 0016 1969 ldr r1, [r3, #16] + 225 .LVL14: + 226 .loc 1 147 0 + 227 0018 5A61 str r2, [r3, #20] + 228 .loc 1 148 0 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 5 + + + 229 001a 8A42 cmp r2, r1 + 230 .loc 1 149 0 + 231 001c 28BF it cs + 232 001e DA68 ldrcs r2, [r3, #12] + 233 .loc 1 151 0 + 234 0020 1868 ldr r0, [r3, #0] + 235 .loc 1 149 0 + 236 0022 28BF it cs + 237 0024 5A61 strcs r2, [r3, #20] + 238 .loc 1 151 0 + 239 0026 9842 cmp r0, r3 + 240 0028 08D0 beq .L19 + 241 .LVL15: + 242 .LBB16: + 243 .LBB17: + 244 .loc 2 62 0 + 245 002a 0268 ldr r2, [r0, #0] + 246 002c 1A60 str r2, [r3, #0] + 247 002e 5360 str r3, [r2, #4] + 248 .LBE17: + 249 .LBE16: + 250 .loc 1 152 0 + 251 0030 FFF7FEFF bl chSchReadyI + 252 .LVL16: + 253 0034 0023 movs r3, #0 + 254 0036 4362 str r3, [r0, #36] + 255 .loc 1 154 0 + 256 0038 1846 mov r0, r3 + 257 003a 08BD pop {r3, pc} + 258 .LVL17: + 259 .L19: + 260 003c 0020 movs r0, #0 + 261 .loc 1 155 0 + 262 003e 08BD pop {r3, pc} + 263 .LVL18: + 264 .L14: + 265 .loc 1 143 0 discriminator 1 + 266 0040 0028 cmp r0, #0 + 267 0042 E4D0 beq .L15 + 268 .loc 1 144 0 + 269 0044 6FF00300 mvn r0, #3 + 270 0048 08BD pop {r3, pc} + 271 .cfi_endproc + 272 .LFE10: + 273 .size chIQPutI, .-chIQPutI + 274 004a 00BFAFF3 .section .text.chIQGetTimeout,"ax",%progbits + 274 0080 + 275 .align 2 + 276 .p2align 4,,15 + 277 .global chIQGetTimeout + 278 .thumb + 279 .thumb_func + 280 .type chIQGetTimeout, %function + 281 chIQGetTimeout: + 282 .LFB11: + 283 .loc 1 177 0 + 284 .cfi_startproc + ARM GAS C:\cygwin\tmp\cchfGMii.s page 6 + + + 285 @ args = 0, pretend = 0, frame = 0 + 286 @ frame_needed = 0, uses_anonymous_args = 0 + 287 .LVL19: + 288 0000 38B5 push {r3, r4, r5, lr} + 289 .LCFI4: + 290 .cfi_def_cfa_offset 16 + 291 .cfi_offset 3, -16 + 292 .cfi_offset 4, -12 + 293 .cfi_offset 5, -8 + 294 .cfi_offset 14, -4 + 295 .loc 1 177 0 + 296 0002 0446 mov r4, r0 + 297 0004 0D46 mov r5, r1 + 298 .loc 1 180 0 + 299 @ 180 "../..//os/kernel/src/chqueues.c" 1 + 300 0006 72B6 cpsid i + 301 @ 0 "" 2 + 302 .loc 1 181 0 + 303 .thumb + 304 0008 C369 ldr r3, [r0, #28] + 305 000a 03B1 cbz r3, .L28 + 306 .loc 1 182 0 + 307 000c 9847 blx r3 + 308 .LVL20: + 309 .L28: + 310 .loc 1 184 0 discriminator 1 + 311 000e A368 ldr r3, [r4, #8] + 312 .LBB18: + 313 .loc 1 186 0 discriminator 1 + 314 0010 2046 mov r0, r4 + 315 0012 2946 mov r1, r5 + 316 .LBE18: + 317 .loc 1 184 0 discriminator 1 + 318 0014 2BB9 cbnz r3, .L31 + 319 .LVL21: + 320 .LBB19: + 321 .loc 1 186 0 + 322 0016 FFF7FEFF bl qwait + 323 .LVL22: + 324 001a 0028 cmp r0, #0 + 325 001c F7DA bge .L28 + 326 .LBE19: + 327 .loc 1 197 0 + 328 @ 197 "../..//os/kernel/src/chqueues.c" 1 + 329 001e 62B6 cpsie i + 330 @ 0 "" 2 + 331 .loc 1 199 0 + 332 .thumb + 333 0020 38BD pop {r3, r4, r5, pc} + 334 .LVL23: + 335 .L31: + 336 .loc 1 193 0 + 337 0022 A269 ldr r2, [r4, #24] + 338 .loc 1 192 0 + 339 0024 013B subs r3, r3, #1 + 340 0026 A360 str r3, [r4, #8] + 341 .loc 1 193 0 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 7 + + + 342 0028 12F8010B ldrb r0, [r2], #1 @ zero_extendqisi2 + 343 .LVL24: + 344 .loc 1 194 0 + 345 002c 2369 ldr r3, [r4, #16] + 346 .loc 1 193 0 + 347 002e A261 str r2, [r4, #24] + 348 .loc 1 194 0 + 349 0030 9A42 cmp r2, r3 + 350 .loc 1 195 0 + 351 0032 24BF itt cs + 352 0034 E368 ldrcs r3, [r4, #12] + 353 0036 A361 strcs r3, [r4, #24] + 354 .loc 1 197 0 + 355 @ 197 "../..//os/kernel/src/chqueues.c" 1 + 356 0038 62B6 cpsie i + 357 @ 0 "" 2 + 358 .loc 1 199 0 + 359 .thumb + 360 003a 38BD pop {r3, r4, r5, pc} + 361 .cfi_endproc + 362 .LFE11: + 363 .size chIQGetTimeout, .-chIQGetTimeout + 364 .section .text.chIQReadTimeout,"ax",%progbits + 365 .align 2 + 366 .p2align 4,,15 + 367 .global chIQReadTimeout + 368 .thumb + 369 .thumb_func + 370 .type chIQReadTimeout, %function + 371 chIQReadTimeout: + 372 .LFB12: + 373 .loc 1 226 0 + 374 .cfi_startproc + 375 @ args = 0, pretend = 0, frame = 0 + 376 @ frame_needed = 0, uses_anonymous_args = 0 + 377 .LVL25: + 378 0000 2DE9F047 push {r4, r5, r6, r7, r8, r9, sl, lr} + 379 .LCFI5: + 380 .cfi_def_cfa_offset 32 + 381 .cfi_offset 4, -32 + 382 .cfi_offset 5, -28 + 383 .cfi_offset 6, -24 + 384 .cfi_offset 7, -20 + 385 .cfi_offset 8, -16 + 386 .cfi_offset 9, -12 + 387 .cfi_offset 10, -8 + 388 .cfi_offset 14, -4 + 389 .loc 1 226 0 + 390 0004 0446 mov r4, r0 + 391 0006 1E46 mov r6, r3 + 392 .loc 1 227 0 + 393 0008 C769 ldr r7, [r0, #28] + 394 .LVL26: + 395 .loc 1 232 0 + 396 @ 232 "../..//os/kernel/src/chqueues.c" 1 + 397 000a 72B6 cpsid i + 398 @ 0 "" 2 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 8 + + + 399 .loc 1 228 0 + 400 .thumb + 401 000c 4FF00008 mov r8, #0 + 402 .loc 1 225 0 + 403 0010 01F10109 add r9, r1, #1 + 404 0014 01EB020A add sl, r1, r2 + 405 .LVL27: + 406 .L38: + 407 .loc 1 234 0 + 408 0018 0FB1 cbz r7, .L43 + 409 .loc 1 235 0 + 410 001a 2046 mov r0, r4 + 411 .LVL28: + 412 001c B847 blx r7 + 413 .LVL29: + 414 .L43: + 415 .loc 1 237 0 discriminator 1 + 416 001e A568 ldr r5, [r4, #8] + 417 .loc 1 238 0 discriminator 1 + 418 0020 2046 mov r0, r4 + 419 0022 3146 mov r1, r6 + 420 .loc 1 237 0 discriminator 1 + 421 0024 3DB9 cbnz r5, .L47 + 422 .LVL30: + 423 .loc 1 238 0 + 424 0026 FFF7FEFF bl qwait + 425 .LVL31: + 426 002a 0028 cmp r0, #0 + 427 002c F7D0 beq .L43 + 428 .loc 1 239 0 + 429 @ 239 "../..//os/kernel/src/chqueues.c" 1 + 430 002e 62B6 cpsie i + 431 @ 0 "" 2 + 432 .thumb + 433 .L35: + 434 .loc 1 256 0 + 435 0030 4046 mov r0, r8 + 436 0032 BDE8F087 pop {r4, r5, r6, r7, r8, r9, sl, pc} + 437 .LVL32: + 438 .L47: + 439 .loc 1 245 0 + 440 0036 A369 ldr r3, [r4, #24] + 441 .loc 1 244 0 + 442 0038 013D subs r5, r5, #1 + 443 003a A560 str r5, [r4, #8] + 444 .loc 1 245 0 + 445 003c 13F8012B ldrb r2, [r3], #1 @ zero_extendqisi2 + 446 0040 09F8012C strb r2, [r9, #-1] + 447 .loc 1 246 0 + 448 0044 2269 ldr r2, [r4, #16] + 449 .loc 1 245 0 + 450 0046 A361 str r3, [r4, #24] + 451 .loc 1 246 0 + 452 0048 9342 cmp r3, r2 + 453 .loc 1 247 0 + 454 004a 24BF itt cs + 455 004c E368 ldrcs r3, [r4, #12] + ARM GAS C:\cygwin\tmp\cchfGMii.s page 9 + + + 456 004e A361 strcs r3, [r4, #24] + 457 .loc 1 249 0 + 458 @ 249 "../..//os/kernel/src/chqueues.c" 1 + 459 0050 62B6 cpsie i + 460 @ 0 "" 2 + 461 .loc 1 251 0 + 462 .thumb + 463 0052 D145 cmp r9, sl + 464 .loc 1 250 0 + 465 0054 08F10108 add r8, r8, #1 + 466 .LVL33: + 467 .loc 1 251 0 + 468 0058 EAD0 beq .L35 + 469 .loc 1 254 0 + 470 @ 254 "../..//os/kernel/src/chqueues.c" 1 + 471 005a 72B6 cpsid i + 472 @ 0 "" 2 + 473 .thumb + 474 005c 09F10109 add r9, r9, #1 + 475 .loc 1 255 0 + 476 0060 DAE7 b .L38 + 477 .cfi_endproc + 478 .LFE12: + 479 .size chIQReadTimeout, .-chIQReadTimeout + 480 0062 00BFAFF3 .section .text.chOQInit,"ax",%progbits + 480 0080AFF3 + 480 0080AFF3 + 480 0080 + 481 .align 2 + 482 .p2align 4,,15 + 483 .global chOQInit + 484 .thumb + 485 .thumb_func + 486 .type chOQInit, %function + 487 chOQInit: + 488 .LFB13: + 489 .loc 1 273 0 + 490 .cfi_startproc + 491 @ args = 0, pretend = 0, frame = 0 + 492 @ frame_needed = 0, uses_anonymous_args = 0 + 493 @ link register save eliminated. + 494 .LVL34: + 495 0000 10B4 push {r4} + 496 .LCFI6: + 497 .cfi_def_cfa_offset 4 + 498 .cfi_offset 4, -4 + 499 .loc 1 278 0 + 500 0002 8C18 adds r4, r1, r2 + 501 .loc 1 275 0 + 502 0004 4060 str r0, [r0, #4] + 503 0006 0060 str r0, [r0, #0] + 504 .loc 1 276 0 + 505 0008 8260 str r2, [r0, #8] + 506 .loc 1 277 0 + 507 000a 4161 str r1, [r0, #20] + 508 000c 8161 str r1, [r0, #24] + 509 000e C160 str r1, [r0, #12] + ARM GAS C:\cygwin\tmp\cchfGMii.s page 10 + + + 510 .loc 1 278 0 + 511 0010 0461 str r4, [r0, #16] + 512 .loc 1 279 0 + 513 0012 C361 str r3, [r0, #28] + 514 .loc 1 280 0 + 515 0014 10BC pop {r4} + 516 0016 7047 bx lr + 517 .cfi_endproc + 518 .LFE13: + 519 .size chOQInit, .-chOQInit + 520 0018 AFF30080 .section .text.chOQResetI,"ax",%progbits + 520 AFF30080 + 521 .align 2 + 522 .p2align 4,,15 + 523 .global chOQResetI + 524 .thumb + 525 .thumb_func + 526 .type chOQResetI, %function + 527 chOQResetI: + 528 .LFB14: + 529 .loc 1 293 0 + 530 .cfi_startproc + 531 @ args = 0, pretend = 0, frame = 0 + 532 @ frame_needed = 0, uses_anonymous_args = 0 + 533 .LVL35: + 534 0000 38B5 push {r3, r4, r5, lr} + 535 .LCFI7: + 536 .cfi_def_cfa_offset 16 + 537 .cfi_offset 3, -16 + 538 .cfi_offset 4, -12 + 539 .cfi_offset 5, -8 + 540 .cfi_offset 14, -4 + 541 .loc 1 298 0 + 542 0002 0269 ldr r2, [r0, #16] + 543 .loc 1 293 0 + 544 0004 0446 mov r4, r0 + 545 .loc 1 297 0 + 546 0006 C368 ldr r3, [r0, #12] + 547 .loc 1 299 0 + 548 0008 0068 ldr r0, [r0, #0] + 549 .LVL36: + 550 .loc 1 298 0 + 551 000a D21A subs r2, r2, r3 + 552 .loc 1 299 0 + 553 000c A042 cmp r0, r4 + 554 .loc 1 297 0 + 555 000e 6361 str r3, [r4, #20] + 556 0010 A361 str r3, [r4, #24] + 557 .loc 1 298 0 + 558 0012 A260 str r2, [r4, #8] + 559 .loc 1 299 0 + 560 0014 0AD0 beq .L49 + 561 .loc 1 300 0 + 562 0016 6FF00105 mvn r5, #1 + 563 .L53: + 564 .LVL37: + 565 .LBB20: + ARM GAS C:\cygwin\tmp\cchfGMii.s page 11 + + + 566 .LBB21: + 567 .loc 2 62 0 + 568 001a 0368 ldr r3, [r0, #0] + 569 001c 2360 str r3, [r4, #0] + 570 001e 5C60 str r4, [r3, #4] + 571 .LBE21: + 572 .LBE20: + 573 .loc 1 300 0 + 574 0020 FFF7FEFF bl chSchReadyI + 575 .LVL38: + 576 0024 4562 str r5, [r0, #36] + 577 .loc 1 299 0 + 578 0026 2068 ldr r0, [r4, #0] + 579 0028 A042 cmp r0, r4 + 580 002a F6D1 bne .L53 + 581 .LVL39: + 582 .L49: + 583 002c 38BD pop {r3, r4, r5, pc} + 584 .cfi_endproc + 585 .LFE14: + 586 .size chOQResetI, .-chOQResetI + 587 002e 00BF .section .text.chOQPutTimeout,"ax",%progbits + 588 .align 2 + 589 .p2align 4,,15 + 590 .global chOQPutTimeout + 591 .thumb + 592 .thumb_func + 593 .type chOQPutTimeout, %function + 594 chOQPutTimeout: + 595 .LFB15: + 596 .loc 1 325 0 + 597 .cfi_startproc + 598 @ args = 0, pretend = 0, frame = 0 + 599 @ frame_needed = 0, uses_anonymous_args = 0 + 600 .LVL40: + 601 0000 70B5 push {r4, r5, r6, lr} + 602 .LCFI8: + 603 .cfi_def_cfa_offset 16 + 604 .cfi_offset 4, -16 + 605 .cfi_offset 5, -12 + 606 .cfi_offset 6, -8 + 607 .cfi_offset 14, -4 + 608 .loc 1 325 0 + 609 0002 0446 mov r4, r0 + 610 0004 0E46 mov r6, r1 + 611 0006 1546 mov r5, r2 + 612 .loc 1 327 0 + 613 @ 327 "../..//os/kernel/src/chqueues.c" 1 + 614 0008 72B6 cpsid i + 615 @ 0 "" 2 + 616 .LVL41: + 617 .thumb + 618 .L56: + 619 .loc 1 328 0 discriminator 1 + 620 000a A368 ldr r3, [r4, #8] + 621 .LBB22: + 622 .loc 1 331 0 discriminator 1 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 12 + + + 623 000c 2046 mov r0, r4 + 624 000e 2946 mov r1, r5 + 625 .LBE22: + 626 .loc 1 328 0 discriminator 1 + 627 0010 2BB9 cbnz r3, .L65 + 628 .LVL42: + 629 .LBB23: + 630 .loc 1 331 0 + 631 0012 FFF7FEFF bl qwait + 632 .LVL43: + 633 0016 0028 cmp r0, #0 + 634 0018 F7DA bge .L56 + 635 .loc 1 332 0 + 636 @ 332 "../..//os/kernel/src/chqueues.c" 1 + 637 001a 62B6 cpsie i + 638 @ 0 "" 2 + 639 .loc 1 333 0 + 640 .thumb + 641 001c 70BD pop {r4, r5, r6, pc} + 642 .LVL44: + 643 .L65: + 644 .LBE23: + 645 .loc 1 338 0 + 646 001e 6269 ldr r2, [r4, #20] + 647 .loc 1 337 0 + 648 0020 013B subs r3, r3, #1 + 649 0022 A360 str r3, [r4, #8] + 650 .loc 1 338 0 + 651 0024 02F8016B strb r6, [r2], #1 + 652 .loc 1 339 0 + 653 0028 2369 ldr r3, [r4, #16] + 654 .loc 1 338 0 + 655 002a 6261 str r2, [r4, #20] + 656 .loc 1 339 0 + 657 002c 9A42 cmp r2, r3 + 658 .loc 1 340 0 + 659 002e 24BF itt cs + 660 0030 E368 ldrcs r3, [r4, #12] + 661 0032 6361 strcs r3, [r4, #20] + 662 .loc 1 342 0 + 663 0034 E369 ldr r3, [r4, #28] + 664 0036 0BB1 cbz r3, .L60 + 665 .loc 1 343 0 + 666 0038 2046 mov r0, r4 + 667 .LVL45: + 668 003a 9847 blx r3 + 669 .LVL46: + 670 .L60: + 671 .loc 1 345 0 + 672 @ 345 "../..//os/kernel/src/chqueues.c" 1 + 673 003c 62B6 cpsie i + 674 @ 0 "" 2 + 675 .loc 1 346 0 + 676 .thumb + 677 003e 0020 movs r0, #0 + 678 .loc 1 347 0 + 679 0040 70BD pop {r4, r5, r6, pc} + ARM GAS C:\cygwin\tmp\cchfGMii.s page 13 + + + 680 .cfi_endproc + 681 .LFE15: + 682 .size chOQPutTimeout, .-chOQPutTimeout + 683 0042 00BFAFF3 .section .text.chOQGetI,"ax",%progbits + 683 0080AFF3 + 683 0080AFF3 + 683 0080 + 684 .align 2 + 685 .p2align 4,,15 + 686 .global chOQGetI + 687 .thumb + 688 .thumb_func + 689 .type chOQGetI, %function + 690 chOQGetI: + 691 .LFB16: + 692 .loc 1 359 0 + 693 .cfi_startproc + 694 @ args = 0, pretend = 0, frame = 0 + 695 @ frame_needed = 0, uses_anonymous_args = 0 + 696 .LVL47: + 697 .loc 1 364 0 + 698 0000 4169 ldr r1, [r0, #20] + 699 0002 8269 ldr r2, [r0, #24] + 700 .loc 1 359 0 + 701 0004 10B5 push {r4, lr} + 702 .LCFI9: + 703 .cfi_def_cfa_offset 8 + 704 .cfi_offset 4, -8 + 705 .cfi_offset 14, -4 + 706 .loc 1 364 0 + 707 0006 9142 cmp r1, r2 + 708 .loc 1 359 0 + 709 0008 0346 mov r3, r0 + 710 .loc 1 364 0 + 711 000a 8168 ldr r1, [r0, #8] + 712 000c 16D0 beq .L67 + 713 .L68: + 714 .loc 1 367 0 + 715 000e 0131 adds r1, r1, #1 + 716 0010 9960 str r1, [r3, #8] + 717 .loc 1 368 0 + 718 0012 12F8014B ldrb r4, [r2], #1 @ zero_extendqisi2 + 719 .LVL48: + 720 .loc 1 369 0 + 721 0016 1969 ldr r1, [r3, #16] + 722 .loc 1 368 0 + 723 0018 9A61 str r2, [r3, #24] + 724 .loc 1 369 0 + 725 001a 8A42 cmp r2, r1 + 726 .loc 1 370 0 + 727 001c 28BF it cs + 728 001e DA68 ldrcs r2, [r3, #12] + 729 .loc 1 372 0 + 730 0020 1868 ldr r0, [r3, #0] + 731 .LVL49: + 732 .loc 1 370 0 + 733 0022 28BF it cs + ARM GAS C:\cygwin\tmp\cchfGMii.s page 14 + + + 734 0024 9A61 strcs r2, [r3, #24] + 735 .loc 1 372 0 + 736 0026 9842 cmp r0, r3 + 737 0028 06D0 beq .L71 + 738 .LVL50: + 739 .LBB24: + 740 .LBB25: + 741 .loc 2 62 0 + 742 002a 0268 ldr r2, [r0, #0] + 743 002c 1A60 str r2, [r3, #0] + 744 002e 5360 str r3, [r2, #4] + 745 .LBE25: + 746 .LBE24: + 747 .loc 1 373 0 + 748 0030 FFF7FEFF bl chSchReadyI + 749 .LVL51: + 750 0034 0023 movs r3, #0 + 751 0036 4362 str r3, [r0, #36] + 752 .LVL52: + 753 .L71: + 754 .loc 1 375 0 + 755 0038 2046 mov r0, r4 + 756 003a 10BD pop {r4, pc} + 757 .LVL53: + 758 .L67: + 759 .loc 1 364 0 discriminator 1 + 760 003c 0029 cmp r1, #0 + 761 003e E6D0 beq .L68 + 762 .loc 1 365 0 + 763 0040 6FF00200 mvn r0, #2 + 764 .LVL54: + 765 .loc 1 376 0 + 766 0044 10BD pop {r4, pc} + 767 .cfi_endproc + 768 .LFE16: + 769 .size chOQGetI, .-chOQGetI + 770 0046 00BFAFF3 .section .text.chOQWriteTimeout,"ax",%progbits + 770 0080AFF3 + 770 0080 + 771 .align 2 + 772 .p2align 4,,15 + 773 .global chOQWriteTimeout + 774 .thumb + 775 .thumb_func + 776 .type chOQWriteTimeout, %function + 777 chOQWriteTimeout: + 778 .LFB17: + 779 .loc 1 403 0 + 780 .cfi_startproc + 781 @ args = 0, pretend = 0, frame = 0 + 782 @ frame_needed = 0, uses_anonymous_args = 0 + 783 .LVL55: + 784 0000 2DE9F047 push {r4, r5, r6, r7, r8, r9, sl, lr} + 785 .LCFI10: + 786 .cfi_def_cfa_offset 32 + 787 .cfi_offset 4, -32 + 788 .cfi_offset 5, -28 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 15 + + + 789 .cfi_offset 6, -24 + 790 .cfi_offset 7, -20 + 791 .cfi_offset 8, -16 + 792 .cfi_offset 9, -12 + 793 .cfi_offset 10, -8 + 794 .cfi_offset 14, -4 + 795 .loc 1 403 0 + 796 0004 0446 mov r4, r0 + 797 0006 8846 mov r8, r1 + 798 0008 1646 mov r6, r2 + 799 000a 9A46 mov sl, r3 + 800 .loc 1 404 0 + 801 000c D0F81C90 ldr r9, [r0, #28] + 802 .LVL56: + 803 .loc 1 409 0 + 804 @ 409 "../..//os/kernel/src/chqueues.c" 1 + 805 0010 72B6 cpsid i + 806 @ 0 "" 2 + 807 .loc 1 405 0 + 808 .thumb + 809 0012 0027 movs r7, #0 + 810 .LVL57: + 811 .L91: + 812 .loc 1 411 0 discriminator 1 + 813 0014 A568 ldr r5, [r4, #8] + 814 .loc 1 423 0 discriminator 1 + 815 0016 2046 mov r0, r4 + 816 .loc 1 417 0 discriminator 1 + 817 0018 6B1E subs r3, r5, #1 + 818 .loc 1 411 0 discriminator 1 + 819 001a CDB1 cbz r5, .L77 + 820 .LVL58: + 821 .L92: + 822 .loc 1 417 0 + 823 001c A360 str r3, [r4, #8] + 824 .loc 1 418 0 + 825 001e 18F8013B ldrb r3, [r8], #1 @ zero_extendqisi2 + 826 .LVL59: + 827 0022 6569 ldr r5, [r4, #20] + 828 0024 05F8013B strb r3, [r5], #1 + 829 .loc 1 419 0 + 830 0028 2369 ldr r3, [r4, #16] + 831 .loc 1 418 0 + 832 002a 6561 str r5, [r4, #20] + 833 .LVL60: + 834 .loc 1 419 0 + 835 002c 9D42 cmp r5, r3 + 836 .loc 1 420 0 + 837 002e 24BF itt cs + 838 0030 E368 ldrcs r3, [r4, #12] + 839 0032 6361 strcs r3, [r4, #20] + 840 .loc 1 422 0 + 841 0034 B9F1000F cmp r9, #0 + 842 0038 00D0 beq .L79 + 843 .loc 1 423 0 + 844 003a C847 blx r9 + 845 .LVL61: + ARM GAS C:\cygwin\tmp\cchfGMii.s page 16 + + + 846 .L79: + 847 .loc 1 425 0 + 848 @ 425 "../..//os/kernel/src/chqueues.c" 1 + 849 003c 62B6 cpsie i + 850 @ 0 "" 2 + 851 .loc 1 426 0 + 852 .thumb + 853 003e 0137 adds r7, r7, #1 + 854 .LVL62: + 855 .loc 1 427 0 + 856 0040 013E subs r6, r6, #1 + 857 .LVL63: + 858 0042 0CD0 beq .L76 + 859 .loc 1 429 0 + 860 @ 429 "../..//os/kernel/src/chqueues.c" 1 + 861 0044 72B6 cpsid i + 862 @ 0 "" 2 + 863 .loc 1 411 0 + 864 .thumb + 865 0046 A568 ldr r5, [r4, #8] + 866 .loc 1 423 0 + 867 0048 2046 mov r0, r4 + 868 .loc 1 417 0 + 869 004a 6B1E subs r3, r5, #1 + 870 .loc 1 411 0 + 871 004c 002D cmp r5, #0 + 872 004e E5D1 bne .L92 + 873 .LVL64: + 874 .L77: + 875 .loc 1 412 0 + 876 0050 2046 mov r0, r4 + 877 .LVL65: + 878 0052 5146 mov r1, sl + 879 0054 FFF7FEFF bl qwait + 880 .LVL66: + 881 0058 0028 cmp r0, #0 + 882 005a DBD0 beq .L91 + 883 .loc 1 413 0 + 884 @ 413 "../..//os/kernel/src/chqueues.c" 1 + 885 005c 62B6 cpsie i + 886 @ 0 "" 2 + 887 .thumb + 888 .L76: + 889 .loc 1 431 0 + 890 005e 3846 mov r0, r7 + 891 0060 BDE8F087 pop {r4, r5, r6, r7, r8, r9, sl, pc} + 892 .cfi_endproc + 893 .LFE17: + 894 .size chOQWriteTimeout, .-chOQWriteTimeout + 895 0064 AFF30080 .text + 895 AFF30080 + 895 AFF30080 + 896 .Letext0: + 897 .file 3 "c:\\yagarto\\bin\\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h" + 898 .file 4 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 899 .file 5 "../..//os/ports/GCC/ARMCMx/chtypes.h" + 900 .file 6 "../..//os/kernel/include/chlists.h" + ARM GAS C:\cygwin\tmp\cchfGMii.s page 17 + + + 901 .file 7 "../..//os/kernel/include/chthreads.h" + 902 .file 8 "../..//os/ports/GCC/ARMCMx/chcore_v7m.h" + 903 .file 9 "../..//os/kernel/include/chschd.h" + 904 .file 10 "../..//os/kernel/include/chmtx.h" + 905 .file 11 "../..//os/kernel/include/chqueues.h" + 906 .section .debug_info,"",%progbits + 907 .Ldebug_info0: + 908 0000 AD0A0000 .4byte 0xaad + 909 0004 0200 .2byte 0x2 + 910 0006 00000000 .4byte .Ldebug_abbrev0 + 911 000a 04 .byte 0x4 + 912 000b 01 .uleb128 0x1 + 913 000c 2E020000 .4byte .LASF89 + 914 0010 01 .byte 0x1 + 915 0011 09030000 .4byte .LASF90 + 916 0015 D9010000 .4byte .LASF91 + 917 0019 30000000 .4byte .Ldebug_ranges0+0x30 + 918 001d 00000000 .4byte 0 + 919 0021 00000000 .4byte 0 + 920 0025 00000000 .4byte .Ldebug_line0 + 921 0029 02 .uleb128 0x2 + 922 002a 04 .byte 0x4 + 923 002b 05 .byte 0x5 + 924 002c 696E7400 .ascii "int\000" + 925 0030 03 .uleb128 0x3 + 926 0031 21000000 .4byte .LASF2 + 927 0035 03 .byte 0x3 + 928 0036 D5 .byte 0xd5 + 929 0037 3B000000 .4byte 0x3b + 930 003b 04 .uleb128 0x4 + 931 003c 04 .byte 0x4 + 932 003d 07 .byte 0x7 + 933 003e 1F010000 .4byte .LASF0 + 934 0042 04 .uleb128 0x4 + 935 0043 01 .byte 0x1 + 936 0044 06 .byte 0x6 + 937 0045 93000000 .4byte .LASF1 + 938 0049 03 .uleb128 0x3 + 939 004a 95030000 .4byte .LASF3 + 940 004e 04 .byte 0x4 + 941 004f 2A .byte 0x2a + 942 0050 54000000 .4byte 0x54 + 943 0054 04 .uleb128 0x4 + 944 0055 01 .byte 0x1 + 945 0056 08 .byte 0x8 + 946 0057 7D020000 .4byte .LASF4 + 947 005b 04 .uleb128 0x4 + 948 005c 02 .byte 0x2 + 949 005d 05 .byte 0x5 + 950 005e 95020000 .4byte .LASF5 + 951 0062 04 .uleb128 0x4 + 952 0063 02 .byte 0x2 + 953 0064 07 .byte 0x7 + 954 0065 56010000 .4byte .LASF6 + 955 0069 03 .uleb128 0x3 + 956 006a 75020000 .4byte .LASF7 + 957 006e 04 .byte 0x4 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 18 + + + 958 006f 4F .byte 0x4f + 959 0070 74000000 .4byte 0x74 + 960 0074 04 .uleb128 0x4 + 961 0075 04 .byte 0x4 + 962 0076 05 .byte 0x5 + 963 0077 BC000000 .4byte .LASF8 + 964 007b 03 .uleb128 0x3 + 965 007c DB020000 .4byte .LASF9 + 966 0080 04 .byte 0x4 + 967 0081 50 .byte 0x50 + 968 0082 86000000 .4byte 0x86 + 969 0086 04 .uleb128 0x4 + 970 0087 04 .byte 0x4 + 971 0088 07 .byte 0x7 + 972 0089 37010000 .4byte .LASF10 + 973 008d 04 .uleb128 0x4 + 974 008e 08 .byte 0x8 + 975 008f 05 .byte 0x5 + 976 0090 85000000 .4byte .LASF11 + 977 0094 04 .uleb128 0x4 + 978 0095 08 .byte 0x8 + 979 0096 07 .byte 0x7 + 980 0097 54000000 .4byte .LASF12 + 981 009b 03 .uleb128 0x3 + 982 009c A7000000 .4byte .LASF13 + 983 00a0 05 .byte 0x5 + 984 00a1 2E .byte 0x2e + 985 00a2 69000000 .4byte 0x69 + 986 00a6 03 .uleb128 0x3 + 987 00a7 6F010000 .4byte .LASF14 + 988 00ab 05 .byte 0x5 + 989 00ac 2F .byte 0x2f + 990 00ad 49000000 .4byte 0x49 + 991 00b1 03 .uleb128 0x3 + 992 00b2 C5000000 .4byte .LASF15 + 993 00b6 05 .byte 0x5 + 994 00b7 30 .byte 0x30 + 995 00b8 49000000 .4byte 0x49 + 996 00bc 03 .uleb128 0x3 + 997 00bd 4C020000 .4byte .LASF16 + 998 00c1 05 .byte 0x5 + 999 00c2 31 .byte 0x31 + 1000 00c3 49000000 .4byte 0x49 + 1001 00c7 03 .uleb128 0x3 + 1002 00c8 65020000 .4byte .LASF17 + 1003 00cc 05 .byte 0x5 + 1004 00cd 32 .byte 0x32 + 1005 00ce 7B000000 .4byte 0x7b + 1006 00d2 03 .uleb128 0x3 + 1007 00d3 69010000 .4byte .LASF18 + 1008 00d7 05 .byte 0x5 + 1009 00d8 33 .byte 0x33 + 1010 00d9 69000000 .4byte 0x69 + 1011 00dd 03 .uleb128 0x3 + 1012 00de 83010000 .4byte .LASF19 + 1013 00e2 05 .byte 0x5 + 1014 00e3 35 .byte 0x35 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 19 + + + 1015 00e4 7B000000 .4byte 0x7b + 1016 00e8 03 .uleb128 0x3 + 1017 00e9 30030000 .4byte .LASF20 + 1018 00ed 05 .byte 0x5 + 1019 00ee 36 .byte 0x36 + 1020 00ef 7B000000 .4byte 0x7b + 1021 00f3 03 .uleb128 0x3 + 1022 00f4 19010000 .4byte .LASF21 + 1023 00f8 05 .byte 0x5 + 1024 00f9 37 .byte 0x37 + 1025 00fa 69000000 .4byte 0x69 + 1026 00fe 03 .uleb128 0x3 + 1027 00ff C9020000 .4byte .LASF22 + 1028 0103 06 .byte 0x6 + 1029 0104 2A .byte 0x2a + 1030 0105 09010000 .4byte 0x109 + 1031 0109 05 .uleb128 0x5 + 1032 010a C9020000 .4byte .LASF22 + 1033 010e 48 .byte 0x48 + 1034 010f 07 .byte 0x7 + 1035 0110 5E .byte 0x5e + 1036 0111 20020000 .4byte 0x220 + 1037 0115 06 .uleb128 0x6 + 1038 0116 B5020000 .4byte .LASF23 + 1039 011a 07 .byte 0x7 + 1040 011b 5F .byte 0x5f + 1041 011c 45020000 .4byte 0x245 + 1042 0120 02 .byte 0x2 + 1043 0121 23 .byte 0x23 + 1044 0122 00 .uleb128 0 + 1045 0123 06 .uleb128 0x6 + 1046 0124 5E020000 .4byte .LASF24 + 1047 0128 07 .byte 0x7 + 1048 0129 61 .byte 0x61 + 1049 012a 45020000 .4byte 0x245 + 1050 012e 02 .byte 0x2 + 1051 012f 23 .byte 0x23 + 1052 0130 04 .uleb128 0x4 + 1053 0131 06 .uleb128 0x6 + 1054 0132 74000000 .4byte .LASF25 + 1055 0136 07 .byte 0x7 + 1056 0137 63 .byte 0x63 + 1057 0138 C7000000 .4byte 0xc7 + 1058 013c 02 .byte 0x2 + 1059 013d 23 .byte 0x23 + 1060 013e 08 .uleb128 0x8 + 1061 013f 06 .uleb128 0x6 + 1062 0140 D2030000 .4byte .LASF26 + 1063 0144 07 .byte 0x7 + 1064 0145 64 .byte 0x64 + 1065 0146 12030000 .4byte 0x312 + 1066 014a 02 .byte 0x2 + 1067 014b 23 .byte 0x23 + 1068 014c 0C .uleb128 0xc + 1069 014d 06 .uleb128 0x6 + 1070 014e E8000000 .4byte .LASF27 + 1071 0152 07 .byte 0x7 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 20 + + + 1072 0153 66 .byte 0x66 + 1073 0154 45020000 .4byte 0x245 + 1074 0158 02 .byte 0x2 + 1075 0159 23 .byte 0x23 + 1076 015a 10 .uleb128 0x10 + 1077 015b 06 .uleb128 0x6 + 1078 015c D1010000 .4byte .LASF28 + 1079 0160 07 .byte 0x7 + 1080 0161 67 .byte 0x67 + 1081 0162 45020000 .4byte 0x245 + 1082 0166 02 .byte 0x2 + 1083 0167 23 .byte 0x23 + 1084 0168 14 .uleb128 0x14 + 1085 0169 06 .uleb128 0x6 + 1086 016a A4030000 .4byte .LASF29 + 1087 016e 07 .byte 0x7 + 1088 016f 6E .byte 0x6e + 1089 0170 34040000 .4byte 0x434 + 1090 0174 02 .byte 0x2 + 1091 0175 23 .byte 0x23 + 1092 0176 18 .uleb128 0x18 + 1093 0177 06 .uleb128 0x6 + 1094 0178 9F020000 .4byte .LASF30 + 1095 017c 07 .byte 0x7 + 1096 017d 79 .byte 0x79 + 1097 017e B1000000 .4byte 0xb1 + 1098 0182 02 .byte 0x2 + 1099 0183 23 .byte 0x23 + 1100 0184 1C .uleb128 0x1c + 1101 0185 06 .uleb128 0x6 + 1102 0186 C1020000 .4byte .LASF31 + 1103 018a 07 .byte 0x7 + 1104 018b 7D .byte 0x7d + 1105 018c A6000000 .4byte 0xa6 + 1106 0190 02 .byte 0x2 + 1107 0191 23 .byte 0x23 + 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.uleb128 0x9 + 1615 0534 04 .byte 0x4 + 1616 0535 4B020000 .4byte 0x24b + 1617 0539 15 .uleb128 0x15 + 1618 053a FD020000 .4byte .LASF93 + 1619 053e 02 .byte 0x2 + 1620 053f 3B .byte 0x3b + 1621 0540 01 .byte 0x1 + 1622 0541 45020000 .4byte 0x245 + 1623 0545 03 .byte 0x3 + 1624 0546 60050000 .4byte 0x560 + 1625 054a 14 .uleb128 0x14 + 1626 054b 74717000 .ascii "tqp\000" + 1627 054f 02 .byte 0x2 + 1628 0550 3B .byte 0x3b + 1629 0551 33050000 .4byte 0x533 + 1630 0555 16 .uleb128 0x16 + 1631 0556 747000 .ascii "tp\000" + 1632 0559 02 .byte 0x2 + 1633 055a 3C .byte 0x3c + 1634 055b 45020000 .4byte 0x245 + 1635 055f 00 .byte 0 + 1636 0560 17 .uleb128 0x17 + 1637 0561 B6000000 .4byte .LASF94 + 1638 0565 01 .byte 0x1 + 1639 0566 48 .byte 0x48 + 1640 0567 01 .byte 0x1 + 1641 0568 D2000000 .4byte 0xd2 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 30 + + + 1642 056c 00000000 .4byte .LFB7 + 1643 0570 2C000000 .4byte .LFE7 + 1644 0574 00000000 .4byte .LLST0 + 1645 0578 01 .byte 0x1 + 1646 0579 D8050000 .4byte 0x5d8 + 1647 057d 18 .uleb128 0x18 + 1648 057e 717000 .ascii "qp\000" + 1649 0581 01 .byte 0x1 + 1650 0582 48 .byte 0x48 + 1651 0583 E3040000 .4byte 0x4e3 + 1652 0587 20000000 .4byte .LLST1 + 1653 058b 19 .uleb128 0x19 + 1654 058c 29020000 .4byte .LASF75 + 1655 0590 01 .byte 0x1 + 1656 0591 48 .byte 0x48 + 1657 0592 E8000000 .4byte 0xe8 + 1658 0596 62000000 .4byte .LLST2 + 1659 059a 1A .uleb128 0x1a + 1660 059b 10050000 .4byte 0x510 + 1661 059f 0E000000 .4byte .LBB12 + 1662 05a3 18000000 .4byte .LBE12 + 1663 05a7 01 .byte 0x1 + 1664 05a8 4D .byte 0x4d + 1665 05a9 C0050000 .4byte 0x5c0 + 1666 05ad 1B .uleb128 0x1b + 1667 05ae 27050000 .4byte 0x527 + 1668 05b2 8E000000 .4byte .LLST3 + 1669 05b6 1B .uleb128 0x1b + 1670 05b7 1D050000 .4byte 0x51d + 1671 05bb AF000000 .4byte .LLST4 + 1672 05bf 00 .byte 0 + 1673 05c0 1C .uleb128 0x1c + 1674 05c1 1E000000 .4byte .LVL3 + 1675 05c5 01 .byte 0x1 + 1676 05c6 7F0A0000 .4byte 0xa7f + 1677 05ca 1D .uleb128 0x1d + 1678 05cb 01 .byte 0x1 + 1679 05cc 51 .byte 0x51 + 1680 05cd 03 .byte 0x3 + 1681 05ce F3 .byte 0xf3 + 1682 05cf 01 .uleb128 0x1 + 1683 05d0 51 .byte 0x51 + 1684 05d1 1D .uleb128 0x1d + 1685 05d2 01 .byte 0x1 + 1686 05d3 50 .byte 0x50 + 1687 05d4 01 .byte 0x1 + 1688 05d5 3D .byte 0x3d + 1689 05d6 00 .byte 0 + 1690 05d7 00 .byte 0 + 1691 05d8 1E .uleb128 0x1e + 1692 05d9 01 .byte 0x1 + 1693 05da 2F000000 .4byte .LASF78 + 1694 05de 01 .byte 0x1 + 1695 05df 60 .byte 0x60 + 1696 05e0 01 .byte 0x1 + 1697 05e1 00000000 .4byte .LFB8 + 1698 05e5 1A000000 .4byte .LFE8 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 31 + + + 1699 05e9 C2000000 .4byte .LLST5 + 1700 05ed 01 .byte 0x1 + 1701 05ee 28060000 .4byte 0x628 + 1702 05f2 1F .uleb128 0x1f + 1703 05f3 69717000 .ascii "iqp\000" + 1704 05f7 01 .byte 0x1 + 1705 05f8 60 .byte 0x60 + 1706 05f9 28060000 .4byte 0x628 + 1707 05fd 01 .byte 0x1 + 1708 05fe 50 .byte 0x50 + 1709 05ff 1F .uleb128 0x1f + 1710 0600 627000 .ascii "bp\000" + 1711 0603 01 .byte 0x1 + 1712 0604 60 .byte 0x60 + 1713 0605 E9040000 .4byte 0x4e9 + 1714 0609 01 .byte 0x1 + 1715 060a 51 .byte 0x51 + 1716 060b 19 .uleb128 0x19 + 1717 060c 51010000 .4byte .LASF76 + 1718 0610 01 .byte 0x1 + 1719 0611 60 .byte 0x60 + 1720 0612 30000000 .4byte 0x30 + 1721 0616 E2000000 .4byte .LLST6 + 1722 061a 20 .uleb128 0x20 + 1723 061b BC020000 .4byte .LASF77 + 1724 061f 01 .byte 0x1 + 1725 0620 60 .byte 0x60 + 1726 0621 C6040000 .4byte 0x4c6 + 1727 0625 01 .byte 0x1 + 1728 0626 53 .byte 0x53 + 1729 0627 00 .byte 0 + 1730 0628 09 .uleb128 0x9 + 1731 0629 04 .byte 0x4 + 1732 062a EF040000 .4byte 0x4ef + 1733 062e 1E .uleb128 0x1e + 1734 062f 01 .byte 0x1 + 1735 0630 2C010000 .4byte .LASF79 + 1736 0634 01 .byte 0x1 + 1737 0635 74 .byte 0x74 + 1738 0636 01 .byte 0x1 + 1739 0637 00000000 .4byte .LFB9 + 1740 063b 2C000000 .4byte .LFE9 + 1741 063f 03010000 .4byte .LLST7 + 1742 0643 01 .byte 0x1 + 1743 0644 91060000 .4byte 0x691 + 1744 0648 18 .uleb128 0x18 + 1745 0649 69717000 .ascii "iqp\000" + 1746 064d 01 .byte 0x1 + 1747 064e 74 .byte 0x74 + 1748 064f 28060000 .4byte 0x628 + 1749 0653 23010000 .4byte .LLST8 + 1750 0657 1A .uleb128 0x1a + 1751 0658 39050000 .4byte 0x539 + 1752 065c 18000000 .4byte .LBB14 + 1753 0660 1E000000 .4byte .LBE14 + 1754 0664 01 .byte 0x1 + 1755 0665 7B .byte 0x7b + ARM GAS C:\cygwin\tmp\cchfGMii.s page 32 + + + 1756 0666 87060000 .4byte 0x687 + 1757 066a 1B .uleb128 0x1b + 1758 066b 4A050000 .4byte 0x54a + 1759 066f 41010000 .4byte .LLST9 + 1760 0673 21 .uleb128 0x21 + 1761 0674 18000000 .4byte .LBB15 + 1762 0678 1E000000 .4byte .LBE15 + 1763 067c 22 .uleb128 0x22 + 1764 067d 55050000 .4byte 0x555 + 1765 0681 54010000 .4byte .LLST10 + 1766 0685 00 .byte 0 + 1767 0686 00 .byte 0 + 1768 0687 23 .uleb128 0x23 + 1769 0688 22000000 .4byte .LVL10 + 1770 068c 9C0A0000 .4byte 0xa9c + 1771 0690 00 .byte 0 + 1772 0691 24 .uleb128 0x24 + 1773 0692 01 .byte 0x1 + 1774 0693 10010000 .4byte .LASF80 + 1775 0697 01 .byte 0x1 + 1776 0698 8B .byte 0x8b + 1777 0699 01 .byte 0x1 + 1778 069a D2000000 .4byte 0xd2 + 1779 069e 00000000 .4byte .LFB10 + 1780 06a2 4A000000 .4byte .LFE10 + 1781 06a6 67010000 .4byte .LLST11 + 1782 06aa 01 .byte 0x1 + 1783 06ab 05070000 .4byte 0x705 + 1784 06af 18 .uleb128 0x18 + 1785 06b0 69717000 .ascii "iqp\000" + 1786 06b4 01 .byte 0x1 + 1787 06b5 8B .byte 0x8b + 1788 06b6 28060000 .4byte 0x628 + 1789 06ba 87010000 .4byte .LLST12 + 1790 06be 18 .uleb128 0x18 + 1791 06bf 6200 .ascii "b\000" + 1792 06c1 01 .byte 0x1 + 1793 06c2 8B .byte 0x8b + 1794 06c3 49000000 .4byte 0x49 + 1795 06c7 BE010000 .4byte .LLST13 + 1796 06cb 1A .uleb128 0x1a + 1797 06cc 39050000 .4byte 0x539 + 1798 06d0 2A000000 .4byte .LBB16 + 1799 06d4 30000000 .4byte .LBE16 + 1800 06d8 01 .byte 0x1 + 1801 06d9 98 .byte 0x98 + 1802 06da FB060000 .4byte 0x6fb + 1803 06de 1B .uleb128 0x1b + 1804 06df 4A050000 .4byte 0x54a + 1805 06e3 04020000 .4byte .LLST14 + 1806 06e7 21 .uleb128 0x21 + 1807 06e8 2A000000 .4byte .LBB17 + 1808 06ec 30000000 .4byte .LBE17 + 1809 06f0 22 .uleb128 0x22 + 1810 06f1 55050000 .4byte 0x555 + 1811 06f5 25020000 .4byte .LLST15 + 1812 06f9 00 .byte 0 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 33 + + + 1813 06fa 00 .byte 0 + 1814 06fb 23 .uleb128 0x23 + 1815 06fc 34000000 .4byte .LVL16 + 1816 0700 9C0A0000 .4byte 0xa9c + 1817 0704 00 .byte 0 + 1818 0705 24 .uleb128 0x24 + 1819 0706 01 .byte 0x1 + 1820 0707 E2030000 .4byte .LASF81 + 1821 070b 01 .byte 0x1 + 1822 070c B1 .byte 0xb1 + 1823 070d 01 .byte 0x1 + 1824 070e D2000000 .4byte 0xd2 + 1825 0712 00000000 .4byte .LFB11 + 1826 0716 3C000000 .4byte .LFE11 + 1827 071a 38020000 .4byte .LLST16 + 1828 071e 01 .byte 0x1 + 1829 071f 8A070000 .4byte 0x78a + 1830 0723 18 .uleb128 0x18 + 1831 0724 69717000 .ascii "iqp\000" + 1832 0728 01 .byte 0x1 + 1833 0729 B1 .byte 0xb1 + 1834 072a 28060000 .4byte 0x628 + 1835 072e 58020000 .4byte .LLST17 + 1836 0732 19 .uleb128 0x19 + 1837 0733 29020000 .4byte .LASF75 + 1838 0737 01 .byte 0x1 + 1839 0738 B1 .byte 0xb1 + 1840 0739 E8000000 .4byte 0xe8 + 1841 073d A2020000 .4byte .LLST18 + 1842 0741 25 .uleb128 0x25 + 1843 0742 6200 .ascii "b\000" + 1844 0744 01 .byte 0x1 + 1845 0745 B2 .byte 0xb2 + 1846 0746 49000000 .4byte 0x49 + 1847 074a 03 .byte 0x3 + 1848 074b 74 .byte 0x74 + 1849 074c 18 .sleb128 24 + 1850 074d 06 .byte 0x6 + 1851 074e 26 .uleb128 0x26 + 1852 074f 00000000 .4byte .Ldebug_ranges0+0 + 1853 0753 7D070000 .4byte 0x77d + 1854 0757 27 .uleb128 0x27 + 1855 0758 6D736700 .ascii "msg\000" + 1856 075c 01 .byte 0x1 + 1857 075d B9 .byte 0xb9 + 1858 075e D2000000 .4byte 0xd2 + 1859 0762 E1020000 .4byte .LLST19 + 1860 0766 28 .uleb128 0x28 + 1861 0767 1A000000 .4byte .LVL22 + 1862 076b 60050000 .4byte 0x560 + 1863 076f 1D .uleb128 0x1d + 1864 0770 01 .byte 0x1 + 1865 0771 51 .byte 0x51 + 1866 0772 02 .byte 0x2 + 1867 0773 75 .byte 0x75 + 1868 0774 00 .sleb128 0 + 1869 0775 1D .uleb128 0x1d + ARM GAS C:\cygwin\tmp\cchfGMii.s page 34 + + + 1870 0776 01 .byte 0x1 + 1871 0777 50 .byte 0x50 + 1872 0778 02 .byte 0x2 + 1873 0779 74 .byte 0x74 + 1874 077a 00 .sleb128 0 + 1875 077b 00 .byte 0 + 1876 077c 00 .byte 0 + 1877 077d 29 .uleb128 0x29 + 1878 077e 0E000000 .4byte .LVL20 + 1879 0782 1D .uleb128 0x1d + 1880 0783 01 .byte 0x1 + 1881 0784 50 .byte 0x50 + 1882 0785 02 .byte 0x2 + 1883 0786 74 .byte 0x74 + 1884 0787 00 .sleb128 0 + 1885 0788 00 .byte 0 + 1886 0789 00 .byte 0 + 1887 078a 24 .uleb128 0x24 + 1888 078b 01 .byte 0x1 + 1889 078c 44000000 .4byte .LASF82 + 1890 0790 01 .byte 0x1 + 1891 0791 E1 .byte 0xe1 + 1892 0792 01 .byte 0x1 + 1893 0793 30000000 .4byte 0x30 + 1894 0797 00000000 .4byte .LFB12 + 1895 079b 62000000 .4byte .LFE12 + 1896 079f F4020000 .4byte .LLST20 + 1897 07a3 01 .byte 0x1 + 1898 07a4 22080000 .4byte 0x822 + 1899 07a8 18 .uleb128 0x18 + 1900 07a9 69717000 .ascii "iqp\000" + 1901 07ad 01 .byte 0x1 + 1902 07ae E1 .byte 0xe1 + 1903 07af 28060000 .4byte 0x628 + 1904 07b3 14030000 .4byte .LLST21 + 1905 07b7 18 .uleb128 0x18 + 1906 07b8 627000 .ascii "bp\000" + 1907 07bb 01 .byte 0x1 + 1908 07bc E1 .byte 0xe1 + 1909 07bd E9040000 .4byte 0x4e9 + 1910 07c1 53030000 .4byte .LLST22 + 1911 07c5 18 .uleb128 0x18 + 1912 07c6 6E00 .ascii "n\000" + 1913 07c8 01 .byte 0x1 + 1914 07c9 E2 .byte 0xe2 + 1915 07ca 30000000 .4byte 0x30 + 1916 07ce 66030000 .4byte .LLST23 + 1917 07d2 19 .uleb128 0x19 + 1918 07d3 29020000 .4byte .LASF75 + 1919 07d7 01 .byte 0x1 + 1920 07d8 E2 .byte 0xe2 + 1921 07d9 E8000000 .4byte 0xe8 + 1922 07dd 79030000 .4byte .LLST24 + 1923 07e1 25 .uleb128 0x25 + 1924 07e2 6E667900 .ascii "nfy\000" + 1925 07e6 01 .byte 0x1 + 1926 07e7 E3 .byte 0xe3 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 35 + + + 1927 07e8 C6040000 .4byte 0x4c6 + 1928 07ec 01 .byte 0x1 + 1929 07ed 57 .byte 0x57 + 1930 07ee 27 .uleb128 0x27 + 1931 07ef 7200 .ascii "r\000" + 1932 07f1 01 .byte 0x1 + 1933 07f2 E4 .byte 0xe4 + 1934 07f3 30000000 .4byte 0x30 + 1935 07f7 B8030000 .4byte .LLST25 + 1936 07fb 2A .uleb128 0x2a + 1937 07fc 1E000000 .4byte .LVL29 + 1938 0800 0B080000 .4byte 0x80b + 1939 0804 1D .uleb128 0x1d + 1940 0805 01 .byte 0x1 + 1941 0806 50 .byte 0x50 + 1942 0807 02 .byte 0x2 + 1943 0808 74 .byte 0x74 + 1944 0809 00 .sleb128 0 + 1945 080a 00 .byte 0 + 1946 080b 28 .uleb128 0x28 + 1947 080c 2A000000 .4byte .LVL31 + 1948 0810 60050000 .4byte 0x560 + 1949 0814 1D .uleb128 0x1d + 1950 0815 01 .byte 0x1 + 1951 0816 51 .byte 0x51 + 1952 0817 02 .byte 0x2 + 1953 0818 76 .byte 0x76 + 1954 0819 00 .sleb128 0 + 1955 081a 1D .uleb128 0x1d + 1956 081b 01 .byte 0x1 + 1957 081c 50 .byte 0x50 + 1958 081d 02 .byte 0x2 + 1959 081e 74 .byte 0x74 + 1960 081f 00 .sleb128 0 + 1961 0820 00 .byte 0 + 1962 0821 00 .byte 0 + 1963 0822 2B .uleb128 0x2b + 1964 0823 01 .byte 0x1 + 1965 0824 00000000 .4byte .LASF83 + 1966 0828 01 .byte 0x1 + 1967 0829 1101 .2byte 0x111 + 1968 082b 01 .byte 0x1 + 1969 082c 00000000 .4byte .LFB13 + 1970 0830 18000000 .4byte .LFE13 + 1971 0834 D7030000 .4byte .LLST26 + 1972 0838 01 .byte 0x1 + 1973 0839 75080000 .4byte 0x875 + 1974 083d 2C .uleb128 0x2c + 1975 083e 6F717000 .ascii "oqp\000" + 1976 0842 01 .byte 0x1 + 1977 0843 1101 .2byte 0x111 + 1978 0845 75080000 .4byte 0x875 + 1979 0849 01 .byte 0x1 + 1980 084a 50 .byte 0x50 + 1981 084b 2C .uleb128 0x2c + 1982 084c 627000 .ascii "bp\000" + 1983 084f 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 36 + + + 1984 0850 1101 .2byte 0x111 + 1985 0852 E9040000 .4byte 0x4e9 + 1986 0856 01 .byte 0x1 + 1987 0857 51 .byte 0x51 + 1988 0858 2D .uleb128 0x2d + 1989 0859 51010000 .4byte .LASF76 + 1990 085d 01 .byte 0x1 + 1991 085e 1101 .2byte 0x111 + 1992 0860 30000000 .4byte 0x30 + 1993 0864 01 .byte 0x1 + 1994 0865 52 .byte 0x52 + 1995 0866 2D .uleb128 0x2d + 1996 0867 1C000000 .4byte .LASF84 + 1997 086b 01 .byte 0x1 + 1998 086c 1101 .2byte 0x111 + 1999 086e C6040000 .4byte 0x4c6 + 2000 0872 01 .byte 0x1 + 2001 0873 53 .byte 0x53 + 2002 0874 00 .byte 0 + 2003 0875 09 .uleb128 0x9 + 2004 0876 04 .byte 0x4 + 2005 0877 FA040000 .4byte 0x4fa + 2006 087b 2B .uleb128 0x2b + 2007 087c 01 .byte 0x1 + 2008 087d 45030000 .4byte .LASF85 + 2009 0881 01 .byte 0x1 + 2010 0882 2501 .2byte 0x125 + 2011 0884 01 .byte 0x1 + 2012 0885 00000000 .4byte .LFB14 + 2013 0889 2E000000 .4byte .LFE14 + 2014 088d F7030000 .4byte .LLST27 + 2015 0891 01 .byte 0x1 + 2016 0892 E1080000 .4byte 0x8e1 + 2017 0896 2E .uleb128 0x2e + 2018 0897 6F717000 .ascii "oqp\000" + 2019 089b 01 .byte 0x1 + 2020 089c 2501 .2byte 0x125 + 2021 089e 75080000 .4byte 0x875 + 2022 08a2 17040000 .4byte .LLST28 + 2023 08a6 2F .uleb128 0x2f + 2024 08a7 39050000 .4byte 0x539 + 2025 08ab 1A000000 .4byte .LBB20 + 2026 08af 20000000 .4byte .LBE20 + 2027 08b3 01 .byte 0x1 + 2028 08b4 2C01 .2byte 0x12c + 2029 08b6 D7080000 .4byte 0x8d7 + 2030 08ba 1B .uleb128 0x1b + 2031 08bb 4A050000 .4byte 0x54a + 2032 08bf 35040000 .4byte .LLST29 + 2033 08c3 21 .uleb128 0x21 + 2034 08c4 1A000000 .4byte .LBB21 + 2035 08c8 20000000 .4byte .LBE21 + 2036 08cc 22 .uleb128 0x22 + 2037 08cd 55050000 .4byte 0x555 + 2038 08d1 48040000 .4byte .LLST30 + 2039 08d5 00 .byte 0 + 2040 08d6 00 .byte 0 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 37 + + + 2041 08d7 23 .uleb128 0x23 + 2042 08d8 24000000 .4byte .LVL38 + 2043 08dc 9C0A0000 .4byte 0xa9c + 2044 08e0 00 .byte 0 + 2045 08e1 30 .uleb128 0x30 + 2046 08e2 01 .byte 0x1 + 2047 08e3 01010000 .4byte .LASF86 + 2048 08e7 01 .byte 0x1 + 2049 08e8 4501 .2byte 0x145 + 2050 08ea 01 .byte 0x1 + 2051 08eb D2000000 .4byte 0xd2 + 2052 08ef 00000000 .4byte .LFB15 + 2053 08f3 42000000 .4byte .LFE15 + 2054 08f7 5B040000 .4byte .LLST31 + 2055 08fb 01 .byte 0x1 + 2056 08fc 6B090000 .4byte 0x96b + 2057 0900 2E .uleb128 0x2e + 2058 0901 6F717000 .ascii "oqp\000" + 2059 0905 01 .byte 0x1 + 2060 0906 4501 .2byte 0x145 + 2061 0908 75080000 .4byte 0x875 + 2062 090c 7B040000 .4byte .LLST32 + 2063 0910 2E .uleb128 0x2e + 2064 0911 6200 .ascii "b\000" + 2065 0913 01 .byte 0x1 + 2066 0914 4501 .2byte 0x145 + 2067 0916 49000000 .4byte 0x49 + 2068 091a C5040000 .4byte .LLST33 + 2069 091e 31 .uleb128 0x31 + 2070 091f 29020000 .4byte .LASF75 + 2071 0923 01 .byte 0x1 + 2072 0924 4501 .2byte 0x145 + 2073 0926 E8000000 .4byte 0xe8 + 2074 092a E6040000 .4byte .LLST34 + 2075 092e 26 .uleb128 0x26 + 2076 092f 18000000 .4byte .Ldebug_ranges0+0x18 + 2077 0933 5E090000 .4byte 0x95e + 2078 0937 32 .uleb128 0x32 + 2079 0938 6D736700 .ascii "msg\000" + 2080 093c 01 .byte 0x1 + 2081 093d 4901 .2byte 0x149 + 2082 093f D2000000 .4byte 0xd2 + 2083 0943 30050000 .4byte .LLST35 + 2084 0947 28 .uleb128 0x28 + 2085 0948 16000000 .4byte .LVL43 + 2086 094c 60050000 .4byte 0x560 + 2087 0950 1D .uleb128 0x1d + 2088 0951 01 .byte 0x1 + 2089 0952 51 .byte 0x51 + 2090 0953 02 .byte 0x2 + 2091 0954 75 .byte 0x75 + 2092 0955 00 .sleb128 0 + 2093 0956 1D .uleb128 0x1d + 2094 0957 01 .byte 0x1 + 2095 0958 50 .byte 0x50 + 2096 0959 02 .byte 0x2 + 2097 095a 74 .byte 0x74 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 38 + + + 2098 095b 00 .sleb128 0 + 2099 095c 00 .byte 0 + 2100 095d 00 .byte 0 + 2101 095e 29 .uleb128 0x29 + 2102 095f 3C000000 .4byte .LVL46 + 2103 0963 1D .uleb128 0x1d + 2104 0964 01 .byte 0x1 + 2105 0965 50 .byte 0x50 + 2106 0966 02 .byte 0x2 + 2107 0967 74 .byte 0x74 + 2108 0968 00 .sleb128 0 + 2109 0969 00 .byte 0 + 2110 096a 00 .byte 0 + 2111 096b 30 .uleb128 0x30 + 2112 096c 01 .byte 0x1 + 2113 096d CE000000 .4byte .LASF87 + 2114 0971 01 .byte 0x1 + 2115 0972 6701 .2byte 0x167 + 2116 0974 01 .byte 0x1 + 2117 0975 D2000000 .4byte 0xd2 + 2118 0979 00000000 .4byte .LFB16 + 2119 097d 46000000 .4byte .LFE16 + 2120 0981 43050000 .4byte .LLST36 + 2121 0985 01 .byte 0x1 + 2122 0986 E3090000 .4byte 0x9e3 + 2123 098a 2E .uleb128 0x2e + 2124 098b 6F717000 .ascii "oqp\000" + 2125 098f 01 .byte 0x1 + 2126 0990 6701 .2byte 0x167 + 2127 0992 75080000 .4byte 0x875 + 2128 0996 63050000 .4byte .LLST37 + 2129 099a 32 .uleb128 0x32 + 2130 099b 6200 .ascii "b\000" + 2131 099d 01 .byte 0x1 + 2132 099e 6801 .2byte 0x168 + 2133 09a0 49000000 .4byte 0x49 + 2134 09a4 A5050000 .4byte .LLST38 + 2135 09a8 2F .uleb128 0x2f + 2136 09a9 39050000 .4byte 0x539 + 2137 09ad 2A000000 .4byte .LBB24 + 2138 09b1 30000000 .4byte .LBE24 + 2139 09b5 01 .byte 0x1 + 2140 09b6 7501 .2byte 0x175 + 2141 09b8 D9090000 .4byte 0x9d9 + 2142 09bc 1B .uleb128 0x1b + 2143 09bd 4A050000 .4byte 0x54a + 2144 09c1 D2050000 .4byte .LLST39 + 2145 09c5 21 .uleb128 0x21 + 2146 09c6 2A000000 .4byte .LBB25 + 2147 09ca 30000000 .4byte .LBE25 + 2148 09ce 22 .uleb128 0x22 + 2149 09cf 55050000 .4byte 0x555 + 2150 09d3 F3050000 .4byte .LLST40 + 2151 09d7 00 .byte 0 + 2152 09d8 00 .byte 0 + 2153 09d9 23 .uleb128 0x23 + 2154 09da 34000000 .4byte .LVL51 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 39 + + + 2155 09de 9C0A0000 .4byte 0xa9c + 2156 09e2 00 .byte 0 + 2157 09e3 33 .uleb128 0x33 + 2158 09e4 01 .byte 0x1 + 2159 09e5 AD010000 .4byte .LASF88 + 2160 09e9 01 .byte 0x1 + 2161 09ea 9201 .2byte 0x192 + 2162 09ec 01 .byte 0x1 + 2163 09ed 30000000 .4byte 0x30 + 2164 09f1 00000000 .4byte .LFB17 + 2165 09f5 64000000 .4byte .LFE17 + 2166 09f9 06060000 .4byte .LLST41 + 2167 09fd 01 .byte 0x1 + 2168 09fe 720A0000 .4byte 0xa72 + 2169 0a02 2E .uleb128 0x2e + 2170 0a03 6F717000 .ascii "oqp\000" + 2171 0a07 01 .byte 0x1 + 2172 0a08 9201 .2byte 0x192 + 2173 0a0a 75080000 .4byte 0x875 + 2174 0a0e 26060000 .4byte .LLST42 + 2175 0a12 2E .uleb128 0x2e + 2176 0a13 627000 .ascii "bp\000" + 2177 0a16 01 .byte 0x1 + 2178 0a17 9201 .2byte 0x192 + 2179 0a19 05050000 .4byte 0x505 + 2180 0a1d 70060000 .4byte .LLST43 + 2181 0a21 2E .uleb128 0x2e + 2182 0a22 6E00 .ascii "n\000" + 2183 0a24 01 .byte 0x1 + 2184 0a25 9301 .2byte 0x193 + 2185 0a27 30000000 .4byte 0x30 + 2186 0a2b A6060000 .4byte .LLST44 + 2187 0a2f 31 .uleb128 0x31 + 2188 0a30 29020000 .4byte .LASF75 + 2189 0a34 01 .byte 0x1 + 2190 0a35 9301 .2byte 0x193 + 2191 0a37 E8000000 .4byte 0xe8 + 2192 0a3b DC060000 .4byte .LLST45 + 2193 0a3f 34 .uleb128 0x34 + 2194 0a40 6E667900 .ascii "nfy\000" + 2195 0a44 01 .byte 0x1 + 2196 0a45 9401 .2byte 0x194 + 2197 0a47 C6040000 .4byte 0x4c6 + 2198 0a4b 01 .byte 0x1 + 2199 0a4c 59 .byte 0x59 + 2200 0a4d 32 .uleb128 0x32 + 2201 0a4e 7700 .ascii "w\000" + 2202 0a50 01 .byte 0x1 + 2203 0a51 9501 .2byte 0x195 + 2204 0a53 30000000 .4byte 0x30 + 2205 0a57 FA060000 .4byte .LLST46 + 2206 0a5b 28 .uleb128 0x28 + 2207 0a5c 58000000 .4byte .LVL66 + 2208 0a60 60050000 .4byte 0x560 + 2209 0a64 1D .uleb128 0x1d + 2210 0a65 01 .byte 0x1 + 2211 0a66 51 .byte 0x51 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 40 + + + 2212 0a67 02 .byte 0x2 + 2213 0a68 7A .byte 0x7a + 2214 0a69 00 .sleb128 0 + 2215 0a6a 1D .uleb128 0x1d + 2216 0a6b 01 .byte 0x1 + 2217 0a6c 50 .byte 0x50 + 2218 0a6d 02 .byte 0x2 + 2219 0a6e 74 .byte 0x74 + 2220 0a6f 00 .sleb128 0 + 2221 0a70 00 .byte 0 + 2222 0a71 00 .byte 0 + 2223 0a72 35 .uleb128 0x35 + 2224 0a73 8F030000 .4byte .LASF95 + 2225 0a77 09 .byte 0x9 + 2226 0a78 72 .byte 0x72 + 2227 0a79 AC030000 .4byte 0x3ac + 2228 0a7d 01 .byte 0x1 + 2229 0a7e 01 .byte 0x1 + 2230 0a7f 36 .uleb128 0x36 + 2231 0a80 01 .byte 0x1 + 2232 0a81 AB030000 .4byte .LASF96 + 2233 0a85 09 .byte 0x9 + 2234 0a86 99 .byte 0x99 + 2235 0a87 01 .byte 0x1 + 2236 0a88 D2000000 .4byte 0xd2 + 2237 0a8c 01 .byte 0x1 + 2238 0a8d 9C0A0000 .4byte 0xa9c + 2239 0a91 12 .uleb128 0x12 + 2240 0a92 B1000000 .4byte 0xb1 + 2241 0a96 12 .uleb128 0x12 + 2242 0a97 E8000000 .4byte 0xe8 + 2243 0a9b 00 .byte 0 + 2244 0a9c 37 .uleb128 0x37 + 2245 0a9d 01 .byte 0x1 + 2246 0a9e EC020000 .4byte .LASF97 + 2247 0aa2 09 .byte 0x9 + 2248 0aa3 93 .byte 0x93 + 2249 0aa4 01 .byte 0x1 + 2250 0aa5 45020000 .4byte 0x245 + 2251 0aa9 01 .byte 0x1 + 2252 0aaa 12 .uleb128 0x12 + 2253 0aab 45020000 .4byte 0x245 + 2254 0aaf 00 .byte 0 + 2255 0ab0 00 .byte 0 + 2256 .section .debug_abbrev,"",%progbits + 2257 .Ldebug_abbrev0: + 2258 0000 01 .uleb128 0x1 + 2259 0001 11 .uleb128 0x11 + 2260 0002 01 .byte 0x1 + 2261 0003 25 .uleb128 0x25 + 2262 0004 0E .uleb128 0xe + 2263 0005 13 .uleb128 0x13 + 2264 0006 0B .uleb128 0xb + 2265 0007 03 .uleb128 0x3 + 2266 0008 0E .uleb128 0xe + 2267 0009 1B .uleb128 0x1b + 2268 000a 0E .uleb128 0xe + ARM GAS C:\cygwin\tmp\cchfGMii.s page 41 + + + 2269 000b 55 .uleb128 0x55 + 2270 000c 06 .uleb128 0x6 + 2271 000d 11 .uleb128 0x11 + 2272 000e 01 .uleb128 0x1 + 2273 000f 52 .uleb128 0x52 + 2274 0010 01 .uleb128 0x1 + 2275 0011 10 .uleb128 0x10 + 2276 0012 06 .uleb128 0x6 + 2277 0013 00 .byte 0 + 2278 0014 00 .byte 0 + 2279 0015 02 .uleb128 0x2 + 2280 0016 24 .uleb128 0x24 + 2281 0017 00 .byte 0 + 2282 0018 0B .uleb128 0xb + 2283 0019 0B .uleb128 0xb + 2284 001a 3E .uleb128 0x3e + 2285 001b 0B .uleb128 0xb + 2286 001c 03 .uleb128 0x3 + 2287 001d 08 .uleb128 0x8 + 2288 001e 00 .byte 0 + 2289 001f 00 .byte 0 + 2290 0020 03 .uleb128 0x3 + 2291 0021 16 .uleb128 0x16 + 2292 0022 00 .byte 0 + 2293 0023 03 .uleb128 0x3 + 2294 0024 0E .uleb128 0xe + 2295 0025 3A .uleb128 0x3a + 2296 0026 0B .uleb128 0xb + 2297 0027 3B .uleb128 0x3b + 2298 0028 0B .uleb128 0xb + 2299 0029 49 .uleb128 0x49 + 2300 002a 13 .uleb128 0x13 + 2301 002b 00 .byte 0 + 2302 002c 00 .byte 0 + 2303 002d 04 .uleb128 0x4 + 2304 002e 24 .uleb128 0x24 + 2305 002f 00 .byte 0 + 2306 0030 0B .uleb128 0xb + 2307 0031 0B .uleb128 0xb + 2308 0032 3E .uleb128 0x3e + 2309 0033 0B .uleb128 0xb + 2310 0034 03 .uleb128 0x3 + 2311 0035 0E .uleb128 0xe + 2312 0036 00 .byte 0 + 2313 0037 00 .byte 0 + 2314 0038 05 .uleb128 0x5 + 2315 0039 13 .uleb128 0x13 + 2316 003a 01 .byte 0x1 + 2317 003b 03 .uleb128 0x3 + 2318 003c 0E .uleb128 0xe + 2319 003d 0B .uleb128 0xb + 2320 003e 0B .uleb128 0xb + 2321 003f 3A .uleb128 0x3a + 2322 0040 0B .uleb128 0xb + 2323 0041 3B .uleb128 0x3b + 2324 0042 0B .uleb128 0xb + 2325 0043 01 .uleb128 0x1 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 42 + + + 2326 0044 13 .uleb128 0x13 + 2327 0045 00 .byte 0 + 2328 0046 00 .byte 0 + 2329 0047 06 .uleb128 0x6 + 2330 0048 0D .uleb128 0xd + 2331 0049 00 .byte 0 + 2332 004a 03 .uleb128 0x3 + 2333 004b 0E .uleb128 0xe + 2334 004c 3A .uleb128 0x3a + 2335 004d 0B .uleb128 0xb + 2336 004e 3B .uleb128 0x3b + 2337 004f 0B .uleb128 0xb + 2338 0050 49 .uleb128 0x49 + 2339 0051 13 .uleb128 0x13 + 2340 0052 38 .uleb128 0x38 + 2341 0053 0A .uleb128 0xa + 2342 0054 00 .byte 0 + 2343 0055 00 .byte 0 + 2344 0056 07 .uleb128 0x7 + 2345 0057 0D .uleb128 0xd + 2346 0058 00 .byte 0 + 2347 0059 03 .uleb128 0x3 + 2348 005a 08 .uleb128 0x8 + 2349 005b 3A .uleb128 0x3a + 2350 005c 0B .uleb128 0xb + 2351 005d 3B .uleb128 0x3b + 2352 005e 0B .uleb128 0xb + 2353 005f 49 .uleb128 0x49 + 2354 0060 13 .uleb128 0x13 + 2355 0061 38 .uleb128 0x38 + 2356 0062 0A .uleb128 0xa + 2357 0063 00 .byte 0 + 2358 0064 00 .byte 0 + 2359 0065 08 .uleb128 0x8 + 2360 0066 13 .uleb128 0x13 + 2361 0067 01 .byte 0x1 + 2362 0068 0B .uleb128 0xb + 2363 0069 0B .uleb128 0xb + 2364 006a 3A .uleb128 0x3a + 2365 006b 0B .uleb128 0xb + 2366 006c 3B .uleb128 0x3b + 2367 006d 0B .uleb128 0xb + 2368 006e 01 .uleb128 0x1 + 2369 006f 13 .uleb128 0x13 + 2370 0070 00 .byte 0 + 2371 0071 00 .byte 0 + 2372 0072 09 .uleb128 0x9 + 2373 0073 0F .uleb128 0xf + 2374 0074 00 .byte 0 + 2375 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.uleb128 0x3b + 2446 00bc 0B .uleb128 0xb + 2447 00bd 49 .uleb128 0x49 + 2448 00be 13 .uleb128 0x13 + 2449 00bf 00 .byte 0 + 2450 00c0 00 .byte 0 + 2451 00c1 10 .uleb128 0x10 + 2452 00c2 26 .uleb128 0x26 + 2453 00c3 00 .byte 0 + 2454 00c4 49 .uleb128 0x49 + 2455 00c5 13 .uleb128 0x13 + 2456 00c6 00 .byte 0 + 2457 00c7 00 .byte 0 + 2458 00c8 11 .uleb128 0x11 + 2459 00c9 15 .uleb128 0x15 + 2460 00ca 01 .byte 0x1 + 2461 00cb 27 .uleb128 0x27 + 2462 00cc 0C .uleb128 0xc + 2463 00cd 01 .uleb128 0x1 + 2464 00ce 13 .uleb128 0x13 + 2465 00cf 00 .byte 0 + 2466 00d0 00 .byte 0 + 2467 00d1 12 .uleb128 0x12 + 2468 00d2 05 .uleb128 0x5 + 2469 00d3 00 .byte 0 + 2470 00d4 49 .uleb128 0x49 + 2471 00d5 13 .uleb128 0x13 + 2472 00d6 00 .byte 0 + 2473 00d7 00 .byte 0 + 2474 00d8 13 .uleb128 0x13 + 2475 00d9 2E .uleb128 0x2e + 2476 00da 01 .byte 0x1 + 2477 00db 03 .uleb128 0x3 + 2478 00dc 0E .uleb128 0xe + 2479 00dd 3A .uleb128 0x3a + 2480 00de 0B .uleb128 0xb + 2481 00df 3B .uleb128 0x3b + 2482 00e0 0B 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2517 0103 20 .uleb128 0x20 + 2518 0104 0B .uleb128 0xb + 2519 0105 01 .uleb128 0x1 + 2520 0106 13 .uleb128 0x13 + 2521 0107 00 .byte 0 + 2522 0108 00 .byte 0 + 2523 0109 16 .uleb128 0x16 + 2524 010a 34 .uleb128 0x34 + 2525 010b 00 .byte 0 + 2526 010c 03 .uleb128 0x3 + 2527 010d 08 .uleb128 0x8 + 2528 010e 3A .uleb128 0x3a + 2529 010f 0B .uleb128 0xb + 2530 0110 3B .uleb128 0x3b + 2531 0111 0B .uleb128 0xb + 2532 0112 49 .uleb128 0x49 + 2533 0113 13 .uleb128 0x13 + 2534 0114 00 .byte 0 + 2535 0115 00 .byte 0 + 2536 0116 17 .uleb128 0x17 + 2537 0117 2E .uleb128 0x2e + 2538 0118 01 .byte 0x1 + 2539 0119 03 .uleb128 0x3 + 2540 011a 0E .uleb128 0xe + 2541 011b 3A .uleb128 0x3a + 2542 011c 0B .uleb128 0xb + 2543 011d 3B .uleb128 0x3b + 2544 011e 0B .uleb128 0xb + 2545 011f 27 .uleb128 0x27 + 2546 0120 0C .uleb128 0xc + 2547 0121 49 .uleb128 0x49 + 2548 0122 13 .uleb128 0x13 + 2549 0123 11 .uleb128 0x11 + 2550 0124 01 .uleb128 0x1 + 2551 0125 12 .uleb128 0x12 + 2552 0126 01 .uleb128 0x1 + 2553 0127 40 .uleb128 0x40 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 46 + + + 2554 0128 06 .uleb128 0x6 + 2555 0129 9742 .uleb128 0x2117 + 2556 012b 0C .uleb128 0xc + 2557 012c 01 .uleb128 0x1 + 2558 012d 13 .uleb128 0x13 + 2559 012e 00 .byte 0 + 2560 012f 00 .byte 0 + 2561 0130 18 .uleb128 0x18 + 2562 0131 05 .uleb128 0x5 + 2563 0132 00 .byte 0 + 2564 0133 03 .uleb128 0x3 + 2565 0134 08 .uleb128 0x8 + 2566 0135 3A .uleb128 0x3a + 2567 0136 0B .uleb128 0xb + 2568 0137 3B .uleb128 0x3b + 2569 0138 0B .uleb128 0xb + 2570 0139 49 .uleb128 0x49 + 2571 013a 13 .uleb128 0x13 + 2572 013b 02 .uleb128 0x2 + 2573 013c 06 .uleb128 0x6 + 2574 013d 00 .byte 0 + 2575 013e 00 .byte 0 + 2576 013f 19 .uleb128 0x19 + 2577 0140 05 .uleb128 0x5 + 2578 0141 00 .byte 0 + 2579 0142 03 .uleb128 0x3 + 2580 0143 0E .uleb128 0xe + 2581 0144 3A .uleb128 0x3a + 2582 0145 0B .uleb128 0xb + 2583 0146 3B .uleb128 0x3b + 2584 0147 0B .uleb128 0xb + 2585 0148 49 .uleb128 0x49 + 2586 0149 13 .uleb128 0x13 + 2587 014a 02 .uleb128 0x2 + 2588 014b 06 .uleb128 0x6 + 2589 014c 00 .byte 0 + 2590 014d 00 .byte 0 + 2591 014e 1A .uleb128 0x1a + 2592 014f 1D .uleb128 0x1d + 2593 0150 01 .byte 0x1 + 2594 0151 31 .uleb128 0x31 + 2595 0152 13 .uleb128 0x13 + 2596 0153 11 .uleb128 0x11 + 2597 0154 01 .uleb128 0x1 + 2598 0155 12 .uleb128 0x12 + 2599 0156 01 .uleb128 0x1 + 2600 0157 58 .uleb128 0x58 + 2601 0158 0B .uleb128 0xb + 2602 0159 59 .uleb128 0x59 + 2603 015a 0B .uleb128 0xb + 2604 015b 01 .uleb128 0x1 + 2605 015c 13 .uleb128 0x13 + 2606 015d 00 .byte 0 + 2607 015e 00 .byte 0 + 2608 015f 1B .uleb128 0x1b + 2609 0160 05 .uleb128 0x5 + 2610 0161 00 .byte 0 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 47 + + + 2611 0162 31 .uleb128 0x31 + 2612 0163 13 .uleb128 0x13 + 2613 0164 02 .uleb128 0x2 + 2614 0165 06 .uleb128 0x6 + 2615 0166 00 .byte 0 + 2616 0167 00 .byte 0 + 2617 0168 1C .uleb128 0x1c + 2618 0169 898201 .uleb128 0x4109 + 2619 016c 01 .byte 0x1 + 2620 016d 11 .uleb128 0x11 + 2621 016e 01 .uleb128 0x1 + 2622 016f 9542 .uleb128 0x2115 + 2623 0171 0C .uleb128 0xc + 2624 0172 31 .uleb128 0x31 + 2625 0173 13 .uleb128 0x13 + 2626 0174 00 .byte 0 + 2627 0175 00 .byte 0 + 2628 0176 1D .uleb128 0x1d + 2629 0177 8A8201 .uleb128 0x410a + 2630 017a 00 .byte 0 + 2631 017b 02 .uleb128 0x2 + 2632 017c 0A .uleb128 0xa + 2633 017d 9142 .uleb128 0x2111 + 2634 017f 0A .uleb128 0xa + 2635 0180 00 .byte 0 + 2636 0181 00 .byte 0 + 2637 0182 1E .uleb128 0x1e + 2638 0183 2E .uleb128 0x2e + 2639 0184 01 .byte 0x1 + 2640 0185 3F .uleb128 0x3f + 2641 0186 0C .uleb128 0xc + 2642 0187 03 .uleb128 0x3 + 2643 0188 0E .uleb128 0xe + 2644 0189 3A .uleb128 0x3a + 2645 018a 0B .uleb128 0xb + 2646 018b 3B .uleb128 0x3b + 2647 018c 0B .uleb128 0xb + 2648 018d 27 .uleb128 0x27 + 2649 018e 0C .uleb128 0xc + 2650 018f 11 .uleb128 0x11 + 2651 0190 01 .uleb128 0x1 + 2652 0191 12 .uleb128 0x12 + 2653 0192 01 .uleb128 0x1 + 2654 0193 40 .uleb128 0x40 + 2655 0194 06 .uleb128 0x6 + 2656 0195 9742 .uleb128 0x2117 + 2657 0197 0C .uleb128 0xc + 2658 0198 01 .uleb128 0x1 + 2659 0199 13 .uleb128 0x13 + 2660 019a 00 .byte 0 + 2661 019b 00 .byte 0 + 2662 019c 1F .uleb128 0x1f + 2663 019d 05 .uleb128 0x5 + 2664 019e 00 .byte 0 + 2665 019f 03 .uleb128 0x3 + 2666 01a0 08 .uleb128 0x8 + 2667 01a1 3A .uleb128 0x3a + ARM GAS C:\cygwin\tmp\cchfGMii.s page 48 + + + 2668 01a2 0B .uleb128 0xb + 2669 01a3 3B .uleb128 0x3b + 2670 01a4 0B .uleb128 0xb + 2671 01a5 49 .uleb128 0x49 + 2672 01a6 13 .uleb128 0x13 + 2673 01a7 02 .uleb128 0x2 + 2674 01a8 0A .uleb128 0xa + 2675 01a9 00 .byte 0 + 2676 01aa 00 .byte 0 + 2677 01ab 20 .uleb128 0x20 + 2678 01ac 05 .uleb128 0x5 + 2679 01ad 00 .byte 0 + 2680 01ae 03 .uleb128 0x3 + 2681 01af 0E .uleb128 0xe + 2682 01b0 3A .uleb128 0x3a + 2683 01b1 0B .uleb128 0xb + 2684 01b2 3B .uleb128 0x3b + 2685 01b3 0B .uleb128 0xb + 2686 01b4 49 .uleb128 0x49 + 2687 01b5 13 .uleb128 0x13 + 2688 01b6 02 .uleb128 0x2 + 2689 01b7 0A .uleb128 0xa + 2690 01b8 00 .byte 0 + 2691 01b9 00 .byte 0 + 2692 01ba 21 .uleb128 0x21 + 2693 01bb 0B .uleb128 0xb + 2694 01bc 01 .byte 0x1 + 2695 01bd 11 .uleb128 0x11 + 2696 01be 01 .uleb128 0x1 + 2697 01bf 12 .uleb128 0x12 + 2698 01c0 01 .uleb128 0x1 + 2699 01c1 00 .byte 0 + 2700 01c2 00 .byte 0 + 2701 01c3 22 .uleb128 0x22 + 2702 01c4 34 .uleb128 0x34 + 2703 01c5 00 .byte 0 + 2704 01c6 31 .uleb128 0x31 + 2705 01c7 13 .uleb128 0x13 + 2706 01c8 02 .uleb128 0x2 + 2707 01c9 06 .uleb128 0x6 + 2708 01ca 00 .byte 0 + 2709 01cb 00 .byte 0 + 2710 01cc 23 .uleb128 0x23 + 2711 01cd 898201 .uleb128 0x4109 + 2712 01d0 00 .byte 0 + 2713 01d1 11 .uleb128 0x11 + 2714 01d2 01 .uleb128 0x1 + 2715 01d3 31 .uleb128 0x31 + 2716 01d4 13 .uleb128 0x13 + 2717 01d5 00 .byte 0 + 2718 01d6 00 .byte 0 + 2719 01d7 24 .uleb128 0x24 + 2720 01d8 2E .uleb128 0x2e + 2721 01d9 01 .byte 0x1 + 2722 01da 3F .uleb128 0x3f + 2723 01db 0C .uleb128 0xc + 2724 01dc 03 .uleb128 0x3 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 49 + + + 2725 01dd 0E .uleb128 0xe + 2726 01de 3A .uleb128 0x3a + 2727 01df 0B .uleb128 0xb + 2728 01e0 3B .uleb128 0x3b + 2729 01e1 0B .uleb128 0xb + 2730 01e2 27 .uleb128 0x27 + 2731 01e3 0C .uleb128 0xc + 2732 01e4 49 .uleb128 0x49 + 2733 01e5 13 .uleb128 0x13 + 2734 01e6 11 .uleb128 0x11 + 2735 01e7 01 .uleb128 0x1 + 2736 01e8 12 .uleb128 0x12 + 2737 01e9 01 .uleb128 0x1 + 2738 01ea 40 .uleb128 0x40 + 2739 01eb 06 .uleb128 0x6 + 2740 01ec 9742 .uleb128 0x2117 + 2741 01ee 0C .uleb128 0xc + 2742 01ef 01 .uleb128 0x1 + 2743 01f0 13 .uleb128 0x13 + 2744 01f1 00 .byte 0 + 2745 01f2 00 .byte 0 + 2746 01f3 25 .uleb128 0x25 + 2747 01f4 34 .uleb128 0x34 + 2748 01f5 00 .byte 0 + 2749 01f6 03 .uleb128 0x3 + 2750 01f7 08 .uleb128 0x8 + 2751 01f8 3A .uleb128 0x3a + 2752 01f9 0B .uleb128 0xb + 2753 01fa 3B .uleb128 0x3b + 2754 01fb 0B .uleb128 0xb + 2755 01fc 49 .uleb128 0x49 + 2756 01fd 13 .uleb128 0x13 + 2757 01fe 02 .uleb128 0x2 + 2758 01ff 0A .uleb128 0xa + 2759 0200 00 .byte 0 + 2760 0201 00 .byte 0 + 2761 0202 26 .uleb128 0x26 + 2762 0203 0B .uleb128 0xb + 2763 0204 01 .byte 0x1 + 2764 0205 55 .uleb128 0x55 + 2765 0206 06 .uleb128 0x6 + 2766 0207 01 .uleb128 0x1 + 2767 0208 13 .uleb128 0x13 + 2768 0209 00 .byte 0 + 2769 020a 00 .byte 0 + 2770 020b 27 .uleb128 0x27 + 2771 020c 34 .uleb128 0x34 + 2772 020d 00 .byte 0 + 2773 020e 03 .uleb128 0x3 + 2774 020f 08 .uleb128 0x8 + 2775 0210 3A .uleb128 0x3a + 2776 0211 0B .uleb128 0xb + 2777 0212 3B .uleb128 0x3b + 2778 0213 0B .uleb128 0xb + 2779 0214 49 .uleb128 0x49 + 2780 0215 13 .uleb128 0x13 + 2781 0216 02 .uleb128 0x2 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 50 + + + 2782 0217 06 .uleb128 0x6 + 2783 0218 00 .byte 0 + 2784 0219 00 .byte 0 + 2785 021a 28 .uleb128 0x28 + 2786 021b 898201 .uleb128 0x4109 + 2787 021e 01 .byte 0x1 + 2788 021f 11 .uleb128 0x11 + 2789 0220 01 .uleb128 0x1 + 2790 0221 31 .uleb128 0x31 + 2791 0222 13 .uleb128 0x13 + 2792 0223 00 .byte 0 + 2793 0224 00 .byte 0 + 2794 0225 29 .uleb128 0x29 + 2795 0226 898201 .uleb128 0x4109 + 2796 0229 01 .byte 0x1 + 2797 022a 11 .uleb128 0x11 + 2798 022b 01 .uleb128 0x1 + 2799 022c 00 .byte 0 + 2800 022d 00 .byte 0 + 2801 022e 2A .uleb128 0x2a + 2802 022f 898201 .uleb128 0x4109 + 2803 0232 01 .byte 0x1 + 2804 0233 11 .uleb128 0x11 + 2805 0234 01 .uleb128 0x1 + 2806 0235 01 .uleb128 0x1 + 2807 0236 13 .uleb128 0x13 + 2808 0237 00 .byte 0 + 2809 0238 00 .byte 0 + 2810 0239 2B .uleb128 0x2b + 2811 023a 2E .uleb128 0x2e + 2812 023b 01 .byte 0x1 + 2813 023c 3F .uleb128 0x3f + 2814 023d 0C .uleb128 0xc + 2815 023e 03 .uleb128 0x3 + 2816 023f 0E .uleb128 0xe + 2817 0240 3A .uleb128 0x3a + 2818 0241 0B .uleb128 0xb + 2819 0242 3B .uleb128 0x3b + 2820 0243 05 .uleb128 0x5 + 2821 0244 27 .uleb128 0x27 + 2822 0245 0C .uleb128 0xc + 2823 0246 11 .uleb128 0x11 + 2824 0247 01 .uleb128 0x1 + 2825 0248 12 .uleb128 0x12 + 2826 0249 01 .uleb128 0x1 + 2827 024a 40 .uleb128 0x40 + 2828 024b 06 .uleb128 0x6 + 2829 024c 9742 .uleb128 0x2117 + 2830 024e 0C .uleb128 0xc + 2831 024f 01 .uleb128 0x1 + 2832 0250 13 .uleb128 0x13 + 2833 0251 00 .byte 0 + 2834 0252 00 .byte 0 + 2835 0253 2C .uleb128 0x2c + 2836 0254 05 .uleb128 0x5 + 2837 0255 00 .byte 0 + 2838 0256 03 .uleb128 0x3 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 51 + + + 2839 0257 08 .uleb128 0x8 + 2840 0258 3A .uleb128 0x3a + 2841 0259 0B .uleb128 0xb + 2842 025a 3B .uleb128 0x3b + 2843 025b 05 .uleb128 0x5 + 2844 025c 49 .uleb128 0x49 + 2845 025d 13 .uleb128 0x13 + 2846 025e 02 .uleb128 0x2 + 2847 025f 0A .uleb128 0xa + 2848 0260 00 .byte 0 + 2849 0261 00 .byte 0 + 2850 0262 2D .uleb128 0x2d + 2851 0263 05 .uleb128 0x5 + 2852 0264 00 .byte 0 + 2853 0265 03 .uleb128 0x3 + 2854 0266 0E .uleb128 0xe + 2855 0267 3A .uleb128 0x3a + 2856 0268 0B .uleb128 0xb + 2857 0269 3B .uleb128 0x3b + 2858 026a 05 .uleb128 0x5 + 2859 026b 49 .uleb128 0x49 + 2860 026c 13 .uleb128 0x13 + 2861 026d 02 .uleb128 0x2 + 2862 026e 0A .uleb128 0xa + 2863 026f 00 .byte 0 + 2864 0270 00 .byte 0 + 2865 0271 2E .uleb128 0x2e + 2866 0272 05 .uleb128 0x5 + 2867 0273 00 .byte 0 + 2868 0274 03 .uleb128 0x3 + 2869 0275 08 .uleb128 0x8 + 2870 0276 3A .uleb128 0x3a + 2871 0277 0B .uleb128 0xb + 2872 0278 3B .uleb128 0x3b + 2873 0279 05 .uleb128 0x5 + 2874 027a 49 .uleb128 0x49 + 2875 027b 13 .uleb128 0x13 + 2876 027c 02 .uleb128 0x2 + 2877 027d 06 .uleb128 0x6 + 2878 027e 00 .byte 0 + 2879 027f 00 .byte 0 + 2880 0280 2F .uleb128 0x2f + 2881 0281 1D .uleb128 0x1d + 2882 0282 01 .byte 0x1 + 2883 0283 31 .uleb128 0x31 + 2884 0284 13 .uleb128 0x13 + 2885 0285 11 .uleb128 0x11 + 2886 0286 01 .uleb128 0x1 + 2887 0287 12 .uleb128 0x12 + 2888 0288 01 .uleb128 0x1 + 2889 0289 58 .uleb128 0x58 + 2890 028a 0B .uleb128 0xb + 2891 028b 59 .uleb128 0x59 + 2892 028c 05 .uleb128 0x5 + 2893 028d 01 .uleb128 0x1 + 2894 028e 13 .uleb128 0x13 + 2895 028f 00 .byte 0 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 52 + + + 2896 0290 00 .byte 0 + 2897 0291 30 .uleb128 0x30 + 2898 0292 2E .uleb128 0x2e + 2899 0293 01 .byte 0x1 + 2900 0294 3F .uleb128 0x3f + 2901 0295 0C .uleb128 0xc + 2902 0296 03 .uleb128 0x3 + 2903 0297 0E .uleb128 0xe + 2904 0298 3A .uleb128 0x3a + 2905 0299 0B .uleb128 0xb + 2906 029a 3B .uleb128 0x3b + 2907 029b 05 .uleb128 0x5 + 2908 029c 27 .uleb128 0x27 + 2909 029d 0C .uleb128 0xc + 2910 029e 49 .uleb128 0x49 + 2911 029f 13 .uleb128 0x13 + 2912 02a0 11 .uleb128 0x11 + 2913 02a1 01 .uleb128 0x1 + 2914 02a2 12 .uleb128 0x12 + 2915 02a3 01 .uleb128 0x1 + 2916 02a4 40 .uleb128 0x40 + 2917 02a5 06 .uleb128 0x6 + 2918 02a6 9742 .uleb128 0x2117 + 2919 02a8 0C .uleb128 0xc + 2920 02a9 01 .uleb128 0x1 + 2921 02aa 13 .uleb128 0x13 + 2922 02ab 00 .byte 0 + 2923 02ac 00 .byte 0 + 2924 02ad 31 .uleb128 0x31 + 2925 02ae 05 .uleb128 0x5 + 2926 02af 00 .byte 0 + 2927 02b0 03 .uleb128 0x3 + 2928 02b1 0E .uleb128 0xe + 2929 02b2 3A .uleb128 0x3a + 2930 02b3 0B .uleb128 0xb + 2931 02b4 3B .uleb128 0x3b + 2932 02b5 05 .uleb128 0x5 + 2933 02b6 49 .uleb128 0x49 + 2934 02b7 13 .uleb128 0x13 + 2935 02b8 02 .uleb128 0x2 + 2936 02b9 06 .uleb128 0x6 + 2937 02ba 00 .byte 0 + 2938 02bb 00 .byte 0 + 2939 02bc 32 .uleb128 0x32 + 2940 02bd 34 .uleb128 0x34 + 2941 02be 00 .byte 0 + 2942 02bf 03 .uleb128 0x3 + 2943 02c0 08 .uleb128 0x8 + 2944 02c1 3A .uleb128 0x3a + 2945 02c2 0B .uleb128 0xb + 2946 02c3 3B .uleb128 0x3b + 2947 02c4 05 .uleb128 0x5 + 2948 02c5 49 .uleb128 0x49 + 2949 02c6 13 .uleb128 0x13 + 2950 02c7 02 .uleb128 0x2 + 2951 02c8 06 .uleb128 0x6 + 2952 02c9 00 .byte 0 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 53 + + + 2953 02ca 00 .byte 0 + 2954 02cb 33 .uleb128 0x33 + 2955 02cc 2E .uleb128 0x2e + 2956 02cd 01 .byte 0x1 + 2957 02ce 3F .uleb128 0x3f + 2958 02cf 0C .uleb128 0xc + 2959 02d0 03 .uleb128 0x3 + 2960 02d1 0E .uleb128 0xe + 2961 02d2 3A .uleb128 0x3a + 2962 02d3 0B .uleb128 0xb + 2963 02d4 3B .uleb128 0x3b + 2964 02d5 05 .uleb128 0x5 + 2965 02d6 27 .uleb128 0x27 + 2966 02d7 0C .uleb128 0xc + 2967 02d8 49 .uleb128 0x49 + 2968 02d9 13 .uleb128 0x13 + 2969 02da 11 .uleb128 0x11 + 2970 02db 01 .uleb128 0x1 + 2971 02dc 12 .uleb128 0x12 + 2972 02dd 01 .uleb128 0x1 + 2973 02de 40 .uleb128 0x40 + 2974 02df 06 .uleb128 0x6 + 2975 02e0 9642 .uleb128 0x2116 + 2976 02e2 0C .uleb128 0xc + 2977 02e3 01 .uleb128 0x1 + 2978 02e4 13 .uleb128 0x13 + 2979 02e5 00 .byte 0 + 2980 02e6 00 .byte 0 + 2981 02e7 34 .uleb128 0x34 + 2982 02e8 34 .uleb128 0x34 + 2983 02e9 00 .byte 0 + 2984 02ea 03 .uleb128 0x3 + 2985 02eb 08 .uleb128 0x8 + 2986 02ec 3A .uleb128 0x3a + 2987 02ed 0B .uleb128 0xb + 2988 02ee 3B .uleb128 0x3b + 2989 02ef 05 .uleb128 0x5 + 2990 02f0 49 .uleb128 0x49 + 2991 02f1 13 .uleb128 0x13 + 2992 02f2 02 .uleb128 0x2 + 2993 02f3 0A .uleb128 0xa + 2994 02f4 00 .byte 0 + 2995 02f5 00 .byte 0 + 2996 02f6 35 .uleb128 0x35 + 2997 02f7 34 .uleb128 0x34 + 2998 02f8 00 .byte 0 + 2999 02f9 03 .uleb128 0x3 + 3000 02fa 0E .uleb128 0xe + 3001 02fb 3A .uleb128 0x3a + 3002 02fc 0B .uleb128 0xb + 3003 02fd 3B .uleb128 0x3b + 3004 02fe 0B .uleb128 0xb + 3005 02ff 49 .uleb128 0x49 + 3006 0300 13 .uleb128 0x13 + 3007 0301 3F .uleb128 0x3f + 3008 0302 0C .uleb128 0xc + 3009 0303 3C .uleb128 0x3c + ARM GAS C:\cygwin\tmp\cchfGMii.s page 54 + + + 3010 0304 0C .uleb128 0xc + 3011 0305 00 .byte 0 + 3012 0306 00 .byte 0 + 3013 0307 36 .uleb128 0x36 + 3014 0308 2E .uleb128 0x2e + 3015 0309 01 .byte 0x1 + 3016 030a 3F .uleb128 0x3f + 3017 030b 0C .uleb128 0xc + 3018 030c 03 .uleb128 0x3 + 3019 030d 0E .uleb128 0xe + 3020 030e 3A .uleb128 0x3a + 3021 030f 0B .uleb128 0xb + 3022 0310 3B .uleb128 0x3b + 3023 0311 0B .uleb128 0xb + 3024 0312 27 .uleb128 0x27 + 3025 0313 0C .uleb128 0xc + 3026 0314 49 .uleb128 0x49 + 3027 0315 13 .uleb128 0x13 + 3028 0316 3C .uleb128 0x3c + 3029 0317 0C .uleb128 0xc + 3030 0318 01 .uleb128 0x1 + 3031 0319 13 .uleb128 0x13 + 3032 031a 00 .byte 0 + 3033 031b 00 .byte 0 + 3034 031c 37 .uleb128 0x37 + 3035 031d 2E .uleb128 0x2e + 3036 031e 01 .byte 0x1 + 3037 031f 3F .uleb128 0x3f + 3038 0320 0C .uleb128 0xc + 3039 0321 03 .uleb128 0x3 + 3040 0322 0E .uleb128 0xe + 3041 0323 3A .uleb128 0x3a + 3042 0324 0B .uleb128 0xb + 3043 0325 3B .uleb128 0x3b + 3044 0326 0B .uleb128 0xb + 3045 0327 27 .uleb128 0x27 + 3046 0328 0C .uleb128 0xc + 3047 0329 49 .uleb128 0x49 + 3048 032a 13 .uleb128 0x13 + 3049 032b 3C .uleb128 0x3c + 3050 032c 0C .uleb128 0xc + 3051 032d 00 .byte 0 + 3052 032e 00 .byte 0 + 3053 032f 00 .byte 0 + 3054 .section .debug_loc,"",%progbits + 3055 .Ldebug_loc0: + 3056 .LLST0: + 3057 0000 00000000 .4byte .LFB7 + 3058 0004 02000000 .4byte .LCFI0 + 3059 0008 0200 .2byte 0x2 + 3060 000a 7D .byte 0x7d + 3061 000b 00 .sleb128 0 + 3062 000c 02000000 .4byte .LCFI0 + 3063 0010 2C000000 .4byte .LFE7 + 3064 0014 0200 .2byte 0x2 + 3065 0016 7D .byte 0x7d + 3066 0017 04 .sleb128 4 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 55 + + + 3067 0018 00000000 .4byte 0 + 3068 001c 00000000 .4byte 0 + 3069 .LLST1: + 3070 0020 00000000 .4byte .LVL0 + 3071 0024 0A000000 .4byte .LVL1 + 3072 0028 0100 .2byte 0x1 + 3073 002a 50 .byte 0x50 + 3074 002b 0A000000 .4byte .LVL1 + 3075 002f 1D000000 .4byte .LVL3-1 + 3076 0033 0100 .2byte 0x1 + 3077 0035 52 .byte 0x52 + 3078 0036 1D000000 .4byte .LVL3-1 + 3079 003a 1E000000 .4byte .LVL3 + 3080 003e 0400 .2byte 0x4 + 3081 0040 F3 .byte 0xf3 + 3082 0041 01 .uleb128 0x1 + 3083 0042 50 .byte 0x50 + 3084 0043 9F .byte 0x9f + 3085 0044 1E000000 .4byte .LVL3 + 3086 0048 22000000 .4byte .LVL4 + 3087 004c 0100 .2byte 0x1 + 3088 004e 50 .byte 0x50 + 3089 004f 22000000 .4byte .LVL4 + 3090 0053 2C000000 .4byte .LFE7 + 3091 0057 0100 .2byte 0x1 + 3092 0059 52 .byte 0x52 + 3093 005a 00000000 .4byte 0 + 3094 005e 00000000 .4byte 0 + 3095 .LLST2: + 3096 0062 00000000 .4byte .LVL0 + 3097 0066 1D000000 .4byte .LVL3-1 + 3098 006a 0100 .2byte 0x1 + 3099 006c 51 .byte 0x51 + 3100 006d 1D000000 .4byte .LVL3-1 + 3101 0071 1E000000 .4byte .LVL3 + 3102 0075 0400 .2byte 0x4 + 3103 0077 F3 .byte 0xf3 + 3104 0078 01 .uleb128 0x1 + 3105 0079 51 .byte 0x51 + 3106 007a 9F .byte 0x9f + 3107 007b 1E000000 .4byte .LVL3 + 3108 007f 2C000000 .4byte .LFE7 + 3109 0083 0100 .2byte 0x1 + 3110 0085 51 .byte 0x51 + 3111 0086 00000000 .4byte 0 + 3112 008a 00000000 .4byte 0 + 3113 .LLST3: + 3114 008e 0E000000 .4byte .LVL2 + 3115 0092 1D000000 .4byte .LVL3-1 + 3116 0096 0100 .2byte 0x1 + 3117 0098 52 .byte 0x52 + 3118 0099 1D000000 .4byte .LVL3-1 + 3119 009d 1E000000 .4byte .LVL3 + 3120 00a1 0400 .2byte 0x4 + 3121 00a3 F3 .byte 0xf3 + 3122 00a4 01 .uleb128 0x1 + 3123 00a5 50 .byte 0x50 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 56 + + + 3124 00a6 9F .byte 0x9f + 3125 00a7 00000000 .4byte 0 + 3126 00ab 00000000 .4byte 0 + 3127 .LLST4: + 3128 00af 0E000000 .4byte .LVL2 + 3129 00b3 1D000000 .4byte .LVL3-1 + 3130 00b7 0100 .2byte 0x1 + 3131 00b9 53 .byte 0x53 + 3132 00ba 00000000 .4byte 0 + 3133 00be 00000000 .4byte 0 + 3134 .LLST5: + 3135 00c2 00000000 .4byte .LFB8 + 3136 00c6 02000000 .4byte .LCFI1 + 3137 00ca 0200 .2byte 0x2 + 3138 00cc 7D .byte 0x7d + 3139 00cd 00 .sleb128 0 + 3140 00ce 02000000 .4byte .LCFI1 + 3141 00d2 1A000000 .4byte .LFE8 + 3142 00d6 0200 .2byte 0x2 + 3143 00d8 7D .byte 0x7d + 3144 00d9 04 .sleb128 4 + 3145 00da 00000000 .4byte 0 + 3146 00de 00000000 .4byte 0 + 3147 .LLST6: + 3148 00e2 00000000 .4byte .LVL5 + 3149 00e6 04000000 .4byte .LVL6 + 3150 00ea 0100 .2byte 0x1 + 3151 00ec 52 .byte 0x52 + 3152 00ed 04000000 .4byte .LVL6 + 3153 00f1 1A000000 .4byte .LFE8 + 3154 00f5 0400 .2byte 0x4 + 3155 00f7 F3 .byte 0xf3 + 3156 00f8 01 .uleb128 0x1 + 3157 00f9 52 .byte 0x52 + 3158 00fa 9F .byte 0x9f + 3159 00fb 00000000 .4byte 0 + 3160 00ff 00000000 .4byte 0 + 3161 .LLST7: + 3162 0103 00000000 .4byte .LFB9 + 3163 0107 02000000 .4byte .LCFI2 + 3164 010b 0200 .2byte 0x2 + 3165 010d 7D .byte 0x7d + 3166 010e 00 .sleb128 0 + 3167 010f 02000000 .4byte .LCFI2 + 3168 0113 2C000000 .4byte .LFE9 + 3169 0117 0200 .2byte 0x2 + 3170 0119 7D .byte 0x7d + 3171 011a 10 .sleb128 16 + 3172 011b 00000000 .4byte 0 + 3173 011f 00000000 .4byte 0 + 3174 .LLST8: + 3175 0123 00000000 .4byte .LVL7 + 3176 0127 08000000 .4byte .LVL8 + 3177 012b 0100 .2byte 0x1 + 3178 012d 50 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C:\cygwin\tmp\cchfGMii.s page 65 + + + 3637 .LLST39: + 3638 05d2 2A000000 .4byte .LVL50 + 3639 05d6 33000000 .4byte .LVL51-1 + 3640 05da 0100 .2byte 0x1 + 3641 05dc 53 .byte 0x53 + 3642 05dd 33000000 .4byte .LVL51-1 + 3643 05e1 38000000 .4byte .LVL52 + 3644 05e5 0400 .2byte 0x4 + 3645 05e7 F3 .byte 0xf3 + 3646 05e8 01 .uleb128 0x1 + 3647 05e9 50 .byte 0x50 + 3648 05ea 9F .byte 0x9f + 3649 05eb 00000000 .4byte 0 + 3650 05ef 00000000 .4byte 0 + 3651 .LLST40: + 3652 05f3 2A000000 .4byte .LVL50 + 3653 05f7 33000000 .4byte .LVL51-1 + 3654 05fb 0100 .2byte 0x1 + 3655 05fd 50 .byte 0x50 + 3656 05fe 00000000 .4byte 0 + 3657 0602 00000000 .4byte 0 + 3658 .LLST41: + 3659 0606 00000000 .4byte .LFB17 + 3660 060a 04000000 .4byte .LCFI10 + 3661 060e 0200 .2byte 0x2 + 3662 0610 7D .byte 0x7d + 3663 0611 00 .sleb128 0 + 3664 0612 04000000 .4byte .LCFI10 + 3665 0616 64000000 .4byte .LFE17 + 3666 061a 0200 .2byte 0x2 + 3667 061c 7D .byte 0x7d + 3668 061d 20 .sleb128 32 + 3669 061e 00000000 .4byte 0 + 3670 0622 00000000 .4byte 0 + 3671 .LLST42: + 3672 0626 00000000 .4byte .LVL55 + 3673 062a 14000000 .4byte .LVL57 + 3674 062e 0100 .2byte 0x1 + 3675 0630 50 .byte 0x50 + 3676 0631 14000000 .4byte .LVL57 + 3677 0635 1C000000 .4byte .LVL58 + 3678 0639 0100 .2byte 0x1 + 3679 063b 54 .byte 0x54 + 3680 063c 1C000000 .4byte .LVL58 + 3681 0640 3B000000 .4byte .LVL61-1 + 3682 0644 0100 .2byte 0x1 + 3683 0646 50 .byte 0x50 + 3684 0647 3B000000 .4byte .LVL61-1 + 3685 064b 50000000 .4byte .LVL64 + 3686 064f 0100 .2byte 0x1 + 3687 0651 54 .byte 0x54 + 3688 0652 50000000 .4byte .LVL64 + 3689 0656 52000000 .4byte .LVL65 + 3690 065a 0100 .2byte 0x1 + 3691 065c 50 .byte 0x50 + 3692 065d 52000000 .4byte .LVL65 + 3693 0661 64000000 .4byte .LFE17 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 66 + + + 3694 0665 0100 .2byte 0x1 + 3695 0667 54 .byte 0x54 + 3696 0668 00000000 .4byte 0 + 3697 066c 00000000 .4byte 0 + 3698 .LLST43: + 3699 0670 00000000 .4byte .LVL55 + 3700 0674 14000000 .4byte .LVL57 + 3701 0678 0100 .2byte 0x1 + 3702 067a 51 .byte 0x51 + 3703 067b 14000000 .4byte .LVL57 + 3704 067f 22000000 .4byte .LVL59 + 3705 0683 0100 .2byte 0x1 + 3706 0685 58 .byte 0x58 + 3707 0686 22000000 .4byte .LVL59 + 3708 068a 2C000000 .4byte .LVL60 + 3709 068e 0300 .2byte 0x3 + 3710 0690 78 .byte 0x78 + 3711 0691 7F .sleb128 -1 + 3712 0692 9F .byte 0x9f + 3713 0693 2C000000 .4byte .LVL60 + 3714 0697 64000000 .4byte .LFE17 + 3715 069b 0100 .2byte 0x1 + 3716 069d 58 .byte 0x58 + 3717 069e 00000000 .4byte 0 + 3718 06a2 00000000 .4byte 0 + 3719 .LLST44: + 3720 06a6 00000000 .4byte .LVL55 + 3721 06aa 14000000 .4byte .LVL57 + 3722 06ae 0100 .2byte 0x1 + 3723 06b0 52 .byte 0x52 + 3724 06b1 14000000 .4byte .LVL57 + 3725 06b5 40000000 .4byte .LVL62 + 3726 06b9 0100 .2byte 0x1 + 3727 06bb 56 .byte 0x56 + 3728 06bc 40000000 .4byte .LVL62 + 3729 06c0 42000000 .4byte .LVL63 + 3730 06c4 0300 .2byte 0x3 + 3731 06c6 76 .byte 0x76 + 3732 06c7 7F .sleb128 -1 + 3733 06c8 9F .byte 0x9f + 3734 06c9 42000000 .4byte .LVL63 + 3735 06cd 64000000 .4byte .LFE17 + 3736 06d1 0100 .2byte 0x1 + 3737 06d3 56 .byte 0x56 + 3738 06d4 00000000 .4byte 0 + 3739 06d8 00000000 .4byte 0 + 3740 .LLST45: + 3741 06dc 00000000 .4byte .LVL55 + 3742 06e0 14000000 .4byte .LVL57 + 3743 06e4 0100 .2byte 0x1 + 3744 06e6 53 .byte 0x53 + 3745 06e7 14000000 .4byte .LVL57 + 3746 06eb 64000000 .4byte .LFE17 + 3747 06ef 0100 .2byte 0x1 + 3748 06f1 5A .byte 0x5a + 3749 06f2 00000000 .4byte 0 + 3750 06f6 00000000 .4byte 0 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 67 + + + 3751 .LLST46: + 3752 06fa 10000000 .4byte .LVL56 + 3753 06fe 14000000 .4byte .LVL57 + 3754 0702 0200 .2byte 0x2 + 3755 0704 30 .byte 0x30 + 3756 0705 9F .byte 0x9f + 3757 0706 14000000 .4byte .LVL57 + 3758 070a 64000000 .4byte .LFE17 + 3759 070e 0100 .2byte 0x1 + 3760 0710 57 .byte 0x57 + 3761 0711 00000000 .4byte 0 + 3762 0715 00000000 .4byte 0 + 3763 .section .debug_aranges,"",%progbits + 3764 0000 6C000000 .4byte 0x6c + 3765 0004 0200 .2byte 0x2 + 3766 0006 00000000 .4byte .Ldebug_info0 + 3767 000a 04 .byte 0x4 + 3768 000b 00 .byte 0 + 3769 000c 0000 .2byte 0 + 3770 000e 0000 .2byte 0 + 3771 0010 00000000 .4byte .LFB7 + 3772 0014 2C000000 .4byte .LFE7-.LFB7 + 3773 0018 00000000 .4byte .LFB8 + 3774 001c 1A000000 .4byte .LFE8-.LFB8 + 3775 0020 00000000 .4byte .LFB9 + 3776 0024 2C000000 .4byte .LFE9-.LFB9 + 3777 0028 00000000 .4byte .LFB10 + 3778 002c 4A000000 .4byte .LFE10-.LFB10 + 3779 0030 00000000 .4byte .LFB11 + 3780 0034 3C000000 .4byte .LFE11-.LFB11 + 3781 0038 00000000 .4byte .LFB12 + 3782 003c 62000000 .4byte .LFE12-.LFB12 + 3783 0040 00000000 .4byte .LFB13 + 3784 0044 18000000 .4byte .LFE13-.LFB13 + 3785 0048 00000000 .4byte .LFB14 + 3786 004c 2E000000 .4byte .LFE14-.LFB14 + 3787 0050 00000000 .4byte .LFB15 + 3788 0054 42000000 .4byte .LFE15-.LFB15 + 3789 0058 00000000 .4byte .LFB16 + 3790 005c 46000000 .4byte .LFE16-.LFB16 + 3791 0060 00000000 .4byte .LFB17 + 3792 0064 64000000 .4byte .LFE17-.LFB17 + 3793 0068 00000000 .4byte 0 + 3794 006c 00000000 .4byte 0 + 3795 .section .debug_ranges,"",%progbits + 3796 .Ldebug_ranges0: + 3797 0000 10000000 .4byte .LBB18 + 3798 0004 14000000 .4byte .LBE18 + 3799 0008 16000000 .4byte .LBB19 + 3800 000c 1E000000 .4byte .LBE19 + 3801 0010 00000000 .4byte 0 + 3802 0014 00000000 .4byte 0 + 3803 0018 0C000000 .4byte .LBB22 + 3804 001c 10000000 .4byte .LBE22 + 3805 0020 12000000 .4byte .LBB23 + 3806 0024 1E000000 .4byte .LBE23 + 3807 0028 00000000 .4byte 0 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 68 + + + 3808 002c 00000000 .4byte 0 + 3809 0030 00000000 .4byte .LFB7 + 3810 0034 2C000000 .4byte .LFE7 + 3811 0038 00000000 .4byte .LFB8 + 3812 003c 1A000000 .4byte .LFE8 + 3813 0040 00000000 .4byte .LFB9 + 3814 0044 2C000000 .4byte .LFE9 + 3815 0048 00000000 .4byte .LFB10 + 3816 004c 4A000000 .4byte .LFE10 + 3817 0050 00000000 .4byte .LFB11 + 3818 0054 3C000000 .4byte .LFE11 + 3819 0058 00000000 .4byte .LFB12 + 3820 005c 62000000 .4byte .LFE12 + 3821 0060 00000000 .4byte .LFB13 + 3822 0064 18000000 .4byte .LFE13 + 3823 0068 00000000 .4byte .LFB14 + 3824 006c 2E000000 .4byte .LFE14 + 3825 0070 00000000 .4byte .LFB15 + 3826 0074 42000000 .4byte .LFE15 + 3827 0078 00000000 .4byte .LFB16 + 3828 007c 46000000 .4byte .LFE16 + 3829 0080 00000000 .4byte .LFB17 + 3830 0084 64000000 .4byte .LFE17 + 3831 0088 00000000 .4byte 0 + 3832 008c 00000000 .4byte 0 + 3833 .section .debug_line,"",%progbits + 3834 .Ldebug_line0: + 3835 0000 4C030000 .section .debug_str,"MS",%progbits,1 + 3835 02005701 + 3835 00000201 + 3835 FB0E0D00 + 3835 01010101 + 3836 .LASF83: + 3837 0000 63684F51 .ascii "chOQInit\000" + 3837 496E6974 + 3837 00 + 3838 .LASF36: + 3839 0009 705F6D73 .ascii "p_msg\000" + 3839 6700 + 3840 .LASF92: + 3841 000f 71756575 .ascii "queue_insert\000" + 3841 655F696E + 3841 73657274 + 3841 00 + 3842 .LASF84: + 3843 001c 6F6E6679 .ascii "onfy\000" + 3843 00 + 3844 .LASF2: + 3845 0021 73697A65 .ascii "size_t\000" + 3845 5F7400 + 3846 .LASF59: + 3847 0028 7264796D .ascii "rdymsg\000" + 3847 736700 + 3848 .LASF78: + 3849 002f 63684951 .ascii "chIQInit\000" + 3849 496E6974 + 3849 00 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 69 + + + 3850 .LASF74: + 3851 0038 4F757470 .ascii "OutputQueue\000" + 3851 75745175 + 3851 65756500 + 3852 .LASF82: + 3853 0044 63684951 .ascii "chIQReadTimeout\000" + 3853 52656164 + 3853 54696D65 + 3853 6F757400 + 3854 .LASF12: + 3855 0054 6C6F6E67 .ascii "long long unsigned int\000" + 3855 206C6F6E + 3855 6720756E + 3855 7369676E + 3855 65642069 + 3856 .LASF60: + 3857 006b 65786974 .ascii "exitcode\000" + 3857 636F6465 + 3857 00 + 3858 .LASF25: + 3859 0074 705F7072 .ascii "p_prio\000" + 3859 696F00 + 3860 .LASF65: + 3861 007b 715F7761 .ascii "q_waiting\000" + 3861 6974696E + 3861 6700 + 3862 .LASF11: + 3863 0085 6C6F6E67 .ascii "long long int\000" + 3863 206C6F6E + 3863 6720696E + 3863 7400 + 3864 .LASF1: + 3865 0093 7369676E .ascii "signed char\000" + 3865 65642063 + 3865 68617200 + 3866 .LASF40: + 3867 009f 705F6D70 .ascii "p_mpool\000" + 3867 6F6F6C00 + 3868 .LASF13: + 3869 00a7 626F6F6C .ascii "bool_t\000" + 3869 5F7400 + 3870 .LASF56: + 3871 00ae 6D5F7175 .ascii "m_queue\000" + 3871 65756500 + 3872 .LASF94: + 3873 00b6 71776169 .ascii "qwait\000" + 3873 7400 + 3874 .LASF8: + 3875 00bc 6C6F6E67 .ascii "long int\000" + 3875 20696E74 + 3875 00 + 3876 .LASF15: + 3877 00c5 74737461 .ascii "tstate_t\000" + 3877 74655F74 + 3877 00 + 3878 .LASF87: + 3879 00ce 63684F51 .ascii "chOQGetI\000" + ARM GAS C:\cygwin\tmp\cchfGMii.s page 70 + + + 3879 47657449 + 3879 00 + 3880 .LASF67: + 3881 00d7 715F6275 .ascii "q_buffer\000" + 3881 66666572 + 3881 00 + 3882 .LASF69: + 3883 00e0 715F7772 .ascii "q_wrptr\000" + 3883 70747200 + 3884 .LASF27: + 3885 00e8 705F6E65 .ascii "p_newer\000" + 3885 77657200 + 3886 .LASF50: + 3887 00f0 725F6E65 .ascii "r_newer\000" + 3887 77657200 + 3888 .LASF43: + 3889 00f8 72656761 .ascii "regarm_t\000" + 3889 726D5F74 + 3889 00 + 3890 .LASF86: + 3891 0101 63684F51 .ascii "chOQPutTimeout\000" + 3891 50757454 + 3891 696D656F + 3891 757400 + 3892 .LASF80: + 3893 0110 63684951 .ascii "chIQPutI\000" + 3893 50757449 + 3893 00 + 3894 .LASF21: + 3895 0119 636E745F .ascii "cnt_t\000" + 3895 7400 + 3896 .LASF0: + 3897 011f 756E7369 .ascii "unsigned int\000" + 3897 676E6564 + 3897 20696E74 + 3897 00 + 3898 .LASF79: + 3899 012c 63684951 .ascii "chIQResetI\000" + 3899 52657365 + 3899 744900 + 3900 .LASF10: + 3901 0137 6C6F6E67 .ascii "long unsigned int\000" + 3901 20756E73 + 3901 69676E65 + 3901 6420696E + 3901 7400 + 3902 .LASF45: + 3903 0149 636F6E74 .ascii "context\000" + 3903 65787400 + 3904 .LASF76: + 3905 0151 73697A65 .ascii "size\000" + 3905 00 + 3906 .LASF6: + 3907 0156 73686F72 .ascii "short unsigned int\000" + 3907 7420756E + 3907 7369676E + 3907 65642069 + ARM GAS C:\cygwin\tmp\cchfGMii.s page 71 + + + 3907 6E7400 + 3908 .LASF18: + 3909 0169 6D73675F .ascii "msg_t\000" + 3909 7400 + 3910 .LASF14: + 3911 016f 746D6F64 .ascii "tmode_t\000" + 3911 655F7400 + 3912 .LASF42: + 3913 0177 54687265 .ascii "ThreadsList\000" + 3913 6164734C + 3913 69737400 + 3914 .LASF19: + 3915 0183 6576656E .ascii "eventmask_t\000" + 3915 746D6173 + 3915 6B5F7400 + 3916 .LASF73: + 3917 018f 496E7075 .ascii "InputQueue\000" + 3917 74517565 + 3917 756500 + 3918 .LASF55: + 3919 019a 4D757465 .ascii "Mutex\000" + 3919 7800 + 3920 .LASF64: + 3921 01a0 47656E65 .ascii "GenericQueue\000" + 3921 72696351 + 3921 75657565 + 3921 00 + 3922 .LASF88: + 3923 01ad 63684F51 .ascii "chOQWriteTimeout\000" + 3923 57726974 + 3923 6554696D + 3923 656F7574 + 3923 00 + 3924 .LASF46: + 3925 01be 73697A65 .ascii "sizetype\000" + 3925 74797065 + 3925 00 + 3926 .LASF66: + 3927 01c7 715F636F .ascii "q_counter\000" + 3927 756E7465 + 3927 7200 + 3928 .LASF28: + 3929 01d1 705F6F6C .ascii "p_older\000" + 3929 64657200 + 3930 .LASF91: + 3931 01d9 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 3931 73657273 + 3931 5C496D61 + 3931 6E6F6C5C + 3931 64657665 + 3932 0206 6C696361 .ascii "lications\\smartcities\000" + 3932 74696F6E + 3932 735C736D + 3932 61727463 + 3932 69746965 + 3933 .LASF41: + 3934 021c 54687265 .ascii "ThreadsQueue\000" + ARM GAS C:\cygwin\tmp\cchfGMii.s page 72 + + + 3934 61647351 + 3934 75657565 + 3934 00 + 3935 .LASF75: + 3936 0229 74696D65 .ascii "time\000" + 3936 00 + 3937 .LASF89: + 3938 022e 474E5520 .ascii "GNU C 4.7.2\000" + 3938 4320342E + 3938 372E3200 + 3939 .LASF53: + 3940 023a 725F6375 .ascii "r_current\000" + 3940 7272656E + 3940 7400 + 3941 .LASF51: + 3942 0244 725F6F6C .ascii "r_older\000" + 3942 64657200 + 3943 .LASF16: + 3944 024c 74726566 .ascii "trefs_t\000" + 3944 735F7400 + 3945 .LASF72: + 3946 0254 716E6F74 .ascii "qnotify_t\000" + 3946 6966795F + 3946 7400 + 3947 .LASF24: + 3948 025e 705F7072 .ascii "p_prev\000" + 3948 657600 + 3949 .LASF17: + 3950 0265 74707269 .ascii "tprio_t\000" + 3950 6F5F7400 + 3951 .LASF70: + 3952 026d 715F7264 .ascii "q_rdptr\000" + 3952 70747200 + 3953 .LASF7: + 3954 0275 696E7433 .ascii "int32_t\000" + 3954 325F7400 + 3955 .LASF4: + 3956 027d 756E7369 .ascii "unsigned char\000" + 3956 676E6564 + 3956 20636861 + 3956 7200 + 3957 .LASF38: + 3958 028b 705F6D74 .ascii "p_mtxlist\000" + 3958 786C6973 + 3958 7400 + 3959 .LASF5: + 3960 0295 73686F72 .ascii "short int\000" + 3960 7420696E + 3960 7400 + 3961 .LASF30: + 3962 029f 705F7374 .ascii "p_state\000" + 3962 61746500 + 3963 .LASF48: + 3964 02a7 725F7072 .ascii "r_prio\000" + 3964 696F00 + 3965 .LASF62: + 3966 02ae 65776D61 .ascii "ewmask\000" + ARM GAS C:\cygwin\tmp\cchfGMii.s page 73 + + + 3966 736B00 + 3967 .LASF23: + 3968 02b5 705F6E65 .ascii "p_next\000" + 3968 787400 + 3969 .LASF77: + 3970 02bc 696E6679 .ascii "infy\000" + 3970 00 + 3971 .LASF31: + 3972 02c1 705F666C .ascii "p_flags\000" + 3972 61677300 + 3973 .LASF22: + 3974 02c9 54687265 .ascii "Thread\000" + 3974 616400 + 3975 .LASF37: + 3976 02d0 705F6570 .ascii "p_epending\000" + 3976 656E6469 + 3976 6E6700 + 3977 .LASF9: + 3978 02db 75696E74 .ascii "uint32_t\000" + 3978 33325F74 + 3978 00 + 3979 .LASF47: + 3980 02e4 725F7175 .ascii "r_queue\000" + 3980 65756500 + 3981 .LASF97: + 3982 02ec 63685363 .ascii "chSchReadyI\000" + 3982 68526561 + 3982 64794900 + 3983 .LASF63: + 3984 02f8 63686172 .ascii "char\000" + 3984 00 + 3985 .LASF93: + 3986 02fd 6669666F .ascii "fifo_remove\000" + 3986 5F72656D + 3986 6F766500 + 3987 .LASF90: + 3988 0309 2E2E2F2E .ascii "../..//os/kernel/src/chqueues.c\000" + 3988 2E2F2F6F + 3988 732F6B65 + 3988 726E656C + 3988 2F737263 + 3989 .LASF58: + 3990 0329 6D5F6E65 .ascii "m_next\000" + 3990 787400 + 3991 .LASF20: + 3992 0330 73797374 .ascii "systime_t\000" + 3992 696D655F + 3992 7400 + 3993 .LASF39: + 3994 033a 705F7265 .ascii "p_realprio\000" + 3994 616C7072 + 3994 696F00 + 3995 .LASF85: + 3996 0345 63684F51 .ascii "chOQResetI\000" + 3996 52657365 + 3996 744900 + 3997 .LASF33: + ARM GAS C:\cygwin\tmp\cchfGMii.s page 74 + + + 3998 0350 705F7469 .ascii "p_time\000" + 3998 6D6500 + 3999 .LASF49: + 4000 0357 725F6374 .ascii "r_ctx\000" + 4000 7800 + 4001 .LASF44: + 4002 035d 696E7463 .ascii "intctx\000" + 4002 747800 + 4003 .LASF35: + 4004 0364 705F6D73 .ascii "p_msgqueue\000" + 4004 67717565 + 4004 756500 + 4005 .LASF68: + 4006 036f 715F746F .ascii "q_top\000" + 4006 7000 + 4007 .LASF32: + 4008 0375 705F7265 .ascii "p_refs\000" + 4008 667300 + 4009 .LASF54: + 4010 037c 52656164 .ascii "ReadyList\000" + 4010 794C6973 + 4010 7400 + 4011 .LASF71: + 4012 0386 715F6E6F .ascii "q_notify\000" + 4012 74696679 + 4012 00 + 4013 .LASF95: + 4014 038f 726C6973 .ascii "rlist\000" + 4014 7400 + 4015 .LASF3: + 4016 0395 75696E74 .ascii "uint8_t\000" + 4016 385F7400 + 4017 .LASF61: + 4018 039d 77746F62 .ascii "wtobjp\000" + 4018 6A7000 + 4019 .LASF29: + 4020 03a4 705F6E61 .ascii "p_name\000" + 4020 6D6500 + 4021 .LASF96: + 4022 03ab 63685363 .ascii "chSchGoSleepTimeoutS\000" + 4022 68476F53 + 4022 6C656570 + 4022 54696D65 + 4022 6F757453 + 4023 .LASF52: + 4024 03c0 725F7072 .ascii "r_preempt\000" + 4024 65656D70 + 4024 7400 + 4025 .LASF57: + 4026 03ca 6D5F6F77 .ascii "m_owner\000" + 4026 6E657200 + 4027 .LASF26: + 4028 03d2 705F6374 .ascii "p_ctx\000" + 4028 7800 + 4029 .LASF34: + 4030 03d8 705F7761 .ascii "p_waiting\000" + 4030 6974696E + ARM GAS C:\cygwin\tmp\cchfGMii.s page 75 + + + 4030 6700 + 4031 .LASF81: + 4032 03e2 63684951 .ascii "chIQGetTimeout\000" + 4032 47657454 + 4032 696D656F + 4032 757400 + 4033 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\cchfGMii.s page 76 + + +DEFINED SYMBOLS + *ABS*:00000000 chqueues.c +C:\cygwin\tmp\cchfGMii.s:19 .text.qwait:00000000 $t +C:\cygwin\tmp\cchfGMii.s:24 .text.qwait:00000000 qwait +C:\cygwin\tmp\cchfGMii.s:75 .text.qwait:00000028 $d +C:\cygwin\tmp\cchfGMii.s:80 .text.chIQInit:00000000 $t +C:\cygwin\tmp\cchfGMii.s:86 .text.chIQInit:00000000 chIQInit +C:\cygwin\tmp\cchfGMii.s:123 .text.chIQResetI:00000000 $t +C:\cygwin\tmp\cchfGMii.s:129 .text.chIQResetI:00000000 chIQResetI +C:\cygwin\tmp\cchfGMii.s:188 .text.chIQPutI:00000000 $t +C:\cygwin\tmp\cchfGMii.s:194 .text.chIQPutI:00000000 chIQPutI +C:\cygwin\tmp\cchfGMii.s:275 .text.chIQGetTimeout:00000000 $t +C:\cygwin\tmp\cchfGMii.s:281 .text.chIQGetTimeout:00000000 chIQGetTimeout +C:\cygwin\tmp\cchfGMii.s:365 .text.chIQReadTimeout:00000000 $t +C:\cygwin\tmp\cchfGMii.s:371 .text.chIQReadTimeout:00000000 chIQReadTimeout +C:\cygwin\tmp\cchfGMii.s:481 .text.chOQInit:00000000 $t +C:\cygwin\tmp\cchfGMii.s:487 .text.chOQInit:00000000 chOQInit +C:\cygwin\tmp\cchfGMii.s:521 .text.chOQResetI:00000000 $t +C:\cygwin\tmp\cchfGMii.s:527 .text.chOQResetI:00000000 chOQResetI +C:\cygwin\tmp\cchfGMii.s:588 .text.chOQPutTimeout:00000000 $t +C:\cygwin\tmp\cchfGMii.s:594 .text.chOQPutTimeout:00000000 chOQPutTimeout +C:\cygwin\tmp\cchfGMii.s:684 .text.chOQGetI:00000000 $t +C:\cygwin\tmp\cchfGMii.s:690 .text.chOQGetI:00000000 chOQGetI +C:\cygwin\tmp\cchfGMii.s:771 .text.chOQWriteTimeout:00000000 $t +C:\cygwin\tmp\cchfGMii.s:777 .text.chOQWriteTimeout:00000000 chOQWriteTimeout + .debug_frame:00000010 $d +C:\cygwin\tmp\cchfGMii.s:79 .text.qwait:0000002c $t + +UNDEFINED SYMBOLS +chSchGoSleepTimeoutS +rlist +chSchReadyI diff --git a/Project/applications/smartcities/build/lst/chregistry.lst b/Project/applications/smartcities/build/lst/chregistry.lst new file mode 100644 index 0000000..dde1bda --- /dev/null +++ b/Project/applications/smartcities/build/lst/chregistry.lst @@ -0,0 +1,1917 @@ +ARM GAS C:\cygwin\tmp\cctqk36j.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "chregistry.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text.chRegFirstThread,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .global chRegFirstThread + 22 .thumb + 23 .thumb_func + 24 .type chRegFirstThread, %function + 25 chRegFirstThread: + 26 .LFB7: + 27 .file 1 "../..//os/kernel/src/chregistry.c" + 28 .loc 1 113 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .loc 1 116 0 + 34 @ 116 "../..//os/kernel/src/chregistry.c" 1 + 35 0000 72B6 cpsid i + 36 @ 0 "" 2 + 37 .loc 1 117 0 + 38 .thumb + 39 0002 40F20003 movw r3, #:lower16:rlist + 40 0006 C0F20003 movt r3, #:upper16:rlist + 41 000a 1869 ldr r0, [r3, #16] + 42 .LVL0: + 43 .loc 1 119 0 + 44 000c 837F ldrb r3, [r0, #30] @ zero_extendqisi2 + 45 000e 0133 adds r3, r3, #1 + 46 0010 8377 strb r3, [r0, #30] + 47 .loc 1 121 0 + 48 @ 121 "../..//os/kernel/src/chregistry.c" 1 + 49 0012 62B6 cpsie i + 50 @ 0 "" 2 + 51 .loc 1 123 0 + 52 .thumb + 53 0014 7047 bx lr + 54 .cfi_endproc + 55 .LFE7: + 56 .size chRegFirstThread, .-chRegFirstThread + 57 0016 00BFAFF3 .section .text.chRegNextThread,"ax",%progbits + ARM GAS C:\cygwin\tmp\cctqk36j.s page 2 + + + 57 0080AFF3 + 57 0080 + 58 .align 2 + 59 .p2align 4,,15 + 60 .global chRegNextThread + 61 .thumb + 62 .thumb_func + 63 .type chRegNextThread, %function + 64 chRegNextThread: + 65 .LFB8: + 66 .loc 1 136 0 + 67 .cfi_startproc + 68 @ args = 0, pretend = 0, frame = 0 + 69 @ frame_needed = 0, uses_anonymous_args = 0 + 70 .LVL1: + 71 0000 10B5 push {r4, lr} + 72 .LCFI0: + 73 .cfi_def_cfa_offset 8 + 74 .cfi_offset 4, -8 + 75 .cfi_offset 14, -4 + 76 .loc 1 139 0 + 77 @ 139 "../..//os/kernel/src/chregistry.c" 1 + 78 0002 72B6 cpsid i + 79 @ 0 "" 2 + 80 .loc 1 141 0 + 81 .thumb + 82 0004 064B ldr r3, .L6 + 83 .loc 1 140 0 + 84 0006 0469 ldr r4, [r0, #16] + 85 .LVL2: + 86 .loc 1 141 0 + 87 0008 9C42 cmp r4, r3 + 88 000a 07D0 beq .L4 + 89 .loc 1 147 0 + 90 000c A37F ldrb r3, [r4, #30] @ zero_extendqisi2 + 91 000e 0133 adds r3, r3, #1 + 92 0010 A377 strb r3, [r4, #30] + 93 .LVL3: + 94 .L3: + 95 .loc 1 150 0 + 96 @ 150 "../..//os/kernel/src/chregistry.c" 1 + 97 0012 62B6 cpsie i + 98 @ 0 "" 2 + 99 .loc 1 152 0 + 100 .thumb + 101 0014 FFF7FEFF bl chThdRelease + 102 .LVL4: + 103 .loc 1 155 0 + 104 0018 2046 mov r0, r4 + 105 001a 10BD pop {r4, pc} + 106 .LVL5: + 107 .L4: + 108 .loc 1 142 0 + 109 001c 0024 movs r4, #0 + 110 .LVL6: + 111 001e F8E7 b .L3 + 112 .L7: + ARM GAS C:\cygwin\tmp\cctqk36j.s page 3 + + + 113 .align 2 + 114 .L6: + 115 0020 00000000 .word rlist + 116 .cfi_endproc + 117 .LFE8: + 118 .size chRegNextThread, .-chRegNextThread + 119 .global ch_debug + 120 0024 AFF30080 .section .rodata.ch_debug,"a",%progbits + 120 AFF30080 + 120 AFF30080 + 121 .align 2 + 122 .type ch_debug, %object + 123 .size ch_debug, 22 + 124 ch_debug: + 125 0000 6D61696E .ascii "main" + 126 0004 00 .byte 0 + 127 0005 16 .byte 22 + 128 0006 0411 .short 4356 + 129 0008 04 .byte 4 + 130 0009 04 .byte 4 + 131 000a 48 .byte 72 + 132 000b 08 .byte 8 + 133 000c 0C .byte 12 + 134 000d 10 .byte 16 + 135 000e 14 .byte 20 + 136 000f 18 .byte 24 + 137 0010 00 .byte 0 + 138 0011 1C .byte 28 + 139 0012 1D .byte 29 + 140 0013 1E .byte 30 + 141 0014 00 .byte 0 + 142 0015 20 .byte 32 + 143 0016 0000 .text + 144 .Letext0: + 145 .file 2 "c:\\yagarto\\bin\\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h" + 146 .file 3 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 147 .file 4 "../..//os/ports/GCC/ARMCMx/chtypes.h" + 148 .file 5 "../..//os/kernel/include/chlists.h" + 149 .file 6 "../..//os/kernel/include/chthreads.h" + 150 .file 7 "../..//os/ports/GCC/ARMCMx/chcore_v7m.h" + 151 .file 8 "../..//os/kernel/include/chschd.h" + 152 .file 9 "../..//os/kernel/include/chmtx.h" + 153 .file 10 "../..//os/kernel/include/chregistry.h" + 154 .file 11 "../..//os/kernel/include/chdynamic.h" + 155 .section .debug_info,"",%progbits + 156 .Ldebug_info0: + 157 0000 0C060000 .4byte 0x60c + 158 0004 0200 .2byte 0x2 + 159 0006 00000000 .4byte .Ldebug_abbrev0 + 160 000a 04 .byte 0x4 + 161 000b 01 .uleb128 0x1 + 162 000c 1B020000 .4byte .LASF87 + 163 0010 01 .byte 0x1 + 164 0011 70030000 .4byte .LASF88 + 165 0015 C3010000 .4byte .LASF89 + 166 0019 00000000 .4byte .Ldebug_ranges0+0 + 167 001d 00000000 .4byte 0 + ARM GAS C:\cygwin\tmp\cctqk36j.s page 4 + + + 168 0021 00000000 .4byte 0 + 169 0025 00000000 .4byte .Ldebug_line0 + 170 0029 02 .uleb128 0x2 + 171 002a 04 .byte 0x4 + 172 002b 05 .byte 0x5 + 173 002c 696E7400 .ascii "int\000" + 174 0030 03 .uleb128 0x3 + 175 0031 13000000 .4byte .LASF2 + 176 0035 02 .byte 0x2 + 177 0036 D5 .byte 0xd5 + 178 0037 3B000000 .4byte 0x3b + 179 003b 04 .uleb128 0x4 + 180 003c 04 .byte 0x4 + 181 003d 07 .byte 0x7 + 182 003e 17010000 .4byte .LASF0 + 183 0042 04 .uleb128 0x4 + 184 0043 01 .byte 0x1 + 185 0044 06 .byte 0x6 + 186 0045 8C000000 .4byte .LASF1 + 187 0049 03 .uleb128 0x3 + 188 004a 98030000 .4byte .LASF3 + 189 004e 03 .byte 0x3 + 190 004f 2A .byte 0x2a + 191 0050 54000000 .4byte 0x54 + 192 0054 04 .uleb128 0x4 + 193 0055 01 .byte 0x1 + 194 0056 08 .byte 0x8 + 195 0057 63020000 .4byte .LASF4 + 196 005b 04 .uleb128 0x4 + 197 005c 02 .byte 0x2 + 198 005d 05 .byte 0x5 + 199 005e 7B020000 .4byte .LASF5 + 200 0062 03 .uleb128 0x3 + 201 0063 E5000000 .4byte .LASF6 + 202 0067 03 .byte 0x3 + 203 0068 36 .byte 0x36 + 204 0069 6D000000 .4byte 0x6d + 205 006d 04 .uleb128 0x4 + 206 006e 02 .byte 0x2 + 207 006f 07 .byte 0x7 + 208 0070 47010000 .4byte .LASF7 + 209 0074 03 .uleb128 0x3 + 210 0075 5B020000 .4byte .LASF8 + 211 0079 03 .byte 0x3 + 212 007a 4F .byte 0x4f + 213 007b 7F000000 .4byte 0x7f + 214 007f 04 .uleb128 0x4 + 215 0080 04 .byte 0x4 + 216 0081 05 .byte 0x5 + 217 0082 D3000000 .4byte .LASF9 + 218 0086 03 .uleb128 0x3 + 219 0087 F1020000 .4byte .LASF10 + 220 008b 03 .byte 0x3 + 221 008c 50 .byte 0x50 + 222 008d 91000000 .4byte 0x91 + 223 0091 04 .uleb128 0x4 + 224 0092 04 .byte 0x4 + ARM GAS C:\cygwin\tmp\cctqk36j.s page 5 + + + 225 0093 07 .byte 0x7 + 226 0094 24010000 .4byte .LASF11 + 227 0098 04 .uleb128 0x4 + 228 0099 08 .byte 0x8 + 229 009a 05 .byte 0x5 + 230 009b 7E000000 .4byte .LASF12 + 231 009f 04 .uleb128 0x4 + 232 00a0 08 .byte 0x8 + 233 00a1 07 .byte 0x7 + 234 00a2 2B000000 .4byte .LASF13 + 235 00a6 03 .uleb128 0x3 + 236 00a7 60010000 .4byte .LASF14 + 237 00ab 04 .byte 0x4 + 238 00ac 2F .byte 0x2f + 239 00ad 49000000 .4byte 0x49 + 240 00b1 03 .uleb128 0x3 + 241 00b2 DC000000 .4byte .LASF15 + 242 00b6 04 .byte 0x4 + 243 00b7 30 .byte 0x30 + 244 00b8 49000000 .4byte 0x49 + 245 00bc 03 .uleb128 0x3 + 246 00bd 39020000 .4byte .LASF16 + 247 00c1 04 .byte 0x4 + 248 00c2 31 .byte 0x31 + 249 00c3 49000000 .4byte 0x49 + 250 00c7 03 .uleb128 0x3 + 251 00c8 53020000 .4byte .LASF17 + 252 00cc 04 .byte 0x4 + 253 00cd 32 .byte 0x32 + 254 00ce 86000000 .4byte 0x86 + 255 00d2 03 .uleb128 0x3 + 256 00d3 5A010000 .4byte .LASF18 + 257 00d7 04 .byte 0x4 + 258 00d8 33 .byte 0x33 + 259 00d9 74000000 .4byte 0x74 + 260 00dd 03 .uleb128 0x3 + 261 00de 74010000 .4byte .LASF19 + 262 00e2 04 .byte 0x4 + 263 00e3 35 .byte 0x35 + 264 00e4 86000000 .4byte 0x86 + 265 00e8 03 .uleb128 0x3 + 266 00e9 2A030000 .4byte .LASF20 + 267 00ed 04 .byte 0x4 + 268 00ee 36 .byte 0x36 + 269 00ef 86000000 .4byte 0x86 + 270 00f3 03 .uleb128 0x3 + 271 00f4 11010000 .4byte .LASF21 + 272 00f8 04 .byte 0x4 + 273 00f9 37 .byte 0x37 + 274 00fa 74000000 .4byte 0x74 + 275 00fe 03 .uleb128 0x3 + 276 00ff D2020000 .4byte .LASF22 + 277 0103 05 .byte 0x5 + 278 0104 2A .byte 0x2a + 279 0105 09010000 .4byte 0x109 + 280 0109 05 .uleb128 0x5 + 281 010a D2020000 .4byte .LASF22 + ARM GAS C:\cygwin\tmp\cctqk36j.s page 6 + + + 282 010e 48 .byte 0x48 + 283 010f 06 .byte 0x6 + 284 0110 5E .byte 0x5e + 285 0111 20020000 .4byte 0x220 + 286 0115 06 .uleb128 0x6 + 287 0116 A7020000 .4byte .LASF23 + 288 011a 06 .byte 0x6 + 289 011b 5F .byte 0x5f + 290 011c 45020000 .4byte 0x245 + 291 0120 02 .byte 0x2 + 292 0121 23 .byte 0x23 + 293 0122 00 .uleb128 0 + 294 0123 06 .uleb128 0x6 + 295 0124 4C020000 .4byte .LASF24 + 296 0128 06 .byte 0x6 + 297 0129 61 .byte 0x61 + 298 012a 45020000 .4byte 0x245 + 299 012e 02 .byte 0x2 + 300 012f 23 .byte 0x23 + 301 0130 04 .uleb128 0x4 + 302 0131 06 .uleb128 0x6 + 303 0132 6A000000 .4byte .LASF25 + 304 0136 06 .byte 0x6 + 305 0137 63 .byte 0x63 + 306 0138 C7000000 .4byte 0xc7 + 307 013c 02 .byte 0x2 + 308 013d 23 .byte 0x23 + 309 013e 08 .uleb128 0x8 + 310 013f 06 .uleb128 0x6 + 311 0140 CB030000 .4byte .LASF26 + 312 0144 06 .byte 0x6 + 313 0145 64 .byte 0x64 + 314 0146 12030000 .4byte 0x312 + 315 014a 02 .byte 0x2 + 316 014b 23 .byte 0x23 + 317 014c 0C .uleb128 0xc + 318 014d 06 .uleb128 0x6 + 319 014e F8000000 .4byte .LASF27 + 320 0152 06 .byte 0x6 + 321 0153 66 .byte 0x66 + 322 0154 45020000 .4byte 0x245 + 323 0158 02 .byte 0x2 + 324 0159 23 .byte 0x23 + 325 015a 10 .uleb128 0x10 + 326 015b 06 .uleb128 0x6 + 327 015c BB010000 .4byte .LASF28 + 328 0160 06 .byte 0x6 + 329 0161 67 .byte 0x67 + 330 0162 45020000 .4byte 0x245 + 331 0166 02 .byte 0x2 + 332 0167 23 .byte 0x23 + 333 0168 14 .uleb128 0x14 + 334 0169 06 .uleb128 0x6 + 335 016a A7030000 .4byte .LASF29 + 336 016e 06 .byte 0x6 + 337 016f 6E .byte 0x6e + 338 0170 34040000 .4byte 0x434 + ARM GAS C:\cygwin\tmp\cctqk36j.s page 7 + + + 339 0174 02 .byte 0x2 + 340 0175 23 .byte 0x23 + 341 0176 18 .uleb128 0x18 + 342 0177 06 .uleb128 0x6 + 343 0178 85020000 .4byte .LASF30 + 344 017c 06 .byte 0x6 + 345 017d 79 .byte 0x79 + 346 017e B1000000 .4byte 0xb1 + 347 0182 02 .byte 0x2 + 348 0183 23 .byte 0x23 + 349 0184 1C .uleb128 0x1c + 350 0185 06 .uleb128 0x6 + 351 0186 BD020000 .4byte .LASF31 + 352 018a 06 .byte 0x6 + 353 018b 7D .byte 0x7d + 354 018c A6000000 .4byte 0xa6 + 355 0190 02 .byte 0x2 + 356 0191 23 .byte 0x23 + 357 0192 1D .uleb128 0x1d + 358 0193 06 .uleb128 0x6 + 359 0194 69030000 .4byte .LASF32 + 360 0198 06 .byte 0x6 + 361 0199 82 .byte 0x82 + 362 019a BC000000 .4byte 0xbc + 363 019e 02 .byte 0x2 + 364 019f 23 .byte 0x23 + 365 01a0 1E .uleb128 0x1e + 366 01a1 06 .uleb128 0x6 + 367 01a2 3F030000 .4byte .LASF33 + 368 01a6 06 .byte 0x6 + 369 01a7 89 .byte 0x89 + 370 01a8 3C030000 .4byte 0x33c + 371 01ac 02 .byte 0x2 + 372 01ad 23 .byte 0x23 + 373 01ae 20 .uleb128 0x20 + 374 01af 07 .uleb128 0x7 + 375 01b0 705F7500 .ascii "p_u\000" + 376 01b4 06 .byte 0x6 + 377 01b5 AE .byte 0xae + 378 01b6 FF030000 .4byte 0x3ff + 379 01ba 02 .byte 0x2 + 380 01bb 23 .byte 0x23 + 381 01bc 24 .uleb128 0x24 + 382 01bd 06 .uleb128 0x6 + 383 01be D1030000 .4byte .LASF34 + 384 01c2 06 .byte 0x6 + 385 01c3 B3 .byte 0xb3 + 386 01c4 6D020000 .4byte 0x26d + 387 01c8 02 .byte 0x2 + 388 01c9 23 .byte 0x23 + 389 01ca 28 .uleb128 0x28 + 390 01cb 06 .uleb128 0x6 + 391 01cc 53030000 .4byte .LASF35 + 392 01d0 06 .byte 0x6 + 393 01d1 B9 .byte 0xb9 + 394 01d2 4B020000 .4byte 0x24b + 395 01d6 02 .byte 0x2 + ARM GAS C:\cygwin\tmp\cctqk36j.s page 8 + + + 396 01d7 23 .byte 0x23 + 397 01d8 2C .uleb128 0x2c + 398 01d9 06 .uleb128 0x6 + 399 01da 0D000000 .4byte .LASF36 + 400 01de 06 .byte 0x6 + 401 01df BD .byte 0xbd + 402 01e0 D2000000 .4byte 0xd2 + 403 01e4 02 .byte 0x2 + 404 01e5 23 .byte 0x23 + 405 01e6 34 .uleb128 0x34 + 406 01e7 06 .uleb128 0x6 + 407 01e8 E6020000 .4byte .LASF37 + 408 01ec 06 .byte 0x6 + 409 01ed C3 .byte 0xc3 + 410 01ee DD000000 .4byte 0xdd + 411 01f2 02 .byte 0x2 + 412 01f3 23 .byte 0x23 + 413 01f4 38 .uleb128 0x38 + 414 01f5 06 .uleb128 0x6 + 415 01f6 71020000 .4byte .LASF38 + 416 01fa 06 .byte 0x6 + 417 01fb CA .byte 0xca + 418 01fc 46040000 .4byte 0x446 + 419 0200 02 .byte 0x2 + 420 0201 23 .byte 0x23 + 421 0202 3C .uleb128 0x3c + 422 0203 06 .uleb128 0x6 + 423 0204 34030000 .4byte .LASF39 + 424 0208 06 .byte 0x6 + 425 0209 CE .byte 0xce + 426 020a C7000000 .4byte 0xc7 + 427 020e 02 .byte 0x2 + 428 020f 23 .byte 0x23 + 429 0210 40 .uleb128 0x40 + 430 0211 06 .uleb128 0x6 + 431 0212 B5000000 .4byte .LASF40 + 432 0216 06 .byte 0x6 + 433 0217 D4 .byte 0xd4 + 434 0218 83020000 .4byte 0x283 + 435 021c 02 .byte 0x2 + 436 021d 23 .byte 0x23 + 437 021e 44 .uleb128 0x44 + 438 021f 00 .byte 0 + 439 0220 08 .uleb128 0x8 + 440 0221 08 .byte 0x8 + 441 0222 05 .byte 0x5 + 442 0223 61 .byte 0x61 + 443 0224 45020000 .4byte 0x245 + 444 0228 06 .uleb128 0x6 + 445 0229 A7020000 .4byte .LASF23 + 446 022d 05 .byte 0x5 + 447 022e 62 .byte 0x62 + 448 022f 45020000 .4byte 0x245 + 449 0233 02 .byte 0x2 + 450 0234 23 .byte 0x23 + 451 0235 00 .uleb128 0 + 452 0236 06 .uleb128 0x6 + ARM GAS C:\cygwin\tmp\cctqk36j.s page 9 + + + 453 0237 4C020000 .4byte .LASF24 + 454 023b 05 .byte 0x5 + 455 023c 64 .byte 0x64 + 456 023d 45020000 .4byte 0x245 + 457 0241 02 .byte 0x2 + 458 0242 23 .byte 0x23 + 459 0243 04 .uleb128 0x4 + 460 0244 00 .byte 0 + 461 0245 09 .uleb128 0x9 + 462 0246 04 .byte 0x4 + 463 0247 FE000000 .4byte 0xfe + 464 024b 03 .uleb128 0x3 + 465 024c 06020000 .4byte .LASF41 + 466 0250 05 .byte 0x5 + 467 0251 66 .byte 0x66 + 468 0252 20020000 .4byte 0x220 + 469 0256 08 .uleb128 0x8 + 470 0257 04 .byte 0x4 + 471 0258 05 .byte 0x5 + 472 0259 6B .byte 0x6b + 473 025a 6D020000 .4byte 0x26d + 474 025e 06 .uleb128 0x6 + 475 025f A7020000 .4byte .LASF23 + 476 0263 05 .byte 0x5 + 477 0264 6D .byte 0x6d + 478 0265 45020000 .4byte 0x245 + 479 0269 02 .byte 0x2 + 480 026a 23 .byte 0x23 + 481 026b 00 .uleb128 0 + 482 026c 00 .byte 0 + 483 026d 03 .uleb128 0x3 + 484 026e 68010000 .4byte .LASF42 + 485 0272 05 .byte 0x5 + 486 0273 70 .byte 0x70 + 487 0274 56020000 .4byte 0x256 + 488 0278 03 .uleb128 0x3 + 489 0279 08010000 .4byte .LASF43 + 490 027d 07 .byte 0x7 + 491 027e D7 .byte 0xd7 + 492 027f 83020000 .4byte 0x283 + 493 0283 0A .uleb128 0xa + 494 0284 04 .byte 0x4 + 495 0285 05 .uleb128 0x5 + 496 0286 4C030000 .4byte .LASF44 + 497 028a 24 .byte 0x24 + 498 028b 07 .byte 0x7 + 499 028c FE .byte 0xfe + 500 028d 12030000 .4byte 0x312 + 501 0291 0B .uleb128 0xb + 502 0292 723400 .ascii "r4\000" + 503 0295 07 .byte 0x7 + 504 0296 1101 .2byte 0x111 + 505 0298 78020000 .4byte 0x278 + 506 029c 02 .byte 0x2 + 507 029d 23 .byte 0x23 + 508 029e 00 .uleb128 0 + 509 029f 0B .uleb128 0xb + ARM GAS C:\cygwin\tmp\cctqk36j.s page 10 + + + 510 02a0 723500 .ascii "r5\000" + 511 02a3 07 .byte 0x7 + 512 02a4 1201 .2byte 0x112 + 513 02a6 78020000 .4byte 0x278 + 514 02aa 02 .byte 0x2 + 515 02ab 23 .byte 0x23 + 516 02ac 04 .uleb128 0x4 + 517 02ad 0B .uleb128 0xb + 518 02ae 723600 .ascii "r6\000" + 519 02b1 07 .byte 0x7 + 520 02b2 1301 .2byte 0x113 + 521 02b4 78020000 .4byte 0x278 + 522 02b8 02 .byte 0x2 + 523 02b9 23 .byte 0x23 + 524 02ba 08 .uleb128 0x8 + 525 02bb 0B .uleb128 0xb + 526 02bc 723700 .ascii "r7\000" + 527 02bf 07 .byte 0x7 + 528 02c0 1401 .2byte 0x114 + 529 02c2 78020000 .4byte 0x278 + 530 02c6 02 .byte 0x2 + 531 02c7 23 .byte 0x23 + 532 02c8 0C .uleb128 0xc + 533 02c9 0B .uleb128 0xb + 534 02ca 723800 .ascii "r8\000" + 535 02cd 07 .byte 0x7 + 536 02ce 1501 .2byte 0x115 + 537 02d0 78020000 .4byte 0x278 + 538 02d4 02 .byte 0x2 + 539 02d5 23 .byte 0x23 + 540 02d6 10 .uleb128 0x10 + 541 02d7 0B .uleb128 0xb + 542 02d8 723900 .ascii "r9\000" + 543 02db 07 .byte 0x7 + 544 02dc 1601 .2byte 0x116 + 545 02de 78020000 .4byte 0x278 + 546 02e2 02 .byte 0x2 + 547 02e3 23 .byte 0x23 + 548 02e4 14 .uleb128 0x14 + 549 02e5 0B .uleb128 0xb + 550 02e6 72313000 .ascii "r10\000" + 551 02ea 07 .byte 0x7 + 552 02eb 1701 .2byte 0x117 + 553 02ed 78020000 .4byte 0x278 + 554 02f1 02 .byte 0x2 + 555 02f2 23 .byte 0x23 + 556 02f3 18 .uleb128 0x18 + 557 02f4 0B .uleb128 0xb + 558 02f5 72313100 .ascii "r11\000" + 559 02f9 07 .byte 0x7 + 560 02fa 1801 .2byte 0x118 + 561 02fc 78020000 .4byte 0x278 + 562 0300 02 .byte 0x2 + 563 0301 23 .byte 0x23 + 564 0302 1C .uleb128 0x1c + 565 0303 0B .uleb128 0xb + 566 0304 6C7200 .ascii "lr\000" + ARM GAS C:\cygwin\tmp\cctqk36j.s page 11 + + + 567 0307 07 .byte 0x7 + 568 0308 1901 .2byte 0x119 + 569 030a 78020000 .4byte 0x278 + 570 030e 02 .byte 0x2 + 571 030f 23 .byte 0x23 + 572 0310 20 .uleb128 0x20 + 573 0311 00 .byte 0 + 574 0312 0C .uleb128 0xc + 575 0313 3F010000 .4byte .LASF45 + 576 0317 04 .byte 0x4 + 577 0318 07 .byte 0x7 + 578 0319 2301 .2byte 0x123 + 579 031b 2F030000 .4byte 0x32f + 580 031f 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.byte 0x23 + 686 03de 08 .uleb128 0x8 + 687 03df 06 .uleb128 0x6 + 688 03e0 23030000 .4byte .LASF58 + 689 03e4 09 .byte 0x9 + 690 03e5 31 .byte 0x31 + 691 03e6 EE030000 .4byte 0x3ee + 692 03ea 02 .byte 0x2 + 693 03eb 23 .byte 0x23 + 694 03ec 0C .uleb128 0xc + 695 03ed 00 .byte 0 + 696 03ee 09 .uleb128 0x9 + 697 03ef 04 .byte 0x4 + 698 03f0 B7030000 .4byte 0x3b7 + 699 03f4 03 .uleb128 0x3 + 700 03f5 80010000 .4byte .LASF55 + 701 03f9 09 .byte 0x9 + 702 03fa 33 .byte 0x33 + 703 03fb B7030000 .4byte 0x3b7 + 704 03ff 0E .uleb128 0xe + 705 0400 04 .byte 0x4 + 706 0401 06 .byte 0x6 + 707 0402 90 .byte 0x90 + 708 0403 34040000 .4byte 0x434 + 709 0407 0F .uleb128 0xf + 710 0408 1A000000 .4byte .LASF59 + 711 040c 06 .byte 0x6 + 712 040d 97 .byte 0x97 + 713 040e D2000000 .4byte 0xd2 + 714 0412 0F .uleb128 0xf + 715 0413 50000000 .4byte .LASF60 + 716 0417 06 .byte 0x6 + 717 0418 9E .byte 0x9e + 718 0419 D2000000 .4byte 0xd2 + 719 041d 0F .uleb128 0xf + 720 041e A0030000 .4byte .LASF61 + 721 0422 06 .byte 0x6 + 722 0423 A5 .byte 0xa5 + 723 0424 83020000 .4byte 0x283 + 724 0428 0F .uleb128 0xf + 725 0429 A0020000 .4byte .LASF62 + 726 042d 06 .byte 0x6 + 727 042e AC .byte 0xac + 728 042f DD000000 .4byte 0xdd + 729 0433 00 .byte 0 + 730 0434 09 .uleb128 0x9 + 731 0435 04 .byte 0x4 + 732 0436 3A040000 .4byte 0x43a + 733 043a 10 .uleb128 0x10 + 734 043b 3F040000 .4byte 0x43f + 735 043f 04 .uleb128 0x4 + 736 0440 01 .byte 0x1 + 737 0441 08 .byte 0x8 + ARM GAS C:\cygwin\tmp\cctqk36j.s page 14 + + + 738 0442 0E030000 .4byte .LASF63 + 739 0446 09 .uleb128 0x9 + 740 0447 04 .byte 0x4 + 741 0448 F4030000 .4byte 0x3f4 + 742 044c 08 .uleb128 0x8 + 743 044d 16 .byte 0x16 + 744 044e 0A .byte 0xa + 745 044f 2C .byte 0x2c + 746 0450 51050000 .4byte 0x551 + 747 0454 06 .uleb128 0x6 + 748 0455 C5000000 .4byte .LASF64 + 749 0459 0A .byte 0xa + 750 045a 2D .byte 0x2d + 751 045b 51050000 .4byte 0x551 + 752 045f 02 .byte 0x2 + 753 0460 23 .byte 0x23 + 754 0461 00 .uleb128 0 + 755 0462 06 .uleb128 0x6 + 756 0463 86010000 .4byte .LASF65 + 757 0467 0A .byte 0xa + 758 0468 2E .byte 0x2e + 759 0469 49000000 .4byte 0x49 + 760 046d 02 .byte 0x2 + 761 046e 23 .byte 0x23 + 762 046f 04 .uleb128 0x4 + 763 0470 06 .uleb128 0x6 + 764 0471 13020000 .4byte .LASF66 + 765 0475 0A .byte 0xa + 766 0476 2F .byte 0x2f + 767 0477 49000000 .4byte 0x49 + 768 047b 02 .byte 0x2 + 769 047c 23 .byte 0x23 + 770 047d 05 .uleb128 0x5 + 771 047e 06 .uleb128 0x6 + 772 047f AE030000 .4byte .LASF67 + 773 0483 0A .byte 0xa + 774 0484 30 .byte 0x30 + 775 0485 62000000 .4byte 0x62 + 776 0489 02 .byte 0x2 + 777 048a 23 .byte 0x23 + 778 048b 06 .uleb128 0x6 + 779 048c 06 .uleb128 0x6 + 780 048d 41020000 .4byte .LASF68 + 781 0491 0A .byte 0xa + 782 0492 31 .byte 0x31 + 783 0493 49000000 .4byte 0x49 + 784 0497 02 .byte 0x2 + 785 0498 23 .byte 0x23 + 786 0499 08 .uleb128 0x8 + 787 049a 06 .uleb128 0x6 + 788 049b A3010000 .4byte .LASF69 + 789 049f 0A .byte 0xa + 790 04a0 32 .byte 0x32 + 791 04a1 49000000 .4byte 0x49 + 792 04a5 02 .byte 0x2 + 793 04a6 23 .byte 0x23 + 794 04a7 09 .uleb128 0x9 + ARM GAS C:\cygwin\tmp\cctqk36j.s page 15 + + + 795 04a8 06 .uleb128 0x6 + 796 04a9 42000000 .4byte .LASF70 + 797 04ad 0A .byte 0xa + 798 04ae 33 .byte 0x33 + 799 04af 49000000 .4byte 0x49 + 800 04b3 02 .byte 0x2 + 801 04b4 23 .byte 0x23 + 802 04b5 0A .uleb128 0xa + 803 04b6 06 .uleb128 0x6 + 804 04b7 FA020000 .4byte .LASF71 + 805 04bb 0A .byte 0xa + 806 04bc 34 .byte 0x34 + 807 04bd 49000000 .4byte 0x49 + 808 04c1 02 .byte 0x2 + 809 04c2 23 .byte 0x23 + 810 04c3 0B .uleb128 0xb + 811 04c4 06 .uleb128 0x6 + 812 04c5 5E030000 .4byte .LASF72 + 813 04c9 0A .byte 0xa + 814 04ca 35 .byte 0x35 + 815 04cb 49000000 .4byte 0x49 + 816 04cf 02 .byte 0x2 + 817 04d0 23 .byte 0x23 + 818 04d1 0C .uleb128 0xc + 819 04d2 06 .uleb128 0x6 + 820 04d3 D9020000 .4byte .LASF73 + 821 04d7 0A .byte 0xa + 822 04d8 36 .byte 0x36 + 823 04d9 49000000 .4byte 0x49 + 824 04dd 02 .byte 0x2 + 825 04de 23 .byte 0x23 + 826 04df 0D .uleb128 0xd + 827 04e0 06 .uleb128 0x6 + 828 04e1 00000000 .4byte .LASF74 + 829 04e5 0A .byte 0xa + 830 04e6 37 .byte 0x37 + 831 04e7 49000000 .4byte 0x49 + 832 04eb 02 .byte 0x2 + 833 04ec 23 .byte 0x23 + 834 04ed 0E .uleb128 0xe + 835 04ee 06 .uleb128 0x6 + 836 04ef AF010000 .4byte .LASF75 + 837 04f3 0A .byte 0xa + 838 04f4 38 .byte 0x38 + 839 04f5 49000000 .4byte 0x49 + 840 04f9 02 .byte 0x2 + 841 04fa 23 .byte 0x23 + 842 04fb 0F .uleb128 0xf + 843 04fc 06 .uleb128 0x6 + 844 04fd 98000000 .4byte .LASF76 + 845 0501 0A .byte 0xa + 846 0502 39 .byte 0x39 + 847 0503 49000000 .4byte 0x49 + 848 0507 02 .byte 0x2 + 849 0508 23 .byte 0x23 + 850 0509 10 .uleb128 0x10 + 851 050a 06 .uleb128 0x6 + ARM GAS C:\cygwin\tmp\cctqk36j.s page 16 + + + 852 050b 71000000 .4byte .LASF77 + 853 050f 0A .byte 0xa + 854 0510 3B .byte 0x3b + 855 0511 49000000 .4byte 0x49 + 856 0515 02 .byte 0x2 + 857 0516 23 .byte 0x23 + 858 0517 11 .uleb128 0x11 + 859 0518 06 .uleb128 0x6 + 860 0519 A8000000 .4byte .LASF78 + 861 051d 0A .byte 0xa + 862 051e 3C .byte 0x3c + 863 051f 49000000 .4byte 0x49 + 864 0523 02 .byte 0x2 + 865 0524 23 .byte 0x23 + 866 0525 12 .uleb128 0x12 + 867 0526 06 .uleb128 0x6 + 868 0527 8E010000 .4byte .LASF79 + 869 052b 0A .byte 0xa + 870 052c 3D .byte 0x3d + 871 052d 49000000 .4byte 0x49 + 872 0531 02 .byte 0x2 + 873 0532 23 .byte 0x23 + 874 0533 13 .uleb128 0x13 + 875 0534 06 .uleb128 0x6 + 876 0535 AE020000 .4byte .LASF80 + 877 0539 0A .byte 0xa + 878 053a 3E .byte 0x3e + 879 053b 49000000 .4byte 0x49 + 880 053f 02 .byte 0x2 + 881 0540 23 .byte 0x23 + 882 0541 14 .uleb128 0x14 + 883 0542 06 .uleb128 0x6 + 884 0543 8D020000 .4byte .LASF81 + 885 0547 0A .byte 0xa + 886 0548 40 .byte 0x40 + 887 0549 49000000 .4byte 0x49 + 888 054d 02 .byte 0x2 + 889 054e 23 .byte 0x23 + 890 054f 15 .uleb128 0x15 + 891 0550 00 .byte 0 + 892 0551 11 .uleb128 0x11 + 893 0552 3F040000 .4byte 0x43f + 894 0556 61050000 .4byte 0x561 + 895 055a 12 .uleb128 0x12 + 896 055b 35030000 .4byte 0x335 + 897 055f 03 .byte 0x3 + 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.4byte 0x245 + 933 05a3 00000000 .4byte .LFB8 + 934 05a7 24000000 .4byte .LFE8 + 935 05ab 00000000 .4byte .LLST0 + 936 05af 01 .byte 0x1 + 937 05b0 DB050000 .4byte 0x5db + 938 05b4 16 .uleb128 0x16 + 939 05b5 747000 .ascii "tp\000" + 940 05b8 01 .byte 0x1 + 941 05b9 88 .byte 0x88 + 942 05ba 45020000 .4byte 0x245 + 943 05be 20000000 .4byte .LLST1 + 944 05c2 17 .uleb128 0x17 + 945 05c3 6E747000 .ascii "ntp\000" + 946 05c7 01 .byte 0x1 + 947 05c8 89 .byte 0x89 + 948 05c9 45020000 .4byte 0x245 + 949 05cd 4C000000 .4byte .LLST2 + 950 05d1 18 .uleb128 0x18 + 951 05d2 18000000 .4byte .LVL4 + 952 05d6 FF050000 .4byte 0x5ff + 953 05da 00 .byte 0 + 954 05db 19 .uleb128 0x19 + 955 05dc 92030000 .4byte .LASF85 + 956 05e0 08 .byte 0x8 + 957 05e1 72 .byte 0x72 + 958 05e2 AC030000 .4byte 0x3ac + 959 05e6 01 .byte 0x1 + 960 05e7 01 .byte 0x1 + 961 05e8 1A .uleb128 0x1a + 962 05e9 36010000 .4byte .LASF86 + 963 05ed 01 .byte 0x1 + 964 05ee 42 .byte 0x42 + 965 05ef FA050000 .4byte 0x5fa + ARM GAS C:\cygwin\tmp\cctqk36j.s page 18 + + + 966 05f3 01 .byte 0x1 + 967 05f4 05 .byte 0x5 + 968 05f5 03 .byte 0x3 + 969 05f6 00000000 .4byte ch_debug + 970 05fa 10 .uleb128 0x10 + 971 05fb 61050000 .4byte 0x561 + 972 05ff 1B .uleb128 0x1b + 973 0600 01 .byte 0x1 + 974 0601 C5020000 .4byte .LASF90 + 975 0605 0B .byte 0xb + 976 0606 3A .byte 0x3a + 977 0607 01 .byte 0x1 + 978 0608 01 .byte 0x1 + 979 0609 1C .uleb128 0x1c + 980 060a 45020000 .4byte 0x245 + 981 060e 00 .byte 0 + 982 060f 00 .byte 0 + 983 .section .debug_abbrev,"",%progbits + 984 .Ldebug_abbrev0: + 985 0000 01 .uleb128 0x1 + 986 0001 11 .uleb128 0x11 + 987 0002 01 .byte 0x1 + 988 0003 25 .uleb128 0x25 + 989 0004 0E .uleb128 0xe + 990 0005 13 .uleb128 0x13 + 991 0006 0B .uleb128 0xb + 992 0007 03 .uleb128 0x3 + 993 0008 0E .uleb128 0xe + 994 0009 1B .uleb128 0x1b + 995 000a 0E .uleb128 0xe + 996 000b 55 .uleb128 0x55 + 997 000c 06 .uleb128 0x6 + 998 000d 11 .uleb128 0x11 + 999 000e 01 .uleb128 0x1 + 1000 000f 52 .uleb128 0x52 + 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+ 1073 0058 00 .byte 0 + 1074 0059 03 .uleb128 0x3 + 1075 005a 08 .uleb128 0x8 + 1076 005b 3A .uleb128 0x3a + 1077 005c 0B .uleb128 0xb + 1078 005d 3B .uleb128 0x3b + 1079 005e 0B .uleb128 0xb + ARM GAS C:\cygwin\tmp\cctqk36j.s page 20 + + + 1080 005f 49 .uleb128 0x49 + 1081 0060 13 .uleb128 0x13 + 1082 0061 38 .uleb128 0x38 + 1083 0062 0A .uleb128 0xa + 1084 0063 00 .byte 0 + 1085 0064 00 .byte 0 + 1086 0065 08 .uleb128 0x8 + 1087 0066 13 .uleb128 0x13 + 1088 0067 01 .byte 0x1 + 1089 0068 0B .uleb128 0xb + 1090 0069 0B .uleb128 0xb + 1091 006a 3A .uleb128 0x3a + 1092 006b 0B .uleb128 0xb + 1093 006c 3B .uleb128 0x3b + 1094 006d 0B .uleb128 0xb + 1095 006e 01 .uleb128 0x1 + 1096 006f 13 .uleb128 0x13 + 1097 0070 00 .byte 0 + 1098 0071 00 .byte 0 + 1099 0072 09 .uleb128 0x9 + 1100 0073 0F .uleb128 0xf + 1101 0074 00 .byte 0 + 1102 0075 0B .uleb128 0xb + 1103 0076 0B .uleb128 0xb + 1104 0077 49 .uleb128 0x49 + 1105 0078 13 .uleb128 0x13 + 1106 0079 00 .byte 0 + 1107 007a 00 .byte 0 + 1108 007b 0A .uleb128 0xa + 1109 007c 0F .uleb128 0xf + 1110 007d 00 .byte 0 + 1111 007e 0B .uleb128 0xb + 1112 007f 0B .uleb128 0xb + 1113 0080 00 .byte 0 + 1114 0081 00 .byte 0 + 1115 0082 0B .uleb128 0xb + 1116 0083 0D .uleb128 0xd + 1117 0084 00 .byte 0 + 1118 0085 03 .uleb128 0x3 + 1119 0086 08 .uleb128 0x8 + 1120 0087 3A .uleb128 0x3a + 1121 0088 0B .uleb128 0xb + 1122 0089 3B .uleb128 0x3b + 1123 008a 05 .uleb128 0x5 + 1124 008b 49 .uleb128 0x49 + 1125 008c 13 .uleb128 0x13 + 1126 008d 38 .uleb128 0x38 + 1127 008e 0A .uleb128 0xa + 1128 008f 00 .byte 0 + 1129 0090 00 .byte 0 + 1130 0091 0C .uleb128 0xc + 1131 0092 13 .uleb128 0x13 + 1132 0093 01 .byte 0x1 + 1133 0094 03 .uleb128 0x3 + 1134 0095 0E .uleb128 0xe + 1135 0096 0B .uleb128 0xb + 1136 0097 0B .uleb128 0xb + ARM GAS C:\cygwin\tmp\cctqk36j.s page 21 + + + 1137 0098 3A .uleb128 0x3a + 1138 0099 0B .uleb128 0xb + 1139 009a 3B .uleb128 0x3b + 1140 009b 05 .uleb128 0x5 + 1141 009c 01 .uleb128 0x1 + 1142 009d 13 .uleb128 0x13 + 1143 009e 00 .byte 0 + 1144 009f 00 .byte 0 + 1145 00a0 0D .uleb128 0xd + 1146 00a1 35 .uleb128 0x35 + 1147 00a2 00 .byte 0 + 1148 00a3 49 .uleb128 0x49 + 1149 00a4 13 .uleb128 0x13 + 1150 00a5 00 .byte 0 + 1151 00a6 00 .byte 0 + 1152 00a7 0E .uleb128 0xe + 1153 00a8 17 .uleb128 0x17 + 1154 00a9 01 .byte 0x1 + 1155 00aa 0B .uleb128 0xb + 1156 00ab 0B .uleb128 0xb + 1157 00ac 3A .uleb128 0x3a + 1158 00ad 0B .uleb128 0xb + 1159 00ae 3B .uleb128 0x3b + 1160 00af 0B .uleb128 0xb + 1161 00b0 01 .uleb128 0x1 + 1162 00b1 13 .uleb128 0x13 + 1163 00b2 00 .byte 0 + 1164 00b3 00 .byte 0 + 1165 00b4 0F .uleb128 0xf + 1166 00b5 0D .uleb128 0xd + 1167 00b6 00 .byte 0 + 1168 00b7 03 .uleb128 0x3 + 1169 00b8 0E .uleb128 0xe + 1170 00b9 3A .uleb128 0x3a + 1171 00ba 0B .uleb128 0xb + 1172 00bb 3B .uleb128 0x3b + 1173 00bc 0B .uleb128 0xb + 1174 00bd 49 .uleb128 0x49 + 1175 00be 13 .uleb128 0x13 + 1176 00bf 00 .byte 0 + 1177 00c0 00 .byte 0 + 1178 00c1 10 .uleb128 0x10 + 1179 00c2 26 .uleb128 0x26 + 1180 00c3 00 .byte 0 + 1181 00c4 49 .uleb128 0x49 + 1182 00c5 13 .uleb128 0x13 + 1183 00c6 00 .byte 0 + 1184 00c7 00 .byte 0 + 1185 00c8 11 .uleb128 0x11 + 1186 00c9 01 .uleb128 0x1 + 1187 00ca 01 .byte 0x1 + 1188 00cb 49 .uleb128 0x49 + 1189 00cc 13 .uleb128 0x13 + 1190 00cd 01 .uleb128 0x1 + 1191 00ce 13 .uleb128 0x13 + 1192 00cf 00 .byte 0 + 1193 00d0 00 .byte 0 + ARM GAS C:\cygwin\tmp\cctqk36j.s page 22 + + + 1194 00d1 12 .uleb128 0x12 + 1195 00d2 21 .uleb128 0x21 + 1196 00d3 00 .byte 0 + 1197 00d4 49 .uleb128 0x49 + 1198 00d5 13 .uleb128 0x13 + 1199 00d6 2F .uleb128 0x2f + 1200 00d7 0B .uleb128 0xb + 1201 00d8 00 .byte 0 + 1202 00d9 00 .byte 0 + 1203 00da 13 .uleb128 0x13 + 1204 00db 2E .uleb128 0x2e + 1205 00dc 01 .byte 0x1 + 1206 00dd 3F .uleb128 0x3f + 1207 00de 0C .uleb128 0xc + 1208 00df 03 .uleb128 0x3 + 1209 00e0 0E .uleb128 0xe + 1210 00e1 3A .uleb128 0x3a + 1211 00e2 0B .uleb128 0xb + 1212 00e3 3B .uleb128 0x3b + 1213 00e4 0B .uleb128 0xb + 1214 00e5 27 .uleb128 0x27 + 1215 00e6 0C .uleb128 0xc + 1216 00e7 49 .uleb128 0x49 + 1217 00e8 13 .uleb128 0x13 + 1218 00e9 11 .uleb128 0x11 + 1219 00ea 01 .uleb128 0x1 + 1220 00eb 12 .uleb128 0x12 + 1221 00ec 01 .uleb128 0x1 + 1222 00ed 40 .uleb128 0x40 + 1223 00ee 0A .uleb128 0xa + 1224 00ef 9742 .uleb128 0x2117 + 1225 00f1 0C .uleb128 0xc + 1226 00f2 01 .uleb128 0x1 + 1227 00f3 13 .uleb128 0x13 + 1228 00f4 00 .byte 0 + 1229 00f5 00 .byte 0 + 1230 00f6 14 .uleb128 0x14 + 1231 00f7 34 .uleb128 0x34 + 1232 00f8 00 .byte 0 + 1233 00f9 03 .uleb128 0x3 + 1234 00fa 08 .uleb128 0x8 + 1235 00fb 3A .uleb128 0x3a + 1236 00fc 0B .uleb128 0xb + 1237 00fd 3B .uleb128 0x3b + 1238 00fe 0B .uleb128 0xb + 1239 00ff 49 .uleb128 0x49 + 1240 0100 13 .uleb128 0x13 + 1241 0101 02 .uleb128 0x2 + 1242 0102 0A .uleb128 0xa + 1243 0103 00 .byte 0 + 1244 0104 00 .byte 0 + 1245 0105 15 .uleb128 0x15 + 1246 0106 2E .uleb128 0x2e + 1247 0107 01 .byte 0x1 + 1248 0108 3F .uleb128 0x3f + 1249 0109 0C .uleb128 0xc + 1250 010a 03 .uleb128 0x3 + ARM GAS C:\cygwin\tmp\cctqk36j.s page 23 + + + 1251 010b 0E .uleb128 0xe + 1252 010c 3A .uleb128 0x3a + 1253 010d 0B .uleb128 0xb + 1254 010e 3B .uleb128 0x3b + 1255 010f 0B .uleb128 0xb + 1256 0110 27 .uleb128 0x27 + 1257 0111 0C .uleb128 0xc + 1258 0112 49 .uleb128 0x49 + 1259 0113 13 .uleb128 0x13 + 1260 0114 11 .uleb128 0x11 + 1261 0115 01 .uleb128 0x1 + 1262 0116 12 .uleb128 0x12 + 1263 0117 01 .uleb128 0x1 + 1264 0118 40 .uleb128 0x40 + 1265 0119 06 .uleb128 0x6 + 1266 011a 9742 .uleb128 0x2117 + 1267 011c 0C .uleb128 0xc + 1268 011d 01 .uleb128 0x1 + 1269 011e 13 .uleb128 0x13 + 1270 011f 00 .byte 0 + 1271 0120 00 .byte 0 + 1272 0121 16 .uleb128 0x16 + 1273 0122 05 .uleb128 0x5 + 1274 0123 00 .byte 0 + 1275 0124 03 .uleb128 0x3 + 1276 0125 08 .uleb128 0x8 + 1277 0126 3A .uleb128 0x3a + 1278 0127 0B .uleb128 0xb + 1279 0128 3B .uleb128 0x3b + 1280 0129 0B .uleb128 0xb + 1281 012a 49 .uleb128 0x49 + 1282 012b 13 .uleb128 0x13 + 1283 012c 02 .uleb128 0x2 + 1284 012d 06 .uleb128 0x6 + 1285 012e 00 .byte 0 + 1286 012f 00 .byte 0 + 1287 0130 17 .uleb128 0x17 + 1288 0131 34 .uleb128 0x34 + 1289 0132 00 .byte 0 + 1290 0133 03 .uleb128 0x3 + 1291 0134 08 .uleb128 0x8 + 1292 0135 3A .uleb128 0x3a + 1293 0136 0B .uleb128 0xb + 1294 0137 3B .uleb128 0x3b + 1295 0138 0B .uleb128 0xb + 1296 0139 49 .uleb128 0x49 + 1297 013a 13 .uleb128 0x13 + 1298 013b 02 .uleb128 0x2 + 1299 013c 06 .uleb128 0x6 + 1300 013d 00 .byte 0 + 1301 013e 00 .byte 0 + 1302 013f 18 .uleb128 0x18 + 1303 0140 898201 .uleb128 0x4109 + 1304 0143 00 .byte 0 + 1305 0144 11 .uleb128 0x11 + 1306 0145 01 .uleb128 0x1 + 1307 0146 31 .uleb128 0x31 + ARM GAS C:\cygwin\tmp\cctqk36j.s page 24 + + + 1308 0147 13 .uleb128 0x13 + 1309 0148 00 .byte 0 + 1310 0149 00 .byte 0 + 1311 014a 19 .uleb128 0x19 + 1312 014b 34 .uleb128 0x34 + 1313 014c 00 .byte 0 + 1314 014d 03 .uleb128 0x3 + 1315 014e 0E .uleb128 0xe + 1316 014f 3A .uleb128 0x3a + 1317 0150 0B .uleb128 0xb + 1318 0151 3B .uleb128 0x3b + 1319 0152 0B .uleb128 0xb + 1320 0153 49 .uleb128 0x49 + 1321 0154 13 .uleb128 0x13 + 1322 0155 3F .uleb128 0x3f + 1323 0156 0C .uleb128 0xc + 1324 0157 3C .uleb128 0x3c + 1325 0158 0C .uleb128 0xc + 1326 0159 00 .byte 0 + 1327 015a 00 .byte 0 + 1328 015b 1A .uleb128 0x1a + 1329 015c 34 .uleb128 0x34 + 1330 015d 00 .byte 0 + 1331 015e 03 .uleb128 0x3 + 1332 015f 0E .uleb128 0xe + 1333 0160 3A .uleb128 0x3a + 1334 0161 0B .uleb128 0xb + 1335 0162 3B .uleb128 0x3b + 1336 0163 0B .uleb128 0xb + 1337 0164 49 .uleb128 0x49 + 1338 0165 13 .uleb128 0x13 + 1339 0166 3F .uleb128 0x3f + 1340 0167 0C .uleb128 0xc + 1341 0168 02 .uleb128 0x2 + 1342 0169 0A .uleb128 0xa + 1343 016a 00 .byte 0 + 1344 016b 00 .byte 0 + 1345 016c 1B .uleb128 0x1b + 1346 016d 2E .uleb128 0x2e + 1347 016e 01 .byte 0x1 + 1348 016f 3F .uleb128 0x3f + 1349 0170 0C .uleb128 0xc + 1350 0171 03 .uleb128 0x3 + 1351 0172 0E .uleb128 0xe + 1352 0173 3A .uleb128 0x3a + 1353 0174 0B .uleb128 0xb + 1354 0175 3B .uleb128 0x3b + 1355 0176 0B .uleb128 0xb + 1356 0177 27 .uleb128 0x27 + 1357 0178 0C .uleb128 0xc + 1358 0179 3C .uleb128 0x3c + 1359 017a 0C .uleb128 0xc + 1360 017b 00 .byte 0 + 1361 017c 00 .byte 0 + 1362 017d 1C .uleb128 0x1c + 1363 017e 05 .uleb128 0x5 + 1364 017f 00 .byte 0 + ARM GAS C:\cygwin\tmp\cctqk36j.s page 25 + + + 1365 0180 49 .uleb128 0x49 + 1366 0181 13 .uleb128 0x13 + 1367 0182 00 .byte 0 + 1368 0183 00 .byte 0 + 1369 0184 00 .byte 0 + 1370 .section .debug_loc,"",%progbits + 1371 .Ldebug_loc0: + 1372 .LLST0: + 1373 0000 00000000 .4byte .LFB8 + 1374 0004 02000000 .4byte .LCFI0 + 1375 0008 0200 .2byte 0x2 + 1376 000a 7D .byte 0x7d + 1377 000b 00 .sleb128 0 + 1378 000c 02000000 .4byte .LCFI0 + 1379 0010 24000000 .4byte .LFE8 + 1380 0014 0200 .2byte 0x2 + 1381 0016 7D .byte 0x7d + 1382 0017 08 .sleb128 8 + 1383 0018 00000000 .4byte 0 + 1384 001c 00000000 .4byte 0 + 1385 .LLST1: + 1386 0020 00000000 .4byte .LVL1 + 1387 0024 17000000 .4byte .LVL4-1 + 1388 0028 0100 .2byte 0x1 + 1389 002a 50 .byte 0x50 + 1390 002b 17000000 .4byte .LVL4-1 + 1391 002f 1C000000 .4byte .LVL5 + 1392 0033 0400 .2byte 0x4 + 1393 0035 F3 .byte 0xf3 + 1394 0036 01 .uleb128 0x1 + 1395 0037 50 .byte 0x50 + 1396 0038 9F .byte 0x9f + 1397 0039 1C000000 .4byte .LVL5 + 1398 003d 24000000 .4byte .LFE8 + 1399 0041 0100 .2byte 0x1 + 1400 0043 50 .byte 0x50 + 1401 0044 00000000 .4byte 0 + 1402 0048 00000000 .4byte 0 + 1403 .LLST2: + 1404 004c 08000000 .4byte .LVL2 + 1405 0050 1E000000 .4byte .LVL6 + 1406 0054 0100 .2byte 0x1 + 1407 0056 54 .byte 0x54 + 1408 0057 1E000000 .4byte .LVL6 + 1409 005b 24000000 .4byte .LFE8 + 1410 005f 0200 .2byte 0x2 + 1411 0061 70 .byte 0x70 + 1412 0062 10 .sleb128 16 + 1413 0063 00000000 .4byte 0 + 1414 0067 00000000 .4byte 0 + 1415 .section .debug_aranges,"",%progbits + 1416 0000 24000000 .4byte 0x24 + 1417 0004 0200 .2byte 0x2 + 1418 0006 00000000 .4byte .Ldebug_info0 + 1419 000a 04 .byte 0x4 + 1420 000b 00 .byte 0 + 1421 000c 0000 .2byte 0 + ARM GAS C:\cygwin\tmp\cctqk36j.s page 26 + + + 1422 000e 0000 .2byte 0 + 1423 0010 00000000 .4byte .LFB7 + 1424 0014 16000000 .4byte .LFE7-.LFB7 + 1425 0018 00000000 .4byte .LFB8 + 1426 001c 24000000 .4byte .LFE8-.LFB8 + 1427 0020 00000000 .4byte 0 + 1428 0024 00000000 .4byte 0 + 1429 .section .debug_ranges,"",%progbits + 1430 .Ldebug_ranges0: + 1431 0000 00000000 .4byte .LFB7 + 1432 0004 16000000 .4byte .LFE7 + 1433 0008 00000000 .4byte .LFB8 + 1434 000c 24000000 .4byte .LFE8 + 1435 0010 00000000 .4byte 0 + 1436 0014 00000000 .4byte 0 + 1437 .section .debug_line,"",%progbits + 1438 .Ldebug_line0: + 1439 0000 92010000 .section .debug_str,"MS",%progbits,1 + 1439 02005C01 + 1439 00000201 + 1439 FB0E0D00 + 1439 01010101 + 1440 .LASF74: + 1441 0000 63665F6F .ascii "cf_off_older\000" + 1441 66665F6F + 1441 6C646572 + 1441 00 + 1442 .LASF36: + 1443 000d 705F6D73 .ascii "p_msg\000" + 1443 6700 + 1444 .LASF2: + 1445 0013 73697A65 .ascii "size_t\000" + 1445 5F7400 + 1446 .LASF59: + 1447 001a 7264796D .ascii "rdymsg\000" + 1447 736700 + 1448 .LASF54: + 1449 0021 52656164 .ascii "ReadyList\000" + 1449 794C6973 + 1449 7400 + 1450 .LASF13: + 1451 002b 6C6F6E67 .ascii "long long unsigned int\000" + 1451 206C6F6E + 1451 6720756E + 1451 7369676E + 1451 65642069 + 1452 .LASF70: + 1453 0042 63685F74 .ascii "ch_threadsize\000" + 1453 68726561 + 1453 6473697A + 1453 6500 + 1454 .LASF60: + 1455 0050 65786974 .ascii "exitcode\000" + 1455 636F6465 + 1455 00 + 1456 .LASF83: + 1457 0059 63685265 .ascii "chRegFirstThread\000" + ARM GAS C:\cygwin\tmp\cctqk36j.s page 27 + + + 1457 67466972 + 1457 73745468 + 1457 72656164 + 1457 00 + 1458 .LASF25: + 1459 006a 705F7072 .ascii "p_prio\000" + 1459 696F00 + 1460 .LASF77: + 1461 0071 63665F6F .ascii "cf_off_state\000" + 1461 66665F73 + 1461 74617465 + 1461 00 + 1462 .LASF12: + 1463 007e 6C6F6E67 .ascii "long long int\000" + 1463 206C6F6E + 1463 6720696E + 1463 7400 + 1464 .LASF1: + 1465 008c 7369676E .ascii "signed char\000" + 1465 65642063 + 1465 68617200 + 1466 .LASF76: + 1467 0098 63665F6F .ascii "cf_off_stklimit\000" + 1467 66665F73 + 1467 746B6C69 + 1467 6D697400 + 1468 .LASF78: + 1469 00a8 63665F6F .ascii "cf_off_flags\000" + 1469 66665F66 + 1469 6C616773 + 1469 00 + 1470 .LASF40: + 1471 00b5 705F6D70 .ascii "p_mpool\000" + 1471 6F6F6C00 + 1472 .LASF56: + 1473 00bd 6D5F7175 .ascii "m_queue\000" + 1473 65756500 + 1474 .LASF64: + 1475 00c5 63685F69 .ascii "ch_identifier\000" + 1475 64656E74 + 1475 69666965 + 1475 7200 + 1476 .LASF9: + 1477 00d3 6C6F6E67 .ascii "long int\000" + 1477 20696E74 + 1477 00 + 1478 .LASF15: + 1479 00dc 74737461 .ascii "tstate_t\000" + 1479 74655F74 + 1479 00 + 1480 .LASF6: + 1481 00e5 75696E74 .ascii "uint16_t\000" + 1481 31365F74 + 1481 00 + 1482 .LASF82: + 1483 00ee 63686465 .ascii "chdebug_t\000" + 1483 6275675F + ARM GAS C:\cygwin\tmp\cctqk36j.s page 28 + + + 1483 7400 + 1484 .LASF27: + 1485 00f8 705F6E65 .ascii "p_newer\000" + 1485 77657200 + 1486 .LASF50: + 1487 0100 725F6E65 .ascii "r_newer\000" + 1487 77657200 + 1488 .LASF43: + 1489 0108 72656761 .ascii "regarm_t\000" + 1489 726D5F74 + 1489 00 + 1490 .LASF21: + 1491 0111 636E745F .ascii "cnt_t\000" + 1491 7400 + 1492 .LASF0: + 1493 0117 756E7369 .ascii "unsigned int\000" + 1493 676E6564 + 1493 20696E74 + 1493 00 + 1494 .LASF11: + 1495 0124 6C6F6E67 .ascii "long unsigned int\000" + 1495 20756E73 + 1495 69676E65 + 1495 6420696E + 1495 7400 + 1496 .LASF86: + 1497 0136 63685F64 .ascii "ch_debug\000" + 1497 65627567 + 1497 00 + 1498 .LASF45: + 1499 013f 636F6E74 .ascii "context\000" + 1499 65787400 + 1500 .LASF7: + 1501 0147 73686F72 .ascii "short unsigned int\000" + 1501 7420756E + 1501 7369676E + 1501 65642069 + 1501 6E7400 + 1502 .LASF18: + 1503 015a 6D73675F .ascii "msg_t\000" + 1503 7400 + 1504 .LASF14: + 1505 0160 746D6F64 .ascii "tmode_t\000" + 1505 655F7400 + 1506 .LASF42: + 1507 0168 54687265 .ascii "ThreadsList\000" + 1507 6164734C + 1507 69737400 + 1508 .LASF19: + 1509 0174 6576656E .ascii "eventmask_t\000" + 1509 746D6173 + 1509 6B5F7400 + 1510 .LASF55: + 1511 0180 4D757465 .ascii "Mutex\000" + 1511 7800 + 1512 .LASF65: + 1513 0186 63685F7A .ascii "ch_zero\000" + ARM GAS C:\cygwin\tmp\cctqk36j.s page 29 + + + 1513 65726F00 + 1514 .LASF79: + 1515 018e 63665F6F .ascii "cf_off_refs\000" + 1515 66665F72 + 1515 65667300 + 1516 .LASF46: + 1517 019a 73697A65 .ascii "sizetype\000" + 1517 74797065 + 1517 00 + 1518 .LASF69: + 1519 01a3 63685F74 .ascii "ch_timesize\000" + 1519 696D6573 + 1519 697A6500 + 1520 .LASF75: + 1521 01af 63665F6F .ascii "cf_off_name\000" + 1521 66665F6E + 1521 616D6500 + 1522 .LASF28: + 1523 01bb 705F6F6C .ascii "p_older\000" + 1523 64657200 + 1524 .LASF89: + 1525 01c3 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 1525 73657273 + 1525 5C496D61 + 1525 6E6F6C5C + 1525 64657665 + 1526 01f0 6C696361 .ascii "lications\\smartcities\000" + 1526 74696F6E + 1526 735C736D + 1526 61727463 + 1526 69746965 + 1527 .LASF41: + 1528 0206 54687265 .ascii "ThreadsQueue\000" + 1528 61647351 + 1528 75657565 + 1528 00 + 1529 .LASF66: + 1530 0213 63685F73 .ascii "ch_size\000" + 1530 697A6500 + 1531 .LASF87: + 1532 021b 474E5520 .ascii "GNU C 4.7.2\000" + 1532 4320342E + 1532 372E3200 + 1533 .LASF53: + 1534 0227 725F6375 .ascii "r_current\000" + 1534 7272656E + 1534 7400 + 1535 .LASF51: + 1536 0231 725F6F6C .ascii "r_older\000" + 1536 64657200 + 1537 .LASF16: + 1538 0239 74726566 .ascii "trefs_t\000" + 1538 735F7400 + 1539 .LASF68: + 1540 0241 63685F70 .ascii "ch_ptrsize\000" + 1540 74727369 + 1540 7A6500 + ARM GAS C:\cygwin\tmp\cctqk36j.s page 30 + + + 1541 .LASF24: + 1542 024c 705F7072 .ascii "p_prev\000" + 1542 657600 + 1543 .LASF17: + 1544 0253 74707269 .ascii "tprio_t\000" + 1544 6F5F7400 + 1545 .LASF8: + 1546 025b 696E7433 .ascii "int32_t\000" + 1546 325F7400 + 1547 .LASF4: + 1548 0263 756E7369 .ascii "unsigned char\000" + 1548 676E6564 + 1548 20636861 + 1548 7200 + 1549 .LASF38: + 1550 0271 705F6D74 .ascii "p_mtxlist\000" + 1550 786C6973 + 1550 7400 + 1551 .LASF5: + 1552 027b 73686F72 .ascii "short int\000" + 1552 7420696E + 1552 7400 + 1553 .LASF30: + 1554 0285 705F7374 .ascii "p_state\000" + 1554 61746500 + 1555 .LASF81: + 1556 028d 63665F6F .ascii "cf_off_time\000" + 1556 66665F74 + 1556 696D6500 + 1557 .LASF48: + 1558 0299 725F7072 .ascii "r_prio\000" + 1558 696F00 + 1559 .LASF62: + 1560 02a0 65776D61 .ascii "ewmask\000" + 1560 736B00 + 1561 .LASF23: + 1562 02a7 705F6E65 .ascii "p_next\000" + 1562 787400 + 1563 .LASF80: + 1564 02ae 63665F6F .ascii "cf_off_preempt\000" + 1564 66665F70 + 1564 7265656D + 1564 707400 + 1565 .LASF31: + 1566 02bd 705F666C .ascii "p_flags\000" + 1566 61677300 + 1567 .LASF90: + 1568 02c5 63685468 .ascii "chThdRelease\000" + 1568 6452656C + 1568 65617365 + 1568 00 + 1569 .LASF22: + 1570 02d2 54687265 .ascii "Thread\000" + 1570 616400 + 1571 .LASF73: + 1572 02d9 63665F6F .ascii "cf_off_newer\000" + 1572 66665F6E + ARM GAS C:\cygwin\tmp\cctqk36j.s page 31 + + + 1572 65776572 + 1572 00 + 1573 .LASF37: + 1574 02e6 705F6570 .ascii "p_epending\000" + 1574 656E6469 + 1574 6E6700 + 1575 .LASF10: + 1576 02f1 75696E74 .ascii "uint32_t\000" + 1576 33325F74 + 1576 00 + 1577 .LASF71: + 1578 02fa 63665F6F .ascii "cf_off_prio\000" + 1578 66665F70 + 1578 72696F00 + 1579 .LASF47: + 1580 0306 725F7175 .ascii "r_queue\000" + 1580 65756500 + 1581 .LASF63: + 1582 030e 63686172 .ascii "char\000" + 1582 00 + 1583 .LASF84: + 1584 0313 63685265 .ascii "chRegNextThread\000" + 1584 674E6578 + 1584 74546872 + 1584 65616400 + 1585 .LASF58: + 1586 0323 6D5F6E65 .ascii "m_next\000" + 1586 787400 + 1587 .LASF20: + 1588 032a 73797374 .ascii "systime_t\000" + 1588 696D655F + 1588 7400 + 1589 .LASF39: + 1590 0334 705F7265 .ascii "p_realprio\000" + 1590 616C7072 + 1590 696F00 + 1591 .LASF33: + 1592 033f 705F7469 .ascii "p_time\000" + 1592 6D6500 + 1593 .LASF49: + 1594 0346 725F6374 .ascii "r_ctx\000" + 1594 7800 + 1595 .LASF44: + 1596 034c 696E7463 .ascii "intctx\000" + 1596 747800 + 1597 .LASF35: + 1598 0353 705F6D73 .ascii "p_msgqueue\000" + 1598 67717565 + 1598 756500 + 1599 .LASF72: + 1600 035e 63665F6F .ascii "cf_off_ctx\000" + 1600 66665F63 + 1600 747800 + 1601 .LASF32: + 1602 0369 705F7265 .ascii "p_refs\000" + 1602 667300 + 1603 .LASF88: + ARM GAS C:\cygwin\tmp\cctqk36j.s page 32 + + + 1604 0370 2E2E2F2E .ascii "../..//os/kernel/src/chregistry.c\000" + 1604 2E2F2F6F + 1604 732F6B65 + 1604 726E656C + 1604 2F737263 + 1605 .LASF85: + 1606 0392 726C6973 .ascii "rlist\000" + 1606 7400 + 1607 .LASF3: + 1608 0398 75696E74 .ascii "uint8_t\000" + 1608 385F7400 + 1609 .LASF61: + 1610 03a0 77746F62 .ascii "wtobjp\000" + 1610 6A7000 + 1611 .LASF29: + 1612 03a7 705F6E61 .ascii "p_name\000" + 1612 6D6500 + 1613 .LASF67: + 1614 03ae 63685F76 .ascii "ch_version\000" + 1614 65727369 + 1614 6F6E00 + 1615 .LASF52: + 1616 03b9 725F7072 .ascii "r_preempt\000" + 1616 65656D70 + 1616 7400 + 1617 .LASF57: + 1618 03c3 6D5F6F77 .ascii "m_owner\000" + 1618 6E657200 + 1619 .LASF26: + 1620 03cb 705F6374 .ascii "p_ctx\000" + 1620 7800 + 1621 .LASF34: + 1622 03d1 705F7761 .ascii "p_waiting\000" + 1622 6974696E + 1622 6700 + 1623 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\cctqk36j.s page 33 + + +DEFINED SYMBOLS + *ABS*:00000000 chregistry.c +C:\cygwin\tmp\cctqk36j.s:19 .text.chRegFirstThread:00000000 $t +C:\cygwin\tmp\cctqk36j.s:25 .text.chRegFirstThread:00000000 chRegFirstThread +C:\cygwin\tmp\cctqk36j.s:58 .text.chRegNextThread:00000000 $t +C:\cygwin\tmp\cctqk36j.s:64 .text.chRegNextThread:00000000 chRegNextThread +C:\cygwin\tmp\cctqk36j.s:115 .text.chRegNextThread:00000020 $d +C:\cygwin\tmp\cctqk36j.s:124 .rodata.ch_debug:00000000 ch_debug +C:\cygwin\tmp\cctqk36j.s:121 .rodata.ch_debug:00000000 $d + .debug_frame:00000010 $d +C:\cygwin\tmp\cctqk36j.s:120 .text.chRegNextThread:00000024 $t + +UNDEFINED SYMBOLS +rlist +chThdRelease diff --git a/Project/applications/smartcities/build/lst/chschd.lst b/Project/applications/smartcities/build/lst/chschd.lst new file mode 100644 index 0000000..9c86319 --- /dev/null +++ b/Project/applications/smartcities/build/lst/chschd.lst @@ -0,0 +1,3571 @@ +ARM GAS C:\cygwin\tmp\ccNqiZol.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "chschd.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text.wakeup,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .thumb + 22 .thumb_func + 23 .type wakeup, %function + 24 wakeup: + 25 .LFB10: + 26 .file 1 "../..//os/kernel/src/chschd.c" + 27 .loc 1 133 0 + 28 .cfi_startproc + 29 @ args = 0, pretend = 0, frame = 0 + 30 @ frame_needed = 0, uses_anonymous_args = 0 + 31 @ link register save eliminated. + 32 .LVL0: + 33 .loc 1 136 0 + 34 0000 037F ldrb r3, [r0, #28] @ zero_extendqisi2 + 35 0002 0D2B cmp r3, #13 + 36 0004 11D8 bhi .L2 + 37 0006 DFE803F0 tbb [pc, r3] + 38 .L6: + 39 000a 20 .byte (.L1-.L6)/2 + 40 000b 10 .byte (.L2-.L6)/2 + 41 000c 10 .byte (.L2-.L6)/2 + 42 000d 07 .byte (.L4-.L6)/2 + 43 000e 10 .byte (.L2-.L6)/2 + 44 000f 0B .byte (.L5-.L6)/2 + 45 0010 10 .byte (.L2-.L6)/2 + 46 0011 10 .byte (.L2-.L6)/2 + 47 0012 10 .byte (.L2-.L6)/2 + 48 0013 10 .byte (.L2-.L6)/2 + 49 0014 10 .byte (.L2-.L6)/2 + 50 0015 10 .byte (.L2-.L6)/2 + 51 0016 10 .byte (.L2-.L6)/2 + 52 0017 0B .byte (.L5-.L6)/2 + 53 .align 1 + 54 .L4: + 55 .loc 1 145 0 + 56 0018 436A ldr r3, [r0, #36] + 57 001a 9A68 ldr r2, [r3, #8] + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 2 + + + 58 001c 0132 adds r2, r2, #1 + 59 001e 9A60 str r2, [r3, #8] + 60 .L5: + 61 .LVL1: + 62 .LBB17: + 63 .LBB18: + 64 .file 2 "../..//os/kernel/include/chinline.h" + 65 .loc 2 75 0 + 66 0020 90E80C00 ldmia r0, {r2, r3} + 67 0024 1A60 str r2, [r3, #0] + 68 .loc 2 76 0 + 69 0026 0268 ldr r2, [r0, #0] + 70 0028 5360 str r3, [r2, #4] + 71 .LVL2: + 72 .L2: + 73 .LBE18: + 74 .LBE17: + 75 .loc 1 158 0 + 76 002a 4FF0FF32 mov r2, #-1 + 77 002e 4262 str r2, [r0, #36] + 78 .LVL3: + 79 0030 8168 ldr r1, [r0, #8] + 80 .LBB19: + 81 .LBB20: + 82 .loc 1 91 0 + 83 0032 0022 movs r2, #0 + 84 .loc 1 92 0 + 85 0034 054B ldr r3, .L10 + 86 .loc 1 91 0 + 87 0036 0277 strb r2, [r0, #28] + 88 .LVL4: + 89 .L7: + 90 .loc 1 94 0 + 91 0038 1B68 ldr r3, [r3, #0] + 92 .LVL5: + 93 .loc 1 95 0 + 94 003a 9A68 ldr r2, [r3, #8] + 95 003c 8A42 cmp r2, r1 + 96 003e FBD2 bcs .L7 + 97 .loc 1 98 0 + 98 0040 5A68 ldr r2, [r3, #4] + 99 .loc 1 97 0 + 100 0042 0360 str r3, [r0, #0] + 101 .loc 1 98 0 + 102 0044 4260 str r2, [r0, #4] + 103 .loc 1 99 0 + 104 0046 1060 str r0, [r2, #0] + 105 0048 5860 str r0, [r3, #4] + 106 .LVL6: + 107 .L1: + 108 004a 7047 bx lr + 109 .L11: + 110 .align 2 + 111 .L10: + 112 004c 00000000 .word .LANCHOR0 + 113 .LBE20: + 114 .LBE19: + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 3 + + + 115 .cfi_endproc + 116 .LFE10: + 117 .size wakeup, .-wakeup + 118 .section .text._scheduler_init,"ax",%progbits + 119 .align 2 + 120 .p2align 4,,15 + 121 .global _scheduler_init + 122 .thumb + 123 .thumb_func + 124 .type _scheduler_init, %function + 125 _scheduler_init: + 126 .LFB7: + 127 .loc 1 55 0 + 128 .cfi_startproc + 129 @ args = 0, pretend = 0, frame = 0 + 130 @ frame_needed = 0, uses_anonymous_args = 0 + 131 @ link register save eliminated. + 132 .loc 1 57 0 + 133 0000 40F20003 movw r3, #:lower16:.LANCHOR0 + 134 0004 C0F20003 movt r3, #:upper16:.LANCHOR0 + 135 .loc 1 58 0 + 136 0008 0022 movs r2, #0 + 137 000a 9A60 str r2, [r3, #8] + 138 .loc 1 60 0 + 139 000c 1422 movs r2, #20 + 140 .loc 1 57 0 + 141 000e 5B60 str r3, [r3, #4] + 142 0010 1B60 str r3, [r3, #0] + 143 .loc 1 60 0 + 144 0012 9A61 str r2, [r3, #24] + 145 .loc 1 63 0 + 146 0014 5B61 str r3, [r3, #20] + 147 0016 1B61 str r3, [r3, #16] + 148 0018 7047 bx lr + 149 .cfi_endproc + 150 .LFE7: + 151 .size _scheduler_init, .-_scheduler_init + 152 001a 00BFAFF3 .section .text.chSchReadyI,"ax",%progbits + 152 0080 + 153 .align 2 + 154 .p2align 4,,15 + 155 .global chSchReadyI + 156 .thumb + 157 .thumb_func + 158 .type chSchReadyI, %function + 159 chSchReadyI: + 160 .LFB8: + 161 .loc 1 82 0 + 162 .cfi_startproc + 163 @ args = 0, pretend = 0, frame = 0 + 164 @ frame_needed = 0, uses_anonymous_args = 0 + 165 @ link register save eliminated. + 166 .LVL7: + 167 .loc 1 91 0 + 168 0000 0022 movs r2, #0 + 169 0002 8168 ldr r1, [r0, #8] + 170 .loc 1 92 0 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 4 + + + 171 0004 054B ldr r3, .L16 + 172 .loc 1 91 0 + 173 0006 0277 strb r2, [r0, #28] + 174 .LVL8: + 175 .L14: + 176 .loc 1 94 0 discriminator 1 + 177 0008 1B68 ldr r3, [r3, #0] + 178 .LVL9: + 179 .loc 1 95 0 discriminator 1 + 180 000a 9A68 ldr r2, [r3, #8] + 181 000c 8A42 cmp r2, r1 + 182 000e FBD2 bcs .L14 + 183 .loc 1 98 0 + 184 0010 5A68 ldr r2, [r3, #4] + 185 .loc 1 97 0 + 186 0012 0360 str r3, [r0, #0] + 187 .loc 1 98 0 + 188 0014 4260 str r2, [r0, #4] + 189 .loc 1 99 0 + 190 0016 1060 str r0, [r2, #0] + 191 0018 5860 str r0, [r3, #4] + 192 .loc 1 101 0 + 193 001a 7047 bx lr + 194 .L17: + 195 .align 2 + 196 .L16: + 197 001c 00000000 .word .LANCHOR0 + 198 .cfi_endproc + 199 .LFE8: + 200 .size chSchReadyI, .-chSchReadyI + 201 .section .text.chSchGoSleepS,"ax",%progbits + 202 .align 2 + 203 .p2align 4,,15 + 204 .global chSchGoSleepS + 205 .thumb + 206 .thumb_func + 207 .type chSchGoSleepS, %function + 208 chSchGoSleepS: + 209 .LFB9: + 210 .loc 1 114 0 + 211 .cfi_startproc + 212 @ args = 0, pretend = 0, frame = 0 + 213 @ frame_needed = 0, uses_anonymous_args = 0 + 214 @ link register save eliminated. + 215 .LVL10: + 216 .loc 1 119 0 + 217 0000 40F20003 movw r3, #:lower16:.LANCHOR0 + 218 .loc 1 114 0 + 219 0004 30B4 push {r4, r5} + 220 .LCFI0: + 221 .cfi_def_cfa_offset 8 + 222 .cfi_offset 4, -8 + 223 .cfi_offset 5, -4 + 224 .loc 1 119 0 + 225 0006 C0F20003 movt r3, #:upper16:.LANCHOR0 + 226 .LBB21: + 227 .LBB22: + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 5 + + + 228 .loc 2 60 0 + 229 000a 1A68 ldr r2, [r3, #0] + 230 .LBE22: + 231 .LBE21: + 232 .loc 1 119 0 + 233 000c D969 ldr r1, [r3, #28] + 234 .LVL11: + 235 .LBB25: + 236 .LBB23: + 237 .loc 2 62 0 + 238 000e 1468 ldr r4, [r2, #0] + 239 .LBE23: + 240 .LBE25: + 241 .loc 1 119 0 + 242 0010 0877 strb r0, [r1, #28] + 243 .loc 1 121 0 + 244 0012 1420 movs r0, #20 + 245 .LVL12: + 246 0014 9861 str r0, [r3, #24] + 247 .LVL13: + 248 .loc 1 124 0 + 249 0016 0125 movs r5, #1 + 250 .loc 1 125 0 + 251 0018 1046 mov r0, r2 + 252 .LBB26: + 253 .LBB24: + 254 .loc 2 62 0 + 255 001a 6360 str r3, [r4, #4] + 256 001c 1C60 str r4, [r3, #0] + 257 .LBE24: + 258 .LBE26: + 259 .loc 1 123 0 + 260 001e DA61 str r2, [r3, #28] + 261 .loc 1 124 0 + 262 0020 1577 strb r5, [r2, #28] + 263 .loc 1 126 0 + 264 0022 30BC pop {r4, r5} + 265 .loc 1 125 0 + 266 0024 FFF7FEBF b _port_switch + 267 .LVL14: + 268 .cfi_endproc + 269 .LFE9: + 270 .size chSchGoSleepS, .-chSchGoSleepS + 271 0028 AFF30080 .section .text.chSchGoSleepTimeoutS,"ax",%progbits + 271 AFF30080 + 272 .align 2 + 273 .p2align 4,,15 + 274 .global chSchGoSleepTimeoutS + 275 .thumb + 276 .thumb_func + 277 .type chSchGoSleepTimeoutS, %function + 278 chSchGoSleepTimeoutS: + 279 .LFB11: + 280 .loc 1 183 0 + 281 .cfi_startproc + 282 @ args = 0, pretend = 0, frame = 24 + 283 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 6 + + + 284 .LVL15: + 285 0000 30B5 push {r4, r5, lr} + 286 .LCFI1: + 287 .cfi_def_cfa_offset 12 + 288 .cfi_offset 4, -12 + 289 .cfi_offset 5, -8 + 290 .cfi_offset 14, -4 + 291 .loc 1 187 0 + 292 0002 4B1C adds r3, r1, #1 + 293 .loc 1 183 0 + 294 0004 87B0 sub sp, sp, #28 + 295 .LCFI2: + 296 .cfi_def_cfa_offset 40 + 297 .loc 1 183 0 + 298 0006 0546 mov r5, r0 + 299 .loc 1 187 0 + 300 0008 11D0 beq .L20 + 301 .LBB27: + 302 .loc 1 190 0 + 303 000a 0B4C ldr r4, .L26 + 304 000c 0B4A ldr r2, .L26+4 + 305 000e E369 ldr r3, [r4, #28] + 306 0010 01A8 add r0, sp, #4 + 307 .LVL16: + 308 0012 FFF7FEFF bl chVTSetI + 309 .LVL17: + 310 .loc 1 191 0 + 311 0016 2846 mov r0, r5 + 312 0018 FFF7FEFF bl chSchGoSleepS + 313 .LVL18: + 314 .loc 1 192 0 + 315 001c 049B ldr r3, [sp, #16] + 316 001e 13B1 cbz r3, .L22 + 317 .loc 1 193 0 + 318 0020 01A8 add r0, sp, #4 + 319 0022 FFF7FEFF bl chVTResetI + 320 .LVL19: + 321 .L22: + 322 .LBE27: + 323 .loc 1 197 0 + 324 0026 E369 ldr r3, [r4, #28] + 325 .loc 1 198 0 + 326 0028 586A ldr r0, [r3, #36] + 327 002a 07B0 add sp, sp, #28 + 328 002c 30BD pop {r4, r5, pc} + 329 .LVL20: + 330 .L20: + 331 .loc 1 196 0 + 332 002e FFF7FEFF bl chSchGoSleepS + 333 .LVL21: + 334 0032 014C ldr r4, .L26 + 335 0034 F7E7 b .L22 + 336 .L27: + 337 0036 00BF .align 2 + 338 .L26: + 339 0038 00000000 .word .LANCHOR0 + 340 003c 00000000 .word wakeup + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 7 + + + 341 .cfi_endproc + 342 .LFE11: + 343 .size chSchGoSleepTimeoutS, .-chSchGoSleepTimeoutS + 344 .section .text.chSchWakeupS,"ax",%progbits + 345 .align 2 + 346 .p2align 4,,15 + 347 .global chSchWakeupS + 348 .thumb + 349 .thumb_func + 350 .type chSchWakeupS, %function + 351 chSchWakeupS: + 352 .LFB12: + 353 .loc 1 219 0 + 354 .cfi_startproc + 355 @ args = 0, pretend = 0, frame = 0 + 356 @ frame_needed = 0, uses_anonymous_args = 0 + 357 @ link register save eliminated. + 358 .LVL22: + 359 0000 F0B4 push {r4, r5, r6, r7} + 360 .LCFI3: + 361 .cfi_def_cfa_offset 16 + 362 .cfi_offset 4, -16 + 363 .cfi_offset 5, -12 + 364 .cfi_offset 6, -8 + 365 .cfi_offset 7, -4 + 366 .loc 1 228 0 + 367 0002 154F ldr r7, .L36 + 368 .loc 1 219 0 + 369 0004 0446 mov r4, r0 + 370 .loc 1 228 0 + 371 0006 FE69 ldr r6, [r7, #28] + 372 0008 8568 ldr r5, [r0, #8] + 373 000a B068 ldr r0, [r6, #8] + 374 .LVL23: + 375 .LBB28: + 376 .LBB29: + 377 .loc 1 91 0 + 378 000c 0023 movs r3, #0 + 379 .LBE29: + 380 .LBE28: + 381 .loc 1 228 0 + 382 000e 8542 cmp r5, r0 + 383 .loc 1 223 0 + 384 0010 6162 str r1, [r4, #36] + 385 .loc 1 228 0 + 386 0012 0CD8 bhi .L29 + 387 .LVL24: + 388 .LBB31: + 389 .LBB30: + 390 .loc 1 91 0 + 391 0014 2377 strb r3, [r4, #28] + 392 .LVL25: + 393 .loc 1 92 0 + 394 0016 3B46 mov r3, r7 + 395 .LVL26: + 396 .L30: + 397 .loc 1 94 0 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 8 + + + 398 0018 1B68 ldr r3, [r3, #0] + 399 .LVL27: + 400 .loc 1 95 0 + 401 001a 9A68 ldr r2, [r3, #8] + 402 001c 9542 cmp r5, r2 + 403 001e FBD9 bls .L30 + 404 .loc 1 98 0 + 405 0020 5A68 ldr r2, [r3, #4] + 406 .loc 1 97 0 + 407 0022 2360 str r3, [r4, #0] + 408 .loc 1 98 0 + 409 0024 6260 str r2, [r4, #4] + 410 .loc 1 99 0 + 411 0026 1460 str r4, [r2, #0] + 412 0028 5C60 str r4, [r3, #4] + 413 .LBE30: + 414 .LBE31: + 415 .loc 1 239 0 + 416 002a F0BC pop {r4, r5, r6, r7} + 417 002c 7047 bx lr + 418 .LVL28: + 419 .L29: + 420 .LBB32: + 421 .LBB33: + 422 .LBB34: + 423 .loc 1 91 0 + 424 002e 3377 strb r3, [r6, #28] + 425 .LVL29: + 426 .loc 1 92 0 + 427 0030 3B46 mov r3, r7 + 428 .LVL30: + 429 .L32: + 430 .loc 1 94 0 + 431 0032 1B68 ldr r3, [r3, #0] + 432 .LVL31: + 433 .loc 1 95 0 + 434 0034 9A68 ldr r2, [r3, #8] + 435 0036 9042 cmp r0, r2 + 436 0038 FBD9 bls .L32 + 437 .loc 1 98 0 + 438 003a 5A68 ldr r2, [r3, #4] + 439 .loc 1 97 0 + 440 003c 3360 str r3, [r6, #0] + 441 .loc 1 98 0 + 442 003e 7260 str r2, [r6, #4] + 443 .loc 1 99 0 + 444 0040 5E60 str r6, [r3, #4] + 445 .LBE34: + 446 .LBE33: + 447 .loc 1 236 0 + 448 0042 0123 movs r3, #1 + 449 .LVL32: + 450 .LBB36: + 451 .LBB35: + 452 .loc 1 99 0 + 453 0044 1660 str r6, [r2, #0] + 454 .LBE35: + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 9 + + + 455 .LBE36: + 456 .loc 1 237 0 + 457 0046 2046 mov r0, r4 + 458 .loc 1 235 0 + 459 0048 FC61 str r4, [r7, #28] + 460 .loc 1 237 0 + 461 004a 3146 mov r1, r6 + 462 .LVL33: + 463 .loc 1 236 0 + 464 004c 2377 strb r3, [r4, #28] + 465 .loc 1 233 0 + 466 004e 1423 movs r3, #20 + 467 0050 BB61 str r3, [r7, #24] + 468 .LBE32: + 469 .loc 1 239 0 + 470 0052 F0BC pop {r4, r5, r6, r7} + 471 .LBB37: + 472 .loc 1 237 0 + 473 0054 FFF7FEBF b _port_switch + 474 .LVL34: + 475 .L37: + 476 .align 2 + 477 .L36: + 478 0058 00000000 .word .LANCHOR0 + 479 .LBE37: + 480 .cfi_endproc + 481 .LFE12: + 482 .size chSchWakeupS, .-chSchWakeupS + 483 005c AFF30080 .section .text.chSchDoReschedule,"ax",%progbits + 484 .align 2 + 485 .p2align 4,,15 + 486 .global chSchDoReschedule + 487 .thumb + 488 .thumb_func + 489 .type chSchDoReschedule, %function + 490 chSchDoReschedule: + 491 .LFB14: + 492 .loc 1 298 0 + 493 .cfi_startproc + 494 @ args = 0, pretend = 0, frame = 0 + 495 @ frame_needed = 0, uses_anonymous_args = 0 + 496 @ link register save eliminated. + 497 .loc 1 302 0 + 498 0000 0E4A ldr r2, .L42 + 499 .loc 1 298 0 + 500 0002 30B4 push {r4, r5} + 501 .LCFI4: + 502 .cfi_def_cfa_offset 8 + 503 .cfi_offset 4, -8 + 504 .cfi_offset 5, -4 + 505 .LBB38: + 506 .LBB39: + 507 .loc 2 60 0 + 508 0004 1068 ldr r0, [r2, #0] + 509 .LBE39: + 510 .LBE38: + 511 .loc 1 304 0 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 10 + + + 512 0006 D169 ldr r1, [r2, #28] + 513 .LVL35: + 514 .LBB43: + 515 .LBB40: + 516 .loc 2 62 0 + 517 0008 0368 ldr r3, [r0, #0] + 518 .LBE40: + 519 .LBE43: + 520 .loc 1 302 0 + 521 000a 1425 movs r5, #20 + 522 000c 8C68 ldr r4, [r1, #8] + 523 .LBB44: + 524 .LBB41: + 525 .loc 2 62 0 + 526 000e 1360 str r3, [r2, #0] + 527 .LBE41: + 528 .LBE44: + 529 .loc 1 302 0 + 530 0010 9561 str r5, [r2, #24] + 531 .LBB45: + 532 .LBB42: + 533 .loc 2 62 0 + 534 0012 5A60 str r2, [r3, #4] + 535 .LBE42: + 536 .LBE45: + 537 .loc 1 306 0 + 538 0014 D061 str r0, [r2, #28] + 539 .loc 1 307 0 + 540 0016 0122 movs r2, #1 + 541 0018 0277 strb r2, [r0, #28] + 542 .LVL36: + 543 .LBB46: + 544 .LBB47: + 545 .loc 1 91 0 + 546 001a 0022 movs r2, #0 + 547 001c 0346 mov r3, r0 + 548 001e 0A77 strb r2, [r1, #28] + 549 .LVL37: + 550 0020 00E0 b .L40 + 551 .LVL38: + 552 .L41: + 553 0022 1B68 ldr r3, [r3, #0] + 554 .LVL39: + 555 .L40: + 556 .loc 1 95 0 + 557 0024 9A68 ldr r2, [r3, #8] + 558 0026 A242 cmp r2, r4 + 559 0028 FBD2 bcs .L41 + 560 .loc 1 98 0 + 561 002a 5A68 ldr r2, [r3, #4] + 562 .loc 1 97 0 + 563 002c 0B60 str r3, [r1, #0] + 564 .loc 1 98 0 + 565 002e 4A60 str r2, [r1, #4] + 566 .loc 1 99 0 + 567 0030 1160 str r1, [r2, #0] + 568 0032 5960 str r1, [r3, #4] + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 11 + + + 569 .LBE47: + 570 .LBE46: + 571 .loc 1 310 0 + 572 0034 30BC pop {r4, r5} + 573 .loc 1 309 0 + 574 0036 FFF7FEBF b _port_switch + 575 .LVL40: + 576 .L43: + 577 003a 00BF .align 2 + 578 .L42: + 579 003c 00000000 .word .LANCHOR0 + 580 .cfi_endproc + 581 .LFE14: + 582 .size chSchDoReschedule, .-chSchDoReschedule + 583 .section .text.chSchRescheduleS,"ax",%progbits + 584 .align 2 + 585 .p2align 4,,15 + 586 .global chSchRescheduleS + 587 .thumb + 588 .thumb_func + 589 .type chSchRescheduleS, %function + 590 chSchRescheduleS: + 591 .LFB13: + 592 .loc 1 250 0 + 593 .cfi_startproc + 594 @ args = 0, pretend = 0, frame = 0 + 595 @ frame_needed = 0, uses_anonymous_args = 0 + 596 @ link register save eliminated. + 597 .loc 1 254 0 + 598 0000 044B ldr r3, .L47 + 599 0002 1A68 ldr r2, [r3, #0] + 600 0004 DB69 ldr r3, [r3, #28] + 601 0006 9268 ldr r2, [r2, #8] + 602 0008 9B68 ldr r3, [r3, #8] + 603 000a 9A42 cmp r2, r3 + 604 000c 00D8 bhi .L46 + 605 000e 7047 bx lr + 606 .L46: + 607 .loc 1 256 0 + 608 .loc 1 255 0 + 609 0010 FFF7FEBF b chSchDoReschedule + 610 .LVL41: + 611 .L48: + 612 .align 2 + 613 .L47: + 614 0014 00000000 .word .LANCHOR0 + 615 .cfi_endproc + 616 .LFE13: + 617 .size chSchRescheduleS, .-chSchRescheduleS + 618 .global rlist + 619 0018 AFF30080 .section .bss.rlist,"aw",%nobits + 619 AFF30080 + 620 .align 2 + 621 .set .LANCHOR0,. + 0 + 622 .type rlist, %object + 623 .size rlist, 32 + 624 rlist: + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 12 + + + 625 0000 00000000 .space 32 + 625 00000000 + 625 00000000 + 625 00000000 + 625 00000000 + 626 .text + 627 .Letext0: + 628 .file 3 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 629 .file 4 "../..//os/ports/GCC/ARMCMx/chtypes.h" + 630 .file 5 "../..//os/kernel/include/chlists.h" + 631 .file 6 "../..//os/kernel/include/chthreads.h" + 632 .file 7 "../..//os/ports/GCC/ARMCMx/chcore_v7m.h" + 633 .file 8 "../..//os/kernel/include/chvt.h" + 634 .file 9 "../..//os/kernel/include/chschd.h" + 635 .file 10 "../..//os/kernel/include/chsem.h" + 636 .file 11 "../..//os/kernel/include/chmtx.h" + 637 .section .debug_info,"",%progbits + 638 .Ldebug_info0: + 639 0000 F6080000 .4byte 0x8f6 + 640 0004 0200 .2byte 0x2 + 641 0006 00000000 .4byte .Ldebug_abbrev0 + 642 000a 04 .byte 0x4 + 643 000b 01 .uleb128 0x1 + 644 000c 07020000 .4byte .LASF82 + 645 0010 01 .byte 0x1 + 646 0011 67010000 .4byte .LASF83 + 647 0015 AF010000 .4byte .LASF84 + 648 0019 08010000 .4byte .Ldebug_ranges0+0x108 + 649 001d 00000000 .4byte 0 + 650 0021 00000000 .4byte 0 + 651 0025 00000000 .4byte .Ldebug_line0 + 652 0029 02 .uleb128 0x2 + 653 002a 04 .byte 0x4 + 654 002b 05 .byte 0x5 + 655 002c 696E7400 .ascii "int\000" + 656 0030 03 .uleb128 0x3 + 657 0031 04 .byte 0x4 + 658 0032 07 .byte 0x7 + 659 0033 D2000000 .4byte .LASF0 + 660 0037 03 .uleb128 0x3 + 661 0038 01 .byte 0x1 + 662 0039 06 .byte 0x6 + 663 003a 52000000 .4byte .LASF1 + 664 003e 04 .uleb128 0x4 + 665 003f 6B030000 .4byte .LASF5 + 666 0043 03 .byte 0x3 + 667 0044 2A .byte 0x2a + 668 0045 49000000 .4byte 0x49 + 669 0049 03 .uleb128 0x3 + 670 004a 01 .byte 0x1 + 671 004b 08 .byte 0x8 + 672 004c 44020000 .4byte .LASF2 + 673 0050 03 .uleb128 0x3 + 674 0051 02 .byte 0x2 + 675 0052 05 .byte 0x5 + 676 0053 65020000 .4byte .LASF3 + 677 0057 03 .uleb128 0x3 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 13 + + + 678 0058 02 .byte 0x2 + 679 0059 07 .byte 0x7 + 680 005a 1B010000 .4byte .LASF4 + 681 005e 04 .uleb128 0x4 + 682 005f 3C020000 .4byte .LASF6 + 683 0063 03 .byte 0x3 + 684 0064 4F .byte 0x4f + 685 0065 69000000 .4byte 0x69 + 686 0069 03 .uleb128 0x3 + 687 006a 04 .byte 0x4 + 688 006b 05 .byte 0x5 + 689 006c 6E000000 .4byte .LASF7 + 690 0070 04 .uleb128 0x4 + 691 0071 BF020000 .4byte .LASF8 + 692 0075 03 .byte 0x3 + 693 0076 50 .byte 0x50 + 694 0077 7B000000 .4byte 0x7b + 695 007b 03 .uleb128 0x3 + 696 007c 04 .byte 0x4 + 697 007d 07 .byte 0x7 + 698 007e FB000000 .4byte .LASF9 + 699 0082 03 .uleb128 0x3 + 700 0083 08 .byte 0x8 + 701 0084 05 .byte 0x5 + 702 0085 44000000 .4byte .LASF10 + 703 0089 03 .uleb128 0x3 + 704 008a 08 .byte 0x8 + 705 008b 07 .byte 0x7 + 706 008c 0D000000 .4byte .LASF11 + 707 0090 04 .uleb128 0x4 + 708 0091 41010000 .4byte .LASF12 + 709 0095 04 .byte 0x4 + 710 0096 2F .byte 0x2f + 711 0097 3E000000 .4byte 0x3e + 712 009b 04 .uleb128 0x4 + 713 009c 77000000 .4byte .LASF13 + 714 00a0 04 .byte 0x4 + 715 00a1 30 .byte 0x30 + 716 00a2 3E000000 .4byte 0x3e + 717 00a6 04 .uleb128 0x4 + 718 00a7 25020000 .4byte .LASF14 + 719 00ab 04 .byte 0x4 + 720 00ac 31 .byte 0x31 + 721 00ad 3E000000 .4byte 0x3e + 722 00b1 04 .uleb128 0x4 + 723 00b2 34020000 .4byte .LASF15 + 724 00b6 04 .byte 0x4 + 725 00b7 32 .byte 0x32 + 726 00b8 70000000 .4byte 0x70 + 727 00bc 04 .uleb128 0x4 + 728 00bd 3B010000 .4byte .LASF16 + 729 00c1 04 .byte 0x4 + 730 00c2 33 .byte 0x33 + 731 00c3 5E000000 .4byte 0x5e + 732 00c7 04 .uleb128 0x4 + 733 00c8 55010000 .4byte .LASF17 + 734 00cc 04 .byte 0x4 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 14 + + + 735 00cd 35 .byte 0x35 + 736 00ce 70000000 .4byte 0x70 + 737 00d2 04 .uleb128 0x4 + 738 00d3 01030000 .4byte .LASF18 + 739 00d7 04 .byte 0x4 + 740 00d8 36 .byte 0x36 + 741 00d9 70000000 .4byte 0x70 + 742 00dd 04 .uleb128 0x4 + 743 00de CC000000 .4byte .LASF19 + 744 00e2 04 .byte 0x4 + 745 00e3 37 .byte 0x37 + 746 00e4 5E000000 .4byte 0x5e + 747 00e8 04 .uleb128 0x4 + 748 00e9 94020000 .4byte .LASF20 + 749 00ed 05 .byte 0x5 + 750 00ee 2A .byte 0x2a + 751 00ef F3000000 .4byte 0xf3 + 752 00f3 05 .uleb128 0x5 + 753 00f4 94020000 .4byte .LASF20 + 754 00f8 48 .byte 0x48 + 755 00f9 06 .byte 0x6 + 756 00fa 5E .byte 0x5e + 757 00fb 0A020000 .4byte 0x20a + 758 00ff 06 .uleb128 0x6 + 759 0100 85020000 .4byte .LASF21 + 760 0104 06 .byte 0x6 + 761 0105 5F .byte 0x5f + 762 0106 2F020000 .4byte 0x22f + 763 010a 02 .byte 0x2 + 764 010b 23 .byte 0x23 + 765 010c 00 .uleb128 0 + 766 010d 06 .uleb128 0x6 + 767 010e 2D020000 .4byte .LASF22 + 768 0112 06 .byte 0x6 + 769 0113 61 .byte 0x61 + 770 0114 2F020000 .4byte 0x22f + 771 0118 02 .byte 0x2 + 772 0119 23 .byte 0x23 + 773 011a 04 .uleb128 0x4 + 774 011b 06 .uleb128 0x6 + 775 011c 2D000000 .4byte .LASF23 + 776 0120 06 .byte 0x6 + 777 0121 63 .byte 0x63 + 778 0122 B1000000 .4byte 0xb1 + 779 0126 02 .byte 0x2 + 780 0127 23 .byte 0x23 + 781 0128 08 .uleb128 0x8 + 782 0129 06 .uleb128 0x6 + 783 012a A8030000 .4byte .LASF24 + 784 012e 06 .byte 0x6 + 785 012f 64 .byte 0x64 + 786 0130 FC020000 .4byte 0x2fc + 787 0134 02 .byte 0x2 + 788 0135 23 .byte 0x23 + 789 0136 0C .uleb128 0xc + 790 0137 06 .uleb128 0x6 + 791 0138 80000000 .4byte .LASF25 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 15 + + + 792 013c 06 .byte 0x6 + 793 013d 66 .byte 0x66 + 794 013e 2F020000 .4byte 0x22f + 795 0142 02 .byte 0x2 + 796 0143 23 .byte 0x23 + 797 0144 10 .uleb128 0x10 + 798 0145 06 .uleb128 0x6 + 799 0146 A7010000 .4byte .LASF26 + 800 014a 06 .byte 0x6 + 801 014b 67 .byte 0x67 + 802 014c 2F020000 .4byte 0x22f + 803 0150 02 .byte 0x2 + 804 0151 23 .byte 0x23 + 805 0152 14 .uleb128 0x14 + 806 0153 06 .uleb128 0x6 + 807 0154 7A030000 .4byte .LASF27 + 808 0158 06 .byte 0x6 + 809 0159 6E .byte 0x6e + 810 015a D3040000 .4byte 0x4d3 + 811 015e 02 .byte 0x2 + 812 015f 23 .byte 0x23 + 813 0160 18 .uleb128 0x18 + 814 0161 06 .uleb128 0x6 + 815 0162 6F020000 .4byte .LASF28 + 816 0166 06 .byte 0x6 + 817 0167 79 .byte 0x79 + 818 0168 9B000000 .4byte 0x9b + 819 016c 02 .byte 0x2 + 820 016d 23 .byte 0x23 + 821 016e 1C .uleb128 0x1c + 822 016f 06 .uleb128 0x6 + 823 0170 8C020000 .4byte .LASF29 + 824 0174 06 .byte 0x6 + 825 0175 7D .byte 0x7d + 826 0176 90000000 .4byte 0x90 + 827 017a 02 .byte 0x2 + 828 017b 23 .byte 0x23 + 829 017c 1D .uleb128 0x1d + 830 017d 06 .uleb128 0x6 + 831 017e 54030000 .4byte .LASF30 + 832 0182 06 .byte 0x6 + 833 0183 82 .byte 0x82 + 834 0184 A6000000 .4byte 0xa6 + 835 0188 02 .byte 0x2 + 836 0189 23 .byte 0x23 + 837 018a 1E .uleb128 0x1e + 838 018b 06 .uleb128 0x6 + 839 018c 1F030000 .4byte .LASF31 + 840 0190 06 .byte 0x6 + 841 0191 89 .byte 0x89 + 842 0192 A7030000 .4byte 0x3a7 + 843 0196 02 .byte 0x2 + 844 0197 23 .byte 0x23 + 845 0198 20 .uleb128 0x20 + 846 0199 07 .uleb128 0x7 + 847 019a 705F7500 .ascii "p_u\000" + 848 019e 06 .byte 0x6 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 16 + + + 849 019f AE .byte 0xae + 850 01a0 9E040000 .4byte 0x49e + 851 01a4 02 .byte 0x2 + 852 01a5 23 .byte 0x23 + 853 01a6 24 .uleb128 0x24 + 854 01a7 06 .uleb128 0x6 + 855 01a8 AE030000 .4byte .LASF32 + 856 01ac 06 .byte 0x6 + 857 01ad B3 .byte 0xb3 + 858 01ae 57020000 .4byte 0x257 + 859 01b2 02 .byte 0x2 + 860 01b3 23 .byte 0x23 + 861 01b4 28 .uleb128 0x28 + 862 01b5 06 .uleb128 0x6 + 863 01b6 33030000 .4byte .LASF33 + 864 01ba 06 .byte 0x6 + 865 01bb B9 .byte 0xb9 + 866 01bc 35020000 .4byte 0x235 + 867 01c0 02 .byte 0x2 + 868 01c1 23 .byte 0x23 + 869 01c2 2C .uleb128 0x2c + 870 01c3 06 .uleb128 0x6 + 871 01c4 00000000 .4byte .LASF34 + 872 01c8 06 .byte 0x6 + 873 01c9 BD .byte 0xbd + 874 01ca BC000000 .4byte 0xbc + 875 01ce 02 .byte 0x2 + 876 01cf 23 .byte 0x23 + 877 01d0 34 .uleb128 0x34 + 878 01d1 06 .uleb128 0x6 + 879 01d2 B4020000 .4byte .LASF35 + 880 01d6 06 .byte 0x6 + 881 01d7 C3 .byte 0xc3 + 882 01d8 C7000000 .4byte 0xc7 + 883 01dc 02 .byte 0x2 + 884 01dd 23 .byte 0x23 + 885 01de 38 .uleb128 0x38 + 886 01df 06 .uleb128 0x6 + 887 01e0 5B020000 .4byte .LASF36 + 888 01e4 06 .byte 0x6 + 889 01e5 CA .byte 0xca + 890 01e6 E5040000 .4byte 0x4e5 + 891 01ea 02 .byte 0x2 + 892 01eb 23 .byte 0x23 + 893 01ec 3C .uleb128 0x3c + 894 01ed 06 .uleb128 0x6 + 895 01ee 0B030000 .4byte .LASF37 + 896 01f2 06 .byte 0x6 + 897 01f3 CE .byte 0xce + 898 01f4 B1000000 .4byte 0xb1 + 899 01f8 02 .byte 0x2 + 900 01f9 23 .byte 0x23 + 901 01fa 40 .uleb128 0x40 + 902 01fb 06 .uleb128 0x6 + 903 01fc 5E000000 .4byte .LASF38 + 904 0200 06 .byte 0x6 + 905 0201 D4 .byte 0xd4 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 17 + + + 906 0202 6D020000 .4byte 0x26d + 907 0206 02 .byte 0x2 + 908 0207 23 .byte 0x23 + 909 0208 44 .uleb128 0x44 + 910 0209 00 .byte 0 + 911 020a 08 .uleb128 0x8 + 912 020b 08 .byte 0x8 + 913 020c 05 .byte 0x5 + 914 020d 61 .byte 0x61 + 915 020e 2F020000 .4byte 0x22f + 916 0212 06 .uleb128 0x6 + 917 0213 85020000 .4byte .LASF21 + 918 0217 05 .byte 0x5 + 919 0218 62 .byte 0x62 + 920 0219 2F020000 .4byte 0x22f + 921 021d 02 .byte 0x2 + 922 021e 23 .byte 0x23 + 923 021f 00 .uleb128 0 + 924 0220 06 .uleb128 0x6 + 925 0221 2D020000 .4byte .LASF22 + 926 0225 05 .byte 0x5 + 927 0226 64 .byte 0x64 + 928 0227 2F020000 .4byte 0x22f + 929 022b 02 .byte 0x2 + 930 022c 23 .byte 0x23 + 931 022d 04 .uleb128 0x4 + 932 022e 00 .byte 0 + 933 022f 09 .uleb128 0x9 + 934 0230 04 .byte 0x4 + 935 0231 E8000000 .4byte 0xe8 + 936 0235 04 .uleb128 0x4 + 937 0236 F2010000 .4byte .LASF39 + 938 023a 05 .byte 0x5 + 939 023b 66 .byte 0x66 + 940 023c 0A020000 .4byte 0x20a + 941 0240 08 .uleb128 0x8 + 942 0241 04 .byte 0x4 + 943 0242 05 .byte 0x5 + 944 0243 6B .byte 0x6b + 945 0244 57020000 .4byte 0x257 + 946 0248 06 .uleb128 0x6 + 947 0249 85020000 .4byte .LASF21 + 948 024d 05 .byte 0x5 + 949 024e 6D .byte 0x6d + 950 024f 2F020000 .4byte 0x22f + 951 0253 02 .byte 0x2 + 952 0254 23 .byte 0x23 + 953 0255 00 .uleb128 0 + 954 0256 00 .byte 0 + 955 0257 04 .uleb128 0x4 + 956 0258 49010000 .4byte .LASF40 + 957 025c 05 .byte 0x5 + 958 025d 70 .byte 0x70 + 959 025e 40020000 .4byte 0x240 + 960 0262 04 .uleb128 0x4 + 961 0263 A9000000 .4byte .LASF41 + 962 0267 07 .byte 0x7 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 18 + + + 963 0268 D7 .byte 0xd7 + 964 0269 6D020000 .4byte 0x26d + 965 026d 0A .uleb128 0xa + 966 026e 04 .byte 0x4 + 967 026f 05 .uleb128 0x5 + 968 0270 2C030000 .4byte .LASF42 + 969 0274 24 .byte 0x24 + 970 0275 07 .byte 0x7 + 971 0276 FE .byte 0xfe + 972 0277 FC020000 .4byte 0x2fc + 973 027b 0B .uleb128 0xb + 974 027c 723400 .ascii "r4\000" + 975 027f 07 .byte 0x7 + 976 0280 1101 .2byte 0x111 + 977 0282 62020000 .4byte 0x262 + 978 0286 02 .byte 0x2 + 979 0287 23 .byte 0x23 + 980 0288 00 .uleb128 0 + 981 0289 0B .uleb128 0xb + 982 028a 723500 .ascii "r5\000" + 983 028d 07 .byte 0x7 + 984 028e 1201 .2byte 0x112 + 985 0290 62020000 .4byte 0x262 + 986 0294 02 .byte 0x2 + 987 0295 23 .byte 0x23 + 988 0296 04 .uleb128 0x4 + 989 0297 0B .uleb128 0xb + 990 0298 723600 .ascii "r6\000" + 991 029b 07 .byte 0x7 + 992 029c 1301 .2byte 0x113 + 993 029e 62020000 .4byte 0x262 + 994 02a2 02 .byte 0x2 + 995 02a3 23 .byte 0x23 + 996 02a4 08 .uleb128 0x8 + 997 02a5 0B .uleb128 0xb + 998 02a6 723700 .ascii "r7\000" + 999 02a9 07 .byte 0x7 + 1000 02aa 1401 .2byte 0x114 + 1001 02ac 62020000 .4byte 0x262 + 1002 02b0 02 .byte 0x2 + 1003 02b1 23 .byte 0x23 + 1004 02b2 0C .uleb128 0xc + 1005 02b3 0B .uleb128 0xb + 1006 02b4 723800 .ascii "r8\000" + 1007 02b7 07 .byte 0x7 + 1008 02b8 1501 .2byte 0x115 + 1009 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0x519 + 1445 0603 01 .byte 0x1 + 1446 0604 50 .byte 0x50 + 1447 0605 22 .uleb128 0x22 + 1448 0606 23050000 .4byte 0x523 + 1449 060a 01 .byte 0x1 + 1450 060b 53 .byte 0x53 + 1451 060c 00 .byte 0 + 1452 060d 23 .uleb128 0x23 + 1453 060e 01 .byte 0x1 + 1454 060f A6020000 .4byte .LASF76 + 1455 0613 01 .byte 0x1 + 1456 0614 72 .byte 0x72 + 1457 0615 01 .byte 0x1 + 1458 0616 00000000 .4byte .LFB9 + 1459 061a 28000000 .4byte .LFE9 + 1460 061e 39000000 .4byte .LLST3 + 1461 0622 01 .byte 0x1 + 1462 0623 7F060000 .4byte 0x67f + 1463 0627 24 .uleb128 0x24 + 1464 0628 52020000 .4byte .LASF74 + 1465 062c 01 .byte 0x1 + 1466 062d 72 .byte 0x72 + 1467 062e 9B000000 .4byte 0x9b + 1468 0632 59000000 .4byte .LLST4 + 1469 0636 25 .uleb128 0x25 + 1470 0637 6F747000 .ascii "otp\000" + 1471 063b 01 .byte 0x1 + 1472 063c 73 .byte 0x73 + 1473 063d 2F020000 .4byte 0x22f + 1474 0641 86000000 .4byte .LLST5 + 1475 0645 26 .uleb128 0x26 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 27 + + + 1476 0646 2E050000 .4byte 0x52e + 1477 064a 0A000000 .4byte .LBB21 + 1478 064e 00000000 .4byte .Ldebug_ranges0+0 + 1479 0652 01 .byte 0x1 + 1480 0653 7B .byte 0x7b + 1481 0654 74060000 .4byte 0x674 + 1482 0658 21 .uleb128 0x21 + 1483 0659 3F050000 .4byte 0x53f + 1484 065d 06 .byte 0x6 + 1485 065e 03 .byte 0x3 + 1486 065f 00000000 .4byte rlist + 1487 0663 9F .byte 0x9f + 1488 0664 27 .uleb128 0x27 + 1489 0665 20000000 .4byte .Ldebug_ranges0+0x20 + 1490 0669 1E .uleb128 0x1e + 1491 066a 4A050000 .4byte 0x54a + 1492 066e 99000000 .4byte .LLST6 + 1493 0672 00 .byte 0 + 1494 0673 00 .byte 0 + 1495 0674 28 .uleb128 0x28 + 1496 0675 28000000 .4byte .LVL14 + 1497 0679 01 .byte 0x1 + 1498 067a AC080000 .4byte 0x8ac + 1499 067e 00 .byte 0 + 1500 067f 29 .uleb128 0x29 + 1501 0680 01 .byte 0x1 + 1502 0681 81030000 .4byte .LASF88 + 1503 0685 01 .byte 0x1 + 1504 0686 B7 .byte 0xb7 + 1505 0687 01 .byte 0x1 + 1506 0688 BC000000 .4byte 0xbc + 1507 068c 00000000 .4byte .LFB11 + 1508 0690 40000000 .4byte .LFE11 + 1509 0694 AC000000 .4byte .LLST7 + 1510 0698 01 .byte 0x1 + 1511 0699 28070000 .4byte 0x728 + 1512 069d 24 .uleb128 0x24 + 1513 069e 52020000 .4byte .LASF74 + 1514 06a2 01 .byte 0x1 + 1515 06a3 B7 .byte 0xb7 + 1516 06a4 9B000000 .4byte 0x9b + 1517 06a8 D8000000 .4byte .LLST8 + 1518 06ac 24 .uleb128 0x24 + 1519 06ad 3E030000 .4byte .LASF75 + 1520 06b1 01 .byte 0x1 + 1521 06b2 B7 .byte 0xb7 + 1522 06b3 D2000000 .4byte 0xd2 + 1523 06b7 12010000 .4byte .LLST9 + 1524 06bb 2A .uleb128 0x2a + 1525 06bc 0A000000 .4byte .LBB27 + 1526 06c0 26000000 .4byte .LBE27 + 1527 06c4 1E070000 .4byte 0x71e + 1528 06c8 19 .uleb128 0x19 + 1529 06c9 767400 .ascii "vt\000" + 1530 06cc 01 .byte 0x1 + 1531 06cd BC .byte 0xbc + 1532 06ce 43030000 .4byte 0x343 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 28 + + + 1533 06d2 02 .byte 0x2 + 1534 06d3 91 .byte 0x91 + 1535 06d4 5C .sleb128 -36 + 1536 06d5 2B .uleb128 0x2b + 1537 06d6 16000000 .4byte .LVL17 + 1538 06da C6080000 .4byte 0x8c6 + 1539 06de F9060000 .4byte 0x6f9 + 1540 06e2 2C .uleb128 0x2c + 1541 06e3 01 .byte 0x1 + 1542 06e4 52 .byte 0x52 + 1543 06e5 05 .byte 0x5 + 1544 06e6 03 .byte 0x3 + 1545 06e7 00000000 .4byte wakeup + 1546 06eb 2C .uleb128 0x2c + 1547 06ec 01 .byte 0x1 + 1548 06ed 51 .byte 0x51 + 1549 06ee 03 .byte 0x3 + 1550 06ef F3 .byte 0xf3 + 1551 06f0 01 .uleb128 0x1 + 1552 06f1 51 .byte 0x51 + 1553 06f2 2C .uleb128 0x2c + 1554 06f3 01 .byte 0x1 + 1555 06f4 50 .byte 0x50 + 1556 06f5 02 .byte 0x2 + 1557 06f6 91 .byte 0x91 + 1558 06f7 5C .sleb128 -36 + 1559 06f8 00 .byte 0 + 1560 06f9 2B .uleb128 0x2b + 1561 06fa 1C000000 .4byte .LVL18 + 1562 06fe 0D060000 .4byte 0x60d + 1563 0702 0D070000 .4byte 0x70d + 1564 0706 2C .uleb128 0x2c + 1565 0707 01 .byte 0x1 + 1566 0708 50 .byte 0x50 + 1567 0709 02 .byte 0x2 + 1568 070a 75 .byte 0x75 + 1569 070b 00 .sleb128 0 + 1570 070c 00 .byte 0 + 1571 070d 2D .uleb128 0x2d + 1572 070e 26000000 .4byte .LVL19 + 1573 0712 E9080000 .4byte 0x8e9 + 1574 0716 2C .uleb128 0x2c + 1575 0717 01 .byte 0x1 + 1576 0718 50 .byte 0x50 + 1577 0719 02 .byte 0x2 + 1578 071a 91 .byte 0x91 + 1579 071b 5C .sleb128 -36 + 1580 071c 00 .byte 0 + 1581 071d 00 .byte 0 + 1582 071e 2E .uleb128 0x2e + 1583 071f 32000000 .4byte .LVL21 + 1584 0723 0D060000 .4byte 0x60d + 1585 0727 00 .byte 0 + 1586 0728 23 .uleb128 0x23 + 1587 0729 01 .byte 0x1 + 1588 072a 2E010000 .4byte .LASF77 + 1589 072e 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 29 + + + 1590 072f DB .byte 0xdb + 1591 0730 01 .byte 0x1 + 1592 0731 00000000 .4byte .LFB12 + 1593 0735 5C000000 .4byte .LFE12 + 1594 0739 4C010000 .4byte .LLST10 + 1595 073d 01 .byte 0x1 + 1596 073e DF070000 .4byte 0x7df + 1597 0742 2F .uleb128 0x2f + 1598 0743 6E747000 .ascii "ntp\000" + 1599 0747 01 .byte 0x1 + 1600 0748 DB .byte 0xdb + 1601 0749 2F020000 .4byte 0x22f + 1602 074d 6C010000 .4byte .LLST11 + 1603 0751 2F .uleb128 0x2f + 1604 0752 6D736700 .ascii "msg\000" + 1605 0756 01 .byte 0x1 + 1606 0757 DB .byte 0xdb + 1607 0758 BC000000 .4byte 0xbc + 1608 075c 8A010000 .4byte .LLST12 + 1609 0760 26 .uleb128 0x26 + 1610 0761 07050000 .4byte 0x507 + 1611 0765 0C000000 .4byte .LBB28 + 1612 0769 40000000 .4byte .Ldebug_ranges0+0x40 + 1613 076d 01 .byte 0x1 + 1614 076e E5 .byte 0xe5 + 1615 076f 8C070000 .4byte 0x78c + 1616 0773 1B .uleb128 0x1b + 1617 0774 19050000 .4byte 0x519 + 1618 0778 B7010000 .4byte .LLST13 + 1619 077c 27 .uleb128 0x27 + 1620 077d 58000000 .4byte .Ldebug_ranges0+0x58 + 1621 0781 1E .uleb128 0x1e + 1622 0782 23050000 .4byte 0x523 + 1623 0786 CA010000 .4byte .LLST14 + 1624 078a 00 .byte 0 + 1625 078b 00 .byte 0 + 1626 078c 27 .uleb128 0x27 + 1627 078d 70000000 .4byte .Ldebug_ranges0+0x70 + 1628 0791 16 .uleb128 0x16 + 1629 0792 6F747000 .ascii "otp\000" + 1630 0796 01 .byte 0x1 + 1631 0797 E7 .byte 0xe7 + 1632 0798 2F020000 .4byte 0x22f + 1633 079c 26 .uleb128 0x26 + 1634 079d 07050000 .4byte 0x507 + 1635 07a1 2E000000 .4byte .LBB33 + 1636 07a5 88000000 .4byte .Ldebug_ranges0+0x88 + 1637 07a9 01 .byte 0x1 + 1638 07aa E7 .byte 0xe7 + 1639 07ab C6070000 .4byte 0x7c6 + 1640 07af 21 .uleb128 0x21 + 1641 07b0 19050000 .4byte 0x519 + 1642 07b4 01 .byte 0x1 + 1643 07b5 56 .byte 0x56 + 1644 07b6 27 .uleb128 0x27 + 1645 07b7 A0000000 .4byte .Ldebug_ranges0+0xa0 + 1646 07bb 1E .uleb128 0x1e + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 30 + + + 1647 07bc 23050000 .4byte 0x523 + 1648 07c0 ED010000 .4byte .LLST15 + 1649 07c4 00 .byte 0 + 1650 07c5 00 .byte 0 + 1651 07c6 30 .uleb128 0x30 + 1652 07c7 58000000 .4byte .LVL34 + 1653 07cb 01 .byte 0x1 + 1654 07cc AC080000 .4byte 0x8ac + 1655 07d0 2C .uleb128 0x2c + 1656 07d1 01 .byte 0x1 + 1657 07d2 51 .byte 0x51 + 1658 07d3 02 .byte 0x2 + 1659 07d4 76 .byte 0x76 + 1660 07d5 00 .sleb128 0 + 1661 07d6 2C .uleb128 0x2c + 1662 07d7 01 .byte 0x1 + 1663 07d8 50 .byte 0x50 + 1664 07d9 02 .byte 0x2 + 1665 07da 74 .byte 0x74 + 1666 07db 00 .sleb128 0 + 1667 07dc 00 .byte 0 + 1668 07dd 00 .byte 0 + 1669 07de 00 .byte 0 + 1670 07df 31 .uleb128 0x31 + 1671 07e0 01 .byte 0x1 + 1672 07e1 BA000000 .4byte .LASF78 + 1673 07e5 01 .byte 0x1 + 1674 07e6 2A01 .2byte 0x12a + 1675 07e8 01 .byte 0x1 + 1676 07e9 00000000 .4byte .LFB14 + 1677 07ed 40000000 .4byte .LFE14 + 1678 07f1 1C020000 .4byte .LLST16 + 1679 07f5 01 .byte 0x1 + 1680 07f6 76080000 .4byte 0x876 + 1681 07fa 32 .uleb128 0x32 + 1682 07fb 6F747000 .ascii "otp\000" + 1683 07ff 01 .byte 0x1 + 1684 0800 2B01 .2byte 0x12b + 1685 0802 2F020000 .4byte 0x22f + 1686 0806 3C020000 .4byte .LLST17 + 1687 080a 33 .uleb128 0x33 + 1688 080b 2E050000 .4byte 0x52e + 1689 080f 04000000 .4byte .LBB38 + 1690 0813 B8000000 .4byte .Ldebug_ranges0+0xb8 + 1691 0817 01 .byte 0x1 + 1692 0818 3201 .2byte 0x132 + 1693 081a 3A080000 .4byte 0x83a + 1694 081e 21 .uleb128 0x21 + 1695 081f 3F050000 .4byte 0x53f + 1696 0823 06 .byte 0x6 + 1697 0824 03 .byte 0x3 + 1698 0825 00000000 .4byte rlist + 1699 0829 9F .byte 0x9f + 1700 082a 27 .uleb128 0x27 + 1701 082b E0000000 .4byte .Ldebug_ranges0+0xe0 + 1702 082f 1E .uleb128 0x1e + 1703 0830 4A050000 .4byte 0x54a + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 31 + + + 1704 0834 4F020000 .4byte .LLST18 + 1705 0838 00 .byte 0 + 1706 0839 00 .byte 0 + 1707 083a 34 .uleb128 0x34 + 1708 083b 07050000 .4byte 0x507 + 1709 083f 1A000000 .4byte .LBB46 + 1710 0843 34000000 .4byte .LBE46 + 1711 0847 01 .byte 0x1 + 1712 0848 3401 .2byte 0x134 + 1713 084a 6B080000 .4byte 0x86b + 1714 084e 1B .uleb128 0x1b + 1715 084f 19050000 .4byte 0x519 + 1716 0853 62020000 .4byte .LLST19 + 1717 0857 1D .uleb128 0x1d + 1718 0858 1A000000 .4byte .LBB47 + 1719 085c 34000000 .4byte .LBE47 + 1720 0860 1E .uleb128 0x1e + 1721 0861 23050000 .4byte 0x523 + 1722 0865 75020000 .4byte .LLST20 + 1723 0869 00 .byte 0 + 1724 086a 00 .byte 0 + 1725 086b 28 .uleb128 0x28 + 1726 086c 3A000000 .4byte .LVL40 + 1727 0870 01 .byte 0x1 + 1728 0871 AC080000 .4byte 0x8ac + 1729 0875 00 .byte 0 + 1730 0876 35 .uleb128 0x35 + 1731 0877 01 .byte 0x1 + 1732 0878 90000000 .4byte .LASF79 + 1733 087c 01 .byte 0x1 + 1734 087d FA .byte 0xfa + 1735 087e 01 .byte 0x1 + 1736 087f 00000000 .4byte .LFB13 + 1737 0883 18000000 .4byte .LFE13 + 1738 0887 02 .byte 0x2 + 1739 0888 7D .byte 0x7d + 1740 0889 00 .sleb128 0 + 1741 088a 01 .byte 0x1 + 1742 088b 9A080000 .4byte 0x89a + 1743 088f 28 .uleb128 0x28 + 1744 0890 14000000 .4byte .LVL41 + 1745 0894 01 .byte 0x1 + 1746 0895 DF070000 .4byte 0x7df + 1747 0899 00 .byte 0 + 1748 089a 36 .uleb128 0x36 + 1749 089b 65030000 .4byte .LASF89 + 1750 089f 01 .byte 0x1 + 1751 08a0 2F .byte 0x2f + 1752 08a1 17040000 .4byte 0x417 + 1753 08a5 01 .byte 0x1 + 1754 08a6 05 .byte 0x5 + 1755 08a7 03 .byte 0x3 + 1756 08a8 00000000 .4byte rlist + 1757 08ac 37 .uleb128 0x37 + 1758 08ad 01 .byte 0x1 + 1759 08ae EE000000 .4byte .LASF80 + 1760 08b2 07 .byte 0x7 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 32 + + + 1761 08b3 F801 .2byte 0x1f8 + 1762 08b5 01 .byte 0x1 + 1763 08b6 01 .byte 0x1 + 1764 08b7 C6080000 .4byte 0x8c6 + 1765 08bb 0E .uleb128 0xe + 1766 08bc 2F020000 .4byte 0x22f + 1767 08c0 0E .uleb128 0xe + 1768 08c1 2F020000 .4byte 0x22f + 1769 08c5 00 .byte 0 + 1770 08c6 38 .uleb128 0x38 + 1771 08c7 01 .byte 0x1 + 1772 08c8 9E010000 .4byte .LASF81 + 1773 08cc 08 .byte 0x8 + 1774 08cd BF .byte 0xbf + 1775 08ce 01 .byte 0x1 + 1776 08cf 01 .byte 0x1 + 1777 08d0 E9080000 .4byte 0x8e9 + 1778 08d4 0E .uleb128 0xe + 1779 08d5 A1030000 .4byte 0x3a1 + 1780 08d9 0E .uleb128 0xe + 1781 08da D2000000 .4byte 0xd2 + 1782 08de 0E .uleb128 0xe + 1783 08df 26030000 .4byte 0x326 + 1784 08e3 0E .uleb128 0xe + 1785 08e4 6D020000 .4byte 0x26d + 1786 08e8 00 .byte 0 + 1787 08e9 39 .uleb128 0x39 + 1788 08ea 01 .byte 0x1 + 1789 08eb 9B020000 .4byte .LASF90 + 1790 08ef 08 .byte 0x8 + 1791 08f0 C0 .byte 0xc0 + 1792 08f1 01 .byte 0x1 + 1793 08f2 01 .byte 0x1 + 1794 08f3 0E .uleb128 0xe + 1795 08f4 A1030000 .4byte 0x3a1 + 1796 08f8 00 .byte 0 + 1797 08f9 00 .byte 0 + 1798 .section .debug_abbrev,"",%progbits + 1799 .Ldebug_abbrev0: + 1800 0000 01 .uleb128 0x1 + 1801 0001 11 .uleb128 0x11 + 1802 0002 01 .byte 0x1 + 1803 0003 25 .uleb128 0x25 + 1804 0004 0E .uleb128 0xe + 1805 0005 13 .uleb128 0x13 + 1806 0006 0B .uleb128 0xb + 1807 0007 03 .uleb128 0x3 + 1808 0008 0E .uleb128 0xe + 1809 0009 1B .uleb128 0x1b + 1810 000a 0E .uleb128 0xe + 1811 000b 55 .uleb128 0x55 + 1812 000c 06 .uleb128 0x6 + 1813 000d 11 .uleb128 0x11 + 1814 000e 01 .uleb128 0x1 + 1815 000f 52 .uleb128 0x52 + 1816 0010 01 .uleb128 0x1 + 1817 0011 10 .uleb128 0x10 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 33 + + + 1818 0012 06 .uleb128 0x6 + 1819 0013 00 .byte 0 + 1820 0014 00 .byte 0 + 1821 0015 02 .uleb128 0x2 + 1822 0016 24 .uleb128 0x24 + 1823 0017 00 .byte 0 + 1824 0018 0B .uleb128 0xb + 1825 0019 0B .uleb128 0xb + 1826 001a 3E .uleb128 0x3e + 1827 001b 0B .uleb128 0xb + 1828 001c 03 .uleb128 0x3 + 1829 001d 08 .uleb128 0x8 + 1830 001e 00 .byte 0 + 1831 001f 00 .byte 0 + 1832 0020 03 .uleb128 0x3 + 1833 0021 24 .uleb128 0x24 + 1834 0022 00 .byte 0 + 1835 0023 0B .uleb128 0xb + 1836 0024 0B .uleb128 0xb + 1837 0025 3E .uleb128 0x3e + 1838 0026 0B .uleb128 0xb + 1839 0027 03 .uleb128 0x3 + 1840 0028 0E .uleb128 0xe + 1841 0029 00 .byte 0 + 1842 002a 00 .byte 0 + 1843 002b 04 .uleb128 0x4 + 1844 002c 16 .uleb128 0x16 + 1845 002d 00 .byte 0 + 1846 002e 03 .uleb128 0x3 + 1847 002f 0E .uleb128 0xe + 1848 0030 3A .uleb128 0x3a + 1849 0031 0B .uleb128 0xb + 1850 0032 3B .uleb128 0x3b + 1851 0033 0B .uleb128 0xb + 1852 0034 49 .uleb128 0x49 + 1853 0035 13 .uleb128 0x13 + 1854 0036 00 .byte 0 + 1855 0037 00 .byte 0 + 1856 0038 05 .uleb128 0x5 + 1857 0039 13 .uleb128 0x13 + 1858 003a 01 .byte 0x1 + 1859 003b 03 .uleb128 0x3 + 1860 003c 0E .uleb128 0xe + 1861 003d 0B .uleb128 0xb + 1862 003e 0B .uleb128 0xb + 1863 003f 3A .uleb128 0x3a + 1864 0040 0B .uleb128 0xb + 1865 0041 3B .uleb128 0x3b + 1866 0042 0B .uleb128 0xb + 1867 0043 01 .uleb128 0x1 + 1868 0044 13 .uleb128 0x13 + 1869 0045 00 .byte 0 + 1870 0046 00 .byte 0 + 1871 0047 06 .uleb128 0x6 + 1872 0048 0D .uleb128 0xd + 1873 0049 00 .byte 0 + 1874 004a 03 .uleb128 0x3 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 34 + + + 1875 004b 0E .uleb128 0xe + 1876 004c 3A .uleb128 0x3a + 1877 004d 0B .uleb128 0xb + 1878 004e 3B .uleb128 0x3b + 1879 004f 0B .uleb128 0xb + 1880 0050 49 .uleb128 0x49 + 1881 0051 13 .uleb128 0x13 + 1882 0052 38 .uleb128 0x38 + 1883 0053 0A .uleb128 0xa + 1884 0054 00 .byte 0 + 1885 0055 00 .byte 0 + 1886 0056 07 .uleb128 0x7 + 1887 0057 0D .uleb128 0xd + 1888 0058 00 .byte 0 + 1889 0059 03 .uleb128 0x3 + 1890 005a 08 .uleb128 0x8 + 1891 005b 3A .uleb128 0x3a + 1892 005c 0B .uleb128 0xb + 1893 005d 3B .uleb128 0x3b + 1894 005e 0B .uleb128 0xb + 1895 005f 49 .uleb128 0x49 + 1896 0060 13 .uleb128 0x13 + 1897 0061 38 .uleb128 0x38 + 1898 0062 0A .uleb128 0xa + 1899 0063 00 .byte 0 + 1900 0064 00 .byte 0 + 1901 0065 08 .uleb128 0x8 + 1902 0066 13 .uleb128 0x13 + 1903 0067 01 .byte 0x1 + 1904 0068 0B .uleb128 0xb + 1905 0069 0B .uleb128 0xb + 1906 006a 3A .uleb128 0x3a + 1907 006b 0B .uleb128 0xb + 1908 006c 3B .uleb128 0x3b + 1909 006d 0B .uleb128 0xb + 1910 006e 01 .uleb128 0x1 + 1911 006f 13 .uleb128 0x13 + 1912 0070 00 .byte 0 + 1913 0071 00 .byte 0 + 1914 0072 09 .uleb128 0x9 + 1915 0073 0F .uleb128 0xf + 1916 0074 00 .byte 0 + 1917 0075 0B .uleb128 0xb + 1918 0076 0B .uleb128 0xb + 1919 0077 49 .uleb128 0x49 + 1920 0078 13 .uleb128 0x13 + 1921 0079 00 .byte 0 + 1922 007a 00 .byte 0 + 1923 007b 0A .uleb128 0xa + 1924 007c 0F .uleb128 0xf + 1925 007d 00 .byte 0 + 1926 007e 0B .uleb128 0xb + 1927 007f 0B .uleb128 0xb + 1928 0080 00 .byte 0 + 1929 0081 00 .byte 0 + 1930 0082 0B .uleb128 0xb + 1931 0083 0D .uleb128 0xd + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 35 + + + 1932 0084 00 .byte 0 + 1933 0085 03 .uleb128 0x3 + 1934 0086 08 .uleb128 0x8 + 1935 0087 3A .uleb128 0x3a + 1936 0088 0B .uleb128 0xb + 1937 0089 3B .uleb128 0x3b + 1938 008a 05 .uleb128 0x5 + 1939 008b 49 .uleb128 0x49 + 1940 008c 13 .uleb128 0x13 + 1941 008d 38 .uleb128 0x38 + 1942 008e 0A .uleb128 0xa + 1943 008f 00 .byte 0 + 1944 0090 00 .byte 0 + 1945 0091 0C .uleb128 0xc + 1946 0092 13 .uleb128 0x13 + 1947 0093 01 .byte 0x1 + 1948 0094 03 .uleb128 0x3 + 1949 0095 0E .uleb128 0xe + 1950 0096 0B .uleb128 0xb + 1951 0097 0B .uleb128 0xb + 1952 0098 3A .uleb128 0x3a + 1953 0099 0B .uleb128 0xb + 1954 009a 3B .uleb128 0x3b + 1955 009b 05 .uleb128 0x5 + 1956 009c 01 .uleb128 0x1 + 1957 009d 13 .uleb128 0x13 + 1958 009e 00 .byte 0 + 1959 009f 00 .byte 0 + 1960 00a0 0D .uleb128 0xd + 1961 00a1 15 .uleb128 0x15 + 1962 00a2 01 .byte 0x1 + 1963 00a3 27 .uleb128 0x27 + 1964 00a4 0C .uleb128 0xc + 1965 00a5 01 .uleb128 0x1 + 1966 00a6 13 .uleb128 0x13 + 1967 00a7 00 .byte 0 + 1968 00a8 00 .byte 0 + 1969 00a9 0E .uleb128 0xe + 1970 00aa 05 .uleb128 0x5 + 1971 00ab 00 .byte 0 + 1972 00ac 49 .uleb128 0x49 + 1973 00ad 13 .uleb128 0x13 + 1974 00ae 00 .byte 0 + 1975 00af 00 .byte 0 + 1976 00b0 0F .uleb128 0xf + 1977 00b1 35 .uleb128 0x35 + 1978 00b2 00 .byte 0 + 1979 00b3 49 .uleb128 0x49 + 1980 00b4 13 .uleb128 0x13 + 1981 00b5 00 .byte 0 + 1982 00b6 00 .byte 0 + 1983 00b7 10 .uleb128 0x10 + 1984 00b8 17 .uleb128 0x17 + 1985 00b9 01 .byte 0x1 + 1986 00ba 0B .uleb128 0xb + 1987 00bb 0B .uleb128 0xb + 1988 00bc 3A .uleb128 0x3a + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 36 + + + 1989 00bd 0B .uleb128 0xb + 1990 00be 3B .uleb128 0x3b + 1991 00bf 0B .uleb128 0xb + 1992 00c0 01 .uleb128 0x1 + 1993 00c1 13 .uleb128 0x13 + 1994 00c2 00 .byte 0 + 1995 00c3 00 .byte 0 + 1996 00c4 11 .uleb128 0x11 + 1997 00c5 0D .uleb128 0xd + 1998 00c6 00 .byte 0 + 1999 00c7 03 .uleb128 0x3 + 2000 00c8 0E .uleb128 0xe + 2001 00c9 3A .uleb128 0x3a + 2002 00ca 0B .uleb128 0xb + 2003 00cb 3B .uleb128 0x3b + 2004 00cc 0B .uleb128 0xb + 2005 00cd 49 .uleb128 0x49 + 2006 00ce 13 .uleb128 0x13 + 2007 00cf 00 .byte 0 + 2008 00d0 00 .byte 0 + 2009 00d1 12 .uleb128 0x12 + 2010 00d2 26 .uleb128 0x26 + 2011 00d3 00 .byte 0 + 2012 00d4 49 .uleb128 0x49 + 2013 00d5 13 .uleb128 0x13 + 2014 00d6 00 .byte 0 + 2015 00d7 00 .byte 0 + 2016 00d8 13 .uleb128 0x13 + 2017 00d9 2E .uleb128 0x2e + 2018 00da 01 .byte 0x1 + 2019 00db 03 .uleb128 0x3 + 2020 00dc 0E .uleb128 0xe + 2021 00dd 3A .uleb128 0x3a + 2022 00de 0B .uleb128 0xb + 2023 00df 3B .uleb128 0x3b + 2024 00e0 0B .uleb128 0xb + 2025 00e1 27 .uleb128 0x27 + 2026 00e2 0C .uleb128 0xc + 2027 00e3 49 .uleb128 0x49 + 2028 00e4 13 .uleb128 0x13 + 2029 00e5 20 .uleb128 0x20 + 2030 00e6 0B .uleb128 0xb + 2031 00e7 01 .uleb128 0x1 + 2032 00e8 13 .uleb128 0x13 + 2033 00e9 00 .byte 0 + 2034 00ea 00 .byte 0 + 2035 00eb 14 .uleb128 0x14 + 2036 00ec 05 .uleb128 0x5 + 2037 00ed 00 .byte 0 + 2038 00ee 03 .uleb128 0x3 + 2039 00ef 08 .uleb128 0x8 + 2040 00f0 3A .uleb128 0x3a + 2041 00f1 0B .uleb128 0xb + 2042 00f2 3B .uleb128 0x3b + 2043 00f3 0B .uleb128 0xb + 2044 00f4 49 .uleb128 0x49 + 2045 00f5 13 .uleb128 0x13 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 37 + + + 2046 00f6 00 .byte 0 + 2047 00f7 00 .byte 0 + 2048 00f8 15 .uleb128 0x15 + 2049 00f9 2E .uleb128 0x2e + 2050 00fa 01 .byte 0x1 + 2051 00fb 3F .uleb128 0x3f + 2052 00fc 0C .uleb128 0xc + 2053 00fd 03 .uleb128 0x3 + 2054 00fe 0E .uleb128 0xe + 2055 00ff 3A .uleb128 0x3a + 2056 0100 0B .uleb128 0xb + 2057 0101 3B .uleb128 0x3b + 2058 0102 0B .uleb128 0xb + 2059 0103 27 .uleb128 0x27 + 2060 0104 0C .uleb128 0xc + 2061 0105 49 .uleb128 0x49 + 2062 0106 13 .uleb128 0x13 + 2063 0107 20 .uleb128 0x20 + 2064 0108 0B .uleb128 0xb + 2065 0109 01 .uleb128 0x1 + 2066 010a 13 .uleb128 0x13 + 2067 010b 00 .byte 0 + 2068 010c 00 .byte 0 + 2069 010d 16 .uleb128 0x16 + 2070 010e 34 .uleb128 0x34 + 2071 010f 00 .byte 0 + 2072 0110 03 .uleb128 0x3 + 2073 0111 08 .uleb128 0x8 + 2074 0112 3A .uleb128 0x3a + 2075 0113 0B .uleb128 0xb + 2076 0114 3B .uleb128 0x3b + 2077 0115 0B .uleb128 0xb + 2078 0116 49 .uleb128 0x49 + 2079 0117 13 .uleb128 0x13 + 2080 0118 00 .byte 0 + 2081 0119 00 .byte 0 + 2082 011a 17 .uleb128 0x17 + 2083 011b 2E .uleb128 0x2e + 2084 011c 01 .byte 0x1 + 2085 011d 03 .uleb128 0x3 + 2086 011e 0E .uleb128 0xe + 2087 011f 3A .uleb128 0x3a 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0143 00 .byte 0 + 2123 0144 03 .uleb128 0x3 + 2124 0145 08 .uleb128 0x8 + 2125 0146 3A .uleb128 0x3a + 2126 0147 0B .uleb128 0xb + 2127 0148 3B .uleb128 0x3b + 2128 0149 0B .uleb128 0xb + 2129 014a 49 .uleb128 0x49 + 2130 014b 13 .uleb128 0x13 + 2131 014c 02 .uleb128 0x2 + 2132 014d 0A .uleb128 0xa + 2133 014e 00 .byte 0 + 2134 014f 00 .byte 0 + 2135 0150 1A .uleb128 0x1a + 2136 0151 1D .uleb128 0x1d + 2137 0152 01 .byte 0x1 + 2138 0153 31 .uleb128 0x31 + 2139 0154 13 .uleb128 0x13 + 2140 0155 11 .uleb128 0x11 + 2141 0156 01 .uleb128 0x1 + 2142 0157 12 .uleb128 0x12 + 2143 0158 01 .uleb128 0x1 + 2144 0159 58 .uleb128 0x58 + 2145 015a 0B .uleb128 0xb + 2146 015b 59 .uleb128 0x59 + 2147 015c 0B .uleb128 0xb + 2148 015d 01 .uleb128 0x1 + 2149 015e 13 .uleb128 0x13 + 2150 015f 00 .byte 0 + 2151 0160 00 .byte 0 + 2152 0161 1B .uleb128 0x1b + 2153 0162 05 .uleb128 0x5 + 2154 0163 00 .byte 0 + 2155 0164 31 .uleb128 0x31 + 2156 0165 13 .uleb128 0x13 + 2157 0166 02 .uleb128 0x2 + 2158 0167 06 .uleb128 0x6 + 2159 0168 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 39 + + + 2160 0169 00 .byte 0 + 2161 016a 1C .uleb128 0x1c + 2162 016b 1D .uleb128 0x1d + 2163 016c 01 .byte 0x1 + 2164 016d 31 .uleb128 0x31 + 2165 016e 13 .uleb128 0x13 + 2166 016f 11 .uleb128 0x11 + 2167 0170 01 .uleb128 0x1 + 2168 0171 12 .uleb128 0x12 + 2169 0172 01 .uleb128 0x1 + 2170 0173 58 .uleb128 0x58 + 2171 0174 0B .uleb128 0xb + 2172 0175 59 .uleb128 0x59 + 2173 0176 0B .uleb128 0xb + 2174 0177 00 .byte 0 + 2175 0178 00 .byte 0 + 2176 0179 1D .uleb128 0x1d + 2177 017a 0B .uleb128 0xb + 2178 017b 01 .byte 0x1 + 2179 017c 11 .uleb128 0x11 + 2180 017d 01 .uleb128 0x1 + 2181 017e 12 .uleb128 0x12 + 2182 017f 01 .uleb128 0x1 + 2183 0180 00 .byte 0 + 2184 0181 00 .byte 0 + 2185 0182 1E .uleb128 0x1e + 2186 0183 34 .uleb128 0x34 + 2187 0184 00 .byte 0 + 2188 0185 31 .uleb128 0x31 + 2189 0186 13 .uleb128 0x13 + 2190 0187 02 .uleb128 0x2 + 2191 0188 06 .uleb128 0x6 + 2192 0189 00 .byte 0 + 2193 018a 00 .byte 0 + 2194 018b 1F .uleb128 0x1f + 2195 018c 2E .uleb128 0x2e + 2196 018d 00 .byte 0 + 2197 018e 3F .uleb128 0x3f + 2198 018f 0C .uleb128 0xc + 2199 0190 03 .uleb128 0x3 + 2200 0191 0E .uleb128 0xe + 2201 0192 3A .uleb128 0x3a + 2202 0193 0B .uleb128 0xb + 2203 0194 3B .uleb128 0x3b + 2204 0195 0B .uleb128 0xb + 2205 0196 27 .uleb128 0x27 + 2206 0197 0C .uleb128 0xc + 2207 0198 11 .uleb128 0x11 + 2208 0199 01 .uleb128 0x1 + 2209 019a 12 .uleb128 0x12 + 2210 019b 01 .uleb128 0x1 + 2211 019c 40 .uleb128 0x40 + 2212 019d 0A .uleb128 0xa + 2213 019e 9742 .uleb128 0x2117 + 2214 01a0 0C .uleb128 0xc + 2215 01a1 00 .byte 0 + 2216 01a2 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 40 + + + 2217 01a3 20 .uleb128 0x20 + 2218 01a4 2E .uleb128 0x2e + 2219 01a5 01 .byte 0x1 + 2220 01a6 31 .uleb128 0x31 + 2221 01a7 13 .uleb128 0x13 + 2222 01a8 11 .uleb128 0x11 + 2223 01a9 01 .uleb128 0x1 + 2224 01aa 12 .uleb128 0x12 + 2225 01ab 01 .uleb128 0x1 + 2226 01ac 40 .uleb128 0x40 + 2227 01ad 0A .uleb128 0xa + 2228 01ae 9742 .uleb128 0x2117 + 2229 01b0 0C .uleb128 0xc + 2230 01b1 01 .uleb128 0x1 + 2231 01b2 13 .uleb128 0x13 + 2232 01b3 00 .byte 0 + 2233 01b4 00 .byte 0 + 2234 01b5 21 .uleb128 0x21 + 2235 01b6 05 .uleb128 0x5 + 2236 01b7 00 .byte 0 + 2237 01b8 31 .uleb128 0x31 + 2238 01b9 13 .uleb128 0x13 + 2239 01ba 02 .uleb128 0x2 + 2240 01bb 0A .uleb128 0xa + 2241 01bc 00 .byte 0 + 2242 01bd 00 .byte 0 + 2243 01be 22 .uleb128 0x22 + 2244 01bf 34 .uleb128 0x34 + 2245 01c0 00 .byte 0 + 2246 01c1 31 .uleb128 0x31 + 2247 01c2 13 .uleb128 0x13 + 2248 01c3 02 .uleb128 0x2 + 2249 01c4 0A .uleb128 0xa + 2250 01c5 00 .byte 0 + 2251 01c6 00 .byte 0 + 2252 01c7 23 .uleb128 0x23 + 2253 01c8 2E .uleb128 0x2e + 2254 01c9 01 .byte 0x1 + 2255 01ca 3F .uleb128 0x3f + 2256 01cb 0C .uleb128 0xc + 2257 01cc 03 .uleb128 0x3 + 2258 01cd 0E .uleb128 0xe + 2259 01ce 3A .uleb128 0x3a + 2260 01cf 0B .uleb128 0xb + 2261 01d0 3B .uleb128 0x3b + 2262 01d1 0B .uleb128 0xb + 2263 01d2 27 .uleb128 0x27 + 2264 01d3 0C .uleb128 0xc + 2265 01d4 11 .uleb128 0x11 + 2266 01d5 01 .uleb128 0x1 + 2267 01d6 12 .uleb128 0x12 + 2268 01d7 01 .uleb128 0x1 + 2269 01d8 40 .uleb128 0x40 + 2270 01d9 06 .uleb128 0x6 + 2271 01da 9742 .uleb128 0x2117 + 2272 01dc 0C .uleb128 0xc + 2273 01dd 01 .uleb128 0x1 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 41 + + + 2274 01de 13 .uleb128 0x13 + 2275 01df 00 .byte 0 + 2276 01e0 00 .byte 0 + 2277 01e1 24 .uleb128 0x24 + 2278 01e2 05 .uleb128 0x5 + 2279 01e3 00 .byte 0 + 2280 01e4 03 .uleb128 0x3 + 2281 01e5 0E .uleb128 0xe + 2282 01e6 3A .uleb128 0x3a + 2283 01e7 0B .uleb128 0xb + 2284 01e8 3B .uleb128 0x3b + 2285 01e9 0B .uleb128 0xb + 2286 01ea 49 .uleb128 0x49 + 2287 01eb 13 .uleb128 0x13 + 2288 01ec 02 .uleb128 0x2 + 2289 01ed 06 .uleb128 0x6 + 2290 01ee 00 .byte 0 + 2291 01ef 00 .byte 0 + 2292 01f0 25 .uleb128 0x25 + 2293 01f1 34 .uleb128 0x34 + 2294 01f2 00 .byte 0 + 2295 01f3 03 .uleb128 0x3 + 2296 01f4 08 .uleb128 0x8 + 2297 01f5 3A .uleb128 0x3a + 2298 01f6 0B .uleb128 0xb + 2299 01f7 3B .uleb128 0x3b + 2300 01f8 0B .uleb128 0xb + 2301 01f9 49 .uleb128 0x49 + 2302 01fa 13 .uleb128 0x13 + 2303 01fb 02 .uleb128 0x2 + 2304 01fc 06 .uleb128 0x6 + 2305 01fd 00 .byte 0 + 2306 01fe 00 .byte 0 + 2307 01ff 26 .uleb128 0x26 + 2308 0200 1D .uleb128 0x1d + 2309 0201 01 .byte 0x1 + 2310 0202 31 .uleb128 0x31 + 2311 0203 13 .uleb128 0x13 + 2312 0204 52 .uleb128 0x52 + 2313 0205 01 .uleb128 0x1 + 2314 0206 55 .uleb128 0x55 + 2315 0207 06 .uleb128 0x6 + 2316 0208 58 .uleb128 0x58 + 2317 0209 0B .uleb128 0xb + 2318 020a 59 .uleb128 0x59 + 2319 020b 0B .uleb128 0xb + 2320 020c 01 .uleb128 0x1 + 2321 020d 13 .uleb128 0x13 + 2322 020e 00 .byte 0 + 2323 020f 00 .byte 0 + 2324 0210 27 .uleb128 0x27 + 2325 0211 0B .uleb128 0xb + 2326 0212 01 .byte 0x1 + 2327 0213 55 .uleb128 0x55 + 2328 0214 06 .uleb128 0x6 + 2329 0215 00 .byte 0 + 2330 0216 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 42 + + + 2331 0217 28 .uleb128 0x28 + 2332 0218 898201 .uleb128 0x4109 + 2333 021b 00 .byte 0 + 2334 021c 11 .uleb128 0x11 + 2335 021d 01 .uleb128 0x1 + 2336 021e 9542 .uleb128 0x2115 + 2337 0220 0C .uleb128 0xc + 2338 0221 31 .uleb128 0x31 + 2339 0222 13 .uleb128 0x13 + 2340 0223 00 .byte 0 + 2341 0224 00 .byte 0 + 2342 0225 29 .uleb128 0x29 + 2343 0226 2E .uleb128 0x2e + 2344 0227 01 .byte 0x1 + 2345 0228 3F .uleb128 0x3f + 2346 0229 0C .uleb128 0xc + 2347 022a 03 .uleb128 0x3 + 2348 022b 0E .uleb128 0xe + 2349 022c 3A .uleb128 0x3a + 2350 022d 0B .uleb128 0xb + 2351 022e 3B .uleb128 0x3b + 2352 022f 0B .uleb128 0xb + 2353 0230 27 .uleb128 0x27 + 2354 0231 0C .uleb128 0xc + 2355 0232 49 .uleb128 0x49 + 2356 0233 13 .uleb128 0x13 + 2357 0234 11 .uleb128 0x11 + 2358 0235 01 .uleb128 0x1 + 2359 0236 12 .uleb128 0x12 + 2360 0237 01 .uleb128 0x1 + 2361 0238 40 .uleb128 0x40 + 2362 0239 06 .uleb128 0x6 + 2363 023a 9742 .uleb128 0x2117 + 2364 023c 0C .uleb128 0xc + 2365 023d 01 .uleb128 0x1 + 2366 023e 13 .uleb128 0x13 + 2367 023f 00 .byte 0 + 2368 0240 00 .byte 0 + 2369 0241 2A .uleb128 0x2a + 2370 0242 0B .uleb128 0xb + 2371 0243 01 .byte 0x1 + 2372 0244 11 .uleb128 0x11 + 2373 0245 01 .uleb128 0x1 + 2374 0246 12 .uleb128 0x12 + 2375 0247 01 .uleb128 0x1 + 2376 0248 01 .uleb128 0x1 + 2377 0249 13 .uleb128 0x13 + 2378 024a 00 .byte 0 + 2379 024b 00 .byte 0 + 2380 024c 2B .uleb128 0x2b + 2381 024d 898201 .uleb128 0x4109 + 2382 0250 01 .byte 0x1 + 2383 0251 11 .uleb128 0x11 + 2384 0252 01 .uleb128 0x1 + 2385 0253 31 .uleb128 0x31 + 2386 0254 13 .uleb128 0x13 + 2387 0255 01 .uleb128 0x1 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 43 + + + 2388 0256 13 .uleb128 0x13 + 2389 0257 00 .byte 0 + 2390 0258 00 .byte 0 + 2391 0259 2C .uleb128 0x2c + 2392 025a 8A8201 .uleb128 0x410a + 2393 025d 00 .byte 0 + 2394 025e 02 .uleb128 0x2 + 2395 025f 0A .uleb128 0xa + 2396 0260 9142 .uleb128 0x2111 + 2397 0262 0A .uleb128 0xa + 2398 0263 00 .byte 0 + 2399 0264 00 .byte 0 + 2400 0265 2D .uleb128 0x2d + 2401 0266 898201 .uleb128 0x4109 + 2402 0269 01 .byte 0x1 + 2403 026a 11 .uleb128 0x11 + 2404 026b 01 .uleb128 0x1 + 2405 026c 31 .uleb128 0x31 + 2406 026d 13 .uleb128 0x13 + 2407 026e 00 .byte 0 + 2408 026f 00 .byte 0 + 2409 0270 2E .uleb128 0x2e + 2410 0271 898201 .uleb128 0x4109 + 2411 0274 00 .byte 0 + 2412 0275 11 .uleb128 0x11 + 2413 0276 01 .uleb128 0x1 + 2414 0277 31 .uleb128 0x31 + 2415 0278 13 .uleb128 0x13 + 2416 0279 00 .byte 0 + 2417 027a 00 .byte 0 + 2418 027b 2F .uleb128 0x2f + 2419 027c 05 .uleb128 0x5 + 2420 027d 00 .byte 0 + 2421 027e 03 .uleb128 0x3 + 2422 027f 08 .uleb128 0x8 + 2423 0280 3A .uleb128 0x3a + 2424 0281 0B .uleb128 0xb + 2425 0282 3B .uleb128 0x3b + 2426 0283 0B .uleb128 0xb + 2427 0284 49 .uleb128 0x49 + 2428 0285 13 .uleb128 0x13 + 2429 0286 02 .uleb128 0x2 + 2430 0287 06 .uleb128 0x6 + 2431 0288 00 .byte 0 + 2432 0289 00 .byte 0 + 2433 028a 30 .uleb128 0x30 + 2434 028b 898201 .uleb128 0x4109 + 2435 028e 01 .byte 0x1 + 2436 028f 11 .uleb128 0x11 + 2437 0290 01 .uleb128 0x1 + 2438 0291 9542 .uleb128 0x2115 + 2439 0293 0C .uleb128 0xc + 2440 0294 31 .uleb128 0x31 + 2441 0295 13 .uleb128 0x13 + 2442 0296 00 .byte 0 + 2443 0297 00 .byte 0 + 2444 0298 31 .uleb128 0x31 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 44 + + + 2445 0299 2E .uleb128 0x2e + 2446 029a 01 .byte 0x1 + 2447 029b 3F .uleb128 0x3f + 2448 029c 0C .uleb128 0xc + 2449 029d 03 .uleb128 0x3 + 2450 029e 0E .uleb128 0xe + 2451 029f 3A .uleb128 0x3a + 2452 02a0 0B .uleb128 0xb + 2453 02a1 3B .uleb128 0x3b + 2454 02a2 05 .uleb128 0x5 + 2455 02a3 27 .uleb128 0x27 + 2456 02a4 0C .uleb128 0xc + 2457 02a5 11 .uleb128 0x11 + 2458 02a6 01 .uleb128 0x1 + 2459 02a7 12 .uleb128 0x12 + 2460 02a8 01 .uleb128 0x1 + 2461 02a9 40 .uleb128 0x40 + 2462 02aa 06 .uleb128 0x6 + 2463 02ab 9742 .uleb128 0x2117 + 2464 02ad 0C .uleb128 0xc + 2465 02ae 01 .uleb128 0x1 + 2466 02af 13 .uleb128 0x13 + 2467 02b0 00 .byte 0 + 2468 02b1 00 .byte 0 + 2469 02b2 32 .uleb128 0x32 + 2470 02b3 34 .uleb128 0x34 + 2471 02b4 00 .byte 0 + 2472 02b5 03 .uleb128 0x3 + 2473 02b6 08 .uleb128 0x8 + 2474 02b7 3A .uleb128 0x3a + 2475 02b8 0B .uleb128 0xb + 2476 02b9 3B .uleb128 0x3b + 2477 02ba 05 .uleb128 0x5 + 2478 02bb 49 .uleb128 0x49 + 2479 02bc 13 .uleb128 0x13 + 2480 02bd 02 .uleb128 0x2 + 2481 02be 06 .uleb128 0x6 + 2482 02bf 00 .byte 0 + 2483 02c0 00 .byte 0 + 2484 02c1 33 .uleb128 0x33 + 2485 02c2 1D .uleb128 0x1d + 2486 02c3 01 .byte 0x1 + 2487 02c4 31 .uleb128 0x31 + 2488 02c5 13 .uleb128 0x13 + 2489 02c6 52 .uleb128 0x52 + 2490 02c7 01 .uleb128 0x1 + 2491 02c8 55 .uleb128 0x55 + 2492 02c9 06 .uleb128 0x6 + 2493 02ca 58 .uleb128 0x58 + 2494 02cb 0B .uleb128 0xb + 2495 02cc 59 .uleb128 0x59 + 2496 02cd 05 .uleb128 0x5 + 2497 02ce 01 .uleb128 0x1 + 2498 02cf 13 .uleb128 0x13 + 2499 02d0 00 .byte 0 + 2500 02d1 00 .byte 0 + 2501 02d2 34 .uleb128 0x34 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 45 + + + 2502 02d3 1D .uleb128 0x1d + 2503 02d4 01 .byte 0x1 + 2504 02d5 31 .uleb128 0x31 + 2505 02d6 13 .uleb128 0x13 + 2506 02d7 11 .uleb128 0x11 + 2507 02d8 01 .uleb128 0x1 + 2508 02d9 12 .uleb128 0x12 + 2509 02da 01 .uleb128 0x1 + 2510 02db 58 .uleb128 0x58 + 2511 02dc 0B .uleb128 0xb + 2512 02dd 59 .uleb128 0x59 + 2513 02de 05 .uleb128 0x5 + 2514 02df 01 .uleb128 0x1 + 2515 02e0 13 .uleb128 0x13 + 2516 02e1 00 .byte 0 + 2517 02e2 00 .byte 0 + 2518 02e3 35 .uleb128 0x35 + 2519 02e4 2E .uleb128 0x2e + 2520 02e5 01 .byte 0x1 + 2521 02e6 3F .uleb128 0x3f + 2522 02e7 0C .uleb128 0xc + 2523 02e8 03 .uleb128 0x3 + 2524 02e9 0E .uleb128 0xe + 2525 02ea 3A .uleb128 0x3a + 2526 02eb 0B .uleb128 0xb + 2527 02ec 3B .uleb128 0x3b + 2528 02ed 0B .uleb128 0xb + 2529 02ee 27 .uleb128 0x27 + 2530 02ef 0C .uleb128 0xc + 2531 02f0 11 .uleb128 0x11 + 2532 02f1 01 .uleb128 0x1 + 2533 02f2 12 .uleb128 0x12 + 2534 02f3 01 .uleb128 0x1 + 2535 02f4 40 .uleb128 0x40 + 2536 02f5 0A .uleb128 0xa + 2537 02f6 9742 .uleb128 0x2117 + 2538 02f8 0C .uleb128 0xc + 2539 02f9 01 .uleb128 0x1 + 2540 02fa 13 .uleb128 0x13 + 2541 02fb 00 .byte 0 + 2542 02fc 00 .byte 0 + 2543 02fd 36 .uleb128 0x36 + 2544 02fe 34 .uleb128 0x34 + 2545 02ff 00 .byte 0 + 2546 0300 03 .uleb128 0x3 + 2547 0301 0E .uleb128 0xe + 2548 0302 3A .uleb128 0x3a + 2549 0303 0B .uleb128 0xb + 2550 0304 3B .uleb128 0x3b + 2551 0305 0B .uleb128 0xb + 2552 0306 49 .uleb128 0x49 + 2553 0307 13 .uleb128 0x13 + 2554 0308 3F .uleb128 0x3f + 2555 0309 0C .uleb128 0xc + 2556 030a 02 .uleb128 0x2 + 2557 030b 0A .uleb128 0xa + 2558 030c 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 46 + + + 2559 030d 00 .byte 0 + 2560 030e 37 .uleb128 0x37 + 2561 030f 2E .uleb128 0x2e + 2562 0310 01 .byte 0x1 + 2563 0311 3F .uleb128 0x3f + 2564 0312 0C .uleb128 0xc + 2565 0313 03 .uleb128 0x3 + 2566 0314 0E .uleb128 0xe + 2567 0315 3A .uleb128 0x3a + 2568 0316 0B .uleb128 0xb + 2569 0317 3B .uleb128 0x3b + 2570 0318 05 .uleb128 0x5 + 2571 0319 27 .uleb128 0x27 + 2572 031a 0C .uleb128 0xc + 2573 031b 3C .uleb128 0x3c + 2574 031c 0C .uleb128 0xc + 2575 031d 01 .uleb128 0x1 + 2576 031e 13 .uleb128 0x13 + 2577 031f 00 .byte 0 + 2578 0320 00 .byte 0 + 2579 0321 38 .uleb128 0x38 + 2580 0322 2E .uleb128 0x2e + 2581 0323 01 .byte 0x1 + 2582 0324 3F .uleb128 0x3f + 2583 0325 0C .uleb128 0xc + 2584 0326 03 .uleb128 0x3 + 2585 0327 0E .uleb128 0xe + 2586 0328 3A .uleb128 0x3a + 2587 0329 0B .uleb128 0xb + 2588 032a 3B .uleb128 0x3b + 2589 032b 0B .uleb128 0xb + 2590 032c 27 .uleb128 0x27 + 2591 032d 0C .uleb128 0xc + 2592 032e 3C .uleb128 0x3c + 2593 032f 0C .uleb128 0xc + 2594 0330 01 .uleb128 0x1 + 2595 0331 13 .uleb128 0x13 + 2596 0332 00 .byte 0 + 2597 0333 00 .byte 0 + 2598 0334 39 .uleb128 0x39 + 2599 0335 2E .uleb128 0x2e + 2600 0336 01 .byte 0x1 + 2601 0337 3F .uleb128 0x3f + 2602 0338 0C .uleb128 0xc + 2603 0339 03 .uleb128 0x3 + 2604 033a 0E .uleb128 0xe + 2605 033b 3A .uleb128 0x3a + 2606 033c 0B .uleb128 0xb + 2607 033d 3B .uleb128 0x3b + 2608 033e 0B .uleb128 0xb + 2609 033f 27 .uleb128 0x27 + 2610 0340 0C .uleb128 0xc + 2611 0341 3C .uleb128 0x3c + 2612 0342 0C .uleb128 0xc + 2613 0343 00 .byte 0 + 2614 0344 00 .byte 0 + 2615 0345 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 47 + + + 2616 .section .debug_loc,"",%progbits + 2617 .Ldebug_loc0: + 2618 .LLST0: + 2619 0000 20000000 .4byte .LVL1 + 2620 0004 2A000000 .4byte .LVL2 + 2621 0008 0100 .2byte 0x1 + 2622 000a 50 .byte 0x50 + 2623 000b 00000000 .4byte 0 + 2624 000f 00000000 .4byte 0 + 2625 .LLST1: + 2626 0013 30000000 .4byte .LVL3 + 2627 0017 4A000000 .4byte .LVL6 + 2628 001b 0100 .2byte 0x1 + 2629 001d 50 .byte 0x50 + 2630 001e 00000000 .4byte 0 + 2631 0022 00000000 .4byte 0 + 2632 .LLST2: + 2633 0026 38000000 .4byte .LVL4 + 2634 002a 4A000000 .4byte .LVL6 + 2635 002e 0100 .2byte 0x1 + 2636 0030 53 .byte 0x53 + 2637 0031 00000000 .4byte 0 + 2638 0035 00000000 .4byte 0 + 2639 .LLST3: + 2640 0039 00000000 .4byte .LFB9 + 2641 003d 06000000 .4byte .LCFI0 + 2642 0041 0200 .2byte 0x2 + 2643 0043 7D .byte 0x7d + 2644 0044 00 .sleb128 0 + 2645 0045 06000000 .4byte .LCFI0 + 2646 0049 28000000 .4byte .LFE9 + 2647 004d 0200 .2byte 0x2 + 2648 004f 7D .byte 0x7d + 2649 0050 08 .sleb128 8 + 2650 0051 00000000 .4byte 0 + 2651 0055 00000000 .4byte 0 + 2652 .LLST4: + 2653 0059 00000000 .4byte .LVL10 + 2654 005d 14000000 .4byte .LVL12 + 2655 0061 0100 .2byte 0x1 + 2656 0063 50 .byte 0x50 + 2657 0064 14000000 .4byte .LVL12 + 2658 0068 27000000 .4byte .LVL14-1 + 2659 006c 0200 .2byte 0x2 + 2660 006e 71 .byte 0x71 + 2661 006f 1C .sleb128 28 + 2662 0070 27000000 .4byte .LVL14-1 + 2663 0074 28000000 .4byte .LFE9 + 2664 0078 0400 .2byte 0x4 + 2665 007a F3 .byte 0xf3 + 2666 007b 01 .uleb128 0x1 + 2667 007c 50 .byte 0x50 + 2668 007d 9F .byte 0x9f + 2669 007e 00000000 .4byte 0 + 2670 0082 00000000 .4byte 0 + 2671 .LLST5: + 2672 0086 0E000000 .4byte .LVL11 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 48 + + + 2673 008a 27000000 .4byte .LVL14-1 + 2674 008e 0100 .2byte 0x1 + 2675 0090 51 .byte 0x51 + 2676 0091 00000000 .4byte 0 + 2677 0095 00000000 .4byte 0 + 2678 .LLST6: + 2679 0099 16000000 .4byte .LVL13 + 2680 009d 27000000 .4byte .LVL14-1 + 2681 00a1 0100 .2byte 0x1 + 2682 00a3 52 .byte 0x52 + 2683 00a4 00000000 .4byte 0 + 2684 00a8 00000000 .4byte 0 + 2685 .LLST7: + 2686 00ac 00000000 .4byte .LFB11 + 2687 00b0 02000000 .4byte .LCFI1 + 2688 00b4 0200 .2byte 0x2 + 2689 00b6 7D .byte 0x7d + 2690 00b7 00 .sleb128 0 + 2691 00b8 02000000 .4byte .LCFI1 + 2692 00bc 06000000 .4byte .LCFI2 + 2693 00c0 0200 .2byte 0x2 + 2694 00c2 7D .byte 0x7d + 2695 00c3 0C .sleb128 12 + 2696 00c4 06000000 .4byte .LCFI2 + 2697 00c8 40000000 .4byte .LFE11 + 2698 00cc 0200 .2byte 0x2 + 2699 00ce 7D .byte 0x7d + 2700 00cf 28 .sleb128 40 + 2701 00d0 00000000 .4byte 0 + 2702 00d4 00000000 .4byte 0 + 2703 .LLST8: + 2704 00d8 00000000 .4byte .LVL15 + 2705 00dc 12000000 .4byte .LVL16 + 2706 00e0 0100 .2byte 0x1 + 2707 00e2 50 .byte 0x50 + 2708 00e3 12000000 .4byte .LVL16 + 2709 00e7 2E000000 .4byte .LVL20 + 2710 00eb 0400 .2byte 0x4 + 2711 00ed F3 .byte 0xf3 + 2712 00ee 01 .uleb128 0x1 + 2713 00ef 50 .byte 0x50 + 2714 00f0 9F .byte 0x9f + 2715 00f1 2E000000 .4byte .LVL20 + 2716 00f5 31000000 .4byte .LVL21-1 + 2717 00f9 0100 .2byte 0x1 + 2718 00fb 50 .byte 0x50 + 2719 00fc 31000000 .4byte .LVL21-1 + 2720 0100 40000000 .4byte .LFE11 + 2721 0104 0400 .2byte 0x4 + 2722 0106 F3 .byte 0xf3 + 2723 0107 01 .uleb128 0x1 + 2724 0108 50 .byte 0x50 + 2725 0109 9F .byte 0x9f + 2726 010a 00000000 .4byte 0 + 2727 010e 00000000 .4byte 0 + 2728 .LLST9: + 2729 0112 00000000 .4byte .LVL15 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 49 + + + 2730 0116 15000000 .4byte .LVL17-1 + 2731 011a 0100 .2byte 0x1 + 2732 011c 51 .byte 0x51 + 2733 011d 15000000 .4byte .LVL17-1 + 2734 0121 2E000000 .4byte .LVL20 + 2735 0125 0400 .2byte 0x4 + 2736 0127 F3 .byte 0xf3 + 2737 0128 01 .uleb128 0x1 + 2738 0129 51 .byte 0x51 + 2739 012a 9F .byte 0x9f + 2740 012b 2E000000 .4byte .LVL20 + 2741 012f 31000000 .4byte .LVL21-1 + 2742 0133 0100 .2byte 0x1 + 2743 0135 51 .byte 0x51 + 2744 0136 31000000 .4byte .LVL21-1 + 2745 013a 40000000 .4byte .LFE11 + 2746 013e 0400 .2byte 0x4 + 2747 0140 F3 .byte 0xf3 + 2748 0141 01 .uleb128 0x1 + 2749 0142 51 .byte 0x51 + 2750 0143 9F .byte 0x9f + 2751 0144 00000000 .4byte 0 + 2752 0148 00000000 .4byte 0 + 2753 .LLST10: + 2754 014c 00000000 .4byte .LFB12 + 2755 0150 02000000 .4byte .LCFI3 + 2756 0154 0200 .2byte 0x2 + 2757 0156 7D .byte 0x7d + 2758 0157 00 .sleb128 0 + 2759 0158 02000000 .4byte .LCFI3 + 2760 015c 5C000000 .4byte .LFE12 + 2761 0160 0200 .2byte 0x2 + 2762 0162 7D .byte 0x7d + 2763 0163 10 .sleb128 16 + 2764 0164 00000000 .4byte 0 + 2765 0168 00000000 .4byte 0 + 2766 .LLST11: + 2767 016c 00000000 .4byte .LVL22 + 2768 0170 0C000000 .4byte .LVL23 + 2769 0174 0100 .2byte 0x1 + 2770 0176 50 .byte 0x50 + 2771 0177 0C000000 .4byte .LVL23 + 2772 017b 5C000000 .4byte .LFE12 + 2773 017f 0100 .2byte 0x1 + 2774 0181 54 .byte 0x54 + 2775 0182 00000000 .4byte 0 + 2776 0186 00000000 .4byte 0 + 2777 .LLST12: + 2778 018a 00000000 .4byte .LVL22 + 2779 018e 4C000000 .4byte .LVL33 + 2780 0192 0100 .2byte 0x1 + 2781 0194 51 .byte 0x51 + 2782 0195 4C000000 .4byte .LVL33 + 2783 0199 57000000 .4byte .LVL34-1 + 2784 019d 0200 .2byte 0x2 + 2785 019f 74 .byte 0x74 + 2786 01a0 24 .sleb128 36 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 50 + + + 2787 01a1 57000000 .4byte .LVL34-1 + 2788 01a5 5C000000 .4byte .LFE12 + 2789 01a9 0400 .2byte 0x4 + 2790 01ab F3 .byte 0xf3 + 2791 01ac 01 .uleb128 0x1 + 2792 01ad 51 .byte 0x51 + 2793 01ae 9F .byte 0x9f + 2794 01af 00000000 .4byte 0 + 2795 01b3 00000000 .4byte 0 + 2796 .LLST13: + 2797 01b7 14000000 .4byte .LVL24 + 2798 01bb 2E000000 .4byte .LVL28 + 2799 01bf 0100 .2byte 0x1 + 2800 01c1 54 .byte 0x54 + 2801 01c2 00000000 .4byte 0 + 2802 01c6 00000000 .4byte 0 + 2803 .LLST14: + 2804 01ca 16000000 .4byte .LVL25 + 2805 01ce 18000000 .4byte .LVL26 + 2806 01d2 0600 .2byte 0x6 + 2807 01d4 03 .byte 0x3 + 2808 01d5 00000000 .4byte rlist + 2809 01d9 9F .byte 0x9f + 2810 01da 18000000 .4byte .LVL26 + 2811 01de 2E000000 .4byte .LVL28 + 2812 01e2 0100 .2byte 0x1 + 2813 01e4 53 .byte 0x53 + 2814 01e5 00000000 .4byte 0 + 2815 01e9 00000000 .4byte 0 + 2816 .LLST15: + 2817 01ed 30000000 .4byte .LVL29 + 2818 01f1 32000000 .4byte .LVL30 + 2819 01f5 0600 .2byte 0x6 + 2820 01f7 03 .byte 0x3 + 2821 01f8 00000000 .4byte rlist + 2822 01fc 9F .byte 0x9f + 2823 01fd 32000000 .4byte .LVL30 + 2824 0201 44000000 .4byte .LVL32 + 2825 0205 0100 .2byte 0x1 + 2826 0207 53 .byte 0x53 + 2827 0208 44000000 .4byte .LVL32 + 2828 020c 57000000 .4byte .LVL34-1 + 2829 0210 0200 .2byte 0x2 + 2830 0212 76 .byte 0x76 + 2831 0213 00 .sleb128 0 + 2832 0214 00000000 .4byte 0 + 2833 0218 00000000 .4byte 0 + 2834 .LLST16: + 2835 021c 00000000 .4byte .LFB14 + 2836 0220 04000000 .4byte .LCFI4 + 2837 0224 0200 .2byte 0x2 + 2838 0226 7D .byte 0x7d + 2839 0227 00 .sleb128 0 + 2840 0228 04000000 .4byte .LCFI4 + 2841 022c 40000000 .4byte .LFE14 + 2842 0230 0200 .2byte 0x2 + 2843 0232 7D .byte 0x7d + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 51 + + + 2844 0233 08 .sleb128 8 + 2845 0234 00000000 .4byte 0 + 2846 0238 00000000 .4byte 0 + 2847 .LLST17: + 2848 023c 08000000 .4byte .LVL35 + 2849 0240 39000000 .4byte .LVL40-1 + 2850 0244 0100 .2byte 0x1 + 2851 0246 51 .byte 0x51 + 2852 0247 00000000 .4byte 0 + 2853 024b 00000000 .4byte 0 + 2854 .LLST18: + 2855 024f 08000000 .4byte .LVL35 + 2856 0253 39000000 .4byte .LVL40-1 + 2857 0257 0100 .2byte 0x1 + 2858 0259 50 .byte 0x50 + 2859 025a 00000000 .4byte 0 + 2860 025e 00000000 .4byte 0 + 2861 .LLST19: + 2862 0262 1A000000 .4byte .LVL36 + 2863 0266 39000000 .4byte .LVL40-1 + 2864 026a 0100 .2byte 0x1 + 2865 026c 51 .byte 0x51 + 2866 026d 00000000 .4byte 0 + 2867 0271 00000000 .4byte 0 + 2868 .LLST20: + 2869 0275 20000000 .4byte .LVL37 + 2870 0279 22000000 .4byte .LVL38 + 2871 027d 0600 .2byte 0x6 + 2872 027f 03 .byte 0x3 + 2873 0280 00000000 .4byte rlist + 2874 0284 9F .byte 0x9f + 2875 0285 22000000 .4byte .LVL38 + 2876 0289 39000000 .4byte .LVL40-1 + 2877 028d 0100 .2byte 0x1 + 2878 028f 53 .byte 0x53 + 2879 0290 00000000 .4byte 0 + 2880 0294 00000000 .4byte 0 + 2881 .section .debug_aranges,"",%progbits + 2882 0000 54000000 .4byte 0x54 + 2883 0004 0200 .2byte 0x2 + 2884 0006 00000000 .4byte .Ldebug_info0 + 2885 000a 04 .byte 0x4 + 2886 000b 00 .byte 0 + 2887 000c 0000 .2byte 0 + 2888 000e 0000 .2byte 0 + 2889 0010 00000000 .4byte .LFB10 + 2890 0014 50000000 .4byte .LFE10-.LFB10 + 2891 0018 00000000 .4byte .LFB7 + 2892 001c 1A000000 .4byte .LFE7-.LFB7 + 2893 0020 00000000 .4byte .LFB8 + 2894 0024 20000000 .4byte .LFE8-.LFB8 + 2895 0028 00000000 .4byte .LFB9 + 2896 002c 28000000 .4byte .LFE9-.LFB9 + 2897 0030 00000000 .4byte .LFB11 + 2898 0034 40000000 .4byte .LFE11-.LFB11 + 2899 0038 00000000 .4byte .LFB12 + 2900 003c 5C000000 .4byte .LFE12-.LFB12 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 52 + + + 2901 0040 00000000 .4byte .LFB14 + 2902 0044 40000000 .4byte .LFE14-.LFB14 + 2903 0048 00000000 .4byte .LFB13 + 2904 004c 18000000 .4byte .LFE13-.LFB13 + 2905 0050 00000000 .4byte 0 + 2906 0054 00000000 .4byte 0 + 2907 .section .debug_ranges,"",%progbits + 2908 .Ldebug_ranges0: + 2909 0000 0A000000 .4byte .LBB21 + 2910 0004 0C000000 .4byte .LBE21 + 2911 0008 0E000000 .4byte .LBB25 + 2912 000c 10000000 .4byte .LBE25 + 2913 0010 1A000000 .4byte .LBB26 + 2914 0014 1E000000 .4byte .LBE26 + 2915 0018 00000000 .4byte 0 + 2916 001c 00000000 .4byte 0 + 2917 0020 0A000000 .4byte .LBB22 + 2918 0024 0C000000 .4byte .LBE22 + 2919 0028 0E000000 .4byte .LBB23 + 2920 002c 10000000 .4byte .LBE23 + 2921 0030 1A000000 .4byte .LBB24 + 2922 0034 1E000000 .4byte .LBE24 + 2923 0038 00000000 .4byte 0 + 2924 003c 00000000 .4byte 0 + 2925 0040 0C000000 .4byte .LBB28 + 2926 0044 0E000000 .4byte .LBE28 + 2927 0048 14000000 .4byte .LBB31 + 2928 004c 2A000000 .4byte .LBE31 + 2929 0050 00000000 .4byte 0 + 2930 0054 00000000 .4byte 0 + 2931 0058 0C000000 .4byte .LBB29 + 2932 005c 0E000000 .4byte .LBE29 + 2933 0060 14000000 .4byte .LBB30 + 2934 0064 2A000000 .4byte .LBE30 + 2935 0068 00000000 .4byte 0 + 2936 006c 00000000 .4byte 0 + 2937 0070 2E000000 .4byte .LBB32 + 2938 0074 52000000 .4byte .LBE32 + 2939 0078 54000000 .4byte .LBB37 + 2940 007c 5C000000 .4byte .LBE37 + 2941 0080 00000000 .4byte 0 + 2942 0084 00000000 .4byte 0 + 2943 0088 2E000000 .4byte .LBB33 + 2944 008c 42000000 .4byte .LBE33 + 2945 0090 44000000 .4byte .LBB36 + 2946 0094 46000000 .4byte .LBE36 + 2947 0098 00000000 .4byte 0 + 2948 009c 00000000 .4byte 0 + 2949 00a0 2E000000 .4byte .LBB34 + 2950 00a4 42000000 .4byte .LBE34 + 2951 00a8 44000000 .4byte .LBB35 + 2952 00ac 46000000 .4byte .LBE35 + 2953 00b0 00000000 .4byte 0 + 2954 00b4 00000000 .4byte 0 + 2955 00b8 04000000 .4byte .LBB38 + 2956 00bc 06000000 .4byte .LBE38 + 2957 00c0 08000000 .4byte .LBB43 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 53 + + + 2958 00c4 0A000000 .4byte .LBE43 + 2959 00c8 0E000000 .4byte .LBB44 + 2960 00cc 10000000 .4byte .LBE44 + 2961 00d0 12000000 .4byte .LBB45 + 2962 00d4 14000000 .4byte .LBE45 + 2963 00d8 00000000 .4byte 0 + 2964 00dc 00000000 .4byte 0 + 2965 00e0 04000000 .4byte .LBB39 + 2966 00e4 06000000 .4byte .LBE39 + 2967 00e8 08000000 .4byte .LBB40 + 2968 00ec 0A000000 .4byte .LBE40 + 2969 00f0 0E000000 .4byte .LBB41 + 2970 00f4 10000000 .4byte .LBE41 + 2971 00f8 12000000 .4byte .LBB42 + 2972 00fc 14000000 .4byte .LBE42 + 2973 0100 00000000 .4byte 0 + 2974 0104 00000000 .4byte 0 + 2975 0108 00000000 .4byte .LFB10 + 2976 010c 50000000 .4byte .LFE10 + 2977 0110 00000000 .4byte .LFB7 + 2978 0114 1A000000 .4byte .LFE7 + 2979 0118 00000000 .4byte .LFB8 + 2980 011c 20000000 .4byte .LFE8 + 2981 0120 00000000 .4byte .LFB9 + 2982 0124 28000000 .4byte .LFE9 + 2983 0128 00000000 .4byte .LFB11 + 2984 012c 40000000 .4byte .LFE11 + 2985 0130 00000000 .4byte .LFB12 + 2986 0134 5C000000 .4byte .LFE12 + 2987 0138 00000000 .4byte .LFB14 + 2988 013c 40000000 .4byte .LFE14 + 2989 0140 00000000 .4byte .LFB13 + 2990 0144 18000000 .4byte .LFE13 + 2991 0148 00000000 .4byte 0 + 2992 014c 00000000 .4byte 0 + 2993 .section .debug_line,"",%progbits + 2994 .Ldebug_line0: + 2995 0000 8B020000 .section .debug_str,"MS",%progbits,1 + 2995 02001A01 + 2995 00000201 + 2995 FB0E0D00 + 2995 01010101 + 2996 .LASF34: + 2997 0000 705F6D73 .ascii "p_msg\000" + 2997 6700 + 2998 .LASF67: + 2999 0006 7264796D .ascii "rdymsg\000" + 2999 736700 + 3000 .LASF11: + 3001 000d 6C6F6E67 .ascii "long long unsigned int\000" + 3001 206C6F6E + 3001 6720756E + 3001 7369676E + 3001 65642069 + 3002 .LASF68: + 3003 0024 65786974 .ascii "exitcode\000" + 3003 636F6465 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 54 + + + 3003 00 + 3004 .LASF23: + 3005 002d 705F7072 .ascii "p_prio\000" + 3005 696F00 + 3006 .LASF87: + 3007 0034 5F736368 .ascii "_scheduler_init\000" + 3007 6564756C + 3007 65725F69 + 3007 6E697400 + 3008 .LASF10: + 3009 0044 6C6F6E67 .ascii "long long int\000" + 3009 206C6F6E + 3009 6720696E + 3009 7400 + 3010 .LASF1: + 3011 0052 7369676E .ascii "signed char\000" + 3011 65642063 + 3011 68617200 + 3012 .LASF38: + 3013 005e 705F6D70 .ascii "p_mpool\000" + 3013 6F6F6C00 + 3014 .LASF64: + 3015 0066 6D5F7175 .ascii "m_queue\000" + 3015 65756500 + 3016 .LASF7: + 3017 006e 6C6F6E67 .ascii "long int\000" + 3017 20696E74 + 3017 00 + 3018 .LASF13: + 3019 0077 74737461 .ascii "tstate_t\000" + 3019 74655F74 + 3019 00 + 3020 .LASF25: + 3021 0080 705F6E65 .ascii "p_newer\000" + 3021 77657200 + 3022 .LASF61: + 3023 0088 735F7175 .ascii "s_queue\000" + 3023 65756500 + 3024 .LASF79: + 3025 0090 63685363 .ascii "chSchRescheduleS\000" + 3025 68526573 + 3025 63686564 + 3025 756C6553 + 3025 00 + 3026 .LASF55: + 3027 00a1 725F6E65 .ascii "r_newer\000" + 3027 77657200 + 3028 .LASF41: + 3029 00a9 72656761 .ascii "regarm_t\000" + 3029 726D5F74 + 3029 00 + 3030 .LASF48: + 3031 00b2 76745F70 .ascii "vt_prev\000" + 3031 72657600 + 3032 .LASF78: + 3033 00ba 63685363 .ascii "chSchDoReschedule\000" + 3033 68446F52 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 55 + + + 3033 65736368 + 3033 6564756C + 3033 6500 + 3034 .LASF19: + 3035 00cc 636E745F .ascii "cnt_t\000" + 3035 7400 + 3036 .LASF0: + 3037 00d2 756E7369 .ascii "unsigned int\000" + 3037 676E6564 + 3037 20696E74 + 3037 00 + 3038 .LASF86: + 3039 00df 77616B65 .ascii "wakeup\000" + 3039 757000 + 3040 .LASF47: + 3041 00e6 76745F6E .ascii "vt_next\000" + 3041 65787400 + 3042 .LASF80: + 3043 00ee 5F706F72 .ascii "_port_switch\000" + 3043 745F7377 + 3043 69746368 + 3043 00 + 3044 .LASF9: + 3045 00fb 6C6F6E67 .ascii "long unsigned int\000" + 3045 20756E73 + 3045 69676E65 + 3045 6420696E + 3045 7400 + 3046 .LASF62: + 3047 010d 735F636E .ascii "s_cnt\000" + 3047 7400 + 3048 .LASF43: + 3049 0113 636F6E74 .ascii "context\000" + 3049 65787400 + 3050 .LASF4: + 3051 011b 73686F72 .ascii "short unsigned int\000" + 3051 7420756E + 3051 7369676E + 3051 65642069 + 3051 6E7400 + 3052 .LASF77: + 3053 012e 63685363 .ascii "chSchWakeupS\000" + 3053 6857616B + 3053 65757053 + 3053 00 + 3054 .LASF16: + 3055 013b 6D73675F .ascii "msg_t\000" + 3055 7400 + 3056 .LASF12: + 3057 0141 746D6F64 .ascii "tmode_t\000" + 3057 655F7400 + 3058 .LASF40: + 3059 0149 54687265 .ascii "ThreadsList\000" + 3059 6164734C + 3059 69737400 + 3060 .LASF17: + 3061 0155 6576656E .ascii "eventmask_t\000" + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 56 + + + 3061 746D6173 + 3061 6B5F7400 + 3062 .LASF63: + 3063 0161 4D757465 .ascii "Mutex\000" + 3063 7800 + 3064 .LASF83: + 3065 0167 2E2E2F2E .ascii "../..//os/kernel/src/chschd.c\000" + 3065 2E2F2F6F + 3065 732F6B65 + 3065 726E656C + 3065 2F737263 + 3066 .LASF49: + 3067 0185 76745F74 .ascii "vt_time\000" + 3067 696D6500 + 3068 .LASF44: + 3069 018d 73697A65 .ascii "sizetype\000" + 3069 74797065 + 3069 00 + 3070 .LASF50: + 3071 0196 76745F66 .ascii "vt_func\000" + 3071 756E6300 + 3072 .LASF81: + 3073 019e 63685654 .ascii "chVTSetI\000" + 3073 53657449 + 3073 00 + 3074 .LASF26: + 3075 01a7 705F6F6C .ascii "p_older\000" + 3075 64657200 + 3076 .LASF84: + 3077 01af 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 3077 73657273 + 3077 5C496D61 + 3077 6E6F6C5C + 3077 64657665 + 3078 01dc 6C696361 .ascii "lications\\smartcities\000" + 3078 74696F6E + 3078 735C736D + 3078 61727463 + 3078 69746965 + 3079 .LASF39: + 3080 01f2 54687265 .ascii "ThreadsQueue\000" + 3080 61647351 + 3080 75657565 + 3080 00 + 3081 .LASF72: + 3082 01ff 64657175 .ascii "dequeue\000" + 3082 65756500 + 3083 .LASF82: + 3084 0207 474E5520 .ascii "GNU C 4.7.2\000" + 3084 4320342E + 3084 372E3200 + 3085 .LASF58: + 3086 0213 725F6375 .ascii "r_current\000" + 3086 7272656E + 3086 7400 + 3087 .LASF56: + 3088 021d 725F6F6C .ascii "r_older\000" + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 57 + + + 3088 64657200 + 3089 .LASF14: + 3090 0225 74726566 .ascii "trefs_t\000" + 3090 735F7400 + 3091 .LASF22: + 3092 022d 705F7072 .ascii "p_prev\000" + 3092 657600 + 3093 .LASF15: + 3094 0234 74707269 .ascii "tprio_t\000" + 3094 6F5F7400 + 3095 .LASF6: + 3096 023c 696E7433 .ascii "int32_t\000" + 3096 325F7400 + 3097 .LASF2: + 3098 0244 756E7369 .ascii "unsigned char\000" + 3098 676E6564 + 3098 20636861 + 3098 7200 + 3099 .LASF74: + 3100 0252 6E657773 .ascii "newstate\000" + 3100 74617465 + 3100 00 + 3101 .LASF36: + 3102 025b 705F6D74 .ascii "p_mtxlist\000" + 3102 786C6973 + 3102 7400 + 3103 .LASF3: + 3104 0265 73686F72 .ascii "short int\000" + 3104 7420696E + 3104 7400 + 3105 .LASF28: + 3106 026f 705F7374 .ascii "p_state\000" + 3106 61746500 + 3107 .LASF53: + 3108 0277 725F7072 .ascii "r_prio\000" + 3108 696F00 + 3109 .LASF70: + 3110 027e 65776D61 .ascii "ewmask\000" + 3110 736B00 + 3111 .LASF21: + 3112 0285 705F6E65 .ascii "p_next\000" + 3112 787400 + 3113 .LASF29: + 3114 028c 705F666C .ascii "p_flags\000" + 3114 61677300 + 3115 .LASF20: + 3116 0294 54687265 .ascii "Thread\000" + 3116 616400 + 3117 .LASF90: + 3118 029b 63685654 .ascii "chVTResetI\000" + 3118 52657365 + 3118 744900 + 3119 .LASF76: + 3120 02a6 63685363 .ascii "chSchGoSleepS\000" + 3120 68476F53 + 3120 6C656570 + 3120 5300 + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 58 + + + 3121 .LASF35: + 3122 02b4 705F6570 .ascii "p_epending\000" + 3122 656E6469 + 3122 6E6700 + 3123 .LASF8: + 3124 02bf 75696E74 .ascii "uint32_t\000" + 3124 33325F74 + 3124 00 + 3125 .LASF52: + 3126 02c8 725F7175 .ascii "r_queue\000" + 3126 65756500 + 3127 .LASF46: + 3128 02d0 56697274 .ascii "VirtualTimer\000" + 3128 75616C54 + 3128 696D6572 + 3128 00 + 3129 .LASF71: + 3130 02dd 63686172 .ascii "char\000" + 3130 00 + 3131 .LASF73: + 3132 02e2 6669666F .ascii "fifo_remove\000" + 3132 5F72656D + 3132 6F766500 + 3133 .LASF85: + 3134 02ee 63685363 .ascii "chSchReadyI\000" + 3134 68526561 + 3134 64794900 + 3135 .LASF66: + 3136 02fa 6D5F6E65 .ascii "m_next\000" + 3136 787400 + 3137 .LASF18: + 3138 0301 73797374 .ascii "systime_t\000" + 3138 696D655F + 3138 7400 + 3139 .LASF37: + 3140 030b 705F7265 .ascii "p_realprio\000" + 3140 616C7072 + 3140 696F00 + 3141 .LASF45: + 3142 0316 76746675 .ascii "vtfunc_t\000" + 3142 6E635F74 + 3142 00 + 3143 .LASF31: + 3144 031f 705F7469 .ascii "p_time\000" + 3144 6D6500 + 3145 .LASF54: + 3146 0326 725F6374 .ascii "r_ctx\000" + 3146 7800 + 3147 .LASF42: + 3148 032c 696E7463 .ascii "intctx\000" + 3148 747800 + 3149 .LASF33: + 3150 0333 705F6D73 .ascii "p_msgqueue\000" + 3150 67717565 + 3150 756500 + 3151 .LASF75: + 3152 033e 74696D65 .ascii "time\000" + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 59 + + + 3152 00 + 3153 .LASF51: + 3154 0343 76745F70 .ascii "vt_par\000" + 3154 617200 + 3155 .LASF60: + 3156 034a 53656D61 .ascii "Semaphore\000" + 3156 70686F72 + 3156 6500 + 3157 .LASF30: + 3158 0354 705F7265 .ascii "p_refs\000" + 3158 667300 + 3159 .LASF59: + 3160 035b 52656164 .ascii "ReadyList\000" + 3160 794C6973 + 3160 7400 + 3161 .LASF89: + 3162 0365 726C6973 .ascii "rlist\000" + 3162 7400 + 3163 .LASF5: + 3164 036b 75696E74 .ascii "uint8_t\000" + 3164 385F7400 + 3165 .LASF69: + 3166 0373 77746F62 .ascii "wtobjp\000" + 3166 6A7000 + 3167 .LASF27: + 3168 037a 705F6E61 .ascii "p_name\000" + 3168 6D6500 + 3169 .LASF88: + 3170 0381 63685363 .ascii "chSchGoSleepTimeoutS\000" + 3170 68476F53 + 3170 6C656570 + 3170 54696D65 + 3170 6F757453 + 3171 .LASF57: + 3172 0396 725F7072 .ascii "r_preempt\000" + 3172 65656D70 + 3172 7400 + 3173 .LASF65: + 3174 03a0 6D5F6F77 .ascii "m_owner\000" + 3174 6E657200 + 3175 .LASF24: + 3176 03a8 705F6374 .ascii "p_ctx\000" + 3176 7800 + 3177 .LASF32: + 3178 03ae 705F7761 .ascii "p_waiting\000" + 3178 6974696E + 3178 6700 + 3179 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\ccNqiZol.s page 60 + + +DEFINED SYMBOLS + *ABS*:00000000 chschd.c +C:\cygwin\tmp\ccNqiZol.s:19 .text.wakeup:00000000 $t +C:\cygwin\tmp\ccNqiZol.s:24 .text.wakeup:00000000 wakeup +C:\cygwin\tmp\ccNqiZol.s:39 .text.wakeup:0000000a $d +C:\cygwin\tmp\ccNqiZol.s:53 .text.wakeup:00000018 $t +C:\cygwin\tmp\ccNqiZol.s:112 .text.wakeup:0000004c $d +C:\cygwin\tmp\ccNqiZol.s:119 .text._scheduler_init:00000000 $t +C:\cygwin\tmp\ccNqiZol.s:125 .text._scheduler_init:00000000 _scheduler_init +C:\cygwin\tmp\ccNqiZol.s:621 .bss.rlist:00000000 .LANCHOR0 +C:\cygwin\tmp\ccNqiZol.s:153 .text.chSchReadyI:00000000 $t +C:\cygwin\tmp\ccNqiZol.s:159 .text.chSchReadyI:00000000 chSchReadyI +C:\cygwin\tmp\ccNqiZol.s:197 .text.chSchReadyI:0000001c $d +C:\cygwin\tmp\ccNqiZol.s:202 .text.chSchGoSleepS:00000000 $t +C:\cygwin\tmp\ccNqiZol.s:208 .text.chSchGoSleepS:00000000 chSchGoSleepS +C:\cygwin\tmp\ccNqiZol.s:272 .text.chSchGoSleepTimeoutS:00000000 $t +C:\cygwin\tmp\ccNqiZol.s:278 .text.chSchGoSleepTimeoutS:00000000 chSchGoSleepTimeoutS +C:\cygwin\tmp\ccNqiZol.s:339 .text.chSchGoSleepTimeoutS:00000038 $d +C:\cygwin\tmp\ccNqiZol.s:345 .text.chSchWakeupS:00000000 $t +C:\cygwin\tmp\ccNqiZol.s:351 .text.chSchWakeupS:00000000 chSchWakeupS +C:\cygwin\tmp\ccNqiZol.s:478 .text.chSchWakeupS:00000058 $d +C:\cygwin\tmp\ccNqiZol.s:484 .text.chSchDoReschedule:00000000 $t +C:\cygwin\tmp\ccNqiZol.s:490 .text.chSchDoReschedule:00000000 chSchDoReschedule +C:\cygwin\tmp\ccNqiZol.s:579 .text.chSchDoReschedule:0000003c $d +C:\cygwin\tmp\ccNqiZol.s:584 .text.chSchRescheduleS:00000000 $t +C:\cygwin\tmp\ccNqiZol.s:590 .text.chSchRescheduleS:00000000 chSchRescheduleS +C:\cygwin\tmp\ccNqiZol.s:614 .text.chSchRescheduleS:00000014 $d +C:\cygwin\tmp\ccNqiZol.s:624 .bss.rlist:00000000 rlist +C:\cygwin\tmp\ccNqiZol.s:620 .bss.rlist:00000000 $d + .debug_frame:00000010 $d +C:\cygwin\tmp\ccNqiZol.s:483 .text.chSchWakeupS:0000005c $t +C:\cygwin\tmp\ccNqiZol.s:619 .text.chSchRescheduleS:00000018 $t + +UNDEFINED SYMBOLS +_port_switch +chVTSetI +chVTResetI diff --git a/Project/applications/smartcities/build/lst/chsem.lst b/Project/applications/smartcities/build/lst/chsem.lst new file mode 100644 index 0000000..0265c57 --- /dev/null +++ b/Project/applications/smartcities/build/lst/chsem.lst @@ -0,0 +1,4114 @@ +ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "chsem.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text.chSemInit,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .global chSemInit + 22 .thumb + 23 .thumb_func + 24 .type chSemInit, %function + 25 chSemInit: + 26 .LFB7: + 27 .file 1 "../..//os/kernel/src/chsem.c" + 28 .loc 1 86 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .LVL0: + 34 .loc 1 90 0 + 35 0000 4060 str r0, [r0, #4] + 36 0002 0060 str r0, [r0, #0] + 37 .loc 1 91 0 + 38 0004 8160 str r1, [r0, #8] + 39 0006 7047 bx lr + 40 .cfi_endproc + 41 .LFE7: + 42 .size chSemInit, .-chSemInit + 43 0008 AFF30080 .section .text.chSemResetI,"ax",%progbits + 43 AFF30080 + 44 .align 2 + 45 .p2align 4,,15 + 46 .global chSemResetI + 47 .thumb + 48 .thumb_func + 49 .type chSemResetI, %function + 50 chSemResetI: + 51 .LFB9: + 52 .loc 1 136 0 + 53 .cfi_startproc + 54 @ args = 0, pretend = 0, frame = 0 + 55 @ frame_needed = 0, uses_anonymous_args = 0 + 56 .LVL1: + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 2 + + + 57 0000 70B5 push {r4, r5, r6, lr} + 58 .LCFI0: + 59 .cfi_def_cfa_offset 16 + 60 .cfi_offset 4, -16 + 61 .cfi_offset 5, -12 + 62 .cfi_offset 6, -8 + 63 .cfi_offset 14, -4 + 64 .loc 1 141 0 + 65 0002 8568 ldr r5, [r0, #8] + 66 .LVL2: + 67 .loc 1 136 0 + 68 0004 0446 mov r4, r0 + 69 .loc 1 148 0 + 70 0006 0135 adds r5, r5, #1 + 71 .LVL3: + 72 0008 002D cmp r5, #0 + 73 .loc 1 147 0 + 74 000a 8160 str r1, [r0, #8] + 75 .LVL4: + 76 .loc 1 148 0 + 77 000c 0BDC bgt .L2 + 78 .loc 1 149 0 + 79 000e 6FF00106 mvn r6, #1 + 80 .LVL5: + 81 .L6: + 82 .LBB20: + 83 .LBB21: + 84 .file 2 "../..//os/kernel/include/chinline.h" + 85 .loc 2 67 0 + 86 0012 6068 ldr r0, [r4, #4] + 87 .LVL6: + 88 .LBE21: + 89 .LBE20: + 90 .loc 1 148 0 + 91 0014 0135 adds r5, r5, #1 + 92 .LVL7: + 93 .LBB23: + 94 .LBB22: + 95 .loc 2 69 0 + 96 0016 4368 ldr r3, [r0, #4] + 97 0018 6360 str r3, [r4, #4] + 98 001a 1C60 str r4, [r3, #0] + 99 .LBE22: + 100 .LBE23: + 101 .loc 1 149 0 + 102 001c FFF7FEFF bl chSchReadyI + 103 .LVL8: + 104 .loc 1 148 0 + 105 0020 012D cmp r5, #1 + 106 .loc 1 149 0 + 107 0022 4662 str r6, [r0, #36] + 108 .LVL9: + 109 .loc 1 148 0 + 110 0024 F5D1 bne .L6 + 111 .LVL10: + 112 .L2: + 113 0026 70BD pop {r4, r5, r6, pc} + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 3 + + + 114 .cfi_endproc + 115 .LFE9: + 116 .size chSemResetI, .-chSemResetI + 117 0028 AFF30080 .section .text.chSemReset,"ax",%progbits + 117 AFF30080 + 118 .align 2 + 119 .p2align 4,,15 + 120 .global chSemReset + 121 .thumb + 122 .thumb_func + 123 .type chSemReset, %function + 124 chSemReset: + 125 .LFB8: + 126 .loc 1 109 0 + 127 .cfi_startproc + 128 @ args = 0, pretend = 0, frame = 0 + 129 @ frame_needed = 0, uses_anonymous_args = 0 + 130 .LVL11: + 131 0000 08B5 push {r3, lr} + 132 .LCFI1: + 133 .cfi_def_cfa_offset 8 + 134 .cfi_offset 3, -8 + 135 .cfi_offset 14, -4 + 136 .loc 1 111 0 + 137 @ 111 "../..//os/kernel/src/chsem.c" 1 + 138 0002 72B6 cpsid i + 139 @ 0 "" 2 + 140 .loc 1 112 0 + 141 .thumb + 142 0004 FFF7FEFF bl chSemResetI + 143 .LVL12: + 144 .loc 1 113 0 + 145 0008 FFF7FEFF bl chSchRescheduleS + 146 .LVL13: + 147 .loc 1 114 0 + 148 @ 114 "../..//os/kernel/src/chsem.c" 1 + 149 000c 62B6 cpsie i + 150 @ 0 "" 2 + 151 .thumb + 152 000e 08BD pop {r3, pc} + 153 .cfi_endproc + 154 .LFE8: + 155 .size chSemReset, .-chSemReset + 156 .section .text.chSemWaitS,"ax",%progbits + 157 .align 2 + 158 .p2align 4,,15 + 159 .global chSemWaitS + 160 .thumb + 161 .thumb_func + 162 .type chSemWaitS, %function + 163 chSemWaitS: + 164 .LFB11: + 165 .loc 1 185 0 + 166 .cfi_startproc + 167 @ args = 0, pretend = 0, frame = 0 + 168 @ frame_needed = 0, uses_anonymous_args = 0 + 169 .LVL14: + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 4 + + + 170 .loc 1 194 0 + 171 0000 8268 ldr r2, [r0, #8] + 172 .loc 1 185 0 + 173 0002 10B5 push {r4, lr} + 174 .LCFI2: + 175 .cfi_def_cfa_offset 8 + 176 .cfi_offset 4, -8 + 177 .cfi_offset 14, -4 + 178 .loc 1 194 0 + 179 0004 013A subs r2, r2, #1 + 180 0006 002A cmp r2, #0 + 181 .loc 1 185 0 + 182 0008 0346 mov r3, r0 + 183 .loc 1 194 0 + 184 000a 8260 str r2, [r0, #8] + 185 000c 01DB blt .L13 + 186 .loc 1 200 0 + 187 000e 0020 movs r0, #0 + 188 .LVL15: + 189 .loc 1 201 0 + 190 0010 10BD pop {r4, pc} + 191 .LVL16: + 192 .L13: + 193 .loc 1 195 0 + 194 0012 074C ldr r4, .L14 + 195 .loc 1 197 0 + 196 0014 0320 movs r0, #3 + 197 .LVL17: + 198 .loc 1 195 0 + 199 0016 E269 ldr r2, [r4, #28] + 200 0018 5362 str r3, [r2, #36] + 201 .LVL18: + 202 .LBB24: + 203 .LBB25: + 204 .loc 2 55 0 + 205 001a 5968 ldr r1, [r3, #4] + 206 .loc 2 54 0 + 207 001c 1360 str r3, [r2, #0] + 208 .loc 2 55 0 + 209 001e 5160 str r1, [r2, #4] + 210 .loc 2 56 0 + 211 0020 5A60 str r2, [r3, #4] + 212 0022 0A60 str r2, [r1, #0] + 213 .LBE25: + 214 .LBE24: + 215 .loc 1 197 0 + 216 0024 FFF7FEFF bl chSchGoSleepS + 217 .LVL19: + 218 .loc 1 198 0 + 219 0028 E369 ldr r3, [r4, #28] + 220 002a 586A ldr r0, [r3, #36] + 221 002c 10BD pop {r4, pc} + 222 .L15: + 223 002e 00BF .align 2 + 224 .L14: + 225 0030 00000000 .word rlist + 226 .cfi_endproc + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 5 + + + 227 .LFE11: + 228 .size chSemWaitS, .-chSemWaitS + 229 0034 AFF30080 .section .text.chSemWait,"ax",%progbits + 229 AFF30080 + 229 AFF30080 + 230 .align 2 + 231 .p2align 4,,15 + 232 .global chSemWait + 233 .thumb + 234 .thumb_func + 235 .type chSemWait, %function + 236 chSemWait: + 237 .LFB10: + 238 .loc 1 164 0 + 239 .cfi_startproc + 240 @ args = 0, pretend = 0, frame = 0 + 241 @ frame_needed = 0, uses_anonymous_args = 0 + 242 .LVL20: + 243 0000 08B5 push {r3, lr} + 244 .LCFI3: + 245 .cfi_def_cfa_offset 8 + 246 .cfi_offset 3, -8 + 247 .cfi_offset 14, -4 + 248 .loc 1 167 0 + 249 @ 167 "../..//os/kernel/src/chsem.c" 1 + 250 0002 72B6 cpsid i + 251 @ 0 "" 2 + 252 .loc 1 168 0 + 253 .thumb + 254 0004 FFF7FEFF bl chSemWaitS + 255 .LVL21: + 256 .loc 1 169 0 + 257 @ 169 "../..//os/kernel/src/chsem.c" 1 + 258 0008 62B6 cpsie i + 259 @ 0 "" 2 + 260 .loc 1 171 0 + 261 .thumb + 262 000a 08BD pop {r3, pc} + 263 .cfi_endproc + 264 .LFE10: + 265 .size chSemWait, .-chSemWait + 266 000c AFF30080 .section .text.chSemWaitTimeoutS,"ax",%progbits + 267 .align 2 + 268 .p2align 4,,15 + 269 .global chSemWaitTimeoutS + 270 .thumb + 271 .thumb_func + 272 .type chSemWaitTimeoutS, %function + 273 chSemWaitTimeoutS: + 274 .LFB13: + 275 .loc 1 250 0 + 276 .cfi_startproc + 277 @ args = 0, pretend = 0, frame = 0 + 278 @ frame_needed = 0, uses_anonymous_args = 0 + 279 @ link register save eliminated. + 280 .LVL22: + 281 0000 0346 mov r3, r0 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 6 + + + 282 .loc 1 254 0 + 283 0002 8068 ldr r0, [r0, #8] + 284 .LVL23: + 285 .loc 1 250 0 + 286 0004 10B4 push {r4} + 287 .LCFI4: + 288 .cfi_def_cfa_offset 4 + 289 .cfi_offset 4, -4 + 290 .loc 1 259 0 + 291 0006 421E subs r2, r0, #1 + 292 0008 002A cmp r2, #0 + 293 .loc 1 250 0 + 294 000a 0C46 mov r4, r1 + 295 .loc 1 259 0 + 296 000c 9A60 str r2, [r3, #8] + 297 000e 02DB blt .L21 + 298 .loc 1 268 0 + 299 0010 0020 movs r0, #0 + 300 .L18: + 301 .loc 1 269 0 + 302 0012 10BC pop {r4} + 303 0014 7047 bx lr + 304 .L21: + 305 .loc 1 260 0 + 306 0016 59B1 cbz r1, .L22 + 307 .loc 1 264 0 + 308 0018 074A ldr r2, .L23 + 309 .loc 1 266 0 + 310 001a 0320 movs r0, #3 + 311 .loc 1 264 0 + 312 001c D269 ldr r2, [r2, #28] + 313 001e 5362 str r3, [r2, #36] + 314 .LVL24: + 315 .LBB26: + 316 .LBB27: + 317 .loc 2 55 0 + 318 0020 5C68 ldr r4, [r3, #4] + 319 0022 82E81800 stmia r2, {r3, r4} + 320 .loc 2 56 0 + 321 0026 5A60 str r2, [r3, #4] + 322 0028 2260 str r2, [r4, #0] + 323 .LBE27: + 324 .LBE26: + 325 .loc 1 269 0 + 326 002a 10BC pop {r4} + 327 .loc 1 266 0 + 328 002c FFF7FEBF b chSchGoSleepTimeoutS + 329 .LVL25: + 330 .L22: + 331 .loc 1 261 0 + 332 0030 9860 str r0, [r3, #8] + 333 .loc 1 262 0 + 334 0032 4FF0FF30 mov r0, #-1 + 335 0036 ECE7 b .L18 + 336 .L24: + 337 .align 2 + 338 .L23: + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 7 + + + 339 0038 00000000 .word rlist + 340 .cfi_endproc + 341 .LFE13: + 342 .size chSemWaitTimeoutS, .-chSemWaitTimeoutS + 343 003c AFF30080 .section .text.chSemWaitTimeout,"ax",%progbits + 344 .align 2 + 345 .p2align 4,,15 + 346 .global chSemWaitTimeout + 347 .thumb + 348 .thumb_func + 349 .type chSemWaitTimeout, %function + 350 chSemWaitTimeout: + 351 .LFB12: + 352 .loc 1 222 0 + 353 .cfi_startproc + 354 @ args = 0, pretend = 0, frame = 0 + 355 @ frame_needed = 0, uses_anonymous_args = 0 + 356 .LVL26: + 357 0000 08B5 push {r3, lr} + 358 .LCFI5: + 359 .cfi_def_cfa_offset 8 + 360 .cfi_offset 3, -8 + 361 .cfi_offset 14, -4 + 362 .loc 1 225 0 + 363 @ 225 "../..//os/kernel/src/chsem.c" 1 + 364 0002 72B6 cpsid i + 365 @ 0 "" 2 + 366 .loc 1 226 0 + 367 .thumb + 368 0004 FFF7FEFF bl chSemWaitTimeoutS + 369 .LVL27: + 370 .loc 1 227 0 + 371 @ 227 "../..//os/kernel/src/chsem.c" 1 + 372 0008 62B6 cpsie i + 373 @ 0 "" 2 + 374 .loc 1 229 0 + 375 .thumb + 376 000a 08BD pop {r3, pc} + 377 .cfi_endproc + 378 .LFE12: + 379 .size chSemWaitTimeout, .-chSemWaitTimeout + 380 000c AFF30080 .section .text.chSemSignal,"ax",%progbits + 381 .align 2 + 382 .p2align 4,,15 + 383 .global chSemSignal + 384 .thumb + 385 .thumb_func + 386 .type chSemSignal, %function + 387 chSemSignal: + 388 .LFB14: + 389 .loc 1 278 0 + 390 .cfi_startproc + 391 @ args = 0, pretend = 0, frame = 0 + 392 @ frame_needed = 0, uses_anonymous_args = 0 + 393 .LVL28: + 394 0000 08B5 push {r3, lr} + 395 .LCFI6: + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 8 + + + 396 .cfi_def_cfa_offset 8 + 397 .cfi_offset 3, -8 + 398 .cfi_offset 14, -4 + 399 .loc 1 278 0 + 400 0002 0346 mov r3, r0 + 401 .loc 1 282 0 + 402 @ 282 "../..//os/kernel/src/chsem.c" 1 + 403 0004 72B6 cpsid i + 404 @ 0 "" 2 + 405 .loc 1 289 0 + 406 .thumb + 407 0006 8268 ldr r2, [r0, #8] + 408 0008 0132 adds r2, r2, #1 + 409 000a 002A cmp r2, #0 + 410 000c 8260 str r2, [r0, #8] + 411 000e 01DD ble .L28 + 412 .loc 1 291 0 + 413 @ 291 "../..//os/kernel/src/chsem.c" 1 + 414 0010 62B6 cpsie i + 415 @ 0 "" 2 + 416 .thumb + 417 0012 08BD pop {r3, pc} + 418 .L28: + 419 .LVL29: + 420 .LBB28: + 421 .LBB29: + 422 .loc 2 60 0 + 423 0014 0068 ldr r0, [r0, #0] + 424 .LVL30: + 425 .LBE29: + 426 .LBE28: + 427 .loc 1 290 0 + 428 0016 0021 movs r1, #0 + 429 .LBB31: + 430 .LBB30: + 431 .loc 2 62 0 + 432 0018 0268 ldr r2, [r0, #0] + 433 001a 1A60 str r2, [r3, #0] + 434 001c 5360 str r3, [r2, #4] + 435 .LBE30: + 436 .LBE31: + 437 .loc 1 290 0 + 438 001e FFF7FEFF bl chSchWakeupS + 439 .LVL31: + 440 .loc 1 291 0 + 441 @ 291 "../..//os/kernel/src/chsem.c" 1 + 442 0022 62B6 cpsie i + 443 @ 0 "" 2 + 444 .thumb + 445 0024 08BD pop {r3, pc} + 446 .cfi_endproc + 447 .LFE14: + 448 .size chSemSignal, .-chSemSignal + 449 0026 00BFAFF3 .section .text.chSemSignalI,"ax",%progbits + 449 0080AFF3 + 449 0080 + 450 .align 2 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 9 + + + 451 .p2align 4,,15 + 452 .global chSemSignalI + 453 .thumb + 454 .thumb_func + 455 .type chSemSignalI, %function + 456 chSemSignalI: + 457 .LFB15: + 458 .loc 1 305 0 + 459 .cfi_startproc + 460 @ args = 0, pretend = 0, frame = 0 + 461 @ frame_needed = 0, uses_anonymous_args = 0 + 462 @ link register save eliminated. + 463 .LVL32: + 464 .loc 1 314 0 + 465 0000 8268 ldr r2, [r0, #8] + 466 .loc 1 305 0 + 467 0002 0346 mov r3, r0 + 468 .loc 1 314 0 + 469 0004 0132 adds r2, r2, #1 + 470 0006 002A cmp r2, #0 + 471 0008 8260 str r2, [r0, #8] + 472 000a 00DD ble .L31 + 473 000c 7047 bx lr + 474 .L31: + 475 .LVL33: + 476 .LBB32: + 477 .LBB33: + 478 .LBB34: + 479 .loc 2 60 0 + 480 000e 0268 ldr r2, [r0, #0] + 481 .LVL34: + 482 .loc 2 62 0 + 483 0010 1168 ldr r1, [r2, #0] + 484 .LBE34: + 485 .LBE33: + 486 .loc 1 319 0 + 487 0012 1046 mov r0, r2 + 488 .LVL35: + 489 .LBB36: + 490 .LBB35: + 491 .loc 2 62 0 + 492 0014 1960 str r1, [r3, #0] + 493 0016 4B60 str r3, [r1, #4] + 494 .LBE35: + 495 .LBE36: + 496 .loc 1 318 0 + 497 0018 0023 movs r3, #0 + 498 .LVL36: + 499 001a 5362 str r3, [r2, #36] + 500 .LBE32: + 501 .loc 1 321 0 + 502 .LBB37: + 503 .loc 1 319 0 + 504 001c FFF7FEBF b chSchReadyI + 505 .LVL37: + 506 .LBE37: + 507 .cfi_endproc + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 10 + + + 508 .LFE15: + 509 .size chSemSignalI, .-chSemSignalI + 510 .section .text.chSemAddCounterI,"ax",%progbits + 511 .align 2 + 512 .p2align 4,,15 + 513 .global chSemAddCounterI + 514 .thumb + 515 .thumb_func + 516 .type chSemAddCounterI, %function + 517 chSemAddCounterI: + 518 .LFB16: + 519 .loc 1 336 0 + 520 .cfi_startproc + 521 @ args = 0, pretend = 0, frame = 0 + 522 @ frame_needed = 0, uses_anonymous_args = 0 + 523 .LVL38: + 524 0000 70B5 push {r4, r5, r6, lr} + 525 .LCFI7: + 526 .cfi_def_cfa_offset 16 + 527 .cfi_offset 4, -16 + 528 .cfi_offset 5, -12 + 529 .cfi_offset 6, -8 + 530 .cfi_offset 14, -4 + 531 .loc 1 345 0 + 532 0002 0C1E subs r4, r1, #0 + 533 .loc 1 336 0 + 534 0004 0546 mov r5, r0 + 535 .loc 1 345 0 + 536 0006 11DD ble .L32 + 537 .loc 1 347 0 + 538 0008 0026 movs r6, #0 + 539 000a 01E0 b .L37 + 540 .LVL39: + 541 .L34: + 542 .loc 1 345 0 + 543 000c 013C subs r4, r4, #1 + 544 .LVL40: + 545 000e 0DD0 beq .L32 + 546 .LVL41: + 547 .L37: + 548 .loc 1 346 0 + 549 0010 AB68 ldr r3, [r5, #8] + 550 0012 0133 adds r3, r3, #1 + 551 0014 002B cmp r3, #0 + 552 0016 AB60 str r3, [r5, #8] + 553 0018 F8DC bgt .L34 + 554 .LVL42: + 555 .LBB38: + 556 .LBB39: + 557 .loc 2 60 0 + 558 001a 2868 ldr r0, [r5, #0] + 559 .LVL43: + 560 .loc 2 62 0 + 561 001c 0368 ldr r3, [r0, #0] + 562 001e 2B60 str r3, [r5, #0] + 563 0020 5D60 str r5, [r3, #4] + 564 .LBE39: + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 11 + + + 565 .LBE38: + 566 .loc 1 347 0 + 567 0022 FFF7FEFF bl chSchReadyI + 568 .LVL44: + 569 .loc 1 345 0 + 570 0026 013C subs r4, r4, #1 + 571 .loc 1 347 0 + 572 0028 4662 str r6, [r0, #36] + 573 .loc 1 345 0 + 574 002a F1D1 bne .L37 + 575 .LVL45: + 576 .L32: + 577 002c 70BD pop {r4, r5, r6, pc} + 578 .cfi_endproc + 579 .LFE16: + 580 .size chSemAddCounterI, .-chSemAddCounterI + 581 002e 00BF .section .text.chSemSignalWait,"ax",%progbits + 582 .align 2 + 583 .p2align 4,,15 + 584 .global chSemSignalWait + 585 .thumb + 586 .thumb_func + 587 .type chSemSignalWait, %function + 588 chSemSignalWait: + 589 .LFB17: + 590 .loc 1 368 0 + 591 .cfi_startproc + 592 @ args = 0, pretend = 0, frame = 8 + 593 @ frame_needed = 0, uses_anonymous_args = 0 + 594 .LVL46: + 595 0000 10B5 push {r4, lr} + 596 .LCFI8: + 597 .cfi_def_cfa_offset 8 + 598 .cfi_offset 4, -8 + 599 .cfi_offset 14, -4 + 600 0002 0346 mov r3, r0 + 601 0004 82B0 sub sp, sp, #8 + 602 .LCFI9: + 603 .cfi_def_cfa_offset 16 + 604 .loc 1 381 0 + 605 @ 381 "../..//os/kernel/src/chsem.c" 1 + 606 0006 72B6 cpsid i + 607 @ 0 "" 2 + 608 .loc 1 382 0 + 609 .thumb + 610 0008 8268 ldr r2, [r0, #8] + 611 000a 0132 adds r2, r2, #1 + 612 000c 002A cmp r2, #0 + 613 000e 8260 str r2, [r0, #8] + 614 0010 17DD ble .L43 + 615 .LVL47: + 616 .L40: + 617 .loc 1 384 0 + 618 0012 8B68 ldr r3, [r1, #8] + 619 0014 013B subs r3, r3, #1 + 620 0016 002B cmp r3, #0 + 621 0018 8B60 str r3, [r1, #8] + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 12 + + + 622 001a 05DB blt .L44 + 623 .loc 1 392 0 + 624 001c FFF7FEFF bl chSchRescheduleS + 625 .LVL48: + 626 .loc 1 393 0 + 627 0020 0020 movs r0, #0 + 628 .LVL49: + 629 .L42: + 630 .loc 1 395 0 + 631 @ 395 "../..//os/kernel/src/chsem.c" 1 + 632 0022 62B6 cpsie i + 633 @ 0 "" 2 + 634 .loc 1 397 0 + 635 .thumb + 636 0024 02B0 add sp, sp, #8 + 637 0026 10BD pop {r4, pc} + 638 .LVL50: + 639 .L44: + 640 .LBB40: + 641 .loc 1 385 0 + 642 0028 0B4A ldr r2, .L45 + 643 .LBB41: + 644 .LBB42: + 645 .loc 2 55 0 + 646 002a 4B68 ldr r3, [r1, #4] + 647 .LBE42: + 648 .LBE41: + 649 .loc 1 385 0 + 650 002c D469 ldr r4, [r2, #28] + 651 .LVL51: + 652 .loc 1 388 0 + 653 002e 0320 movs r0, #3 + 654 .LBB44: + 655 .LBB43: + 656 .loc 2 55 0 + 657 0030 84E80A00 stmia r4, {r1, r3} + 658 .loc 2 56 0 + 659 0034 4C60 str r4, [r1, #4] + 660 0036 1C60 str r4, [r3, #0] + 661 .LBE43: + 662 .LBE44: + 663 .loc 1 387 0 + 664 0038 6162 str r1, [r4, #36] + 665 .loc 1 388 0 + 666 003a FFF7FEFF bl chSchGoSleepS + 667 .LVL52: + 668 .loc 1 389 0 + 669 003e 606A ldr r0, [r4, #36] + 670 .LVL53: + 671 0040 EFE7 b .L42 + 672 .LVL54: + 673 .L43: + 674 .LBE40: + 675 .LBB45: + 676 .LBB46: + 677 .loc 2 60 0 + 678 0042 0068 ldr r0, [r0, #0] + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 13 + + + 679 .LVL55: + 680 .loc 2 62 0 + 681 0044 0268 ldr r2, [r0, #0] + 682 0046 1A60 str r2, [r3, #0] + 683 0048 5360 str r3, [r2, #4] + 684 .LBE46: + 685 .LBE45: + 686 .loc 1 383 0 + 687 004a 0191 str r1, [sp, #4] + 688 004c FFF7FEFF bl chSchReadyI + 689 .LVL56: + 690 0050 0023 movs r3, #0 + 691 0052 4362 str r3, [r0, #36] + 692 0054 0199 ldr r1, [sp, #4] + 693 0056 DCE7 b .L40 + 694 .L46: + 695 .align 2 + 696 .L45: + 697 0058 00000000 .word rlist + 698 .cfi_endproc + 699 .LFE17: + 700 .size chSemSignalWait, .-chSemSignalWait + 701 005c AFF30080 .text + 702 .Letext0: + 703 .file 3 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 704 .file 4 "../..//os/ports/GCC/ARMCMx/chtypes.h" + 705 .file 5 "../..//os/kernel/include/chlists.h" + 706 .file 6 "../..//os/kernel/include/chthreads.h" + 707 .file 7 "../..//os/ports/GCC/ARMCMx/chcore_v7m.h" + 708 .file 8 "../..//os/kernel/include/chschd.h" + 709 .file 9 "../..//os/kernel/include/chsem.h" + 710 .file 10 "../..//os/kernel/include/chmtx.h" + 711 .section .debug_info,"",%progbits + 712 .Ldebug_info0: + 713 0000 150A0000 .4byte 0xa15 + 714 0004 0200 .2byte 0x2 + 715 0006 00000000 .4byte .Ldebug_abbrev0 + 716 000a 04 .byte 0x4 + 717 000b 01 .uleb128 0x1 + 718 000c FA010000 .4byte .LASF81 + 719 0010 01 .byte 0x1 + 720 0011 4B010000 .4byte .LASF82 + 721 0015 A5010000 .4byte .LASF83 + 722 0019 C0000000 .4byte .Ldebug_ranges0+0xc0 + 723 001d 00000000 .4byte 0 + 724 0021 00000000 .4byte 0 + 725 0025 00000000 .4byte .Ldebug_line0 + 726 0029 02 .uleb128 0x2 + 727 002a 04 .byte 0x4 + 728 002b 05 .byte 0x5 + 729 002c 696E7400 .ascii "int\000" + 730 0030 03 .uleb128 0x3 + 731 0031 04 .byte 0x4 + 732 0032 07 .byte 0x7 + 733 0033 EF000000 .4byte .LASF0 + 734 0037 03 .uleb128 0x3 + 735 0038 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 14 + + + 736 0039 06 .byte 0x6 + 737 003a 6D000000 .4byte .LASF1 + 738 003e 04 .uleb128 0x4 + 739 003f 74030000 .4byte .LASF5 + 740 0043 03 .byte 0x3 + 741 0044 2A .byte 0x2a + 742 0045 49000000 .4byte 0x49 + 743 0049 03 .uleb128 0x3 + 744 004a 01 .byte 0x1 + 745 004b 08 .byte 0x8 + 746 004c 37020000 .4byte .LASF2 + 747 0050 03 .uleb128 0x3 + 748 0051 02 .byte 0x2 + 749 0052 05 .byte 0x5 + 750 0053 4F020000 .4byte .LASF3 + 751 0057 03 .uleb128 0x3 + 752 0058 02 .byte 0x2 + 753 0059 07 .byte 0x7 + 754 005a 2D010000 .4byte .LASF4 + 755 005e 04 .uleb128 0x4 + 756 005f 2F020000 .4byte .LASF6 + 757 0063 03 .byte 0x3 + 758 0064 4F .byte 0x4f + 759 0065 69000000 .4byte 0x69 + 760 0069 03 .uleb128 0x3 + 761 006a 04 .byte 0x4 + 762 006b 05 .byte 0x5 + 763 006c 99000000 .4byte .LASF7 + 764 0070 04 .uleb128 0x4 + 765 0071 A9020000 .4byte .LASF8 + 766 0075 03 .byte 0x3 + 767 0076 50 .byte 0x50 + 768 0077 7B000000 .4byte 0x7b + 769 007b 03 .uleb128 0x3 + 770 007c 04 .byte 0x4 + 771 007d 07 .byte 0x7 + 772 007e 0D010000 .4byte .LASF9 + 773 0082 03 .uleb128 0x3 + 774 0083 08 .byte 0x8 + 775 0084 05 .byte 0x5 + 776 0085 5F000000 .4byte .LASF10 + 777 0089 03 .uleb128 0x3 + 778 008a 08 .byte 0x8 + 779 008b 07 .byte 0x7 + 780 008c 27000000 .4byte .LASF11 + 781 0090 04 .uleb128 0x4 + 782 0091 6E010000 .4byte .LASF12 + 783 0095 04 .byte 0x4 + 784 0096 2F .byte 0x2f + 785 0097 3E000000 .4byte 0x3e + 786 009b 04 .uleb128 0x4 + 787 009c A2000000 .4byte .LASF13 + 788 00a0 04 .byte 0x4 + 789 00a1 30 .byte 0x30 + 790 00a2 3E000000 .4byte 0x3e + 791 00a6 04 .uleb128 0x4 + 792 00a7 18020000 .4byte .LASF14 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 15 + + + 793 00ab 04 .byte 0x4 + 794 00ac 31 .byte 0x31 + 795 00ad 3E000000 .4byte 0x3e + 796 00b1 04 .uleb128 0x4 + 797 00b2 27020000 .4byte .LASF15 + 798 00b6 04 .byte 0x4 + 799 00b7 32 .byte 0x32 + 800 00b8 70000000 .4byte 0x70 + 801 00bc 04 .uleb128 0x4 + 802 00bd 68010000 .4byte .LASF16 + 803 00c1 04 .byte 0x4 + 804 00c2 33 .byte 0x33 + 805 00c3 5E000000 .4byte 0x5e + 806 00c7 04 .uleb128 0x4 + 807 00c8 82010000 .4byte .LASF17 + 808 00cc 04 .byte 0x4 + 809 00cd 35 .byte 0x35 + 810 00ce 70000000 .4byte 0x70 + 811 00d2 04 .uleb128 0x4 + 812 00d3 F0020000 .4byte .LASF18 + 813 00d7 04 .byte 0x4 + 814 00d8 36 .byte 0x36 + 815 00d9 70000000 .4byte 0x70 + 816 00dd 04 .uleb128 0x4 + 817 00de E9000000 .4byte .LASF19 + 818 00e2 04 .byte 0x4 + 819 00e3 37 .byte 0x37 + 820 00e4 5E000000 .4byte 0x5e + 821 00e8 04 .uleb128 0x4 + 822 00e9 89020000 .4byte .LASF20 + 823 00ed 05 .byte 0x5 + 824 00ee 2A .byte 0x2a + 825 00ef F3000000 .4byte 0xf3 + 826 00f3 05 .uleb128 0x5 + 827 00f4 89020000 .4byte .LASF20 + 828 00f8 48 .byte 0x48 + 829 00f9 06 .byte 0x6 + 830 00fa 5E .byte 0x5e + 831 00fb 0A020000 .4byte 0x20a + 832 00ff 06 .uleb128 0x6 + 833 0100 6F020000 .4byte .LASF21 + 834 0104 06 .byte 0x6 + 835 0105 5F .byte 0x5f + 836 0106 2F020000 .4byte 0x22f + 837 010a 02 .byte 0x2 + 838 010b 23 .byte 0x23 + 839 010c 00 .uleb128 0 + 840 010d 06 .uleb128 0x6 + 841 010e 20020000 .4byte .LASF22 + 842 0112 06 .byte 0x6 + 843 0113 61 .byte 0x61 + 844 0114 2F020000 .4byte 0x22f + 845 0118 02 .byte 0x2 + 846 0119 23 .byte 0x23 + 847 011a 04 .uleb128 0x4 + 848 011b 06 .uleb128 0x6 + 849 011c 58000000 .4byte .LASF23 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 16 + + + 850 0120 06 .byte 0x6 + 851 0121 63 .byte 0x63 + 852 0122 B1000000 .4byte 0xb1 + 853 0126 02 .byte 0x2 + 854 0127 23 .byte 0x23 + 855 0128 08 .uleb128 0x8 + 856 0129 06 .uleb128 0x6 + 857 012a B1030000 .4byte .LASF24 + 858 012e 06 .byte 0x6 + 859 012f 64 .byte 0x64 + 860 0130 FC020000 .4byte 0x2fc + 861 0134 02 .byte 0x2 + 862 0135 23 .byte 0x23 + 863 0136 0C .uleb128 0xc + 864 0137 06 .uleb128 0x6 + 865 0138 B7000000 .4byte .LASF25 + 866 013c 06 .byte 0x6 + 867 013d 66 .byte 0x66 + 868 013e 2F020000 .4byte 0x22f + 869 0142 02 .byte 0x2 + 870 0143 23 .byte 0x23 + 871 0144 10 .uleb128 0x10 + 872 0145 06 .uleb128 0x6 + 873 0146 9D010000 .4byte .LASF26 + 874 014a 06 .byte 0x6 + 875 014b 67 .byte 0x67 + 876 014c 2F020000 .4byte 0x22f + 877 0150 02 .byte 0x2 + 878 0151 23 .byte 0x23 + 879 0152 14 .uleb128 0x14 + 880 0153 06 .uleb128 0x6 + 881 0154 83030000 .4byte .LASF27 + 882 0158 06 .byte 0x6 + 883 0159 6E .byte 0x6e + 884 015a 52040000 .4byte 0x452 + 885 015e 02 .byte 0x2 + 886 015f 23 .byte 0x23 + 887 0160 18 .uleb128 0x18 + 888 0161 06 .uleb128 0x6 + 889 0162 59020000 .4byte .LASF28 + 890 0166 06 .byte 0x6 + 891 0167 79 .byte 0x79 + 892 0168 9B000000 .4byte 0x9b + 893 016c 02 .byte 0x2 + 894 016d 23 .byte 0x23 + 895 016e 1C .uleb128 0x1c + 896 016f 06 .uleb128 0x6 + 897 0170 76020000 .4byte .LASF29 + 898 0174 06 .byte 0x6 + 899 0175 7D .byte 0x7d + 900 0176 90000000 .4byte 0x90 + 901 017a 02 .byte 0x2 + 902 017b 23 .byte 0x23 + 903 017c 1D .uleb128 0x1d + 904 017d 06 .uleb128 0x6 + 905 017e 51030000 .4byte .LASF30 + 906 0182 06 .byte 0x6 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 17 + + + 907 0183 82 .byte 0x82 + 908 0184 A6000000 .4byte 0xa6 + 909 0188 02 .byte 0x2 + 910 0189 23 .byte 0x23 + 911 018a 1E .uleb128 0x1e + 912 018b 06 .uleb128 0x6 + 913 018c 0F030000 .4byte .LASF31 + 914 0190 06 .byte 0x6 + 915 0191 89 .byte 0x89 + 916 0192 26030000 .4byte 0x326 + 917 0196 02 .byte 0x2 + 918 0197 23 .byte 0x23 + 919 0198 20 .uleb128 0x20 + 920 0199 07 .uleb128 0x7 + 921 019a 705F7500 .ascii "p_u\000" + 922 019e 06 .byte 0x6 + 923 019f AE .byte 0xae + 924 01a0 1D040000 .4byte 0x41d + 925 01a4 02 .byte 0x2 + 926 01a5 23 .byte 0x23 + 927 01a6 24 .uleb128 0x24 + 928 01a7 06 .uleb128 0x6 + 929 01a8 B7030000 .4byte .LASF32 + 930 01ac 06 .byte 0x6 + 931 01ad B3 .byte 0xb3 + 932 01ae 57020000 .4byte 0x257 + 933 01b2 02 .byte 0x2 + 934 01b3 23 .byte 0x23 + 935 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0520 01 .byte 0x1 + 1412 0521 00000000 .4byte .LFB9 + 1413 0525 28000000 .4byte .LFE9 + 1414 0529 00000000 .4byte .LLST0 + 1415 052d 01 .byte 0x1 + 1416 052e 92050000 .4byte 0x592 + 1417 0532 18 .uleb128 0x18 + 1418 0533 737000 .ascii "sp\000" + 1419 0536 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 26 + + + 1420 0537 88 .byte 0x88 + 1421 0538 12050000 .4byte 0x512 + 1422 053c 20000000 .4byte .LLST1 + 1423 0540 18 .uleb128 0x18 + 1424 0541 6E00 .ascii "n\000" + 1425 0543 01 .byte 0x1 + 1426 0544 88 .byte 0x88 + 1427 0545 DD000000 .4byte 0xdd + 1428 0549 3E000000 .4byte .LLST2 + 1429 054d 19 .uleb128 0x19 + 1430 054e 636E7400 .ascii "cnt\000" + 1431 0552 01 .byte 0x1 + 1432 0553 89 .byte 0x89 + 1433 0554 DD000000 .4byte 0xdd + 1434 0558 5F000000 .4byte .LLST3 + 1435 055c 1A .uleb128 0x1a + 1436 055d 6A040000 .4byte 0x46a + 1437 0561 12000000 .4byte .LBB20 + 1438 0565 00000000 .4byte .Ldebug_ranges0+0 + 1439 0569 01 .byte 0x1 + 1440 056a 95 .byte 0x95 + 1441 056b 88050000 .4byte 0x588 + 1442 056f 1B .uleb128 0x1b + 1443 0570 7B040000 .4byte 0x47b + 1444 0574 A1000000 .4byte .LLST4 + 1445 0578 1C .uleb128 0x1c + 1446 0579 18000000 .4byte .Ldebug_ranges0+0x18 + 1447 057d 1D .uleb128 0x1d + 1448 057e 86040000 .4byte 0x486 + 1449 0582 B4000000 .4byte .LLST5 + 1450 0586 00 .byte 0 + 1451 0587 00 .byte 0 + 1452 0588 1E .uleb128 0x1e + 1453 0589 20000000 .4byte .LVL8 + 1454 058d B0090000 .4byte 0x9b0 + 1455 0591 00 .byte 0 + 1456 0592 17 .uleb128 0x17 + 1457 0593 01 .byte 0x1 + 1458 0594 40010000 .4byte .LASF69 + 1459 0598 01 .byte 0x1 + 1460 0599 6D .byte 0x6d + 1461 059a 01 .byte 0x1 + 1462 059b 00000000 .4byte .LFB8 + 1463 059f 10000000 .4byte .LFE8 + 1464 05a3 C7000000 .4byte .LLST6 + 1465 05a7 01 .byte 0x1 + 1466 05a8 ED050000 .4byte 0x5ed + 1467 05ac 18 .uleb128 0x18 + 1468 05ad 737000 .ascii "sp\000" + 1469 05b0 01 .byte 0x1 + 1470 05b1 6D .byte 0x6d + 1471 05b2 12050000 .4byte 0x512 + 1472 05b6 E7000000 .4byte .LLST7 + 1473 05ba 18 .uleb128 0x18 + 1474 05bb 6E00 .ascii "n\000" + 1475 05bd 01 .byte 0x1 + 1476 05be 6D .byte 0x6d + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 27 + + + 1477 05bf DD000000 .4byte 0xdd + 1478 05c3 08010000 .4byte .LLST8 + 1479 05c7 1F .uleb128 0x1f + 1480 05c8 08000000 .4byte .LVL12 + 1481 05cc 18050000 .4byte 0x518 + 1482 05d0 E3050000 .4byte 0x5e3 + 1483 05d4 20 .uleb128 0x20 + 1484 05d5 01 .byte 0x1 + 1485 05d6 51 .byte 0x51 + 1486 05d7 03 .byte 0x3 + 1487 05d8 F3 .byte 0xf3 + 1488 05d9 01 .uleb128 0x1 + 1489 05da 51 .byte 0x51 + 1490 05db 20 .uleb128 0x20 + 1491 05dc 01 .byte 0x1 + 1492 05dd 50 .byte 0x50 + 1493 05de 03 .byte 0x3 + 1494 05df F3 .byte 0xf3 + 1495 05e0 01 .uleb128 0x1 + 1496 05e1 50 .byte 0x50 + 1497 05e2 00 .byte 0 + 1498 05e3 1E .uleb128 0x1e + 1499 05e4 0C000000 .4byte .LVL13 + 1500 05e8 C8090000 .4byte 0x9c8 + 1501 05ec 00 .byte 0 + 1502 05ed 21 .uleb128 0x21 + 1503 05ee 01 .byte 0x1 + 1504 05ef 7E020000 .4byte .LASF70 + 1505 05f3 01 .byte 0x1 + 1506 05f4 B9 .byte 0xb9 + 1507 05f5 01 .byte 0x1 + 1508 05f6 BC000000 .4byte 0xbc + 1509 05fa 00000000 .4byte .LFB11 + 1510 05fe 34000000 .4byte .LFE11 + 1511 0602 29010000 .4byte .LLST9 + 1512 0606 01 .byte 0x1 + 1513 0607 4F060000 .4byte 0x64f + 1514 060b 18 .uleb128 0x18 + 1515 060c 737000 .ascii "sp\000" + 1516 060f 01 .byte 0x1 + 1517 0610 B9 .byte 0xb9 + 1518 0611 12050000 .4byte 0x512 + 1519 0615 49010000 .4byte .LLST10 + 1520 0619 22 .uleb128 0x22 + 1521 061a 97040000 .4byte 0x497 + 1522 061e 1A000000 .4byte .LBB24 + 1523 0622 24000000 .4byte .LBE24 + 1524 0626 01 .byte 0x1 + 1525 0627 C4 .byte 0xc4 + 1526 0628 3F060000 .4byte 0x63f + 1527 062c 1B .uleb128 0x1b + 1528 062d AE040000 .4byte 0x4ae + 1529 0631 8B010000 .4byte .LLST11 + 1530 0635 1B .uleb128 0x1b + 1531 0636 A4040000 .4byte 0x4a4 + 1532 063a AD010000 .4byte .LLST12 + 1533 063e 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 28 + + + 1534 063f 23 .uleb128 0x23 + 1535 0640 28000000 .4byte .LVL19 + 1536 0644 D2090000 .4byte 0x9d2 + 1537 0648 20 .uleb128 0x20 + 1538 0649 01 .byte 0x1 + 1539 064a 50 .byte 0x50 + 1540 064b 01 .byte 0x1 + 1541 064c 33 .byte 0x33 + 1542 064d 00 .byte 0 + 1543 064e 00 .byte 0 + 1544 064f 21 .uleb128 0x21 + 1545 0650 01 .byte 0x1 + 1546 0651 05030000 .4byte .LASF71 + 1547 0655 01 .byte 0x1 + 1548 0656 A4 .byte 0xa4 + 1549 0657 01 .byte 0x1 + 1550 0658 BC000000 .4byte 0xbc + 1551 065c 00000000 .4byte .LFB10 + 1552 0660 0C000000 .4byte .LFE10 + 1553 0664 C0010000 .4byte .LLST13 + 1554 0668 01 .byte 0x1 + 1555 0669 9A060000 .4byte 0x69a + 1556 066d 18 .uleb128 0x18 + 1557 066e 737000 .ascii "sp\000" + 1558 0671 01 .byte 0x1 + 1559 0672 A4 .byte 0xa4 + 1560 0673 12050000 .4byte 0x512 + 1561 0677 E0010000 .4byte .LLST14 + 1562 067b 24 .uleb128 0x24 + 1563 067c 6D736700 .ascii "msg\000" + 1564 0680 01 .byte 0x1 + 1565 0681 A5 .byte 0xa5 + 1566 0682 BC000000 .4byte 0xbc + 1567 0686 01 .byte 0x1 + 1568 0687 50 .byte 0x50 + 1569 0688 23 .uleb128 0x23 + 1570 0689 08000000 .4byte .LVL21 + 1571 068d ED050000 .4byte 0x5ed + 1572 0691 20 .uleb128 0x20 + 1573 0692 01 .byte 0x1 + 1574 0693 50 .byte 0x50 + 1575 0694 03 .byte 0x3 + 1576 0695 F3 .byte 0xf3 + 1577 0696 01 .uleb128 0x1 + 1578 0697 50 .byte 0x50 + 1579 0698 00 .byte 0 + 1580 0699 00 .byte 0 + 1581 069a 21 .uleb128 0x21 + 1582 069b 01 .byte 0x1 + 1583 069c D7020000 .4byte .LASF72 + 1584 06a0 01 .byte 0x1 + 1585 06a1 FA .byte 0xfa + 1586 06a2 01 .byte 0x1 + 1587 06a3 BC000000 .4byte 0xbc + 1588 06a7 00000000 .4byte .LFB13 + 1589 06ab 3C000000 .4byte .LFE13 + 1590 06af 01020000 .4byte .LLST15 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 29 + + + 1591 06b3 01 .byte 0x1 + 1592 06b4 0D070000 .4byte 0x70d + 1593 06b8 18 .uleb128 0x18 + 1594 06b9 737000 .ascii "sp\000" + 1595 06bc 01 .byte 0x1 + 1596 06bd FA .byte 0xfa + 1597 06be 12050000 .4byte 0x512 + 1598 06c2 21020000 .4byte .LLST16 + 1599 06c6 25 .uleb128 0x25 + 1600 06c7 F5010000 .4byte .LASF73 + 1601 06cb 01 .byte 0x1 + 1602 06cc FA .byte 0xfa + 1603 06cd D2000000 .4byte 0xd2 + 1604 06d1 58020000 .4byte .LLST17 + 1605 06d5 26 .uleb128 0x26 + 1606 06d6 97040000 .4byte 0x497 + 1607 06da 20000000 .4byte .LBB26 + 1608 06de 2A000000 .4byte .LBE26 + 1609 06e2 01 .byte 0x1 + 1610 06e3 0901 .2byte 0x109 + 1611 06e5 FC060000 .4byte 0x6fc + 1612 06e9 1B .uleb128 0x1b + 1613 06ea AE040000 .4byte 0x4ae + 1614 06ee 84020000 .4byte .LLST18 + 1615 06f2 1B .uleb128 0x1b + 1616 06f3 A4040000 .4byte 0x4a4 + 1617 06f7 A6020000 .4byte .LLST19 + 1618 06fb 00 .byte 0 + 1619 06fc 27 .uleb128 0x27 + 1620 06fd 30000000 .4byte .LVL25 + 1621 0701 01 .byte 0x1 + 1622 0702 E6090000 .4byte 0x9e6 + 1623 0706 20 .uleb128 0x20 + 1624 0707 01 .byte 0x1 + 1625 0708 50 .byte 0x50 + 1626 0709 01 .byte 0x1 + 1627 070a 33 .byte 0x33 + 1628 070b 00 .byte 0 + 1629 070c 00 .byte 0 + 1630 070d 21 .uleb128 0x21 + 1631 070e 01 .byte 0x1 + 1632 070f FC000000 .4byte .LASF74 + 1633 0713 01 .byte 0x1 + 1634 0714 DE .byte 0xde + 1635 0715 01 .byte 0x1 + 1636 0716 BC000000 .4byte 0xbc + 1637 071a 00000000 .4byte .LFB12 + 1638 071e 0C000000 .4byte .LFE12 + 1639 0722 B9020000 .4byte .LLST20 + 1640 0726 01 .byte 0x1 + 1641 0727 6E070000 .4byte 0x76e + 1642 072b 18 .uleb128 0x18 + 1643 072c 737000 .ascii "sp\000" + 1644 072f 01 .byte 0x1 + 1645 0730 DE .byte 0xde + 1646 0731 12050000 .4byte 0x512 + 1647 0735 D9020000 .4byte .LLST21 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 30 + + + 1648 0739 25 .uleb128 0x25 + 1649 073a F5010000 .4byte .LASF73 + 1650 073e 01 .byte 0x1 + 1651 073f DE .byte 0xde + 1652 0740 D2000000 .4byte 0xd2 + 1653 0744 FA020000 .4byte .LLST22 + 1654 0748 24 .uleb128 0x24 + 1655 0749 6D736700 .ascii "msg\000" + 1656 074d 01 .byte 0x1 + 1657 074e DF .byte 0xdf + 1658 074f BC000000 .4byte 0xbc + 1659 0753 01 .byte 0x1 + 1660 0754 50 .byte 0x50 + 1661 0755 23 .uleb128 0x23 + 1662 0756 08000000 .4byte .LVL27 + 1663 075a 9A060000 .4byte 0x69a + 1664 075e 20 .uleb128 0x20 + 1665 075f 01 .byte 0x1 + 1666 0760 51 .byte 0x51 + 1667 0761 03 .byte 0x3 + 1668 0762 F3 .byte 0xf3 + 1669 0763 01 .uleb128 0x1 + 1670 0764 51 .byte 0x51 + 1671 0765 20 .uleb128 0x20 + 1672 0766 01 .byte 0x1 + 1673 0767 50 .byte 0x50 + 1674 0768 03 .byte 0x3 + 1675 0769 F3 .byte 0xf3 + 1676 076a 01 .uleb128 0x1 + 1677 076b 50 .byte 0x50 + 1678 076c 00 .byte 0 + 1679 076d 00 .byte 0 + 1680 076e 28 .uleb128 0x28 + 1681 076f 01 .byte 0x1 + 1682 0770 AB000000 .4byte .LASF75 + 1683 0774 01 .byte 0x1 + 1684 0775 1601 .2byte 0x116 + 1685 0777 01 .byte 0x1 + 1686 0778 00000000 .4byte .LFB14 + 1687 077c 26000000 .4byte .LFE14 + 1688 0780 1B030000 .4byte .LLST23 + 1689 0784 01 .byte 0x1 + 1690 0785 D5070000 .4byte 0x7d5 + 1691 0789 29 .uleb128 0x29 + 1692 078a 737000 .ascii "sp\000" + 1693 078d 01 .byte 0x1 + 1694 078e 1601 .2byte 0x116 + 1695 0790 12050000 .4byte 0x512 + 1696 0794 3B030000 .4byte .LLST24 + 1697 0798 2A .uleb128 0x2a + 1698 0799 BA040000 .4byte 0x4ba + 1699 079d 14000000 .4byte .LBB28 + 1700 07a1 30000000 .4byte .Ldebug_ranges0+0x30 + 1701 07a5 01 .byte 0x1 + 1702 07a6 2201 .2byte 0x122 + 1703 07a8 C5070000 .4byte 0x7c5 + 1704 07ac 1B .uleb128 0x1b + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 31 + + + 1705 07ad CB040000 .4byte 0x4cb + 1706 07b1 67030000 .4byte .LLST25 + 1707 07b5 1C .uleb128 0x1c + 1708 07b6 48000000 .4byte .Ldebug_ranges0+0x48 + 1709 07ba 1D .uleb128 0x1d + 1710 07bb D6040000 .4byte 0x4d6 + 1711 07bf 93030000 .4byte .LLST26 + 1712 07c3 00 .byte 0 + 1713 07c4 00 .byte 0 + 1714 07c5 23 .uleb128 0x23 + 1715 07c6 22000000 .4byte .LVL31 + 1716 07ca 030A0000 .4byte 0xa03 + 1717 07ce 20 .uleb128 0x20 + 1718 07cf 01 .byte 0x1 + 1719 07d0 51 .byte 0x51 + 1720 07d1 01 .byte 0x1 + 1721 07d2 30 .byte 0x30 + 1722 07d3 00 .byte 0 + 1723 07d4 00 .byte 0 + 1724 07d5 2B .uleb128 0x2b + 1725 07d6 01 .byte 0x1 + 1726 07d7 13000000 .4byte .LASF76 + 1727 07db 01 .byte 0x1 + 1728 07dc 3101 .2byte 0x131 + 1729 07de 01 .byte 0x1 + 1730 07df 00000000 .4byte .LFB15 + 1731 07e3 20000000 .4byte .LFE15 + 1732 07e7 02 .byte 0x2 + 1733 07e8 7D .byte 0x7d + 1734 07e9 00 .sleb128 0 + 1735 07ea 01 .byte 0x1 + 1736 07eb 49080000 .4byte 0x849 + 1737 07ef 29 .uleb128 0x29 + 1738 07f0 737000 .ascii "sp\000" + 1739 07f3 01 .byte 0x1 + 1740 07f4 3101 .2byte 0x131 + 1741 07f6 12050000 .4byte 0x512 + 1742 07fa A6030000 .4byte .LLST27 + 1743 07fe 1C .uleb128 0x1c + 1744 07ff 60000000 .4byte .Ldebug_ranges0+0x60 + 1745 0803 2C .uleb128 0x2c + 1746 0804 747000 .ascii "tp\000" + 1747 0807 01 .byte 0x1 + 1748 0808 3D01 .2byte 0x13d + 1749 080a 2F020000 .4byte 0x22f + 1750 080e 01 .byte 0x1 + 1751 080f 52 .byte 0x52 + 1752 0810 2A .uleb128 0x2a + 1753 0811 BA040000 .4byte 0x4ba + 1754 0815 0E000000 .4byte .LBB33 + 1755 0819 78000000 .4byte .Ldebug_ranges0+0x78 + 1756 081d 01 .byte 0x1 + 1757 081e 3D01 .2byte 0x13d + 1758 0820 3D080000 .4byte 0x83d + 1759 0824 1B .uleb128 0x1b + 1760 0825 CB040000 .4byte 0x4cb + 1761 0829 DE030000 .4byte .LLST28 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 32 + + + 1762 082d 1C .uleb128 0x1c + 1763 082e 90000000 .4byte .Ldebug_ranges0+0x90 + 1764 0832 1D .uleb128 0x1d + 1765 0833 D6040000 .4byte 0x4d6 + 1766 0837 16040000 .4byte .LLST29 + 1767 083b 00 .byte 0 + 1768 083c 00 .byte 0 + 1769 083d 2D .uleb128 0x2d + 1770 083e 20000000 .4byte .LVL37 + 1771 0842 01 .byte 0x1 + 1772 0843 B0090000 .4byte 0x9b0 + 1773 0847 00 .byte 0 + 1774 0848 00 .byte 0 + 1775 0849 28 .uleb128 0x28 + 1776 084a 01 .byte 0x1 + 1777 084b 47000000 .4byte .LASF77 + 1778 084f 01 .byte 0x1 + 1779 0850 5001 .2byte 0x150 + 1780 0852 01 .byte 0x1 + 1781 0853 00000000 .4byte .LFB16 + 1782 0857 2E000000 .4byte .LFE16 + 1783 085b 29040000 .4byte .LLST30 + 1784 085f 01 .byte 0x1 + 1785 0860 BC080000 .4byte 0x8bc + 1786 0864 29 .uleb128 0x29 + 1787 0865 737000 .ascii "sp\000" + 1788 0868 01 .byte 0x1 + 1789 0869 5001 .2byte 0x150 + 1790 086b 12050000 .4byte 0x512 + 1791 086f 49040000 .4byte .LLST31 + 1792 0873 29 .uleb128 0x29 + 1793 0874 6E00 .ascii "n\000" + 1794 0876 01 .byte 0x1 + 1795 0877 5001 .2byte 0x150 + 1796 0879 DD000000 .4byte 0xdd + 1797 087d 67040000 .4byte .LLST32 + 1798 0881 26 .uleb128 0x26 + 1799 0882 BA040000 .4byte 0x4ba + 1800 0886 1A000000 .4byte .LBB38 + 1801 088a 22000000 .4byte .LBE38 + 1802 088e 01 .byte 0x1 + 1803 088f 5B01 .2byte 0x15b + 1804 0891 B2080000 .4byte 0x8b2 + 1805 0895 1B .uleb128 0x1b + 1806 0896 CB040000 .4byte 0x4cb + 1807 089a 92040000 .4byte .LLST33 + 1808 089e 2E .uleb128 0x2e + 1809 089f 1A000000 .4byte .LBB39 + 1810 08a3 22000000 .4byte .LBE39 + 1811 08a7 1D .uleb128 0x1d + 1812 08a8 D6040000 .4byte 0x4d6 + 1813 08ac A5040000 .4byte .LLST34 + 1814 08b0 00 .byte 0 + 1815 08b1 00 .byte 0 + 1816 08b2 1E .uleb128 0x1e + 1817 08b3 26000000 .4byte .LVL44 + 1818 08b7 B0090000 .4byte 0x9b0 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 33 + + + 1819 08bb 00 .byte 0 + 1820 08bc 2F .uleb128 0x2f + 1821 08bd 01 .byte 0x1 + 1822 08be 79000000 .4byte .LASF78 + 1823 08c2 01 .byte 0x1 + 1824 08c3 7001 .2byte 0x170 + 1825 08c5 01 .byte 0x1 + 1826 08c6 BC000000 .4byte 0xbc + 1827 08ca 00000000 .4byte .LFB17 + 1828 08ce 5C000000 .4byte .LFE17 + 1829 08d2 B8040000 .4byte .LLST35 + 1830 08d6 01 .byte 0x1 + 1831 08d7 A3090000 .4byte 0x9a3 + 1832 08db 29 .uleb128 0x29 + 1833 08dc 73707300 .ascii "sps\000" + 1834 08e0 01 .byte 0x1 + 1835 08e1 7001 .2byte 0x170 + 1836 08e3 12050000 .4byte 0x512 + 1837 08e7 E4040000 .4byte .LLST36 + 1838 08eb 29 .uleb128 0x29 + 1839 08ec 73707700 .ascii "spw\000" + 1840 08f0 01 .byte 0x1 + 1841 08f1 7001 .2byte 0x170 + 1842 08f3 12050000 .4byte 0x512 + 1843 08f7 29050000 .4byte .LLST37 + 1844 08fb 30 .uleb128 0x30 + 1845 08fc 6D736700 .ascii "msg\000" + 1846 0900 01 .byte 0x1 + 1847 0901 7101 .2byte 0x171 + 1848 0903 BC000000 .4byte 0xbc + 1849 0907 63050000 .4byte .LLST38 + 1850 090b 31 .uleb128 0x31 + 1851 090c 28000000 .4byte .LBB40 + 1852 0910 42000000 .4byte .LBE40 + 1853 0914 5F090000 .4byte 0x95f + 1854 0918 30 .uleb128 0x30 + 1855 0919 63747000 .ascii "ctp\000" + 1856 091d 01 .byte 0x1 + 1857 091e 8101 .2byte 0x181 + 1858 0920 2F020000 .4byte 0x22f + 1859 0924 8D050000 .4byte .LLST39 + 1860 0928 2A .uleb128 0x2a + 1861 0929 97040000 .4byte 0x497 + 1862 092d 2A000000 .4byte .LBB41 + 1863 0931 A8000000 .4byte .Ldebug_ranges0+0xa8 + 1864 0935 01 .byte 0x1 + 1865 0936 8201 .2byte 0x182 + 1866 0938 4F090000 .4byte 0x94f + 1867 093c 1B .uleb128 0x1b + 1868 093d AE040000 .4byte 0x4ae + 1869 0941 A0050000 .4byte .LLST40 + 1870 0945 1B .uleb128 0x1b + 1871 0946 A4040000 .4byte 0x4a4 + 1872 094a 8D050000 .4byte .LLST39 + 1873 094e 00 .byte 0 + 1874 094f 23 .uleb128 0x23 + 1875 0950 3E000000 .4byte .LVL52 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 34 + + + 1876 0954 D2090000 .4byte 0x9d2 + 1877 0958 20 .uleb128 0x20 + 1878 0959 01 .byte 0x1 + 1879 095a 50 .byte 0x50 + 1880 095b 01 .byte 0x1 + 1881 095c 33 .byte 0x33 + 1882 095d 00 .byte 0 + 1883 095e 00 .byte 0 + 1884 095f 26 .uleb128 0x26 + 1885 0960 BA040000 .4byte 0x4ba + 1886 0964 42000000 .4byte .LBB45 + 1887 0968 4A000000 .4byte .LBE45 + 1888 096c 01 .byte 0x1 + 1889 096d 7F01 .2byte 0x17f + 1890 096f 90090000 .4byte 0x990 + 1891 0973 1B .uleb128 0x1b + 1892 0974 CB040000 .4byte 0x4cb + 1893 0978 B3050000 .4byte .LLST42 + 1894 097c 2E .uleb128 0x2e + 1895 097d 42000000 .4byte .LBB46 + 1896 0981 4A000000 .4byte .LBE46 + 1897 0985 1D .uleb128 0x1d + 1898 0986 D6040000 .4byte 0x4d6 + 1899 098a DF050000 .4byte .LLST43 + 1900 098e 00 .byte 0 + 1901 098f 00 .byte 0 + 1902 0990 1E .uleb128 0x1e + 1903 0991 20000000 .4byte .LVL48 + 1904 0995 C8090000 .4byte 0x9c8 + 1905 0999 1E .uleb128 0x1e + 1906 099a 50000000 .4byte .LVL56 + 1907 099e B0090000 .4byte 0x9b0 + 1908 09a2 00 .byte 0 + 1909 09a3 32 .uleb128 0x32 + 1910 09a4 6E030000 .4byte .LASF85 + 1911 09a8 08 .byte 0x8 + 1912 09a9 72 .byte 0x72 + 1913 09aa 96030000 .4byte 0x396 + 1914 09ae 01 .byte 0x1 + 1915 09af 01 .byte 0x1 + 1916 09b0 33 .uleb128 0x33 + 1917 09b1 01 .byte 0x1 + 1918 09b2 BA020000 .4byte .LASF79 + 1919 09b6 08 .byte 0x8 + 1920 09b7 93 .byte 0x93 + 1921 09b8 01 .byte 0x1 + 1922 09b9 2F020000 .4byte 0x22f + 1923 09bd 01 .byte 0x1 + 1924 09be C8090000 .4byte 0x9c8 + 1925 09c2 34 .uleb128 0x34 + 1926 09c3 2F020000 .4byte 0x22f + 1927 09c7 00 .byte 0 + 1928 09c8 35 .uleb128 0x35 + 1929 09c9 01 .byte 0x1 + 1930 09ca C7000000 .4byte .LASF86 + 1931 09ce 08 .byte 0x8 + 1932 09cf 9F .byte 0x9f + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 35 + + + 1933 09d0 01 .byte 0x1 + 1934 09d1 01 .byte 0x1 + 1935 09d2 36 .uleb128 0x36 + 1936 09d3 01 .byte 0x1 + 1937 09d4 90020000 .4byte .LASF87 + 1938 09d8 08 .byte 0x8 + 1939 09d9 96 .byte 0x96 + 1940 09da 01 .byte 0x1 + 1941 09db 01 .byte 0x1 + 1942 09dc E6090000 .4byte 0x9e6 + 1943 09e0 34 .uleb128 0x34 + 1944 09e1 9B000000 .4byte 0x9b + 1945 09e5 00 .byte 0 + 1946 09e6 33 .uleb128 0x33 + 1947 09e7 01 .byte 0x1 + 1948 09e8 8A030000 .4byte .LASF80 + 1949 09ec 08 .byte 0x8 + 1950 09ed 99 .byte 0x99 + 1951 09ee 01 .byte 0x1 + 1952 09ef BC000000 .4byte 0xbc + 1953 09f3 01 .byte 0x1 + 1954 09f4 030A0000 .4byte 0xa03 + 1955 09f8 34 .uleb128 0x34 + 1956 09f9 9B000000 .4byte 0x9b + 1957 09fd 34 .uleb128 0x34 + 1958 09fe D2000000 .4byte 0xd2 + 1959 0a02 00 .byte 0 + 1960 0a03 37 .uleb128 0x37 + 1961 0a04 01 .byte 0x1 + 1962 0a05 3A030000 .4byte .LASF88 + 1963 0a09 08 .byte 0x8 + 1964 0a0a 9C .byte 0x9c + 1965 0a0b 01 .byte 0x1 + 1966 0a0c 01 .byte 0x1 + 1967 0a0d 34 .uleb128 0x34 + 1968 0a0e 2F020000 .4byte 0x22f + 1969 0a12 34 .uleb128 0x34 + 1970 0a13 BC000000 .4byte 0xbc + 1971 0a17 00 .byte 0 + 1972 0a18 00 .byte 0 + 1973 .section .debug_abbrev,"",%progbits + 1974 .Ldebug_abbrev0: + 1975 0000 01 .uleb128 0x1 + 1976 0001 11 .uleb128 0x11 + 1977 0002 01 .byte 0x1 + 1978 0003 25 .uleb128 0x25 + 1979 0004 0E .uleb128 0xe + 1980 0005 13 .uleb128 0x13 + 1981 0006 0B .uleb128 0xb + 1982 0007 03 .uleb128 0x3 + 1983 0008 0E .uleb128 0xe + 1984 0009 1B .uleb128 0x1b + 1985 000a 0E .uleb128 0xe + 1986 000b 55 .uleb128 0x55 + 1987 000c 06 .uleb128 0x6 + 1988 000d 11 .uleb128 0x11 + 1989 000e 01 .uleb128 0x1 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 36 + + + 1990 000f 52 .uleb128 0x52 + 1991 0010 01 .uleb128 0x1 + 1992 0011 10 .uleb128 0x10 + 1993 0012 06 .uleb128 0x6 + 1994 0013 00 .byte 0 + 1995 0014 00 .byte 0 + 1996 0015 02 .uleb128 0x2 + 1997 0016 24 .uleb128 0x24 + 1998 0017 00 .byte 0 + 1999 0018 0B .uleb128 0xb + 2000 0019 0B .uleb128 0xb + 2001 001a 3E .uleb128 0x3e + 2002 001b 0B .uleb128 0xb + 2003 001c 03 .uleb128 0x3 + 2004 001d 08 .uleb128 0x8 + 2005 001e 00 .byte 0 + 2006 001f 00 .byte 0 + 2007 0020 03 .uleb128 0x3 + 2008 0021 24 .uleb128 0x24 + 2009 0022 00 .byte 0 + 2010 0023 0B .uleb128 0xb + 2011 0024 0B .uleb128 0xb + 2012 0025 3E .uleb128 0x3e + 2013 0026 0B .uleb128 0xb + 2014 0027 03 .uleb128 0x3 + 2015 0028 0E .uleb128 0xe + 2016 0029 00 .byte 0 + 2017 002a 00 .byte 0 + 2018 002b 04 .uleb128 0x4 + 2019 002c 16 .uleb128 0x16 + 2020 002d 00 .byte 0 + 2021 002e 03 .uleb128 0x3 + 2022 002f 0E .uleb128 0xe + 2023 0030 3A .uleb128 0x3a + 2024 0031 0B .uleb128 0xb + 2025 0032 3B .uleb128 0x3b + 2026 0033 0B .uleb128 0xb + 2027 0034 49 .uleb128 0x49 + 2028 0035 13 .uleb128 0x13 + 2029 0036 00 .byte 0 + 2030 0037 00 .byte 0 + 2031 0038 05 .uleb128 0x5 + 2032 0039 13 .uleb128 0x13 + 2033 003a 01 .byte 0x1 + 2034 003b 03 .uleb128 0x3 + 2035 003c 0E .uleb128 0xe + 2036 003d 0B .uleb128 0xb + 2037 003e 0B .uleb128 0xb + 2038 003f 3A .uleb128 0x3a + 2039 0040 0B .uleb128 0xb + 2040 0041 3B .uleb128 0x3b + 2041 0042 0B .uleb128 0xb + 2042 0043 01 .uleb128 0x1 + 2043 0044 13 .uleb128 0x13 + 2044 0045 00 .byte 0 + 2045 0046 00 .byte 0 + 2046 0047 06 .uleb128 0x6 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 37 + + + 2047 0048 0D .uleb128 0xd + 2048 0049 00 .byte 0 + 2049 004a 03 .uleb128 0x3 + 2050 004b 0E .uleb128 0xe + 2051 004c 3A .uleb128 0x3a + 2052 004d 0B .uleb128 0xb + 2053 004e 3B .uleb128 0x3b + 2054 004f 0B .uleb128 0xb + 2055 0050 49 .uleb128 0x49 + 2056 0051 13 .uleb128 0x13 + 2057 0052 38 .uleb128 0x38 + 2058 0053 0A .uleb128 0xa + 2059 0054 00 .byte 0 + 2060 0055 00 .byte 0 + 2061 0056 07 .uleb128 0x7 + 2062 0057 0D .uleb128 0xd + 2063 0058 00 .byte 0 + 2064 0059 03 .uleb128 0x3 + 2065 005a 08 .uleb128 0x8 + 2066 005b 3A .uleb128 0x3a + 2067 005c 0B .uleb128 0xb + 2068 005d 3B .uleb128 0x3b + 2069 005e 0B .uleb128 0xb + 2070 005f 49 .uleb128 0x49 + 2071 0060 13 .uleb128 0x13 + 2072 0061 38 .uleb128 0x38 + 2073 0062 0A .uleb128 0xa + 2074 0063 00 .byte 0 + 2075 0064 00 .byte 0 + 2076 0065 08 .uleb128 0x8 + 2077 0066 13 .uleb128 0x13 + 2078 0067 01 .byte 0x1 + 2079 0068 0B .uleb128 0xb + 2080 0069 0B .uleb128 0xb + 2081 006a 3A .uleb128 0x3a + 2082 006b 0B .uleb128 0xb + 2083 006c 3B .uleb128 0x3b + 2084 006d 0B .uleb128 0xb + 2085 006e 01 .uleb128 0x1 + 2086 006f 13 .uleb128 0x13 + 2087 0070 00 .byte 0 + 2088 0071 00 .byte 0 + 2089 0072 09 .uleb128 0x9 + 2090 0073 0F .uleb128 0xf + 2091 0074 00 .byte 0 + 2092 0075 0B .uleb128 0xb + 2093 0076 0B .uleb128 0xb + 2094 0077 49 .uleb128 0x49 + 2095 0078 13 .uleb128 0x13 + 2096 0079 00 .byte 0 + 2097 007a 00 .byte 0 + 2098 007b 0A .uleb128 0xa + 2099 007c 0F .uleb128 0xf + 2100 007d 00 .byte 0 + 2101 007e 0B .uleb128 0xb + 2102 007f 0B .uleb128 0xb + 2103 0080 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 38 + + + 2104 0081 00 .byte 0 + 2105 0082 0B .uleb128 0xb + 2106 0083 0D .uleb128 0xd + 2107 0084 00 .byte 0 + 2108 0085 03 .uleb128 0x3 + 2109 0086 08 .uleb128 0x8 + 2110 0087 3A .uleb128 0x3a + 2111 0088 0B .uleb128 0xb + 2112 0089 3B .uleb128 0x3b + 2113 008a 05 .uleb128 0x5 + 2114 008b 49 .uleb128 0x49 + 2115 008c 13 .uleb128 0x13 + 2116 008d 38 .uleb128 0x38 + 2117 008e 0A .uleb128 0xa + 2118 008f 00 .byte 0 + 2119 0090 00 .byte 0 + 2120 0091 0C .uleb128 0xc + 2121 0092 13 .uleb128 0x13 + 2122 0093 01 .byte 0x1 + 2123 0094 03 .uleb128 0x3 + 2124 0095 0E .uleb128 0xe + 2125 0096 0B .uleb128 0xb + 2126 0097 0B .uleb128 0xb + 2127 0098 3A .uleb128 0x3a + 2128 0099 0B .uleb128 0xb + 2129 009a 3B .uleb128 0x3b + 2130 009b 05 .uleb128 0x5 + 2131 009c 01 .uleb128 0x1 + 2132 009d 13 .uleb128 0x13 + 2133 009e 00 .byte 0 + 2134 009f 00 .byte 0 + 2135 00a0 0D .uleb128 0xd + 2136 00a1 35 .uleb128 0x35 + 2137 00a2 00 .byte 0 + 2138 00a3 49 .uleb128 0x49 + 2139 00a4 13 .uleb128 0x13 + 2140 00a5 00 .byte 0 + 2141 00a6 00 .byte 0 + 2142 00a7 0E .uleb128 0xe + 2143 00a8 17 .uleb128 0x17 + 2144 00a9 01 .byte 0x1 + 2145 00aa 0B .uleb128 0xb + 2146 00ab 0B .uleb128 0xb + 2147 00ac 3A .uleb128 0x3a + 2148 00ad 0B .uleb128 0xb + 2149 00ae 3B .uleb128 0x3b + 2150 00af 0B .uleb128 0xb + 2151 00b0 01 .uleb128 0x1 + 2152 00b1 13 .uleb128 0x13 + 2153 00b2 00 .byte 0 + 2154 00b3 00 .byte 0 + 2155 00b4 0F .uleb128 0xf + 2156 00b5 0D .uleb128 0xd + 2157 00b6 00 .byte 0 + 2158 00b7 03 .uleb128 0x3 + 2159 00b8 0E .uleb128 0xe + 2160 00b9 3A .uleb128 0x3a + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 39 + + + 2161 00ba 0B .uleb128 0xb + 2162 00bb 3B .uleb128 0x3b + 2163 00bc 0B .uleb128 0xb + 2164 00bd 49 .uleb128 0x49 + 2165 00be 13 .uleb128 0x13 + 2166 00bf 00 .byte 0 + 2167 00c0 00 .byte 0 + 2168 00c1 10 .uleb128 0x10 + 2169 00c2 26 .uleb128 0x26 + 2170 00c3 00 .byte 0 + 2171 00c4 49 .uleb128 0x49 + 2172 00c5 13 .uleb128 0x13 + 2173 00c6 00 .byte 0 + 2174 00c7 00 .byte 0 + 2175 00c8 11 .uleb128 0x11 + 2176 00c9 2E .uleb128 0x2e + 2177 00ca 01 .byte 0x1 + 2178 00cb 03 .uleb128 0x3 + 2179 00cc 0E .uleb128 0xe + 2180 00cd 3A .uleb128 0x3a + 2181 00ce 0B .uleb128 0xb + 2182 00cf 3B .uleb128 0x3b + 2183 00d0 0B .uleb128 0xb + 2184 00d1 27 .uleb128 0x27 + 2185 00d2 0C .uleb128 0xc + 2186 00d3 49 .uleb128 0x49 + 2187 00d4 13 .uleb128 0x13 + 2188 00d5 20 .uleb128 0x20 + 2189 00d6 0B .uleb128 0xb + 2190 00d7 01 .uleb128 0x1 + 2191 00d8 13 .uleb128 0x13 + 2192 00d9 00 .byte 0 + 2193 00da 00 .byte 0 + 2194 00db 12 .uleb128 0x12 + 2195 00dc 05 .uleb128 0x5 + 2196 00dd 00 .byte 0 + 2197 00de 03 .uleb128 0x3 + 2198 00df 08 .uleb128 0x8 + 2199 00e0 3A .uleb128 0x3a + 2200 00e1 0B .uleb128 0xb + 2201 00e2 3B .uleb128 0x3b + 2202 00e3 0B .uleb128 0xb + 2203 00e4 49 .uleb128 0x49 + 2204 00e5 13 .uleb128 0x13 + 2205 00e6 00 .byte 0 + 2206 00e7 00 .byte 0 + 2207 00e8 13 .uleb128 0x13 + 2208 00e9 34 .uleb128 0x34 + 2209 00ea 00 .byte 0 + 2210 00eb 03 .uleb128 0x3 + 2211 00ec 08 .uleb128 0x8 + 2212 00ed 3A .uleb128 0x3a + 2213 00ee 0B .uleb128 0xb + 2214 00ef 3B .uleb128 0x3b + 2215 00f0 0B .uleb128 0xb + 2216 00f1 49 .uleb128 0x49 + 2217 00f2 13 .uleb128 0x13 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 40 + + + 2218 00f3 00 .byte 0 + 2219 00f4 00 .byte 0 + 2220 00f5 14 .uleb128 0x14 + 2221 00f6 2E .uleb128 0x2e + 2222 00f7 01 .byte 0x1 + 2223 00f8 03 .uleb128 0x3 + 2224 00f9 0E .uleb128 0xe + 2225 00fa 3A .uleb128 0x3a + 2226 00fb 0B .uleb128 0xb + 2227 00fc 3B .uleb128 0x3b + 2228 00fd 0B .uleb128 0xb + 2229 00fe 27 .uleb128 0x27 + 2230 00ff 0C .uleb128 0xc + 2231 0100 20 .uleb128 0x20 + 2232 0101 0B .uleb128 0xb + 2233 0102 01 .uleb128 0x1 + 2234 0103 13 .uleb128 0x13 + 2235 0104 00 .byte 0 + 2236 0105 00 .byte 0 + 2237 0106 15 .uleb128 0x15 + 2238 0107 2E .uleb128 0x2e + 2239 0108 01 .byte 0x1 + 2240 0109 3F .uleb128 0x3f + 2241 010a 0C .uleb128 0xc + 2242 010b 03 .uleb128 0x3 + 2243 010c 0E .uleb128 0xe + 2244 010d 3A .uleb128 0x3a + 2245 010e 0B .uleb128 0xb + 2246 010f 3B .uleb128 0x3b + 2247 0110 0B .uleb128 0xb + 2248 0111 27 .uleb128 0x27 + 2249 0112 0C .uleb128 0xc + 2250 0113 11 .uleb128 0x11 + 2251 0114 01 .uleb128 0x1 + 2252 0115 12 .uleb128 0x12 + 2253 0116 01 .uleb128 0x1 + 2254 0117 40 .uleb128 0x40 + 2255 0118 0A .uleb128 0xa + 2256 0119 9742 .uleb128 0x2117 + 2257 011b 0C .uleb128 0xc + 2258 011c 01 .uleb128 0x1 + 2259 011d 13 .uleb128 0x13 + 2260 011e 00 .byte 0 + 2261 011f 00 .byte 0 + 2262 0120 16 .uleb128 0x16 + 2263 0121 05 .uleb128 0x5 + 2264 0122 00 .byte 0 + 2265 0123 03 .uleb128 0x3 + 2266 0124 08 .uleb128 0x8 + 2267 0125 3A .uleb128 0x3a + 2268 0126 0B .uleb128 0xb + 2269 0127 3B .uleb128 0x3b + 2270 0128 0B .uleb128 0xb + 2271 0129 49 .uleb128 0x49 + 2272 012a 13 .uleb128 0x13 + 2273 012b 02 .uleb128 0x2 + 2274 012c 0A .uleb128 0xa + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 41 + + + 2275 012d 00 .byte 0 + 2276 012e 00 .byte 0 + 2277 012f 17 .uleb128 0x17 + 2278 0130 2E .uleb128 0x2e + 2279 0131 01 .byte 0x1 + 2280 0132 3F .uleb128 0x3f + 2281 0133 0C .uleb128 0xc + 2282 0134 03 .uleb128 0x3 + 2283 0135 0E .uleb128 0xe + 2284 0136 3A .uleb128 0x3a + 2285 0137 0B .uleb128 0xb + 2286 0138 3B .uleb128 0x3b + 2287 0139 0B .uleb128 0xb + 2288 013a 27 .uleb128 0x27 + 2289 013b 0C .uleb128 0xc + 2290 013c 11 .uleb128 0x11 + 2291 013d 01 .uleb128 0x1 + 2292 013e 12 .uleb128 0x12 + 2293 013f 01 .uleb128 0x1 + 2294 0140 40 .uleb128 0x40 + 2295 0141 06 .uleb128 0x6 + 2296 0142 9742 .uleb128 0x2117 + 2297 0144 0C .uleb128 0xc + 2298 0145 01 .uleb128 0x1 + 2299 0146 13 .uleb128 0x13 + 2300 0147 00 .byte 0 + 2301 0148 00 .byte 0 + 2302 0149 18 .uleb128 0x18 + 2303 014a 05 .uleb128 0x5 + 2304 014b 00 .byte 0 + 2305 014c 03 .uleb128 0x3 + 2306 014d 08 .uleb128 0x8 + 2307 014e 3A .uleb128 0x3a + 2308 014f 0B .uleb128 0xb + 2309 0150 3B .uleb128 0x3b + 2310 0151 0B .uleb128 0xb + 2311 0152 49 .uleb128 0x49 + 2312 0153 13 .uleb128 0x13 + 2313 0154 02 .uleb128 0x2 + 2314 0155 06 .uleb128 0x6 + 2315 0156 00 .byte 0 + 2316 0157 00 .byte 0 + 2317 0158 19 .uleb128 0x19 + 2318 0159 34 .uleb128 0x34 + 2319 015a 00 .byte 0 + 2320 015b 03 .uleb128 0x3 + 2321 015c 08 .uleb128 0x8 + 2322 015d 3A .uleb128 0x3a + 2323 015e 0B .uleb128 0xb + 2324 015f 3B .uleb128 0x3b + 2325 0160 0B .uleb128 0xb + 2326 0161 49 .uleb128 0x49 + 2327 0162 13 .uleb128 0x13 + 2328 0163 02 .uleb128 0x2 + 2329 0164 06 .uleb128 0x6 + 2330 0165 00 .byte 0 + 2331 0166 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 42 + + + 2332 0167 1A .uleb128 0x1a + 2333 0168 1D .uleb128 0x1d + 2334 0169 01 .byte 0x1 + 2335 016a 31 .uleb128 0x31 + 2336 016b 13 .uleb128 0x13 + 2337 016c 52 .uleb128 0x52 + 2338 016d 01 .uleb128 0x1 + 2339 016e 55 .uleb128 0x55 + 2340 016f 06 .uleb128 0x6 + 2341 0170 58 .uleb128 0x58 + 2342 0171 0B .uleb128 0xb + 2343 0172 59 .uleb128 0x59 + 2344 0173 0B .uleb128 0xb + 2345 0174 01 .uleb128 0x1 + 2346 0175 13 .uleb128 0x13 + 2347 0176 00 .byte 0 + 2348 0177 00 .byte 0 + 2349 0178 1B .uleb128 0x1b + 2350 0179 05 .uleb128 0x5 + 2351 017a 00 .byte 0 + 2352 017b 31 .uleb128 0x31 + 2353 017c 13 .uleb128 0x13 + 2354 017d 02 .uleb128 0x2 + 2355 017e 06 .uleb128 0x6 + 2356 017f 00 .byte 0 + 2357 0180 00 .byte 0 + 2358 0181 1C .uleb128 0x1c + 2359 0182 0B .uleb128 0xb + 2360 0183 01 .byte 0x1 + 2361 0184 55 .uleb128 0x55 + 2362 0185 06 .uleb128 0x6 + 2363 0186 00 .byte 0 + 2364 0187 00 .byte 0 + 2365 0188 1D .uleb128 0x1d + 2366 0189 34 .uleb128 0x34 + 2367 018a 00 .byte 0 + 2368 018b 31 .uleb128 0x31 + 2369 018c 13 .uleb128 0x13 + 2370 018d 02 .uleb128 0x2 + 2371 018e 06 .uleb128 0x6 + 2372 018f 00 .byte 0 + 2373 0190 00 .byte 0 + 2374 0191 1E .uleb128 0x1e + 2375 0192 898201 .uleb128 0x4109 + 2376 0195 00 .byte 0 + 2377 0196 11 .uleb128 0x11 + 2378 0197 01 .uleb128 0x1 + 2379 0198 31 .uleb128 0x31 + 2380 0199 13 .uleb128 0x13 + 2381 019a 00 .byte 0 + 2382 019b 00 .byte 0 + 2383 019c 1F .uleb128 0x1f + 2384 019d 898201 .uleb128 0x4109 + 2385 01a0 01 .byte 0x1 + 2386 01a1 11 .uleb128 0x11 + 2387 01a2 01 .uleb128 0x1 + 2388 01a3 31 .uleb128 0x31 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 43 + + + 2389 01a4 13 .uleb128 0x13 + 2390 01a5 01 .uleb128 0x1 + 2391 01a6 13 .uleb128 0x13 + 2392 01a7 00 .byte 0 + 2393 01a8 00 .byte 0 + 2394 01a9 20 .uleb128 0x20 + 2395 01aa 8A8201 .uleb128 0x410a + 2396 01ad 00 .byte 0 + 2397 01ae 02 .uleb128 0x2 + 2398 01af 0A .uleb128 0xa + 2399 01b0 9142 .uleb128 0x2111 + 2400 01b2 0A .uleb128 0xa + 2401 01b3 00 .byte 0 + 2402 01b4 00 .byte 0 + 2403 01b5 21 .uleb128 0x21 + 2404 01b6 2E .uleb128 0x2e + 2405 01b7 01 .byte 0x1 + 2406 01b8 3F .uleb128 0x3f + 2407 01b9 0C .uleb128 0xc + 2408 01ba 03 .uleb128 0x3 + 2409 01bb 0E .uleb128 0xe + 2410 01bc 3A .uleb128 0x3a + 2411 01bd 0B .uleb128 0xb + 2412 01be 3B .uleb128 0x3b + 2413 01bf 0B .uleb128 0xb + 2414 01c0 27 .uleb128 0x27 + 2415 01c1 0C .uleb128 0xc + 2416 01c2 49 .uleb128 0x49 + 2417 01c3 13 .uleb128 0x13 + 2418 01c4 11 .uleb128 0x11 + 2419 01c5 01 .uleb128 0x1 + 2420 01c6 12 .uleb128 0x12 + 2421 01c7 01 .uleb128 0x1 + 2422 01c8 40 .uleb128 0x40 + 2423 01c9 06 .uleb128 0x6 + 2424 01ca 9742 .uleb128 0x2117 + 2425 01cc 0C .uleb128 0xc + 2426 01cd 01 .uleb128 0x1 + 2427 01ce 13 .uleb128 0x13 + 2428 01cf 00 .byte 0 + 2429 01d0 00 .byte 0 + 2430 01d1 22 .uleb128 0x22 + 2431 01d2 1D .uleb128 0x1d + 2432 01d3 01 .byte 0x1 + 2433 01d4 31 .uleb128 0x31 + 2434 01d5 13 .uleb128 0x13 + 2435 01d6 11 .uleb128 0x11 + 2436 01d7 01 .uleb128 0x1 + 2437 01d8 12 .uleb128 0x12 + 2438 01d9 01 .uleb128 0x1 + 2439 01da 58 .uleb128 0x58 + 2440 01db 0B .uleb128 0xb + 2441 01dc 59 .uleb128 0x59 + 2442 01dd 0B .uleb128 0xb + 2443 01de 01 .uleb128 0x1 + 2444 01df 13 .uleb128 0x13 + 2445 01e0 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 44 + + + 2446 01e1 00 .byte 0 + 2447 01e2 23 .uleb128 0x23 + 2448 01e3 898201 .uleb128 0x4109 + 2449 01e6 01 .byte 0x1 + 2450 01e7 11 .uleb128 0x11 + 2451 01e8 01 .uleb128 0x1 + 2452 01e9 31 .uleb128 0x31 + 2453 01ea 13 .uleb128 0x13 + 2454 01eb 00 .byte 0 + 2455 01ec 00 .byte 0 + 2456 01ed 24 .uleb128 0x24 + 2457 01ee 34 .uleb128 0x34 + 2458 01ef 00 .byte 0 + 2459 01f0 03 .uleb128 0x3 + 2460 01f1 08 .uleb128 0x8 + 2461 01f2 3A .uleb128 0x3a + 2462 01f3 0B .uleb128 0xb + 2463 01f4 3B .uleb128 0x3b + 2464 01f5 0B .uleb128 0xb + 2465 01f6 49 .uleb128 0x49 + 2466 01f7 13 .uleb128 0x13 + 2467 01f8 02 .uleb128 0x2 + 2468 01f9 0A .uleb128 0xa + 2469 01fa 00 .byte 0 + 2470 01fb 00 .byte 0 + 2471 01fc 25 .uleb128 0x25 + 2472 01fd 05 .uleb128 0x5 + 2473 01fe 00 .byte 0 + 2474 01ff 03 .uleb128 0x3 + 2475 0200 0E .uleb128 0xe + 2476 0201 3A .uleb128 0x3a + 2477 0202 0B .uleb128 0xb + 2478 0203 3B .uleb128 0x3b + 2479 0204 0B .uleb128 0xb + 2480 0205 49 .uleb128 0x49 + 2481 0206 13 .uleb128 0x13 + 2482 0207 02 .uleb128 0x2 + 2483 0208 06 .uleb128 0x6 + 2484 0209 00 .byte 0 + 2485 020a 00 .byte 0 + 2486 020b 26 .uleb128 0x26 + 2487 020c 1D .uleb128 0x1d + 2488 020d 01 .byte 0x1 + 2489 020e 31 .uleb128 0x31 + 2490 020f 13 .uleb128 0x13 + 2491 0210 11 .uleb128 0x11 + 2492 0211 01 .uleb128 0x1 + 2493 0212 12 .uleb128 0x12 + 2494 0213 01 .uleb128 0x1 + 2495 0214 58 .uleb128 0x58 + 2496 0215 0B .uleb128 0xb + 2497 0216 59 .uleb128 0x59 + 2498 0217 05 .uleb128 0x5 + 2499 0218 01 .uleb128 0x1 + 2500 0219 13 .uleb128 0x13 + 2501 021a 00 .byte 0 + 2502 021b 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 45 + + + 2503 021c 27 .uleb128 0x27 + 2504 021d 898201 .uleb128 0x4109 + 2505 0220 01 .byte 0x1 + 2506 0221 11 .uleb128 0x11 + 2507 0222 01 .uleb128 0x1 + 2508 0223 9542 .uleb128 0x2115 + 2509 0225 0C .uleb128 0xc + 2510 0226 31 .uleb128 0x31 + 2511 0227 13 .uleb128 0x13 + 2512 0228 00 .byte 0 + 2513 0229 00 .byte 0 + 2514 022a 28 .uleb128 0x28 + 2515 022b 2E .uleb128 0x2e + 2516 022c 01 .byte 0x1 + 2517 022d 3F .uleb128 0x3f + 2518 022e 0C .uleb128 0xc + 2519 022f 03 .uleb128 0x3 + 2520 0230 0E .uleb128 0xe + 2521 0231 3A .uleb128 0x3a + 2522 0232 0B .uleb128 0xb + 2523 0233 3B .uleb128 0x3b + 2524 0234 05 .uleb128 0x5 + 2525 0235 27 .uleb128 0x27 + 2526 0236 0C .uleb128 0xc + 2527 0237 11 .uleb128 0x11 + 2528 0238 01 .uleb128 0x1 + 2529 0239 12 .uleb128 0x12 + 2530 023a 01 .uleb128 0x1 + 2531 023b 40 .uleb128 0x40 + 2532 023c 06 .uleb128 0x6 + 2533 023d 9742 .uleb128 0x2117 + 2534 023f 0C .uleb128 0xc + 2535 0240 01 .uleb128 0x1 + 2536 0241 13 .uleb128 0x13 + 2537 0242 00 .byte 0 + 2538 0243 00 .byte 0 + 2539 0244 29 .uleb128 0x29 + 2540 0245 05 .uleb128 0x5 + 2541 0246 00 .byte 0 + 2542 0247 03 .uleb128 0x3 + 2543 0248 08 .uleb128 0x8 + 2544 0249 3A .uleb128 0x3a + 2545 024a 0B .uleb128 0xb + 2546 024b 3B .uleb128 0x3b + 2547 024c 05 .uleb128 0x5 + 2548 024d 49 .uleb128 0x49 + 2549 024e 13 .uleb128 0x13 + 2550 024f 02 .uleb128 0x2 + 2551 0250 06 .uleb128 0x6 + 2552 0251 00 .byte 0 + 2553 0252 00 .byte 0 + 2554 0253 2A .uleb128 0x2a + 2555 0254 1D .uleb128 0x1d + 2556 0255 01 .byte 0x1 + 2557 0256 31 .uleb128 0x31 + 2558 0257 13 .uleb128 0x13 + 2559 0258 52 .uleb128 0x52 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 46 + + + 2560 0259 01 .uleb128 0x1 + 2561 025a 55 .uleb128 0x55 + 2562 025b 06 .uleb128 0x6 + 2563 025c 58 .uleb128 0x58 + 2564 025d 0B .uleb128 0xb + 2565 025e 59 .uleb128 0x59 + 2566 025f 05 .uleb128 0x5 + 2567 0260 01 .uleb128 0x1 + 2568 0261 13 .uleb128 0x13 + 2569 0262 00 .byte 0 + 2570 0263 00 .byte 0 + 2571 0264 2B .uleb128 0x2b + 2572 0265 2E .uleb128 0x2e + 2573 0266 01 .byte 0x1 + 2574 0267 3F .uleb128 0x3f + 2575 0268 0C .uleb128 0xc + 2576 0269 03 .uleb128 0x3 + 2577 026a 0E .uleb128 0xe + 2578 026b 3A .uleb128 0x3a + 2579 026c 0B .uleb128 0xb + 2580 026d 3B .uleb128 0x3b + 2581 026e 05 .uleb128 0x5 + 2582 026f 27 .uleb128 0x27 + 2583 0270 0C .uleb128 0xc + 2584 0271 11 .uleb128 0x11 + 2585 0272 01 .uleb128 0x1 + 2586 0273 12 .uleb128 0x12 + 2587 0274 01 .uleb128 0x1 + 2588 0275 40 .uleb128 0x40 + 2589 0276 0A .uleb128 0xa + 2590 0277 9742 .uleb128 0x2117 + 2591 0279 0C .uleb128 0xc + 2592 027a 01 .uleb128 0x1 + 2593 027b 13 .uleb128 0x13 + 2594 027c 00 .byte 0 + 2595 027d 00 .byte 0 + 2596 027e 2C .uleb128 0x2c + 2597 027f 34 .uleb128 0x34 + 2598 0280 00 .byte 0 + 2599 0281 03 .uleb128 0x3 + 2600 0282 08 .uleb128 0x8 + 2601 0283 3A .uleb128 0x3a + 2602 0284 0B .uleb128 0xb + 2603 0285 3B .uleb128 0x3b + 2604 0286 05 .uleb128 0x5 + 2605 0287 49 .uleb128 0x49 + 2606 0288 13 .uleb128 0x13 + 2607 0289 02 .uleb128 0x2 + 2608 028a 0A .uleb128 0xa + 2609 028b 00 .byte 0 + 2610 028c 00 .byte 0 + 2611 028d 2D .uleb128 0x2d + 2612 028e 898201 .uleb128 0x4109 + 2613 0291 00 .byte 0 + 2614 0292 11 .uleb128 0x11 + 2615 0293 01 .uleb128 0x1 + 2616 0294 9542 .uleb128 0x2115 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 47 + + + 2617 0296 0C .uleb128 0xc + 2618 0297 31 .uleb128 0x31 + 2619 0298 13 .uleb128 0x13 + 2620 0299 00 .byte 0 + 2621 029a 00 .byte 0 + 2622 029b 2E .uleb128 0x2e + 2623 029c 0B .uleb128 0xb + 2624 029d 01 .byte 0x1 + 2625 029e 11 .uleb128 0x11 + 2626 029f 01 .uleb128 0x1 + 2627 02a0 12 .uleb128 0x12 + 2628 02a1 01 .uleb128 0x1 + 2629 02a2 00 .byte 0 + 2630 02a3 00 .byte 0 + 2631 02a4 2F .uleb128 0x2f + 2632 02a5 2E .uleb128 0x2e + 2633 02a6 01 .byte 0x1 + 2634 02a7 3F .uleb128 0x3f + 2635 02a8 0C .uleb128 0xc + 2636 02a9 03 .uleb128 0x3 + 2637 02aa 0E .uleb128 0xe + 2638 02ab 3A .uleb128 0x3a + 2639 02ac 0B .uleb128 0xb + 2640 02ad 3B .uleb128 0x3b + 2641 02ae 05 .uleb128 0x5 + 2642 02af 27 .uleb128 0x27 + 2643 02b0 0C .uleb128 0xc + 2644 02b1 49 .uleb128 0x49 + 2645 02b2 13 .uleb128 0x13 + 2646 02b3 11 .uleb128 0x11 + 2647 02b4 01 .uleb128 0x1 + 2648 02b5 12 .uleb128 0x12 + 2649 02b6 01 .uleb128 0x1 + 2650 02b7 40 .uleb128 0x40 + 2651 02b8 06 .uleb128 0x6 + 2652 02b9 9742 .uleb128 0x2117 + 2653 02bb 0C .uleb128 0xc + 2654 02bc 01 .uleb128 0x1 + 2655 02bd 13 .uleb128 0x13 + 2656 02be 00 .byte 0 + 2657 02bf 00 .byte 0 + 2658 02c0 30 .uleb128 0x30 + 2659 02c1 34 .uleb128 0x34 + 2660 02c2 00 .byte 0 + 2661 02c3 03 .uleb128 0x3 + 2662 02c4 08 .uleb128 0x8 + 2663 02c5 3A .uleb128 0x3a + 2664 02c6 0B .uleb128 0xb + 2665 02c7 3B .uleb128 0x3b + 2666 02c8 05 .uleb128 0x5 + 2667 02c9 49 .uleb128 0x49 + 2668 02ca 13 .uleb128 0x13 + 2669 02cb 02 .uleb128 0x2 + 2670 02cc 06 .uleb128 0x6 + 2671 02cd 00 .byte 0 + 2672 02ce 00 .byte 0 + 2673 02cf 31 .uleb128 0x31 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 48 + + + 2674 02d0 0B .uleb128 0xb + 2675 02d1 01 .byte 0x1 + 2676 02d2 11 .uleb128 0x11 + 2677 02d3 01 .uleb128 0x1 + 2678 02d4 12 .uleb128 0x12 + 2679 02d5 01 .uleb128 0x1 + 2680 02d6 01 .uleb128 0x1 + 2681 02d7 13 .uleb128 0x13 + 2682 02d8 00 .byte 0 + 2683 02d9 00 .byte 0 + 2684 02da 32 .uleb128 0x32 + 2685 02db 34 .uleb128 0x34 + 2686 02dc 00 .byte 0 + 2687 02dd 03 .uleb128 0x3 + 2688 02de 0E .uleb128 0xe + 2689 02df 3A .uleb128 0x3a + 2690 02e0 0B .uleb128 0xb + 2691 02e1 3B .uleb128 0x3b + 2692 02e2 0B .uleb128 0xb + 2693 02e3 49 .uleb128 0x49 + 2694 02e4 13 .uleb128 0x13 + 2695 02e5 3F .uleb128 0x3f + 2696 02e6 0C .uleb128 0xc + 2697 02e7 3C .uleb128 0x3c + 2698 02e8 0C .uleb128 0xc + 2699 02e9 00 .byte 0 + 2700 02ea 00 .byte 0 + 2701 02eb 33 .uleb128 0x33 + 2702 02ec 2E .uleb128 0x2e + 2703 02ed 01 .byte 0x1 + 2704 02ee 3F .uleb128 0x3f + 2705 02ef 0C .uleb128 0xc + 2706 02f0 03 .uleb128 0x3 + 2707 02f1 0E .uleb128 0xe + 2708 02f2 3A .uleb128 0x3a + 2709 02f3 0B .uleb128 0xb + 2710 02f4 3B .uleb128 0x3b + 2711 02f5 0B .uleb128 0xb + 2712 02f6 27 .uleb128 0x27 + 2713 02f7 0C .uleb128 0xc + 2714 02f8 49 .uleb128 0x49 + 2715 02f9 13 .uleb128 0x13 + 2716 02fa 3C .uleb128 0x3c + 2717 02fb 0C .uleb128 0xc + 2718 02fc 01 .uleb128 0x1 + 2719 02fd 13 .uleb128 0x13 + 2720 02fe 00 .byte 0 + 2721 02ff 00 .byte 0 + 2722 0300 34 .uleb128 0x34 + 2723 0301 05 .uleb128 0x5 + 2724 0302 00 .byte 0 + 2725 0303 49 .uleb128 0x49 + 2726 0304 13 .uleb128 0x13 + 2727 0305 00 .byte 0 + 2728 0306 00 .byte 0 + 2729 0307 35 .uleb128 0x35 + 2730 0308 2E .uleb128 0x2e + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 49 + + + 2731 0309 00 .byte 0 + 2732 030a 3F .uleb128 0x3f + 2733 030b 0C .uleb128 0xc + 2734 030c 03 .uleb128 0x3 + 2735 030d 0E .uleb128 0xe + 2736 030e 3A .uleb128 0x3a + 2737 030f 0B .uleb128 0xb + 2738 0310 3B .uleb128 0x3b + 2739 0311 0B .uleb128 0xb + 2740 0312 27 .uleb128 0x27 + 2741 0313 0C .uleb128 0xc + 2742 0314 3C .uleb128 0x3c + 2743 0315 0C .uleb128 0xc + 2744 0316 00 .byte 0 + 2745 0317 00 .byte 0 + 2746 0318 36 .uleb128 0x36 + 2747 0319 2E .uleb128 0x2e + 2748 031a 01 .byte 0x1 + 2749 031b 3F .uleb128 0x3f + 2750 031c 0C .uleb128 0xc + 2751 031d 03 .uleb128 0x3 + 2752 031e 0E .uleb128 0xe + 2753 031f 3A .uleb128 0x3a + 2754 0320 0B .uleb128 0xb + 2755 0321 3B .uleb128 0x3b + 2756 0322 0B .uleb128 0xb + 2757 0323 27 .uleb128 0x27 + 2758 0324 0C .uleb128 0xc + 2759 0325 3C .uleb128 0x3c + 2760 0326 0C .uleb128 0xc + 2761 0327 01 .uleb128 0x1 + 2762 0328 13 .uleb128 0x13 + 2763 0329 00 .byte 0 + 2764 032a 00 .byte 0 + 2765 032b 37 .uleb128 0x37 + 2766 032c 2E .uleb128 0x2e + 2767 032d 01 .byte 0x1 + 2768 032e 3F .uleb128 0x3f + 2769 032f 0C .uleb128 0xc + 2770 0330 03 .uleb128 0x3 + 2771 0331 0E .uleb128 0xe + 2772 0332 3A .uleb128 0x3a + 2773 0333 0B .uleb128 0xb + 2774 0334 3B .uleb128 0x3b + 2775 0335 0B .uleb128 0xb + 2776 0336 27 .uleb128 0x27 + 2777 0337 0C .uleb128 0xc + 2778 0338 3C .uleb128 0x3c + 2779 0339 0C .uleb128 0xc + 2780 033a 00 .byte 0 + 2781 033b 00 .byte 0 + 2782 033c 00 .byte 0 + 2783 .section .debug_loc,"",%progbits + 2784 .Ldebug_loc0: + 2785 .LLST0: + 2786 0000 00000000 .4byte .LFB9 + 2787 0004 02000000 .4byte .LCFI0 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 50 + + + 2788 0008 0200 .2byte 0x2 + 2789 000a 7D .byte 0x7d + 2790 000b 00 .sleb128 0 + 2791 000c 02000000 .4byte .LCFI0 + 2792 0010 28000000 .4byte .LFE9 + 2793 0014 0200 .2byte 0x2 + 2794 0016 7D .byte 0x7d + 2795 0017 10 .sleb128 16 + 2796 0018 00000000 .4byte 0 + 2797 001c 00000000 .4byte 0 + 2798 .LLST1: + 2799 0020 00000000 .4byte .LVL1 + 2800 0024 12000000 .4byte .LVL5 + 2801 0028 0100 .2byte 0x1 + 2802 002a 50 .byte 0x50 + 2803 002b 12000000 .4byte .LVL5 + 2804 002f 28000000 .4byte .LFE9 + 2805 0033 0100 .2byte 0x1 + 2806 0035 54 .byte 0x54 + 2807 0036 00000000 .4byte 0 + 2808 003a 00000000 .4byte 0 + 2809 .LLST2: + 2810 003e 00000000 .4byte .LVL1 + 2811 0042 12000000 .4byte .LVL5 + 2812 0046 0100 .2byte 0x1 + 2813 0048 51 .byte 0x51 + 2814 0049 12000000 .4byte .LVL5 + 2815 004d 28000000 .4byte .LFE9 + 2816 0051 0400 .2byte 0x4 + 2817 0053 F3 .byte 0xf3 + 2818 0054 01 .uleb128 0x1 + 2819 0055 51 .byte 0x51 + 2820 0056 9F .byte 0x9f + 2821 0057 00000000 .4byte 0 + 2822 005b 00000000 .4byte 0 + 2823 .LLST3: + 2824 005f 04000000 .4byte .LVL2 + 2825 0063 08000000 .4byte .LVL3 + 2826 0067 0100 .2byte 0x1 + 2827 0069 55 .byte 0x55 + 2828 006a 08000000 .4byte .LVL3 + 2829 006e 0C000000 .4byte .LVL4 + 2830 0072 0200 .2byte 0x2 + 2831 0074 70 .byte 0x70 + 2832 0075 08 .sleb128 8 + 2833 0076 0C000000 .4byte .LVL4 + 2834 007a 16000000 .4byte .LVL7 + 2835 007e 0100 .2byte 0x1 + 2836 0080 55 .byte 0x55 + 2837 0081 16000000 .4byte .LVL7 + 2838 0085 24000000 .4byte .LVL9 + 2839 0089 0300 .2byte 0x3 + 2840 008b 75 .byte 0x75 + 2841 008c 7F .sleb128 -1 + 2842 008d 9F .byte 0x9f + 2843 008e 24000000 .4byte .LVL9 + 2844 0092 28000000 .4byte .LFE9 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 51 + + + 2845 0096 0100 .2byte 0x1 + 2846 0098 55 .byte 0x55 + 2847 0099 00000000 .4byte 0 + 2848 009d 00000000 .4byte 0 + 2849 .LLST4: + 2850 00a1 12000000 .4byte .LVL5 + 2851 00a5 26000000 .4byte .LVL10 + 2852 00a9 0100 .2byte 0x1 + 2853 00ab 54 .byte 0x54 + 2854 00ac 00000000 .4byte 0 + 2855 00b0 00000000 .4byte 0 + 2856 .LLST5: + 2857 00b4 14000000 .4byte .LVL6 + 2858 00b8 1F000000 .4byte .LVL8-1 + 2859 00bc 0100 .2byte 0x1 + 2860 00be 50 .byte 0x50 + 2861 00bf 00000000 .4byte 0 + 2862 00c3 00000000 .4byte 0 + 2863 .LLST6: + 2864 00c7 00000000 .4byte .LFB8 + 2865 00cb 02000000 .4byte .LCFI1 + 2866 00cf 0200 .2byte 0x2 + 2867 00d1 7D .byte 0x7d + 2868 00d2 00 .sleb128 0 + 2869 00d3 02000000 .4byte .LCFI1 + 2870 00d7 10000000 .4byte .LFE8 + 2871 00db 0200 .2byte 0x2 + 2872 00dd 7D .byte 0x7d + 2873 00de 08 .sleb128 8 + 2874 00df 00000000 .4byte 0 + 2875 00e3 00000000 .4byte 0 + 2876 .LLST7: + 2877 00e7 00000000 .4byte .LVL11 + 2878 00eb 07000000 .4byte .LVL12-1 + 2879 00ef 0100 .2byte 0x1 + 2880 00f1 50 .byte 0x50 + 2881 00f2 07000000 .4byte .LVL12-1 + 2882 00f6 10000000 .4byte .LFE8 + 2883 00fa 0400 .2byte 0x4 + 2884 00fc F3 .byte 0xf3 + 2885 00fd 01 .uleb128 0x1 + 2886 00fe 50 .byte 0x50 + 2887 00ff 9F .byte 0x9f + 2888 0100 00000000 .4byte 0 + 2889 0104 00000000 .4byte 0 + 2890 .LLST8: + 2891 0108 00000000 .4byte .LVL11 + 2892 010c 07000000 .4byte .LVL12-1 + 2893 0110 0100 .2byte 0x1 + 2894 0112 51 .byte 0x51 + 2895 0113 07000000 .4byte .LVL12-1 + 2896 0117 10000000 .4byte .LFE8 + 2897 011b 0400 .2byte 0x4 + 2898 011d F3 .byte 0xf3 + 2899 011e 01 .uleb128 0x1 + 2900 011f 51 .byte 0x51 + 2901 0120 9F .byte 0x9f + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 52 + + + 2902 0121 00000000 .4byte 0 + 2903 0125 00000000 .4byte 0 + 2904 .LLST9: + 2905 0129 00000000 .4byte .LFB11 + 2906 012d 04000000 .4byte .LCFI2 + 2907 0131 0200 .2byte 0x2 + 2908 0133 7D .byte 0x7d + 2909 0134 00 .sleb128 0 + 2910 0135 04000000 .4byte .LCFI2 + 2911 0139 34000000 .4byte .LFE11 + 2912 013d 0200 .2byte 0x2 + 2913 013f 7D .byte 0x7d + 2914 0140 08 .sleb128 8 + 2915 0141 00000000 .4byte 0 + 2916 0145 00000000 .4byte 0 + 2917 .LLST10: + 2918 0149 00000000 .4byte .LVL14 + 2919 014d 10000000 .4byte .LVL15 + 2920 0151 0100 .2byte 0x1 + 2921 0153 50 .byte 0x50 + 2922 0154 10000000 .4byte .LVL15 + 2923 0158 12000000 .4byte .LVL16 + 2924 015c 0100 .2byte 0x1 + 2925 015e 53 .byte 0x53 + 2926 015f 12000000 .4byte .LVL16 + 2927 0163 16000000 .4byte .LVL17 + 2928 0167 0100 .2byte 0x1 + 2929 0169 50 .byte 0x50 + 2930 016a 16000000 .4byte .LVL17 + 2931 016e 27000000 .4byte .LVL19-1 + 2932 0172 0100 .2byte 0x1 + 2933 0174 53 .byte 0x53 + 2934 0175 27000000 .4byte .LVL19-1 + 2935 0179 34000000 .4byte .LFE11 + 2936 017d 0400 .2byte 0x4 + 2937 017f F3 .byte 0xf3 + 2938 0180 01 .uleb128 0x1 + 2939 0181 50 .byte 0x50 + 2940 0182 9F .byte 0x9f + 2941 0183 00000000 .4byte 0 + 2942 0187 00000000 .4byte 0 + 2943 .LLST11: + 2944 018b 1A000000 .4byte .LVL18 + 2945 018f 27000000 .4byte .LVL19-1 + 2946 0193 0200 .2byte 0x2 + 2947 0195 72 .byte 0x72 + 2948 0196 24 .sleb128 36 + 2949 0197 27000000 .4byte .LVL19-1 + 2950 019b 34000000 .4byte .LFE11 + 2951 019f 0400 .2byte 0x4 + 2952 01a1 F3 .byte 0xf3 + 2953 01a2 01 .uleb128 0x1 + 2954 01a3 50 .byte 0x50 + 2955 01a4 9F .byte 0x9f + 2956 01a5 00000000 .4byte 0 + 2957 01a9 00000000 .4byte 0 + 2958 .LLST12: + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 53 + + + 2959 01ad 1A000000 .4byte .LVL18 + 2960 01b1 27000000 .4byte .LVL19-1 + 2961 01b5 0100 .2byte 0x1 + 2962 01b7 52 .byte 0x52 + 2963 01b8 00000000 .4byte 0 + 2964 01bc 00000000 .4byte 0 + 2965 .LLST13: + 2966 01c0 00000000 .4byte .LFB10 + 2967 01c4 02000000 .4byte .LCFI3 + 2968 01c8 0200 .2byte 0x2 + 2969 01ca 7D .byte 0x7d + 2970 01cb 00 .sleb128 0 + 2971 01cc 02000000 .4byte .LCFI3 + 2972 01d0 0C000000 .4byte .LFE10 + 2973 01d4 0200 .2byte 0x2 + 2974 01d6 7D .byte 0x7d + 2975 01d7 08 .sleb128 8 + 2976 01d8 00000000 .4byte 0 + 2977 01dc 00000000 .4byte 0 + 2978 .LLST14: + 2979 01e0 00000000 .4byte .LVL20 + 2980 01e4 07000000 .4byte .LVL21-1 + 2981 01e8 0100 .2byte 0x1 + 2982 01ea 50 .byte 0x50 + 2983 01eb 07000000 .4byte .LVL21-1 + 2984 01ef 0C000000 .4byte .LFE10 + 2985 01f3 0400 .2byte 0x4 + 2986 01f5 F3 .byte 0xf3 + 2987 01f6 01 .uleb128 0x1 + 2988 01f7 50 .byte 0x50 + 2989 01f8 9F .byte 0x9f + 2990 01f9 00000000 .4byte 0 + 2991 01fd 00000000 .4byte 0 + 2992 .LLST15: + 2993 0201 00000000 .4byte .LFB13 + 2994 0205 06000000 .4byte .LCFI4 + 2995 0209 0200 .2byte 0x2 + 2996 020b 7D .byte 0x7d + 2997 020c 00 .sleb128 0 + 2998 020d 06000000 .4byte .LCFI4 + 2999 0211 3C000000 .4byte .LFE13 + 3000 0215 0200 .2byte 0x2 + 3001 0217 7D .byte 0x7d + 3002 0218 04 .sleb128 4 + 3003 0219 00000000 .4byte 0 + 3004 021d 00000000 .4byte 0 + 3005 .LLST16: + 3006 0221 00000000 .4byte .LVL22 + 3007 0225 04000000 .4byte .LVL23 + 3008 0229 0100 .2byte 0x1 + 3009 022b 50 .byte 0x50 + 3010 022c 04000000 .4byte .LVL23 + 3011 0230 2F000000 .4byte .LVL25-1 + 3012 0234 0100 .2byte 0x1 + 3013 0236 53 .byte 0x53 + 3014 0237 2F000000 .4byte .LVL25-1 + 3015 023b 30000000 .4byte .LVL25 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 54 + + + 3016 023f 0400 .2byte 0x4 + 3017 0241 F3 .byte 0xf3 + 3018 0242 01 .uleb128 0x1 + 3019 0243 50 .byte 0x50 + 3020 0244 9F .byte 0x9f + 3021 0245 30000000 .4byte .LVL25 + 3022 0249 3C000000 .4byte .LFE13 + 3023 024d 0100 .2byte 0x1 + 3024 024f 53 .byte 0x53 + 3025 0250 00000000 .4byte 0 + 3026 0254 00000000 .4byte 0 + 3027 .LLST17: + 3028 0258 00000000 .4byte .LVL22 + 3029 025c 2F000000 .4byte .LVL25-1 + 3030 0260 0100 .2byte 0x1 + 3031 0262 51 .byte 0x51 + 3032 0263 2F000000 .4byte .LVL25-1 + 3033 0267 30000000 .4byte .LVL25 + 3034 026b 0400 .2byte 0x4 + 3035 026d F3 .byte 0xf3 + 3036 026e 01 .uleb128 0x1 + 3037 026f 51 .byte 0x51 + 3038 0270 9F .byte 0x9f + 3039 0271 30000000 .4byte .LVL25 + 3040 0275 3C000000 .4byte .LFE13 + 3041 0279 0100 .2byte 0x1 + 3042 027b 51 .byte 0x51 + 3043 027c 00000000 .4byte 0 + 3044 0280 00000000 .4byte 0 + 3045 .LLST18: + 3046 0284 20000000 .4byte .LVL24 + 3047 0288 2F000000 .4byte .LVL25-1 + 3048 028c 0200 .2byte 0x2 + 3049 028e 72 .byte 0x72 + 3050 028f 24 .sleb128 36 + 3051 0290 2F000000 .4byte .LVL25-1 + 3052 0294 30000000 .4byte .LVL25 + 3053 0298 0400 .2byte 0x4 + 3054 029a F3 .byte 0xf3 + 3055 029b 01 .uleb128 0x1 + 3056 029c 50 .byte 0x50 + 3057 029d 9F .byte 0x9f + 3058 029e 00000000 .4byte 0 + 3059 02a2 00000000 .4byte 0 + 3060 .LLST19: + 3061 02a6 20000000 .4byte .LVL24 + 3062 02aa 2F000000 .4byte .LVL25-1 + 3063 02ae 0100 .2byte 0x1 + 3064 02b0 52 .byte 0x52 + 3065 02b1 00000000 .4byte 0 + 3066 02b5 00000000 .4byte 0 + 3067 .LLST20: + 3068 02b9 00000000 .4byte .LFB12 + 3069 02bd 02000000 .4byte .LCFI5 + 3070 02c1 0200 .2byte 0x2 + 3071 02c3 7D .byte 0x7d + 3072 02c4 00 .sleb128 0 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 55 + + + 3073 02c5 02000000 .4byte .LCFI5 + 3074 02c9 0C000000 .4byte .LFE12 + 3075 02cd 0200 .2byte 0x2 + 3076 02cf 7D .byte 0x7d + 3077 02d0 08 .sleb128 8 + 3078 02d1 00000000 .4byte 0 + 3079 02d5 00000000 .4byte 0 + 3080 .LLST21: + 3081 02d9 00000000 .4byte .LVL26 + 3082 02dd 07000000 .4byte .LVL27-1 + 3083 02e1 0100 .2byte 0x1 + 3084 02e3 50 .byte 0x50 + 3085 02e4 07000000 .4byte .LVL27-1 + 3086 02e8 0C000000 .4byte .LFE12 + 3087 02ec 0400 .2byte 0x4 + 3088 02ee F3 .byte 0xf3 + 3089 02ef 01 .uleb128 0x1 + 3090 02f0 50 .byte 0x50 + 3091 02f1 9F .byte 0x9f + 3092 02f2 00000000 .4byte 0 + 3093 02f6 00000000 .4byte 0 + 3094 .LLST22: + 3095 02fa 00000000 .4byte .LVL26 + 3096 02fe 07000000 .4byte .LVL27-1 + 3097 0302 0100 .2byte 0x1 + 3098 0304 51 .byte 0x51 + 3099 0305 07000000 .4byte .LVL27-1 + 3100 0309 0C000000 .4byte .LFE12 + 3101 030d 0400 .2byte 0x4 + 3102 030f F3 .byte 0xf3 + 3103 0310 01 .uleb128 0x1 + 3104 0311 51 .byte 0x51 + 3105 0312 9F .byte 0x9f + 3106 0313 00000000 .4byte 0 + 3107 0317 00000000 .4byte 0 + 3108 .LLST23: + 3109 031b 00000000 .4byte .LFB14 + 3110 031f 02000000 .4byte .LCFI6 + 3111 0323 0200 .2byte 0x2 + 3112 0325 7D .byte 0x7d + 3113 0326 00 .sleb128 0 + 3114 0327 02000000 .4byte .LCFI6 + 3115 032b 26000000 .4byte .LFE14 + 3116 032f 0200 .2byte 0x2 + 3117 0331 7D .byte 0x7d + 3118 0332 08 .sleb128 8 + 3119 0333 00000000 .4byte 0 + 3120 0337 00000000 .4byte 0 + 3121 .LLST24: + 3122 033b 00000000 .4byte .LVL28 + 3123 033f 16000000 .4byte .LVL30 + 3124 0343 0100 .2byte 0x1 + 3125 0345 50 .byte 0x50 + 3126 0346 16000000 .4byte .LVL30 + 3127 034a 21000000 .4byte .LVL31-1 + 3128 034e 0100 .2byte 0x1 + 3129 0350 53 .byte 0x53 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 56 + + + 3130 0351 21000000 .4byte .LVL31-1 + 3131 0355 26000000 .4byte .LFE14 + 3132 0359 0400 .2byte 0x4 + 3133 035b F3 .byte 0xf3 + 3134 035c 01 .uleb128 0x1 + 3135 035d 50 .byte 0x50 + 3136 035e 9F .byte 0x9f + 3137 035f 00000000 .4byte 0 + 3138 0363 00000000 .4byte 0 + 3139 .LLST25: + 3140 0367 14000000 .4byte .LVL29 + 3141 036b 16000000 .4byte .LVL30 + 3142 036f 0100 .2byte 0x1 + 3143 0371 50 .byte 0x50 + 3144 0372 16000000 .4byte .LVL30 + 3145 0376 21000000 .4byte .LVL31-1 + 3146 037a 0100 .2byte 0x1 + 3147 037c 53 .byte 0x53 + 3148 037d 21000000 .4byte .LVL31-1 + 3149 0381 26000000 .4byte .LFE14 + 3150 0385 0400 .2byte 0x4 + 3151 0387 F3 .byte 0xf3 + 3152 0388 01 .uleb128 0x1 + 3153 0389 50 .byte 0x50 + 3154 038a 9F .byte 0x9f + 3155 038b 00000000 .4byte 0 + 3156 038f 00000000 .4byte 0 + 3157 .LLST26: + 3158 0393 16000000 .4byte .LVL30 + 3159 0397 21000000 .4byte .LVL31-1 + 3160 039b 0100 .2byte 0x1 + 3161 039d 50 .byte 0x50 + 3162 039e 00000000 .4byte 0 + 3163 03a2 00000000 .4byte 0 + 3164 .LLST27: + 3165 03a6 00000000 .4byte .LVL32 + 3166 03aa 14000000 .4byte .LVL35 + 3167 03ae 0100 .2byte 0x1 + 3168 03b0 50 .byte 0x50 + 3169 03b1 14000000 .4byte .LVL35 + 3170 03b5 1A000000 .4byte .LVL36 + 3171 03b9 0100 .2byte 0x1 + 3172 03bb 53 .byte 0x53 + 3173 03bc 1A000000 .4byte .LVL36 + 3174 03c0 1F000000 .4byte .LVL37-1 + 3175 03c4 0200 .2byte 0x2 + 3176 03c6 71 .byte 0x71 + 3177 03c7 04 .sleb128 4 + 3178 03c8 1F000000 .4byte .LVL37-1 + 3179 03cc 20000000 .4byte .LFE15 + 3180 03d0 0400 .2byte 0x4 + 3181 03d2 F3 .byte 0xf3 + 3182 03d3 01 .uleb128 0x1 + 3183 03d4 50 .byte 0x50 + 3184 03d5 9F .byte 0x9f + 3185 03d6 00000000 .4byte 0 + 3186 03da 00000000 .4byte 0 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 57 + + + 3187 .LLST28: + 3188 03de 0E000000 .4byte .LVL33 + 3189 03e2 14000000 .4byte .LVL35 + 3190 03e6 0100 .2byte 0x1 + 3191 03e8 50 .byte 0x50 + 3192 03e9 14000000 .4byte .LVL35 + 3193 03ed 1A000000 .4byte .LVL36 + 3194 03f1 0100 .2byte 0x1 + 3195 03f3 53 .byte 0x53 + 3196 03f4 1A000000 .4byte .LVL36 + 3197 03f8 1F000000 .4byte .LVL37-1 + 3198 03fc 0200 .2byte 0x2 + 3199 03fe 71 .byte 0x71 + 3200 03ff 04 .sleb128 4 + 3201 0400 1F000000 .4byte .LVL37-1 + 3202 0404 20000000 .4byte .LFE15 + 3203 0408 0400 .2byte 0x4 + 3204 040a F3 .byte 0xf3 + 3205 040b 01 .uleb128 0x1 + 3206 040c 50 .byte 0x50 + 3207 040d 9F .byte 0x9f + 3208 040e 00000000 .4byte 0 + 3209 0412 00000000 .4byte 0 + 3210 .LLST29: + 3211 0416 10000000 .4byte .LVL34 + 3212 041a 1F000000 .4byte .LVL37-1 + 3213 041e 0100 .2byte 0x1 + 3214 0420 52 .byte 0x52 + 3215 0421 00000000 .4byte 0 + 3216 0425 00000000 .4byte 0 + 3217 .LLST30: + 3218 0429 00000000 .4byte .LFB16 + 3219 042d 02000000 .4byte .LCFI7 + 3220 0431 0200 .2byte 0x2 + 3221 0433 7D .byte 0x7d + 3222 0434 00 .sleb128 0 + 3223 0435 02000000 .4byte .LCFI7 + 3224 0439 2E000000 .4byte .LFE16 + 3225 043d 0200 .2byte 0x2 + 3226 043f 7D .byte 0x7d + 3227 0440 10 .sleb128 16 + 3228 0441 00000000 .4byte 0 + 3229 0445 00000000 .4byte 0 + 3230 .LLST31: + 3231 0449 00000000 .4byte .LVL38 + 3232 044d 0C000000 .4byte .LVL39 + 3233 0451 0100 .2byte 0x1 + 3234 0453 50 .byte 0x50 + 3235 0454 0C000000 .4byte .LVL39 + 3236 0458 2E000000 .4byte .LFE16 + 3237 045c 0100 .2byte 0x1 + 3238 045e 55 .byte 0x55 + 3239 045f 00000000 .4byte 0 + 3240 0463 00000000 .4byte 0 + 3241 .LLST32: + 3242 0467 00000000 .4byte .LVL38 + 3243 046b 0C000000 .4byte .LVL39 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 58 + + + 3244 046f 0100 .2byte 0x1 + 3245 0471 51 .byte 0x51 + 3246 0472 0C000000 .4byte .LVL39 + 3247 0476 0E000000 .4byte .LVL40 + 3248 047a 0300 .2byte 0x3 + 3249 047c 74 .byte 0x74 + 3250 047d 7F .sleb128 -1 + 3251 047e 9F .byte 0x9f + 3252 047f 0E000000 .4byte .LVL40 + 3253 0483 10000000 .4byte .LVL41 + 3254 0487 0100 .2byte 0x1 + 3255 0489 54 .byte 0x54 + 3256 048a 00000000 .4byte 0 + 3257 048e 00000000 .4byte 0 + 3258 .LLST33: + 3259 0492 1A000000 .4byte .LVL42 + 3260 0496 2C000000 .4byte .LVL45 + 3261 049a 0100 .2byte 0x1 + 3262 049c 55 .byte 0x55 + 3263 049d 00000000 .4byte 0 + 3264 04a1 00000000 .4byte 0 + 3265 .LLST34: + 3266 04a5 1C000000 .4byte .LVL43 + 3267 04a9 25000000 .4byte .LVL44-1 + 3268 04ad 0100 .2byte 0x1 + 3269 04af 50 .byte 0x50 + 3270 04b0 00000000 .4byte 0 + 3271 04b4 00000000 .4byte 0 + 3272 .LLST35: + 3273 04b8 00000000 .4byte .LFB17 + 3274 04bc 02000000 .4byte .LCFI8 + 3275 04c0 0200 .2byte 0x2 + 3276 04c2 7D .byte 0x7d + 3277 04c3 00 .sleb128 0 + 3278 04c4 02000000 .4byte .LCFI8 + 3279 04c8 06000000 .4byte .LCFI9 + 3280 04cc 0200 .2byte 0x2 + 3281 04ce 7D .byte 0x7d + 3282 04cf 08 .sleb128 8 + 3283 04d0 06000000 .4byte .LCFI9 + 3284 04d4 5C000000 .4byte .LFE17 + 3285 04d8 0200 .2byte 0x2 + 3286 04da 7D .byte 0x7d + 3287 04db 10 .sleb128 16 + 3288 04dc 00000000 .4byte 0 + 3289 04e0 00000000 .4byte 0 + 3290 .LLST36: + 3291 04e4 00000000 .4byte .LVL46 + 3292 04e8 12000000 .4byte .LVL47 + 3293 04ec 0100 .2byte 0x1 + 3294 04ee 50 .byte 0x50 + 3295 04ef 12000000 .4byte .LVL47 + 3296 04f3 42000000 .4byte .LVL54 + 3297 04f7 0400 .2byte 0x4 + 3298 04f9 F3 .byte 0xf3 + 3299 04fa 01 .uleb128 0x1 + 3300 04fb 50 .byte 0x50 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 59 + + + 3301 04fc 9F .byte 0x9f + 3302 04fd 42000000 .4byte .LVL54 + 3303 0501 44000000 .4byte .LVL55 + 3304 0505 0100 .2byte 0x1 + 3305 0507 50 .byte 0x50 + 3306 0508 44000000 .4byte .LVL55 + 3307 050c 4F000000 .4byte .LVL56-1 + 3308 0510 0100 .2byte 0x1 + 3309 0512 53 .byte 0x53 + 3310 0513 4F000000 .4byte .LVL56-1 + 3311 0517 5C000000 .4byte .LFE17 + 3312 051b 0400 .2byte 0x4 + 3313 051d F3 .byte 0xf3 + 3314 051e 01 .uleb128 0x1 + 3315 051f 50 .byte 0x50 + 3316 0520 9F .byte 0x9f + 3317 0521 00000000 .4byte 0 + 3318 0525 00000000 .4byte 0 + 3319 .LLST37: + 3320 0529 00000000 .4byte .LVL46 + 3321 052d 12000000 .4byte .LVL47 + 3322 0531 0100 .2byte 0x1 + 3323 0533 51 .byte 0x51 + 3324 0534 12000000 .4byte .LVL47 + 3325 0538 42000000 .4byte .LVL54 + 3326 053c 0400 .2byte 0x4 + 3327 053e F3 .byte 0xf3 + 3328 053f 01 .uleb128 0x1 + 3329 0540 51 .byte 0x51 + 3330 0541 9F .byte 0x9f + 3331 0542 42000000 .4byte .LVL54 + 3332 0546 4F000000 .4byte .LVL56-1 + 3333 054a 0100 .2byte 0x1 + 3334 054c 51 .byte 0x51 + 3335 054d 4F000000 .4byte .LVL56-1 + 3336 0551 5C000000 .4byte .LFE17 + 3337 0555 0400 .2byte 0x4 + 3338 0557 F3 .byte 0xf3 + 3339 0558 01 .uleb128 0x1 + 3340 0559 51 .byte 0x51 + 3341 055a 9F .byte 0x9f + 3342 055b 00000000 .4byte 0 + 3343 055f 00000000 .4byte 0 + 3344 .LLST38: + 3345 0563 20000000 .4byte .LVL48 + 3346 0567 22000000 .4byte .LVL49 + 3347 056b 0200 .2byte 0x2 + 3348 056d 30 .byte 0x30 + 3349 056e 9F .byte 0x9f + 3350 056f 22000000 .4byte .LVL49 + 3351 0573 28000000 .4byte .LVL50 + 3352 0577 0100 .2byte 0x1 + 3353 0579 50 .byte 0x50 + 3354 057a 40000000 .4byte .LVL53 + 3355 057e 42000000 .4byte .LVL54 + 3356 0582 0100 .2byte 0x1 + 3357 0584 50 .byte 0x50 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 60 + + + 3358 0585 00000000 .4byte 0 + 3359 0589 00000000 .4byte 0 + 3360 .LLST39: + 3361 058d 2E000000 .4byte .LVL51 + 3362 0591 42000000 .4byte .LVL54 + 3363 0595 0100 .2byte 0x1 + 3364 0597 54 .byte 0x54 + 3365 0598 00000000 .4byte 0 + 3366 059c 00000000 .4byte 0 + 3367 .LLST40: + 3368 05a0 2E000000 .4byte .LVL51 + 3369 05a4 3D000000 .4byte .LVL52-1 + 3370 05a8 0100 .2byte 0x1 + 3371 05aa 51 .byte 0x51 + 3372 05ab 00000000 .4byte 0 + 3373 05af 00000000 .4byte 0 + 3374 .LLST42: + 3375 05b3 42000000 .4byte .LVL54 + 3376 05b7 44000000 .4byte .LVL55 + 3377 05bb 0100 .2byte 0x1 + 3378 05bd 50 .byte 0x50 + 3379 05be 44000000 .4byte .LVL55 + 3380 05c2 4F000000 .4byte .LVL56-1 + 3381 05c6 0100 .2byte 0x1 + 3382 05c8 53 .byte 0x53 + 3383 05c9 4F000000 .4byte .LVL56-1 + 3384 05cd 5C000000 .4byte .LFE17 + 3385 05d1 0400 .2byte 0x4 + 3386 05d3 F3 .byte 0xf3 + 3387 05d4 01 .uleb128 0x1 + 3388 05d5 50 .byte 0x50 + 3389 05d6 9F .byte 0x9f + 3390 05d7 00000000 .4byte 0 + 3391 05db 00000000 .4byte 0 + 3392 .LLST43: + 3393 05df 44000000 .4byte .LVL55 + 3394 05e3 4F000000 .4byte .LVL56-1 + 3395 05e7 0100 .2byte 0x1 + 3396 05e9 50 .byte 0x50 + 3397 05ea 00000000 .4byte 0 + 3398 05ee 00000000 .4byte 0 + 3399 .section .debug_aranges,"",%progbits + 3400 0000 6C000000 .4byte 0x6c + 3401 0004 0200 .2byte 0x2 + 3402 0006 00000000 .4byte .Ldebug_info0 + 3403 000a 04 .byte 0x4 + 3404 000b 00 .byte 0 + 3405 000c 0000 .2byte 0 + 3406 000e 0000 .2byte 0 + 3407 0010 00000000 .4byte .LFB7 + 3408 0014 08000000 .4byte .LFE7-.LFB7 + 3409 0018 00000000 .4byte .LFB9 + 3410 001c 28000000 .4byte .LFE9-.LFB9 + 3411 0020 00000000 .4byte .LFB8 + 3412 0024 10000000 .4byte .LFE8-.LFB8 + 3413 0028 00000000 .4byte .LFB11 + 3414 002c 34000000 .4byte .LFE11-.LFB11 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 61 + + + 3415 0030 00000000 .4byte .LFB10 + 3416 0034 0C000000 .4byte .LFE10-.LFB10 + 3417 0038 00000000 .4byte .LFB13 + 3418 003c 3C000000 .4byte .LFE13-.LFB13 + 3419 0040 00000000 .4byte .LFB12 + 3420 0044 0C000000 .4byte .LFE12-.LFB12 + 3421 0048 00000000 .4byte .LFB14 + 3422 004c 26000000 .4byte .LFE14-.LFB14 + 3423 0050 00000000 .4byte .LFB15 + 3424 0054 20000000 .4byte .LFE15-.LFB15 + 3425 0058 00000000 .4byte .LFB16 + 3426 005c 2E000000 .4byte .LFE16-.LFB16 + 3427 0060 00000000 .4byte .LFB17 + 3428 0064 5C000000 .4byte .LFE17-.LFB17 + 3429 0068 00000000 .4byte 0 + 3430 006c 00000000 .4byte 0 + 3431 .section .debug_ranges,"",%progbits + 3432 .Ldebug_ranges0: + 3433 0000 12000000 .4byte .LBB20 + 3434 0004 14000000 .4byte .LBE20 + 3435 0008 16000000 .4byte .LBB23 + 3436 000c 1C000000 .4byte .LBE23 + 3437 0010 00000000 .4byte 0 + 3438 0014 00000000 .4byte 0 + 3439 0018 12000000 .4byte .LBB21 + 3440 001c 14000000 .4byte .LBE21 + 3441 0020 16000000 .4byte .LBB22 + 3442 0024 1C000000 .4byte .LBE22 + 3443 0028 00000000 .4byte 0 + 3444 002c 00000000 .4byte 0 + 3445 0030 14000000 .4byte .LBB28 + 3446 0034 16000000 .4byte .LBE28 + 3447 0038 18000000 .4byte .LBB31 + 3448 003c 1E000000 .4byte .LBE31 + 3449 0040 00000000 .4byte 0 + 3450 0044 00000000 .4byte 0 + 3451 0048 14000000 .4byte .LBB29 + 3452 004c 16000000 .4byte .LBE29 + 3453 0050 18000000 .4byte .LBB30 + 3454 0054 1E000000 .4byte .LBE30 + 3455 0058 00000000 .4byte 0 + 3456 005c 00000000 .4byte 0 + 3457 0060 0E000000 .4byte .LBB32 + 3458 0064 1C000000 .4byte .LBE32 + 3459 0068 1C000000 .4byte .LBB37 + 3460 006c 20000000 .4byte .LBE37 + 3461 0070 00000000 .4byte 0 + 3462 0074 00000000 .4byte 0 + 3463 0078 0E000000 .4byte .LBB33 + 3464 007c 12000000 .4byte .LBE33 + 3465 0080 14000000 .4byte .LBB36 + 3466 0084 18000000 .4byte .LBE36 + 3467 0088 00000000 .4byte 0 + 3468 008c 00000000 .4byte 0 + 3469 0090 0E000000 .4byte .LBB34 + 3470 0094 12000000 .4byte .LBE34 + 3471 0098 14000000 .4byte .LBB35 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 62 + + + 3472 009c 18000000 .4byte .LBE35 + 3473 00a0 00000000 .4byte 0 + 3474 00a4 00000000 .4byte 0 + 3475 00a8 2A000000 .4byte .LBB41 + 3476 00ac 2C000000 .4byte .LBE41 + 3477 00b0 30000000 .4byte .LBB44 + 3478 00b4 38000000 .4byte .LBE44 + 3479 00b8 00000000 .4byte 0 + 3480 00bc 00000000 .4byte 0 + 3481 00c0 00000000 .4byte .LFB7 + 3482 00c4 08000000 .4byte .LFE7 + 3483 00c8 00000000 .4byte .LFB9 + 3484 00cc 28000000 .4byte .LFE9 + 3485 00d0 00000000 .4byte .LFB8 + 3486 00d4 10000000 .4byte .LFE8 + 3487 00d8 00000000 .4byte .LFB11 + 3488 00dc 34000000 .4byte .LFE11 + 3489 00e0 00000000 .4byte .LFB10 + 3490 00e4 0C000000 .4byte .LFE10 + 3491 00e8 00000000 .4byte .LFB13 + 3492 00ec 3C000000 .4byte .LFE13 + 3493 00f0 00000000 .4byte .LFB12 + 3494 00f4 0C000000 .4byte .LFE12 + 3495 00f8 00000000 .4byte .LFB14 + 3496 00fc 26000000 .4byte .LFE14 + 3497 0100 00000000 .4byte .LFB15 + 3498 0104 20000000 .4byte .LFE15 + 3499 0108 00000000 .4byte .LFB16 + 3500 010c 2E000000 .4byte .LFE16 + 3501 0110 00000000 .4byte .LFB17 + 3502 0114 5C000000 .4byte .LFE17 + 3503 0118 00000000 .4byte 0 + 3504 011c 00000000 .4byte 0 + 3505 .section .debug_line,"",%progbits + 3506 .Ldebug_line0: + 3507 0000 D3020000 .section .debug_str,"MS",%progbits,1 + 3507 02000F01 + 3507 00000201 + 3507 FB0E0D00 + 3507 01010101 + 3508 .LASF34: + 3509 0000 705F6D73 .ascii "p_msg\000" + 3509 6700 + 3510 .LASF84: + 3511 0006 71756575 .ascii "queue_insert\000" + 3511 655F696E + 3511 73657274 + 3511 00 + 3512 .LASF76: + 3513 0013 63685365 .ascii "chSemSignalI\000" + 3513 6D536967 + 3513 6E616C49 + 3513 00 + 3514 .LASF60: + 3515 0020 7264796D .ascii "rdymsg\000" + 3515 736700 + 3516 .LASF11: + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 63 + + + 3517 0027 6C6F6E67 .ascii "long long unsigned int\000" + 3517 206C6F6E + 3517 6720756E + 3517 7369676E + 3517 65642069 + 3518 .LASF61: + 3519 003e 65786974 .ascii "exitcode\000" + 3519 636F6465 + 3519 00 + 3520 .LASF77: + 3521 0047 63685365 .ascii "chSemAddCounterI\000" + 3521 6D416464 + 3521 436F756E + 3521 74657249 + 3521 00 + 3522 .LASF23: + 3523 0058 705F7072 .ascii "p_prio\000" + 3523 696F00 + 3524 .LASF10: + 3525 005f 6C6F6E67 .ascii "long long int\000" + 3525 206C6F6E + 3525 6720696E + 3525 7400 + 3526 .LASF1: + 3527 006d 7369676E .ascii "signed char\000" + 3527 65642063 + 3527 68617200 + 3528 .LASF78: + 3529 0079 63685365 .ascii "chSemSignalWait\000" + 3529 6D536967 + 3529 6E616C57 + 3529 61697400 + 3530 .LASF38: + 3531 0089 705F6D70 .ascii "p_mpool\000" + 3531 6F6F6C00 + 3532 .LASF57: + 3533 0091 6D5F7175 .ascii "m_queue\000" + 3533 65756500 + 3534 .LASF7: + 3535 0099 6C6F6E67 .ascii "long int\000" + 3535 20696E74 + 3535 00 + 3536 .LASF13: + 3537 00a2 74737461 .ascii "tstate_t\000" + 3537 74655F74 + 3537 00 + 3538 .LASF75: + 3539 00ab 63685365 .ascii "chSemSignal\000" + 3539 6D536967 + 3539 6E616C00 + 3540 .LASF25: + 3541 00b7 705F6E65 .ascii "p_newer\000" + 3541 77657200 + 3542 .LASF54: + 3543 00bf 735F7175 .ascii "s_queue\000" + 3543 65756500 + 3544 .LASF86: + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 64 + + + 3545 00c7 63685363 .ascii "chSchRescheduleS\000" + 3545 68526573 + 3545 63686564 + 3545 756C6553 + 3545 00 + 3546 .LASF48: + 3547 00d8 725F6E65 .ascii "r_newer\000" + 3547 77657200 + 3548 .LASF41: + 3549 00e0 72656761 .ascii "regarm_t\000" + 3549 726D5F74 + 3549 00 + 3550 .LASF19: + 3551 00e9 636E745F .ascii "cnt_t\000" + 3551 7400 + 3552 .LASF0: + 3553 00ef 756E7369 .ascii "unsigned int\000" + 3553 676E6564 + 3553 20696E74 + 3553 00 + 3554 .LASF74: + 3555 00fc 63685365 .ascii "chSemWaitTimeout\000" + 3555 6D576169 + 3555 7454696D + 3555 656F7574 + 3555 00 + 3556 .LASF9: + 3557 010d 6C6F6E67 .ascii "long unsigned int\000" + 3557 20756E73 + 3557 69676E65 + 3557 6420696E + 3557 7400 + 3558 .LASF55: + 3559 011f 735F636E .ascii "s_cnt\000" + 3559 7400 + 3560 .LASF43: + 3561 0125 636F6E74 .ascii "context\000" + 3561 65787400 + 3562 .LASF4: + 3563 012d 73686F72 .ascii "short unsigned int\000" + 3563 7420756E + 3563 7369676E + 3563 65642069 + 3563 6E7400 + 3564 .LASF69: + 3565 0140 63685365 .ascii "chSemReset\000" + 3565 6D526573 + 3565 657400 + 3566 .LASF82: + 3567 014b 2E2E2F2E .ascii "../..//os/kernel/src/chsem.c\000" + 3567 2E2F2F6F + 3567 732F6B65 + 3567 726E656C + 3567 2F737263 + 3568 .LASF16: + 3569 0168 6D73675F .ascii "msg_t\000" + 3569 7400 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 65 + + + 3570 .LASF12: + 3571 016e 746D6F64 .ascii "tmode_t\000" + 3571 655F7400 + 3572 .LASF40: + 3573 0176 54687265 .ascii "ThreadsList\000" + 3573 6164734C + 3573 69737400 + 3574 .LASF17: + 3575 0182 6576656E .ascii "eventmask_t\000" + 3575 746D6173 + 3575 6B5F7400 + 3576 .LASF56: + 3577 018e 4D757465 .ascii "Mutex\000" + 3577 7800 + 3578 .LASF44: + 3579 0194 73697A65 .ascii "sizetype\000" + 3579 74797065 + 3579 00 + 3580 .LASF26: + 3581 019d 705F6F6C .ascii "p_older\000" + 3581 64657200 + 3582 .LASF83: + 3583 01a5 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 3583 73657273 + 3583 5C496D61 + 3583 6E6F6C5C + 3583 64657665 + 3584 01d2 6C696361 .ascii "lications\\smartcities\000" + 3584 74696F6E + 3584 735C736D + 3584 61727463 + 3584 69746965 + 3585 .LASF39: + 3586 01e8 54687265 .ascii "ThreadsQueue\000" + 3586 61647351 + 3586 75657565 + 3586 00 + 3587 .LASF73: + 3588 01f5 74696D65 .ascii "time\000" + 3588 00 + 3589 .LASF81: + 3590 01fa 474E5520 .ascii "GNU C 4.7.2\000" + 3590 4320342E + 3590 372E3200 + 3591 .LASF51: + 3592 0206 725F6375 .ascii "r_current\000" + 3592 7272656E + 3592 7400 + 3593 .LASF49: + 3594 0210 725F6F6C .ascii "r_older\000" + 3594 64657200 + 3595 .LASF14: + 3596 0218 74726566 .ascii "trefs_t\000" + 3596 735F7400 + 3597 .LASF22: + 3598 0220 705F7072 .ascii "p_prev\000" + 3598 657600 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 66 + + + 3599 .LASF15: + 3600 0227 74707269 .ascii "tprio_t\000" + 3600 6F5F7400 + 3601 .LASF6: + 3602 022f 696E7433 .ascii "int32_t\000" + 3602 325F7400 + 3603 .LASF2: + 3604 0237 756E7369 .ascii "unsigned char\000" + 3604 676E6564 + 3604 20636861 + 3604 7200 + 3605 .LASF36: + 3606 0245 705F6D74 .ascii "p_mtxlist\000" + 3606 786C6973 + 3606 7400 + 3607 .LASF3: + 3608 024f 73686F72 .ascii "short int\000" + 3608 7420696E + 3608 7400 + 3609 .LASF28: + 3610 0259 705F7374 .ascii "p_state\000" + 3610 61746500 + 3611 .LASF46: + 3612 0261 725F7072 .ascii "r_prio\000" + 3612 696F00 + 3613 .LASF63: + 3614 0268 65776D61 .ascii "ewmask\000" + 3614 736B00 + 3615 .LASF21: + 3616 026f 705F6E65 .ascii "p_next\000" + 3616 787400 + 3617 .LASF29: + 3618 0276 705F666C .ascii "p_flags\000" + 3618 61677300 + 3619 .LASF70: + 3620 027e 63685365 .ascii "chSemWaitS\000" + 3620 6D576169 + 3620 745300 + 3621 .LASF20: + 3622 0289 54687265 .ascii "Thread\000" + 3622 616400 + 3623 .LASF87: + 3624 0290 63685363 .ascii "chSchGoSleepS\000" + 3624 68476F53 + 3624 6C656570 + 3624 5300 + 3625 .LASF35: + 3626 029e 705F6570 .ascii "p_epending\000" + 3626 656E6469 + 3626 6E6700 + 3627 .LASF8: + 3628 02a9 75696E74 .ascii "uint32_t\000" + 3628 33325F74 + 3628 00 + 3629 .LASF45: + 3630 02b2 725F7175 .ascii "r_queue\000" + 3630 65756500 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 67 + + + 3631 .LASF79: + 3632 02ba 63685363 .ascii "chSchReadyI\000" + 3632 68526561 + 3632 64794900 + 3633 .LASF64: + 3634 02c6 63686172 .ascii "char\000" + 3634 00 + 3635 .LASF66: + 3636 02cb 6669666F .ascii "fifo_remove\000" + 3636 5F72656D + 3636 6F766500 + 3637 .LASF72: + 3638 02d7 63685365 .ascii "chSemWaitTimeoutS\000" + 3638 6D576169 + 3638 7454696D + 3638 656F7574 + 3638 5300 + 3639 .LASF59: + 3640 02e9 6D5F6E65 .ascii "m_next\000" + 3640 787400 + 3641 .LASF18: + 3642 02f0 73797374 .ascii "systime_t\000" + 3642 696D655F + 3642 7400 + 3643 .LASF37: + 3644 02fa 705F7265 .ascii "p_realprio\000" + 3644 616C7072 + 3644 696F00 + 3645 .LASF71: + 3646 0305 63685365 .ascii "chSemWait\000" + 3646 6D576169 + 3646 7400 + 3647 .LASF31: + 3648 030f 705F7469 .ascii "p_time\000" + 3648 6D6500 + 3649 .LASF47: + 3650 0316 725F6374 .ascii "r_ctx\000" + 3650 7800 + 3651 .LASF65: + 3652 031c 6C69666F .ascii "lifo_remove\000" + 3652 5F72656D + 3652 6F766500 + 3653 .LASF42: + 3654 0328 696E7463 .ascii "intctx\000" + 3654 747800 + 3655 .LASF33: + 3656 032f 705F6D73 .ascii "p_msgqueue\000" + 3656 67717565 + 3656 756500 + 3657 .LASF88: + 3658 033a 63685363 .ascii "chSchWakeupS\000" + 3658 6857616B + 3658 65757053 + 3658 00 + 3659 .LASF53: + 3660 0347 53656D61 .ascii "Semaphore\000" + 3660 70686F72 + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 68 + + + 3660 6500 + 3661 .LASF30: + 3662 0351 705F7265 .ascii "p_refs\000" + 3662 667300 + 3663 .LASF52: + 3664 0358 52656164 .ascii "ReadyList\000" + 3664 794C6973 + 3664 7400 + 3665 .LASF68: + 3666 0362 63685365 .ascii "chSemResetI\000" + 3666 6D526573 + 3666 65744900 + 3667 .LASF85: + 3668 036e 726C6973 .ascii "rlist\000" + 3668 7400 + 3669 .LASF5: + 3670 0374 75696E74 .ascii "uint8_t\000" + 3670 385F7400 + 3671 .LASF62: + 3672 037c 77746F62 .ascii "wtobjp\000" + 3672 6A7000 + 3673 .LASF27: + 3674 0383 705F6E61 .ascii "p_name\000" + 3674 6D6500 + 3675 .LASF80: + 3676 038a 63685363 .ascii "chSchGoSleepTimeoutS\000" + 3676 68476F53 + 3676 6C656570 + 3676 54696D65 + 3676 6F757453 + 3677 .LASF50: + 3678 039f 725F7072 .ascii "r_preempt\000" + 3678 65656D70 + 3678 7400 + 3679 .LASF58: + 3680 03a9 6D5F6F77 .ascii "m_owner\000" + 3680 6E657200 + 3681 .LASF24: + 3682 03b1 705F6374 .ascii "p_ctx\000" + 3682 7800 + 3683 .LASF32: + 3684 03b7 705F7761 .ascii "p_waiting\000" + 3684 6974696E + 3684 6700 + 3685 .LASF67: + 3686 03c1 63685365 .ascii "chSemInit\000" + 3686 6D496E69 + 3686 7400 + 3687 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\ccSEIsXl.s page 69 + + +DEFINED SYMBOLS + *ABS*:00000000 chsem.c +C:\cygwin\tmp\ccSEIsXl.s:19 .text.chSemInit:00000000 $t +C:\cygwin\tmp\ccSEIsXl.s:25 .text.chSemInit:00000000 chSemInit +C:\cygwin\tmp\ccSEIsXl.s:44 .text.chSemResetI:00000000 $t +C:\cygwin\tmp\ccSEIsXl.s:50 .text.chSemResetI:00000000 chSemResetI +C:\cygwin\tmp\ccSEIsXl.s:118 .text.chSemReset:00000000 $t +C:\cygwin\tmp\ccSEIsXl.s:124 .text.chSemReset:00000000 chSemReset +C:\cygwin\tmp\ccSEIsXl.s:157 .text.chSemWaitS:00000000 $t +C:\cygwin\tmp\ccSEIsXl.s:163 .text.chSemWaitS:00000000 chSemWaitS +C:\cygwin\tmp\ccSEIsXl.s:225 .text.chSemWaitS:00000030 $d +C:\cygwin\tmp\ccSEIsXl.s:230 .text.chSemWait:00000000 $t +C:\cygwin\tmp\ccSEIsXl.s:236 .text.chSemWait:00000000 chSemWait +C:\cygwin\tmp\ccSEIsXl.s:267 .text.chSemWaitTimeoutS:00000000 $t +C:\cygwin\tmp\ccSEIsXl.s:273 .text.chSemWaitTimeoutS:00000000 chSemWaitTimeoutS +C:\cygwin\tmp\ccSEIsXl.s:339 .text.chSemWaitTimeoutS:00000038 $d +C:\cygwin\tmp\ccSEIsXl.s:344 .text.chSemWaitTimeout:00000000 $t +C:\cygwin\tmp\ccSEIsXl.s:350 .text.chSemWaitTimeout:00000000 chSemWaitTimeout +C:\cygwin\tmp\ccSEIsXl.s:381 .text.chSemSignal:00000000 $t +C:\cygwin\tmp\ccSEIsXl.s:387 .text.chSemSignal:00000000 chSemSignal +C:\cygwin\tmp\ccSEIsXl.s:450 .text.chSemSignalI:00000000 $t +C:\cygwin\tmp\ccSEIsXl.s:456 .text.chSemSignalI:00000000 chSemSignalI +C:\cygwin\tmp\ccSEIsXl.s:511 .text.chSemAddCounterI:00000000 $t +C:\cygwin\tmp\ccSEIsXl.s:517 .text.chSemAddCounterI:00000000 chSemAddCounterI +C:\cygwin\tmp\ccSEIsXl.s:582 .text.chSemSignalWait:00000000 $t +C:\cygwin\tmp\ccSEIsXl.s:588 .text.chSemSignalWait:00000000 chSemSignalWait +C:\cygwin\tmp\ccSEIsXl.s:697 .text.chSemSignalWait:00000058 $d + .debug_frame:00000010 $d +C:\cygwin\tmp\ccSEIsXl.s:229 .text.chSemWaitS:00000034 $t +C:\cygwin\tmp\ccSEIsXl.s:343 .text.chSemWaitTimeoutS:0000003c $t +C:\cygwin\tmp\ccSEIsXl.s:701 .text.chSemSignalWait:0000005c $t + +UNDEFINED SYMBOLS +chSchReadyI +chSchRescheduleS +chSchGoSleepS +rlist +chSchGoSleepTimeoutS +chSchWakeupS diff --git a/Project/applications/smartcities/build/lst/chsys.lst b/Project/applications/smartcities/build/lst/chsys.lst new file mode 100644 index 0000000..bdb24da --- /dev/null +++ b/Project/applications/smartcities/build/lst/chsys.lst @@ -0,0 +1,2249 @@ +ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "chsys.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text.chSysInit,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .global chSysInit + 22 .thumb + 23 .thumb_func + 24 .type chSysInit, %function + 25 chSysInit: + 26 .LFB7: + 27 .file 1 "../..//os/kernel/src/chsys.c" + 28 .loc 1 84 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 0000 08B5 push {r3, lr} + 33 .LCFI0: + 34 .cfi_def_cfa_offset 8 + 35 .cfi_offset 3, -8 + 36 .cfi_offset 14, -4 + 37 .loc 1 90 0 + 38 0002 FFF7FEFF bl _port_init + 39 .LVL0: + 40 .loc 1 91 0 + 41 0006 FFF7FEFF bl _scheduler_init + 42 .LVL1: + 43 .loc 1 92 0 + 44 000a FFF7FEFF bl _vt_init + 45 .LVL2: + 46 .loc 1 94 0 + 47 000e FFF7FEFF bl _core_init + 48 .LVL3: + 49 .loc 1 97 0 + 50 0012 FFF7FEFF bl _heap_init + 51 .LVL4: + 52 .loc 1 104 0 + 53 0016 40F20000 movw r0, #:lower16:.LANCHOR0 + 54 001a 4021 movs r1, #64 + 55 001c C0F20000 movt r0, #:upper16:.LANCHOR0 + 56 0020 FFF7FEFF bl _thread_init + 57 .LVL5: + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 2 + + + 58 0024 40F20003 movw r3, #:lower16:rlist + 59 0028 C0F20003 movt r3, #:upper16:rlist + 60 .loc 1 105 0 + 61 002c 0122 movs r2, #1 + 62 .loc 1 104 0 + 63 002e D861 str r0, [r3, #28] + 64 .loc 1 105 0 + 65 0030 0277 strb r2, [r0, #28] + 66 .loc 1 111 0 + 67 @ 111 "../..//os/kernel/src/chsys.c" 1 + 68 0032 62B6 cpsie i + 69 @ 0 "" 2 + 70 .loc 1 115 0 + 71 .thumb + 72 0034 40F20002 movw r2, #:lower16:ch_debug + 73 0038 DB69 ldr r3, [r3, #28] + 74 003a C0F20002 movt r2, #:upper16:ch_debug + 75 003e 9A61 str r2, [r3, #24] + 76 0040 08BD pop {r3, pc} + 77 .cfi_endproc + 78 .LFE7: + 79 .size chSysInit, .-chSysInit + 80 0042 00BFAFF3 .section .text.chSysTimerHandlerI,"ax",%progbits + 80 0080AFF3 + 80 0080AFF3 + 80 0080 + 81 .align 2 + 82 .p2align 4,,15 + 83 .global chSysTimerHandlerI + 84 .thumb + 85 .thumb_func + 86 .type chSysTimerHandlerI, %function + 87 chSysTimerHandlerI: + 88 .LFB8: + 89 .loc 1 137 0 + 90 .cfi_startproc + 91 @ args = 0, pretend = 0, frame = 0 + 92 @ frame_needed = 0, uses_anonymous_args = 0 + 93 0000 38B5 push {r3, r4, r5, lr} + 94 .LCFI1: + 95 .cfi_def_cfa_offset 16 + 96 .cfi_offset 3, -16 + 97 .cfi_offset 4, -12 + 98 .cfi_offset 5, -8 + 99 .cfi_offset 14, -4 + 100 .loc 1 143 0 + 101 0002 104B ldr r3, .L13 + 102 0004 9A69 ldr r2, [r3, #24] + 103 0006 002A cmp r2, #0 + 104 0008 01DD ble .L3 + 105 .loc 1 145 0 + 106 000a 013A subs r2, r2, #1 + 107 000c 9A61 str r2, [r3, #24] + 108 .L3: + 109 .loc 1 148 0 + 110 000e DA69 ldr r2, [r3, #28] + 111 .loc 1 150 0 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 3 + + + 112 0010 0D4C ldr r4, .L13+4 + 113 .loc 1 148 0 + 114 0012 116A ldr r1, [r2, #32] + 115 .loc 1 150 0 + 116 0014 2368 ldr r3, [r4, #0] + 117 .loc 1 148 0 + 118 0016 0131 adds r1, r1, #1 + 119 0018 1162 str r1, [r2, #32] + 120 .loc 1 150 0 + 121 001a E268 ldr r2, [r4, #12] + 122 001c 0132 adds r2, r2, #1 + 123 001e A342 cmp r3, r4 + 124 0020 E260 str r2, [r4, #12] + 125 0022 0ED0 beq .L2 + 126 .LBB2: + 127 .loc 1 150 0 is_stmt 0 discriminator 1 + 128 0024 9D68 ldr r5, [r3, #8] + 129 0026 013D subs r5, r5, #1 + 130 0028 9D60 str r5, [r3, #8] + 131 .LVL6: + 132 002a 55B9 cbnz r5, .L2 + 133 .L9: + 134 .LBB3: + 135 .loc 1 150 0 discriminator 3 + 136 002c 1A68 ldr r2, [r3, #0] + 137 002e D968 ldr r1, [r3, #12] + 138 .LVL7: + 139 0030 1869 ldr r0, [r3, #16] + 140 0032 DD60 str r5, [r3, #12] + 141 0034 5460 str r4, [r2, #4] + 142 0036 2260 str r2, [r4, #0] + 143 0038 8847 blx r1 + 144 .LVL8: + 145 .LBE3: + 146 003a 2368 ldr r3, [r4, #0] + 147 .LVL9: + 148 003c 9A68 ldr r2, [r3, #8] + 149 003e 002A cmp r2, #0 + 150 0040 F4D0 beq .L9 + 151 .LVL10: + 152 .L2: + 153 0042 38BD pop {r3, r4, r5, pc} + 154 .L14: + 155 .align 2 + 156 .L13: + 157 0044 00000000 .word rlist + 158 0048 00000000 .word vtlist + 159 .LBE2: + 160 .cfi_endproc + 161 .LFE8: + 162 .size chSysTimerHandlerI, .-chSysTimerHandlerI + 163 004c AFF30080 .section .bss.mainthread.4814,"aw",%nobits + 164 .align 2 + 165 .set .LANCHOR0,. + 0 + 166 .type mainthread.4814, %object + 167 .size mainthread.4814, 72 + 168 mainthread.4814: + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 4 + + + 169 0000 00000000 .space 72 + 169 00000000 + 169 00000000 + 169 00000000 + 169 00000000 + 170 .text + 171 .Letext0: + 172 .file 2 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 173 .file 3 "../..//os/ports/GCC/ARMCMx/chtypes.h" + 174 .file 4 "../..//os/kernel/include/chlists.h" + 175 .file 5 "../..//os/kernel/include/chthreads.h" + 176 .file 6 "../..//os/ports/GCC/ARMCMx/chcore_v7m.h" + 177 .file 7 "../..//os/kernel/include/chvt.h" + 178 .file 8 "../..//os/kernel/include/chschd.h" + 179 .file 9 "../..//os/kernel/include/chmtx.h" + 180 .file 10 "../..//os/kernel/include/chregistry.h" + 181 .file 11 "../..//os/kernel/include/chmemcore.h" + 182 .file 12 "../..//os/kernel/include/chheap.h" + 183 .section .debug_info,"",%progbits + 184 .Ldebug_info0: + 185 0000 62070000 .4byte 0x762 + 186 0004 0200 .2byte 0x2 + 187 0006 00000000 .4byte .Ldebug_abbrev0 + 188 000a 04 .byte 0x4 + 189 000b 01 .uleb128 0x1 + 190 000c 8D020000 .4byte .LASF102 + 191 0010 01 .byte 0x1 + 192 0011 6D000000 .4byte .LASF103 + 193 0015 35020000 .4byte .LASF104 + 194 0019 00000000 .4byte .Ldebug_ranges0+0 + 195 001d 00000000 .4byte 0 + 196 0021 00000000 .4byte 0 + 197 0025 00000000 .4byte .Ldebug_line0 + 198 0029 02 .uleb128 0x2 + 199 002a 04 .byte 0x4 + 200 002b 05 .byte 0x5 + 201 002c 696E7400 .ascii "int\000" + 202 0030 03 .uleb128 0x3 + 203 0031 04 .byte 0x4 + 204 0032 07 .byte 0x7 + 205 0033 64010000 .4byte .LASF0 + 206 0037 03 .uleb128 0x3 + 207 0038 01 .byte 0x1 + 208 0039 06 .byte 0x6 + 209 003a BC000000 .4byte .LASF1 + 210 003e 04 .uleb128 0x4 + 211 003f 06040000 .4byte .LASF4 + 212 0043 02 .byte 0x2 + 213 0044 2A .byte 0x2a + 214 0045 49000000 .4byte 0x49 + 215 0049 03 .uleb128 0x3 + 216 004a 01 .byte 0x1 + 217 004b 08 .byte 0x8 + 218 004c D5020000 .4byte .LASF2 + 219 0050 03 .uleb128 0x3 + 220 0051 02 .byte 0x2 + 221 0052 05 .byte 0x5 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 5 + + + 222 0053 F8020000 .4byte .LASF3 + 223 0057 04 .uleb128 0x4 + 224 0058 15010000 .4byte .LASF5 + 225 005c 02 .byte 0x2 + 226 005d 36 .byte 0x36 + 227 005e 62000000 .4byte 0x62 + 228 0062 03 .uleb128 0x3 + 229 0063 02 .byte 0x2 + 230 0064 07 .byte 0x7 + 231 0065 A9010000 .4byte .LASF6 + 232 0069 04 .uleb128 0x4 + 233 006a CD020000 .4byte .LASF7 + 234 006e 02 .byte 0x2 + 235 006f 4F .byte 0x4f + 236 0070 74000000 .4byte 0x74 + 237 0074 03 .uleb128 0x3 + 238 0075 04 .byte 0x4 + 239 0076 05 .byte 0x5 + 240 0077 03010000 .4byte .LASF8 + 241 007b 04 .uleb128 0x4 + 242 007c 61030000 .4byte .LASF9 + 243 0080 02 .byte 0x2 + 244 0081 50 .byte 0x50 + 245 0082 86000000 .4byte 0x86 + 246 0086 03 .uleb128 0x3 + 247 0087 04 .byte 0x4 + 248 0088 07 .byte 0x7 + 249 0089 86010000 .4byte .LASF10 + 250 008d 03 .uleb128 0x3 + 251 008e 08 .byte 0x8 + 252 008f 05 .byte 0x5 + 253 0090 AE000000 .4byte .LASF11 + 254 0094 03 .uleb128 0x3 + 255 0095 08 .byte 0x8 + 256 0096 07 .byte 0x7 + 257 0097 34000000 .4byte .LASF12 + 258 009b 04 .uleb128 0x4 + 259 009c C2010000 .4byte .LASF13 + 260 00a0 03 .byte 0x3 + 261 00a1 2F .byte 0x2f + 262 00a2 3E000000 .4byte 0x3e + 263 00a6 04 .uleb128 0x4 + 264 00a7 0C010000 .4byte .LASF14 + 265 00ab 03 .byte 0x3 + 266 00ac 30 .byte 0x30 + 267 00ad 3E000000 .4byte 0x3e + 268 00b1 04 .uleb128 0x4 + 269 00b2 AB020000 .4byte .LASF15 + 270 00b6 03 .byte 0x3 + 271 00b7 31 .byte 0x31 + 272 00b8 3E000000 .4byte 0x3e + 273 00bc 04 .uleb128 0x4 + 274 00bd C5020000 .4byte .LASF16 + 275 00c1 03 .byte 0x3 + 276 00c2 32 .byte 0x32 + 277 00c3 7B000000 .4byte 0x7b + 278 00c7 04 .uleb128 0x4 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 6 + + + 279 00c8 BC010000 .4byte .LASF17 + 280 00cc 03 .byte 0x3 + 281 00cd 33 .byte 0x33 + 282 00ce 69000000 .4byte 0x69 + 283 00d2 04 .uleb128 0x4 + 284 00d3 D6010000 .4byte .LASF18 + 285 00d7 03 .byte 0x3 + 286 00d8 35 .byte 0x35 + 287 00d9 7B000000 .4byte 0x7b + 288 00dd 04 .uleb128 0x4 + 289 00de 97030000 .4byte .LASF19 + 290 00e2 03 .byte 0x3 + 291 00e3 36 .byte 0x36 + 292 00e4 7B000000 .4byte 0x7b + 293 00e8 04 .uleb128 0x4 + 294 00e9 5E010000 .4byte .LASF20 + 295 00ed 03 .byte 0x3 + 296 00ee 37 .byte 0x37 + 297 00ef 69000000 .4byte 0x69 + 298 00f3 04 .uleb128 0x4 + 299 00f4 42030000 .4byte .LASF21 + 300 00f8 04 .byte 0x4 + 301 00f9 2A .byte 0x2a + 302 00fa FE000000 .4byte 0xfe + 303 00fe 05 .uleb128 0x5 + 304 00ff 42030000 .4byte .LASF21 + 305 0103 48 .byte 0x48 + 306 0104 05 .byte 0x5 + 307 0105 5E .byte 0x5e + 308 0106 15020000 .4byte 0x215 + 309 010a 06 .uleb128 0x6 + 310 010b 24030000 .4byte .LASF22 + 311 010f 05 .byte 0x5 + 312 0110 5F .byte 0x5f + 313 0111 3A020000 .4byte 0x23a + 314 0115 02 .byte 0x2 + 315 0116 23 .byte 0x23 + 316 0117 00 .uleb128 0 + 317 0118 06 .uleb128 0x6 + 318 0119 BE020000 .4byte .LASF23 + 319 011d 05 .byte 0x5 + 320 011e 61 .byte 0x61 + 321 011f 3A020000 .4byte 0x23a + 322 0123 02 .byte 0x2 + 323 0124 23 .byte 0x23 + 324 0125 04 .uleb128 0x4 + 325 0126 06 .uleb128 0x6 + 326 0127 8A000000 .4byte .LASF24 + 327 012b 05 .byte 0x5 + 328 012c 63 .byte 0x63 + 329 012d BC000000 .4byte 0xbc + 330 0131 02 .byte 0x2 + 331 0132 23 .byte 0x23 + 332 0133 08 .uleb128 0x8 + 333 0134 06 .uleb128 0x6 + 334 0135 56040000 .4byte .LASF25 + 335 0139 05 .byte 0x5 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 7 + + + 336 013a 64 .byte 0x64 + 337 013b 07030000 .4byte 0x307 + 338 013f 02 .byte 0x2 + 339 0140 23 .byte 0x23 + 340 0141 0C .uleb128 0xc + 341 0142 06 .uleb128 0x6 + 342 0143 28010000 .4byte .LASF26 + 343 0147 05 .byte 0x5 + 344 0148 66 .byte 0x66 + 345 0149 3A020000 .4byte 0x23a + 346 014d 02 .byte 0x2 + 347 014e 23 .byte 0x23 + 348 014f 10 .uleb128 0x10 + 349 0150 06 .uleb128 0x6 + 350 0151 2D020000 .4byte .LASF27 + 351 0155 05 .byte 0x5 + 352 0156 67 .byte 0x67 + 353 0157 3A020000 .4byte 0x23a + 354 015b 02 .byte 0x2 + 355 015c 23 .byte 0x23 + 356 015d 14 .uleb128 0x14 + 357 015e 06 .uleb128 0x6 + 358 015f 20040000 .4byte .LASF28 + 359 0163 05 .byte 0x5 + 360 0164 6E .byte 0x6e + 361 0165 F6040000 .4byte 0x4f6 + 362 0169 02 .byte 0x2 + 363 016a 23 .byte 0x23 + 364 016b 18 .uleb128 0x18 + 365 016c 06 .uleb128 0x6 + 366 016d 02030000 .4byte .LASF29 + 367 0171 05 .byte 0x5 + 368 0172 79 .byte 0x79 + 369 0173 A6000000 .4byte 0xa6 + 370 0177 02 .byte 0x2 + 371 0178 23 .byte 0x23 + 372 0179 1C .uleb128 0x1c + 373 017a 06 .uleb128 0x6 + 374 017b 3A030000 .4byte .LASF30 + 375 017f 05 .byte 0x5 + 376 0180 7D .byte 0x7d + 377 0181 9B000000 .4byte 0x9b + 378 0185 02 .byte 0x2 + 379 0186 23 .byte 0x23 + 380 0187 1D .uleb128 0x1d + 381 0188 06 .uleb128 0x6 + 382 0189 EF030000 .4byte .LASF31 + 383 018d 05 .byte 0x5 + 384 018e 82 .byte 0x82 + 385 018f B1000000 .4byte 0xb1 + 386 0193 02 .byte 0x2 + 387 0194 23 .byte 0x23 + 388 0195 1E .uleb128 0x1e + 389 0196 06 .uleb128 0x6 + 390 0197 BE030000 .4byte .LASF32 + 391 019b 05 .byte 0x5 + 392 019c 89 .byte 0x89 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 8 + + + 393 019d F3030000 .4byte 0x3f3 + 394 01a1 02 .byte 0x2 + 395 01a2 23 .byte 0x23 + 396 01a3 20 .uleb128 0x20 + 397 01a4 07 .uleb128 0x7 + 398 01a5 705F7500 .ascii "p_u\000" + 399 01a9 05 .byte 0x5 + 400 01aa AE .byte 0xae + 401 01ab C1040000 .4byte 0x4c1 + 402 01af 02 .byte 0x2 + 403 01b0 23 .byte 0x23 + 404 01b1 24 .uleb128 0x24 + 405 01b2 06 .uleb128 0x6 + 406 01b3 5C040000 .4byte .LASF33 + 407 01b7 05 .byte 0x5 + 408 01b8 B3 .byte 0xb3 + 409 01b9 62020000 .4byte 0x262 + 410 01bd 02 .byte 0x2 + 411 01be 23 .byte 0x23 + 412 01bf 28 .uleb128 0x28 + 413 01c0 06 .uleb128 0x6 + 414 01c1 D2030000 .4byte .LASF34 + 415 01c5 05 .byte 0x5 + 416 01c6 B9 .byte 0xb9 + 417 01c7 40020000 .4byte 0x240 + 418 01cb 02 .byte 0x2 + 419 01cc 23 .byte 0x23 + 420 01cd 2C .uleb128 0x2c + 421 01ce 06 .uleb128 0x6 + 422 01cf 0D000000 .4byte .LASF35 + 423 01d3 05 .byte 0x5 + 424 01d4 BD .byte 0xbd + 425 01d5 C7000000 .4byte 0xc7 + 426 01d9 02 .byte 0x2 + 427 01da 23 .byte 0x23 + 428 01db 34 .uleb128 0x34 + 429 01dc 06 .uleb128 0x6 + 430 01dd 56030000 .4byte .LASF36 + 431 01e1 05 .byte 0x5 + 432 01e2 C3 .byte 0xc3 + 433 01e3 D2000000 .4byte 0xd2 + 434 01e7 02 .byte 0x2 + 435 01e8 23 .byte 0x23 + 436 01e9 38 .uleb128 0x38 + 437 01ea 06 .uleb128 0x6 + 438 01eb EE020000 .4byte .LASF37 + 439 01ef 05 .byte 0x5 + 440 01f0 CA .byte 0xca + 441 01f1 08050000 .4byte 0x508 + 442 01f5 02 .byte 0x2 + 443 01f6 23 .byte 0x23 + 444 01f7 3C .uleb128 0x3c + 445 01f8 06 .uleb128 0x6 + 446 01f9 A1030000 .4byte .LASF38 + 447 01fd 05 .byte 0x5 + 448 01fe CE .byte 0xce + 449 01ff BC000000 .4byte 0xbc + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 9 + + + 450 0203 02 .byte 0x2 + 451 0204 23 .byte 0x23 + 452 0205 40 .uleb128 0x40 + 453 0206 06 .uleb128 0x6 + 454 0207 E5000000 .4byte .LASF39 + 455 020b 05 .byte 0x5 + 456 020c D4 .byte 0xd4 + 457 020d 78020000 .4byte 0x278 + 458 0211 02 .byte 0x2 + 459 0212 23 .byte 0x23 + 460 0213 44 .uleb128 0x44 + 461 0214 00 .byte 0 + 462 0215 08 .uleb128 0x8 + 463 0216 08 .byte 0x8 + 464 0217 04 .byte 0x4 + 465 0218 61 .byte 0x61 + 466 0219 3A020000 .4byte 0x23a + 467 021d 06 .uleb128 0x6 + 468 021e 24030000 .4byte .LASF22 + 469 0222 04 .byte 0x4 + 470 0223 62 .byte 0x62 + 471 0224 3A020000 .4byte 0x23a + 472 0228 02 .byte 0x2 + 473 0229 23 .byte 0x23 + 474 022a 00 .uleb128 0 + 475 022b 06 .uleb128 0x6 + 476 022c BE020000 .4byte .LASF23 + 477 0230 04 .byte 0x4 + 478 0231 64 .byte 0x64 + 479 0232 3A020000 .4byte 0x23a + 480 0236 02 .byte 0x2 + 481 0237 23 .byte 0x23 + 482 0238 04 .uleb128 0x4 + 483 0239 00 .byte 0 + 484 023a 09 .uleb128 0x9 + 485 023b 04 .byte 0x4 + 486 023c F3000000 .4byte 0xf3 + 487 0240 04 .uleb128 0x4 + 488 0241 78020000 .4byte .LASF40 + 489 0245 04 .byte 0x4 + 490 0246 66 .byte 0x66 + 491 0247 15020000 .4byte 0x215 + 492 024b 08 .uleb128 0x8 + 493 024c 04 .byte 0x4 + 494 024d 04 .byte 0x4 + 495 024e 6B .byte 0x6b + 496 024f 62020000 .4byte 0x262 + 497 0253 06 .uleb128 0x6 + 498 0254 24030000 .4byte .LASF22 + 499 0258 04 .byte 0x4 + 500 0259 6D .byte 0x6d + 501 025a 3A020000 .4byte 0x23a + 502 025e 02 .byte 0x2 + 503 025f 23 .byte 0x23 + 504 0260 00 .uleb128 0 + 505 0261 00 .byte 0 + 506 0262 04 .uleb128 0x4 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 10 + + + 507 0263 CA010000 .4byte .LASF41 + 508 0267 04 .byte 0x4 + 509 0268 70 .byte 0x70 + 510 0269 4B020000 .4byte 0x24b + 511 026d 04 .uleb128 0x4 + 512 026e 38010000 .4byte .LASF42 + 513 0272 06 .byte 0x6 + 514 0273 D7 .byte 0xd7 + 515 0274 78020000 .4byte 0x278 + 516 0278 0A .uleb128 0xa + 517 0279 04 .byte 0x4 + 518 027a 05 .uleb128 0x5 + 519 027b CB030000 .4byte .LASF43 + 520 027f 24 .byte 0x24 + 521 0280 06 .byte 0x6 + 522 0281 FE .byte 0xfe + 523 0282 07030000 .4byte 0x307 + 524 0286 0B .uleb128 0xb + 525 0287 723400 .ascii "r4\000" + 526 028a 06 .byte 0x6 + 527 028b 1101 .2byte 0x111 + 528 028d 6D020000 .4byte 0x26d + 529 0291 02 .byte 0x2 + 530 0292 23 .byte 0x23 + 531 0293 00 .uleb128 0 + 532 0294 0B .uleb128 0xb + 533 0295 723500 .ascii "r5\000" + 534 0298 06 .byte 0x6 + 535 0299 1201 .2byte 0x112 + 536 029b 6D020000 .4byte 0x26d + 537 029f 02 .byte 0x2 + 538 02a0 23 .byte 0x23 + 539 02a1 04 .uleb128 0x4 + 540 02a2 0B .uleb128 0xb + 541 02a3 723600 .ascii "r6\000" + 542 02a6 06 .byte 0x6 + 543 02a7 1301 .2byte 0x113 + 544 02a9 6D020000 .4byte 0x26d + 545 02ad 02 .byte 0x2 + 546 02ae 23 .byte 0x23 + 547 02af 08 .uleb128 0x8 + 548 02b0 0B .uleb128 0xb + 549 02b1 723700 .ascii "r7\000" + 550 02b4 06 .byte 0x6 + 551 02b5 1401 .2byte 0x114 + 552 02b7 6D020000 .4byte 0x26d + 553 02bb 02 .byte 0x2 + 554 02bc 23 .byte 0x23 + 555 02bd 0C .uleb128 0xc + 556 02be 0B .uleb128 0xb + 557 02bf 723800 .ascii "r8\000" + 558 02c2 06 .byte 0x6 + 559 02c3 1501 .2byte 0x115 + 560 02c5 6D020000 .4byte 0x26d + 561 02c9 02 .byte 0x2 + 562 02ca 23 .byte 0x23 + 563 02cb 10 .uleb128 0x10 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 11 + + + 564 02cc 0B .uleb128 0xb + 565 02cd 723900 .ascii "r9\000" + 566 02d0 06 .byte 0x6 + 567 02d1 1601 .2byte 0x116 + 568 02d3 6D020000 .4byte 0x26d + 569 02d7 02 .byte 0x2 + 570 02d8 23 .byte 0x23 + 571 02d9 14 .uleb128 0x14 + 572 02da 0B .uleb128 0xb + 573 02db 72313000 .ascii "r10\000" + 574 02df 06 .byte 0x6 + 575 02e0 1701 .2byte 0x117 + 576 02e2 6D020000 .4byte 0x26d + 577 02e6 02 .byte 0x2 + 578 02e7 23 .byte 0x23 + 579 02e8 18 .uleb128 0x18 + 580 02e9 0B .uleb128 0xb + 581 02ea 72313100 .ascii "r11\000" + 582 02ee 06 .byte 0x6 + 583 02ef 1801 .2byte 0x118 + 584 02f1 6D020000 .4byte 0x26d + 585 02f5 02 .byte 0x2 + 586 02f6 23 .byte 0x23 + 587 02f7 1C .uleb128 0x1c + 588 02f8 0B .uleb128 0xb + 589 02f9 6C7200 .ascii "lr\000" + 590 02fc 06 .byte 0x6 + 591 02fd 1901 .2byte 0x119 + 592 02ff 6D020000 .4byte 0x26d + 593 0303 02 .byte 0x2 + 594 0304 23 .byte 0x23 + 595 0305 20 .uleb128 0x20 + 596 0306 00 .byte 0 + 597 0307 0C .uleb128 0xc + 598 0308 A1010000 .4byte .LASF44 + 599 030c 04 .byte 0x4 + 600 030d 06 .byte 0x6 + 601 030e 2301 .2byte 0x123 + 602 0310 24030000 .4byte 0x324 + 603 0314 0B .uleb128 0xb + 604 0315 72313300 .ascii "r13\000" + 605 0319 06 .byte 0x6 + 606 031a 2401 .2byte 0x124 + 607 031c 24030000 .4byte 0x324 + 608 0320 02 .byte 0x2 + 609 0321 23 .byte 0x23 + 610 0322 00 .uleb128 0 + 611 0323 00 .byte 0 + 612 0324 09 .uleb128 0x9 + 613 0325 04 .byte 0x4 + 614 0326 7A020000 .4byte 0x27a + 615 032a 03 .uleb128 0x3 + 616 032b 04 .byte 0x4 + 617 032c 07 .byte 0x7 + 618 032d 04020000 .4byte .LASF45 + 619 0331 04 .uleb128 0x4 + 620 0332 AC030000 .4byte .LASF46 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 12 + + + 621 0336 07 .byte 0x7 + 622 0337 61 .byte 0x61 + 623 0338 3C030000 .4byte 0x33c + 624 033c 09 .uleb128 0x9 + 625 033d 04 .byte 0x4 + 626 033e 42030000 .4byte 0x342 + 627 0342 0D .uleb128 0xd + 628 0343 01 .byte 0x1 + 629 0344 4E030000 .4byte 0x34e + 630 0348 0E .uleb128 0xe + 631 0349 78020000 .4byte 0x278 + 632 034d 00 .byte 0 + 633 034e 04 .uleb128 0x4 + 634 034f 7E030000 .4byte .LASF47 + 635 0353 07 .byte 0x7 + 636 0354 66 .byte 0x66 + 637 0355 59030000 .4byte 0x359 + 638 0359 05 .uleb128 0x5 + 639 035a 7E030000 .4byte .LASF47 + 640 035e 14 .byte 0x14 + 641 035f 07 .byte 0x7 + 642 0360 6D .byte 0x6d + 643 0361 AC030000 .4byte 0x3ac + 644 0365 06 .uleb128 0x6 + 645 0366 7E010000 .4byte .LASF48 + 646 036a 07 .byte 0x7 + 647 036b 6E .byte 0x6e + 648 036c AC030000 .4byte 0x3ac + 649 0370 02 .byte 0x2 + 650 0371 23 .byte 0x23 + 651 0372 00 .uleb128 0 + 652 0373 06 .uleb128 0x6 + 653 0374 41010000 .4byte .LASF49 + 654 0378 07 .byte 0x7 + 655 0379 70 .byte 0x70 + 656 037a AC030000 .4byte 0x3ac + 657 037e 02 .byte 0x2 + 658 037f 23 .byte 0x23 + 659 0380 04 .uleb128 0x4 + 660 0381 06 .uleb128 0x6 + 661 0382 FC010000 .4byte .LASF50 + 662 0386 07 .byte 0x7 + 663 0387 72 .byte 0x72 + 664 0388 DD000000 .4byte 0xdd + 665 038c 02 .byte 0x2 + 666 038d 23 .byte 0x23 + 667 038e 08 .uleb128 0x8 + 668 038f 06 .uleb128 0x6 + 669 0390 0D020000 .4byte .LASF51 + 670 0394 07 .byte 0x7 + 671 0395 73 .byte 0x73 + 672 0396 31030000 .4byte 0x331 + 673 039a 02 .byte 0x2 + 674 039b 23 .byte 0x23 + 675 039c 0C .uleb128 0xc + 676 039d 06 .uleb128 0x6 + 677 039e DD030000 .4byte .LASF52 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 13 + + + 678 03a2 07 .byte 0x7 + 679 03a3 75 .byte 0x75 + 680 03a4 78020000 .4byte 0x278 + 681 03a8 02 .byte 0x2 + 682 03a9 23 .byte 0x23 + 683 03aa 10 .uleb128 0x10 + 684 03ab 00 .byte 0 + 685 03ac 09 .uleb128 0x9 + 686 03ad 04 .byte 0x4 + 687 03ae 4E030000 .4byte 0x34e + 688 03b2 08 .uleb128 0x8 + 689 03b3 10 .byte 0x10 + 690 03b4 07 .byte 0x7 + 691 03b5 7F .byte 0x7f + 692 03b6 F3030000 .4byte 0x3f3 + 693 03ba 06 .uleb128 0x6 + 694 03bb 7E010000 .4byte .LASF48 + 695 03bf 07 .byte 0x7 + 696 03c0 80 .byte 0x80 + 697 03c1 AC030000 .4byte 0x3ac + 698 03c5 02 .byte 0x2 + 699 03c6 23 .byte 0x23 + 700 03c7 00 .uleb128 0 + 701 03c8 06 .uleb128 0x6 + 702 03c9 41010000 .4byte .LASF49 + 703 03cd 07 .byte 0x7 + 704 03ce 82 .byte 0x82 + 705 03cf AC030000 .4byte 0x3ac + 706 03d3 02 .byte 0x2 + 707 03d4 23 .byte 0x23 + 708 03d5 04 .uleb128 0x4 + 709 03d6 06 .uleb128 0x6 + 710 03d7 FC010000 .4byte .LASF50 + 711 03db 07 .byte 0x7 + 712 03dc 84 .byte 0x84 + 713 03dd DD000000 .4byte 0xdd + 714 03e1 02 .byte 0x2 + 715 03e2 23 .byte 0x23 + 716 03e3 08 .uleb128 0x8 + 717 03e4 06 .uleb128 0x6 + 718 03e5 27040000 .4byte .LASF53 + 719 03e9 07 .byte 0x7 + 720 03ea 85 .byte 0x85 + 721 03eb F3030000 .4byte 0x3f3 + 722 03ef 02 .byte 0x2 + 723 03f0 23 .byte 0x23 + 724 03f1 0C .uleb128 0xc + 725 03f2 00 .byte 0 + 726 03f3 0F .uleb128 0xf + 727 03f4 DD000000 .4byte 0xdd + 728 03f8 04 .uleb128 0x4 + 729 03f9 3D040000 .4byte .LASF54 + 730 03fd 07 .byte 0x7 + 731 03fe 86 .byte 0x86 + 732 03ff B2030000 .4byte 0x3b2 + 733 0403 08 .uleb128 0x8 + 734 0404 20 .byte 0x20 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 14 + + + 735 0405 08 .byte 0x8 + 736 0406 5E .byte 0x5e + 737 0407 6E040000 .4byte 0x46e + 738 040b 06 .uleb128 0x6 + 739 040c 76030000 .4byte .LASF55 + 740 0410 08 .byte 0x8 + 741 0411 5F .byte 0x5f + 742 0412 40020000 .4byte 0x240 + 743 0416 02 .byte 0x2 + 744 0417 23 .byte 0x23 + 745 0418 00 .uleb128 0 + 746 0419 06 .uleb128 0x6 + 747 041a 16030000 .4byte .LASF56 + 748 041e 08 .byte 0x8 + 749 041f 60 .byte 0x60 + 750 0420 BC000000 .4byte 0xbc + 751 0424 02 .byte 0x2 + 752 0425 23 .byte 0x23 + 753 0426 08 .uleb128 0x8 + 754 0427 06 .uleb128 0x6 + 755 0428 C5030000 .4byte .LASF57 + 756 042c 08 .byte 0x8 + 757 042d 62 .byte 0x62 + 758 042e 07030000 .4byte 0x307 + 759 0432 02 .byte 0x2 + 760 0433 23 .byte 0x23 + 761 0434 0C .uleb128 0xc + 762 0435 06 .uleb128 0x6 + 763 0436 30010000 .4byte .LASF58 + 764 043a 08 .byte 0x8 + 765 043b 65 .byte 0x65 + 766 043c 3A020000 .4byte 0x23a + 767 0440 02 .byte 0x2 + 768 0441 23 .byte 0x23 + 769 0442 10 .uleb128 0x10 + 770 0443 06 .uleb128 0x6 + 771 0444 A3020000 .4byte .LASF59 + 772 0448 08 .byte 0x8 + 773 0449 66 .byte 0x66 + 774 044a 3A020000 .4byte 0x23a + 775 044e 02 .byte 0x2 + 776 044f 23 .byte 0x23 + 777 0450 14 .uleb128 0x14 + 778 0451 06 .uleb128 0x6 + 779 0452 44040000 .4byte .LASF60 + 780 0456 08 .byte 0x8 + 781 0457 6A .byte 0x6a + 782 0458 E8000000 .4byte 0xe8 + 783 045c 02 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0522 23 .byte 0x23 + 889 0523 00 .uleb128 0 + 890 0524 06 .uleb128 0x6 + 891 0525 E8010000 .4byte .LASF73 + 892 0529 0A .byte 0xa + 893 052a 2E .byte 0x2e + 894 052b 3E000000 .4byte 0x3e + 895 052f 02 .byte 0x2 + 896 0530 23 .byte 0x23 + 897 0531 04 .uleb128 0x4 + 898 0532 06 .uleb128 0x6 + 899 0533 85020000 .4byte .LASF74 + 900 0537 0A .byte 0xa + 901 0538 2F .byte 0x2f + 902 0539 3E000000 .4byte 0x3e + 903 053d 02 .byte 0x2 + 904 053e 23 .byte 0x23 + 905 053f 05 .uleb128 0x5 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 17 + + + 906 0540 06 .uleb128 0x6 + 907 0541 32040000 .4byte .LASF75 + 908 0545 0A .byte 0xa + 909 0546 30 .byte 0x30 + 910 0547 57000000 .4byte 0x57 + 911 054b 02 .byte 0x2 + 912 054c 23 .byte 0x23 + 913 054d 06 .uleb128 0x6 + 914 054e 06 .uleb128 0x6 + 915 054f B3020000 .4byte .LASF76 + 916 0553 0A .byte 0xa + 917 0554 31 .byte 0x31 + 918 0555 3E000000 .4byte 0x3e + 919 0559 02 .byte 0x2 + 920 055a 23 .byte 0x23 + 921 055b 08 .uleb128 0x8 + 922 055c 06 .uleb128 0x6 + 923 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.byte 0x2 + 960 05a0 23 .byte 0x23 + 961 05a1 0D .uleb128 0xd + 962 05a2 06 .uleb128 0x6 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 18 + + + 963 05a3 00000000 .4byte .LASF82 + 964 05a7 0A .byte 0xa + 965 05a8 37 .byte 0x37 + 966 05a9 3E000000 .4byte 0x3e + 967 05ad 02 .byte 0x2 + 968 05ae 23 .byte 0x23 + 969 05af 0E .uleb128 0xe + 970 05b0 06 .uleb128 0x6 + 971 05b1 21020000 .4byte .LASF83 + 972 05b5 0A .byte 0xa + 973 05b6 38 .byte 0x38 + 974 05b7 3E000000 .4byte 0x3e + 975 05bb 02 .byte 0x2 + 976 05bc 23 .byte 0x23 + 977 05bd 0F .uleb128 0xf + 978 05be 06 .uleb128 0x6 + 979 05bf C8000000 .4byte .LASF84 + 980 05c3 0A .byte 0xa + 981 05c4 39 .byte 0x39 + 982 05c5 3E000000 .4byte 0x3e + 983 05c9 02 .byte 0x2 + 984 05ca 23 .byte 0x23 + 985 05cb 10 .uleb128 0x10 + 986 05cc 06 .uleb128 0x6 + 987 05cd 91000000 .4byte .LASF85 + 988 05d1 0A .byte 0xa + 989 05d2 3B .byte 0x3b + 990 05d3 3E000000 .4byte 0x3e + 991 05d7 02 .byte 0x2 + 992 05d8 23 .byte 0x23 + 993 05d9 11 .uleb128 0x11 + 994 05da 06 .uleb128 0x6 + 995 05db D8000000 .4byte .LASF86 + 996 05df 0A .byte 0xa + 997 05e0 3C .byte 0x3c + 998 05e1 3E000000 .4byte 0x3e + 999 05e5 02 .byte 0x2 + 1000 05e6 23 .byte 0x23 + 1001 05e7 12 .uleb128 0x12 + 1002 05e8 06 .uleb128 0x6 + 1003 05e9 F0010000 .4byte .LASF87 + 1004 05ed 0A .byte 0xa + 1005 05ee 3D .byte 0x3d + 1006 05ef 3E000000 .4byte 0x3e + 1007 05f3 02 .byte 0x2 + 1008 05f4 23 .byte 0x23 + 1009 05f5 13 .uleb128 0x13 + 1010 05f6 06 .uleb128 0x6 + 1011 05f7 2B030000 .4byte .LASF88 + 1012 05fb 0A .byte 0xa + 1013 05fc 3E .byte 0x3e + 1014 05fd 3E000000 .4byte 0x3e + 1015 0601 02 .byte 0x2 + 1016 0602 23 .byte 0x23 + 1017 0603 14 .uleb128 0x14 + 1018 0604 06 .uleb128 0x6 + 1019 0605 0A030000 .4byte .LASF89 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 19 + + + 1020 0609 0A .byte 0xa + 1021 060a 40 .byte 0x40 + 1022 060b 3E000000 .4byte 0x3e + 1023 060f 02 .byte 0x2 + 1024 0610 23 .byte 0x23 + 1025 0611 15 .uleb128 0x15 + 1026 0612 00 .byte 0 + 1027 0613 13 .uleb128 0x13 + 1028 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17 .uleb128 0x17 + 1062 0663 0A000000 .4byte .LVL1 + 1063 0667 23070000 .4byte 0x723 + 1064 066b 17 .uleb128 0x17 + 1065 066c 0E000000 .4byte .LVL2 + 1066 0670 2D070000 .4byte 0x72d + 1067 0674 17 .uleb128 0x17 + 1068 0675 12000000 .4byte .LVL3 + 1069 0679 37070000 .4byte 0x737 + 1070 067d 17 .uleb128 0x17 + 1071 067e 16000000 .4byte .LVL4 + 1072 0682 41070000 .4byte 0x741 + 1073 0686 18 .uleb128 0x18 + 1074 0687 24000000 .4byte .LVL5 + 1075 068b 4B070000 .4byte 0x74b + 1076 068f 19 .uleb128 0x19 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 20 + + + 1077 0690 01 .byte 0x1 + 1078 0691 51 .byte 0x51 + 1079 0692 02 .byte 0x2 + 1080 0693 08 .byte 0x8 + 1081 0694 40 .byte 0x40 + 1082 0695 19 .uleb128 0x19 + 1083 0696 01 .byte 0x1 + 1084 0697 50 .byte 0x50 + 1085 0698 05 .byte 0x5 + 1086 0699 03 .byte 0x3 + 1087 069a 00000000 .4byte .LANCHOR0 + 1088 069e 00 .byte 0 + 1089 069f 00 .byte 0 + 1090 06a0 1A .uleb128 0x1a + 1091 06a1 01 .byte 0x1 + 1092 06a2 21000000 .4byte .LASF92 + 1093 06a6 01 .byte 0x1 + 1094 06a7 89 .byte 0x89 + 1095 06a8 01 .byte 0x1 + 1096 06a9 00000000 .4byte .LFB8 + 1097 06ad 4C000000 .4byte .LFE8 + 1098 06b1 20000000 .4byte .LLST1 + 1099 06b5 01 .byte 0x1 + 1100 06b6 EC060000 .4byte 0x6ec + 1101 06ba 1B .uleb128 0x1b + 1102 06bb 24000000 .4byte .LBB2 + 1103 06bf 4C000000 .4byte .LBE2 + 1104 06c3 1C .uleb128 0x1c + 1105 06c4 76747000 .ascii "vtp\000" + 1106 06c8 01 .byte 0x1 + 1107 06c9 96 .byte 0x96 + 1108 06ca AC030000 .4byte 0x3ac + 1109 06ce 40000000 .4byte .LLST2 + 1110 06d2 1B .uleb128 0x1b + 1111 06d3 2C000000 .4byte .LBB3 + 1112 06d7 3A000000 .4byte .LBE3 + 1113 06db 1C .uleb128 0x1c + 1114 06dc 666E00 .ascii "fn\000" + 1115 06df 01 .byte 0x1 + 1116 06e0 96 .byte 0x96 + 1117 06e1 31030000 .4byte 0x331 + 1118 06e5 5E000000 .4byte .LLST3 + 1119 06e9 00 .byte 0 + 1120 06ea 00 .byte 0 + 1121 06eb 00 .byte 0 + 1122 06ec 1D .uleb128 0x1d + 1123 06ed 1A000000 .4byte .LASF94 + 1124 06f1 07 .byte 0x7 + 1125 06f2 88 .byte 0x88 + 1126 06f3 F8030000 .4byte 0x3f8 + 1127 06f7 01 .byte 0x1 + 1128 06f8 01 .byte 0x1 + 1129 06f9 1D .uleb128 0x1d + 1130 06fa 00040000 .4byte .LASF95 + 1131 06fe 08 .byte 0x8 + 1132 06ff 72 .byte 0x72 + 1133 0700 6E040000 .4byte 0x46e + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 21 + + + 1134 0704 01 .byte 0x1 + 1135 0705 01 .byte 0x1 + 1136 0706 1D .uleb128 0x1d + 1137 0707 98010000 .4byte .LASF96 + 1138 070b 0A .byte 0xa + 1139 070c 7E .byte 0x7e + 1140 070d 13070000 .4byte 0x713 + 1141 0711 01 .byte 0x1 + 1142 0712 01 .byte 0x1 + 1143 0713 12 .uleb128 0x12 + 1144 0714 23060000 .4byte 0x623 + 1145 0718 1E .uleb128 0x1e + 1146 0719 01 .byte 0x1 + 1147 071a 15040000 .4byte .LASF97 + 1148 071e 06 .byte 0x6 + 1149 071f F401 .2byte 0x1f4 + 1150 0721 01 .byte 0x1 + 1151 0722 01 .byte 0x1 + 1152 0723 1F .uleb128 0x1f + 1153 0724 01 .byte 0x1 + 1154 0725 9E000000 .4byte .LASF98 + 1155 0729 08 .byte 0x8 + 1156 072a 91 .byte 0x91 + 1157 072b 01 .byte 0x1 + 1158 072c 01 .byte 0x1 + 1159 072d 1F .uleb128 0x1f + 1160 072e 01 .byte 0x1 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.debug_abbrev,"",%progbits + 1195 .Ldebug_abbrev0: + 1196 0000 01 .uleb128 0x1 + 1197 0001 11 .uleb128 0x11 + 1198 0002 01 .byte 0x1 + 1199 0003 25 .uleb128 0x25 + 1200 0004 0E .uleb128 0xe + 1201 0005 13 .uleb128 0x13 + 1202 0006 0B .uleb128 0xb + 1203 0007 03 .uleb128 0x3 + 1204 0008 0E .uleb128 0xe + 1205 0009 1B .uleb128 0x1b + 1206 000a 0E .uleb128 0xe + 1207 000b 55 .uleb128 0x55 + 1208 000c 06 .uleb128 0x6 + 1209 000d 11 .uleb128 0x11 + 1210 000e 01 .uleb128 0x1 + 1211 000f 52 .uleb128 0x52 + 1212 0010 01 .uleb128 0x1 + 1213 0011 10 .uleb128 0x10 + 1214 0012 06 .uleb128 0x6 + 1215 0013 00 .byte 0 + 1216 0014 00 .byte 0 + 1217 0015 02 .uleb128 0x2 + 1218 0016 24 .uleb128 0x24 + 1219 0017 00 .byte 0 + 1220 0018 0B .uleb128 0xb + 1221 0019 0B .uleb128 0xb + 1222 001a 3E .uleb128 0x3e + 1223 001b 0B .uleb128 0xb + 1224 001c 03 .uleb128 0x3 + 1225 001d 08 .uleb128 0x8 + 1226 001e 00 .byte 0 + 1227 001f 00 .byte 0 + 1228 0020 03 .uleb128 0x3 + 1229 0021 24 .uleb128 0x24 + 1230 0022 00 .byte 0 + 1231 0023 0B .uleb128 0xb + 1232 0024 0B .uleb128 0xb + 1233 0025 3E .uleb128 0x3e + 1234 0026 0B .uleb128 0xb + 1235 0027 03 .uleb128 0x3 + 1236 0028 0E .uleb128 0xe + 1237 0029 00 .byte 0 + 1238 002a 00 .byte 0 + 1239 002b 04 .uleb128 0x4 + 1240 002c 16 .uleb128 0x16 + 1241 002d 00 .byte 0 + 1242 002e 03 .uleb128 0x3 + 1243 002f 0E .uleb128 0xe + 1244 0030 3A .uleb128 0x3a + 1245 0031 0B .uleb128 0xb + 1246 0032 3B .uleb128 0x3b + 1247 0033 0B .uleb128 0xb + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 23 + + + 1248 0034 49 .uleb128 0x49 + 1249 0035 13 .uleb128 0x13 + 1250 0036 00 .byte 0 + 1251 0037 00 .byte 0 + 1252 0038 05 .uleb128 0x5 + 1253 0039 13 .uleb128 0x13 + 1254 003a 01 .byte 0x1 + 1255 003b 03 .uleb128 0x3 + 1256 003c 0E .uleb128 0xe + 1257 003d 0B .uleb128 0xb + 1258 003e 0B .uleb128 0xb + 1259 003f 3A .uleb128 0x3a + 1260 0040 0B .uleb128 0xb + 1261 0041 3B .uleb128 0x3b + 1262 0042 0B .uleb128 0xb + 1263 0043 01 .uleb128 0x1 + 1264 0044 13 .uleb128 0x13 + 1265 0045 00 .byte 0 + 1266 0046 00 .byte 0 + 1267 0047 06 .uleb128 0x6 + 1268 0048 0D .uleb128 0xd + 1269 0049 00 .byte 0 + 1270 004a 03 .uleb128 0x3 + 1271 004b 0E .uleb128 0xe + 1272 004c 3A .uleb128 0x3a + 1273 004d 0B .uleb128 0xb + 1274 004e 3B .uleb128 0x3b + 1275 004f 0B .uleb128 0xb + 1276 0050 49 .uleb128 0x49 + 1277 0051 13 .uleb128 0x13 + 1278 0052 38 .uleb128 0x38 + 1279 0053 0A .uleb128 0xa + 1280 0054 00 .byte 0 + 1281 0055 00 .byte 0 + 1282 0056 07 .uleb128 0x7 + 1283 0057 0D .uleb128 0xd + 1284 0058 00 .byte 0 + 1285 0059 03 .uleb128 0x3 + 1286 005a 08 .uleb128 0x8 + 1287 005b 3A .uleb128 0x3a + 1288 005c 0B .uleb128 0xb + 1289 005d 3B .uleb128 0x3b + 1290 005e 0B .uleb128 0xb + 1291 005f 49 .uleb128 0x49 + 1292 0060 13 .uleb128 0x13 + 1293 0061 38 .uleb128 0x38 + 1294 0062 0A .uleb128 0xa + 1295 0063 00 .byte 0 + 1296 0064 00 .byte 0 + 1297 0065 08 .uleb128 0x8 + 1298 0066 13 .uleb128 0x13 + 1299 0067 01 .byte 0x1 + 1300 0068 0B .uleb128 0xb + 1301 0069 0B .uleb128 0xb + 1302 006a 3A .uleb128 0x3a + 1303 006b 0B .uleb128 0xb + 1304 006c 3B .uleb128 0x3b + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 24 + + + 1305 006d 0B .uleb128 0xb + 1306 006e 01 .uleb128 0x1 + 1307 006f 13 .uleb128 0x13 + 1308 0070 00 .byte 0 + 1309 0071 00 .byte 0 + 1310 0072 09 .uleb128 0x9 + 1311 0073 0F .uleb128 0xf + 1312 0074 00 .byte 0 + 1313 0075 0B .uleb128 0xb + 1314 0076 0B .uleb128 0xb + 1315 0077 49 .uleb128 0x49 + 1316 0078 13 .uleb128 0x13 + 1317 0079 00 .byte 0 + 1318 007a 00 .byte 0 + 1319 007b 0A .uleb128 0xa + 1320 007c 0F .uleb128 0xf + 1321 007d 00 .byte 0 + 1322 007e 0B .uleb128 0xb + 1323 007f 0B .uleb128 0xb + 1324 0080 00 .byte 0 + 1325 0081 00 .byte 0 + 1326 0082 0B .uleb128 0xb + 1327 0083 0D .uleb128 0xd + 1328 0084 00 .byte 0 + 1329 0085 03 .uleb128 0x3 + 1330 0086 08 .uleb128 0x8 + 1331 0087 3A .uleb128 0x3a + 1332 0088 0B .uleb128 0xb + 1333 0089 3B .uleb128 0x3b + 1334 008a 05 .uleb128 0x5 + 1335 008b 49 .uleb128 0x49 + 1336 008c 13 .uleb128 0x13 + 1337 008d 38 .uleb128 0x38 + 1338 008e 0A .uleb128 0xa + 1339 008f 00 .byte 0 + 1340 0090 00 .byte 0 + 1341 0091 0C .uleb128 0xc + 1342 0092 13 .uleb128 0x13 + 1343 0093 01 .byte 0x1 + 1344 0094 03 .uleb128 0x3 + 1345 0095 0E .uleb128 0xe + 1346 0096 0B .uleb128 0xb + 1347 0097 0B .uleb128 0xb + 1348 0098 3A .uleb128 0x3a + 1349 0099 0B .uleb128 0xb + 1350 009a 3B .uleb128 0x3b + 1351 009b 05 .uleb128 0x5 + 1352 009c 01 .uleb128 0x1 + 1353 009d 13 .uleb128 0x13 + 1354 009e 00 .byte 0 + 1355 009f 00 .byte 0 + 1356 00a0 0D .uleb128 0xd + 1357 00a1 15 .uleb128 0x15 + 1358 00a2 01 .byte 0x1 + 1359 00a3 27 .uleb128 0x27 + 1360 00a4 0C .uleb128 0xc + 1361 00a5 01 .uleb128 0x1 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 25 + + + 1362 00a6 13 .uleb128 0x13 + 1363 00a7 00 .byte 0 + 1364 00a8 00 .byte 0 + 1365 00a9 0E .uleb128 0xe + 1366 00aa 05 .uleb128 0x5 + 1367 00ab 00 .byte 0 + 1368 00ac 49 .uleb128 0x49 + 1369 00ad 13 .uleb128 0x13 + 1370 00ae 00 .byte 0 + 1371 00af 00 .byte 0 + 1372 00b0 0F .uleb128 0xf + 1373 00b1 35 .uleb128 0x35 + 1374 00b2 00 .byte 0 + 1375 00b3 49 .uleb128 0x49 + 1376 00b4 13 .uleb128 0x13 + 1377 00b5 00 .byte 0 + 1378 00b6 00 .byte 0 + 1379 00b7 10 .uleb128 0x10 + 1380 00b8 17 .uleb128 0x17 + 1381 00b9 01 .byte 0x1 + 1382 00ba 0B .uleb128 0xb + 1383 00bb 0B .uleb128 0xb + 1384 00bc 3A .uleb128 0x3a + 1385 00bd 0B .uleb128 0xb + 1386 00be 3B .uleb128 0x3b + 1387 00bf 0B .uleb128 0xb + 1388 00c0 01 .uleb128 0x1 + 1389 00c1 13 .uleb128 0x13 + 1390 00c2 00 .byte 0 + 1391 00c3 00 .byte 0 + 1392 00c4 11 .uleb128 0x11 + 1393 00c5 0D .uleb128 0xd + 1394 00c6 00 .byte 0 + 1395 00c7 03 .uleb128 0x3 + 1396 00c8 0E .uleb128 0xe + 1397 00c9 3A .uleb128 0x3a + 1398 00ca 0B .uleb128 0xb + 1399 00cb 3B .uleb128 0x3b + 1400 00cc 0B .uleb128 0xb + 1401 00cd 49 .uleb128 0x49 + 1402 00ce 13 .uleb128 0x13 + 1403 00cf 00 .byte 0 + 1404 00d0 00 .byte 0 + 1405 00d1 12 .uleb128 0x12 + 1406 00d2 26 .uleb128 0x26 + 1407 00d3 00 .byte 0 + 1408 00d4 49 .uleb128 0x49 + 1409 00d5 13 .uleb128 0x13 + 1410 00d6 00 .byte 0 + 1411 00d7 00 .byte 0 + 1412 00d8 13 .uleb128 0x13 + 1413 00d9 01 .uleb128 0x1 + 1414 00da 01 .byte 0x1 + 1415 00db 49 .uleb128 0x49 + 1416 00dc 13 .uleb128 0x13 + 1417 00dd 01 .uleb128 0x1 + 1418 00de 13 .uleb128 0x13 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 26 + + + 1419 00df 00 .byte 0 + 1420 00e0 00 .byte 0 + 1421 00e1 14 .uleb128 0x14 + 1422 00e2 21 .uleb128 0x21 + 1423 00e3 00 .byte 0 + 1424 00e4 49 .uleb128 0x49 + 1425 00e5 13 .uleb128 0x13 + 1426 00e6 2F .uleb128 0x2f + 1427 00e7 0B .uleb128 0xb + 1428 00e8 00 .byte 0 + 1429 00e9 00 .byte 0 + 1430 00ea 15 .uleb128 0x15 + 1431 00eb 2E .uleb128 0x2e + 1432 00ec 01 .byte 0x1 + 1433 00ed 3F .uleb128 0x3f + 1434 00ee 0C .uleb128 0xc + 1435 00ef 03 .uleb128 0x3 + 1436 00f0 0E .uleb128 0xe + 1437 00f1 3A .uleb128 0x3a + 1438 00f2 0B .uleb128 0xb + 1439 00f3 3B .uleb128 0x3b + 1440 00f4 0B .uleb128 0xb + 1441 00f5 27 .uleb128 0x27 + 1442 00f6 0C .uleb128 0xc + 1443 00f7 11 .uleb128 0x11 + 1444 00f8 01 .uleb128 0x1 + 1445 00f9 12 .uleb128 0x12 + 1446 00fa 01 .uleb128 0x1 + 1447 00fb 40 .uleb128 0x40 + 1448 00fc 06 .uleb128 0x6 + 1449 00fd 9742 .uleb128 0x2117 + 1450 00ff 0C .uleb128 0xc + 1451 0100 01 .uleb128 0x1 + 1452 0101 13 .uleb128 0x13 + 1453 0102 00 .byte 0 + 1454 0103 00 .byte 0 + 1455 0104 16 .uleb128 0x16 + 1456 0105 34 .uleb128 0x34 + 1457 0106 00 .byte 0 + 1458 0107 03 .uleb128 0x3 + 1459 0108 0E .uleb128 0xe + 1460 0109 3A .uleb128 0x3a + 1461 010a 0B .uleb128 0xb + 1462 010b 3B .uleb128 0x3b + 1463 010c 0B .uleb128 0xb + 1464 010d 49 .uleb128 0x49 + 1465 010e 13 .uleb128 0x13 + 1466 010f 02 .uleb128 0x2 + 1467 0110 0A .uleb128 0xa + 1468 0111 00 .byte 0 + 1469 0112 00 .byte 0 + 1470 0113 17 .uleb128 0x17 + 1471 0114 898201 .uleb128 0x4109 + 1472 0117 00 .byte 0 + 1473 0118 11 .uleb128 0x11 + 1474 0119 01 .uleb128 0x1 + 1475 011a 31 .uleb128 0x31 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 27 + + + 1476 011b 13 .uleb128 0x13 + 1477 011c 00 .byte 0 + 1478 011d 00 .byte 0 + 1479 011e 18 .uleb128 0x18 + 1480 011f 898201 .uleb128 0x4109 + 1481 0122 01 .byte 0x1 + 1482 0123 11 .uleb128 0x11 + 1483 0124 01 .uleb128 0x1 + 1484 0125 31 .uleb128 0x31 + 1485 0126 13 .uleb128 0x13 + 1486 0127 00 .byte 0 + 1487 0128 00 .byte 0 + 1488 0129 19 .uleb128 0x19 + 1489 012a 8A8201 .uleb128 0x410a + 1490 012d 00 .byte 0 + 1491 012e 02 .uleb128 0x2 + 1492 012f 0A .uleb128 0xa + 1493 0130 9142 .uleb128 0x2111 + 1494 0132 0A .uleb128 0xa + 1495 0133 00 .byte 0 + 1496 0134 00 .byte 0 + 1497 0135 1A .uleb128 0x1a + 1498 0136 2E .uleb128 0x2e + 1499 0137 01 .byte 0x1 + 1500 0138 3F .uleb128 0x3f + 1501 0139 0C .uleb128 0xc + 1502 013a 03 .uleb128 0x3 + 1503 013b 0E .uleb128 0xe + 1504 013c 3A .uleb128 0x3a + 1505 013d 0B .uleb128 0xb + 1506 013e 3B .uleb128 0x3b + 1507 013f 0B .uleb128 0xb + 1508 0140 27 .uleb128 0x27 + 1509 0141 0C .uleb128 0xc + 1510 0142 11 .uleb128 0x11 + 1511 0143 01 .uleb128 0x1 + 1512 0144 12 .uleb128 0x12 + 1513 0145 01 .uleb128 0x1 + 1514 0146 40 .uleb128 0x40 + 1515 0147 06 .uleb128 0x6 + 1516 0148 9642 .uleb128 0x2116 + 1517 014a 0C .uleb128 0xc + 1518 014b 01 .uleb128 0x1 + 1519 014c 13 .uleb128 0x13 + 1520 014d 00 .byte 0 + 1521 014e 00 .byte 0 + 1522 014f 1B .uleb128 0x1b + 1523 0150 0B .uleb128 0xb + 1524 0151 01 .byte 0x1 + 1525 0152 11 .uleb128 0x11 + 1526 0153 01 .uleb128 0x1 + 1527 0154 12 .uleb128 0x12 + 1528 0155 01 .uleb128 0x1 + 1529 0156 00 .byte 0 + 1530 0157 00 .byte 0 + 1531 0158 1C .uleb128 0x1c + 1532 0159 34 .uleb128 0x34 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 28 + + + 1533 015a 00 .byte 0 + 1534 015b 03 .uleb128 0x3 + 1535 015c 08 .uleb128 0x8 + 1536 015d 3A .uleb128 0x3a + 1537 015e 0B .uleb128 0xb + 1538 015f 3B .uleb128 0x3b + 1539 0160 0B .uleb128 0xb + 1540 0161 49 .uleb128 0x49 + 1541 0162 13 .uleb128 0x13 + 1542 0163 02 .uleb128 0x2 + 1543 0164 06 .uleb128 0x6 + 1544 0165 00 .byte 0 + 1545 0166 00 .byte 0 + 1546 0167 1D .uleb128 0x1d + 1547 0168 34 .uleb128 0x34 + 1548 0169 00 .byte 0 + 1549 016a 03 .uleb128 0x3 + 1550 016b 0E .uleb128 0xe + 1551 016c 3A .uleb128 0x3a + 1552 016d 0B .uleb128 0xb + 1553 016e 3B .uleb128 0x3b + 1554 016f 0B .uleb128 0xb + 1555 0170 49 .uleb128 0x49 + 1556 0171 13 .uleb128 0x13 + 1557 0172 3F .uleb128 0x3f + 1558 0173 0C .uleb128 0xc + 1559 0174 3C .uleb128 0x3c + 1560 0175 0C .uleb128 0xc + 1561 0176 00 .byte 0 + 1562 0177 00 .byte 0 + 1563 0178 1E .uleb128 0x1e + 1564 0179 2E .uleb128 0x2e + 1565 017a 00 .byte 0 + 1566 017b 3F .uleb128 0x3f + 1567 017c 0C .uleb128 0xc + 1568 017d 03 .uleb128 0x3 + 1569 017e 0E .uleb128 0xe + 1570 017f 3A .uleb128 0x3a + 1571 0180 0B .uleb128 0xb + 1572 0181 3B .uleb128 0x3b + 1573 0182 05 .uleb128 0x5 + 1574 0183 27 .uleb128 0x27 + 1575 0184 0C .uleb128 0xc + 1576 0185 3C .uleb128 0x3c + 1577 0186 0C .uleb128 0xc + 1578 0187 00 .byte 0 + 1579 0188 00 .byte 0 + 1580 0189 1F .uleb128 0x1f + 1581 018a 2E .uleb128 0x2e + 1582 018b 00 .byte 0 + 1583 018c 3F .uleb128 0x3f + 1584 018d 0C .uleb128 0xc + 1585 018e 03 .uleb128 0x3 + 1586 018f 0E .uleb128 0xe + 1587 0190 3A .uleb128 0x3a + 1588 0191 0B .uleb128 0xb + 1589 0192 3B .uleb128 0x3b + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 29 + + + 1590 0193 0B .uleb128 0xb + 1591 0194 27 .uleb128 0x27 + 1592 0195 0C .uleb128 0xc + 1593 0196 3C .uleb128 0x3c + 1594 0197 0C .uleb128 0xc + 1595 0198 00 .byte 0 + 1596 0199 00 .byte 0 + 1597 019a 20 .uleb128 0x20 + 1598 019b 2E .uleb128 0x2e + 1599 019c 01 .byte 0x1 + 1600 019d 3F .uleb128 0x3f + 1601 019e 0C .uleb128 0xc + 1602 019f 03 .uleb128 0x3 + 1603 01a0 0E .uleb128 0xe + 1604 01a1 3A .uleb128 0x3a + 1605 01a2 0B .uleb128 0xb + 1606 01a3 3B .uleb128 0x3b + 1607 01a4 05 .uleb128 0x5 + 1608 01a5 27 .uleb128 0x27 + 1609 01a6 0C .uleb128 0xc + 1610 01a7 49 .uleb128 0x49 + 1611 01a8 13 .uleb128 0x13 + 1612 01a9 3C .uleb128 0x3c + 1613 01aa 0C .uleb128 0xc + 1614 01ab 00 .byte 0 + 1615 01ac 00 .byte 0 + 1616 01ad 00 .byte 0 + 1617 .section .debug_loc,"",%progbits + 1618 .Ldebug_loc0: + 1619 .LLST0: + 1620 0000 00000000 .4byte .LFB7 + 1621 0004 02000000 .4byte .LCFI0 + 1622 0008 0200 .2byte 0x2 + 1623 000a 7D .byte 0x7d + 1624 000b 00 .sleb128 0 + 1625 000c 02000000 .4byte .LCFI0 + 1626 0010 42000000 .4byte .LFE7 + 1627 0014 0200 .2byte 0x2 + 1628 0016 7D .byte 0x7d + 1629 0017 08 .sleb128 8 + 1630 0018 00000000 .4byte 0 + 1631 001c 00000000 .4byte 0 + 1632 .LLST1: + 1633 0020 00000000 .4byte .LFB8 + 1634 0024 02000000 .4byte .LCFI1 + 1635 0028 0200 .2byte 0x2 + 1636 002a 7D .byte 0x7d + 1637 002b 00 .sleb128 0 + 1638 002c 02000000 .4byte .LCFI1 + 1639 0030 4C000000 .4byte .LFE8 + 1640 0034 0200 .2byte 0x2 + 1641 0036 7D .byte 0x7d + 1642 0037 10 .sleb128 16 + 1643 0038 00000000 .4byte 0 + 1644 003c 00000000 .4byte 0 + 1645 .LLST2: + 1646 0040 2A000000 .4byte .LVL6 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 30 + + + 1647 0044 39000000 .4byte .LVL8-1 + 1648 0048 0100 .2byte 0x1 + 1649 004a 53 .byte 0x53 + 1650 004b 3C000000 .4byte .LVL9 + 1651 004f 42000000 .4byte .LVL10 + 1652 0053 0100 .2byte 0x1 + 1653 0055 53 .byte 0x53 + 1654 0056 00000000 .4byte 0 + 1655 005a 00000000 .4byte 0 + 1656 .LLST3: + 1657 005e 30000000 .4byte .LVL7 + 1658 0062 39000000 .4byte .LVL8-1 + 1659 0066 0100 .2byte 0x1 + 1660 0068 51 .byte 0x51 + 1661 0069 00000000 .4byte 0 + 1662 006d 00000000 .4byte 0 + 1663 .section .debug_aranges,"",%progbits + 1664 0000 24000000 .4byte 0x24 + 1665 0004 0200 .2byte 0x2 + 1666 0006 00000000 .4byte .Ldebug_info0 + 1667 000a 04 .byte 0x4 + 1668 000b 00 .byte 0 + 1669 000c 0000 .2byte 0 + 1670 000e 0000 .2byte 0 + 1671 0010 00000000 .4byte .LFB7 + 1672 0014 42000000 .4byte .LFE7-.LFB7 + 1673 0018 00000000 .4byte .LFB8 + 1674 001c 4C000000 .4byte .LFE8-.LFB8 + 1675 0020 00000000 .4byte 0 + 1676 0024 00000000 .4byte 0 + 1677 .section .debug_ranges,"",%progbits + 1678 .Ldebug_ranges0: + 1679 0000 00000000 .4byte .LFB7 + 1680 0004 42000000 .4byte .LFE7 + 1681 0008 00000000 .4byte .LFB8 + 1682 000c 4C000000 .4byte .LFE8 + 1683 0010 00000000 .4byte 0 + 1684 0014 00000000 .4byte 0 + 1685 .section .debug_line,"",%progbits + 1686 .Ldebug_line0: + 1687 0000 6F010000 .section .debug_str,"MS",%progbits,1 + 1687 02002B01 + 1687 00000201 + 1687 FB0E0D00 + 1687 01010101 + 1688 .LASF82: + 1689 0000 63665F6F .ascii "cf_off_older\000" + 1689 66665F6F + 1689 6C646572 + 1689 00 + 1690 .LASF35: + 1691 000d 705F6D73 .ascii "p_msg\000" + 1691 6700 + 1692 .LASF67: + 1693 0013 7264796D .ascii "rdymsg\000" + 1693 736700 + 1694 .LASF94: + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 31 + + + 1695 001a 76746C69 .ascii "vtlist\000" + 1695 737400 + 1696 .LASF92: + 1697 0021 63685379 .ascii "chSysTimerHandlerI\000" + 1697 7354696D + 1697 65724861 + 1697 6E646C65 + 1697 724900 + 1698 .LASF12: + 1699 0034 6C6F6E67 .ascii "long long unsigned int\000" + 1699 206C6F6E + 1699 6720756E + 1699 7369676E + 1699 65642069 + 1700 .LASF78: + 1701 004b 63685F74 .ascii "ch_threadsize\000" + 1701 68726561 + 1701 6473697A + 1701 6500 + 1702 .LASF68: + 1703 0059 65786974 .ascii "exitcode\000" + 1703 636F6465 + 1703 00 + 1704 .LASF93: + 1705 0062 6D61696E .ascii "mainthread\000" + 1705 74687265 + 1705 616400 + 1706 .LASF103: + 1707 006d 2E2E2F2E .ascii "../..//os/kernel/src/chsys.c\000" + 1707 2E2F2F6F + 1707 732F6B65 + 1707 726E656C + 1707 2F737263 + 1708 .LASF24: + 1709 008a 705F7072 .ascii "p_prio\000" + 1709 696F00 + 1710 .LASF85: + 1711 0091 63665F6F .ascii "cf_off_state\000" + 1711 66665F73 + 1711 74617465 + 1711 00 + 1712 .LASF98: + 1713 009e 5F736368 .ascii "_scheduler_init\000" + 1713 6564756C + 1713 65725F69 + 1713 6E697400 + 1714 .LASF11: + 1715 00ae 6C6F6E67 .ascii "long long int\000" + 1715 206C6F6E + 1715 6720696E + 1715 7400 + 1716 .LASF1: + 1717 00bc 7369676E .ascii "signed char\000" + 1717 65642063 + 1717 68617200 + 1718 .LASF84: + 1719 00c8 63665F6F .ascii "cf_off_stklimit\000" + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 32 + + + 1719 66665F73 + 1719 746B6C69 + 1719 6D697400 + 1720 .LASF86: + 1721 00d8 63665F6F .ascii "cf_off_flags\000" + 1721 66665F66 + 1721 6C616773 + 1721 00 + 1722 .LASF39: + 1723 00e5 705F6D70 .ascii "p_mpool\000" + 1723 6F6F6C00 + 1724 .LASF64: + 1725 00ed 6D5F7175 .ascii "m_queue\000" + 1725 65756500 + 1726 .LASF72: + 1727 00f5 63685F69 .ascii "ch_identifier\000" + 1727 64656E74 + 1727 69666965 + 1727 7200 + 1728 .LASF8: + 1729 0103 6C6F6E67 .ascii "long int\000" + 1729 20696E74 + 1729 00 + 1730 .LASF14: + 1731 010c 74737461 .ascii "tstate_t\000" + 1731 74655F74 + 1731 00 + 1732 .LASF5: + 1733 0115 75696E74 .ascii "uint16_t\000" + 1733 31365F74 + 1733 00 + 1734 .LASF90: + 1735 011e 63686465 .ascii "chdebug_t\000" + 1735 6275675F + 1735 7400 + 1736 .LASF26: + 1737 0128 705F6E65 .ascii "p_newer\000" + 1737 77657200 + 1738 .LASF58: + 1739 0130 725F6E65 .ascii "r_newer\000" + 1739 77657200 + 1740 .LASF42: + 1741 0138 72656761 .ascii "regarm_t\000" + 1741 726D5F74 + 1741 00 + 1742 .LASF49: + 1743 0141 76745F70 .ascii "vt_prev\000" + 1743 72657600 + 1744 .LASF91: + 1745 0149 63685379 .ascii "chSysInit\000" + 1745 73496E69 + 1745 7400 + 1746 .LASF101: + 1747 0153 5F686561 .ascii "_heap_init\000" + 1747 705F696E + 1747 697400 + 1748 .LASF20: + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 33 + + + 1749 015e 636E745F .ascii "cnt_t\000" + 1749 7400 + 1750 .LASF0: + 1751 0164 756E7369 .ascii "unsigned int\000" + 1751 676E6564 + 1751 20696E74 + 1751 00 + 1752 .LASF105: + 1753 0171 5F746872 .ascii "_thread_init\000" + 1753 6561645F + 1753 696E6974 + 1753 00 + 1754 .LASF48: + 1755 017e 76745F6E .ascii "vt_next\000" + 1755 65787400 + 1756 .LASF10: + 1757 0186 6C6F6E67 .ascii "long unsigned int\000" + 1757 20756E73 + 1757 69676E65 + 1757 6420696E + 1757 7400 + 1758 .LASF96: + 1759 0198 63685F64 .ascii "ch_debug\000" + 1759 65627567 + 1759 00 + 1760 .LASF44: + 1761 01a1 636F6E74 .ascii "context\000" + 1761 65787400 + 1762 .LASF6: + 1763 01a9 73686F72 .ascii "short unsigned int\000" + 1763 7420756E + 1763 7369676E + 1763 65642069 + 1763 6E7400 + 1764 .LASF17: + 1765 01bc 6D73675F .ascii "msg_t\000" + 1765 7400 + 1766 .LASF13: + 1767 01c2 746D6F64 .ascii "tmode_t\000" + 1767 655F7400 + 1768 .LASF41: + 1769 01ca 54687265 .ascii "ThreadsList\000" + 1769 6164734C + 1769 69737400 + 1770 .LASF18: + 1771 01d6 6576656E .ascii "eventmask_t\000" + 1771 746D6173 + 1771 6B5F7400 + 1772 .LASF63: + 1773 01e2 4D757465 .ascii "Mutex\000" + 1773 7800 + 1774 .LASF73: + 1775 01e8 63685F7A .ascii "ch_zero\000" + 1775 65726F00 + 1776 .LASF87: + 1777 01f0 63665F6F .ascii "cf_off_refs\000" + 1777 66665F72 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 34 + + + 1777 65667300 + 1778 .LASF50: + 1779 01fc 76745F74 .ascii "vt_time\000" + 1779 696D6500 + 1780 .LASF45: + 1781 0204 73697A65 .ascii "sizetype\000" + 1781 74797065 + 1781 00 + 1782 .LASF51: + 1783 020d 76745F66 .ascii "vt_func\000" + 1783 756E6300 + 1784 .LASF77: + 1785 0215 63685F74 .ascii "ch_timesize\000" + 1785 696D6573 + 1785 697A6500 + 1786 .LASF83: + 1787 0221 63665F6F .ascii "cf_off_name\000" + 1787 66665F6E + 1787 616D6500 + 1788 .LASF27: + 1789 022d 705F6F6C .ascii "p_older\000" + 1789 64657200 + 1790 .LASF104: + 1791 0235 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 1791 73657273 + 1791 5C496D61 + 1791 6E6F6C5C + 1791 64657665 + 1792 0262 6C696361 .ascii "lications\\smartcities\000" + 1792 74696F6E + 1792 735C736D + 1792 61727463 + 1792 69746965 + 1793 .LASF40: + 1794 0278 54687265 .ascii "ThreadsQueue\000" + 1794 61647351 + 1794 75657565 + 1794 00 + 1795 .LASF74: + 1796 0285 63685F73 .ascii "ch_size\000" + 1796 697A6500 + 1797 .LASF102: + 1798 028d 474E5520 .ascii "GNU C 4.7.2\000" + 1798 4320342E + 1798 372E3200 + 1799 .LASF61: + 1800 0299 725F6375 .ascii "r_current\000" + 1800 7272656E + 1800 7400 + 1801 .LASF59: + 1802 02a3 725F6F6C .ascii "r_older\000" + 1802 64657200 + 1803 .LASF15: + 1804 02ab 74726566 .ascii "trefs_t\000" + 1804 735F7400 + 1805 .LASF76: + 1806 02b3 63685F70 .ascii "ch_ptrsize\000" + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 35 + + + 1806 74727369 + 1806 7A6500 + 1807 .LASF23: + 1808 02be 705F7072 .ascii "p_prev\000" + 1808 657600 + 1809 .LASF16: + 1810 02c5 74707269 .ascii "tprio_t\000" + 1810 6F5F7400 + 1811 .LASF7: + 1812 02cd 696E7433 .ascii "int32_t\000" + 1812 325F7400 + 1813 .LASF2: + 1814 02d5 756E7369 .ascii "unsigned char\000" + 1814 676E6564 + 1814 20636861 + 1814 7200 + 1815 .LASF100: + 1816 02e3 5F636F72 .ascii "_core_init\000" + 1816 655F696E + 1816 697400 + 1817 .LASF37: + 1818 02ee 705F6D74 .ascii "p_mtxlist\000" + 1818 786C6973 + 1818 7400 + 1819 .LASF3: + 1820 02f8 73686F72 .ascii "short int\000" + 1820 7420696E + 1820 7400 + 1821 .LASF29: + 1822 0302 705F7374 .ascii "p_state\000" + 1822 61746500 + 1823 .LASF89: + 1824 030a 63665F6F .ascii "cf_off_time\000" + 1824 66665F74 + 1824 696D6500 + 1825 .LASF56: + 1826 0316 725F7072 .ascii "r_prio\000" + 1826 696F00 + 1827 .LASF70: + 1828 031d 65776D61 .ascii "ewmask\000" + 1828 736B00 + 1829 .LASF22: + 1830 0324 705F6E65 .ascii "p_next\000" + 1830 787400 + 1831 .LASF88: + 1832 032b 63665F6F .ascii "cf_off_preempt\000" + 1832 66665F70 + 1832 7265656D + 1832 707400 + 1833 .LASF30: + 1834 033a 705F666C .ascii "p_flags\000" + 1834 61677300 + 1835 .LASF21: + 1836 0342 54687265 .ascii "Thread\000" + 1836 616400 + 1837 .LASF81: + 1838 0349 63665F6F .ascii "cf_off_newer\000" + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 36 + + + 1838 66665F6E + 1838 65776572 + 1838 00 + 1839 .LASF36: + 1840 0356 705F6570 .ascii "p_epending\000" + 1840 656E6469 + 1840 6E6700 + 1841 .LASF9: + 1842 0361 75696E74 .ascii "uint32_t\000" + 1842 33325F74 + 1842 00 + 1843 .LASF79: + 1844 036a 63665F6F .ascii "cf_off_prio\000" + 1844 66665F70 + 1844 72696F00 + 1845 .LASF55: + 1846 0376 725F7175 .ascii "r_queue\000" + 1846 65756500 + 1847 .LASF47: + 1848 037e 56697274 .ascii "VirtualTimer\000" + 1848 75616C54 + 1848 696D6572 + 1848 00 + 1849 .LASF71: + 1850 038b 63686172 .ascii "char\000" + 1850 00 + 1851 .LASF66: + 1852 0390 6D5F6E65 .ascii "m_next\000" + 1852 787400 + 1853 .LASF19: + 1854 0397 73797374 .ascii "systime_t\000" + 1854 696D655F + 1854 7400 + 1855 .LASF38: + 1856 03a1 705F7265 .ascii "p_realprio\000" + 1856 616C7072 + 1856 696F00 + 1857 .LASF46: + 1858 03ac 76746675 .ascii "vtfunc_t\000" + 1858 6E635F74 + 1858 00 + 1859 .LASF99: + 1860 03b5 5F76745F .ascii "_vt_init\000" + 1860 696E6974 + 1860 00 + 1861 .LASF32: + 1862 03be 705F7469 .ascii "p_time\000" + 1862 6D6500 + 1863 .LASF57: + 1864 03c5 725F6374 .ascii "r_ctx\000" + 1864 7800 + 1865 .LASF43: + 1866 03cb 696E7463 .ascii "intctx\000" + 1866 747800 + 1867 .LASF34: + 1868 03d2 705F6D73 .ascii "p_msgqueue\000" + 1868 67717565 + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 37 + + + 1868 756500 + 1869 .LASF52: + 1870 03dd 76745F70 .ascii "vt_par\000" + 1870 617200 + 1871 .LASF80: + 1872 03e4 63665F6F .ascii "cf_off_ctx\000" + 1872 66665F63 + 1872 747800 + 1873 .LASF31: + 1874 03ef 705F7265 .ascii "p_refs\000" + 1874 667300 + 1875 .LASF62: + 1876 03f6 52656164 .ascii "ReadyList\000" + 1876 794C6973 + 1876 7400 + 1877 .LASF95: + 1878 0400 726C6973 .ascii "rlist\000" + 1878 7400 + 1879 .LASF4: + 1880 0406 75696E74 .ascii "uint8_t\000" + 1880 385F7400 + 1881 .LASF69: + 1882 040e 77746F62 .ascii "wtobjp\000" + 1882 6A7000 + 1883 .LASF97: + 1884 0415 5F706F72 .ascii "_port_init\000" + 1884 745F696E + 1884 697400 + 1885 .LASF28: + 1886 0420 705F6E61 .ascii "p_name\000" + 1886 6D6500 + 1887 .LASF53: + 1888 0427 76745F73 .ascii "vt_systime\000" + 1888 79737469 + 1888 6D6500 + 1889 .LASF75: + 1890 0432 63685F76 .ascii "ch_version\000" + 1890 65727369 + 1890 6F6E00 + 1891 .LASF54: + 1892 043d 56544C69 .ascii "VTList\000" + 1892 737400 + 1893 .LASF60: + 1894 0444 725F7072 .ascii "r_preempt\000" + 1894 65656D70 + 1894 7400 + 1895 .LASF65: + 1896 044e 6D5F6F77 .ascii "m_owner\000" + 1896 6E657200 + 1897 .LASF25: + 1898 0456 705F6374 .ascii "p_ctx\000" + 1898 7800 + 1899 .LASF33: + 1900 045c 705F7761 .ascii "p_waiting\000" + 1900 6974696E + 1900 6700 + 1901 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 38 + + + ARM GAS C:\cygwin\tmp\ccKBqVqy.s page 39 + + +DEFINED SYMBOLS + *ABS*:00000000 chsys.c +C:\cygwin\tmp\ccKBqVqy.s:19 .text.chSysInit:00000000 $t +C:\cygwin\tmp\ccKBqVqy.s:25 .text.chSysInit:00000000 chSysInit +C:\cygwin\tmp\ccKBqVqy.s:165 .bss.mainthread.4814:00000000 .LANCHOR0 +C:\cygwin\tmp\ccKBqVqy.s:81 .text.chSysTimerHandlerI:00000000 $t +C:\cygwin\tmp\ccKBqVqy.s:87 .text.chSysTimerHandlerI:00000000 chSysTimerHandlerI +C:\cygwin\tmp\ccKBqVqy.s:157 .text.chSysTimerHandlerI:00000044 $d +C:\cygwin\tmp\ccKBqVqy.s:164 .bss.mainthread.4814:00000000 $d +C:\cygwin\tmp\ccKBqVqy.s:168 .bss.mainthread.4814:00000000 mainthread.4814 + .debug_frame:00000010 $d +C:\cygwin\tmp\ccKBqVqy.s:163 .text.chSysTimerHandlerI:0000004c $t + +UNDEFINED SYMBOLS +_port_init +_scheduler_init +_vt_init +_core_init +_heap_init +_thread_init +rlist +ch_debug +vtlist diff --git a/Project/applications/smartcities/build/lst/chthreads.lst b/Project/applications/smartcities/build/lst/chthreads.lst new file mode 100644 index 0000000..47553c0 --- /dev/null +++ b/Project/applications/smartcities/build/lst/chthreads.lst @@ -0,0 +1,4048 @@ +ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "chthreads.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text._thread_init,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .global _thread_init + 22 .thumb + 23 .thumb_func + 24 .type _thread_init, %function + 25 _thread_init: + 26 .LFB7: + 27 .file 1 "../..//os/kernel/src/chthreads.c" + 28 .loc 1 76 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .LVL0: + 34 0000 F0B4 push {r4, r5, r6, r7} + 35 .LCFI0: + 36 .cfi_def_cfa_offset 16 + 37 .cfi_offset 4, -16 + 38 .cfi_offset 5, -12 + 39 .cfi_offset 6, -8 + 40 .cfi_offset 7, -4 + 41 .loc 1 96 0 + 42 0002 40F20004 movw r4, #:lower16:rlist + 43 0006 C0F20004 movt r4, #:upper16:rlist + 44 000a 6569 ldr r5, [r4, #20] + 45 .loc 1 80 0 + 46 000c 0022 movs r2, #0 + 47 .loc 1 102 0 + 48 000e 00F12C06 add r6, r0, #44 + 49 .loc 1 78 0 + 50 0012 8160 str r1, [r0, #8] + 51 .loc 1 99 0 + 52 0014 00F12807 add r7, r0, #40 + 53 .loc 1 79 0 + 54 0018 4FF0020C mov ip, #2 + 55 .loc 1 82 0 + 56 001c 0164 str r1, [r0, #64] + 57 .loc 1 92 0 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 2 + + + 58 001e 0121 movs r1, #1 + 59 .LVL1: + 60 .loc 1 96 0 + 61 0020 0461 str r4, [r0, #16] + 62 0022 4561 str r5, [r0, #20] + 63 .loc 1 79 0 + 64 0024 80F81CC0 strb ip, [r0, #28] + 65 .loc 1 96 0 + 66 0028 6061 str r0, [r4, #20] + 67 .loc 1 80 0 + 68 002a 4277 strb r2, [r0, #29] + 69 .loc 1 83 0 + 70 002c C263 str r2, [r0, #60] + 71 .loc 1 86 0 + 72 002e 8263 str r2, [r0, #56] + 73 .loc 1 89 0 + 74 0030 0262 str r2, [r0, #32] + 75 .loc 1 92 0 + 76 0032 8177 strb r1, [r0, #30] + 77 .loc 1 95 0 + 78 0034 8261 str r2, [r0, #24] + 79 .loc 1 96 0 + 80 0036 2861 str r0, [r5, #16] + 81 .loc 1 99 0 + 82 0038 8762 str r7, [r0, #40] + 83 .loc 1 102 0 + 84 003a 0663 str r6, [r0, #48] + 85 003c C662 str r6, [r0, #44] + 86 .loc 1 111 0 + 87 003e F0BC pop {r4, r5, r6, r7} + 88 0040 7047 bx lr + 89 .cfi_endproc + 90 .LFE7: + 91 .size _thread_init, .-_thread_init + 92 0042 00BFAFF3 .section .text.chThdCreateI,"ax",%progbits + 92 0080AFF3 + 92 0080AFF3 + 92 0080 + 93 .align 2 + 94 .p2align 4,,15 + 95 .global chThdCreateI + 96 .thumb + 97 .thumb_func + 98 .type chThdCreateI, %function + 99 chThdCreateI: + 100 .LFB8: + 101 .loc 1 155 0 + 102 .cfi_startproc + 103 @ args = 4, pretend = 0, frame = 0 + 104 @ frame_needed = 0, uses_anonymous_args = 0 + 105 @ link register save eliminated. + 106 .LVL2: + 107 0000 2DE9F003 push {r4, r5, r6, r7, r8, r9} + 108 .LCFI1: + 109 .cfi_def_cfa_offset 24 + 110 .cfi_offset 4, -24 + 111 .cfi_offset 5, -20 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 3 + + + 112 .cfi_offset 6, -16 + 113 .cfi_offset 7, -12 + 114 .cfi_offset 8, -8 + 115 .cfi_offset 9, -4 + 116 .loc 1 164 0 + 117 0004 2439 subs r1, r1, #36 + 118 .LVL3: + 119 .LBB8: + 120 .LBB9: + 121 .loc 1 96 0 + 122 0006 40F20005 movw r5, #:lower16:rlist + 123 000a C0F20005 movt r5, #:upper16:rlist + 124 .LBE9: + 125 .LBE8: + 126 .loc 1 164 0 + 127 000e 4718 adds r7, r0, r1 + 128 .LBB15: + 129 .LBB10: + 130 .loc 1 96 0 + 131 0010 D5F814C0 ldr ip, [r5, #20] + 132 .LBE10: + 133 .LBE15: + 134 .loc 1 164 0 + 135 0014 C760 str r7, [r0, #12] + 136 0016 4350 str r3, [r0, r1] + 137 0018 069B ldr r3, [sp, #24] + 138 .LVL4: + 139 .LBB16: + 140 .LBB11: + 141 .loc 1 80 0 + 142 001a 0026 movs r6, #0 + 143 .LBE11: + 144 .LBE16: + 145 .loc 1 164 0 + 146 001c 7B60 str r3, [r7, #4] + 147 001e 40F20003 movw r3, #:lower16:_port_thread_start + 148 0022 C0F20003 movt r3, #:upper16:_port_thread_start + 149 0026 3B62 str r3, [r7, #32] + 150 .LBB17: + 151 .LBB12: + 152 .loc 1 79 0 + 153 0028 0223 movs r3, #2 + 154 .LBE12: + 155 .LBE17: + 156 .loc 1 155 0 + 157 002a 9046 mov r8, r2 + 158 .LBB18: + 159 .LBB13: + 160 .loc 1 99 0 + 161 002c 00F12809 add r9, r0, #40 + 162 .loc 1 102 0 + 163 0030 00F12C02 add r2, r0, #44 + 164 .LVL5: + 165 .loc 1 79 0 + 166 0034 0377 strb r3, [r0, #28] + 167 .loc 1 92 0 + 168 0036 0123 movs r3, #1 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 4 + + + 169 .loc 1 96 0 + 170 0038 0561 str r5, [r0, #16] + 171 .loc 1 78 0 + 172 003a C0F80880 str r8, [r0, #8] + 173 .loc 1 96 0 + 174 003e C0F814C0 str ip, [r0, #20] + 175 .LBE13: + 176 .LBE18: + 177 .loc 1 155 0 + 178 0042 0446 mov r4, r0 + 179 .LVL6: + 180 .LBB19: + 181 .LBB14: + 182 .loc 1 96 0 + 183 0044 6861 str r0, [r5, #20] + 184 .loc 1 80 0 + 185 0046 4677 strb r6, [r0, #29] + 186 .loc 1 82 0 + 187 0048 C0F84080 str r8, [r0, #64] + 188 .loc 1 83 0 + 189 004c C663 str r6, [r0, #60] + 190 .loc 1 86 0 + 191 004e 8663 str r6, [r0, #56] + 192 .loc 1 89 0 + 193 0050 0662 str r6, [r0, #32] + 194 .loc 1 92 0 + 195 0052 8377 strb r3, [r0, #30] + 196 .loc 1 95 0 + 197 0054 8661 str r6, [r0, #24] + 198 .loc 1 96 0 + 199 0056 CCF81000 str r0, [ip, #16] + 200 .loc 1 99 0 + 201 005a C0F82890 str r9, [r0, #40] + 202 .loc 1 102 0 + 203 005e 0263 str r2, [r0, #48] + 204 0060 C262 str r2, [r0, #44] + 205 .LBE14: + 206 .LBE19: + 207 .loc 1 166 0 + 208 0062 BDE8F003 pop {r4, r5, r6, r7, r8, r9} + 209 0066 7047 bx lr + 210 .cfi_endproc + 211 .LFE8: + 212 .size chThdCreateI, .-chThdCreateI + 213 0068 AFF30080 .section .text.chThdCreateStatic,"ax",%progbits + 213 AFF30080 + 214 .align 2 + 215 .p2align 4,,15 + 216 .global chThdCreateStatic + 217 .thumb + 218 .thumb_func + 219 .type chThdCreateStatic, %function + 220 chThdCreateStatic: + 221 .LFB9: + 222 .loc 1 185 0 + 223 .cfi_startproc + 224 @ args = 4, pretend = 0, frame = 0 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 5 + + + 225 @ frame_needed = 0, uses_anonymous_args = 0 + 226 .LVL7: + 227 0000 10B5 push {r4, lr} + 228 .LCFI2: + 229 .cfi_def_cfa_offset 8 + 230 .cfi_offset 4, -8 + 231 .cfi_offset 14, -4 + 232 0002 82B0 sub sp, sp, #8 + 233 .LCFI3: + 234 .cfi_def_cfa_offset 16 + 235 .loc 1 196 0 + 236 @ 196 "../..//os/kernel/src/chthreads.c" 1 + 237 0004 72B6 cpsid i + 238 @ 0 "" 2 + 239 .loc 1 197 0 + 240 .thumb + 241 0006 049C ldr r4, [sp, #16] + 242 0008 0094 str r4, [sp, #0] + 243 000a FFF7FEFF bl chThdCreateI + 244 .LVL8: + 245 000e 0021 movs r1, #0 + 246 0010 0446 mov r4, r0 + 247 .LVL9: + 248 0012 FFF7FEFF bl chSchWakeupS + 249 .LVL10: + 250 .loc 1 198 0 + 251 @ 198 "../..//os/kernel/src/chthreads.c" 1 + 252 0016 62B6 cpsie i + 253 @ 0 "" 2 + 254 .loc 1 200 0 + 255 .thumb + 256 0018 2046 mov r0, r4 + 257 001a 02B0 add sp, sp, #8 + 258 001c 10BD pop {r4, pc} + 259 .cfi_endproc + 260 .LFE9: + 261 .size chThdCreateStatic, .-chThdCreateStatic + 262 .section .text.chThdSetPriority,"ax",%progbits + 263 .align 2 + 264 .p2align 4,,15 + 265 .global chThdSetPriority + 266 .thumb + 267 .thumb_func + 268 .type chThdSetPriority, %function + 269 chThdSetPriority: + 270 .LFB10: + 271 .loc 1 214 0 + 272 .cfi_startproc + 273 @ args = 0, pretend = 0, frame = 0 + 274 @ frame_needed = 0, uses_anonymous_args = 0 + 275 .LVL11: + 276 0000 10B5 push {r4, lr} + 277 .LCFI4: + 278 .cfi_def_cfa_offset 8 + 279 .cfi_offset 4, -8 + 280 .cfi_offset 14, -4 + 281 .loc 1 219 0 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 6 + + + 282 @ 219 "../..//os/kernel/src/chthreads.c" 1 + 283 0002 72B6 cpsid i + 284 @ 0 "" 2 + 285 .loc 1 221 0 + 286 .thumb + 287 0004 074B ldr r3, .L8 + 288 0006 DB69 ldr r3, [r3, #28] + 289 0008 1C6C ldr r4, [r3, #64] + 290 .LVL12: + 291 .loc 1 222 0 + 292 000a 9968 ldr r1, [r3, #8] + 293 000c 8C42 cmp r4, r1 + 294 000e 01D0 beq .L5 + 295 .loc 1 222 0 is_stmt 0 discriminator 1 + 296 0010 8142 cmp r1, r0 + 297 0012 00D2 bcs .L6 + 298 .L5: + 299 .loc 1 223 0 is_stmt 1 + 300 0014 9860 str r0, [r3, #8] + 301 .L6: + 302 .loc 1 224 0 + 303 0016 1864 str r0, [r3, #64] + 304 .loc 1 229 0 + 305 0018 FFF7FEFF bl chSchRescheduleS + 306 .LVL13: + 307 .loc 1 230 0 + 308 @ 230 "../..//os/kernel/src/chthreads.c" 1 + 309 001c 62B6 cpsie i + 310 @ 0 "" 2 + 311 .loc 1 232 0 + 312 .thumb + 313 001e 2046 mov r0, r4 + 314 0020 10BD pop {r4, pc} + 315 .L9: + 316 0022 00BF .align 2 + 317 .L8: + 318 0024 00000000 .word rlist + 319 .cfi_endproc + 320 .LFE10: + 321 .size chThdSetPriority, .-chThdSetPriority + 322 0028 AFF30080 .section .text.chThdResume,"ax",%progbits + 322 AFF30080 + 323 .align 2 + 324 .p2align 4,,15 + 325 .global chThdResume + 326 .thumb + 327 .thumb_func + 328 .type chThdResume, %function + 329 chThdResume: + 330 .LFB11: + 331 .loc 1 247 0 + 332 .cfi_startproc + 333 @ args = 0, pretend = 0, frame = 0 + 334 @ frame_needed = 0, uses_anonymous_args = 0 + 335 .LVL14: + 336 0000 10B5 push {r4, lr} + 337 .LCFI5: + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 7 + + + 338 .cfi_def_cfa_offset 8 + 339 .cfi_offset 4, -8 + 340 .cfi_offset 14, -4 + 341 .loc 1 247 0 + 342 0002 0446 mov r4, r0 + 343 .loc 1 249 0 + 344 @ 249 "../..//os/kernel/src/chthreads.c" 1 + 345 0004 72B6 cpsid i + 346 @ 0 "" 2 + 347 .loc 1 253 0 + 348 .thumb + 349 0006 0021 movs r1, #0 + 350 0008 FFF7FEFF bl chSchWakeupS + 351 .LVL15: + 352 .loc 1 254 0 + 353 @ 254 "../..//os/kernel/src/chthreads.c" 1 + 354 000c 62B6 cpsie i + 355 @ 0 "" 2 + 356 .loc 1 256 0 + 357 .thumb + 358 000e 2046 mov r0, r4 + 359 0010 10BD pop {r4, pc} + 360 .cfi_endproc + 361 .LFE11: + 362 .size chThdResume, .-chThdResume + 363 0012 00BFAFF3 .section .text.chThdTerminate,"ax",%progbits + 363 0080AFF3 + 363 0080AFF3 + 363 0080 + 364 .align 2 + 365 .p2align 4,,15 + 366 .global chThdTerminate + 367 .thumb + 368 .thumb_func + 369 .type chThdTerminate, %function + 370 chThdTerminate: + 371 .LFB12: + 372 .loc 1 270 0 + 373 .cfi_startproc + 374 @ args = 0, pretend = 0, frame = 0 + 375 @ frame_needed = 0, uses_anonymous_args = 0 + 376 @ link register save eliminated. + 377 .LVL16: + 378 .loc 1 272 0 + 379 @ 272 "../..//os/kernel/src/chthreads.c" 1 + 380 0000 72B6 cpsid i + 381 @ 0 "" 2 + 382 .loc 1 273 0 + 383 .thumb + 384 0002 437F ldrb r3, [r0, #29] @ zero_extendqisi2 + 385 0004 43F00403 orr r3, r3, #4 + 386 0008 4377 strb r3, [r0, #29] + 387 .loc 1 274 0 + 388 @ 274 "../..//os/kernel/src/chthreads.c" 1 + 389 000a 62B6 cpsie i + 390 @ 0 "" 2 + 391 .thumb + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 8 + + + 392 000c 7047 bx lr + 393 .cfi_endproc + 394 .LFE12: + 395 .size chThdTerminate, .-chThdTerminate + 396 000e 00BF .section .text.chThdSleep,"ax",%progbits + 397 .align 2 + 398 .p2align 4,,15 + 399 .global chThdSleep + 400 .thumb + 401 .thumb_func + 402 .type chThdSleep, %function + 403 chThdSleep: + 404 .LFB13: + 405 .loc 1 289 0 + 406 .cfi_startproc + 407 @ args = 0, pretend = 0, frame = 0 + 408 @ frame_needed = 0, uses_anonymous_args = 0 + 409 .LVL17: + 410 0000 08B5 push {r3, lr} + 411 .LCFI6: + 412 .cfi_def_cfa_offset 8 + 413 .cfi_offset 3, -8 + 414 .cfi_offset 14, -4 + 415 .loc 1 289 0 + 416 0002 0146 mov r1, r0 + 417 .loc 1 293 0 + 418 @ 293 "../..//os/kernel/src/chthreads.c" 1 + 419 0004 72B6 cpsid i + 420 @ 0 "" 2 + 421 .loc 1 294 0 + 422 .thumb + 423 0006 0620 movs r0, #6 + 424 .LVL18: + 425 0008 FFF7FEFF bl chSchGoSleepTimeoutS + 426 .LVL19: + 427 .loc 1 295 0 + 428 @ 295 "../..//os/kernel/src/chthreads.c" 1 + 429 000c 62B6 cpsie i + 430 @ 0 "" 2 + 431 .thumb + 432 000e 08BD pop {r3, pc} + 433 .cfi_endproc + 434 .LFE13: + 435 .size chThdSleep, .-chThdSleep + 436 .section .text.chThdSleepUntil,"ax",%progbits + 437 .align 2 + 438 .p2align 4,,15 + 439 .global chThdSleepUntil + 440 .thumb + 441 .thumb_func + 442 .type chThdSleepUntil, %function + 443 chThdSleepUntil: + 444 .LFB14: + 445 .loc 1 306 0 + 446 .cfi_startproc + 447 @ args = 0, pretend = 0, frame = 0 + 448 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 9 + + + 449 .LVL20: + 450 0000 08B5 push {r3, lr} + 451 .LCFI7: + 452 .cfi_def_cfa_offset 8 + 453 .cfi_offset 3, -8 + 454 .cfi_offset 14, -4 + 455 .loc 1 308 0 + 456 @ 308 "../..//os/kernel/src/chthreads.c" 1 + 457 0002 72B6 cpsid i + 458 @ 0 "" 2 + 459 .loc 1 309 0 + 460 .thumb + 461 0004 044B ldr r3, .L18 + 462 0006 DB68 ldr r3, [r3, #12] + 463 .LVL21: + 464 0008 C11A subs r1, r0, r3 + 465 .LVL22: + 466 000a 02D0 beq .L14 + 467 .loc 1 310 0 + 468 000c 0620 movs r0, #6 + 469 000e FFF7FEFF bl chSchGoSleepTimeoutS + 470 .LVL23: + 471 .L14: + 472 .loc 1 311 0 + 473 @ 311 "../..//os/kernel/src/chthreads.c" 1 + 474 0012 62B6 cpsie i + 475 @ 0 "" 2 + 476 .thumb + 477 0014 08BD pop {r3, pc} + 478 .L19: + 479 0016 00BF .align 2 + 480 .L18: + 481 0018 00000000 .word vtlist + 482 .cfi_endproc + 483 .LFE14: + 484 .size chThdSleepUntil, .-chThdSleepUntil + 485 001c AFF30080 .section .text.chThdYield,"ax",%progbits + 486 .align 2 + 487 .p2align 4,,15 + 488 .global chThdYield + 489 .thumb + 490 .thumb_func + 491 .type chThdYield, %function + 492 chThdYield: + 493 .LFB15: + 494 .loc 1 321 0 + 495 .cfi_startproc + 496 @ args = 0, pretend = 0, frame = 0 + 497 @ frame_needed = 0, uses_anonymous_args = 0 + 498 0000 08B5 push {r3, lr} + 499 .LCFI8: + 500 .cfi_def_cfa_offset 8 + 501 .cfi_offset 3, -8 + 502 .cfi_offset 14, -4 + 503 .loc 1 323 0 + 504 @ 323 "../..//os/kernel/src/chthreads.c" 1 + 505 0002 72B6 cpsid i + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 10 + + + 506 @ 0 "" 2 + 507 .loc 1 324 0 + 508 .thumb + 509 0004 054B ldr r3, .L22 + 510 0006 1A68 ldr r2, [r3, #0] + 511 0008 DB69 ldr r3, [r3, #28] + 512 000a 9268 ldr r2, [r2, #8] + 513 000c 9B68 ldr r3, [r3, #8] + 514 000e 9A42 cmp r2, r3 + 515 0010 01D3 bcc .L21 + 516 .loc 1 324 0 is_stmt 0 discriminator 1 + 517 0012 FFF7FEFF bl chSchDoReschedule + 518 .LVL24: + 519 .L21: + 520 .loc 1 325 0 is_stmt 1 + 521 @ 325 "../..//os/kernel/src/chthreads.c" 1 + 522 0016 62B6 cpsie i + 523 @ 0 "" 2 + 524 .thumb + 525 0018 08BD pop {r3, pc} + 526 .L23: + 527 001a 00BF .align 2 + 528 .L22: + 529 001c 00000000 .word rlist + 530 .cfi_endproc + 531 .LFE15: + 532 .size chThdYield, .-chThdYield + 533 .section .text.chThdExitS,"ax",%progbits + 534 .align 2 + 535 .p2align 4,,15 + 536 .global chThdExitS + 537 .thumb + 538 .thumb_func + 539 .type chThdExitS, %function + 540 chThdExitS: + 541 .LFB17: + 542 .loc 1 363 0 + 543 .cfi_startproc + 544 @ args = 0, pretend = 0, frame = 0 + 545 @ frame_needed = 0, uses_anonymous_args = 0 + 546 .LVL25: + 547 0000 38B5 push {r3, r4, r5, lr} + 548 .LCFI9: + 549 .cfi_def_cfa_offset 16 + 550 .cfi_offset 3, -16 + 551 .cfi_offset 4, -12 + 552 .cfi_offset 5, -8 + 553 .cfi_offset 14, -4 + 554 .loc 1 364 0 + 555 0002 0E4B ldr r3, .L32 + 556 0004 DC69 ldr r4, [r3, #28] + 557 .LVL26: + 558 .loc 1 371 0 + 559 0006 2546 mov r5, r4 + 560 0008 55F8283F ldr r3, [r5, #40]! + 561 .loc 1 366 0 + 562 000c 6062 str r0, [r4, #36] + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 11 + + + 563 .loc 1 371 0 + 564 000e AB42 cmp r3, r5 + 565 0010 07D0 beq .L29 + 566 .LVL27: + 567 .L30: + 568 .LBB20: + 569 .LBB21: + 570 .file 2 "../..//os/kernel/include/chinline.h" + 571 .loc 2 89 0 + 572 0012 1A68 ldr r2, [r3, #0] + 573 .LBE21: + 574 .LBE20: + 575 .loc 1 372 0 + 576 0014 1846 mov r0, r3 + 577 .LBB23: + 578 .LBB22: + 579 .loc 2 89 0 + 580 0016 A262 str r2, [r4, #40] + 581 .LBE22: + 582 .LBE23: + 583 .loc 1 372 0 + 584 0018 FFF7FEFF bl chSchReadyI + 585 .LVL28: + 586 .loc 1 371 0 + 587 001c A36A ldr r3, [r4, #40] + 588 001e AB42 cmp r3, r5 + 589 0020 F7D1 bne .L30 + 590 .LVL29: + 591 .L29: + 592 .loc 1 377 0 + 593 0022 637F ldrb r3, [r4, #29] @ zero_extendqisi2 + 594 0024 9B07 lsls r3, r3, #30 + 595 0026 04D1 bne .L27 + 596 .loc 1 378 0 + 597 0028 6369 ldr r3, [r4, #20] + 598 002a 2269 ldr r2, [r4, #16] + 599 002c 1A61 str r2, [r3, #16] + 600 002e 2269 ldr r2, [r4, #16] + 601 0030 5361 str r3, [r2, #20] + 602 .L27: + 603 .loc 1 380 0 + 604 0032 0E20 movs r0, #14 + 605 .loc 1 383 0 + 606 0034 BDE83840 pop {r3, r4, r5, lr} + 607 .loc 1 380 0 + 608 0038 FFF7FEBF b chSchGoSleepS + 609 .LVL30: + 610 .L33: + 611 .align 2 + 612 .L32: + 613 003c 00000000 .word rlist + 614 .cfi_endproc + 615 .LFE17: + 616 .size chThdExitS, .-chThdExitS + 617 .section .text.chThdExit,"ax",%progbits + 618 .align 2 + 619 .p2align 4,,15 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 12 + + + 620 .global chThdExit + 621 .thumb + 622 .thumb_func + 623 .type chThdExit, %function + 624 chThdExit: + 625 .LFB16: + 626 .loc 1 342 0 + 627 .cfi_startproc + 628 @ args = 0, pretend = 0, frame = 0 + 629 @ frame_needed = 0, uses_anonymous_args = 0 + 630 @ link register save eliminated. + 631 .LVL31: + 632 .loc 1 344 0 + 633 @ 344 "../..//os/kernel/src/chthreads.c" 1 + 634 0000 72B6 cpsid i + 635 @ 0 "" 2 + 636 .loc 1 347 0 + 637 .thumb + 638 .loc 1 345 0 + 639 0002 FFF7FEBF b chThdExitS + 640 .LVL32: + 641 .cfi_endproc + 642 .LFE16: + 643 .size chThdExit, .-chThdExit + 644 0006 00BFAFF3 .section .text.chThdWait,"ax",%progbits + 644 0080AFF3 + 644 0080 + 645 .align 2 + 646 .p2align 4,,15 + 647 .global chThdWait + 648 .thumb + 649 .thumb_func + 650 .type chThdWait, %function + 651 chThdWait: + 652 .LFB18: + 653 .loc 1 417 0 + 654 .cfi_startproc + 655 @ args = 0, pretend = 0, frame = 0 + 656 @ frame_needed = 0, uses_anonymous_args = 0 + 657 .LVL33: + 658 0000 38B5 push {r3, r4, r5, lr} + 659 .LCFI10: + 660 .cfi_def_cfa_offset 16 + 661 .cfi_offset 3, -16 + 662 .cfi_offset 4, -12 + 663 .cfi_offset 5, -8 + 664 .cfi_offset 14, -4 + 665 .loc 1 417 0 + 666 0002 0446 mov r4, r0 + 667 .loc 1 422 0 + 668 @ 422 "../..//os/kernel/src/chthreads.c" 1 + 669 0004 72B6 cpsid i + 670 @ 0 "" 2 + 671 .loc 1 427 0 + 672 .thumb + 673 0006 037F ldrb r3, [r0, #28] @ zero_extendqisi2 + 674 0008 0E2B cmp r3, #14 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 13 + + + 675 000a 07D0 beq .L36 + 676 .loc 1 428 0 + 677 000c 074B ldr r3, .L40 + 678 .LBB24: + 679 .LBB25: + 680 .loc 2 82 0 + 681 000e 826A ldr r2, [r0, #40] + 682 .LBE25: + 683 .LBE24: + 684 .loc 1 428 0 + 685 0010 DB69 ldr r3, [r3, #28] + 686 .LVL34: + 687 .loc 1 429 0 + 688 0012 0720 movs r0, #7 + 689 .LVL35: + 690 .LBB27: + 691 .LBB26: + 692 .loc 2 82 0 + 693 0014 1A60 str r2, [r3, #0] + 694 .loc 2 83 0 + 695 0016 A362 str r3, [r4, #40] + 696 .LBE26: + 697 .LBE27: + 698 .loc 1 429 0 + 699 0018 FFF7FEFF bl chSchGoSleepS + 700 .LVL36: + 701 .L36: + 702 .loc 1 431 0 + 703 001c 656A ldr r5, [r4, #36] + 704 .LVL37: + 705 .loc 1 432 0 + 706 @ 432 "../..//os/kernel/src/chthreads.c" 1 + 707 001e 62B6 cpsie i + 708 @ 0 "" 2 + 709 .loc 1 434 0 + 710 .thumb + 711 0020 2046 mov r0, r4 + 712 0022 FFF7FEFF bl chThdRelease + 713 .LVL38: + 714 .loc 1 437 0 + 715 0026 2846 mov r0, r5 + 716 0028 38BD pop {r3, r4, r5, pc} + 717 .L41: + 718 002a 00BF .align 2 + 719 .L40: + 720 002c 00000000 .word rlist + 721 .cfi_endproc + 722 .LFE18: + 723 .size chThdWait, .-chThdWait + 724 .text + 725 .Letext0: + 726 .file 3 "c:\\yagarto\\bin\\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h" + 727 .file 4 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 728 .file 5 "../..//os/ports/GCC/ARMCMx/chtypes.h" + 729 .file 6 "../..//os/kernel/include/chlists.h" + 730 .file 7 "../..//os/kernel/include/chthreads.h" + 731 .file 8 "../..//os/ports/GCC/ARMCMx/chcore_v7m.h" + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 14 + + + 732 .file 9 "../..//os/kernel/include/chvt.h" + 733 .file 10 "../..//os/kernel/include/chschd.h" + 734 .file 11 "../..//os/kernel/include/chmtx.h" + 735 .file 12 "../..//os/kernel/include/chdynamic.h" + 736 .section .debug_info,"",%progbits + 737 .Ldebug_info0: + 738 0000 4A0A0000 .4byte 0xa4a + 739 0004 0200 .2byte 0x2 + 740 0006 00000000 .4byte .Ldebug_abbrev0 + 741 000a 04 .byte 0x4 + 742 000b 01 .uleb128 0x1 + 743 000c 74020000 .4byte .LASF98 + 744 0010 01 .byte 0x1 + 745 0011 EB000000 .4byte .LASF99 + 746 0015 1F020000 .4byte .LASF100 + 747 0019 80000000 .4byte .Ldebug_ranges0+0x80 + 748 001d 00000000 .4byte 0 + 749 0021 00000000 .4byte 0 + 750 0025 00000000 .4byte .Ldebug_line0 + 751 0029 02 .uleb128 0x2 + 752 002a 04 .byte 0x4 + 753 002b 05 .byte 0x5 + 754 002c 696E7400 .ascii "int\000" + 755 0030 03 .uleb128 0x3 + 756 0031 0E000000 .4byte .LASF2 + 757 0035 03 .byte 0x3 + 758 0036 D5 .byte 0xd5 + 759 0037 3B000000 .4byte 0x3b + 760 003b 04 .uleb128 0x4 + 761 003c 04 .byte 0x4 + 762 003d 07 .byte 0x7 + 763 003e 35010000 .4byte .LASF0 + 764 0042 04 .uleb128 0x4 + 765 0043 01 .byte 0x1 + 766 0044 06 .byte 0x6 + 767 0045 68000000 .4byte .LASF1 + 768 0049 03 .uleb128 0x3 + 769 004a E8030000 .4byte .LASF3 + 770 004e 04 .byte 0x4 + 771 004f 2A .byte 0x2a + 772 0050 54000000 .4byte 0x54 + 773 0054 04 .uleb128 0x4 + 774 0055 01 .byte 0x1 + 775 0056 08 .byte 0x8 + 776 0057 C1020000 .4byte .LASF4 + 777 005b 04 .uleb128 0x4 + 778 005c 02 .byte 0x2 + 779 005d 05 .byte 0x5 + 780 005e D9020000 .4byte .LASF5 + 781 0062 04 .uleb128 0x4 + 782 0063 02 .byte 0x2 + 783 0064 07 .byte 0x7 + 784 0065 69010000 .4byte .LASF6 + 785 0069 03 .uleb128 0x3 + 786 006a B9020000 .4byte .LASF7 + 787 006e 04 .byte 0x4 + 788 006f 4F .byte 0x4f + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 15 + + + 789 0070 74000000 .4byte 0x74 + 790 0074 04 .uleb128 0x4 + 791 0075 04 .byte 0x4 + 792 0076 05 .byte 0x5 + 793 0077 9B000000 .4byte .LASF8 + 794 007b 03 .uleb128 0x3 + 795 007c 35030000 .4byte .LASF9 + 796 0080 04 .byte 0x4 + 797 0081 50 .byte 0x50 + 798 0082 86000000 .4byte 0x86 + 799 0086 04 .uleb128 0x4 + 800 0087 04 .byte 0x4 + 801 0088 07 .byte 0x7 + 802 0089 4A010000 .4byte .LASF10 + 803 008d 04 .uleb128 0x4 + 804 008e 08 .byte 0x8 + 805 008f 05 .byte 0x5 + 806 0090 5A000000 .4byte .LASF11 + 807 0094 04 .uleb128 0x4 + 808 0095 08 .byte 0x8 + 809 0096 07 .byte 0x7 + 810 0097 33000000 .4byte .LASF12 + 811 009b 03 .uleb128 0x3 + 812 009c 97010000 .4byte .LASF13 + 813 00a0 05 .byte 0x5 + 814 00a1 2F .byte 0x2f + 815 00a2 49000000 .4byte 0x49 + 816 00a6 03 .uleb128 0x3 + 817 00a7 A4000000 .4byte .LASF14 + 818 00ab 05 .byte 0x5 + 819 00ac 30 .byte 0x30 + 820 00ad 49000000 .4byte 0x49 + 821 00b1 03 .uleb128 0x3 + 822 00b2 A2020000 .4byte .LASF15 + 823 00b6 05 .byte 0x5 + 824 00b7 31 .byte 0x31 + 825 00b8 49000000 .4byte 0x49 + 826 00bc 03 .uleb128 0x3 + 827 00bd B1020000 .4byte .LASF16 + 828 00c1 05 .byte 0x5 + 829 00c2 32 .byte 0x32 + 830 00c3 7B000000 .4byte 0x7b + 831 00c7 03 .uleb128 0x3 + 832 00c8 89010000 .4byte .LASF17 + 833 00cc 05 .byte 0x5 + 834 00cd 33 .byte 0x33 + 835 00ce 69000000 .4byte 0x69 + 836 00d2 03 .uleb128 0x3 + 837 00d3 BA010000 .4byte .LASF18 + 838 00d7 05 .byte 0x5 + 839 00d8 35 .byte 0x35 + 840 00d9 7B000000 .4byte 0x7b + 841 00dd 03 .uleb128 0x3 + 842 00de 78030000 .4byte .LASF19 + 843 00e2 05 .byte 0x5 + 844 00e3 36 .byte 0x36 + 845 00e4 7B000000 .4byte 0x7b + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 16 + + + 846 00e8 03 .uleb128 0x3 + 847 00e9 2F010000 .4byte .LASF20 + 848 00ed 05 .byte 0x5 + 849 00ee 37 .byte 0x37 + 850 00ef 69000000 .4byte 0x69 + 851 00f3 03 .uleb128 0x3 + 852 00f4 15030000 .4byte .LASF21 + 853 00f8 06 .byte 0x6 + 854 00f9 2A .byte 0x2a + 855 00fa FE000000 .4byte 0xfe + 856 00fe 05 .uleb128 0x5 + 857 00ff 15030000 .4byte .LASF21 + 858 0103 48 .byte 0x48 + 859 0104 07 .byte 0x7 + 860 0105 5E .byte 0x5e + 861 0106 15020000 .4byte 0x215 + 862 010a 06 .uleb128 0x6 + 863 010b F9020000 .4byte .LASF22 + 864 010f 07 .byte 0x7 + 865 0110 5F .byte 0x5f + 866 0111 3A020000 .4byte 0x23a + 867 0115 02 .byte 0x2 + 868 0116 23 .byte 0x23 + 869 0117 00 .uleb128 0 + 870 0118 06 .uleb128 0x6 + 871 0119 AA020000 .4byte .LASF23 + 872 011d 07 .byte 0x7 + 873 011e 61 .byte 0x61 + 874 011f 3A020000 .4byte 0x23a + 875 0123 02 .byte 0x2 + 876 0124 23 .byte 0x23 + 877 0125 04 .uleb128 0x4 + 878 0126 06 .uleb128 0x6 + 879 0127 53000000 .4byte .LASF24 + 880 012b 07 .byte 0x7 + 881 012c 63 .byte 0x63 + 882 012d BC000000 .4byte 0xbc + 883 0131 02 .byte 0x2 + 884 0132 23 .byte 0x23 + 885 0133 08 .uleb128 0x8 + 886 0134 06 .uleb128 0x6 + 887 0135 42040000 .4byte .LASF25 + 888 0139 07 .byte 0x7 + 889 013a 64 .byte 0x64 + 890 013b 07030000 .4byte 0x307 + 891 013f 02 .byte 0x2 + 892 0140 23 .byte 0x23 + 893 0141 0C .uleb128 0xc + 894 0142 06 .uleb128 0x6 + 895 0143 AD000000 .4byte .LASF26 + 896 0147 07 .byte 0x7 + 897 0148 66 .byte 0x66 + 898 0149 3A020000 .4byte 0x23a + 899 014d 02 .byte 0x2 + 900 014e 23 .byte 0x23 + 901 014f 10 .uleb128 0x10 + 902 0150 06 .uleb128 0x6 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 17 + + + 903 0151 17020000 .4byte .LASF27 + 904 0155 07 .byte 0x7 + 905 0156 67 .byte 0x67 + 906 0157 3A020000 .4byte 0x23a + 907 015b 02 .byte 0x2 + 908 015c 23 .byte 0x23 + 909 015d 14 .uleb128 0x14 + 910 015e 06 .uleb128 0x6 + 911 015f 02040000 .4byte .LASF28 + 912 0163 07 .byte 0x7 + 913 0164 6E .byte 0x6e + 914 0165 F6040000 .4byte 0x4f6 + 915 0169 02 .byte 0x2 + 916 016a 23 .byte 0x23 + 917 016b 18 .uleb128 0x18 + 918 016c 06 .uleb128 0x6 + 919 016d E3020000 .4byte .LASF29 + 920 0171 07 .byte 0x7 + 921 0172 79 .byte 0x79 + 922 0173 A6000000 .4byte 0xa6 + 923 0177 02 .byte 0x2 + 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04d4 11 .uleb128 0x11 + 1403 04d5 4A000000 .4byte .LASF68 + 1404 04d9 07 .byte 0x7 + 1405 04da 9E .byte 0x9e + 1406 04db C7000000 .4byte 0xc7 + 1407 04df 11 .uleb128 0x11 + 1408 04e0 FB030000 .4byte .LASF69 + 1409 04e4 07 .byte 0x7 + 1410 04e5 A5 .byte 0xa5 + 1411 04e6 78020000 .4byte 0x278 + 1412 04ea 11 .uleb128 0x11 + 1413 04eb F2020000 .4byte .LASF70 + 1414 04ef 07 .byte 0x7 + 1415 04f0 AC .byte 0xac + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 26 + + + 1416 04f1 D2000000 .4byte 0xd2 + 1417 04f5 00 .byte 0 + 1418 04f6 09 .uleb128 0x9 + 1419 04f7 04 .byte 0x4 + 1420 04f8 FC040000 .4byte 0x4fc + 1421 04fc 12 .uleb128 0x12 + 1422 04fd 01050000 .4byte 0x501 + 1423 0501 04 .uleb128 0x4 + 1424 0502 01 .byte 0x1 + 1425 0503 08 .byte 0x8 + 1426 0504 60030000 .4byte .LASF71 + 1427 0508 09 .uleb128 0x9 + 1428 0509 04 .byte 0x4 + 1429 050a B6040000 .4byte 0x4b6 + 1430 050e 03 .uleb128 0x3 + 1431 050f 00000000 .4byte .LASF72 + 1432 0513 07 .byte 0x7 + 1433 0514 DF .byte 0xdf + 1434 0515 19050000 .4byte 0x519 + 1435 0519 09 .uleb128 0x9 + 1436 051a 04 .byte 0x4 + 1437 051b 1F050000 .4byte 0x51f + 1438 051f 13 .uleb128 0x13 + 1439 0520 01 .byte 0x1 + 1440 0521 C7000000 .4byte 0xc7 + 1441 0525 2F050000 .4byte 0x52f + 1442 0529 0E .uleb128 0xe + 1443 052a 78020000 .4byte 0x278 + 1444 052e 00 .byte 0 + 1445 052f 14 .uleb128 0x14 + 1446 0530 01 .byte 0x1 + 1447 0531 3E030000 .4byte .LASF91 + 1448 0535 01 .byte 0x1 + 1449 0536 4C .byte 0x4c + 1450 0537 01 .byte 0x1 + 1451 0538 3A020000 .4byte 0x23a + 1452 053c 01 .byte 0x1 + 1453 053d 57050000 .4byte 0x557 + 1454 0541 15 .uleb128 0x15 + 1455 0542 747000 .ascii "tp\000" + 1456 0545 01 .byte 0x1 + 1457 0546 4C .byte 0x4c + 1458 0547 3A020000 .4byte 0x23a + 1459 054b 16 .uleb128 0x16 + 1460 054c 15000000 .4byte .LASF73 + 1461 0550 01 .byte 0x1 + 1462 0551 4C .byte 0x4c + 1463 0552 BC000000 .4byte 0xbc + 1464 0556 00 .byte 0 + 1465 0557 17 .uleb128 0x17 + 1466 0558 B5000000 .4byte .LASF101 + 1467 055c 02 .byte 0x2 + 1468 055d 56 .byte 0x56 + 1469 055e 01 .byte 0x1 + 1470 055f 3A020000 .4byte 0x23a + 1471 0563 03 .byte 0x3 + 1472 0564 7E050000 .4byte 0x57e + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 27 + + + 1473 0568 15 .uleb128 0x15 + 1474 0569 746C7000 .ascii "tlp\000" + 1475 056d 02 .byte 0x2 + 1476 056e 56 .byte 0x56 + 1477 056f 7E050000 .4byte 0x57e + 1478 0573 18 .uleb128 0x18 + 1479 0574 747000 .ascii "tp\000" + 1480 0577 02 .byte 0x2 + 1481 0578 58 .byte 0x58 + 1482 0579 3A020000 .4byte 0x23a + 1483 057d 00 .byte 0 + 1484 057e 09 .uleb128 0x9 + 1485 057f 04 .byte 0x4 + 1486 0580 62020000 .4byte 0x262 + 1487 0584 19 .uleb128 0x19 + 1488 0585 E6010000 .4byte .LASF102 + 1489 0589 02 .byte 0x2 + 1490 058a 50 .byte 0x50 + 1491 058b 01 .byte 0x1 + 1492 058c 03 .byte 0x3 + 1493 058d A7050000 .4byte 0x5a7 + 1494 0591 15 .uleb128 0x15 + 1495 0592 747000 .ascii "tp\000" + 1496 0595 02 .byte 0x2 + 1497 0596 50 .byte 0x50 + 1498 0597 3A020000 .4byte 0x23a + 1499 059b 15 .uleb128 0x15 + 1500 059c 746C7000 .ascii "tlp\000" + 1501 05a0 02 .byte 0x2 + 1502 05a1 50 .byte 0x50 + 1503 05a2 7E050000 .4byte 0x57e + 1504 05a6 00 .byte 0 + 1505 05a7 1A .uleb128 0x1a + 1506 05a8 2F050000 .4byte 0x52f + 1507 05ac 00000000 .4byte .LFB7 + 1508 05b0 42000000 .4byte .LFE7 + 1509 05b4 00000000 .4byte .LLST0 + 1510 05b8 01 .byte 0x1 + 1511 05b9 CE050000 .4byte 0x5ce + 1512 05bd 1B .uleb128 0x1b + 1513 05be 41050000 .4byte 0x541 + 1514 05c2 01 .byte 0x1 + 1515 05c3 50 .byte 0x50 + 1516 05c4 1C .uleb128 0x1c + 1517 05c5 4B050000 .4byte 0x54b + 1518 05c9 20000000 .4byte .LLST1 + 1519 05cd 00 .byte 0 + 1520 05ce 1D .uleb128 0x1d + 1521 05cf 01 .byte 0x1 + 1522 05d0 8E000000 .4byte .LASF75 + 1523 05d4 01 .byte 0x1 + 1524 05d5 9A .byte 0x9a + 1525 05d6 01 .byte 0x1 + 1526 05d7 3A020000 .4byte 0x23a + 1527 05db 00000000 .4byte .LFB8 + 1528 05df 68000000 .4byte .LFE8 + 1529 05e3 3F000000 .4byte .LLST2 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 28 + + + 1530 05e7 01 .byte 0x1 + 1531 05e8 5E060000 .4byte 0x65e + 1532 05ec 1E .uleb128 0x1e + 1533 05ed 77737000 .ascii "wsp\000" + 1534 05f1 01 .byte 0x1 + 1535 05f2 9A .byte 0x9a + 1536 05f3 78020000 .4byte 0x278 + 1537 05f7 01 .byte 0x1 + 1538 05f8 50 .byte 0x50 + 1539 05f9 1F .uleb128 0x1f + 1540 05fa 64010000 .4byte .LASF74 + 1541 05fe 01 .byte 0x1 + 1542 05ff 9A .byte 0x9a + 1543 0600 30000000 .4byte 0x30 + 1544 0604 5F000000 .4byte .LLST3 + 1545 0608 1F .uleb128 0x1f + 1546 0609 15000000 .4byte .LASF73 + 1547 060d 01 .byte 0x1 + 1548 060e 9B .byte 0x9b + 1549 060f BC000000 .4byte 0xbc + 1550 0613 7F000000 .4byte .LLST4 + 1551 0617 20 .uleb128 0x20 + 1552 0618 706600 .ascii "pf\000" + 1553 061b 01 .byte 0x1 + 1554 061c 9B .byte 0x9b + 1555 061d 0E050000 .4byte 0x50e + 1556 0621 9D000000 .4byte .LLST5 + 1557 0625 1E .uleb128 0x1e + 1558 0626 61726700 .ascii "arg\000" + 1559 062a 01 .byte 0x1 + 1560 062b 9B .byte 0x9b + 1561 062c 78020000 .4byte 0x278 + 1562 0630 02 .byte 0x2 + 1563 0631 91 .byte 0x91 + 1564 0632 00 .sleb128 0 + 1565 0633 21 .uleb128 0x21 + 1566 0634 747000 .ascii "tp\000" + 1567 0637 01 .byte 0x1 + 1568 0638 9D .byte 0x9d + 1569 0639 3A020000 .4byte 0x23a + 1570 063d 01 .byte 0x1 + 1571 063e 50 .byte 0x50 + 1572 063f 22 .uleb128 0x22 + 1573 0640 2F050000 .4byte 0x52f + 1574 0644 06000000 .4byte .LBB8 + 1575 0648 00000000 .4byte .Ldebug_ranges0+0 + 1576 064c 01 .byte 0x1 + 1577 064d A5 .byte 0xa5 + 1578 064e 1B .uleb128 0x1b + 1579 064f 4B050000 .4byte 0x54b + 1580 0653 01 .byte 0x1 + 1581 0654 58 .byte 0x58 + 1582 0655 1B .uleb128 0x1b + 1583 0656 41050000 .4byte 0x541 + 1584 065a 01 .byte 0x1 + 1585 065b 50 .byte 0x50 + 1586 065c 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 29 + + + 1587 065d 00 .byte 0 + 1588 065e 1D .uleb128 0x1d + 1589 065f 01 .byte 0x1 + 1590 0660 D4010000 .4byte .LASF76 + 1591 0664 01 .byte 0x1 + 1592 0665 B8 .byte 0xb8 + 1593 0666 01 .byte 0x1 + 1594 0667 3A020000 .4byte 0x23a + 1595 066b 00000000 .4byte .LFB9 + 1596 066f 1E000000 .4byte .LFE9 + 1597 0673 BC000000 .4byte .LLST6 + 1598 0677 01 .byte 0x1 + 1599 0678 1A070000 .4byte 0x71a + 1600 067c 20 .uleb128 0x20 + 1601 067d 77737000 .ascii "wsp\000" + 1602 0681 01 .byte 0x1 + 1603 0682 B8 .byte 0xb8 + 1604 0683 78020000 .4byte 0x278 + 1605 0687 E8000000 .4byte .LLST7 + 1606 068b 1F .uleb128 0x1f + 1607 068c 64010000 .4byte .LASF74 + 1608 0690 01 .byte 0x1 + 1609 0691 B8 .byte 0xb8 + 1610 0692 30000000 .4byte 0x30 + 1611 0696 09010000 .4byte .LLST8 + 1612 069a 1F .uleb128 0x1f + 1613 069b 15000000 .4byte .LASF73 + 1614 069f 01 .byte 0x1 + 1615 06a0 B9 .byte 0xb9 + 1616 06a1 BC000000 .4byte 0xbc + 1617 06a5 2A010000 .4byte .LLST9 + 1618 06a9 20 .uleb128 0x20 + 1619 06aa 706600 .ascii "pf\000" + 1620 06ad 01 .byte 0x1 + 1621 06ae B9 .byte 0xb9 + 1622 06af 0E050000 .4byte 0x50e + 1623 06b3 4B010000 .4byte .LLST10 + 1624 06b7 1E .uleb128 0x1e + 1625 06b8 61726700 .ascii "arg\000" + 1626 06bc 01 .byte 0x1 + 1627 06bd B9 .byte 0xb9 + 1628 06be 78020000 .4byte 0x278 + 1629 06c2 02 .byte 0x2 + 1630 06c3 91 .byte 0x91 + 1631 06c4 00 .sleb128 0 + 1632 06c5 23 .uleb128 0x23 + 1633 06c6 747000 .ascii "tp\000" + 1634 06c9 01 .byte 0x1 + 1635 06ca BA .byte 0xba + 1636 06cb 3A020000 .4byte 0x23a + 1637 06cf 6C010000 .4byte .LLST11 + 1638 06d3 24 .uleb128 0x24 + 1639 06d4 0E000000 .4byte .LVL8 + 1640 06d8 CE050000 .4byte 0x5ce + 1641 06dc 04070000 .4byte 0x704 + 1642 06e0 25 .uleb128 0x25 + 1643 06e1 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 30 + + + 1644 06e2 53 .byte 0x53 + 1645 06e3 03 .byte 0x3 + 1646 06e4 F3 .byte 0xf3 + 1647 06e5 01 .uleb128 0x1 + 1648 06e6 53 .byte 0x53 + 1649 06e7 25 .uleb128 0x25 + 1650 06e8 01 .byte 0x1 + 1651 06e9 52 .byte 0x52 + 1652 06ea 03 .byte 0x3 + 1653 06eb F3 .byte 0xf3 + 1654 06ec 01 .uleb128 0x1 + 1655 06ed 52 .byte 0x52 + 1656 06ee 25 .uleb128 0x25 + 1657 06ef 01 .byte 0x1 + 1658 06f0 51 .byte 0x51 + 1659 06f1 03 .byte 0x3 + 1660 06f2 F3 .byte 0xf3 + 1661 06f3 01 .uleb128 0x1 + 1662 06f4 51 .byte 0x51 + 1663 06f5 25 .uleb128 0x25 + 1664 06f6 01 .byte 0x1 + 1665 06f7 50 .byte 0x50 + 1666 06f8 03 .byte 0x3 + 1667 06f9 F3 .byte 0xf3 + 1668 06fa 01 .uleb128 0x1 + 1669 06fb 50 .byte 0x50 + 1670 06fc 25 .uleb128 0x25 + 1671 06fd 02 .byte 0x2 + 1672 06fe 7D .byte 0x7d + 1673 06ff 00 .sleb128 0 + 1674 0700 02 .byte 0x2 + 1675 0701 74 .byte 0x74 + 1676 0702 00 .sleb128 0 + 1677 0703 00 .byte 0 + 1678 0704 26 .uleb128 0x26 + 1679 0705 16000000 .4byte .LVL10 + 1680 0709 C7090000 .4byte 0x9c7 + 1681 070d 25 .uleb128 0x25 + 1682 070e 01 .byte 0x1 + 1683 070f 51 .byte 0x51 + 1684 0710 01 .byte 0x1 + 1685 0711 30 .byte 0x30 + 1686 0712 25 .uleb128 0x25 + 1687 0713 01 .byte 0x1 + 1688 0714 50 .byte 0x50 + 1689 0715 02 .byte 0x2 + 1690 0716 74 .byte 0x74 + 1691 0717 00 .sleb128 0 + 1692 0718 00 .byte 0 + 1693 0719 00 .byte 0 + 1694 071a 1D .uleb128 0x1d + 1695 071b 01 .byte 0x1 + 1696 071c 1E010000 .4byte .LASF77 + 1697 0720 01 .byte 0x1 + 1698 0721 D6 .byte 0xd6 + 1699 0722 01 .byte 0x1 + 1700 0723 BC000000 .4byte 0xbc + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 31 + + + 1701 0727 00000000 .4byte .LFB10 + 1702 072b 28000000 .4byte .LFE10 + 1703 072f 8A010000 .4byte .LLST12 + 1704 0733 01 .byte 0x1 + 1705 0734 5E070000 .4byte 0x75e + 1706 0738 1F .uleb128 0x1f + 1707 0739 8F010000 .4byte .LASF78 + 1708 073d 01 .byte 0x1 + 1709 073e D6 .byte 0xd6 + 1710 073f BC000000 .4byte 0xbc + 1711 0743 AA010000 .4byte .LLST13 + 1712 0747 27 .uleb128 0x27 + 1713 0748 CC010000 .4byte .LASF79 + 1714 074c 01 .byte 0x1 + 1715 074d D7 .byte 0xd7 + 1716 074e BC000000 .4byte 0xbc + 1717 0752 01 .byte 0x1 + 1718 0753 54 .byte 0x54 + 1719 0754 28 .uleb128 0x28 + 1720 0755 1C000000 .4byte .LVL13 + 1721 0759 E0090000 .4byte 0x9e0 + 1722 075d 00 .byte 0 + 1723 075e 1D .uleb128 0x1d + 1724 075f 01 .byte 0x1 + 1725 0760 0B020000 .4byte .LASF80 + 1726 0764 01 .byte 0x1 + 1727 0765 F7 .byte 0xf7 + 1728 0766 01 .byte 0x1 + 1729 0767 3A020000 .4byte 0x23a + 1730 076b 00000000 .4byte .LFB11 + 1731 076f 12000000 .4byte .LFE11 + 1732 0773 CB010000 .4byte .LLST14 + 1733 0777 01 .byte 0x1 + 1734 0778 A0070000 .4byte 0x7a0 + 1735 077c 20 .uleb128 0x20 + 1736 077d 747000 .ascii "tp\000" + 1737 0780 01 .byte 0x1 + 1738 0781 F7 .byte 0xf7 + 1739 0782 3A020000 .4byte 0x23a + 1740 0786 EB010000 .4byte .LLST15 + 1741 078a 26 .uleb128 0x26 + 1742 078b 0C000000 .4byte .LVL15 + 1743 078f C7090000 .4byte 0x9c7 + 1744 0793 25 .uleb128 0x25 + 1745 0794 01 .byte 0x1 + 1746 0795 51 .byte 0x51 + 1747 0796 01 .byte 0x1 + 1748 0797 30 .byte 0x30 + 1749 0798 25 .uleb128 0x25 + 1750 0799 01 .byte 0x1 + 1751 079a 50 .byte 0x50 + 1752 079b 02 .byte 0x2 + 1753 079c 74 .byte 0x74 + 1754 079d 00 .sleb128 0 + 1755 079e 00 .byte 0 + 1756 079f 00 .byte 0 + 1757 07a0 29 .uleb128 0x29 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 32 + + + 1758 07a1 01 .byte 0x1 + 1759 07a2 9F010000 .4byte .LASF81 + 1760 07a6 01 .byte 0x1 + 1761 07a7 0E01 .2byte 0x10e + 1762 07a9 01 .byte 0x1 + 1763 07aa 00000000 .4byte .LFB12 + 1764 07ae 0E000000 .4byte .LFE12 + 1765 07b2 02 .byte 0x2 + 1766 07b3 7D .byte 0x7d + 1767 07b4 00 .sleb128 0 + 1768 07b5 01 .byte 0x1 + 1769 07b6 C8070000 .4byte 0x7c8 + 1770 07ba 2A .uleb128 0x2a + 1771 07bb 747000 .ascii "tp\000" + 1772 07be 01 .byte 0x1 + 1773 07bf 0E01 .2byte 0x10e + 1774 07c1 3A020000 .4byte 0x23a + 1775 07c5 01 .byte 0x1 + 1776 07c6 50 .byte 0x50 + 1777 07c7 00 .byte 0 + 1778 07c8 2B .uleb128 0x2b + 1779 07c9 01 .byte 0x1 + 1780 07ca C6030000 .4byte .LASF82 + 1781 07ce 01 .byte 0x1 + 1782 07cf 2101 .2byte 0x121 + 1783 07d1 01 .byte 0x1 + 1784 07d2 00000000 .4byte .LFB13 + 1785 07d6 10000000 .4byte .LFE13 + 1786 07da 09020000 .4byte .LLST16 + 1787 07de 01 .byte 0x1 + 1788 07df 0A080000 .4byte 0x80a + 1789 07e3 2C .uleb128 0x2c + 1790 07e4 6F020000 .4byte .LASF83 + 1791 07e8 01 .byte 0x1 + 1792 07e9 2101 .2byte 0x121 + 1793 07eb DD000000 .4byte 0xdd + 1794 07ef 29020000 .4byte .LLST17 + 1795 07f3 26 .uleb128 0x26 + 1796 07f4 0C000000 .4byte .LVL19 + 1797 07f8 EA090000 .4byte 0x9ea + 1798 07fc 25 .uleb128 0x25 + 1799 07fd 01 .byte 0x1 + 1800 07fe 51 .byte 0x51 + 1801 07ff 03 .byte 0x3 + 1802 0800 F3 .byte 0xf3 + 1803 0801 01 .uleb128 0x1 + 1804 0802 50 .byte 0x50 + 1805 0803 25 .uleb128 0x25 + 1806 0804 01 .byte 0x1 + 1807 0805 50 .byte 0x50 + 1808 0806 01 .byte 0x1 + 1809 0807 36 .byte 0x36 + 1810 0808 00 .byte 0 + 1811 0809 00 .byte 0 + 1812 080a 2B .uleb128 0x2b + 1813 080b 01 .byte 0x1 + 1814 080c 92020000 .4byte .LASF84 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 33 + + + 1815 0810 01 .byte 0x1 + 1816 0811 3201 .2byte 0x132 + 1817 0813 01 .byte 0x1 + 1818 0814 00000000 .4byte .LFB14 + 1819 0818 1C000000 .4byte .LFE14 + 1820 081c 55020000 .4byte .LLST18 + 1821 0820 01 .byte 0x1 + 1822 0821 45080000 .4byte 0x845 + 1823 0825 2C .uleb128 0x2c + 1824 0826 6F020000 .4byte .LASF83 + 1825 082a 01 .byte 0x1 + 1826 082b 3201 .2byte 0x132 + 1827 082d DD000000 .4byte 0xdd + 1828 0831 75020000 .4byte .LLST19 + 1829 0835 26 .uleb128 0x26 + 1830 0836 12000000 .4byte .LVL23 + 1831 083a EA090000 .4byte 0x9ea + 1832 083e 25 .uleb128 0x25 + 1833 083f 01 .byte 0x1 + 1834 0840 50 .byte 0x50 + 1835 0841 01 .byte 0x1 + 1836 0842 36 .byte 0x36 + 1837 0843 00 .byte 0 + 1838 0844 00 .byte 0 + 1839 0845 2B .uleb128 0x2b + 1840 0846 01 .byte 0x1 + 1841 0847 F0030000 .4byte .LASF85 + 1842 084b 01 .byte 0x1 + 1843 084c 4101 .2byte 0x141 + 1844 084e 01 .byte 0x1 + 1845 084f 00000000 .4byte .LFB15 + 1846 0853 20000000 .4byte .LFE15 + 1847 0857 A3020000 .4byte .LLST20 + 1848 085b 01 .byte 0x1 + 1849 085c 6A080000 .4byte 0x86a + 1850 0860 28 .uleb128 0x28 + 1851 0861 16000000 .4byte .LVL24 + 1852 0865 070A0000 .4byte 0xa07 + 1853 0869 00 .byte 0 + 1854 086a 2B .uleb128 0x2b + 1855 086b 01 .byte 0x1 + 1856 086c 28000000 .4byte .LASF86 + 1857 0870 01 .byte 0x1 + 1858 0871 6B01 .2byte 0x16b + 1859 0873 01 .byte 0x1 + 1860 0874 00000000 .4byte .LFB17 + 1861 0878 40000000 .4byte .LFE17 + 1862 087c C3020000 .4byte .LLST21 + 1863 0880 01 .byte 0x1 + 1864 0881 E9080000 .4byte 0x8e9 + 1865 0885 2D .uleb128 0x2d + 1866 0886 6D736700 .ascii "msg\000" + 1867 088a 01 .byte 0x1 + 1868 088b 6B01 .2byte 0x16b + 1869 088d C7000000 .4byte 0xc7 + 1870 0891 E3020000 .4byte .LLST22 + 1871 0895 2E .uleb128 0x2e + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 34 + + + 1872 0896 747000 .ascii "tp\000" + 1873 0899 01 .byte 0x1 + 1874 089a 6C01 .2byte 0x16c + 1875 089c 3A020000 .4byte 0x23a + 1876 08a0 01 .byte 0x1 + 1877 08a1 54 .byte 0x54 + 1878 08a2 2F .uleb128 0x2f + 1879 08a3 57050000 .4byte 0x557 + 1880 08a7 12000000 .4byte .LBB20 + 1881 08ab 38000000 .4byte .Ldebug_ranges0+0x38 + 1882 08af 01 .byte 0x1 + 1883 08b0 7401 .2byte 0x174 + 1884 08b2 CF080000 .4byte 0x8cf + 1885 08b6 1C .uleb128 0x1c + 1886 08b7 68050000 .4byte 0x568 + 1887 08bb 04030000 .4byte .LLST23 + 1888 08bf 30 .uleb128 0x30 + 1889 08c0 50000000 .4byte .Ldebug_ranges0+0x50 + 1890 08c4 31 .uleb128 0x31 + 1891 08c5 73050000 .4byte 0x573 + 1892 08c9 19030000 .4byte .LLST24 + 1893 08cd 00 .byte 0 + 1894 08ce 00 .byte 0 + 1895 08cf 28 .uleb128 0x28 + 1896 08d0 1C000000 .4byte .LVL28 + 1897 08d4 110A0000 .4byte 0xa11 + 1898 08d8 32 .uleb128 0x32 + 1899 08d9 3C000000 .4byte .LVL30 + 1900 08dd 01 .byte 0x1 + 1901 08de 290A0000 .4byte 0xa29 + 1902 08e2 25 .uleb128 0x25 + 1903 08e3 01 .byte 0x1 + 1904 08e4 50 .byte 0x50 + 1905 08e5 01 .byte 0x1 + 1906 08e6 3E .byte 0x3e + 1907 08e7 00 .byte 0 + 1908 08e8 00 .byte 0 + 1909 08e9 29 .uleb128 0x29 + 1910 08ea 01 .byte 0x1 + 1911 08eb 74000000 .4byte .LASF87 + 1912 08ef 01 .byte 0x1 + 1913 08f0 5601 .2byte 0x156 + 1914 08f2 01 .byte 0x1 + 1915 08f3 00000000 .4byte .LFB16 + 1916 08f7 06000000 .4byte .LFE16 + 1917 08fb 02 .byte 0x2 + 1918 08fc 7D .byte 0x7d + 1919 08fd 00 .sleb128 0 + 1920 08fe 01 .byte 0x1 + 1921 08ff 26090000 .4byte 0x926 + 1922 0903 2D .uleb128 0x2d + 1923 0904 6D736700 .ascii "msg\000" + 1924 0908 01 .byte 0x1 + 1925 0909 5601 .2byte 0x156 + 1926 090b C7000000 .4byte 0xc7 + 1927 090f 2C030000 .4byte .LLST25 + 1928 0913 32 .uleb128 0x32 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 35 + + + 1929 0914 06000000 .4byte .LVL32 + 1930 0918 01 .byte 0x1 + 1931 0919 6A080000 .4byte 0x86a + 1932 091d 25 .uleb128 0x25 + 1933 091e 01 .byte 0x1 + 1934 091f 50 .byte 0x50 + 1935 0920 03 .byte 0x3 + 1936 0921 F3 .byte 0xf3 + 1937 0922 01 .uleb128 0x1 + 1938 0923 50 .byte 0x50 + 1939 0924 00 .byte 0 + 1940 0925 00 .byte 0 + 1941 0926 33 .uleb128 0x33 + 1942 0927 01 .byte 0x1 + 1943 0928 B5030000 .4byte .LASF88 + 1944 092c 01 .byte 0x1 + 1945 092d A101 .2byte 0x1a1 + 1946 092f 01 .byte 0x1 + 1947 0930 C7000000 .4byte 0xc7 + 1948 0934 00000000 .4byte .LFB18 + 1949 0938 30000000 .4byte .LFE18 + 1950 093c 4D030000 .4byte .LLST26 + 1951 0940 01 .byte 0x1 + 1952 0941 AD090000 .4byte 0x9ad + 1953 0945 2D .uleb128 0x2d + 1954 0946 747000 .ascii "tp\000" + 1955 0949 01 .byte 0x1 + 1956 094a A101 .2byte 0x1a1 + 1957 094c 3A020000 .4byte 0x23a + 1958 0950 6D030000 .4byte .LLST27 + 1959 0954 2E .uleb128 0x2e + 1960 0955 6D736700 .ascii "msg\000" + 1961 0959 01 .byte 0x1 + 1962 095a A201 .2byte 0x1a2 + 1963 095c C7000000 .4byte 0xc7 + 1964 0960 01 .byte 0x1 + 1965 0961 55 .byte 0x55 + 1966 0962 2F .uleb128 0x2f + 1967 0963 84050000 .4byte 0x584 + 1968 0967 0E000000 .4byte .LBB24 + 1969 096b 68000000 .4byte .Ldebug_ranges0+0x68 + 1970 096f 01 .byte 0x1 + 1971 0970 AC01 .2byte 0x1ac + 1972 0972 89090000 .4byte 0x989 + 1973 0976 1C .uleb128 0x1c + 1974 0977 9B050000 .4byte 0x59b + 1975 097b 8B030000 .4byte .LLST28 + 1976 097f 1C .uleb128 0x1c + 1977 0980 91050000 .4byte 0x591 + 1978 0984 AD030000 .4byte .LLST29 + 1979 0988 00 .byte 0 + 1980 0989 24 .uleb128 0x24 + 1981 098a 1C000000 .4byte .LVL36 + 1982 098e 290A0000 .4byte 0xa29 + 1983 0992 9C090000 .4byte 0x99c + 1984 0996 25 .uleb128 0x25 + 1985 0997 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 36 + + + 1986 0998 50 .byte 0x50 + 1987 0999 01 .byte 0x1 + 1988 099a 37 .byte 0x37 + 1989 099b 00 .byte 0 + 1990 099c 26 .uleb128 0x26 + 1991 099d 26000000 .4byte .LVL38 + 1992 09a1 3D0A0000 .4byte 0xa3d + 1993 09a5 25 .uleb128 0x25 + 1994 09a6 01 .byte 0x1 + 1995 09a7 50 .byte 0x50 + 1996 09a8 02 .byte 0x2 + 1997 09a9 74 .byte 0x74 + 1998 09aa 00 .sleb128 0 + 1999 09ab 00 .byte 0 + 2000 09ac 00 .byte 0 + 2001 09ad 34 .uleb128 0x34 + 2002 09ae 21000000 .4byte .LASF89 + 2003 09b2 09 .byte 0x9 + 2004 09b3 88 .byte 0x88 + 2005 09b4 F8030000 .4byte 0x3f8 + 2006 09b8 01 .byte 0x1 + 2007 09b9 01 .byte 0x1 + 2008 09ba 34 .uleb128 0x34 + 2009 09bb E2030000 .4byte .LASF90 + 2010 09bf 0A .byte 0xa + 2011 09c0 72 .byte 0x72 + 2012 09c1 6E040000 .4byte 0x46e + 2013 09c5 01 .byte 0x1 + 2014 09c6 01 .byte 0x1 + 2015 09c7 35 .uleb128 0x35 + 2016 09c8 01 .byte 0x1 + 2017 09c9 7C010000 .4byte .LASF96 + 2018 09cd 0A .byte 0xa + 2019 09ce 9C .byte 0x9c + 2020 09cf 01 .byte 0x1 + 2021 09d0 01 .byte 0x1 + 2022 09d1 E0090000 .4byte 0x9e0 + 2023 09d5 0E .uleb128 0xe + 2024 09d6 3A020000 .4byte 0x23a + 2025 09da 0E .uleb128 0xe + 2026 09db C7000000 .4byte 0xc7 + 2027 09df 00 .byte 0 + 2028 09e0 36 .uleb128 0x36 + 2029 09e1 01 .byte 0x1 + 2030 09e2 C1000000 .4byte .LASF93 + 2031 09e6 0A .byte 0xa + 2032 09e7 9F .byte 0x9f + 2033 09e8 01 .byte 0x1 + 2034 09e9 01 .byte 0x1 + 2035 09ea 37 .uleb128 0x37 + 2036 09eb 01 .byte 0x1 + 2037 09ec 14040000 .4byte .LASF92 + 2038 09f0 0A .byte 0xa + 2039 09f1 99 .byte 0x99 + 2040 09f2 01 .byte 0x1 + 2041 09f3 C7000000 .4byte 0xc7 + 2042 09f7 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 37 + + + 2043 09f8 070A0000 .4byte 0xa07 + 2044 09fc 0E .uleb128 0xe + 2045 09fd A6000000 .4byte 0xa6 + 2046 0a01 0E .uleb128 0xe + 2047 0a02 DD000000 .4byte 0xdd + 2048 0a06 00 .byte 0 + 2049 0a07 36 .uleb128 0x36 + 2050 0a08 01 .byte 0x1 + 2051 0a09 0C010000 .4byte .LASF94 + 2052 0a0d 0A .byte 0xa + 2053 0a0e A5 .byte 0xa5 + 2054 0a0f 01 .byte 0x1 + 2055 0a10 01 .byte 0x1 + 2056 0a11 37 .uleb128 0x37 + 2057 0a12 01 .byte 0x1 + 2058 0a13 65030000 .4byte .LASF95 + 2059 0a17 0A .byte 0xa + 2060 0a18 93 .byte 0x93 + 2061 0a19 01 .byte 0x1 + 2062 0a1a 3A020000 .4byte 0x23a + 2063 0a1e 01 .byte 0x1 + 2064 0a1f 290A0000 .4byte 0xa29 + 2065 0a23 0E .uleb128 0xe + 2066 0a24 3A020000 .4byte 0x23a + 2067 0a28 00 .byte 0 + 2068 0a29 35 .uleb128 0x35 + 2069 0a2a 01 .byte 0x1 + 2070 0a2b 1C030000 .4byte .LASF97 + 2071 0a2f 0A .byte 0xa + 2072 0a30 96 .byte 0x96 + 2073 0a31 01 .byte 0x1 + 2074 0a32 01 .byte 0x1 + 2075 0a33 3D0A0000 .4byte 0xa3d + 2076 0a37 0E .uleb128 0xe + 2077 0a38 A6000000 .4byte 0xa6 + 2078 0a3c 00 .byte 0 + 2079 0a3d 38 .uleb128 0x38 + 2080 0a3e 01 .byte 0x1 + 2081 0a3f 08030000 .4byte .LASF103 + 2082 0a43 0C .byte 0xc + 2083 0a44 3A .byte 0x3a + 2084 0a45 01 .byte 0x1 + 2085 0a46 01 .byte 0x1 + 2086 0a47 0E .uleb128 0xe + 2087 0a48 3A020000 .4byte 0x23a + 2088 0a4c 00 .byte 0 + 2089 0a4d 00 .byte 0 + 2090 .section .debug_abbrev,"",%progbits + 2091 .Ldebug_abbrev0: + 2092 0000 01 .uleb128 0x1 + 2093 0001 11 .uleb128 0x11 + 2094 0002 01 .byte 0x1 + 2095 0003 25 .uleb128 0x25 + 2096 0004 0E .uleb128 0xe + 2097 0005 13 .uleb128 0x13 + 2098 0006 0B .uleb128 0xb + 2099 0007 03 .uleb128 0x3 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 38 + + + 2100 0008 0E .uleb128 0xe + 2101 0009 1B .uleb128 0x1b + 2102 000a 0E .uleb128 0xe + 2103 000b 55 .uleb128 0x55 + 2104 000c 06 .uleb128 0x6 + 2105 000d 11 .uleb128 0x11 + 2106 000e 01 .uleb128 0x1 + 2107 000f 52 .uleb128 0x52 + 2108 0010 01 .uleb128 0x1 + 2109 0011 10 .uleb128 0x10 + 2110 0012 06 .uleb128 0x6 + 2111 0013 00 .byte 0 + 2112 0014 00 .byte 0 + 2113 0015 02 .uleb128 0x2 + 2114 0016 24 .uleb128 0x24 + 2115 0017 00 .byte 0 + 2116 0018 0B .uleb128 0xb + 2117 0019 0B .uleb128 0xb + 2118 001a 3E .uleb128 0x3e + 2119 001b 0B .uleb128 0xb + 2120 001c 03 .uleb128 0x3 + 2121 001d 08 .uleb128 0x8 + 2122 001e 00 .byte 0 + 2123 001f 00 .byte 0 + 2124 0020 03 .uleb128 0x3 + 2125 0021 16 .uleb128 0x16 + 2126 0022 00 .byte 0 + 2127 0023 03 .uleb128 0x3 + 2128 0024 0E .uleb128 0xe + 2129 0025 3A .uleb128 0x3a + 2130 0026 0B .uleb128 0xb + 2131 0027 3B .uleb128 0x3b + 2132 0028 0B .uleb128 0xb + 2133 0029 49 .uleb128 0x49 + 2134 002a 13 .uleb128 0x13 + 2135 002b 00 .byte 0 + 2136 002c 00 .byte 0 + 2137 002d 04 .uleb128 0x4 + 2138 002e 24 .uleb128 0x24 + 2139 002f 00 .byte 0 + 2140 0030 0B .uleb128 0xb + 2141 0031 0B .uleb128 0xb + 2142 0032 3E .uleb128 0x3e + 2143 0033 0B .uleb128 0xb + 2144 0034 03 .uleb128 0x3 + 2145 0035 0E .uleb128 0xe + 2146 0036 00 .byte 0 + 2147 0037 00 .byte 0 + 2148 0038 05 .uleb128 0x5 + 2149 0039 13 .uleb128 0x13 + 2150 003a 01 .byte 0x1 + 2151 003b 03 .uleb128 0x3 + 2152 003c 0E .uleb128 0xe + 2153 003d 0B .uleb128 0xb + 2154 003e 0B .uleb128 0xb + 2155 003f 3A .uleb128 0x3a + 2156 0040 0B .uleb128 0xb + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 39 + + + 2157 0041 3B .uleb128 0x3b + 2158 0042 0B .uleb128 0xb + 2159 0043 01 .uleb128 0x1 + 2160 0044 13 .uleb128 0x13 + 2161 0045 00 .byte 0 + 2162 0046 00 .byte 0 + 2163 0047 06 .uleb128 0x6 + 2164 0048 0D .uleb128 0xd + 2165 0049 00 .byte 0 + 2166 004a 03 .uleb128 0x3 + 2167 004b 0E .uleb128 0xe + 2168 004c 3A .uleb128 0x3a + 2169 004d 0B .uleb128 0xb + 2170 004e 3B .uleb128 0x3b + 2171 004f 0B .uleb128 0xb + 2172 0050 49 .uleb128 0x49 + 2173 0051 13 .uleb128 0x13 + 2174 0052 38 .uleb128 0x38 + 2175 0053 0A .uleb128 0xa + 2176 0054 00 .byte 0 + 2177 0055 00 .byte 0 + 2178 0056 07 .uleb128 0x7 + 2179 0057 0D .uleb128 0xd + 2180 0058 00 .byte 0 + 2181 0059 03 .uleb128 0x3 + 2182 005a 08 .uleb128 0x8 + 2183 005b 3A .uleb128 0x3a + 2184 005c 0B .uleb128 0xb + 2185 005d 3B .uleb128 0x3b + 2186 005e 0B .uleb128 0xb + 2187 005f 49 .uleb128 0x49 + 2188 0060 13 .uleb128 0x13 + 2189 0061 38 .uleb128 0x38 + 2190 0062 0A .uleb128 0xa + 2191 0063 00 .byte 0 + 2192 0064 00 .byte 0 + 2193 0065 08 .uleb128 0x8 + 2194 0066 13 .uleb128 0x13 + 2195 0067 01 .byte 0x1 + 2196 0068 0B .uleb128 0xb + 2197 0069 0B .uleb128 0xb + 2198 006a 3A .uleb128 0x3a + 2199 006b 0B .uleb128 0xb + 2200 006c 3B .uleb128 0x3b + 2201 006d 0B .uleb128 0xb + 2202 006e 01 .uleb128 0x1 + 2203 006f 13 .uleb128 0x13 + 2204 0070 00 .byte 0 + 2205 0071 00 .byte 0 + 2206 0072 09 .uleb128 0x9 + 2207 0073 0F .uleb128 0xf + 2208 0074 00 .byte 0 + 2209 0075 0B .uleb128 0xb + 2210 0076 0B .uleb128 0xb + 2211 0077 49 .uleb128 0x49 + 2212 0078 13 .uleb128 0x13 + 2213 0079 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 40 + + + 2214 007a 00 .byte 0 + 2215 007b 0A .uleb128 0xa + 2216 007c 0F .uleb128 0xf + 2217 007d 00 .byte 0 + 2218 007e 0B .uleb128 0xb + 2219 007f 0B .uleb128 0xb + 2220 0080 00 .byte 0 + 2221 0081 00 .byte 0 + 2222 0082 0B .uleb128 0xb + 2223 0083 0D .uleb128 0xd + 2224 0084 00 .byte 0 + 2225 0085 03 .uleb128 0x3 + 2226 0086 08 .uleb128 0x8 + 2227 0087 3A .uleb128 0x3a + 2228 0088 0B .uleb128 0xb + 2229 0089 3B .uleb128 0x3b + 2230 008a 05 .uleb128 0x5 + 2231 008b 49 .uleb128 0x49 + 2232 008c 13 .uleb128 0x13 + 2233 008d 38 .uleb128 0x38 + 2234 008e 0A .uleb128 0xa + 2235 008f 00 .byte 0 + 2236 0090 00 .byte 0 + 2237 0091 0C .uleb128 0xc + 2238 0092 13 .uleb128 0x13 + 2239 0093 01 .byte 0x1 + 2240 0094 03 .uleb128 0x3 + 2241 0095 0E .uleb128 0xe + 2242 0096 0B .uleb128 0xb + 2243 0097 0B .uleb128 0xb + 2244 0098 3A .uleb128 0x3a + 2245 0099 0B .uleb128 0xb + 2246 009a 3B .uleb128 0x3b + 2247 009b 05 .uleb128 0x5 + 2248 009c 01 .uleb128 0x1 + 2249 009d 13 .uleb128 0x13 + 2250 009e 00 .byte 0 + 2251 009f 00 .byte 0 + 2252 00a0 0D .uleb128 0xd + 2253 00a1 15 .uleb128 0x15 + 2254 00a2 01 .byte 0x1 + 2255 00a3 27 .uleb128 0x27 + 2256 00a4 0C .uleb128 0xc + 2257 00a5 01 .uleb128 0x1 + 2258 00a6 13 .uleb128 0x13 + 2259 00a7 00 .byte 0 + 2260 00a8 00 .byte 0 + 2261 00a9 0E .uleb128 0xe + 2262 00aa 05 .uleb128 0x5 + 2263 00ab 00 .byte 0 + 2264 00ac 49 .uleb128 0x49 + 2265 00ad 13 .uleb128 0x13 + 2266 00ae 00 .byte 0 + 2267 00af 00 .byte 0 + 2268 00b0 0F .uleb128 0xf + 2269 00b1 35 .uleb128 0x35 + 2270 00b2 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 41 + + + 2271 00b3 49 .uleb128 0x49 + 2272 00b4 13 .uleb128 0x13 + 2273 00b5 00 .byte 0 + 2274 00b6 00 .byte 0 + 2275 00b7 10 .uleb128 0x10 + 2276 00b8 17 .uleb128 0x17 + 2277 00b9 01 .byte 0x1 + 2278 00ba 0B .uleb128 0xb + 2279 00bb 0B .uleb128 0xb + 2280 00bc 3A .uleb128 0x3a + 2281 00bd 0B .uleb128 0xb + 2282 00be 3B .uleb128 0x3b + 2283 00bf 0B .uleb128 0xb + 2284 00c0 01 .uleb128 0x1 + 2285 00c1 13 .uleb128 0x13 + 2286 00c2 00 .byte 0 + 2287 00c3 00 .byte 0 + 2288 00c4 11 .uleb128 0x11 + 2289 00c5 0D .uleb128 0xd + 2290 00c6 00 .byte 0 + 2291 00c7 03 .uleb128 0x3 + 2292 00c8 0E .uleb128 0xe + 2293 00c9 3A .uleb128 0x3a + 2294 00ca 0B .uleb128 0xb + 2295 00cb 3B .uleb128 0x3b + 2296 00cc 0B .uleb128 0xb + 2297 00cd 49 .uleb128 0x49 + 2298 00ce 13 .uleb128 0x13 + 2299 00cf 00 .byte 0 + 2300 00d0 00 .byte 0 + 2301 00d1 12 .uleb128 0x12 + 2302 00d2 26 .uleb128 0x26 + 2303 00d3 00 .byte 0 + 2304 00d4 49 .uleb128 0x49 + 2305 00d5 13 .uleb128 0x13 + 2306 00d6 00 .byte 0 + 2307 00d7 00 .byte 0 + 2308 00d8 13 .uleb128 0x13 + 2309 00d9 15 .uleb128 0x15 + 2310 00da 01 .byte 0x1 + 2311 00db 27 .uleb128 0x27 + 2312 00dc 0C .uleb128 0xc + 2313 00dd 49 .uleb128 0x49 + 2314 00de 13 .uleb128 0x13 + 2315 00df 01 .uleb128 0x1 + 2316 00e0 13 .uleb128 0x13 + 2317 00e1 00 .byte 0 + 2318 00e2 00 .byte 0 + 2319 00e3 14 .uleb128 0x14 + 2320 00e4 2E .uleb128 0x2e + 2321 00e5 01 .byte 0x1 + 2322 00e6 3F .uleb128 0x3f + 2323 00e7 0C .uleb128 0xc + 2324 00e8 03 .uleb128 0x3 + 2325 00e9 0E .uleb128 0xe + 2326 00ea 3A .uleb128 0x3a + 2327 00eb 0B .uleb128 0xb + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 42 + + + 2328 00ec 3B .uleb128 0x3b + 2329 00ed 0B .uleb128 0xb + 2330 00ee 27 .uleb128 0x27 + 2331 00ef 0C .uleb128 0xc + 2332 00f0 49 .uleb128 0x49 + 2333 00f1 13 .uleb128 0x13 + 2334 00f2 20 .uleb128 0x20 + 2335 00f3 0B .uleb128 0xb + 2336 00f4 01 .uleb128 0x1 + 2337 00f5 13 .uleb128 0x13 + 2338 00f6 00 .byte 0 + 2339 00f7 00 .byte 0 + 2340 00f8 15 .uleb128 0x15 + 2341 00f9 05 .uleb128 0x5 + 2342 00fa 00 .byte 0 + 2343 00fb 03 .uleb128 0x3 + 2344 00fc 08 .uleb128 0x8 + 2345 00fd 3A .uleb128 0x3a + 2346 00fe 0B .uleb128 0xb + 2347 00ff 3B .uleb128 0x3b + 2348 0100 0B .uleb128 0xb + 2349 0101 49 .uleb128 0x49 + 2350 0102 13 .uleb128 0x13 + 2351 0103 00 .byte 0 + 2352 0104 00 .byte 0 + 2353 0105 16 .uleb128 0x16 + 2354 0106 05 .uleb128 0x5 + 2355 0107 00 .byte 0 + 2356 0108 03 .uleb128 0x3 + 2357 0109 0E .uleb128 0xe + 2358 010a 3A .uleb128 0x3a + 2359 010b 0B .uleb128 0xb + 2360 010c 3B .uleb128 0x3b + 2361 010d 0B .uleb128 0xb + 2362 010e 49 .uleb128 0x49 + 2363 010f 13 .uleb128 0x13 + 2364 0110 00 .byte 0 + 2365 0111 00 .byte 0 + 2366 0112 17 .uleb128 0x17 + 2367 0113 2E .uleb128 0x2e + 2368 0114 01 .byte 0x1 + 2369 0115 03 .uleb128 0x3 + 2370 0116 0E .uleb128 0xe + 2371 0117 3A .uleb128 0x3a + 2372 0118 0B .uleb128 0xb + 2373 0119 3B .uleb128 0x3b + 2374 011a 0B .uleb128 0xb + 2375 011b 27 .uleb128 0x27 + 2376 011c 0C .uleb128 0xc + 2377 011d 49 .uleb128 0x49 + 2378 011e 13 .uleb128 0x13 + 2379 011f 20 .uleb128 0x20 + 2380 0120 0B .uleb128 0xb + 2381 0121 01 .uleb128 0x1 + 2382 0122 13 .uleb128 0x13 + 2383 0123 00 .byte 0 + 2384 0124 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 43 + + + 2385 0125 18 .uleb128 0x18 + 2386 0126 34 .uleb128 0x34 + 2387 0127 00 .byte 0 + 2388 0128 03 .uleb128 0x3 + 2389 0129 08 .uleb128 0x8 + 2390 012a 3A .uleb128 0x3a + 2391 012b 0B .uleb128 0xb + 2392 012c 3B .uleb128 0x3b + 2393 012d 0B .uleb128 0xb + 2394 012e 49 .uleb128 0x49 + 2395 012f 13 .uleb128 0x13 + 2396 0130 00 .byte 0 + 2397 0131 00 .byte 0 + 2398 0132 19 .uleb128 0x19 + 2399 0133 2E .uleb128 0x2e + 2400 0134 01 .byte 0x1 + 2401 0135 03 .uleb128 0x3 + 2402 0136 0E .uleb128 0xe + 2403 0137 3A .uleb128 0x3a + 2404 0138 0B .uleb128 0xb + 2405 0139 3B .uleb128 0x3b + 2406 013a 0B .uleb128 0xb + 2407 013b 27 .uleb128 0x27 + 2408 013c 0C .uleb128 0xc + 2409 013d 20 .uleb128 0x20 + 2410 013e 0B .uleb128 0xb + 2411 013f 01 .uleb128 0x1 + 2412 0140 13 .uleb128 0x13 + 2413 0141 00 .byte 0 + 2414 0142 00 .byte 0 + 2415 0143 1A .uleb128 0x1a + 2416 0144 2E .uleb128 0x2e + 2417 0145 01 .byte 0x1 + 2418 0146 31 .uleb128 0x31 + 2419 0147 13 .uleb128 0x13 + 2420 0148 11 .uleb128 0x11 + 2421 0149 01 .uleb128 0x1 + 2422 014a 12 .uleb128 0x12 + 2423 014b 01 .uleb128 0x1 + 2424 014c 40 .uleb128 0x40 + 2425 014d 06 .uleb128 0x6 + 2426 014e 9742 .uleb128 0x2117 + 2427 0150 0C .uleb128 0xc + 2428 0151 01 .uleb128 0x1 + 2429 0152 13 .uleb128 0x13 + 2430 0153 00 .byte 0 + 2431 0154 00 .byte 0 + 2432 0155 1B .uleb128 0x1b + 2433 0156 05 .uleb128 0x5 + 2434 0157 00 .byte 0 + 2435 0158 31 .uleb128 0x31 + 2436 0159 13 .uleb128 0x13 + 2437 015a 02 .uleb128 0x2 + 2438 015b 0A .uleb128 0xa + 2439 015c 00 .byte 0 + 2440 015d 00 .byte 0 + 2441 015e 1C .uleb128 0x1c + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 44 + + + 2442 015f 05 .uleb128 0x5 + 2443 0160 00 .byte 0 + 2444 0161 31 .uleb128 0x31 + 2445 0162 13 .uleb128 0x13 + 2446 0163 02 .uleb128 0x2 + 2447 0164 06 .uleb128 0x6 + 2448 0165 00 .byte 0 + 2449 0166 00 .byte 0 + 2450 0167 1D .uleb128 0x1d + 2451 0168 2E .uleb128 0x2e + 2452 0169 01 .byte 0x1 + 2453 016a 3F .uleb128 0x3f + 2454 016b 0C .uleb128 0xc + 2455 016c 03 .uleb128 0x3 + 2456 016d 0E .uleb128 0xe + 2457 016e 3A .uleb128 0x3a + 2458 016f 0B .uleb128 0xb + 2459 0170 3B .uleb128 0x3b + 2460 0171 0B .uleb128 0xb + 2461 0172 27 .uleb128 0x27 + 2462 0173 0C .uleb128 0xc + 2463 0174 49 .uleb128 0x49 + 2464 0175 13 .uleb128 0x13 + 2465 0176 11 .uleb128 0x11 + 2466 0177 01 .uleb128 0x1 + 2467 0178 12 .uleb128 0x12 + 2468 0179 01 .uleb128 0x1 + 2469 017a 40 .uleb128 0x40 + 2470 017b 06 .uleb128 0x6 + 2471 017c 9742 .uleb128 0x2117 + 2472 017e 0C .uleb128 0xc + 2473 017f 01 .uleb128 0x1 + 2474 0180 13 .uleb128 0x13 + 2475 0181 00 .byte 0 + 2476 0182 00 .byte 0 + 2477 0183 1E .uleb128 0x1e + 2478 0184 05 .uleb128 0x5 + 2479 0185 00 .byte 0 + 2480 0186 03 .uleb128 0x3 + 2481 0187 08 .uleb128 0x8 + 2482 0188 3A .uleb128 0x3a + 2483 0189 0B .uleb128 0xb + 2484 018a 3B .uleb128 0x3b + 2485 018b 0B .uleb128 0xb + 2486 018c 49 .uleb128 0x49 + 2487 018d 13 .uleb128 0x13 + 2488 018e 02 .uleb128 0x2 + 2489 018f 0A .uleb128 0xa + 2490 0190 00 .byte 0 + 2491 0191 00 .byte 0 + 2492 0192 1F .uleb128 0x1f + 2493 0193 05 .uleb128 0x5 + 2494 0194 00 .byte 0 + 2495 0195 03 .uleb128 0x3 + 2496 0196 0E .uleb128 0xe + 2497 0197 3A .uleb128 0x3a + 2498 0198 0B .uleb128 0xb + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 45 + + + 2499 0199 3B .uleb128 0x3b + 2500 019a 0B .uleb128 0xb + 2501 019b 49 .uleb128 0x49 + 2502 019c 13 .uleb128 0x13 + 2503 019d 02 .uleb128 0x2 + 2504 019e 06 .uleb128 0x6 + 2505 019f 00 .byte 0 + 2506 01a0 00 .byte 0 + 2507 01a1 20 .uleb128 0x20 + 2508 01a2 05 .uleb128 0x5 + 2509 01a3 00 .byte 0 + 2510 01a4 03 .uleb128 0x3 + 2511 01a5 08 .uleb128 0x8 + 2512 01a6 3A .uleb128 0x3a + 2513 01a7 0B .uleb128 0xb + 2514 01a8 3B .uleb128 0x3b + 2515 01a9 0B .uleb128 0xb + 2516 01aa 49 .uleb128 0x49 + 2517 01ab 13 .uleb128 0x13 + 2518 01ac 02 .uleb128 0x2 + 2519 01ad 06 .uleb128 0x6 + 2520 01ae 00 .byte 0 + 2521 01af 00 .byte 0 + 2522 01b0 21 .uleb128 0x21 + 2523 01b1 34 .uleb128 0x34 + 2524 01b2 00 .byte 0 + 2525 01b3 03 .uleb128 0x3 + 2526 01b4 08 .uleb128 0x8 + 2527 01b5 3A .uleb128 0x3a + 2528 01b6 0B .uleb128 0xb + 2529 01b7 3B .uleb128 0x3b + 2530 01b8 0B .uleb128 0xb + 2531 01b9 49 .uleb128 0x49 + 2532 01ba 13 .uleb128 0x13 + 2533 01bb 02 .uleb128 0x2 + 2534 01bc 0A .uleb128 0xa + 2535 01bd 00 .byte 0 + 2536 01be 00 .byte 0 + 2537 01bf 22 .uleb128 0x22 + 2538 01c0 1D .uleb128 0x1d + 2539 01c1 01 .byte 0x1 + 2540 01c2 31 .uleb128 0x31 + 2541 01c3 13 .uleb128 0x13 + 2542 01c4 52 .uleb128 0x52 + 2543 01c5 01 .uleb128 0x1 + 2544 01c6 55 .uleb128 0x55 + 2545 01c7 06 .uleb128 0x6 + 2546 01c8 58 .uleb128 0x58 + 2547 01c9 0B .uleb128 0xb + 2548 01ca 59 .uleb128 0x59 + 2549 01cb 0B .uleb128 0xb + 2550 01cc 00 .byte 0 + 2551 01cd 00 .byte 0 + 2552 01ce 23 .uleb128 0x23 + 2553 01cf 34 .uleb128 0x34 + 2554 01d0 00 .byte 0 + 2555 01d1 03 .uleb128 0x3 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 46 + + + 2556 01d2 08 .uleb128 0x8 + 2557 01d3 3A .uleb128 0x3a + 2558 01d4 0B .uleb128 0xb + 2559 01d5 3B .uleb128 0x3b + 2560 01d6 0B .uleb128 0xb + 2561 01d7 49 .uleb128 0x49 + 2562 01d8 13 .uleb128 0x13 + 2563 01d9 02 .uleb128 0x2 + 2564 01da 06 .uleb128 0x6 + 2565 01db 00 .byte 0 + 2566 01dc 00 .byte 0 + 2567 01dd 24 .uleb128 0x24 + 2568 01de 898201 .uleb128 0x4109 + 2569 01e1 01 .byte 0x1 + 2570 01e2 11 .uleb128 0x11 + 2571 01e3 01 .uleb128 0x1 + 2572 01e4 31 .uleb128 0x31 + 2573 01e5 13 .uleb128 0x13 + 2574 01e6 01 .uleb128 0x1 + 2575 01e7 13 .uleb128 0x13 + 2576 01e8 00 .byte 0 + 2577 01e9 00 .byte 0 + 2578 01ea 25 .uleb128 0x25 + 2579 01eb 8A8201 .uleb128 0x410a + 2580 01ee 00 .byte 0 + 2581 01ef 02 .uleb128 0x2 + 2582 01f0 0A .uleb128 0xa + 2583 01f1 9142 .uleb128 0x2111 + 2584 01f3 0A .uleb128 0xa + 2585 01f4 00 .byte 0 + 2586 01f5 00 .byte 0 + 2587 01f6 26 .uleb128 0x26 + 2588 01f7 898201 .uleb128 0x4109 + 2589 01fa 01 .byte 0x1 + 2590 01fb 11 .uleb128 0x11 + 2591 01fc 01 .uleb128 0x1 + 2592 01fd 31 .uleb128 0x31 + 2593 01fe 13 .uleb128 0x13 + 2594 01ff 00 .byte 0 + 2595 0200 00 .byte 0 + 2596 0201 27 .uleb128 0x27 + 2597 0202 34 .uleb128 0x34 + 2598 0203 00 .byte 0 + 2599 0204 03 .uleb128 0x3 + 2600 0205 0E .uleb128 0xe + 2601 0206 3A .uleb128 0x3a + 2602 0207 0B .uleb128 0xb + 2603 0208 3B .uleb128 0x3b + 2604 0209 0B .uleb128 0xb + 2605 020a 49 .uleb128 0x49 + 2606 020b 13 .uleb128 0x13 + 2607 020c 02 .uleb128 0x2 + 2608 020d 0A .uleb128 0xa + 2609 020e 00 .byte 0 + 2610 020f 00 .byte 0 + 2611 0210 28 .uleb128 0x28 + 2612 0211 898201 .uleb128 0x4109 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 47 + + + 2613 0214 00 .byte 0 + 2614 0215 11 .uleb128 0x11 + 2615 0216 01 .uleb128 0x1 + 2616 0217 31 .uleb128 0x31 + 2617 0218 13 .uleb128 0x13 + 2618 0219 00 .byte 0 + 2619 021a 00 .byte 0 + 2620 021b 29 .uleb128 0x29 + 2621 021c 2E .uleb128 0x2e + 2622 021d 01 .byte 0x1 + 2623 021e 3F .uleb128 0x3f + 2624 021f 0C .uleb128 0xc + 2625 0220 03 .uleb128 0x3 + 2626 0221 0E .uleb128 0xe + 2627 0222 3A .uleb128 0x3a + 2628 0223 0B .uleb128 0xb + 2629 0224 3B .uleb128 0x3b + 2630 0225 05 .uleb128 0x5 + 2631 0226 27 .uleb128 0x27 + 2632 0227 0C .uleb128 0xc + 2633 0228 11 .uleb128 0x11 + 2634 0229 01 .uleb128 0x1 + 2635 022a 12 .uleb128 0x12 + 2636 022b 01 .uleb128 0x1 + 2637 022c 40 .uleb128 0x40 + 2638 022d 0A .uleb128 0xa + 2639 022e 9742 .uleb128 0x2117 + 2640 0230 0C .uleb128 0xc + 2641 0231 01 .uleb128 0x1 + 2642 0232 13 .uleb128 0x13 + 2643 0233 00 .byte 0 + 2644 0234 00 .byte 0 + 2645 0235 2A .uleb128 0x2a + 2646 0236 05 .uleb128 0x5 + 2647 0237 00 .byte 0 + 2648 0238 03 .uleb128 0x3 + 2649 0239 08 .uleb128 0x8 + 2650 023a 3A .uleb128 0x3a + 2651 023b 0B .uleb128 0xb + 2652 023c 3B .uleb128 0x3b + 2653 023d 05 .uleb128 0x5 + 2654 023e 49 .uleb128 0x49 + 2655 023f 13 .uleb128 0x13 + 2656 0240 02 .uleb128 0x2 + 2657 0241 0A .uleb128 0xa + 2658 0242 00 .byte 0 + 2659 0243 00 .byte 0 + 2660 0244 2B .uleb128 0x2b + 2661 0245 2E .uleb128 0x2e + 2662 0246 01 .byte 0x1 + 2663 0247 3F .uleb128 0x3f + 2664 0248 0C .uleb128 0xc + 2665 0249 03 .uleb128 0x3 + 2666 024a 0E .uleb128 0xe + 2667 024b 3A .uleb128 0x3a + 2668 024c 0B .uleb128 0xb + 2669 024d 3B .uleb128 0x3b + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 48 + + + 2670 024e 05 .uleb128 0x5 + 2671 024f 27 .uleb128 0x27 + 2672 0250 0C .uleb128 0xc + 2673 0251 11 .uleb128 0x11 + 2674 0252 01 .uleb128 0x1 + 2675 0253 12 .uleb128 0x12 + 2676 0254 01 .uleb128 0x1 + 2677 0255 40 .uleb128 0x40 + 2678 0256 06 .uleb128 0x6 + 2679 0257 9742 .uleb128 0x2117 + 2680 0259 0C .uleb128 0xc + 2681 025a 01 .uleb128 0x1 + 2682 025b 13 .uleb128 0x13 + 2683 025c 00 .byte 0 + 2684 025d 00 .byte 0 + 2685 025e 2C .uleb128 0x2c + 2686 025f 05 .uleb128 0x5 + 2687 0260 00 .byte 0 + 2688 0261 03 .uleb128 0x3 + 2689 0262 0E .uleb128 0xe + 2690 0263 3A .uleb128 0x3a + 2691 0264 0B .uleb128 0xb + 2692 0265 3B .uleb128 0x3b + 2693 0266 05 .uleb128 0x5 + 2694 0267 49 .uleb128 0x49 + 2695 0268 13 .uleb128 0x13 + 2696 0269 02 .uleb128 0x2 + 2697 026a 06 .uleb128 0x6 + 2698 026b 00 .byte 0 + 2699 026c 00 .byte 0 + 2700 026d 2D .uleb128 0x2d + 2701 026e 05 .uleb128 0x5 + 2702 026f 00 .byte 0 + 2703 0270 03 .uleb128 0x3 + 2704 0271 08 .uleb128 0x8 + 2705 0272 3A .uleb128 0x3a + 2706 0273 0B .uleb128 0xb + 2707 0274 3B .uleb128 0x3b + 2708 0275 05 .uleb128 0x5 + 2709 0276 49 .uleb128 0x49 + 2710 0277 13 .uleb128 0x13 + 2711 0278 02 .uleb128 0x2 + 2712 0279 06 .uleb128 0x6 + 2713 027a 00 .byte 0 + 2714 027b 00 .byte 0 + 2715 027c 2E .uleb128 0x2e + 2716 027d 34 .uleb128 0x34 + 2717 027e 00 .byte 0 + 2718 027f 03 .uleb128 0x3 + 2719 0280 08 .uleb128 0x8 + 2720 0281 3A .uleb128 0x3a + 2721 0282 0B .uleb128 0xb + 2722 0283 3B .uleb128 0x3b + 2723 0284 05 .uleb128 0x5 + 2724 0285 49 .uleb128 0x49 + 2725 0286 13 .uleb128 0x13 + 2726 0287 02 .uleb128 0x2 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 49 + + + 2727 0288 0A .uleb128 0xa + 2728 0289 00 .byte 0 + 2729 028a 00 .byte 0 + 2730 028b 2F .uleb128 0x2f + 2731 028c 1D .uleb128 0x1d + 2732 028d 01 .byte 0x1 + 2733 028e 31 .uleb128 0x31 + 2734 028f 13 .uleb128 0x13 + 2735 0290 52 .uleb128 0x52 + 2736 0291 01 .uleb128 0x1 + 2737 0292 55 .uleb128 0x55 + 2738 0293 06 .uleb128 0x6 + 2739 0294 58 .uleb128 0x58 + 2740 0295 0B .uleb128 0xb + 2741 0296 59 .uleb128 0x59 + 2742 0297 05 .uleb128 0x5 + 2743 0298 01 .uleb128 0x1 + 2744 0299 13 .uleb128 0x13 + 2745 029a 00 .byte 0 + 2746 029b 00 .byte 0 + 2747 029c 30 .uleb128 0x30 + 2748 029d 0B .uleb128 0xb + 2749 029e 01 .byte 0x1 + 2750 029f 55 .uleb128 0x55 + 2751 02a0 06 .uleb128 0x6 + 2752 02a1 00 .byte 0 + 2753 02a2 00 .byte 0 + 2754 02a3 31 .uleb128 0x31 + 2755 02a4 34 .uleb128 0x34 + 2756 02a5 00 .byte 0 + 2757 02a6 31 .uleb128 0x31 + 2758 02a7 13 .uleb128 0x13 + 2759 02a8 02 .uleb128 0x2 + 2760 02a9 06 .uleb128 0x6 + 2761 02aa 00 .byte 0 + 2762 02ab 00 .byte 0 + 2763 02ac 32 .uleb128 0x32 + 2764 02ad 898201 .uleb128 0x4109 + 2765 02b0 01 .byte 0x1 + 2766 02b1 11 .uleb128 0x11 + 2767 02b2 01 .uleb128 0x1 + 2768 02b3 9542 .uleb128 0x2115 + 2769 02b5 0C .uleb128 0xc + 2770 02b6 31 .uleb128 0x31 + 2771 02b7 13 .uleb128 0x13 + 2772 02b8 00 .byte 0 + 2773 02b9 00 .byte 0 + 2774 02ba 33 .uleb128 0x33 + 2775 02bb 2E .uleb128 0x2e + 2776 02bc 01 .byte 0x1 + 2777 02bd 3F .uleb128 0x3f + 2778 02be 0C .uleb128 0xc + 2779 02bf 03 .uleb128 0x3 + 2780 02c0 0E .uleb128 0xe + 2781 02c1 3A .uleb128 0x3a + 2782 02c2 0B .uleb128 0xb + 2783 02c3 3B .uleb128 0x3b + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 50 + + + 2784 02c4 05 .uleb128 0x5 + 2785 02c5 27 .uleb128 0x27 + 2786 02c6 0C .uleb128 0xc + 2787 02c7 49 .uleb128 0x49 + 2788 02c8 13 .uleb128 0x13 + 2789 02c9 11 .uleb128 0x11 + 2790 02ca 01 .uleb128 0x1 + 2791 02cb 12 .uleb128 0x12 + 2792 02cc 01 .uleb128 0x1 + 2793 02cd 40 .uleb128 0x40 + 2794 02ce 06 .uleb128 0x6 + 2795 02cf 9742 .uleb128 0x2117 + 2796 02d1 0C .uleb128 0xc + 2797 02d2 01 .uleb128 0x1 + 2798 02d3 13 .uleb128 0x13 + 2799 02d4 00 .byte 0 + 2800 02d5 00 .byte 0 + 2801 02d6 34 .uleb128 0x34 + 2802 02d7 34 .uleb128 0x34 + 2803 02d8 00 .byte 0 + 2804 02d9 03 .uleb128 0x3 + 2805 02da 0E .uleb128 0xe + 2806 02db 3A .uleb128 0x3a + 2807 02dc 0B .uleb128 0xb + 2808 02dd 3B .uleb128 0x3b + 2809 02de 0B .uleb128 0xb + 2810 02df 49 .uleb128 0x49 + 2811 02e0 13 .uleb128 0x13 + 2812 02e1 3F .uleb128 0x3f + 2813 02e2 0C .uleb128 0xc + 2814 02e3 3C .uleb128 0x3c + 2815 02e4 0C .uleb128 0xc + 2816 02e5 00 .byte 0 + 2817 02e6 00 .byte 0 + 2818 02e7 35 .uleb128 0x35 + 2819 02e8 2E .uleb128 0x2e + 2820 02e9 01 .byte 0x1 + 2821 02ea 3F .uleb128 0x3f + 2822 02eb 0C .uleb128 0xc + 2823 02ec 03 .uleb128 0x3 + 2824 02ed 0E .uleb128 0xe + 2825 02ee 3A .uleb128 0x3a + 2826 02ef 0B .uleb128 0xb + 2827 02f0 3B .uleb128 0x3b + 2828 02f1 0B .uleb128 0xb + 2829 02f2 27 .uleb128 0x27 + 2830 02f3 0C .uleb128 0xc + 2831 02f4 3C .uleb128 0x3c + 2832 02f5 0C .uleb128 0xc + 2833 02f6 01 .uleb128 0x1 + 2834 02f7 13 .uleb128 0x13 + 2835 02f8 00 .byte 0 + 2836 02f9 00 .byte 0 + 2837 02fa 36 .uleb128 0x36 + 2838 02fb 2E .uleb128 0x2e + 2839 02fc 00 .byte 0 + 2840 02fd 3F .uleb128 0x3f + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 51 + + + 2841 02fe 0C .uleb128 0xc + 2842 02ff 03 .uleb128 0x3 + 2843 0300 0E .uleb128 0xe + 2844 0301 3A .uleb128 0x3a + 2845 0302 0B .uleb128 0xb + 2846 0303 3B .uleb128 0x3b + 2847 0304 0B .uleb128 0xb + 2848 0305 27 .uleb128 0x27 + 2849 0306 0C .uleb128 0xc + 2850 0307 3C .uleb128 0x3c + 2851 0308 0C .uleb128 0xc + 2852 0309 00 .byte 0 + 2853 030a 00 .byte 0 + 2854 030b 37 .uleb128 0x37 + 2855 030c 2E .uleb128 0x2e + 2856 030d 01 .byte 0x1 + 2857 030e 3F .uleb128 0x3f + 2858 030f 0C .uleb128 0xc + 2859 0310 03 .uleb128 0x3 + 2860 0311 0E .uleb128 0xe + 2861 0312 3A .uleb128 0x3a + 2862 0313 0B .uleb128 0xb + 2863 0314 3B .uleb128 0x3b + 2864 0315 0B .uleb128 0xb + 2865 0316 27 .uleb128 0x27 + 2866 0317 0C .uleb128 0xc + 2867 0318 49 .uleb128 0x49 + 2868 0319 13 .uleb128 0x13 + 2869 031a 3C .uleb128 0x3c + 2870 031b 0C .uleb128 0xc + 2871 031c 01 .uleb128 0x1 + 2872 031d 13 .uleb128 0x13 + 2873 031e 00 .byte 0 + 2874 031f 00 .byte 0 + 2875 0320 38 .uleb128 0x38 + 2876 0321 2E .uleb128 0x2e + 2877 0322 01 .byte 0x1 + 2878 0323 3F .uleb128 0x3f + 2879 0324 0C .uleb128 0xc + 2880 0325 03 .uleb128 0x3 + 2881 0326 0E .uleb128 0xe + 2882 0327 3A .uleb128 0x3a + 2883 0328 0B .uleb128 0xb + 2884 0329 3B .uleb128 0x3b + 2885 032a 0B .uleb128 0xb + 2886 032b 27 .uleb128 0x27 + 2887 032c 0C .uleb128 0xc + 2888 032d 3C .uleb128 0x3c + 2889 032e 0C .uleb128 0xc + 2890 032f 00 .byte 0 + 2891 0330 00 .byte 0 + 2892 0331 00 .byte 0 + 2893 .section .debug_loc,"",%progbits + 2894 .Ldebug_loc0: + 2895 .LLST0: + 2896 0000 00000000 .4byte .LFB7 + 2897 0004 02000000 .4byte .LCFI0 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 52 + + + 2898 0008 0200 .2byte 0x2 + 2899 000a 7D .byte 0x7d + 2900 000b 00 .sleb128 0 + 2901 000c 02000000 .4byte .LCFI0 + 2902 0010 42000000 .4byte .LFE7 + 2903 0014 0200 .2byte 0x2 + 2904 0016 7D .byte 0x7d + 2905 0017 10 .sleb128 16 + 2906 0018 00000000 .4byte 0 + 2907 001c 00000000 .4byte 0 + 2908 .LLST1: + 2909 0020 00000000 .4byte .LVL0 + 2910 0024 20000000 .4byte .LVL1 + 2911 0028 0100 .2byte 0x1 + 2912 002a 51 .byte 0x51 + 2913 002b 20000000 .4byte .LVL1 + 2914 002f 42000000 .4byte .LFE7 + 2915 0033 0200 .2byte 0x2 + 2916 0035 70 .byte 0x70 + 2917 0036 08 .sleb128 8 + 2918 0037 00000000 .4byte 0 + 2919 003b 00000000 .4byte 0 + 2920 .LLST2: + 2921 003f 00000000 .4byte .LFB8 + 2922 0043 04000000 .4byte .LCFI1 + 2923 0047 0200 .2byte 0x2 + 2924 0049 7D .byte 0x7d + 2925 004a 00 .sleb128 0 + 2926 004b 04000000 .4byte .LCFI1 + 2927 004f 68000000 .4byte .LFE8 + 2928 0053 0200 .2byte 0x2 + 2929 0055 7D .byte 0x7d + 2930 0056 18 .sleb128 24 + 2931 0057 00000000 .4byte 0 + 2932 005b 00000000 .4byte 0 + 2933 .LLST3: + 2934 005f 00000000 .4byte .LVL2 + 2935 0063 06000000 .4byte .LVL3 + 2936 0067 0100 .2byte 0x1 + 2937 0069 51 .byte 0x51 + 2938 006a 06000000 .4byte .LVL3 + 2939 006e 68000000 .4byte .LFE8 + 2940 0072 0300 .2byte 0x3 + 2941 0074 71 .byte 0x71 + 2942 0075 24 .sleb128 36 + 2943 0076 9F .byte 0x9f + 2944 0077 00000000 .4byte 0 + 2945 007b 00000000 .4byte 0 + 2946 .LLST4: + 2947 007f 00000000 .4byte .LVL2 + 2948 0083 34000000 .4byte .LVL5 + 2949 0087 0100 .2byte 0x1 + 2950 0089 52 .byte 0x52 + 2951 008a 34000000 .4byte .LVL5 + 2952 008e 68000000 .4byte .LFE8 + 2953 0092 0100 .2byte 0x1 + 2954 0094 58 .byte 0x58 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 53 + + + 2955 0095 00000000 .4byte 0 + 2956 0099 00000000 .4byte 0 + 2957 .LLST5: + 2958 009d 00000000 .4byte .LVL2 + 2959 00a1 1A000000 .4byte .LVL4 + 2960 00a5 0100 .2byte 0x1 + 2961 00a7 53 .byte 0x53 + 2962 00a8 1A000000 .4byte .LVL4 + 2963 00ac 68000000 .4byte .LFE8 + 2964 00b0 0200 .2byte 0x2 + 2965 00b2 77 .byte 0x77 + 2966 00b3 00 .sleb128 0 + 2967 00b4 00000000 .4byte 0 + 2968 00b8 00000000 .4byte 0 + 2969 .LLST6: + 2970 00bc 00000000 .4byte .LFB9 + 2971 00c0 02000000 .4byte .LCFI2 + 2972 00c4 0200 .2byte 0x2 + 2973 00c6 7D .byte 0x7d + 2974 00c7 00 .sleb128 0 + 2975 00c8 02000000 .4byte .LCFI2 + 2976 00cc 04000000 .4byte .LCFI3 + 2977 00d0 0200 .2byte 0x2 + 2978 00d2 7D .byte 0x7d + 2979 00d3 08 .sleb128 8 + 2980 00d4 04000000 .4byte .LCFI3 + 2981 00d8 1E000000 .4byte .LFE9 + 2982 00dc 0200 .2byte 0x2 + 2983 00de 7D .byte 0x7d + 2984 00df 10 .sleb128 16 + 2985 00e0 00000000 .4byte 0 + 2986 00e4 00000000 .4byte 0 + 2987 .LLST7: + 2988 00e8 00000000 .4byte .LVL7 + 2989 00ec 0D000000 .4byte .LVL8-1 + 2990 00f0 0100 .2byte 0x1 + 2991 00f2 50 .byte 0x50 + 2992 00f3 0D000000 .4byte .LVL8-1 + 2993 00f7 1E000000 .4byte .LFE9 + 2994 00fb 0400 .2byte 0x4 + 2995 00fd F3 .byte 0xf3 + 2996 00fe 01 .uleb128 0x1 + 2997 00ff 50 .byte 0x50 + 2998 0100 9F .byte 0x9f + 2999 0101 00000000 .4byte 0 + 3000 0105 00000000 .4byte 0 + 3001 .LLST8: + 3002 0109 00000000 .4byte .LVL7 + 3003 010d 0D000000 .4byte .LVL8-1 + 3004 0111 0100 .2byte 0x1 + 3005 0113 51 .byte 0x51 + 3006 0114 0D000000 .4byte .LVL8-1 + 3007 0118 1E000000 .4byte .LFE9 + 3008 011c 0400 .2byte 0x4 + 3009 011e F3 .byte 0xf3 + 3010 011f 01 .uleb128 0x1 + 3011 0120 51 .byte 0x51 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 54 + + + 3012 0121 9F .byte 0x9f + 3013 0122 00000000 .4byte 0 + 3014 0126 00000000 .4byte 0 + 3015 .LLST9: + 3016 012a 00000000 .4byte .LVL7 + 3017 012e 0D000000 .4byte .LVL8-1 + 3018 0132 0100 .2byte 0x1 + 3019 0134 52 .byte 0x52 + 3020 0135 0D000000 .4byte .LVL8-1 + 3021 0139 1E000000 .4byte .LFE9 + 3022 013d 0400 .2byte 0x4 + 3023 013f F3 .byte 0xf3 + 3024 0140 01 .uleb128 0x1 + 3025 0141 52 .byte 0x52 + 3026 0142 9F .byte 0x9f + 3027 0143 00000000 .4byte 0 + 3028 0147 00000000 .4byte 0 + 3029 .LLST10: + 3030 014b 00000000 .4byte .LVL7 + 3031 014f 0D000000 .4byte .LVL8-1 + 3032 0153 0100 .2byte 0x1 + 3033 0155 53 .byte 0x53 + 3034 0156 0D000000 .4byte .LVL8-1 + 3035 015a 1E000000 .4byte .LFE9 + 3036 015e 0400 .2byte 0x4 + 3037 0160 F3 .byte 0xf3 + 3038 0161 01 .uleb128 0x1 + 3039 0162 53 .byte 0x53 + 3040 0163 9F .byte 0x9f + 3041 0164 00000000 .4byte 0 + 3042 0168 00000000 .4byte 0 + 3043 .LLST11: + 3044 016c 12000000 .4byte .LVL9 + 3045 0170 15000000 .4byte .LVL10-1 + 3046 0174 0100 .2byte 0x1 + 3047 0176 50 .byte 0x50 + 3048 0177 15000000 .4byte .LVL10-1 + 3049 017b 1E000000 .4byte .LFE9 + 3050 017f 0100 .2byte 0x1 + 3051 0181 54 .byte 0x54 + 3052 0182 00000000 .4byte 0 + 3053 0186 00000000 .4byte 0 + 3054 .LLST12: + 3055 018a 00000000 .4byte .LFB10 + 3056 018e 02000000 .4byte .LCFI4 + 3057 0192 0200 .2byte 0x2 + 3058 0194 7D .byte 0x7d + 3059 0195 00 .sleb128 0 + 3060 0196 02000000 .4byte .LCFI4 + 3061 019a 28000000 .4byte .LFE10 + 3062 019e 0200 .2byte 0x2 + 3063 01a0 7D .byte 0x7d + 3064 01a1 08 .sleb128 8 + 3065 01a2 00000000 .4byte 0 + 3066 01a6 00000000 .4byte 0 + 3067 .LLST13: + 3068 01aa 00000000 .4byte .LVL11 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 55 + + + 3069 01ae 1B000000 .4byte .LVL13-1 + 3070 01b2 0100 .2byte 0x1 + 3071 01b4 50 .byte 0x50 + 3072 01b5 1B000000 .4byte .LVL13-1 + 3073 01b9 28000000 .4byte .LFE10 + 3074 01bd 0400 .2byte 0x4 + 3075 01bf F3 .byte 0xf3 + 3076 01c0 01 .uleb128 0x1 + 3077 01c1 50 .byte 0x50 + 3078 01c2 9F .byte 0x9f + 3079 01c3 00000000 .4byte 0 + 3080 01c7 00000000 .4byte 0 + 3081 .LLST14: + 3082 01cb 00000000 .4byte .LFB11 + 3083 01cf 02000000 .4byte .LCFI5 + 3084 01d3 0200 .2byte 0x2 + 3085 01d5 7D .byte 0x7d + 3086 01d6 00 .sleb128 0 + 3087 01d7 02000000 .4byte .LCFI5 + 3088 01db 12000000 .4byte .LFE11 + 3089 01df 0200 .2byte 0x2 + 3090 01e1 7D .byte 0x7d + 3091 01e2 08 .sleb128 8 + 3092 01e3 00000000 .4byte 0 + 3093 01e7 00000000 .4byte 0 + 3094 .LLST15: + 3095 01eb 00000000 .4byte .LVL14 + 3096 01ef 0B000000 .4byte .LVL15-1 + 3097 01f3 0100 .2byte 0x1 + 3098 01f5 50 .byte 0x50 + 3099 01f6 0B000000 .4byte .LVL15-1 + 3100 01fa 12000000 .4byte .LFE11 + 3101 01fe 0100 .2byte 0x1 + 3102 0200 54 .byte 0x54 + 3103 0201 00000000 .4byte 0 + 3104 0205 00000000 .4byte 0 + 3105 .LLST16: + 3106 0209 00000000 .4byte .LFB13 + 3107 020d 02000000 .4byte .LCFI6 + 3108 0211 0200 .2byte 0x2 + 3109 0213 7D .byte 0x7d + 3110 0214 00 .sleb128 0 + 3111 0215 02000000 .4byte .LCFI6 + 3112 0219 10000000 .4byte .LFE13 + 3113 021d 0200 .2byte 0x2 + 3114 021f 7D .byte 0x7d + 3115 0220 08 .sleb128 8 + 3116 0221 00000000 .4byte 0 + 3117 0225 00000000 .4byte 0 + 3118 .LLST17: + 3119 0229 00000000 .4byte .LVL17 + 3120 022d 08000000 .4byte .LVL18 + 3121 0231 0100 .2byte 0x1 + 3122 0233 50 .byte 0x50 + 3123 0234 08000000 .4byte .LVL18 + 3124 0238 0B000000 .4byte .LVL19-1 + 3125 023c 0100 .2byte 0x1 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 56 + + + 3126 023e 51 .byte 0x51 + 3127 023f 0B000000 .4byte .LVL19-1 + 3128 0243 10000000 .4byte .LFE13 + 3129 0247 0400 .2byte 0x4 + 3130 0249 F3 .byte 0xf3 + 3131 024a 01 .uleb128 0x1 + 3132 024b 50 .byte 0x50 + 3133 024c 9F .byte 0x9f + 3134 024d 00000000 .4byte 0 + 3135 0251 00000000 .4byte 0 + 3136 .LLST18: + 3137 0255 00000000 .4byte .LFB14 + 3138 0259 02000000 .4byte .LCFI7 + 3139 025d 0200 .2byte 0x2 + 3140 025f 7D .byte 0x7d + 3141 0260 00 .sleb128 0 + 3142 0261 02000000 .4byte .LCFI7 + 3143 0265 1C000000 .4byte .LFE14 + 3144 0269 0200 .2byte 0x2 + 3145 026b 7D .byte 0x7d + 3146 026c 08 .sleb128 8 + 3147 026d 00000000 .4byte 0 + 3148 0271 00000000 .4byte 0 + 3149 .LLST19: + 3150 0275 00000000 .4byte .LVL20 + 3151 0279 08000000 .4byte .LVL21 + 3152 027d 0100 .2byte 0x1 + 3153 027f 50 .byte 0x50 + 3154 0280 08000000 .4byte .LVL21 + 3155 0284 0A000000 .4byte .LVL22 + 3156 0288 0600 .2byte 0x6 + 3157 028a 70 .byte 0x70 + 3158 028b 00 .sleb128 0 + 3159 028c 73 .byte 0x73 + 3160 028d 00 .sleb128 0 + 3161 028e 1C .byte 0x1c + 3162 028f 9F .byte 0x9f + 3163 0290 0A000000 .4byte .LVL22 + 3164 0294 11000000 .4byte .LVL23-1 + 3165 0298 0100 .2byte 0x1 + 3166 029a 51 .byte 0x51 + 3167 029b 00000000 .4byte 0 + 3168 029f 00000000 .4byte 0 + 3169 .LLST20: + 3170 02a3 00000000 .4byte .LFB15 + 3171 02a7 02000000 .4byte .LCFI8 + 3172 02ab 0200 .2byte 0x2 + 3173 02ad 7D .byte 0x7d + 3174 02ae 00 .sleb128 0 + 3175 02af 02000000 .4byte .LCFI8 + 3176 02b3 20000000 .4byte .LFE15 + 3177 02b7 0200 .2byte 0x2 + 3178 02b9 7D .byte 0x7d + 3179 02ba 08 .sleb128 8 + 3180 02bb 00000000 .4byte 0 + 3181 02bf 00000000 .4byte 0 + 3182 .LLST21: + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 57 + + + 3183 02c3 00000000 .4byte .LFB17 + 3184 02c7 02000000 .4byte .LCFI9 + 3185 02cb 0200 .2byte 0x2 + 3186 02cd 7D .byte 0x7d + 3187 02ce 00 .sleb128 0 + 3188 02cf 02000000 .4byte .LCFI9 + 3189 02d3 40000000 .4byte .LFE17 + 3190 02d7 0200 .2byte 0x2 + 3191 02d9 7D .byte 0x7d + 3192 02da 10 .sleb128 16 + 3193 02db 00000000 .4byte 0 + 3194 02df 00000000 .4byte 0 + 3195 .LLST22: + 3196 02e3 00000000 .4byte .LVL25 + 3197 02e7 12000000 .4byte .LVL27 + 3198 02eb 0100 .2byte 0x1 + 3199 02ed 50 .byte 0x50 + 3200 02ee 12000000 .4byte .LVL27 + 3201 02f2 40000000 .4byte .LFE17 + 3202 02f6 0400 .2byte 0x4 + 3203 02f8 F3 .byte 0xf3 + 3204 02f9 01 .uleb128 0x1 + 3205 02fa 50 .byte 0x50 + 3206 02fb 9F .byte 0x9f + 3207 02fc 00000000 .4byte 0 + 3208 0300 00000000 .4byte 0 + 3209 .LLST23: + 3210 0304 12000000 .4byte .LVL27 + 3211 0308 22000000 .4byte .LVL29 + 3212 030c 0300 .2byte 0x3 + 3213 030e 74 .byte 0x74 + 3214 030f 28 .sleb128 40 + 3215 0310 9F .byte 0x9f + 3216 0311 00000000 .4byte 0 + 3217 0315 00000000 .4byte 0 + 3218 .LLST24: + 3219 0319 12000000 .4byte .LVL27 + 3220 031d 1B000000 .4byte .LVL28-1 + 3221 0321 0100 .2byte 0x1 + 3222 0323 53 .byte 0x53 + 3223 0324 00000000 .4byte 0 + 3224 0328 00000000 .4byte 0 + 3225 .LLST25: + 3226 032c 00000000 .4byte .LVL31 + 3227 0330 05000000 .4byte .LVL32-1 + 3228 0334 0100 .2byte 0x1 + 3229 0336 50 .byte 0x50 + 3230 0337 05000000 .4byte .LVL32-1 + 3231 033b 06000000 .4byte .LFE16 + 3232 033f 0400 .2byte 0x4 + 3233 0341 F3 .byte 0xf3 + 3234 0342 01 .uleb128 0x1 + 3235 0343 50 .byte 0x50 + 3236 0344 9F .byte 0x9f + 3237 0345 00000000 .4byte 0 + 3238 0349 00000000 .4byte 0 + 3239 .LLST26: + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 58 + + + 3240 034d 00000000 .4byte .LFB18 + 3241 0351 02000000 .4byte .LCFI10 + 3242 0355 0200 .2byte 0x2 + 3243 0357 7D .byte 0x7d + 3244 0358 00 .sleb128 0 + 3245 0359 02000000 .4byte .LCFI10 + 3246 035d 30000000 .4byte .LFE18 + 3247 0361 0200 .2byte 0x2 + 3248 0363 7D .byte 0x7d + 3249 0364 10 .sleb128 16 + 3250 0365 00000000 .4byte 0 + 3251 0369 00000000 .4byte 0 + 3252 .LLST27: + 3253 036d 00000000 .4byte .LVL33 + 3254 0371 14000000 .4byte .LVL35 + 3255 0375 0100 .2byte 0x1 + 3256 0377 50 .byte 0x50 + 3257 0378 14000000 .4byte .LVL35 + 3258 037c 30000000 .4byte .LFE18 + 3259 0380 0100 .2byte 0x1 + 3260 0382 54 .byte 0x54 + 3261 0383 00000000 .4byte 0 + 3262 0387 00000000 .4byte 0 + 3263 .LLST28: + 3264 038b 12000000 .4byte .LVL34 + 3265 038f 14000000 .4byte .LVL35 + 3266 0393 0300 .2byte 0x3 + 3267 0395 70 .byte 0x70 + 3268 0396 28 .sleb128 40 + 3269 0397 9F .byte 0x9f + 3270 0398 14000000 .4byte .LVL35 + 3271 039c 1C000000 .4byte .LVL36 + 3272 03a0 0300 .2byte 0x3 + 3273 03a2 74 .byte 0x74 + 3274 03a3 28 .sleb128 40 + 3275 03a4 9F .byte 0x9f + 3276 03a5 00000000 .4byte 0 + 3277 03a9 00000000 .4byte 0 + 3278 .LLST29: + 3279 03ad 12000000 .4byte .LVL34 + 3280 03b1 1B000000 .4byte .LVL36-1 + 3281 03b5 0100 .2byte 0x1 + 3282 03b7 53 .byte 0x53 + 3283 03b8 00000000 .4byte 0 + 3284 03bc 00000000 .4byte 0 + 3285 .section .debug_aranges,"",%progbits + 3286 0000 74000000 .4byte 0x74 + 3287 0004 0200 .2byte 0x2 + 3288 0006 00000000 .4byte .Ldebug_info0 + 3289 000a 04 .byte 0x4 + 3290 000b 00 .byte 0 + 3291 000c 0000 .2byte 0 + 3292 000e 0000 .2byte 0 + 3293 0010 00000000 .4byte .LFB7 + 3294 0014 42000000 .4byte .LFE7-.LFB7 + 3295 0018 00000000 .4byte .LFB8 + 3296 001c 68000000 .4byte .LFE8-.LFB8 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 59 + + + 3297 0020 00000000 .4byte .LFB9 + 3298 0024 1E000000 .4byte .LFE9-.LFB9 + 3299 0028 00000000 .4byte .LFB10 + 3300 002c 28000000 .4byte .LFE10-.LFB10 + 3301 0030 00000000 .4byte .LFB11 + 3302 0034 12000000 .4byte .LFE11-.LFB11 + 3303 0038 00000000 .4byte .LFB12 + 3304 003c 0E000000 .4byte .LFE12-.LFB12 + 3305 0040 00000000 .4byte .LFB13 + 3306 0044 10000000 .4byte .LFE13-.LFB13 + 3307 0048 00000000 .4byte .LFB14 + 3308 004c 1C000000 .4byte .LFE14-.LFB14 + 3309 0050 00000000 .4byte .LFB15 + 3310 0054 20000000 .4byte .LFE15-.LFB15 + 3311 0058 00000000 .4byte .LFB17 + 3312 005c 40000000 .4byte .LFE17-.LFB17 + 3313 0060 00000000 .4byte .LFB16 + 3314 0064 06000000 .4byte .LFE16-.LFB16 + 3315 0068 00000000 .4byte .LFB18 + 3316 006c 30000000 .4byte .LFE18-.LFB18 + 3317 0070 00000000 .4byte 0 + 3318 0074 00000000 .4byte 0 + 3319 .section .debug_ranges,"",%progbits + 3320 .Ldebug_ranges0: + 3321 0000 06000000 .4byte .LBB8 + 3322 0004 0E000000 .4byte .LBE8 + 3323 0008 10000000 .4byte .LBB15 + 3324 000c 14000000 .4byte .LBE15 + 3325 0010 1A000000 .4byte .LBB16 + 3326 0014 1C000000 .4byte .LBE16 + 3327 0018 28000000 .4byte .LBB17 + 3328 001c 2A000000 .4byte .LBE17 + 3329 0020 2C000000 .4byte .LBB18 + 3330 0024 42000000 .4byte .LBE18 + 3331 0028 44000000 .4byte .LBB19 + 3332 002c 62000000 .4byte .LBE19 + 3333 0030 00000000 .4byte 0 + 3334 0034 00000000 .4byte 0 + 3335 0038 12000000 .4byte .LBB20 + 3336 003c 14000000 .4byte .LBE20 + 3337 0040 16000000 .4byte .LBB23 + 3338 0044 18000000 .4byte .LBE23 + 3339 0048 00000000 .4byte 0 + 3340 004c 00000000 .4byte 0 + 3341 0050 12000000 .4byte .LBB21 + 3342 0054 14000000 .4byte .LBE21 + 3343 0058 16000000 .4byte .LBB22 + 3344 005c 18000000 .4byte .LBE22 + 3345 0060 00000000 .4byte 0 + 3346 0064 00000000 .4byte 0 + 3347 0068 0E000000 .4byte .LBB24 + 3348 006c 10000000 .4byte .LBE24 + 3349 0070 14000000 .4byte .LBB27 + 3350 0074 18000000 .4byte .LBE27 + 3351 0078 00000000 .4byte 0 + 3352 007c 00000000 .4byte 0 + 3353 0080 00000000 .4byte .LFB7 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 60 + + + 3354 0084 42000000 .4byte .LFE7 + 3355 0088 00000000 .4byte .LFB8 + 3356 008c 68000000 .4byte .LFE8 + 3357 0090 00000000 .4byte .LFB9 + 3358 0094 1E000000 .4byte .LFE9 + 3359 0098 00000000 .4byte .LFB10 + 3360 009c 28000000 .4byte .LFE10 + 3361 00a0 00000000 .4byte .LFB11 + 3362 00a4 12000000 .4byte .LFE11 + 3363 00a8 00000000 .4byte .LFB12 + 3364 00ac 0E000000 .4byte .LFE12 + 3365 00b0 00000000 .4byte .LFB13 + 3366 00b4 10000000 .4byte .LFE13 + 3367 00b8 00000000 .4byte .LFB14 + 3368 00bc 1C000000 .4byte .LFE14 + 3369 00c0 00000000 .4byte .LFB15 + 3370 00c4 20000000 .4byte .LFE15 + 3371 00c8 00000000 .4byte .LFB17 + 3372 00cc 40000000 .4byte .LFE17 + 3373 00d0 00000000 .4byte .LFB16 + 3374 00d4 06000000 .4byte .LFE16 + 3375 00d8 00000000 .4byte .LFB18 + 3376 00dc 30000000 .4byte .LFE18 + 3377 00e0 00000000 .4byte 0 + 3378 00e4 00000000 .4byte 0 + 3379 .section .debug_line,"",%progbits + 3380 .Ldebug_line0: + 3381 0000 14030000 .section .debug_str,"MS",%progbits,1 + 3381 02006301 + 3381 00000201 + 3381 FB0E0D00 + 3381 01010101 + 3382 .LASF72: + 3383 0000 7466756E .ascii "tfunc_t\000" + 3383 635F7400 + 3384 .LASF35: + 3385 0008 705F6D73 .ascii "p_msg\000" + 3385 6700 + 3386 .LASF2: + 3387 000e 73697A65 .ascii "size_t\000" + 3387 5F7400 + 3388 .LASF73: + 3389 0015 7072696F .ascii "prio\000" + 3389 00 + 3390 .LASF67: + 3391 001a 7264796D .ascii "rdymsg\000" + 3391 736700 + 3392 .LASF89: + 3393 0021 76746C69 .ascii "vtlist\000" + 3393 737400 + 3394 .LASF86: + 3395 0028 63685468 .ascii "chThdExitS\000" + 3395 64457869 + 3395 745300 + 3396 .LASF12: + 3397 0033 6C6F6E67 .ascii "long long unsigned int\000" + 3397 206C6F6E + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 61 + + + 3397 6720756E + 3397 7369676E + 3397 65642069 + 3398 .LASF68: + 3399 004a 65786974 .ascii "exitcode\000" + 3399 636F6465 + 3399 00 + 3400 .LASF24: + 3401 0053 705F7072 .ascii "p_prio\000" + 3401 696F00 + 3402 .LASF11: + 3403 005a 6C6F6E67 .ascii "long long int\000" + 3403 206C6F6E + 3403 6720696E + 3403 7400 + 3404 .LASF1: + 3405 0068 7369676E .ascii "signed char\000" + 3405 65642063 + 3405 68617200 + 3406 .LASF87: + 3407 0074 63685468 .ascii "chThdExit\000" + 3407 64457869 + 3407 7400 + 3408 .LASF39: + 3409 007e 705F6D70 .ascii "p_mpool\000" + 3409 6F6F6C00 + 3410 .LASF64: + 3411 0086 6D5F7175 .ascii "m_queue\000" + 3411 65756500 + 3412 .LASF75: + 3413 008e 63685468 .ascii "chThdCreateI\000" + 3413 64437265 + 3413 61746549 + 3413 00 + 3414 .LASF8: + 3415 009b 6C6F6E67 .ascii "long int\000" + 3415 20696E74 + 3415 00 + 3416 .LASF14: + 3417 00a4 74737461 .ascii "tstate_t\000" + 3417 74655F74 + 3417 00 + 3418 .LASF26: + 3419 00ad 705F6E65 .ascii "p_newer\000" + 3419 77657200 + 3420 .LASF101: + 3421 00b5 6C697374 .ascii "list_remove\000" + 3421 5F72656D + 3421 6F766500 + 3422 .LASF93: + 3423 00c1 63685363 .ascii "chSchRescheduleS\000" + 3423 68526573 + 3423 63686564 + 3423 756C6553 + 3423 00 + 3424 .LASF58: + 3425 00d2 725F6E65 .ascii "r_newer\000" + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 62 + + + 3425 77657200 + 3426 .LASF42: + 3427 00da 72656761 .ascii "regarm_t\000" + 3427 726D5F74 + 3427 00 + 3428 .LASF49: + 3429 00e3 76745F70 .ascii "vt_prev\000" + 3429 72657600 + 3430 .LASF99: + 3431 00eb 2E2E2F2E .ascii "../..//os/kernel/src/chthreads.c\000" + 3431 2E2F2F6F + 3431 732F6B65 + 3431 726E656C + 3431 2F737263 + 3432 .LASF94: + 3433 010c 63685363 .ascii "chSchDoReschedule\000" + 3433 68446F52 + 3433 65736368 + 3433 6564756C + 3433 6500 + 3434 .LASF77: + 3435 011e 63685468 .ascii "chThdSetPriority\000" + 3435 64536574 + 3435 5072696F + 3435 72697479 + 3435 00 + 3436 .LASF20: + 3437 012f 636E745F .ascii "cnt_t\000" + 3437 7400 + 3438 .LASF0: + 3439 0135 756E7369 .ascii "unsigned int\000" + 3439 676E6564 + 3439 20696E74 + 3439 00 + 3440 .LASF48: + 3441 0142 76745F6E .ascii "vt_next\000" + 3441 65787400 + 3442 .LASF10: + 3443 014a 6C6F6E67 .ascii "long unsigned int\000" + 3443 20756E73 + 3443 69676E65 + 3443 6420696E + 3443 7400 + 3444 .LASF44: + 3445 015c 636F6E74 .ascii "context\000" + 3445 65787400 + 3446 .LASF74: + 3447 0164 73697A65 .ascii "size\000" + 3447 00 + 3448 .LASF6: + 3449 0169 73686F72 .ascii "short unsigned int\000" + 3449 7420756E + 3449 7369676E + 3449 65642069 + 3449 6E7400 + 3450 .LASF96: + 3451 017c 63685363 .ascii "chSchWakeupS\000" + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 63 + + + 3451 6857616B + 3451 65757053 + 3451 00 + 3452 .LASF17: + 3453 0189 6D73675F .ascii "msg_t\000" + 3453 7400 + 3454 .LASF78: + 3455 018f 6E657770 .ascii "newprio\000" + 3455 72696F00 + 3456 .LASF13: + 3457 0197 746D6F64 .ascii "tmode_t\000" + 3457 655F7400 + 3458 .LASF81: + 3459 019f 63685468 .ascii "chThdTerminate\000" + 3459 64546572 + 3459 6D696E61 + 3459 746500 + 3460 .LASF41: + 3461 01ae 54687265 .ascii "ThreadsList\000" + 3461 6164734C + 3461 69737400 + 3462 .LASF18: + 3463 01ba 6576656E .ascii "eventmask_t\000" + 3463 746D6173 + 3463 6B5F7400 + 3464 .LASF63: + 3465 01c6 4D757465 .ascii "Mutex\000" + 3465 7800 + 3466 .LASF79: + 3467 01cc 6F6C6470 .ascii "oldprio\000" + 3467 72696F00 + 3468 .LASF76: + 3469 01d4 63685468 .ascii "chThdCreateStatic\000" + 3469 64437265 + 3469 61746553 + 3469 74617469 + 3469 6300 + 3470 .LASF102: + 3471 01e6 6C697374 .ascii "list_insert\000" + 3471 5F696E73 + 3471 65727400 + 3472 .LASF50: + 3473 01f2 76745F74 .ascii "vt_time\000" + 3473 696D6500 + 3474 .LASF45: + 3475 01fa 73697A65 .ascii "sizetype\000" + 3475 74797065 + 3475 00 + 3476 .LASF51: + 3477 0203 76745F66 .ascii "vt_func\000" + 3477 756E6300 + 3478 .LASF80: + 3479 020b 63685468 .ascii "chThdResume\000" + 3479 64526573 + 3479 756D6500 + 3480 .LASF27: + 3481 0217 705F6F6C .ascii "p_older\000" + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 64 + + + 3481 64657200 + 3482 .LASF100: + 3483 021f 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 3483 73657273 + 3483 5C496D61 + 3483 6E6F6C5C + 3483 64657665 + 3484 024c 6C696361 .ascii "lications\\smartcities\000" + 3484 74696F6E + 3484 735C736D + 3484 61727463 + 3484 69746965 + 3485 .LASF40: + 3486 0262 54687265 .ascii "ThreadsQueue\000" + 3486 61647351 + 3486 75657565 + 3486 00 + 3487 .LASF83: + 3488 026f 74696D65 .ascii "time\000" + 3488 00 + 3489 .LASF98: + 3490 0274 474E5520 .ascii "GNU C 4.7.2\000" + 3490 4320342E + 3490 372E3200 + 3491 .LASF61: + 3492 0280 725F6375 .ascii "r_current\000" + 3492 7272656E + 3492 7400 + 3493 .LASF59: + 3494 028a 725F6F6C .ascii "r_older\000" + 3494 64657200 + 3495 .LASF84: + 3496 0292 63685468 .ascii "chThdSleepUntil\000" + 3496 64536C65 + 3496 6570556E + 3496 74696C00 + 3497 .LASF15: + 3498 02a2 74726566 .ascii "trefs_t\000" + 3498 735F7400 + 3499 .LASF23: + 3500 02aa 705F7072 .ascii "p_prev\000" + 3500 657600 + 3501 .LASF16: + 3502 02b1 74707269 .ascii "tprio_t\000" + 3502 6F5F7400 + 3503 .LASF7: + 3504 02b9 696E7433 .ascii "int32_t\000" + 3504 325F7400 + 3505 .LASF4: + 3506 02c1 756E7369 .ascii "unsigned char\000" + 3506 676E6564 + 3506 20636861 + 3506 7200 + 3507 .LASF37: + 3508 02cf 705F6D74 .ascii "p_mtxlist\000" + 3508 786C6973 + 3508 7400 + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 65 + + + 3509 .LASF5: + 3510 02d9 73686F72 .ascii "short int\000" + 3510 7420696E + 3510 7400 + 3511 .LASF29: + 3512 02e3 705F7374 .ascii "p_state\000" + 3512 61746500 + 3513 .LASF56: + 3514 02eb 725F7072 .ascii "r_prio\000" + 3514 696F00 + 3515 .LASF70: + 3516 02f2 65776D61 .ascii "ewmask\000" + 3516 736B00 + 3517 .LASF22: + 3518 02f9 705F6E65 .ascii "p_next\000" + 3518 787400 + 3519 .LASF30: + 3520 0300 705F666C .ascii "p_flags\000" + 3520 61677300 + 3521 .LASF103: + 3522 0308 63685468 .ascii "chThdRelease\000" + 3522 6452656C + 3522 65617365 + 3522 00 + 3523 .LASF21: + 3524 0315 54687265 .ascii "Thread\000" + 3524 616400 + 3525 .LASF97: + 3526 031c 63685363 .ascii "chSchGoSleepS\000" + 3526 68476F53 + 3526 6C656570 + 3526 5300 + 3527 .LASF36: + 3528 032a 705F6570 .ascii "p_epending\000" + 3528 656E6469 + 3528 6E6700 + 3529 .LASF9: + 3530 0335 75696E74 .ascii "uint32_t\000" + 3530 33325F74 + 3530 00 + 3531 .LASF91: + 3532 033e 5F746872 .ascii "_thread_init\000" + 3532 6561645F + 3532 696E6974 + 3532 00 + 3533 .LASF55: + 3534 034b 725F7175 .ascii "r_queue\000" + 3534 65756500 + 3535 .LASF47: + 3536 0353 56697274 .ascii "VirtualTimer\000" + 3536 75616C54 + 3536 696D6572 + 3536 00 + 3537 .LASF71: + 3538 0360 63686172 .ascii "char\000" + 3538 00 + 3539 .LASF95: + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 66 + + + 3540 0365 63685363 .ascii "chSchReadyI\000" + 3540 68526561 + 3540 64794900 + 3541 .LASF66: + 3542 0371 6D5F6E65 .ascii "m_next\000" + 3542 787400 + 3543 .LASF19: + 3544 0378 73797374 .ascii "systime_t\000" + 3544 696D655F + 3544 7400 + 3545 .LASF38: + 3546 0382 705F7265 .ascii "p_realprio\000" + 3546 616C7072 + 3546 696F00 + 3547 .LASF46: + 3548 038d 76746675 .ascii "vtfunc_t\000" + 3548 6E635F74 + 3548 00 + 3549 .LASF32: + 3550 0396 705F7469 .ascii "p_time\000" + 3550 6D6500 + 3551 .LASF57: + 3552 039d 725F6374 .ascii "r_ctx\000" + 3552 7800 + 3553 .LASF43: + 3554 03a3 696E7463 .ascii "intctx\000" + 3554 747800 + 3555 .LASF34: + 3556 03aa 705F6D73 .ascii "p_msgqueue\000" + 3556 67717565 + 3556 756500 + 3557 .LASF88: + 3558 03b5 63685468 .ascii "chThdWait\000" + 3558 64576169 + 3558 7400 + 3559 .LASF52: + 3560 03bf 76745F70 .ascii "vt_par\000" + 3560 617200 + 3561 .LASF82: + 3562 03c6 63685468 .ascii "chThdSleep\000" + 3562 64536C65 + 3562 657000 + 3563 .LASF31: + 3564 03d1 705F7265 .ascii "p_refs\000" + 3564 667300 + 3565 .LASF62: + 3566 03d8 52656164 .ascii "ReadyList\000" + 3566 794C6973 + 3566 7400 + 3567 .LASF90: + 3568 03e2 726C6973 .ascii "rlist\000" + 3568 7400 + 3569 .LASF3: + 3570 03e8 75696E74 .ascii "uint8_t\000" + 3570 385F7400 + 3571 .LASF85: + 3572 03f0 63685468 .ascii "chThdYield\000" + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 67 + + + 3572 64596965 + 3572 6C6400 + 3573 .LASF69: + 3574 03fb 77746F62 .ascii "wtobjp\000" + 3574 6A7000 + 3575 .LASF28: + 3576 0402 705F6E61 .ascii "p_name\000" + 3576 6D6500 + 3577 .LASF53: + 3578 0409 76745F73 .ascii "vt_systime\000" + 3578 79737469 + 3578 6D6500 + 3579 .LASF92: + 3580 0414 63685363 .ascii "chSchGoSleepTimeoutS\000" + 3580 68476F53 + 3580 6C656570 + 3580 54696D65 + 3580 6F757453 + 3581 .LASF54: + 3582 0429 56544C69 .ascii "VTList\000" + 3582 737400 + 3583 .LASF60: + 3584 0430 725F7072 .ascii "r_preempt\000" + 3584 65656D70 + 3584 7400 + 3585 .LASF65: + 3586 043a 6D5F6F77 .ascii "m_owner\000" + 3586 6E657200 + 3587 .LASF25: + 3588 0442 705F6374 .ascii "p_ctx\000" + 3588 7800 + 3589 .LASF33: + 3590 0448 705F7761 .ascii "p_waiting\000" + 3590 6974696E + 3590 6700 + 3591 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\ccxOoJzG.s page 68 + + +DEFINED SYMBOLS + *ABS*:00000000 chthreads.c +C:\cygwin\tmp\ccxOoJzG.s:19 .text._thread_init:00000000 $t +C:\cygwin\tmp\ccxOoJzG.s:25 .text._thread_init:00000000 _thread_init +C:\cygwin\tmp\ccxOoJzG.s:93 .text.chThdCreateI:00000000 $t +C:\cygwin\tmp\ccxOoJzG.s:99 .text.chThdCreateI:00000000 chThdCreateI +C:\cygwin\tmp\ccxOoJzG.s:214 .text.chThdCreateStatic:00000000 $t +C:\cygwin\tmp\ccxOoJzG.s:220 .text.chThdCreateStatic:00000000 chThdCreateStatic +C:\cygwin\tmp\ccxOoJzG.s:263 .text.chThdSetPriority:00000000 $t +C:\cygwin\tmp\ccxOoJzG.s:269 .text.chThdSetPriority:00000000 chThdSetPriority +C:\cygwin\tmp\ccxOoJzG.s:318 .text.chThdSetPriority:00000024 $d +C:\cygwin\tmp\ccxOoJzG.s:323 .text.chThdResume:00000000 $t +C:\cygwin\tmp\ccxOoJzG.s:329 .text.chThdResume:00000000 chThdResume +C:\cygwin\tmp\ccxOoJzG.s:364 .text.chThdTerminate:00000000 $t +C:\cygwin\tmp\ccxOoJzG.s:370 .text.chThdTerminate:00000000 chThdTerminate +C:\cygwin\tmp\ccxOoJzG.s:397 .text.chThdSleep:00000000 $t +C:\cygwin\tmp\ccxOoJzG.s:403 .text.chThdSleep:00000000 chThdSleep +C:\cygwin\tmp\ccxOoJzG.s:437 .text.chThdSleepUntil:00000000 $t +C:\cygwin\tmp\ccxOoJzG.s:443 .text.chThdSleepUntil:00000000 chThdSleepUntil +C:\cygwin\tmp\ccxOoJzG.s:481 .text.chThdSleepUntil:00000018 $d +C:\cygwin\tmp\ccxOoJzG.s:486 .text.chThdYield:00000000 $t +C:\cygwin\tmp\ccxOoJzG.s:492 .text.chThdYield:00000000 chThdYield +C:\cygwin\tmp\ccxOoJzG.s:529 .text.chThdYield:0000001c $d +C:\cygwin\tmp\ccxOoJzG.s:534 .text.chThdExitS:00000000 $t +C:\cygwin\tmp\ccxOoJzG.s:540 .text.chThdExitS:00000000 chThdExitS +C:\cygwin\tmp\ccxOoJzG.s:613 .text.chThdExitS:0000003c $d +C:\cygwin\tmp\ccxOoJzG.s:618 .text.chThdExit:00000000 $t +C:\cygwin\tmp\ccxOoJzG.s:624 .text.chThdExit:00000000 chThdExit +C:\cygwin\tmp\ccxOoJzG.s:645 .text.chThdWait:00000000 $t +C:\cygwin\tmp\ccxOoJzG.s:651 .text.chThdWait:00000000 chThdWait +C:\cygwin\tmp\ccxOoJzG.s:720 .text.chThdWait:0000002c $d + .debug_frame:00000010 $d +C:\cygwin\tmp\ccxOoJzG.s:322 .text.chThdSetPriority:00000028 $t +C:\cygwin\tmp\ccxOoJzG.s:485 .text.chThdSleepUntil:0000001c $t + +UNDEFINED SYMBOLS +rlist +_port_thread_start +chSchWakeupS +chSchRescheduleS +chSchGoSleepTimeoutS +vtlist +chSchDoReschedule +chSchReadyI +chSchGoSleepS +chThdRelease diff --git a/Project/applications/smartcities/build/lst/chvt.lst b/Project/applications/smartcities/build/lst/chvt.lst new file mode 100644 index 0000000..edeefdc --- /dev/null +++ b/Project/applications/smartcities/build/lst/chvt.lst @@ -0,0 +1,1272 @@ +ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "chvt.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text._vt_init,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .global _vt_init + 22 .thumb + 23 .thumb_func + 24 .type _vt_init, %function + 25 _vt_init: + 26 .LFB7: + 27 .file 1 "../..//os/kernel/src/chvt.c" + 28 .loc 1 50 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .loc 1 52 0 + 34 0000 40F20003 movw r3, #:lower16:.LANCHOR0 + 35 0004 C0F20003 movt r3, #:upper16:.LANCHOR0 + 36 .loc 1 53 0 + 37 0008 4FF0FF32 mov r2, #-1 + 38 000c 9A60 str r2, [r3, #8] + 39 .loc 1 54 0 + 40 000e 0022 movs r2, #0 + 41 .loc 1 52 0 + 42 0010 5B60 str r3, [r3, #4] + 43 0012 1B60 str r3, [r3, #0] + 44 .loc 1 54 0 + 45 0014 DA60 str r2, [r3, #12] + 46 0016 7047 bx lr + 47 .cfi_endproc + 48 .LFE7: + 49 .size _vt_init, .-_vt_init + 50 0018 AFF30080 .section .text.chVTSetI,"ax",%progbits + 50 AFF30080 + 51 .align 2 + 52 .p2align 4,,15 + 53 .global chVTSetI + 54 .thumb + 55 .thumb_func + 56 .type chVTSetI, %function + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 2 + + + 57 chVTSetI: + 58 .LFB8: + 59 .loc 1 77 0 + 60 .cfi_startproc + 61 @ args = 0, pretend = 0, frame = 0 + 62 @ frame_needed = 0, uses_anonymous_args = 0 + 63 @ link register save eliminated. + 64 .LVL0: + 65 0000 70B4 push {r4, r5, r6} + 66 .LCFI0: + 67 .cfi_def_cfa_offset 12 + 68 .cfi_offset 4, -12 + 69 .cfi_offset 5, -8 + 70 .cfi_offset 6, -4 + 71 .loc 1 86 0 + 72 0002 0D4E ldr r6, .L9 + 73 .loc 1 84 0 + 74 0004 0361 str r3, [r0, #16] + 75 .loc 1 86 0 + 76 0006 3468 ldr r4, [r6, #0] + 77 .LVL1: + 78 .loc 1 85 0 + 79 0008 C260 str r2, [r0, #12] + 80 .loc 1 87 0 + 81 000a A568 ldr r5, [r4, #8] + 82 000c A942 cmp r1, r5 + 83 000e 04D9 bls .L3 + 84 .L6: + 85 .loc 1 89 0 + 86 0010 2468 ldr r4, [r4, #0] + 87 .LVL2: + 88 .loc 1 88 0 + 89 0012 491B subs r1, r1, r5 + 90 .LVL3: + 91 .loc 1 87 0 + 92 0014 A568 ldr r5, [r4, #8] + 93 0016 8D42 cmp r5, r1 + 94 0018 FAD3 bcc .L6 + 95 .L3: + 96 .loc 1 92 0 + 97 001a 6368 ldr r3, [r4, #4] + 98 .LVL4: + 99 .loc 1 94 0 + 100 001c 8160 str r1, [r0, #8] + 101 .loc 1 95 0 + 102 001e B442 cmp r4, r6 + 103 .loc 1 92 0 + 104 0020 4360 str r3, [r0, #4] + 105 0022 0460 str r4, [r0, #0] + 106 .loc 1 93 0 + 107 0024 1860 str r0, [r3, #0] + 108 .loc 1 96 0 + 109 0026 18BF it ne + 110 0028 A368 ldrne r3, [r4, #8] + 111 .loc 1 93 0 + 112 002a 6060 str r0, [r4, #4] + 113 .loc 1 96 0 + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 3 + + + 114 002c 1CBF itt ne + 115 002e C1EB0301 rsbne r1, r1, r3 + 116 .LVL5: + 117 0032 A160 strne r1, [r4, #8] + 118 .loc 1 97 0 + 119 0034 70BC pop {r4, r5, r6} + 120 0036 7047 bx lr + 121 .L10: + 122 .align 2 + 123 .L9: + 124 0038 00000000 .word .LANCHOR0 + 125 .cfi_endproc + 126 .LFE8: + 127 .size chVTSetI, .-chVTSetI + 128 003c AFF30080 .section .text.chVTResetI,"ax",%progbits + 129 .align 2 + 130 .p2align 4,,15 + 131 .global chVTResetI + 132 .thumb + 133 .thumb_func + 134 .type chVTResetI, %function + 135 chVTResetI: + 136 .LFB9: + 137 .loc 1 107 0 + 138 .cfi_startproc + 139 @ args = 0, pretend = 0, frame = 0 + 140 @ frame_needed = 0, uses_anonymous_args = 0 + 141 @ link register save eliminated. + 142 .LVL6: + 143 .loc 1 115 0 + 144 0000 0368 ldr r3, [r0, #0] + 145 0002 074A ldr r2, .L13 + 146 0004 9342 cmp r3, r2 + 147 .loc 1 116 0 + 148 0006 1FBF itttt ne + 149 0008 9968 ldrne r1, [r3, #8] + 150 000a 8268 ldrne r2, [r0, #8] + 151 000c 8A18 addne r2, r1, r2 + 152 000e 9A60 strne r2, [r3, #8] + 153 .loc 1 117 0 + 154 0010 4268 ldr r2, [r0, #4] + 155 .loc 1 119 0 + 156 0012 0021 movs r1, #0 + 157 .loc 1 117 0 + 158 0014 1360 str r3, [r2, #0] + 159 .loc 1 118 0 + 160 0016 0368 ldr r3, [r0, #0] + 161 .loc 1 119 0 + 162 0018 C160 str r1, [r0, #12] + 163 .loc 1 118 0 + 164 001a 5A60 str r2, [r3, #4] + 165 001c 7047 bx lr + 166 .L14: + 167 001e 00BF .align 2 + 168 .L13: + 169 0020 00000000 .word .LANCHOR0 + 170 .cfi_endproc + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 4 + + + 171 .LFE9: + 172 .size chVTResetI, .-chVTResetI + 173 0024 AFF30080 .section .text.chTimeIsWithin,"ax",%progbits + 173 AFF30080 + 173 AFF30080 + 174 .align 2 + 175 .p2align 4,,15 + 176 .global chTimeIsWithin + 177 .thumb + 178 .thumb_func + 179 .type chTimeIsWithin, %function + 180 chTimeIsWithin: + 181 .LFB10: + 182 .loc 1 135 0 + 183 .cfi_startproc + 184 @ args = 0, pretend = 0, frame = 0 + 185 @ frame_needed = 0, uses_anonymous_args = 0 + 186 @ link register save eliminated. + 187 .LVL7: + 188 .loc 1 137 0 + 189 0000 0B4A ldr r2, .L19 + 190 .loc 1 138 0 + 191 0002 8142 cmp r1, r0 + 192 .loc 1 135 0 + 193 0004 0346 mov r3, r0 + 194 .loc 1 137 0 + 195 0006 D268 ldr r2, [r2, #12] + 196 .LVL8: + 197 .loc 1 138 0 + 198 0008 09D8 bhi .L18 + 199 .loc 1 139 0 discriminator 2 + 200 000a 8242 cmp r2, r0 + 201 000c 34BF ite cc + 202 000e 0023 movcc r3, #0 + 203 0010 0123 movcs r3, #1 + 204 .loc 1 138 0 discriminator 2 + 205 0012 8A42 cmp r2, r1 + 206 0014 2CBF ite cs + 207 0016 1846 movcs r0, r3 + 208 0018 43F00100 orrcc r0, r3, #1 + 209 .LVL9: + 210 .loc 1 140 0 discriminator 2 + 211 001c 7047 bx lr + 212 .LVL10: + 213 .L18: + 214 .loc 1 138 0 discriminator 1 + 215 001e 8A42 cmp r2, r1 + 216 0020 2CBF ite cs + 217 0022 0020 movcs r0, #0 + 218 .LVL11: + 219 0024 0120 movcc r0, #1 + 220 0026 9A42 cmp r2, r3 + 221 0028 38BF it cc + 222 002a 0020 movcc r0, #0 + 223 002c 7047 bx lr + 224 .L20: + 225 002e 00BF .align 2 + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 5 + + + 226 .L19: + 227 0030 00000000 .word .LANCHOR0 + 228 .cfi_endproc + 229 .LFE10: + 230 .size chTimeIsWithin, .-chTimeIsWithin + 231 .global vtlist + 232 0034 AFF30080 .section .bss.vtlist,"aw",%nobits + 232 AFF30080 + 232 AFF30080 + 233 .align 2 + 234 .set .LANCHOR0,. + 0 + 235 .type vtlist, %object + 236 .size vtlist, 16 + 237 vtlist: + 238 0000 00000000 .space 16 + 238 00000000 + 238 00000000 + 238 00000000 + 239 .text + 240 .Letext0: + 241 .file 2 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 242 .file 3 "../..//os/ports/GCC/ARMCMx/chtypes.h" + 243 .file 4 "../..//os/kernel/include/chvt.h" + 244 .section .debug_info,"",%progbits + 245 .Ldebug_info0: + 246 0000 6F020000 .4byte 0x26f + 247 0004 0200 .2byte 0x2 + 248 0006 00000000 .4byte .Ldebug_abbrev0 + 249 000a 04 .byte 0x4 + 250 000b 01 .uleb128 0x1 + 251 000c 47010000 .4byte .LASF29 + 252 0010 01 .byte 0x1 + 253 0011 7E000000 .4byte .LASF30 + 254 0015 00000000 .4byte .LASF31 + 255 0019 00000000 .4byte .Ldebug_ranges0+0 + 256 001d 00000000 .4byte 0 + 257 0021 00000000 .4byte 0 + 258 0025 00000000 .4byte .Ldebug_line0 + 259 0029 02 .uleb128 0x2 + 260 002a 04 .byte 0x4 + 261 002b 05 .byte 0x5 + 262 002c 696E7400 .ascii "int\000" + 263 0030 03 .uleb128 0x3 + 264 0031 04 .byte 0x4 + 265 0032 07 .byte 0x7 + 266 0033 D1000000 .4byte .LASF0 + 267 0037 03 .uleb128 0x3 + 268 0038 01 .byte 0x1 + 269 0039 06 .byte 0x6 + 270 003a 8D010000 .4byte .LASF1 + 271 003e 03 .uleb128 0x3 + 272 003f 01 .byte 0x1 + 273 0040 08 .byte 0x8 + 274 0041 BA000000 .4byte .LASF2 + 275 0045 03 .uleb128 0x3 + 276 0046 02 .byte 0x2 + 277 0047 05 .byte 0x5 + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 6 + + + 278 0048 5A010000 .4byte .LASF3 + 279 004c 03 .uleb128 0x3 + 280 004d 02 .byte 0x2 + 281 004e 07 .byte 0x7 + 282 004f 9A000000 .4byte .LASF4 + 283 0053 04 .uleb128 0x4 + 284 0054 09010000 .4byte .LASF6 + 285 0058 02 .byte 0x2 + 286 0059 4F .byte 0x4f + 287 005a 5E000000 .4byte 0x5e + 288 005e 03 .uleb128 0x3 + 289 005f 04 .byte 0x4 + 290 0060 05 .byte 0x5 + 291 0061 84010000 .4byte .LASF5 + 292 0065 04 .uleb128 0x4 + 293 0066 7B010000 .4byte .LASF7 + 294 006a 02 .byte 0x2 + 295 006b 50 .byte 0x50 + 296 006c 70000000 .4byte 0x70 + 297 0070 03 .uleb128 0x3 + 298 0071 04 .byte 0x4 + 299 0072 07 .byte 0x7 + 300 0073 6C000000 .4byte .LASF8 + 301 0077 03 .uleb128 0x3 + 302 0078 08 .byte 0x8 + 303 0079 05 .byte 0x5 + 304 007a 25010000 .4byte .LASF9 + 305 007e 03 .uleb128 0x3 + 306 007f 08 .byte 0x8 + 307 0080 07 .byte 0x7 + 308 0081 DE000000 .4byte .LASF10 + 309 0085 04 .uleb128 0x4 + 310 0086 5C000000 .4byte .LASF11 + 311 008a 03 .byte 0x3 + 312 008b 2E .byte 0x2e + 313 008c 53000000 .4byte 0x53 + 314 0090 04 .uleb128 0x4 + 315 0091 4C000000 .4byte .LASF12 + 316 0095 03 .byte 0x3 + 317 0096 36 .byte 0x36 + 318 0097 65000000 .4byte 0x65 + 319 009b 05 .uleb128 0x5 + 320 009c 04 .byte 0x4 + 321 009d 03 .uleb128 0x3 + 322 009e 04 .byte 0x4 + 323 009f 07 .byte 0x7 + 324 00a0 11010000 .4byte .LASF13 + 325 00a4 04 .uleb128 0x4 + 326 00a5 63000000 .4byte .LASF14 + 327 00a9 04 .byte 0x4 + 328 00aa 61 .byte 0x61 + 329 00ab AF000000 .4byte 0xaf + 330 00af 06 .uleb128 0x6 + 331 00b0 04 .byte 0x4 + 332 00b1 B5000000 .4byte 0xb5 + 333 00b5 07 .uleb128 0x7 + 334 00b6 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 7 + + + 335 00b7 C1000000 .4byte 0xc1 + 336 00bb 08 .uleb128 0x8 + 337 00bc 9B000000 .4byte 0x9b + 338 00c0 00 .byte 0 + 339 00c1 04 .uleb128 0x4 + 340 00c2 AD000000 .4byte .LASF15 + 341 00c6 04 .byte 0x4 + 342 00c7 66 .byte 0x66 + 343 00c8 CC000000 .4byte 0xcc + 344 00cc 09 .uleb128 0x9 + 345 00cd AD000000 .4byte .LASF15 + 346 00d1 14 .byte 0x14 + 347 00d2 04 .byte 0x4 + 348 00d3 6D .byte 0x6d + 349 00d4 1F010000 .4byte 0x11f + 350 00d8 0A .uleb128 0xa + 351 00d9 A0010000 .4byte .LASF16 + 352 00dd 04 .byte 0x4 + 353 00de 6E .byte 0x6e + 354 00df 1F010000 .4byte 0x11f + 355 00e3 02 .byte 0x2 + 356 00e4 23 .byte 0x23 + 357 00e5 00 .uleb128 0 + 358 00e6 0A .uleb128 0xa + 359 00e7 73010000 .4byte .LASF17 + 360 00eb 04 .byte 0x4 + 361 00ec 70 .byte 0x70 + 362 00ed 1F010000 .4byte 0x11f + 363 00f1 02 .byte 0x2 + 364 00f2 23 .byte 0x23 + 365 00f3 04 .uleb128 0x4 + 366 00f4 0A .uleb128 0xa + 367 00f5 01010000 .4byte .LASF18 + 368 00f9 04 .byte 0x4 + 369 00fa 72 .byte 0x72 + 370 00fb 90000000 .4byte 0x90 + 371 00ff 02 .byte 0x2 + 372 0100 23 .byte 0x23 + 373 0101 08 .uleb128 0x8 + 374 0102 0A .uleb128 0xa + 375 0103 33010000 .4byte .LASF19 + 376 0107 04 .byte 0x4 + 377 0108 73 .byte 0x73 + 378 0109 A4000000 .4byte 0xa4 + 379 010d 02 .byte 0x2 + 380 010e 23 .byte 0x23 + 381 010f 0C .uleb128 0xc + 382 0110 0A .uleb128 0xa + 383 0111 53010000 .4byte .LASF20 + 384 0115 04 .byte 0x4 + 385 0116 75 .byte 0x75 + 386 0117 9B000000 .4byte 0x9b + 387 011b 02 .byte 0x2 + 388 011c 23 .byte 0x23 + 389 011d 10 .uleb128 0x10 + 390 011e 00 .byte 0 + 391 011f 06 .uleb128 0x6 + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 8 + + + 392 0120 04 .byte 0x4 + 393 0121 C1000000 .4byte 0xc1 + 394 0125 0B .uleb128 0xb + 395 0126 10 .byte 0x10 + 396 0127 04 .byte 0x4 + 397 0128 7F .byte 0x7f + 398 0129 66010000 .4byte 0x166 + 399 012d 0A .uleb128 0xa + 400 012e A0010000 .4byte .LASF16 + 401 0132 04 .byte 0x4 + 402 0133 80 .byte 0x80 + 403 0134 1F010000 .4byte 0x11f + 404 0138 02 .byte 0x2 + 405 0139 23 .byte 0x23 + 406 013a 00 .uleb128 0 + 407 013b 0A .uleb128 0xa + 408 013c 73010000 .4byte .LASF17 + 409 0140 04 .byte 0x4 + 410 0141 82 .byte 0x82 + 411 0142 1F010000 .4byte 0x11f + 412 0146 02 .byte 0x2 + 413 0147 23 .byte 0x23 + 414 0148 04 .uleb128 0x4 + 415 0149 0A .uleb128 0xa + 416 014a 01010000 .4byte .LASF18 + 417 014e 04 .byte 0x4 + 418 014f 84 .byte 0x84 + 419 0150 90000000 .4byte 0x90 + 420 0154 02 .byte 0x2 + 421 0155 23 .byte 0x23 + 422 0156 08 .uleb128 0x8 + 423 0157 0A .uleb128 0xa + 424 0158 1A010000 .4byte .LASF21 + 425 015c 04 .byte 0x4 + 426 015d 85 .byte 0x85 + 427 015e 66010000 .4byte 0x166 + 428 0162 02 .byte 0x2 + 429 0163 23 .byte 0x23 + 430 0164 0C .uleb128 0xc + 431 0165 00 .byte 0 + 432 0166 0C .uleb128 0xc + 433 0167 90000000 .4byte 0x90 + 434 016b 04 .uleb128 0x4 + 435 016c 99010000 .4byte .LASF22 + 436 0170 04 .byte 0x4 + 437 0171 86 .byte 0x86 + 438 0172 25010000 .4byte 0x125 + 439 0176 03 .uleb128 0x3 + 440 0177 01 .byte 0x1 + 441 0178 08 .byte 0x8 + 442 0179 42010000 .4byte .LASF23 + 443 017d 0D .uleb128 0xd + 444 017e 01 .byte 0x1 + 445 017f C8000000 .4byte .LASF32 + 446 0183 01 .byte 0x1 + 447 0184 32 .byte 0x32 + 448 0185 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 9 + + + 449 0186 00000000 .4byte .LFB7 + 450 018a 18000000 .4byte .LFE7 + 451 018e 02 .byte 0x2 + 452 018f 7D .byte 0x7d + 453 0190 00 .sleb128 0 + 454 0191 01 .byte 0x1 + 455 0192 0E .uleb128 0xe + 456 0193 01 .byte 0x1 + 457 0194 43000000 .4byte .LASF26 + 458 0198 01 .byte 0x1 + 459 0199 4D .byte 0x4d + 460 019a 01 .byte 0x1 + 461 019b 00000000 .4byte .LFB8 + 462 019f 3C000000 .4byte .LFE8 + 463 01a3 00000000 .4byte .LLST0 + 464 01a7 01 .byte 0x1 + 465 01a8 F2010000 .4byte 0x1f2 + 466 01ac 0F .uleb128 0xf + 467 01ad 76747000 .ascii "vtp\000" + 468 01b1 01 .byte 0x1 + 469 01b2 4D .byte 0x4d + 470 01b3 1F010000 .4byte 0x11f + 471 01b7 01 .byte 0x1 + 472 01b8 50 .byte 0x50 + 473 01b9 10 .uleb128 0x10 + 474 01ba FC000000 .4byte .LASF24 + 475 01be 01 .byte 0x1 + 476 01bf 4D .byte 0x4d + 477 01c0 90000000 .4byte 0x90 + 478 01c4 20000000 .4byte .LLST1 + 479 01c8 11 .uleb128 0x11 + 480 01c9 3B010000 .4byte .LASF25 + 481 01cd 01 .byte 0x1 + 482 01ce 4D .byte 0x4d + 483 01cf A4000000 .4byte 0xa4 + 484 01d3 01 .byte 0x1 + 485 01d4 52 .byte 0x52 + 486 01d5 12 .uleb128 0x12 + 487 01d6 70617200 .ascii "par\000" + 488 01da 01 .byte 0x1 + 489 01db 4D .byte 0x4d + 490 01dc 9B000000 .4byte 0x9b + 491 01e0 4D000000 .4byte .LLST2 + 492 01e4 13 .uleb128 0x13 + 493 01e5 7000 .ascii "p\000" + 494 01e7 01 .byte 0x1 + 495 01e8 4E .byte 0x4e + 496 01e9 1F010000 .4byte 0x11f + 497 01ed 6C000000 .4byte .LLST3 + 498 01f1 00 .byte 0 + 499 01f2 14 .uleb128 0x14 + 500 01f3 01 .byte 0x1 + 501 01f4 A8010000 .4byte .LASF27 + 502 01f8 01 .byte 0x1 + 503 01f9 6B .byte 0x6b + 504 01fa 01 .byte 0x1 + 505 01fb 00000000 .4byte .LFB9 + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 10 + + + 506 01ff 24000000 .4byte .LFE9 + 507 0203 02 .byte 0x2 + 508 0204 7D .byte 0x7d + 509 0205 00 .sleb128 0 + 510 0206 01 .byte 0x1 + 511 0207 19020000 .4byte 0x219 + 512 020b 0F .uleb128 0xf + 513 020c 76747000 .ascii "vtp\000" + 514 0210 01 .byte 0x1 + 515 0211 6B .byte 0x6b + 516 0212 1F010000 .4byte 0x11f + 517 0216 01 .byte 0x1 + 518 0217 50 .byte 0x50 + 519 0218 00 .byte 0 + 520 0219 15 .uleb128 0x15 + 521 021a 01 .byte 0x1 + 522 021b 64010000 .4byte .LASF33 + 523 021f 01 .byte 0x1 + 524 0220 87 .byte 0x87 + 525 0221 01 .byte 0x1 + 526 0222 85000000 .4byte 0x85 + 527 0226 00000000 .4byte .LFB10 + 528 022a 34000000 .4byte .LFE10 + 529 022e 02 .byte 0x2 + 530 022f 7D .byte 0x7d + 531 0230 00 .sleb128 0 + 532 0231 01 .byte 0x1 + 533 0232 60020000 .4byte 0x260 + 534 0236 10 .uleb128 0x10 + 535 0237 56000000 .4byte .LASF28 + 536 023b 01 .byte 0x1 + 537 023c 87 .byte 0x87 + 538 023d 90000000 .4byte 0x90 + 539 0241 8A000000 .4byte .LLST4 + 540 0245 0F .uleb128 0xf + 541 0246 656E6400 .ascii "end\000" + 542 024a 01 .byte 0x1 + 543 024b 87 .byte 0x87 + 544 024c 90000000 .4byte 0x90 + 545 0250 01 .byte 0x1 + 546 0251 51 .byte 0x51 + 547 0252 16 .uleb128 0x16 + 548 0253 FC000000 .4byte .LASF24 + 549 0257 01 .byte 0x1 + 550 0258 89 .byte 0x89 + 551 0259 90000000 .4byte 0x90 + 552 025d 01 .byte 0x1 + 553 025e 52 .byte 0x52 + 554 025f 00 .byte 0 + 555 0260 17 .uleb128 0x17 + 556 0261 F5000000 .4byte .LASF34 + 557 0265 01 .byte 0x1 + 558 0266 2A .byte 0x2a + 559 0267 6B010000 .4byte 0x16b + 560 026b 01 .byte 0x1 + 561 026c 05 .byte 0x5 + 562 026d 03 .byte 0x3 + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 11 + + + 563 026e 00000000 .4byte vtlist + 564 0272 00 .byte 0 + 565 .section .debug_abbrev,"",%progbits + 566 .Ldebug_abbrev0: + 567 0000 01 .uleb128 0x1 + 568 0001 11 .uleb128 0x11 + 569 0002 01 .byte 0x1 + 570 0003 25 .uleb128 0x25 + 571 0004 0E .uleb128 0xe + 572 0005 13 .uleb128 0x13 + 573 0006 0B .uleb128 0xb + 574 0007 03 .uleb128 0x3 + 575 0008 0E .uleb128 0xe + 576 0009 1B .uleb128 0x1b + 577 000a 0E .uleb128 0xe + 578 000b 55 .uleb128 0x55 + 579 000c 06 .uleb128 0x6 + 580 000d 11 .uleb128 0x11 + 581 000e 01 .uleb128 0x1 + 582 000f 52 .uleb128 0x52 + 583 0010 01 .uleb128 0x1 + 584 0011 10 .uleb128 0x10 + 585 0012 06 .uleb128 0x6 + 586 0013 00 .byte 0 + 587 0014 00 .byte 0 + 588 0015 02 .uleb128 0x2 + 589 0016 24 .uleb128 0x24 + 590 0017 00 .byte 0 + 591 0018 0B .uleb128 0xb + 592 0019 0B .uleb128 0xb + 593 001a 3E .uleb128 0x3e + 594 001b 0B .uleb128 0xb + 595 001c 03 .uleb128 0x3 + 596 001d 08 .uleb128 0x8 + 597 001e 00 .byte 0 + 598 001f 00 .byte 0 + 599 0020 03 .uleb128 0x3 + 600 0021 24 .uleb128 0x24 + 601 0022 00 .byte 0 + 602 0023 0B .uleb128 0xb + 603 0024 0B .uleb128 0xb + 604 0025 3E .uleb128 0x3e + 605 0026 0B .uleb128 0xb + 606 0027 03 .uleb128 0x3 + 607 0028 0E .uleb128 0xe + 608 0029 00 .byte 0 + 609 002a 00 .byte 0 + 610 002b 04 .uleb128 0x4 + 611 002c 16 .uleb128 0x16 + 612 002d 00 .byte 0 + 613 002e 03 .uleb128 0x3 + 614 002f 0E .uleb128 0xe + 615 0030 3A .uleb128 0x3a + 616 0031 0B .uleb128 0xb + 617 0032 3B .uleb128 0x3b + 618 0033 0B .uleb128 0xb + 619 0034 49 .uleb128 0x49 + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 12 + + + 620 0035 13 .uleb128 0x13 + 621 0036 00 .byte 0 + 622 0037 00 .byte 0 + 623 0038 05 .uleb128 0x5 + 624 0039 0F .uleb128 0xf + 625 003a 00 .byte 0 + 626 003b 0B .uleb128 0xb + 627 003c 0B .uleb128 0xb + 628 003d 00 .byte 0 + 629 003e 00 .byte 0 + 630 003f 06 .uleb128 0x6 + 631 0040 0F .uleb128 0xf + 632 0041 00 .byte 0 + 633 0042 0B .uleb128 0xb + 634 0043 0B .uleb128 0xb + 635 0044 49 .uleb128 0x49 + 636 0045 13 .uleb128 0x13 + 637 0046 00 .byte 0 + 638 0047 00 .byte 0 + 639 0048 07 .uleb128 0x7 + 640 0049 15 .uleb128 0x15 + 641 004a 01 .byte 0x1 + 642 004b 27 .uleb128 0x27 + 643 004c 0C .uleb128 0xc + 644 004d 01 .uleb128 0x1 + 645 004e 13 .uleb128 0x13 + 646 004f 00 .byte 0 + 647 0050 00 .byte 0 + 648 0051 08 .uleb128 0x8 + 649 0052 05 .uleb128 0x5 + 650 0053 00 .byte 0 + 651 0054 49 .uleb128 0x49 + 652 0055 13 .uleb128 0x13 + 653 0056 00 .byte 0 + 654 0057 00 .byte 0 + 655 0058 09 .uleb128 0x9 + 656 0059 13 .uleb128 0x13 + 657 005a 01 .byte 0x1 + 658 005b 03 .uleb128 0x3 + 659 005c 0E .uleb128 0xe + 660 005d 0B .uleb128 0xb + 661 005e 0B .uleb128 0xb + 662 005f 3A .uleb128 0x3a + 663 0060 0B .uleb128 0xb + 664 0061 3B .uleb128 0x3b + 665 0062 0B .uleb128 0xb + 666 0063 01 .uleb128 0x1 + 667 0064 13 .uleb128 0x13 + 668 0065 00 .byte 0 + 669 0066 00 .byte 0 + 670 0067 0A .uleb128 0xa + 671 0068 0D .uleb128 0xd + 672 0069 00 .byte 0 + 673 006a 03 .uleb128 0x3 + 674 006b 0E .uleb128 0xe + 675 006c 3A .uleb128 0x3a + 676 006d 0B .uleb128 0xb + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 13 + + + 677 006e 3B .uleb128 0x3b + 678 006f 0B .uleb128 0xb + 679 0070 49 .uleb128 0x49 + 680 0071 13 .uleb128 0x13 + 681 0072 38 .uleb128 0x38 + 682 0073 0A .uleb128 0xa + 683 0074 00 .byte 0 + 684 0075 00 .byte 0 + 685 0076 0B .uleb128 0xb + 686 0077 13 .uleb128 0x13 + 687 0078 01 .byte 0x1 + 688 0079 0B .uleb128 0xb + 689 007a 0B .uleb128 0xb + 690 007b 3A .uleb128 0x3a + 691 007c 0B .uleb128 0xb + 692 007d 3B .uleb128 0x3b + 693 007e 0B .uleb128 0xb + 694 007f 01 .uleb128 0x1 + 695 0080 13 .uleb128 0x13 + 696 0081 00 .byte 0 + 697 0082 00 .byte 0 + 698 0083 0C .uleb128 0xc + 699 0084 35 .uleb128 0x35 + 700 0085 00 .byte 0 + 701 0086 49 .uleb128 0x49 + 702 0087 13 .uleb128 0x13 + 703 0088 00 .byte 0 + 704 0089 00 .byte 0 + 705 008a 0D .uleb128 0xd + 706 008b 2E .uleb128 0x2e + 707 008c 00 .byte 0 + 708 008d 3F .uleb128 0x3f + 709 008e 0C .uleb128 0xc + 710 008f 03 .uleb128 0x3 + 711 0090 0E .uleb128 0xe + 712 0091 3A .uleb128 0x3a + 713 0092 0B .uleb128 0xb + 714 0093 3B .uleb128 0x3b + 715 0094 0B .uleb128 0xb + 716 0095 27 .uleb128 0x27 + 717 0096 0C .uleb128 0xc + 718 0097 11 .uleb128 0x11 + 719 0098 01 .uleb128 0x1 + 720 0099 12 .uleb128 0x12 + 721 009a 01 .uleb128 0x1 + 722 009b 40 .uleb128 0x40 + 723 009c 0A .uleb128 0xa + 724 009d 9742 .uleb128 0x2117 + 725 009f 0C .uleb128 0xc + 726 00a0 00 .byte 0 + 727 00a1 00 .byte 0 + 728 00a2 0E .uleb128 0xe + 729 00a3 2E .uleb128 0x2e + 730 00a4 01 .byte 0x1 + 731 00a5 3F .uleb128 0x3f + 732 00a6 0C .uleb128 0xc + 733 00a7 03 .uleb128 0x3 + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 14 + + + 734 00a8 0E .uleb128 0xe + 735 00a9 3A .uleb128 0x3a + 736 00aa 0B .uleb128 0xb + 737 00ab 3B .uleb128 0x3b + 738 00ac 0B .uleb128 0xb + 739 00ad 27 .uleb128 0x27 + 740 00ae 0C .uleb128 0xc + 741 00af 11 .uleb128 0x11 + 742 00b0 01 .uleb128 0x1 + 743 00b1 12 .uleb128 0x12 + 744 00b2 01 .uleb128 0x1 + 745 00b3 40 .uleb128 0x40 + 746 00b4 06 .uleb128 0x6 + 747 00b5 9742 .uleb128 0x2117 + 748 00b7 0C .uleb128 0xc + 749 00b8 01 .uleb128 0x1 + 750 00b9 13 .uleb128 0x13 + 751 00ba 00 .byte 0 + 752 00bb 00 .byte 0 + 753 00bc 0F .uleb128 0xf + 754 00bd 05 .uleb128 0x5 + 755 00be 00 .byte 0 + 756 00bf 03 .uleb128 0x3 + 757 00c0 08 .uleb128 0x8 + 758 00c1 3A .uleb128 0x3a + 759 00c2 0B .uleb128 0xb + 760 00c3 3B .uleb128 0x3b + 761 00c4 0B .uleb128 0xb + 762 00c5 49 .uleb128 0x49 + 763 00c6 13 .uleb128 0x13 + 764 00c7 02 .uleb128 0x2 + 765 00c8 0A .uleb128 0xa + 766 00c9 00 .byte 0 + 767 00ca 00 .byte 0 + 768 00cb 10 .uleb128 0x10 + 769 00cc 05 .uleb128 0x5 + 770 00cd 00 .byte 0 + 771 00ce 03 .uleb128 0x3 + 772 00cf 0E .uleb128 0xe + 773 00d0 3A .uleb128 0x3a + 774 00d1 0B .uleb128 0xb + 775 00d2 3B .uleb128 0x3b + 776 00d3 0B .uleb128 0xb + 777 00d4 49 .uleb128 0x49 + 778 00d5 13 .uleb128 0x13 + 779 00d6 02 .uleb128 0x2 + 780 00d7 06 .uleb128 0x6 + 781 00d8 00 .byte 0 + 782 00d9 00 .byte 0 + 783 00da 11 .uleb128 0x11 + 784 00db 05 .uleb128 0x5 + 785 00dc 00 .byte 0 + 786 00dd 03 .uleb128 0x3 + 787 00de 0E .uleb128 0xe + 788 00df 3A .uleb128 0x3a + 789 00e0 0B .uleb128 0xb + 790 00e1 3B .uleb128 0x3b + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 15 + + + 791 00e2 0B .uleb128 0xb + 792 00e3 49 .uleb128 0x49 + 793 00e4 13 .uleb128 0x13 + 794 00e5 02 .uleb128 0x2 + 795 00e6 0A .uleb128 0xa + 796 00e7 00 .byte 0 + 797 00e8 00 .byte 0 + 798 00e9 12 .uleb128 0x12 + 799 00ea 05 .uleb128 0x5 + 800 00eb 00 .byte 0 + 801 00ec 03 .uleb128 0x3 + 802 00ed 08 .uleb128 0x8 + 803 00ee 3A .uleb128 0x3a + 804 00ef 0B .uleb128 0xb + 805 00f0 3B .uleb128 0x3b + 806 00f1 0B .uleb128 0xb + 807 00f2 49 .uleb128 0x49 + 808 00f3 13 .uleb128 0x13 + 809 00f4 02 .uleb128 0x2 + 810 00f5 06 .uleb128 0x6 + 811 00f6 00 .byte 0 + 812 00f7 00 .byte 0 + 813 00f8 13 .uleb128 0x13 + 814 00f9 34 .uleb128 0x34 + 815 00fa 00 .byte 0 + 816 00fb 03 .uleb128 0x3 + 817 00fc 08 .uleb128 0x8 + 818 00fd 3A .uleb128 0x3a + 819 00fe 0B .uleb128 0xb + 820 00ff 3B .uleb128 0x3b + 821 0100 0B .uleb128 0xb + 822 0101 49 .uleb128 0x49 + 823 0102 13 .uleb128 0x13 + 824 0103 02 .uleb128 0x2 + 825 0104 06 .uleb128 0x6 + 826 0105 00 .byte 0 + 827 0106 00 .byte 0 + 828 0107 14 .uleb128 0x14 + 829 0108 2E .uleb128 0x2e + 830 0109 01 .byte 0x1 + 831 010a 3F .uleb128 0x3f + 832 010b 0C .uleb128 0xc + 833 010c 03 .uleb128 0x3 + 834 010d 0E .uleb128 0xe + 835 010e 3A .uleb128 0x3a + 836 010f 0B .uleb128 0xb + 837 0110 3B .uleb128 0x3b + 838 0111 0B .uleb128 0xb + 839 0112 27 .uleb128 0x27 + 840 0113 0C .uleb128 0xc + 841 0114 11 .uleb128 0x11 + 842 0115 01 .uleb128 0x1 + 843 0116 12 .uleb128 0x12 + 844 0117 01 .uleb128 0x1 + 845 0118 40 .uleb128 0x40 + 846 0119 0A .uleb128 0xa + 847 011a 9742 .uleb128 0x2117 + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 16 + + + 848 011c 0C .uleb128 0xc + 849 011d 01 .uleb128 0x1 + 850 011e 13 .uleb128 0x13 + 851 011f 00 .byte 0 + 852 0120 00 .byte 0 + 853 0121 15 .uleb128 0x15 + 854 0122 2E .uleb128 0x2e + 855 0123 01 .byte 0x1 + 856 0124 3F .uleb128 0x3f + 857 0125 0C .uleb128 0xc + 858 0126 03 .uleb128 0x3 + 859 0127 0E .uleb128 0xe + 860 0128 3A .uleb128 0x3a + 861 0129 0B .uleb128 0xb + 862 012a 3B .uleb128 0x3b + 863 012b 0B .uleb128 0xb + 864 012c 27 .uleb128 0x27 + 865 012d 0C .uleb128 0xc + 866 012e 49 .uleb128 0x49 + 867 012f 13 .uleb128 0x13 + 868 0130 11 .uleb128 0x11 + 869 0131 01 .uleb128 0x1 + 870 0132 12 .uleb128 0x12 + 871 0133 01 .uleb128 0x1 + 872 0134 40 .uleb128 0x40 + 873 0135 0A .uleb128 0xa + 874 0136 9742 .uleb128 0x2117 + 875 0138 0C .uleb128 0xc + 876 0139 01 .uleb128 0x1 + 877 013a 13 .uleb128 0x13 + 878 013b 00 .byte 0 + 879 013c 00 .byte 0 + 880 013d 16 .uleb128 0x16 + 881 013e 34 .uleb128 0x34 + 882 013f 00 .byte 0 + 883 0140 03 .uleb128 0x3 + 884 0141 0E .uleb128 0xe + 885 0142 3A .uleb128 0x3a + 886 0143 0B .uleb128 0xb + 887 0144 3B .uleb128 0x3b + 888 0145 0B .uleb128 0xb + 889 0146 49 .uleb128 0x49 + 890 0147 13 .uleb128 0x13 + 891 0148 02 .uleb128 0x2 + 892 0149 0A .uleb128 0xa + 893 014a 00 .byte 0 + 894 014b 00 .byte 0 + 895 014c 17 .uleb128 0x17 + 896 014d 34 .uleb128 0x34 + 897 014e 00 .byte 0 + 898 014f 03 .uleb128 0x3 + 899 0150 0E .uleb128 0xe + 900 0151 3A .uleb128 0x3a + 901 0152 0B .uleb128 0xb + 902 0153 3B .uleb128 0x3b + 903 0154 0B .uleb128 0xb + 904 0155 49 .uleb128 0x49 + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 17 + + + 905 0156 13 .uleb128 0x13 + 906 0157 3F .uleb128 0x3f + 907 0158 0C .uleb128 0xc + 908 0159 02 .uleb128 0x2 + 909 015a 0A .uleb128 0xa + 910 015b 00 .byte 0 + 911 015c 00 .byte 0 + 912 015d 00 .byte 0 + 913 .section .debug_loc,"",%progbits + 914 .Ldebug_loc0: + 915 .LLST0: + 916 0000 00000000 .4byte .LFB8 + 917 0004 02000000 .4byte .LCFI0 + 918 0008 0200 .2byte 0x2 + 919 000a 7D .byte 0x7d + 920 000b 00 .sleb128 0 + 921 000c 02000000 .4byte .LCFI0 + 922 0010 3C000000 .4byte .LFE8 + 923 0014 0200 .2byte 0x2 + 924 0016 7D .byte 0x7d + 925 0017 0C .sleb128 12 + 926 0018 00000000 .4byte 0 + 927 001c 00000000 .4byte 0 + 928 .LLST1: + 929 0020 00000000 .4byte .LVL0 + 930 0024 14000000 .4byte .LVL3 + 931 0028 0100 .2byte 0x1 + 932 002a 51 .byte 0x51 + 933 002b 14000000 .4byte .LVL3 + 934 002f 32000000 .4byte .LVL5 + 935 0033 0100 .2byte 0x1 + 936 0035 51 .byte 0x51 + 937 0036 32000000 .4byte .LVL5 + 938 003a 3C000000 .4byte .LFE8 + 939 003e 0500 .2byte 0x5 + 940 0040 74 .byte 0x74 + 941 0041 04 .sleb128 4 + 942 0042 06 .byte 0x6 + 943 0043 23 .byte 0x23 + 944 0044 08 .uleb128 0x8 + 945 0045 00000000 .4byte 0 + 946 0049 00000000 .4byte 0 + 947 .LLST2: + 948 004d 00000000 .4byte .LVL0 + 949 0051 1C000000 .4byte .LVL4 + 950 0055 0100 .2byte 0x1 + 951 0057 53 .byte 0x53 + 952 0058 1C000000 .4byte .LVL4 + 953 005c 3C000000 .4byte .LFE8 + 954 0060 0200 .2byte 0x2 + 955 0062 70 .byte 0x70 + 956 0063 10 .sleb128 16 + 957 0064 00000000 .4byte 0 + 958 0068 00000000 .4byte 0 + 959 .LLST3: + 960 006c 08000000 .4byte .LVL1 + 961 0070 12000000 .4byte .LVL2 + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 18 + + + 962 0074 0100 .2byte 0x1 + 963 0076 54 .byte 0x54 + 964 0077 14000000 .4byte .LVL3 + 965 007b 3C000000 .4byte .LFE8 + 966 007f 0100 .2byte 0x1 + 967 0081 54 .byte 0x54 + 968 0082 00000000 .4byte 0 + 969 0086 00000000 .4byte 0 + 970 .LLST4: + 971 008a 00000000 .4byte .LVL7 + 972 008e 1C000000 .4byte .LVL9 + 973 0092 0100 .2byte 0x1 + 974 0094 50 .byte 0x50 + 975 0095 1C000000 .4byte .LVL9 + 976 0099 1E000000 .4byte .LVL10 + 977 009d 0400 .2byte 0x4 + 978 009f F3 .byte 0xf3 + 979 00a0 01 .uleb128 0x1 + 980 00a1 50 .byte 0x50 + 981 00a2 9F .byte 0x9f + 982 00a3 1E000000 .4byte .LVL10 + 983 00a7 24000000 .4byte .LVL11 + 984 00ab 0100 .2byte 0x1 + 985 00ad 50 .byte 0x50 + 986 00ae 24000000 .4byte .LVL11 + 987 00b2 34000000 .4byte .LFE10 + 988 00b6 0100 .2byte 0x1 + 989 00b8 53 .byte 0x53 + 990 00b9 00000000 .4byte 0 + 991 00bd 00000000 .4byte 0 + 992 .section .debug_aranges,"",%progbits + 993 0000 34000000 .4byte 0x34 + 994 0004 0200 .2byte 0x2 + 995 0006 00000000 .4byte .Ldebug_info0 + 996 000a 04 .byte 0x4 + 997 000b 00 .byte 0 + 998 000c 0000 .2byte 0 + 999 000e 0000 .2byte 0 + 1000 0010 00000000 .4byte .LFB7 + 1001 0014 18000000 .4byte .LFE7-.LFB7 + 1002 0018 00000000 .4byte .LFB8 + 1003 001c 3C000000 .4byte .LFE8-.LFB8 + 1004 0020 00000000 .4byte .LFB9 + 1005 0024 24000000 .4byte .LFE9-.LFB9 + 1006 0028 00000000 .4byte .LFB10 + 1007 002c 34000000 .4byte .LFE10-.LFB10 + 1008 0030 00000000 .4byte 0 + 1009 0034 00000000 .4byte 0 + 1010 .section .debug_ranges,"",%progbits + 1011 .Ldebug_ranges0: + 1012 0000 00000000 .4byte .LFB7 + 1013 0004 18000000 .4byte .LFE7 + 1014 0008 00000000 .4byte .LFB8 + 1015 000c 3C000000 .4byte .LFE8 + 1016 0010 00000000 .4byte .LFB9 + 1017 0014 24000000 .4byte .LFE9 + 1018 0018 00000000 .4byte .LFB10 + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 19 + + + 1019 001c 34000000 .4byte .LFE10 + 1020 0020 00000000 .4byte 0 + 1021 0024 00000000 .4byte 0 + 1022 .section .debug_line,"",%progbits + 1023 .Ldebug_line0: + 1024 0000 3A010000 .section .debug_str,"MS",%progbits,1 + 1024 0200BC00 + 1024 00000201 + 1024 FB0E0D00 + 1024 01010101 + 1025 .LASF31: + 1026 0000 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 1026 73657273 + 1026 5C496D61 + 1026 6E6F6C5C + 1026 64657665 + 1027 002d 6C696361 .ascii "lications\\smartcities\000" + 1027 74696F6E + 1027 735C736D + 1027 61727463 + 1027 69746965 + 1028 .LASF26: + 1029 0043 63685654 .ascii "chVTSetI\000" + 1029 53657449 + 1029 00 + 1030 .LASF12: + 1031 004c 73797374 .ascii "systime_t\000" + 1031 696D655F + 1031 7400 + 1032 .LASF28: + 1033 0056 73746172 .ascii "start\000" + 1033 7400 + 1034 .LASF11: + 1035 005c 626F6F6C .ascii "bool_t\000" + 1035 5F7400 + 1036 .LASF14: + 1037 0063 76746675 .ascii "vtfunc_t\000" + 1037 6E635F74 + 1037 00 + 1038 .LASF8: + 1039 006c 6C6F6E67 .ascii "long unsigned int\000" + 1039 20756E73 + 1039 69676E65 + 1039 6420696E + 1039 7400 + 1040 .LASF30: + 1041 007e 2E2E2F2E .ascii "../..//os/kernel/src/chvt.c\000" + 1041 2E2F2F6F + 1041 732F6B65 + 1041 726E656C + 1041 2F737263 + 1042 .LASF4: + 1043 009a 73686F72 .ascii "short unsigned int\000" + 1043 7420756E + 1043 7369676E + 1043 65642069 + 1043 6E7400 + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 20 + + + 1044 .LASF15: + 1045 00ad 56697274 .ascii "VirtualTimer\000" + 1045 75616C54 + 1045 696D6572 + 1045 00 + 1046 .LASF2: + 1047 00ba 756E7369 .ascii "unsigned char\000" + 1047 676E6564 + 1047 20636861 + 1047 7200 + 1048 .LASF32: + 1049 00c8 5F76745F .ascii "_vt_init\000" + 1049 696E6974 + 1049 00 + 1050 .LASF0: + 1051 00d1 756E7369 .ascii "unsigned int\000" + 1051 676E6564 + 1051 20696E74 + 1051 00 + 1052 .LASF10: + 1053 00de 6C6F6E67 .ascii "long long unsigned int\000" + 1053 206C6F6E + 1053 6720756E + 1053 7369676E + 1053 65642069 + 1054 .LASF34: + 1055 00f5 76746C69 .ascii "vtlist\000" + 1055 737400 + 1056 .LASF24: + 1057 00fc 74696D65 .ascii "time\000" + 1057 00 + 1058 .LASF18: + 1059 0101 76745F74 .ascii "vt_time\000" + 1059 696D6500 + 1060 .LASF6: + 1061 0109 696E7433 .ascii "int32_t\000" + 1061 325F7400 + 1062 .LASF13: + 1063 0111 73697A65 .ascii "sizetype\000" + 1063 74797065 + 1063 00 + 1064 .LASF21: + 1065 011a 76745F73 .ascii "vt_systime\000" + 1065 79737469 + 1065 6D6500 + 1066 .LASF9: + 1067 0125 6C6F6E67 .ascii "long long int\000" + 1067 206C6F6E + 1067 6720696E + 1067 7400 + 1068 .LASF19: + 1069 0133 76745F66 .ascii "vt_func\000" + 1069 756E6300 + 1070 .LASF25: + 1071 013b 76746675 .ascii "vtfunc\000" + 1071 6E6300 + 1072 .LASF23: + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 21 + + + 1073 0142 63686172 .ascii "char\000" + 1073 00 + 1074 .LASF29: + 1075 0147 474E5520 .ascii "GNU C 4.7.2\000" + 1075 4320342E + 1075 372E3200 + 1076 .LASF20: + 1077 0153 76745F70 .ascii "vt_par\000" + 1077 617200 + 1078 .LASF3: + 1079 015a 73686F72 .ascii "short int\000" + 1079 7420696E + 1079 7400 + 1080 .LASF33: + 1081 0164 63685469 .ascii "chTimeIsWithin\000" + 1081 6D654973 + 1081 57697468 + 1081 696E00 + 1082 .LASF17: + 1083 0173 76745F70 .ascii "vt_prev\000" + 1083 72657600 + 1084 .LASF7: + 1085 017b 75696E74 .ascii "uint32_t\000" + 1085 33325F74 + 1085 00 + 1086 .LASF5: + 1087 0184 6C6F6E67 .ascii "long int\000" + 1087 20696E74 + 1087 00 + 1088 .LASF1: + 1089 018d 7369676E .ascii "signed char\000" + 1089 65642063 + 1089 68617200 + 1090 .LASF22: + 1091 0199 56544C69 .ascii "VTList\000" + 1091 737400 + 1092 .LASF16: + 1093 01a0 76745F6E .ascii "vt_next\000" + 1093 65787400 + 1094 .LASF27: + 1095 01a8 63685654 .ascii "chVTResetI\000" + 1095 52657365 + 1095 744900 + 1096 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\cc4H8fyg.s page 22 + + +DEFINED SYMBOLS + *ABS*:00000000 chvt.c +C:\cygwin\tmp\cc4H8fyg.s:19 .text._vt_init:00000000 $t +C:\cygwin\tmp\cc4H8fyg.s:25 .text._vt_init:00000000 _vt_init +C:\cygwin\tmp\cc4H8fyg.s:234 .bss.vtlist:00000000 .LANCHOR0 +C:\cygwin\tmp\cc4H8fyg.s:51 .text.chVTSetI:00000000 $t +C:\cygwin\tmp\cc4H8fyg.s:57 .text.chVTSetI:00000000 chVTSetI +C:\cygwin\tmp\cc4H8fyg.s:124 .text.chVTSetI:00000038 $d +C:\cygwin\tmp\cc4H8fyg.s:129 .text.chVTResetI:00000000 $t +C:\cygwin\tmp\cc4H8fyg.s:135 .text.chVTResetI:00000000 chVTResetI +C:\cygwin\tmp\cc4H8fyg.s:169 .text.chVTResetI:00000020 $d +C:\cygwin\tmp\cc4H8fyg.s:174 .text.chTimeIsWithin:00000000 $t +C:\cygwin\tmp\cc4H8fyg.s:180 .text.chTimeIsWithin:00000000 chTimeIsWithin +C:\cygwin\tmp\cc4H8fyg.s:227 .text.chTimeIsWithin:00000030 $d +C:\cygwin\tmp\cc4H8fyg.s:237 .bss.vtlist:00000000 vtlist +C:\cygwin\tmp\cc4H8fyg.s:233 .bss.vtlist:00000000 $d + .debug_frame:00000010 $d +C:\cygwin\tmp\cc4H8fyg.s:128 .text.chVTSetI:0000003c $t +C:\cygwin\tmp\cc4H8fyg.s:173 .text.chVTResetI:00000024 $t +C:\cygwin\tmp\cc4H8fyg.s:232 .text.chTimeIsWithin:00000034 $t + +NO UNDEFINED SYMBOLS diff --git a/Project/applications/smartcities/build/lst/crt0.lst b/Project/applications/smartcities/build/lst/crt0.lst new file mode 100644 index 0000000..9029d6e --- /dev/null +++ b/Project/applications/smartcities/build/lst/crt0.lst @@ -0,0 +1,1236 @@ +ARM GAS C:\cygwin\tmp\ccCGKYye.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "crt0.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text.__early_init,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .weak __early_init + 22 .thumb + 23 .thumb_func + 24 .type __early_init, %function + 25 __early_init: + 26 .LFB7: + 27 .file 1 "../..//os/ports/GCC/ARMCMx/crt0.c" + 28 .loc 1 220 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 0000 7047 bx lr + 34 .cfi_endproc + 35 .LFE7: + 36 .size __early_init, .-__early_init + 37 0002 00BFAFF3 .section .text.__late_init,"ax",%progbits + 37 0080AFF3 + 37 0080AFF3 + 37 0080 + 38 .align 2 + 39 .p2align 4,,15 + 40 .weak __late_init + 41 .thumb + 42 .thumb_func + 43 .type __late_init, %function + 44 __late_init: + 45 .LFB8: + 46 .loc 1 232 0 + 47 .cfi_startproc + 48 @ args = 0, pretend = 0, frame = 0 + 49 @ frame_needed = 0, uses_anonymous_args = 0 + 50 @ link register save eliminated. + 51 0000 7047 bx lr + 52 .cfi_endproc + 53 .LFE8: + 54 .size __late_init, .-__late_init + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 2 + + + 55 0002 00BFAFF3 .section .text._default_exit,"ax",%progbits + 55 0080AFF3 + 55 0080AFF3 + 55 0080 + 56 .align 2 + 57 .p2align 4,,15 + 58 .weak _default_exit + 59 .thumb + 60 .thumb_func + 61 .type _default_exit, %function + 62 _default_exit: + 63 .LFB9: + 64 .loc 1 243 0 + 65 .cfi_startproc + 66 @ Naked Function: prologue and epilogue provided by programmer. + 67 @ args = 0, pretend = 0, frame = 0 + 68 @ frame_needed = 0, uses_anonymous_args = 0 + 69 .L4: + 70 0000 FEE7 b .L4 + 71 .cfi_endproc + 72 .LFE9: + 73 .size _default_exit, .-_default_exit + 74 0002 00BFAFF3 .section .text.ResetHandler,"ax",%progbits + 74 0080AFF3 + 74 0080AFF3 + 74 0080 + 75 .align 2 + 76 .p2align 4,,15 + 77 .global ResetHandler + 78 .thumb + 79 .thumb_func + 80 .type ResetHandler, %function + 81 ResetHandler: + 82 .LFB10: + 83 .loc 1 254 0 + 84 .cfi_startproc + 85 @ Naked Function: prologue and epilogue provided by programmer. + 86 @ args = 0, pretend = 0, frame = 0 + 87 @ frame_needed = 0, uses_anonymous_args = 0 + 88 .loc 1 260 0 + 89 @ 260 "../..//os/ports/GCC/ARMCMx/crt0.c" 1 + 90 0000 72B6 cpsid i + 91 @ 0 "" 2 + 92 .loc 1 261 0 + 93 .thumb + 94 0002 3748 ldr r0, .L32 + 95 .LVL0: + 96 .loc 1 262 0 + 97 @ 262 "../..//os/ports/GCC/ARMCMx/crt0.c" 1 + 98 0004 80F30988 msr PSP, r0 + 99 @ 0 "" 2 + 100 .LVL1: + 101 .loc 1 282 0 + 102 .thumb + 103 0008 0223 movs r3, #2 + 104 @ 282 "../..//os/ports/GCC/ARMCMx/crt0.c" 1 + 105 000a 83F31488 msr CONTROL, r3 + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 3 + + + 106 @ 0 "" 2 + 107 .loc 1 283 0 + 108 @ 283 "../..//os/ports/GCC/ARMCMx/crt0.c" 1 + 109 000e BFF36F8F isb + 110 @ 0 "" 2 + 111 .LVL2: + 112 .thumb + 113 .LBB2: + 114 .loc 1 287 0 + 115 0012 344A ldr r2, .L32+4 + 116 0014 344B ldr r3, .L32+8 + 117 0016 9A42 cmp r2, r3 + 118 0018 0BD2 bcs .L10 + 119 .LBE2: + 120 .LBB3: + 121 .loc 1 254 0 + 122 001a D143 mvns r1, r2 + 123 001c C918 adds r1, r1, r3 + 124 001e 21F00301 bic r1, r1, #3 + 125 0022 131F subs r3, r2, #4 + 126 0024 8918 adds r1, r1, r2 + 127 .LBE3: + 128 .LBB4: + 129 .loc 1 287 0 + 130 0026 4FF05532 mov r2, #1431655765 + 131 .LVL3: + 132 .L9: + 133 .loc 1 287 0 is_stmt 0 discriminator 2 + 134 002a 43F8042F str r2, [r3, #4]! + 135 002e 8B42 cmp r3, r1 + 136 0030 FBD1 bne .L9 + 137 .L10: + 138 .LVL4: + 139 .LBE4: + 140 .LBB5: + 141 .loc 1 290 0 is_stmt 1 + 142 0032 2E4A ldr r2, .L32+12 + 143 0034 8242 cmp r2, r0 + 144 0036 0CD2 bcs .L8 + 145 .LBE5: + 146 .LBB6: + 147 .loc 1 254 0 + 148 0038 2D49 ldr r1, .L32+16 + 149 003a 131D adds r3, r2, #4 + 150 003c C91A subs r1, r1, r3 + 151 003e 21F00301 bic r1, r1, #3 + 152 0042 131F subs r3, r2, #4 + 153 0044 8918 adds r1, r1, r2 + 154 .LBE6: + 155 .LBB7: + 156 .loc 1 290 0 + 157 0046 4FF05532 mov r2, #1431655765 + 158 .LVL5: + 159 .L13: + 160 .loc 1 290 0 is_stmt 0 discriminator 2 + 161 004a 43F8042F str r2, [r3, #4]! + 162 004e 8B42 cmp r3, r1 + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 4 + + + 163 0050 FBD1 bne .L13 + 164 .L8: + 165 .LBE7: + 166 .loc 1 296 0 is_stmt 1 + 167 0052 FFF7FEFF bl __early_init + 168 .LVL6: + 169 .LBB8: + 170 .loc 1 305 0 + 171 0056 2749 ldr r1, .L32+20 + 172 0058 274B ldr r3, .L32+24 + 173 005a 9942 cmp r1, r3 + 174 005c 0BD2 bcs .L12 + 175 .LBE8: + 176 .LBB9: + 177 .loc 1 254 0 + 178 005e C843 mvns r0, r1 + 179 0060 C018 adds r0, r0, r3 + 180 0062 20F00300 bic r0, r0, #3 + 181 0066 254C ldr r4, .L32+28 + 182 0068 0430 adds r0, r0, #4 + 183 .LBE9: + 184 006a 0023 movs r3, #0 + 185 .LVL7: + 186 .L16: + 187 .LBB10: + 188 .loc 1 306 0 + 189 006c 1A59 ldr r2, [r3, r4] + 190 006e 5A50 str r2, [r3, r1] + 191 0070 0433 adds r3, r3, #4 + 192 .loc 1 305 0 + 193 0072 8342 cmp r3, r0 + 194 0074 FAD1 bne .L16 + 195 .L12: + 196 .LVL8: + 197 .LBE10: + 198 .LBB11: + 199 .loc 1 312 0 + 200 0076 224A ldr r2, .L32+32 + 201 0078 224B ldr r3, .L32+36 + 202 007a 9A42 cmp r2, r3 + 203 007c 0AD2 bcs .L15 + 204 .LBE11: + 205 .LBB12: + 206 .loc 1 254 0 + 207 007e D143 mvns r1, r2 + 208 0080 C918 adds r1, r1, r3 + 209 0082 21F00301 bic r1, r1, #3 + 210 0086 131F subs r3, r2, #4 + 211 0088 8918 adds r1, r1, r2 + 212 .LBE12: + 213 .LBB13: + 214 .loc 1 312 0 + 215 008a 0022 movs r2, #0 + 216 .LVL9: + 217 .L19: + 218 .loc 1 312 0 is_stmt 0 discriminator 2 + 219 008c 43F8042F str r2, [r3, #4]! + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 5 + + + 220 0090 8B42 cmp r3, r1 + 221 0092 FBD1 bne .L19 + 222 .L15: + 223 .LBE13: + 224 .loc 1 316 0 is_stmt 1 + 225 0094 FFF7FEFF bl __late_init + 226 .LVL10: + 227 .LBB14: + 228 .loc 1 322 0 + 229 0098 1B4D ldr r5, .L32+40 + 230 009a 1C4B ldr r3, .L32+44 + 231 009c 9D42 cmp r5, r3 + 232 009e 0BD2 bcs .L18 + 233 .LBE14: + 234 .LBB15: + 235 .loc 1 254 0 + 236 00a0 EE43 mvns r6, r5 + 237 00a2 F618 adds r6, r6, r3 + 238 00a4 B608 lsrs r6, r6, #2 + 239 00a6 043D subs r5, r5, #4 + 240 00a8 0136 adds r6, r6, #1 + 241 .LBE15: + 242 00aa 0024 movs r4, #0 + 243 .LVL11: + 244 .L22: + 245 .LBB16: + 246 .loc 1 323 0 + 247 00ac 55F8043F ldr r3, [r5, #4]! + 248 00b0 0134 adds r4, r4, #1 + 249 00b2 9847 blx r3 + 250 .LVL12: + 251 .loc 1 322 0 + 252 00b4 B442 cmp r4, r6 + 253 00b6 F9D1 bne .L22 + 254 .L18: + 255 .LBE16: + 256 .loc 1 330 0 + 257 00b8 FFF7FEFF bl main + 258 .LVL13: + 259 .LBB17: + 260 .loc 1 336 0 + 261 00bc 144D ldr r5, .L32+48 + 262 00be 154B ldr r3, .L32+52 + 263 00c0 9D42 cmp r5, r3 + 264 00c2 0BD2 bcs .L21 + 265 .LBE17: + 266 .loc 1 254 0 + 267 00c4 EE43 mvns r6, r5 + 268 00c6 F618 adds r6, r6, r3 + 269 00c8 B608 lsrs r6, r6, #2 + 270 00ca 043D subs r5, r5, #4 + 271 00cc 0136 adds r6, r6, #1 + 272 00ce 0024 movs r4, #0 + 273 .LVL14: + 274 .L23: + 275 .LBB18: + 276 .loc 1 337 0 + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 6 + + + 277 00d0 55F8043F ldr r3, [r5, #4]! + 278 00d4 0134 adds r4, r4, #1 + 279 00d6 9847 blx r3 + 280 .LVL15: + 281 .loc 1 336 0 + 282 00d8 B442 cmp r4, r6 + 283 00da F9D1 bne .L23 + 284 .L21: + 285 .LBE18: + 286 .loc 1 344 0 + 287 00dc FFF7FEFF bl _default_exit + 288 .LVL16: + 289 .loc 1 345 0 + 290 .L33: + 291 .align 2 + 292 .L32: + 293 00e0 00000000 .word __process_stack_end__ + 294 00e4 00000000 .word __main_stack_base__ + 295 00e8 00000000 .word __main_stack_end__ + 296 00ec 00000000 .word __process_stack_base__ + 297 00f0 03000000 .word __process_stack_end__+3 + 298 00f4 00000000 .word _data + 299 00f8 00000000 .word _edata + 300 00fc 00000000 .word _textdata + 301 0100 00000000 .word _bss_start + 302 0104 00000000 .word _bss_end + 303 0108 00000000 .word __init_array_start + 304 010c 00000000 .word __init_array_end + 305 0110 00000000 .word __fini_array_start + 306 0114 00000000 .word __fini_array_end + 307 .cfi_endproc + 308 .LFE10: + 309 .size ResetHandler, .-ResetHandler + 310 0118 AFF30080 .text + 310 AFF30080 + 311 .Letext0: + 312 .file 2 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 313 .section .debug_info,"",%progbits + 314 .Ldebug_info0: + 315 0000 AF020000 .4byte 0x2af + 316 0004 0200 .2byte 0x2 + 317 0006 00000000 .4byte .Ldebug_abbrev0 + 318 000a 04 .byte 0x4 + 319 000b 01 .uleb128 0x1 + 320 000c 93010000 .4byte .LASF31 + 321 0010 01 .byte 0x1 + 322 0011 AE000000 .4byte .LASF32 + 323 0015 51000000 .4byte .LASF33 + 324 0019 B8000000 .4byte .Ldebug_ranges0+0xb8 + 325 001d 00000000 .4byte 0 + 326 0021 00000000 .4byte 0 + 327 0025 00000000 .4byte .Ldebug_line0 + 328 0029 02 .uleb128 0x2 + 329 002a 04 .byte 0x4 + 330 002b 05 .byte 0x5 + 331 002c 696E7400 .ascii "int\000" + 332 0030 03 .uleb128 0x3 + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 7 + + + 333 0031 04 .byte 0x4 + 334 0032 07 .byte 0x7 + 335 0033 2B010000 .4byte .LASF0 + 336 0037 03 .uleb128 0x3 + 337 0038 01 .byte 0x1 + 338 0039 06 .byte 0x6 + 339 003a DD010000 .4byte .LASF1 + 340 003e 04 .uleb128 0x4 + 341 003f 78010000 .4byte .LASF6 + 342 0043 02 .byte 0x2 + 343 0044 2A .byte 0x2a + 344 0045 49000000 .4byte 0x49 + 345 0049 03 .uleb128 0x3 + 346 004a 01 .byte 0x1 + 347 004b 08 .byte 0x8 + 348 004c 94000000 .4byte .LASF2 + 349 0050 03 .uleb128 0x3 + 350 0051 02 .byte 0x2 + 351 0052 05 .byte 0x5 + 352 0053 B3010000 .4byte .LASF3 + 353 0057 03 .uleb128 0x3 + 354 0058 02 .byte 0x2 + 355 0059 07 .byte 0x7 + 356 005a EF000000 .4byte .LASF4 + 357 005e 03 .uleb128 0x3 + 358 005f 04 .byte 0x4 + 359 0060 05 .byte 0x5 + 360 0061 CE010000 .4byte .LASF5 + 361 0065 04 .uleb128 0x4 + 362 0066 C5010000 .4byte .LASF7 + 363 006a 02 .byte 0x2 + 364 006b 50 .byte 0x50 + 365 006c 70000000 .4byte 0x70 + 366 0070 03 .uleb128 0x3 + 367 0071 04 .byte 0x4 + 368 0072 07 .byte 0x7 + 369 0073 D0000000 .4byte .LASF8 + 370 0077 03 .uleb128 0x3 + 371 0078 08 .byte 0x8 + 372 0079 05 .byte 0x5 + 373 007a 80010000 .4byte .LASF9 + 374 007e 03 .uleb128 0x3 + 375 007f 08 .byte 0x8 + 376 0080 07 .byte 0x7 + 377 0081 38010000 .4byte .LASF10 + 378 0085 03 .uleb128 0x3 + 379 0086 04 .byte 0x4 + 380 0087 07 .byte 0x7 + 381 0088 6F010000 .4byte .LASF11 + 382 008c 03 .uleb128 0x3 + 383 008d 01 .byte 0x1 + 384 008e 08 .byte 0x8 + 385 008f 8E010000 .4byte .LASF12 + 386 0093 04 .uleb128 0x4 + 387 0094 BD010000 .4byte .LASF13 + 388 0098 01 .byte 0x1 + 389 0099 26 .byte 0x26 + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 8 + + + 390 009a 9E000000 .4byte 0x9e + 391 009e 05 .uleb128 0x5 + 392 009f 04 .byte 0x4 + 393 00a0 A4000000 .4byte 0xa4 + 394 00a4 06 .uleb128 0x6 + 395 00a5 01 .byte 0x1 + 396 00a6 04 .uleb128 0x4 + 397 00a7 3A000000 .4byte .LASF14 + 398 00ab 01 .byte 0x1 + 399 00ac 27 .byte 0x27 + 400 00ad B1000000 .4byte 0xb1 + 401 00b1 05 .uleb128 0x5 + 402 00b2 04 .byte 0x4 + 403 00b3 93000000 .4byte 0x93 + 404 00b7 07 .uleb128 0x7 + 405 00b8 01 .byte 0x1 + 406 00b9 62010000 .4byte .LASF15 + 407 00bd 01 .byte 0x1 + 408 00be DC .byte 0xdc + 409 00bf 01 .byte 0x1 + 410 00c0 00000000 .4byte .LFB7 + 411 00c4 02000000 .4byte .LFE7 + 412 00c8 02 .byte 0x2 + 413 00c9 7D .byte 0x7d + 414 00ca 00 .sleb128 0 + 415 00cb 01 .byte 0x1 + 416 00cc 07 .uleb128 0x7 + 417 00cd 01 .byte 0x1 + 418 00ce A2000000 .4byte .LASF16 + 419 00d2 01 .byte 0x1 + 420 00d3 E8 .byte 0xe8 + 421 00d4 01 .byte 0x1 + 422 00d5 00000000 .4byte .LFB8 + 423 00d9 02000000 .4byte .LFE8 + 424 00dd 02 .byte 0x2 + 425 00de 7D .byte 0x7d + 426 00df 00 .sleb128 0 + 427 00e0 01 .byte 0x1 + 428 00e1 07 .uleb128 0x7 + 429 00e2 01 .byte 0x1 + 430 00e3 43000000 .4byte .LASF17 + 431 00e7 01 .byte 0x1 + 432 00e8 F3 .byte 0xf3 + 433 00e9 01 .byte 0x1 + 434 00ea 00000000 .4byte .LFB9 + 435 00ee 02000000 .4byte .LFE9 + 436 00f2 02 .byte 0x2 + 437 00f3 7D .byte 0x7d + 438 00f4 00 .sleb128 0 + 439 00f5 01 .byte 0x1 + 440 00f6 08 .uleb128 0x8 + 441 00f7 01 .byte 0x1 + 442 00f8 E2000000 .4byte .LASF34 + 443 00fc 01 .byte 0x1 + 444 00fd FE .byte 0xfe + 445 00fe 01 .byte 0x1 + 446 00ff 00000000 .4byte .LFB10 + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 9 + + + 447 0103 18010000 .4byte .LFE10 + 448 0107 02 .byte 0x2 + 449 0108 7D .byte 0x7d + 450 0109 00 .sleb128 0 + 451 010a 01 .byte 0x1 + 452 010b F9010000 .4byte 0x1f9 + 453 010f 09 .uleb128 0x9 + 454 0110 70737000 .ascii "psp\000" + 455 0114 01 .byte 0x1 + 456 0115 FF .byte 0xff + 457 0116 65000000 .4byte 0x65 + 458 011a 01 .byte 0x1 + 459 011b 50 .byte 0x50 + 460 011c 0A .uleb128 0xa + 461 011d 72656700 .ascii "reg\000" + 462 0121 01 .byte 0x1 + 463 0122 FF .byte 0xff + 464 0123 65000000 .4byte 0x65 + 465 0127 02 .byte 0x2 + 466 0128 0B .uleb128 0xb + 467 0129 00000000 .4byte .Ldebug_ranges0+0 + 468 012d 48010000 .4byte 0x148 + 469 0131 0C .uleb128 0xc + 470 0132 703100 .ascii "p1\000" + 471 0135 01 .byte 0x1 + 472 0136 1F01 .2byte 0x11f + 473 0138 F9010000 .4byte 0x1f9 + 474 013c 0C .uleb128 0xc + 475 013d 703200 .ascii "p2\000" + 476 0140 01 .byte 0x1 + 477 0141 1F01 .2byte 0x11f + 478 0143 F9010000 .4byte 0x1f9 + 479 0147 00 .byte 0 + 480 0148 0B .uleb128 0xb + 481 0149 18000000 .4byte .Ldebug_ranges0+0x18 + 482 014d 68010000 .4byte 0x168 + 483 0151 0C .uleb128 0xc + 484 0152 703100 .ascii "p1\000" + 485 0155 01 .byte 0x1 + 486 0156 2201 .2byte 0x122 + 487 0158 F9010000 .4byte 0x1f9 + 488 015c 0C .uleb128 0xc + 489 015d 703200 .ascii "p2\000" + 490 0160 01 .byte 0x1 + 491 0161 2201 .2byte 0x122 + 492 0163 F9010000 .4byte 0x1f9 + 493 0167 00 .byte 0 + 494 0168 0B .uleb128 0xb + 495 0169 38000000 .4byte .Ldebug_ranges0+0x38 + 496 016d 88010000 .4byte 0x188 + 497 0171 0C .uleb128 0xc + 498 0172 747000 .ascii "tp\000" + 499 0175 01 .byte 0x1 + 500 0176 2D01 .2byte 0x12d + 501 0178 F9010000 .4byte 0x1f9 + 502 017c 0C .uleb128 0xc + 503 017d 647000 .ascii "dp\000" + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 10 + + + 504 0180 01 .byte 0x1 + 505 0181 2D01 .2byte 0x12d + 506 0183 F9010000 .4byte 0x1f9 + 507 0187 00 .byte 0 + 508 0188 0B .uleb128 0xb + 509 0189 58000000 .4byte .Ldebug_ranges0+0x58 + 510 018d A8010000 .4byte 0x1a8 + 511 0191 0C .uleb128 0xc + 512 0192 703100 .ascii "p1\000" + 513 0195 01 .byte 0x1 + 514 0196 3801 .2byte 0x138 + 515 0198 F9010000 .4byte 0x1f9 + 516 019c 0C .uleb128 0xc + 517 019d 703200 .ascii "p2\000" + 518 01a0 01 .byte 0x1 + 519 01a1 3801 .2byte 0x138 + 520 01a3 F9010000 .4byte 0x1f9 + 521 01a7 00 .byte 0 + 522 01a8 0B .uleb128 0xb + 523 01a9 78000000 .4byte .Ldebug_ranges0+0x78 + 524 01ad BE010000 .4byte 0x1be + 525 01b1 0C .uleb128 0xc + 526 01b2 66707000 .ascii "fpp\000" + 527 01b6 01 .byte 0x1 + 528 01b7 4101 .2byte 0x141 + 529 01b9 A6000000 .4byte 0xa6 + 530 01bd 00 .byte 0 + 531 01be 0B .uleb128 0xb + 532 01bf 98000000 .4byte .Ldebug_ranges0+0x98 + 533 01c3 D4010000 .4byte 0x1d4 + 534 01c7 0C .uleb128 0xc + 535 01c8 66707000 .ascii "fpp\000" + 536 01cc 01 .byte 0x1 + 537 01cd 4F01 .2byte 0x14f + 538 01cf A6000000 .4byte 0xa6 + 539 01d3 00 .byte 0 + 540 01d4 0D .uleb128 0xd + 541 01d5 56000000 .4byte .LVL6 + 542 01d9 B7000000 .4byte 0xb7 + 543 01dd 0D .uleb128 0xd + 544 01de 98000000 .4byte .LVL10 + 545 01e2 CC000000 .4byte 0xcc + 546 01e6 0D .uleb128 0xd + 547 01e7 BC000000 .4byte .LVL13 + 548 01eb A8020000 .4byte 0x2a8 + 549 01ef 0D .uleb128 0xd + 550 01f0 E0000000 .4byte .LVL16 + 551 01f4 E1000000 .4byte 0xe1 + 552 01f8 00 .byte 0 + 553 01f9 05 .uleb128 0x5 + 554 01fa 04 .byte 0x4 + 555 01fb 65000000 .4byte 0x65 + 556 01ff 0E .uleb128 0xe + 557 0200 9F010000 .4byte .LASF18 + 558 0204 01 .byte 0x1 + 559 0205 7D .byte 0x7d + 560 0206 65000000 .4byte 0x65 + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 11 + + + 561 020a 01 .byte 0x1 + 562 020b 01 .byte 0x1 + 563 020c 0E .uleb128 0xe + 564 020d 12020000 .4byte .LASF19 + 565 0211 01 .byte 0x1 + 566 0212 85 .byte 0x85 + 567 0213 65000000 .4byte 0x65 + 568 0217 01 .byte 0x1 + 569 0218 01 .byte 0x1 + 570 0219 0E .uleb128 0xe + 571 021a 23000000 .4byte .LASF20 + 572 021e 01 .byte 0x1 + 573 021f 8C .byte 0x8c + 574 0220 65000000 .4byte 0x65 + 575 0224 01 .byte 0x1 + 576 0225 01 .byte 0x1 + 577 0226 0E .uleb128 0xe + 578 0227 E9010000 .4byte .LASF21 + 579 022b 01 .byte 0x1 + 580 022c 93 .byte 0x93 + 581 022d 65000000 .4byte 0x65 + 582 0231 01 .byte 0x1 + 583 0232 01 .byte 0x1 + 584 0233 0E .uleb128 0xe + 585 0234 58010000 .4byte .LASF22 + 586 0238 01 .byte 0x1 + 587 0239 99 .byte 0x99 + 588 023a 65000000 .4byte 0x65 + 589 023e 01 .byte 0x1 + 590 023f 01 .byte 0x1 + 591 0240 0E .uleb128 0xe + 592 0241 D7010000 .4byte .LASF23 + 593 0245 01 .byte 0x1 + 594 0246 9F .byte 0x9f + 595 0247 65000000 .4byte 0x65 + 596 024b 01 .byte 0x1 + 597 024c 01 .byte 0x1 + 598 024d 0E .uleb128 0xe + 599 024e 0B000000 .4byte .LASF24 + 600 0252 01 .byte 0x1 + 601 0253 A5 .byte 0xa5 + 602 0254 65000000 .4byte 0x65 + 603 0258 01 .byte 0x1 + 604 0259 01 .byte 0x1 + 605 025a 0E .uleb128 0xe + 606 025b 00000000 .4byte .LASF25 + 607 025f 01 .byte 0x1 + 608 0260 AB .byte 0xab + 609 0261 65000000 .4byte 0x65 + 610 0265 01 .byte 0x1 + 611 0266 01 .byte 0x1 + 612 0267 0E .uleb128 0xe + 613 0268 4F010000 .4byte .LASF26 + 614 026c 01 .byte 0x1 + 615 026d B1 .byte 0xb1 + 616 026e 65000000 .4byte 0x65 + 617 0272 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 12 + + + 618 0273 01 .byte 0x1 + 619 0274 0E .uleb128 0xe + 620 0275 FF010000 .4byte .LASF27 + 621 0279 01 .byte 0x1 + 622 027a B7 .byte 0xb7 + 623 027b 93000000 .4byte 0x93 + 624 027f 01 .byte 0x1 + 625 0280 01 .byte 0x1 + 626 0281 0E .uleb128 0xe + 627 0282 15010000 .4byte .LASF28 + 628 0286 01 .byte 0x1 + 629 0287 BD .byte 0xbd + 630 0288 93000000 .4byte 0x93 + 631 028c 01 .byte 0x1 + 632 028d 01 .byte 0x1 + 633 028e 0E .uleb128 0xe + 634 028f 02010000 .4byte .LASF29 + 635 0293 01 .byte 0x1 + 636 0294 C3 .byte 0xc3 + 637 0295 93000000 .4byte 0x93 + 638 0299 01 .byte 0x1 + 639 029a 01 .byte 0x1 + 640 029b 0E .uleb128 0xe + 641 029c 12000000 .4byte .LASF30 + 642 02a0 01 .byte 0x1 + 643 02a1 C9 .byte 0xc9 + 644 02a2 93000000 .4byte 0x93 + 645 02a6 01 .byte 0x1 + 646 02a7 01 .byte 0x1 + 647 02a8 0F .uleb128 0xf + 648 02a9 01 .byte 0x1 + 649 02aa 26010000 .4byte .LASF35 + 650 02ae 01 .byte 0x1 + 651 02af D0 .byte 0xd0 + 652 02b0 01 .byte 0x1 + 653 02b1 01 .byte 0x1 + 654 02b2 00 .byte 0 + 655 .section .debug_abbrev,"",%progbits + 656 .Ldebug_abbrev0: + 657 0000 01 .uleb128 0x1 + 658 0001 11 .uleb128 0x11 + 659 0002 01 .byte 0x1 + 660 0003 25 .uleb128 0x25 + 661 0004 0E .uleb128 0xe + 662 0005 13 .uleb128 0x13 + 663 0006 0B .uleb128 0xb + 664 0007 03 .uleb128 0x3 + 665 0008 0E .uleb128 0xe + 666 0009 1B .uleb128 0x1b + 667 000a 0E .uleb128 0xe + 668 000b 55 .uleb128 0x55 + 669 000c 06 .uleb128 0x6 + 670 000d 11 .uleb128 0x11 + 671 000e 01 .uleb128 0x1 + 672 000f 52 .uleb128 0x52 + 673 0010 01 .uleb128 0x1 + 674 0011 10 .uleb128 0x10 + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 13 + + + 675 0012 06 .uleb128 0x6 + 676 0013 00 .byte 0 + 677 0014 00 .byte 0 + 678 0015 02 .uleb128 0x2 + 679 0016 24 .uleb128 0x24 + 680 0017 00 .byte 0 + 681 0018 0B .uleb128 0xb + 682 0019 0B .uleb128 0xb + 683 001a 3E .uleb128 0x3e + 684 001b 0B .uleb128 0xb + 685 001c 03 .uleb128 0x3 + 686 001d 08 .uleb128 0x8 + 687 001e 00 .byte 0 + 688 001f 00 .byte 0 + 689 0020 03 .uleb128 0x3 + 690 0021 24 .uleb128 0x24 + 691 0022 00 .byte 0 + 692 0023 0B .uleb128 0xb + 693 0024 0B .uleb128 0xb + 694 0025 3E .uleb128 0x3e + 695 0026 0B .uleb128 0xb + 696 0027 03 .uleb128 0x3 + 697 0028 0E .uleb128 0xe + 698 0029 00 .byte 0 + 699 002a 00 .byte 0 + 700 002b 04 .uleb128 0x4 + 701 002c 16 .uleb128 0x16 + 702 002d 00 .byte 0 + 703 002e 03 .uleb128 0x3 + 704 002f 0E .uleb128 0xe + 705 0030 3A .uleb128 0x3a + 706 0031 0B .uleb128 0xb + 707 0032 3B .uleb128 0x3b + 708 0033 0B .uleb128 0xb + 709 0034 49 .uleb128 0x49 + 710 0035 13 .uleb128 0x13 + 711 0036 00 .byte 0 + 712 0037 00 .byte 0 + 713 0038 05 .uleb128 0x5 + 714 0039 0F .uleb128 0xf + 715 003a 00 .byte 0 + 716 003b 0B .uleb128 0xb + 717 003c 0B .uleb128 0xb + 718 003d 49 .uleb128 0x49 + 719 003e 13 .uleb128 0x13 + 720 003f 00 .byte 0 + 721 0040 00 .byte 0 + 722 0041 06 .uleb128 0x6 + 723 0042 15 .uleb128 0x15 + 724 0043 00 .byte 0 + 725 0044 27 .uleb128 0x27 + 726 0045 0C .uleb128 0xc + 727 0046 00 .byte 0 + 728 0047 00 .byte 0 + 729 0048 07 .uleb128 0x7 + 730 0049 2E .uleb128 0x2e + 731 004a 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 14 + + + 732 004b 3F .uleb128 0x3f + 733 004c 0C .uleb128 0xc + 734 004d 03 .uleb128 0x3 + 735 004e 0E .uleb128 0xe + 736 004f 3A .uleb128 0x3a + 737 0050 0B .uleb128 0xb + 738 0051 3B .uleb128 0x3b + 739 0052 0B .uleb128 0xb + 740 0053 27 .uleb128 0x27 + 741 0054 0C .uleb128 0xc + 742 0055 11 .uleb128 0x11 + 743 0056 01 .uleb128 0x1 + 744 0057 12 .uleb128 0x12 + 745 0058 01 .uleb128 0x1 + 746 0059 40 .uleb128 0x40 + 747 005a 0A .uleb128 0xa + 748 005b 9742 .uleb128 0x2117 + 749 005d 0C .uleb128 0xc + 750 005e 00 .byte 0 + 751 005f 00 .byte 0 + 752 0060 08 .uleb128 0x8 + 753 0061 2E .uleb128 0x2e + 754 0062 01 .byte 0x1 + 755 0063 3F .uleb128 0x3f + 756 0064 0C .uleb128 0xc + 757 0065 03 .uleb128 0x3 + 758 0066 0E .uleb128 0xe + 759 0067 3A .uleb128 0x3a + 760 0068 0B .uleb128 0xb + 761 0069 3B .uleb128 0x3b + 762 006a 0B .uleb128 0xb + 763 006b 27 .uleb128 0x27 + 764 006c 0C .uleb128 0xc + 765 006d 11 .uleb128 0x11 + 766 006e 01 .uleb128 0x1 + 767 006f 12 .uleb128 0x12 + 768 0070 01 .uleb128 0x1 + 769 0071 40 .uleb128 0x40 + 770 0072 0A .uleb128 0xa + 771 0073 9642 .uleb128 0x2116 + 772 0075 0C .uleb128 0xc + 773 0076 01 .uleb128 0x1 + 774 0077 13 .uleb128 0x13 + 775 0078 00 .byte 0 + 776 0079 00 .byte 0 + 777 007a 09 .uleb128 0x9 + 778 007b 34 .uleb128 0x34 + 779 007c 00 .byte 0 + 780 007d 03 .uleb128 0x3 + 781 007e 08 .uleb128 0x8 + 782 007f 3A .uleb128 0x3a + 783 0080 0B .uleb128 0xb + 784 0081 3B .uleb128 0x3b + 785 0082 0B .uleb128 0xb + 786 0083 49 .uleb128 0x49 + 787 0084 13 .uleb128 0x13 + 788 0085 02 .uleb128 0x2 + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 15 + + + 789 0086 0A .uleb128 0xa + 790 0087 00 .byte 0 + 791 0088 00 .byte 0 + 792 0089 0A .uleb128 0xa + 793 008a 34 .uleb128 0x34 + 794 008b 00 .byte 0 + 795 008c 03 .uleb128 0x3 + 796 008d 08 .uleb128 0x8 + 797 008e 3A .uleb128 0x3a + 798 008f 0B .uleb128 0xb + 799 0090 3B .uleb128 0x3b + 800 0091 0B .uleb128 0xb + 801 0092 49 .uleb128 0x49 + 802 0093 13 .uleb128 0x13 + 803 0094 1C .uleb128 0x1c + 804 0095 0B .uleb128 0xb + 805 0096 00 .byte 0 + 806 0097 00 .byte 0 + 807 0098 0B .uleb128 0xb + 808 0099 0B .uleb128 0xb + 809 009a 01 .byte 0x1 + 810 009b 55 .uleb128 0x55 + 811 009c 06 .uleb128 0x6 + 812 009d 01 .uleb128 0x1 + 813 009e 13 .uleb128 0x13 + 814 009f 00 .byte 0 + 815 00a0 00 .byte 0 + 816 00a1 0C .uleb128 0xc + 817 00a2 34 .uleb128 0x34 + 818 00a3 00 .byte 0 + 819 00a4 03 .uleb128 0x3 + 820 00a5 08 .uleb128 0x8 + 821 00a6 3A .uleb128 0x3a + 822 00a7 0B .uleb128 0xb + 823 00a8 3B .uleb128 0x3b + 824 00a9 05 .uleb128 0x5 + 825 00aa 49 .uleb128 0x49 + 826 00ab 13 .uleb128 0x13 + 827 00ac 00 .byte 0 + 828 00ad 00 .byte 0 + 829 00ae 0D .uleb128 0xd + 830 00af 898201 .uleb128 0x4109 + 831 00b2 00 .byte 0 + 832 00b3 11 .uleb128 0x11 + 833 00b4 01 .uleb128 0x1 + 834 00b5 31 .uleb128 0x31 + 835 00b6 13 .uleb128 0x13 + 836 00b7 00 .byte 0 + 837 00b8 00 .byte 0 + 838 00b9 0E .uleb128 0xe + 839 00ba 34 .uleb128 0x34 + 840 00bb 00 .byte 0 + 841 00bc 03 .uleb128 0x3 + 842 00bd 0E .uleb128 0xe + 843 00be 3A .uleb128 0x3a + 844 00bf 0B .uleb128 0xb + 845 00c0 3B .uleb128 0x3b + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 16 + + + 846 00c1 0B .uleb128 0xb + 847 00c2 49 .uleb128 0x49 + 848 00c3 13 .uleb128 0x13 + 849 00c4 3F .uleb128 0x3f + 850 00c5 0C .uleb128 0xc + 851 00c6 3C .uleb128 0x3c + 852 00c7 0C .uleb128 0xc + 853 00c8 00 .byte 0 + 854 00c9 00 .byte 0 + 855 00ca 0F .uleb128 0xf + 856 00cb 2E .uleb128 0x2e + 857 00cc 00 .byte 0 + 858 00cd 3F .uleb128 0x3f + 859 00ce 0C .uleb128 0xc + 860 00cf 03 .uleb128 0x3 + 861 00d0 0E .uleb128 0xe + 862 00d1 3A .uleb128 0x3a + 863 00d2 0B .uleb128 0xb + 864 00d3 3B .uleb128 0x3b + 865 00d4 0B .uleb128 0xb + 866 00d5 27 .uleb128 0x27 + 867 00d6 0C .uleb128 0xc + 868 00d7 3C .uleb128 0x3c + 869 00d8 0C .uleb128 0xc + 870 00d9 00 .byte 0 + 871 00da 00 .byte 0 + 872 00db 00 .byte 0 + 873 .section .debug_aranges,"",%progbits + 874 0000 34000000 .4byte 0x34 + 875 0004 0200 .2byte 0x2 + 876 0006 00000000 .4byte .Ldebug_info0 + 877 000a 04 .byte 0x4 + 878 000b 00 .byte 0 + 879 000c 0000 .2byte 0 + 880 000e 0000 .2byte 0 + 881 0010 00000000 .4byte .LFB7 + 882 0014 02000000 .4byte .LFE7-.LFB7 + 883 0018 00000000 .4byte .LFB8 + 884 001c 02000000 .4byte .LFE8-.LFB8 + 885 0020 00000000 .4byte .LFB9 + 886 0024 02000000 .4byte .LFE9-.LFB9 + 887 0028 00000000 .4byte .LFB10 + 888 002c 18010000 .4byte .LFE10-.LFB10 + 889 0030 00000000 .4byte 0 + 890 0034 00000000 .4byte 0 + 891 .section .debug_ranges,"",%progbits + 892 .Ldebug_ranges0: + 893 0000 12000000 .4byte .LBB2 + 894 0004 1A000000 .4byte .LBE2 + 895 0008 26000000 .4byte .LBB4 + 896 000c 32000000 .4byte .LBE4 + 897 0010 00000000 .4byte 0 + 898 0014 00000000 .4byte 0 + 899 0018 1A000000 .4byte .LBB3 + 900 001c 26000000 .4byte .LBE3 + 901 0020 32000000 .4byte .LBB5 + 902 0024 38000000 .4byte .LBE5 + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 17 + + + 903 0028 46000000 .4byte .LBB7 + 904 002c 52000000 .4byte .LBE7 + 905 0030 00000000 .4byte 0 + 906 0034 00000000 .4byte 0 + 907 0038 38000000 .4byte .LBB6 + 908 003c 46000000 .4byte .LBE6 + 909 0040 56000000 .4byte .LBB8 + 910 0044 5E000000 .4byte .LBE8 + 911 0048 6C000000 .4byte .LBB10 + 912 004c 76000000 .4byte .LBE10 + 913 0050 00000000 .4byte 0 + 914 0054 00000000 .4byte 0 + 915 0058 5E000000 .4byte .LBB9 + 916 005c 6A000000 .4byte .LBE9 + 917 0060 76000000 .4byte .LBB11 + 918 0064 7E000000 .4byte .LBE11 + 919 0068 8A000000 .4byte .LBB13 + 920 006c 94000000 .4byte .LBE13 + 921 0070 00000000 .4byte 0 + 922 0074 00000000 .4byte 0 + 923 0078 7E000000 .4byte .LBB12 + 924 007c 8A000000 .4byte .LBE12 + 925 0080 98000000 .4byte .LBB14 + 926 0084 A0000000 .4byte .LBE14 + 927 0088 AC000000 .4byte .LBB16 + 928 008c B8000000 .4byte .LBE16 + 929 0090 00000000 .4byte 0 + 930 0094 00000000 .4byte 0 + 931 0098 A0000000 .4byte .LBB15 + 932 009c AA000000 .4byte .LBE15 + 933 00a0 BC000000 .4byte .LBB17 + 934 00a4 C4000000 .4byte .LBE17 + 935 00a8 D0000000 .4byte .LBB18 + 936 00ac DC000000 .4byte .LBE18 + 937 00b0 00000000 .4byte 0 + 938 00b4 00000000 .4byte 0 + 939 00b8 00000000 .4byte .LFB7 + 940 00bc 02000000 .4byte .LFE7 + 941 00c0 00000000 .4byte .LFB8 + 942 00c4 02000000 .4byte .LFE8 + 943 00c8 00000000 .4byte .LFB9 + 944 00cc 02000000 .4byte .LFE9 + 945 00d0 00000000 .4byte .LFB10 + 946 00d4 18010000 .4byte .LFE10 + 947 00d8 00000000 .4byte 0 + 948 00dc 00000000 .4byte 0 + 949 .section .debug_line,"",%progbits + 950 .Ldebug_line0: + 951 0000 10010000 .section .debug_str,"MS",%progbits,1 + 951 02007700 + 951 00000201 + 951 FB0E0D00 + 951 01010101 + 952 .LASF25: + 953 0000 5F627373 .ascii "_bss_start\000" + 953 5F737461 + 953 727400 + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 18 + + + 954 .LASF24: + 955 000b 5F656461 .ascii "_edata\000" + 955 746100 + 956 .LASF30: + 957 0012 5F5F6669 .ascii "__fini_array_end\000" + 957 6E695F61 + 957 72726179 + 957 5F656E64 + 957 00 + 958 .LASF20: + 959 0023 5F5F7072 .ascii "__process_stack_base__\000" + 959 6F636573 + 959 735F7374 + 959 61636B5F + 959 62617365 + 960 .LASF14: + 961 003a 66756E63 .ascii "funcpp_t\000" + 961 70705F74 + 961 00 + 962 .LASF17: + 963 0043 5F646566 .ascii "_default_exit\000" + 963 61756C74 + 963 5F657869 + 963 7400 + 964 .LASF33: + 965 0051 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 965 73657273 + 965 5C496D61 + 965 6E6F6C5C + 965 64657665 + 966 007e 6C696361 .ascii "lications\\smartcities\000" + 966 74696F6E + 966 735C736D + 966 61727463 + 966 69746965 + 967 .LASF2: + 968 0094 756E7369 .ascii "unsigned char\000" + 968 676E6564 + 968 20636861 + 968 7200 + 969 .LASF16: + 970 00a2 5F5F6C61 .ascii "__late_init\000" + 970 74655F69 + 970 6E697400 + 971 .LASF32: + 972 00ae 2E2E2F2E .ascii "../..//os/ports/GCC/ARMCMx/crt0.c\000" + 972 2E2F2F6F + 972 732F706F + 972 7274732F + 972 4743432F + 973 .LASF8: + 974 00d0 6C6F6E67 .ascii "long unsigned int\000" + 974 20756E73 + 974 69676E65 + 974 6420696E + 974 7400 + 975 .LASF34: + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 19 + + + 976 00e2 52657365 .ascii "ResetHandler\000" + 976 7448616E + 976 646C6572 + 976 00 + 977 .LASF4: + 978 00ef 73686F72 .ascii "short unsigned int\000" + 978 7420756E + 978 7369676E + 978 65642069 + 978 6E7400 + 979 .LASF29: + 980 0102 5F5F6669 .ascii "__fini_array_start\000" + 980 6E695F61 + 980 72726179 + 980 5F737461 + 980 727400 + 981 .LASF28: + 982 0115 5F5F696E .ascii "__init_array_end\000" + 982 69745F61 + 982 72726179 + 982 5F656E64 + 982 00 + 983 .LASF35: + 984 0126 6D61696E .ascii "main\000" + 984 00 + 985 .LASF0: + 986 012b 756E7369 .ascii "unsigned int\000" + 986 676E6564 + 986 20696E74 + 986 00 + 987 .LASF10: + 988 0138 6C6F6E67 .ascii "long long unsigned int\000" + 988 206C6F6E + 988 6720756E + 988 7369676E + 988 65642069 + 989 .LASF26: + 990 014f 5F627373 .ascii "_bss_end\000" + 990 5F656E64 + 990 00 + 991 .LASF22: + 992 0158 5F746578 .ascii "_textdata\000" + 992 74646174 + 992 6100 + 993 .LASF15: + 994 0162 5F5F6561 .ascii "__early_init\000" + 994 726C795F + 994 696E6974 + 994 00 + 995 .LASF11: + 996 016f 73697A65 .ascii "sizetype\000" + 996 74797065 + 996 00 + 997 .LASF6: + 998 0178 75696E74 .ascii "uint8_t\000" + 998 385F7400 + 999 .LASF9: + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 20 + + + 1000 0180 6C6F6E67 .ascii "long long int\000" + 1000 206C6F6E + 1000 6720696E + 1000 7400 + 1001 .LASF12: + 1002 018e 63686172 .ascii "char\000" + 1002 00 + 1003 .LASF31: + 1004 0193 474E5520 .ascii "GNU C 4.7.2\000" + 1004 4320342E + 1004 372E3200 + 1005 .LASF18: + 1006 019f 5F5F6D61 .ascii "__main_stack_base__\000" + 1006 696E5F73 + 1006 7461636B + 1006 5F626173 + 1006 655F5F00 + 1007 .LASF3: + 1008 01b3 73686F72 .ascii "short int\000" + 1008 7420696E + 1008 7400 + 1009 .LASF13: + 1010 01bd 66756E63 .ascii "funcp_t\000" + 1010 705F7400 + 1011 .LASF7: + 1012 01c5 75696E74 .ascii "uint32_t\000" + 1012 33325F74 + 1012 00 + 1013 .LASF5: + 1014 01ce 6C6F6E67 .ascii "long int\000" + 1014 20696E74 + 1014 00 + 1015 .LASF23: + 1016 01d7 5F646174 .ascii "_data\000" + 1016 6100 + 1017 .LASF1: + 1018 01dd 7369676E .ascii "signed char\000" + 1018 65642063 + 1018 68617200 + 1019 .LASF21: + 1020 01e9 5F5F7072 .ascii "__process_stack_end__\000" + 1020 6F636573 + 1020 735F7374 + 1020 61636B5F + 1020 656E645F + 1021 .LASF27: + 1022 01ff 5F5F696E .ascii "__init_array_start\000" + 1022 69745F61 + 1022 72726179 + 1022 5F737461 + 1022 727400 + 1023 .LASF19: + 1024 0212 5F5F6D61 .ascii "__main_stack_end__\000" + 1024 696E5F73 + 1024 7461636B + 1024 5F656E64 + 1024 5F5F00 + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 21 + + + 1025 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\ccCGKYye.s page 22 + + +DEFINED SYMBOLS + *ABS*:00000000 crt0.c +C:\cygwin\tmp\ccCGKYye.s:19 .text.__early_init:00000000 $t +C:\cygwin\tmp\ccCGKYye.s:25 .text.__early_init:00000000 __early_init +C:\cygwin\tmp\ccCGKYye.s:38 .text.__late_init:00000000 $t +C:\cygwin\tmp\ccCGKYye.s:44 .text.__late_init:00000000 __late_init +C:\cygwin\tmp\ccCGKYye.s:56 .text._default_exit:00000000 $t +C:\cygwin\tmp\ccCGKYye.s:62 .text._default_exit:00000000 _default_exit +C:\cygwin\tmp\ccCGKYye.s:75 .text.ResetHandler:00000000 $t +C:\cygwin\tmp\ccCGKYye.s:81 .text.ResetHandler:00000000 ResetHandler +C:\cygwin\tmp\ccCGKYye.s:293 .text.ResetHandler:000000e0 $d + .debug_frame:00000010 $d +C:\cygwin\tmp\ccCGKYye.s:310 .text.ResetHandler:00000118 $t + +UNDEFINED SYMBOLS +main +__process_stack_end__ +__main_stack_base__ +__main_stack_end__ +__process_stack_base__ +_data +_edata +_textdata +_bss_start +_bss_end +__init_array_start +__init_array_end +__fini_array_start +__fini_array_end diff --git a/Project/applications/smartcities/build/lst/evtimer.lst b/Project/applications/smartcities/build/lst/evtimer.lst new file mode 100644 index 0000000..7a61861 --- /dev/null +++ b/Project/applications/smartcities/build/lst/evtimer.lst @@ -0,0 +1,1916 @@ +ARM GAS C:\cygwin\tmp\ccnN7peE.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "evtimer.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text.tmrcb,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .thumb + 22 .thumb_func + 23 .type tmrcb, %function + 24 tmrcb: + 25 .LFB7: + 26 .file 1 "../..//os/various/evtimer.c" + 27 .loc 1 39 0 + 28 .cfi_startproc + 29 @ args = 0, pretend = 0, frame = 0 + 30 @ frame_needed = 0, uses_anonymous_args = 0 + 31 .LVL0: + 32 0000 10B5 push {r4, lr} + 33 .LCFI0: + 34 .cfi_def_cfa_offset 8 + 35 .cfi_offset 4, -8 + 36 .cfi_offset 14, -4 + 37 .loc 1 42 0 + 38 0002 0021 movs r1, #0 + 39 .loc 1 39 0 + 40 0004 0446 mov r4, r0 + 41 .LVL1: + 42 .loc 1 42 0 + 43 0006 00F11400 add r0, r0, #20 + 44 .LVL2: + 45 000a FFF7FEFF bl chEvtBroadcastFlagsI + 46 .LVL3: + 47 .loc 1 43 0 + 48 000e A169 ldr r1, [r4, #24] + 49 0010 40F20002 movw r2, #:lower16:tmrcb + 50 0014 2046 mov r0, r4 + 51 0016 C0F20002 movt r2, #:upper16:tmrcb + 52 001a 2346 mov r3, r4 + 53 .loc 1 44 0 + 54 001c BDE81040 pop {r4, lr} + 55 .loc 1 43 0 + 56 0020 FFF7FEBF b chVTSetI + 57 .LVL4: + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 2 + + + 58 .cfi_endproc + 59 .LFE7: + 60 .size tmrcb, .-tmrcb + 61 0024 AFF30080 .section .text.evtStart,"ax",%progbits + 61 AFF30080 + 61 AFF30080 + 62 .align 2 + 63 .p2align 4,,15 + 64 .global evtStart + 65 .thumb + 66 .thumb_func + 67 .type evtStart, %function + 68 evtStart: + 69 .LFB8: + 70 .loc 1 52 0 + 71 .cfi_startproc + 72 @ args = 0, pretend = 0, frame = 0 + 73 @ frame_needed = 0, uses_anonymous_args = 0 + 74 .LVL5: + 75 0000 08B5 push {r3, lr} + 76 .LCFI1: + 77 .cfi_def_cfa_offset 8 + 78 .cfi_offset 3, -8 + 79 .cfi_offset 14, -4 + 80 .loc 1 52 0 + 81 0002 0346 mov r3, r0 + 82 .loc 1 54 0 + 83 @ 54 "../..//os/various/evtimer.c" 1 + 84 0004 72B6 cpsid i + 85 @ 0 "" 2 + 86 .loc 1 56 0 + 87 .thumb + 88 0006 C268 ldr r2, [r0, #12] + 89 0008 0AB1 cbz r2, .L5 + 90 .loc 1 59 0 + 91 @ 59 "../..//os/various/evtimer.c" 1 + 92 000a 62B6 cpsie i + 93 @ 0 "" 2 + 94 .thumb + 95 000c 08BD pop {r3, pc} + 96 .L5: + 97 .loc 1 57 0 + 98 000e 8169 ldr r1, [r0, #24] + 99 0010 024A ldr r2, .L6 + 100 0012 FFF7FEFF bl chVTSetI + 101 .LVL6: + 102 .loc 1 59 0 + 103 @ 59 "../..//os/various/evtimer.c" 1 + 104 0016 62B6 cpsie i + 105 @ 0 "" 2 + 106 .thumb + 107 0018 08BD pop {r3, pc} + 108 .L7: + 109 001a 00BF .align 2 + 110 .L6: + 111 001c 00000000 .word tmrcb + 112 .cfi_endproc + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 3 + + + 113 .LFE8: + 114 .size evtStart, .-evtStart + 115 .section .text.evtStop,"ax",%progbits + 116 .align 2 + 117 .p2align 4,,15 + 118 .global evtStop + 119 .thumb + 120 .thumb_func + 121 .type evtStop, %function + 122 evtStop: + 123 .LFB9: + 124 .loc 1 68 0 + 125 .cfi_startproc + 126 @ args = 0, pretend = 0, frame = 0 + 127 @ frame_needed = 0, uses_anonymous_args = 0 + 128 .LVL7: + 129 0000 08B5 push {r3, lr} + 130 .LCFI2: + 131 .cfi_def_cfa_offset 8 + 132 .cfi_offset 3, -8 + 133 .cfi_offset 14, -4 + 134 .loc 1 70 0 + 135 @ 70 "../..//os/various/evtimer.c" 1 + 136 0002 72B6 cpsid i + 137 @ 0 "" 2 + 138 .loc 1 72 0 + 139 .thumb + 140 0004 C368 ldr r3, [r0, #12] + 141 0006 0BB1 cbz r3, .L9 + 142 .loc 1 73 0 + 143 0008 FFF7FEFF bl chVTResetI + 144 .LVL8: + 145 .L9: + 146 .loc 1 75 0 + 147 @ 75 "../..//os/various/evtimer.c" 1 + 148 000c 62B6 cpsie i + 149 @ 0 "" 2 + 150 .thumb + 151 000e 08BD pop {r3, pc} + 152 .cfi_endproc + 153 .LFE9: + 154 .size evtStop, .-evtStop + 155 .text + 156 .Letext0: + 157 .file 2 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 158 .file 3 "../..//os/ports/GCC/ARMCMx/chtypes.h" + 159 .file 4 "../..//os/kernel/include/chlists.h" + 160 .file 5 "../..//os/kernel/include/chthreads.h" + 161 .file 6 "../..//os/ports/GCC/ARMCMx/chcore_v7m.h" + 162 .file 7 "../..//os/kernel/include/chvt.h" + 163 .file 8 "../..//os/kernel/include/chmtx.h" + 164 .file 9 "../..//os/kernel/include/chevents.h" + 165 .file 10 "../..//os/various/evtimer.h" + 166 .section .debug_info,"",%progbits + 167 .Ldebug_info0: + 168 0000 25060000 .4byte 0x625 + 169 0004 0200 .2byte 0x2 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 4 + + + 170 0006 00000000 .4byte .Ldebug_abbrev0 + 171 000a 04 .byte 0x4 + 172 000b 01 .uleb128 0x1 + 173 000c BD010000 .4byte .LASF74 + 174 0010 01 .byte 0x1 + 175 0011 C7020000 .4byte .LASF75 + 176 0015 6D010000 .4byte .LASF76 + 177 0019 00000000 .4byte .Ldebug_ranges0+0 + 178 001d 00000000 .4byte 0 + 179 0021 00000000 .4byte 0 + 180 0025 00000000 .4byte .Ldebug_line0 + 181 0029 02 .uleb128 0x2 + 182 002a 04 .byte 0x4 + 183 002b 05 .byte 0x5 + 184 002c 696E7400 .ascii "int\000" + 185 0030 03 .uleb128 0x3 + 186 0031 04 .byte 0x4 + 187 0032 07 .byte 0x7 + 188 0033 C7000000 .4byte .LASF0 + 189 0037 03 .uleb128 0x3 + 190 0038 01 .byte 0x1 + 191 0039 06 .byte 0x6 + 192 003a 57000000 .4byte .LASF1 + 193 003e 04 .uleb128 0x4 + 194 003f EA020000 .4byte .LASF5 + 195 0043 02 .byte 0x2 + 196 0044 2A .byte 0x2a + 197 0045 49000000 .4byte 0x49 + 198 0049 03 .uleb128 0x3 + 199 004a 01 .byte 0x1 + 200 004b 08 .byte 0x8 + 201 004c F0010000 .4byte .LASF2 + 202 0050 03 .uleb128 0x3 + 203 0051 02 .byte 0x2 + 204 0052 05 .byte 0x5 + 205 0053 14020000 .4byte .LASF3 + 206 0057 03 .uleb128 0x3 + 207 0058 02 .byte 0x2 + 208 0059 07 .byte 0x7 + 209 005a F6000000 .4byte .LASF4 + 210 005e 04 .uleb128 0x4 + 211 005f E8010000 .4byte .LASF6 + 212 0063 02 .byte 0x2 + 213 0064 4F .byte 0x4f + 214 0065 69000000 .4byte 0x69 + 215 0069 03 .uleb128 0x3 + 216 006a 04 .byte 0x4 + 217 006b 05 .byte 0x5 + 218 006c 7B000000 .4byte .LASF7 + 219 0070 04 .uleb128 0x4 + 220 0071 59020000 .4byte .LASF8 + 221 0075 02 .byte 0x2 + 222 0076 50 .byte 0x50 + 223 0077 7B000000 .4byte 0x7b + 224 007b 03 .uleb128 0x3 + 225 007c 04 .byte 0x4 + 226 007d 07 .byte 0x7 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 5 + + + 227 007e DC000000 .4byte .LASF9 + 228 0082 03 .uleb128 0x3 + 229 0083 08 .byte 0x8 + 230 0084 05 .byte 0x5 + 231 0085 49000000 .4byte .LASF10 + 232 0089 03 .uleb128 0x3 + 233 008a 08 .byte 0x8 + 234 008b 07 .byte 0x7 + 235 008c 19000000 .4byte .LASF11 + 236 0090 04 .uleb128 0x4 + 237 0091 17010000 .4byte .LASF12 + 238 0095 03 .byte 0x3 + 239 0096 2F .byte 0x2f + 240 0097 3E000000 .4byte 0x3e + 241 009b 04 .uleb128 0x4 + 242 009c 84000000 .4byte .LASF13 + 243 00a0 03 .byte 0x3 + 244 00a1 30 .byte 0x30 + 245 00a2 3E000000 .4byte 0x3e + 246 00a6 04 .uleb128 0x4 + 247 00a7 D1010000 .4byte .LASF14 + 248 00ab 03 .byte 0x3 + 249 00ac 31 .byte 0x31 + 250 00ad 3E000000 .4byte 0x3e + 251 00b1 04 .uleb128 0x4 + 252 00b2 E0010000 .4byte .LASF15 + 253 00b6 03 .byte 0x3 + 254 00b7 32 .byte 0x32 + 255 00b8 70000000 .4byte 0x70 + 256 00bc 04 .uleb128 0x4 + 257 00bd 09010000 .4byte .LASF16 + 258 00c1 03 .byte 0x3 + 259 00c2 33 .byte 0x33 + 260 00c3 5E000000 .4byte 0x5e + 261 00c7 04 .uleb128 0x4 + 262 00c8 2B010000 .4byte .LASF17 + 263 00cc 03 .byte 0x3 + 264 00cd 35 .byte 0x35 + 265 00ce 70000000 .4byte 0x70 + 266 00d2 04 .uleb128 0x4 + 267 00d3 81020000 .4byte .LASF18 + 268 00d7 03 .byte 0x3 + 269 00d8 36 .byte 0x36 + 270 00d9 70000000 .4byte 0x70 + 271 00dd 04 .uleb128 0x4 + 272 00de 3C020000 .4byte .LASF19 + 273 00e2 04 .byte 0x4 + 274 00e3 2A .byte 0x2a + 275 00e4 E8000000 .4byte 0xe8 + 276 00e8 05 .uleb128 0x5 + 277 00e9 3C020000 .4byte .LASF19 + 278 00ed 48 .byte 0x48 + 279 00ee 05 .byte 0x5 + 280 00ef 5E .byte 0x5e + 281 00f0 FF010000 .4byte 0x1ff + 282 00f4 06 .uleb128 0x6 + 283 00f5 2D020000 .4byte .LASF20 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 6 + + + 284 00f9 05 .byte 0x5 + 285 00fa 5F .byte 0x5f + 286 00fb 24020000 .4byte 0x224 + 287 00ff 02 .byte 0x2 + 288 0100 23 .byte 0x23 + 289 0101 00 .uleb128 0 + 290 0102 06 .uleb128 0x6 + 291 0103 D9010000 .4byte .LASF21 + 292 0107 05 .byte 0x5 + 293 0108 61 .byte 0x61 + 294 0109 24020000 .4byte 0x224 + 295 010d 02 .byte 0x2 + 296 010e 23 .byte 0x23 + 297 010f 04 .uleb128 0x4 + 298 0110 06 .uleb128 0x6 + 299 0111 42000000 .4byte .LASF22 + 300 0115 05 .byte 0x5 + 301 0116 63 .byte 0x63 + 302 0117 B1000000 .4byte 0xb1 + 303 011b 02 .byte 0x2 + 304 011c 23 .byte 0x23 + 305 011d 08 .uleb128 0x8 + 306 011e 06 .uleb128 0x6 + 307 011f 24030000 .4byte .LASF23 + 308 0123 05 .byte 0x5 + 309 0124 64 .byte 0x64 + 310 0125 F1020000 .4byte 0x2f1 + 311 0129 02 .byte 0x2 + 312 012a 23 .byte 0x23 + 313 012b 0C .uleb128 0xc + 314 012c 06 .uleb128 0x6 + 315 012d A2000000 .4byte .LASF24 + 316 0131 05 .byte 0x5 + 317 0132 66 .byte 0x66 + 318 0133 24020000 .4byte 0x224 + 319 0137 02 .byte 0x2 + 320 0138 23 .byte 0x23 + 321 0139 10 .uleb128 0x10 + 322 013a 06 .uleb128 0x6 + 323 013b 65010000 .4byte .LASF25 + 324 013f 05 .byte 0x5 + 325 0140 67 .byte 0x67 + 326 0141 24020000 .4byte 0x224 + 327 0145 02 .byte 0x2 + 328 0146 23 .byte 0x23 + 329 0147 14 .uleb128 0x14 + 330 0148 06 .uleb128 0x6 + 331 0149 07030000 .4byte .LASF26 + 332 014d 05 .byte 0x5 + 333 014e 6E .byte 0x6e + 334 014f 8C040000 .4byte 0x48c + 335 0153 02 .byte 0x2 + 336 0154 23 .byte 0x23 + 337 0155 18 .uleb128 0x18 + 338 0156 06 .uleb128 0x6 + 339 0157 1E020000 .4byte .LASF27 + 340 015b 05 .byte 0x5 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 7 + + + 341 015c 79 .byte 0x79 + 342 015d 9B000000 .4byte 0x9b + 343 0161 02 .byte 0x2 + 344 0162 23 .byte 0x23 + 345 0163 1C .uleb128 0x1c + 346 0164 06 .uleb128 0x6 + 347 0165 34020000 .4byte .LASF28 + 348 0169 05 .byte 0x5 + 349 016a 7D .byte 0x7d + 350 016b 90000000 .4byte 0x90 + 351 016f 02 .byte 0x2 + 352 0170 23 .byte 0x23 + 353 0171 1D .uleb128 0x1d + 354 0172 06 .uleb128 0x6 + 355 0173 E3020000 .4byte .LASF29 + 356 0177 05 .byte 0x5 + 357 0178 82 .byte 0x82 + 358 0179 A6000000 .4byte 0xa6 + 359 017d 02 .byte 0x2 + 360 017e 23 .byte 0x23 + 361 017f 1E .uleb128 0x1e + 362 0180 06 .uleb128 0x6 + 363 0181 A7020000 .4byte .LASF30 + 364 0185 05 .byte 0x5 + 365 0186 89 .byte 0x89 + 366 0187 9C030000 .4byte 0x39c + 367 018b 02 .byte 0x2 + 368 018c 23 .byte 0x23 + 369 018d 20 .uleb128 0x20 + 370 018e 07 .uleb128 0x7 + 371 018f 705F7500 .ascii "p_u\000" + 372 0193 05 .byte 0x5 + 373 0194 AE .byte 0xae + 374 0195 57040000 .4byte 0x457 + 375 0199 02 .byte 0x2 + 376 019a 23 .byte 0x23 + 377 019b 24 .uleb128 0x24 + 378 019c 06 .uleb128 0x6 + 379 019d 2A030000 .4byte .LASF31 + 380 01a1 05 .byte 0x5 + 381 01a2 B3 .byte 0xb3 + 382 01a3 4C020000 .4byte 0x24c + 383 01a7 02 .byte 0x2 + 384 01a8 23 .byte 0x23 + 385 01a9 28 .uleb128 0x28 + 386 01aa 06 .uleb128 0x6 + 387 01ab B5020000 .4byte .LASF32 + 388 01af 05 .byte 0x5 + 389 01b0 B9 .byte 0xb9 + 390 01b1 2A020000 .4byte 0x22a + 391 01b5 02 .byte 0x2 + 392 01b6 23 .byte 0x23 + 393 01b7 2C .uleb128 0x2c + 394 01b8 06 .uleb128 0x6 + 395 01b9 0C000000 .4byte .LASF33 + 396 01bd 05 .byte 0x5 + 397 01be BD .byte 0xbd + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 8 + + + 398 01bf BC000000 .4byte 0xbc + 399 01c3 02 .byte 0x2 + 400 01c4 23 .byte 0x23 + 401 01c5 34 .uleb128 0x34 + 402 01c6 06 .uleb128 0x6 + 403 01c7 4E020000 .4byte .LASF34 + 404 01cb 05 .byte 0x5 + 405 01cc C3 .byte 0xc3 + 406 01cd C7000000 .4byte 0xc7 + 407 01d1 02 .byte 0x2 + 408 01d2 23 .byte 0x23 + 409 01d3 38 .uleb128 0x38 + 410 01d4 06 .uleb128 0x6 + 411 01d5 0A020000 .4byte .LASF35 + 412 01d9 05 .byte 0x5 + 413 01da CA .byte 0xca + 414 01db 9E040000 .4byte 0x49e + 415 01df 02 .byte 0x2 + 416 01e0 23 .byte 0x23 + 417 01e1 3C .uleb128 0x3c + 418 01e2 06 .uleb128 0x6 + 419 01e3 8B020000 .4byte .LASF36 + 420 01e7 05 .byte 0x5 + 421 01e8 CE .byte 0xce + 422 01e9 B1000000 .4byte 0xb1 + 423 01ed 02 .byte 0x2 + 424 01ee 23 .byte 0x23 + 425 01ef 40 .uleb128 0x40 + 426 01f0 06 .uleb128 0x6 + 427 01f1 6B000000 .4byte .LASF37 + 428 01f5 05 .byte 0x5 + 429 01f6 D4 .byte 0xd4 + 430 01f7 62020000 .4byte 0x262 + 431 01fb 02 .byte 0x2 + 432 01fc 23 .byte 0x23 + 433 01fd 44 .uleb128 0x44 + 434 01fe 00 .byte 0 + 435 01ff 08 .uleb128 0x8 + 436 0200 08 .byte 0x8 + 437 0201 04 .byte 0x4 + 438 0202 61 .byte 0x61 + 439 0203 24020000 .4byte 0x224 + 440 0207 06 .uleb128 0x6 + 441 0208 2D020000 .4byte .LASF20 + 442 020c 04 .byte 0x4 + 443 020d 62 .byte 0x62 + 444 020e 24020000 .4byte 0x224 + 445 0212 02 .byte 0x2 + 446 0213 23 .byte 0x23 + 447 0214 00 .uleb128 0 + 448 0215 06 .uleb128 0x6 + 449 0216 D9010000 .4byte .LASF21 + 450 021a 04 .byte 0x4 + 451 021b 64 .byte 0x64 + 452 021c 24020000 .4byte 0x224 + 453 0220 02 .byte 0x2 + 454 0221 23 .byte 0x23 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 9 + + + 455 0222 04 .uleb128 0x4 + 456 0223 00 .byte 0 + 457 0224 09 .uleb128 0x9 + 458 0225 04 .byte 0x4 + 459 0226 DD000000 .4byte 0xdd + 460 022a 04 .uleb128 0x4 + 461 022b B0010000 .4byte .LASF38 + 462 022f 04 .byte 0x4 + 463 0230 66 .byte 0x66 + 464 0231 FF010000 .4byte 0x1ff + 465 0235 08 .uleb128 0x8 + 466 0236 04 .byte 0x4 + 467 0237 04 .byte 0x4 + 468 0238 6B .byte 0x6b + 469 0239 4C020000 .4byte 0x24c + 470 023d 06 .uleb128 0x6 + 471 023e 2D020000 .4byte .LASF20 + 472 0242 04 .byte 0x4 + 473 0243 6D .byte 0x6d + 474 0244 24020000 .4byte 0x224 + 475 0248 02 .byte 0x2 + 476 0249 23 .byte 0x23 + 477 024a 00 .uleb128 0 + 478 024b 00 .byte 0 + 479 024c 04 .uleb128 0x4 + 480 024d 1F010000 .4byte .LASF39 + 481 0251 04 .byte 0x4 + 482 0252 70 .byte 0x70 + 483 0253 35020000 .4byte 0x235 + 484 0257 04 .uleb128 0x4 + 485 0258 AA000000 .4byte .LASF40 + 486 025c 06 .byte 0x6 + 487 025d D7 .byte 0xd7 + 488 025e 62020000 .4byte 0x262 + 489 0262 0A .uleb128 0xa + 490 0263 04 .byte 0x4 + 491 0264 05 .uleb128 0x5 + 492 0265 AE020000 .4byte .LASF41 + 493 0269 24 .byte 0x24 + 494 026a 06 .byte 0x6 + 495 026b FE .byte 0xfe + 496 026c F1020000 .4byte 0x2f1 + 497 0270 0B .uleb128 0xb + 498 0271 723400 .ascii "r4\000" + 499 0274 06 .byte 0x6 + 500 0275 1101 .2byte 0x111 + 501 0277 57020000 .4byte 0x257 + 502 027b 02 .byte 0x2 + 503 027c 23 .byte 0x23 + 504 027d 00 .uleb128 0 + 505 027e 0B .uleb128 0xb + 506 027f 723500 .ascii "r5\000" + 507 0282 06 .byte 0x6 + 508 0283 1201 .2byte 0x112 + 509 0285 57020000 .4byte 0x257 + 510 0289 02 .byte 0x2 + 511 028a 23 .byte 0x23 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 10 + + + 512 028b 04 .uleb128 0x4 + 513 028c 0B .uleb128 0xb + 514 028d 723600 .ascii "r6\000" + 515 0290 06 .byte 0x6 + 516 0291 1301 .2byte 0x113 + 517 0293 57020000 .4byte 0x257 + 518 0297 02 .byte 0x2 + 519 0298 23 .byte 0x23 + 520 0299 08 .uleb128 0x8 + 521 029a 0B .uleb128 0xb + 522 029b 723700 .ascii "r7\000" + 523 029e 06 .byte 0x6 + 524 029f 1401 .2byte 0x114 + 525 02a1 57020000 .4byte 0x257 + 526 02a5 02 .byte 0x2 + 527 02a6 23 .byte 0x23 + 528 02a7 0C .uleb128 0xc + 529 02a8 0B .uleb128 0xb + 530 02a9 723800 .ascii "r8\000" + 531 02ac 06 .byte 0x6 + 532 02ad 1501 .2byte 0x115 + 533 02af 57020000 .4byte 0x257 + 534 02b3 02 .byte 0x2 + 535 02b4 23 .byte 0x23 + 536 02b5 10 .uleb128 0x10 + 537 02b6 0B .uleb128 0xb + 538 02b7 723900 .ascii "r9\000" + 539 02ba 06 .byte 0x6 + 540 02bb 1601 .2byte 0x116 + 541 02bd 57020000 .4byte 0x257 + 542 02c1 02 .byte 0x2 + 543 02c2 23 .byte 0x23 + 544 02c3 14 .uleb128 0x14 + 545 02c4 0B .uleb128 0xb + 546 02c5 72313000 .ascii "r10\000" + 547 02c9 06 .byte 0x6 + 548 02ca 1701 .2byte 0x117 + 549 02cc 57020000 .4byte 0x257 + 550 02d0 02 .byte 0x2 + 551 02d1 23 .byte 0x23 + 552 02d2 18 .uleb128 0x18 + 553 02d3 0B .uleb128 0xb + 554 02d4 72313100 .ascii "r11\000" + 555 02d8 06 .byte 0x6 + 556 02d9 1801 .2byte 0x118 + 557 02db 57020000 .4byte 0x257 + 558 02df 02 .byte 0x2 + 559 02e0 23 .byte 0x23 + 560 02e1 1C .uleb128 0x1c + 561 02e2 0B .uleb128 0xb + 562 02e3 6C7200 .ascii "lr\000" + 563 02e6 06 .byte 0x6 + 564 02e7 1901 .2byte 0x119 + 565 02e9 57020000 .4byte 0x257 + 566 02ed 02 .byte 0x2 + 567 02ee 23 .byte 0x23 + 568 02ef 20 .uleb128 0x20 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 11 + + + 569 02f0 00 .byte 0 + 570 02f1 0C .uleb128 0xc + 571 02f2 EE000000 .4byte .LASF42 + 572 02f6 04 .byte 0x4 + 573 02f7 06 .byte 0x6 + 574 02f8 2301 .2byte 0x123 + 575 02fa 0E030000 .4byte 0x30e + 576 02fe 0B .uleb128 0xb + 577 02ff 72313300 .ascii "r13\000" + 578 0303 06 .byte 0x6 + 579 0304 2401 .2byte 0x124 + 580 0306 0E030000 .4byte 0x30e + 581 030a 02 .byte 0x2 + 582 030b 23 .byte 0x23 + 583 030c 00 .uleb128 0 + 584 030d 00 .byte 0 + 585 030e 09 .uleb128 0x9 + 586 030f 04 .byte 0x4 + 587 0310 64020000 .4byte 0x264 + 588 0314 03 .uleb128 0x3 + 589 0315 04 .byte 0x4 + 590 0316 07 .byte 0x7 + 591 0317 4B010000 .4byte .LASF43 + 592 031b 04 .uleb128 0x4 + 593 031c 96020000 .4byte .LASF44 + 594 0320 07 .byte 0x7 + 595 0321 61 .byte 0x61 + 596 0322 26030000 .4byte 0x326 + 597 0326 09 .uleb128 0x9 + 598 0327 04 .byte 0x4 + 599 0328 2C030000 .4byte 0x32c + 600 032c 0D .uleb128 0xd + 601 032d 01 .byte 0x1 + 602 032e 38030000 .4byte 0x338 + 603 0332 0E .uleb128 0xe + 604 0333 62020000 .4byte 0x262 + 605 0337 00 .byte 0 + 606 0338 04 .uleb128 0x4 + 607 0339 62020000 .4byte .LASF45 + 608 033d 07 .byte 0x7 + 609 033e 66 .byte 0x66 + 610 033f 43030000 .4byte 0x343 + 611 0343 05 .uleb128 0x5 + 612 0344 62020000 .4byte .LASF45 + 613 0348 14 .byte 0x14 + 614 0349 07 .byte 0x7 + 615 034a 6D .byte 0x6d + 616 034b 96030000 .4byte 0x396 + 617 034f 06 .uleb128 0x6 + 618 0350 D4000000 .4byte .LASF46 + 619 0354 07 .byte 0x7 + 620 0355 6E .byte 0x6e + 621 0356 96030000 .4byte 0x396 + 622 035a 02 .byte 0x2 + 623 035b 23 .byte 0x23 + 624 035c 00 .uleb128 0 + 625 035d 06 .uleb128 0x6 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 12 + + + 626 035e B3000000 .4byte .LASF47 + 627 0362 07 .byte 0x7 + 628 0363 70 .byte 0x70 + 629 0364 96030000 .4byte 0x396 + 630 0368 02 .byte 0x2 + 631 0369 23 .byte 0x23 + 632 036a 04 .uleb128 0x4 + 633 036b 06 .uleb128 0x6 + 634 036c 3D010000 .4byte .LASF48 + 635 0370 07 .byte 0x7 + 636 0371 72 .byte 0x72 + 637 0372 D2000000 .4byte 0xd2 + 638 0376 02 .byte 0x2 + 639 0377 23 .byte 0x23 + 640 0378 08 .uleb128 0x8 + 641 0379 06 .uleb128 0x6 + 642 037a 54010000 .4byte .LASF49 + 643 037e 07 .byte 0x7 + 644 037f 73 .byte 0x73 + 645 0380 1B030000 .4byte 0x31b + 646 0384 02 .byte 0x2 + 647 0385 23 .byte 0x23 + 648 0386 0C .uleb128 0xc + 649 0387 06 .uleb128 0x6 + 650 0388 C0020000 .4byte .LASF50 + 651 038c 07 .byte 0x7 + 652 038d 75 .byte 0x75 + 653 038e 62020000 .4byte 0x262 + 654 0392 02 .byte 0x2 + 655 0393 23 .byte 0x23 + 656 0394 10 .uleb128 0x10 + 657 0395 00 .byte 0 + 658 0396 09 .uleb128 0x9 + 659 0397 04 .byte 0x4 + 660 0398 38030000 .4byte 0x338 + 661 039c 0F .uleb128 0xf + 662 039d D2000000 .4byte 0xd2 + 663 03a1 05 .uleb128 0x5 + 664 03a2 37010000 .4byte .LASF51 + 665 03a6 10 .byte 0x10 + 666 03a7 08 .byte 0x8 + 667 03a8 2C .byte 0x2c + 668 03a9 D8030000 .4byte 0x3d8 + 669 03ad 06 .uleb128 0x6 + 670 03ae 73000000 .4byte .LASF52 + 671 03b2 08 .byte 0x8 + 672 03b3 2D .byte 0x2d + 673 03b4 2A020000 .4byte 0x22a + 674 03b8 02 .byte 0x2 + 675 03b9 23 .byte 0x23 + 676 03ba 00 .uleb128 0 + 677 03bb 06 .uleb128 0x6 + 678 03bc 1C030000 .4byte .LASF53 + 679 03c0 08 .byte 0x8 + 680 03c1 2F .byte 0x2f + 681 03c2 24020000 .4byte 0x224 + 682 03c6 02 .byte 0x2 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 13 + + + 683 03c7 23 .byte 0x23 + 684 03c8 08 .uleb128 0x8 + 685 03c9 06 .uleb128 0x6 + 686 03ca 7A020000 .4byte .LASF54 + 687 03ce 08 .byte 0x8 + 688 03cf 31 .byte 0x31 + 689 03d0 D8030000 .4byte 0x3d8 + 690 03d4 02 .byte 0x2 + 691 03d5 23 .byte 0x23 + 692 03d6 0C .uleb128 0xc + 693 03d7 00 .byte 0 + 694 03d8 09 .uleb128 0x9 + 695 03d9 04 .byte 0x4 + 696 03da A1030000 .4byte 0x3a1 + 697 03de 04 .uleb128 0x4 + 698 03df 37010000 .4byte .LASF51 + 699 03e3 08 .byte 0x8 + 700 03e4 33 .byte 0x33 + 701 03e5 A1030000 .4byte 0x3a1 + 702 03e9 04 .uleb128 0x4 + 703 03ea F2020000 .4byte .LASF55 + 704 03ee 09 .byte 0x9 + 705 03ef 29 .byte 0x29 + 706 03f0 F4030000 .4byte 0x3f4 + 707 03f4 05 .uleb128 0x5 + 708 03f5 F2020000 .4byte .LASF55 + 709 03f9 0C .byte 0xc + 710 03fa 09 .byte 0x9 + 711 03fb 2E .byte 0x2e + 712 03fc 2B040000 .4byte 0x42b + 713 0400 06 .uleb128 0x6 + 714 0401 0F010000 .4byte .LASF56 + 715 0405 09 .byte 0x9 + 716 0406 2F .byte 0x2f + 717 0407 2B040000 .4byte 0x42b + 718 040b 02 .byte 0x2 + 719 040c 23 .byte 0x23 + 720 040d 00 .uleb128 0 + 721 040e 06 .uleb128 0x6 + 722 040f FE010000 .4byte .LASF57 + 723 0413 09 .byte 0x9 + 724 0414 32 .byte 0x32 + 725 0415 24020000 .4byte 0x224 + 726 0419 02 .byte 0x2 + 727 041a 23 .byte 0x23 + 728 041b 04 .uleb128 0x4 + 729 041c 06 .uleb128 0x6 + 730 041d C9010000 .4byte .LASF58 + 731 0421 09 .byte 0x9 + 732 0422 34 .byte 0x34 + 733 0423 C7000000 .4byte 0xc7 + 734 0427 02 .byte 0x2 + 735 0428 23 .byte 0x23 + 736 0429 08 .uleb128 0x8 + 737 042a 00 .byte 0 + 738 042b 09 .uleb128 0x9 + 739 042c 04 .byte 0x4 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 14 + + + 740 042d E9030000 .4byte 0x3e9 + 741 0431 05 .uleb128 0x5 + 742 0432 BB000000 .4byte .LASF59 + 743 0436 04 .byte 0x4 + 744 0437 09 .byte 0x9 + 745 0438 3C .byte 0x3c + 746 0439 4C040000 .4byte 0x44c + 747 043d 06 .uleb128 0x6 + 748 043e 0E030000 .4byte .LASF60 + 749 0442 09 .byte 0x9 + 750 0443 3D .byte 0x3d + 751 0444 2B040000 .4byte 0x42b + 752 0448 02 .byte 0x2 + 753 0449 23 .byte 0x23 + 754 044a 00 .uleb128 0 + 755 044b 00 .byte 0 + 756 044c 04 .uleb128 0x4 + 757 044d BB000000 .4byte .LASF59 + 758 0451 09 .byte 0x9 + 759 0452 40 .byte 0x40 + 760 0453 31040000 .4byte 0x431 + 761 0457 10 .uleb128 0x10 + 762 0458 04 .byte 0x4 + 763 0459 05 .byte 0x5 + 764 045a 90 .byte 0x90 + 765 045b 8C040000 .4byte 0x48c + 766 045f 11 .uleb128 0x11 + 767 0460 12000000 .4byte .LASF61 + 768 0464 05 .byte 0x5 + 769 0465 97 .byte 0x97 + 770 0466 BC000000 .4byte 0xbc + 771 046a 11 .uleb128 0x11 + 772 046b 30000000 .4byte .LASF62 + 773 046f 05 .byte 0x5 + 774 0470 9E .byte 0x9e + 775 0471 BC000000 .4byte 0xbc + 776 0475 11 .uleb128 0x11 + 777 0476 00030000 .4byte .LASF63 + 778 047a 05 .byte 0x5 + 779 047b A5 .byte 0xa5 + 780 047c 62020000 .4byte 0x262 + 781 0480 11 .uleb128 0x11 + 782 0481 26020000 .4byte .LASF64 + 783 0485 05 .byte 0x5 + 784 0486 AC .byte 0xac + 785 0487 C7000000 .4byte 0xc7 + 786 048b 00 .byte 0 + 787 048c 09 .uleb128 0x9 + 788 048d 04 .byte 0x4 + 789 048e 92040000 .4byte 0x492 + 790 0492 12 .uleb128 0x12 + 791 0493 97040000 .4byte 0x497 + 792 0497 03 .uleb128 0x3 + 793 0498 01 .byte 0x1 + 794 0499 08 .byte 0x8 + 795 049a 6F020000 .4byte .LASF65 + 796 049e 09 .uleb128 0x9 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 15 + + + 797 049f 04 .byte 0x4 + 798 04a0 DE030000 .4byte 0x3de + 799 04a4 08 .uleb128 0x8 + 800 04a5 1C .byte 0x1c + 801 04a6 0A .byte 0xa + 802 04a7 2A .byte 0x2a + 803 04a8 D7040000 .4byte 0x4d7 + 804 04ac 06 .uleb128 0x6 + 805 04ad 16030000 .4byte .LASF66 + 806 04b1 0A .byte 0xa + 807 04b2 2B .byte 0x2b + 808 04b3 38030000 .4byte 0x338 + 809 04b7 02 .byte 0x2 + 810 04b8 23 .byte 0x23 + 811 04b9 00 .uleb128 0 + 812 04ba 06 .uleb128 0x6 + 813 04bb 45010000 .4byte .LASF67 + 814 04bf 0A .byte 0xa + 815 04c0 2C .byte 0x2c + 816 04c1 4C040000 .4byte 0x44c + 817 04c5 02 .byte 0x2 + 818 04c6 23 .byte 0x23 + 819 04c7 14 .uleb128 0x14 + 820 04c8 06 .uleb128 0x6 + 821 04c9 00000000 .4byte .LASF68 + 822 04cd 0A .byte 0xa + 823 04ce 2D .byte 0x2d + 824 04cf D2000000 .4byte 0xd2 + 825 04d3 02 .byte 0x2 + 826 04d4 23 .byte 0x23 + 827 04d5 18 .uleb128 0x18 + 828 04d6 00 .byte 0 + 829 04d7 04 .uleb128 0x4 + 830 04d8 63000000 .4byte .LASF69 + 831 04dc 0A .byte 0xa + 832 04dd 2E .byte 0x2e + 833 04de A4040000 .4byte 0x4a4 + 834 04e2 13 .uleb128 0x13 + 835 04e3 74020000 .4byte .LASF77 + 836 04e7 01 .byte 0x1 + 837 04e8 27 .byte 0x27 + 838 04e9 01 .byte 0x1 + 839 04ea 00000000 .4byte .LFB7 + 840 04ee 24000000 .4byte .LFE7 + 841 04f2 00000000 .4byte .LLST0 + 842 04f6 01 .byte 0x1 + 843 04f7 51050000 .4byte 0x551 + 844 04fb 14 .uleb128 0x14 + 845 04fc 7000 .ascii "p\000" + 846 04fe 01 .byte 0x1 + 847 04ff 27 .byte 0x27 + 848 0500 62020000 .4byte 0x262 + 849 0504 20000000 .4byte .LLST1 + 850 0508 15 .uleb128 0x15 + 851 0509 65747000 .ascii "etp\000" + 852 050d 01 .byte 0x1 + 853 050e 28 .byte 0x28 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 16 + + + 854 050f 51050000 .4byte 0x551 + 855 0513 3E000000 .4byte .LLST2 + 856 0517 16 .uleb128 0x16 + 857 0518 0E000000 .4byte .LVL3 + 858 051c D6050000 .4byte 0x5d6 + 859 0520 30050000 .4byte 0x530 + 860 0524 17 .uleb128 0x17 + 861 0525 01 .byte 0x1 + 862 0526 51 .byte 0x51 + 863 0527 01 .byte 0x1 + 864 0528 30 .byte 0x30 + 865 0529 17 .uleb128 0x17 + 866 052a 01 .byte 0x1 + 867 052b 50 .byte 0x50 + 868 052c 02 .byte 0x2 + 869 052d 74 .byte 0x74 + 870 052e 14 .sleb128 20 + 871 052f 00 .byte 0 + 872 0530 18 .uleb128 0x18 + 873 0531 24000000 .4byte .LVL4 + 874 0535 01 .byte 0x1 + 875 0536 F5050000 .4byte 0x5f5 + 876 053a 17 .uleb128 0x17 + 877 053b 01 .byte 0x1 + 878 053c 53 .byte 0x53 + 879 053d 02 .byte 0x2 + 880 053e 74 .byte 0x74 + 881 053f 00 .sleb128 0 + 882 0540 17 .uleb128 0x17 + 883 0541 01 .byte 0x1 + 884 0542 52 .byte 0x52 + 885 0543 05 .byte 0x5 + 886 0544 03 .byte 0x3 + 887 0545 00000000 .4byte tmrcb + 888 0549 17 .uleb128 0x17 + 889 054a 01 .byte 0x1 + 890 054b 50 .byte 0x50 + 891 054c 02 .byte 0x2 + 892 054d 74 .byte 0x74 + 893 054e 00 .sleb128 0 + 894 054f 00 .byte 0 + 895 0550 00 .byte 0 + 896 0551 09 .uleb128 0x9 + 897 0552 04 .byte 0x4 + 898 0553 D7040000 .4byte 0x4d7 + 899 0557 19 .uleb128 0x19 + 900 0558 01 .byte 0x1 + 901 0559 39000000 .4byte .LASF70 + 902 055d 01 .byte 0x1 + 903 055e 34 .byte 0x34 + 904 055f 01 .byte 0x1 + 905 0560 00000000 .4byte .LFB8 + 906 0564 20000000 .4byte .LFE8 + 907 0568 5C000000 .4byte .LLST3 + 908 056c 01 .byte 0x1 + 909 056d 9B050000 .4byte 0x59b + 910 0571 14 .uleb128 0x14 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 17 + + + 911 0572 65747000 .ascii "etp\000" + 912 0576 01 .byte 0x1 + 913 0577 34 .byte 0x34 + 914 0578 51050000 .4byte 0x551 + 915 057c 7C000000 .4byte .LLST4 + 916 0580 1A .uleb128 0x1a + 917 0581 16000000 .4byte .LVL6 + 918 0585 F5050000 .4byte 0x5f5 + 919 0589 17 .uleb128 0x17 + 920 058a 01 .byte 0x1 + 921 058b 52 .byte 0x52 + 922 058c 05 .byte 0x5 + 923 058d 03 .byte 0x3 + 924 058e 00000000 .4byte tmrcb + 925 0592 17 .uleb128 0x17 + 926 0593 01 .byte 0x1 + 927 0594 50 .byte 0x50 + 928 0595 03 .byte 0x3 + 929 0596 F3 .byte 0xf3 + 930 0597 01 .uleb128 0x1 + 931 0598 50 .byte 0x50 + 932 0599 00 .byte 0 + 933 059a 00 .byte 0 + 934 059b 19 .uleb128 0x19 + 935 059c 01 .byte 0x1 + 936 059d 9F020000 .4byte .LASF71 + 937 05a1 01 .byte 0x1 + 938 05a2 44 .byte 0x44 + 939 05a3 01 .byte 0x1 + 940 05a4 00000000 .4byte .LFB9 + 941 05a8 10000000 .4byte .LFE9 + 942 05ac 9D000000 .4byte .LLST5 + 943 05b0 01 .byte 0x1 + 944 05b1 D6050000 .4byte 0x5d6 + 945 05b5 14 .uleb128 0x14 + 946 05b6 65747000 .ascii "etp\000" + 947 05ba 01 .byte 0x1 + 948 05bb 44 .byte 0x44 + 949 05bc 51050000 .4byte 0x551 + 950 05c0 BD000000 .4byte .LLST6 + 951 05c4 1A .uleb128 0x1a + 952 05c5 0C000000 .4byte .LVL8 + 953 05c9 18060000 .4byte 0x618 + 954 05cd 17 .uleb128 0x17 + 955 05ce 01 .byte 0x1 + 956 05cf 50 .byte 0x50 + 957 05d0 03 .byte 0x3 + 958 05d1 F3 .byte 0xf3 + 959 05d2 01 .uleb128 0x1 + 960 05d3 50 .byte 0x50 + 961 05d4 00 .byte 0 + 962 05d5 00 .byte 0 + 963 05d6 1B .uleb128 0x1b + 964 05d7 01 .byte 0x1 + 965 05d8 8D000000 .4byte .LASF72 + 966 05dc 09 .byte 0x9 + 967 05dd B3 .byte 0xb3 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 18 + + + 968 05de 01 .byte 0x1 + 969 05df 01 .byte 0x1 + 970 05e0 EF050000 .4byte 0x5ef + 971 05e4 0E .uleb128 0xe + 972 05e5 EF050000 .4byte 0x5ef + 973 05e9 0E .uleb128 0xe + 974 05ea C7000000 .4byte 0xc7 + 975 05ee 00 .byte 0 + 976 05ef 09 .uleb128 0x9 + 977 05f0 04 .byte 0x4 + 978 05f1 4C040000 .4byte 0x44c + 979 05f5 1B .uleb128 0x1b + 980 05f6 01 .byte 0x1 + 981 05f7 5C010000 .4byte .LASF73 + 982 05fb 07 .byte 0x7 + 983 05fc BF .byte 0xbf + 984 05fd 01 .byte 0x1 + 985 05fe 01 .byte 0x1 + 986 05ff 18060000 .4byte 0x618 + 987 0603 0E .uleb128 0xe + 988 0604 96030000 .4byte 0x396 + 989 0608 0E .uleb128 0xe + 990 0609 D2000000 .4byte 0xd2 + 991 060d 0E .uleb128 0xe + 992 060e 1B030000 .4byte 0x31b + 993 0612 0E .uleb128 0xe + 994 0613 62020000 .4byte 0x262 + 995 0617 00 .byte 0 + 996 0618 1C .uleb128 0x1c + 997 0619 01 .byte 0x1 + 998 061a 43020000 .4byte .LASF78 + 999 061e 07 .byte 0x7 + 1000 061f C0 .byte 0xc0 + 1001 0620 01 .byte 0x1 + 1002 0621 01 .byte 0x1 + 1003 0622 0E .uleb128 0xe + 1004 0623 96030000 .4byte 0x396 + 1005 0627 00 .byte 0 + 1006 0628 00 .byte 0 + 1007 .section .debug_abbrev,"",%progbits + 1008 .Ldebug_abbrev0: + 1009 0000 01 .uleb128 0x1 + 1010 0001 11 .uleb128 0x11 + 1011 0002 01 .byte 0x1 + 1012 0003 25 .uleb128 0x25 + 1013 0004 0E .uleb128 0xe + 1014 0005 13 .uleb128 0x13 + 1015 0006 0B .uleb128 0xb + 1016 0007 03 .uleb128 0x3 + 1017 0008 0E .uleb128 0xe + 1018 0009 1B .uleb128 0x1b + 1019 000a 0E .uleb128 0xe + 1020 000b 55 .uleb128 0x55 + 1021 000c 06 .uleb128 0x6 + 1022 000d 11 .uleb128 0x11 + 1023 000e 01 .uleb128 0x1 + 1024 000f 52 .uleb128 0x52 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 19 + + + 1025 0010 01 .uleb128 0x1 + 1026 0011 10 .uleb128 0x10 + 1027 0012 06 .uleb128 0x6 + 1028 0013 00 .byte 0 + 1029 0014 00 .byte 0 + 1030 0015 02 .uleb128 0x2 + 1031 0016 24 .uleb128 0x24 + 1032 0017 00 .byte 0 + 1033 0018 0B .uleb128 0xb + 1034 0019 0B .uleb128 0xb + 1035 001a 3E .uleb128 0x3e + 1036 001b 0B .uleb128 0xb + 1037 001c 03 .uleb128 0x3 + 1038 001d 08 .uleb128 0x8 + 1039 001e 00 .byte 0 + 1040 001f 00 .byte 0 + 1041 0020 03 .uleb128 0x3 + 1042 0021 24 .uleb128 0x24 + 1043 0022 00 .byte 0 + 1044 0023 0B .uleb128 0xb + 1045 0024 0B .uleb128 0xb + 1046 0025 3E .uleb128 0x3e + 1047 0026 0B .uleb128 0xb + 1048 0027 03 .uleb128 0x3 + 1049 0028 0E .uleb128 0xe + 1050 0029 00 .byte 0 + 1051 002a 00 .byte 0 + 1052 002b 04 .uleb128 0x4 + 1053 002c 16 .uleb128 0x16 + 1054 002d 00 .byte 0 + 1055 002e 03 .uleb128 0x3 + 1056 002f 0E .uleb128 0xe + 1057 0030 3A .uleb128 0x3a + 1058 0031 0B .uleb128 0xb + 1059 0032 3B .uleb128 0x3b + 1060 0033 0B .uleb128 0xb + 1061 0034 49 .uleb128 0x49 + 1062 0035 13 .uleb128 0x13 + 1063 0036 00 .byte 0 + 1064 0037 00 .byte 0 + 1065 0038 05 .uleb128 0x5 + 1066 0039 13 .uleb128 0x13 + 1067 003a 01 .byte 0x1 + 1068 003b 03 .uleb128 0x3 + 1069 003c 0E .uleb128 0xe + 1070 003d 0B .uleb128 0xb + 1071 003e 0B .uleb128 0xb + 1072 003f 3A .uleb128 0x3a + 1073 0040 0B .uleb128 0xb + 1074 0041 3B .uleb128 0x3b + 1075 0042 0B .uleb128 0xb + 1076 0043 01 .uleb128 0x1 + 1077 0044 13 .uleb128 0x13 + 1078 0045 00 .byte 0 + 1079 0046 00 .byte 0 + 1080 0047 06 .uleb128 0x6 + 1081 0048 0D .uleb128 0xd + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 20 + + + 1082 0049 00 .byte 0 + 1083 004a 03 .uleb128 0x3 + 1084 004b 0E .uleb128 0xe + 1085 004c 3A .uleb128 0x3a + 1086 004d 0B .uleb128 0xb + 1087 004e 3B .uleb128 0x3b + 1088 004f 0B .uleb128 0xb + 1089 0050 49 .uleb128 0x49 + 1090 0051 13 .uleb128 0x13 + 1091 0052 38 .uleb128 0x38 + 1092 0053 0A .uleb128 0xa + 1093 0054 00 .byte 0 + 1094 0055 00 .byte 0 + 1095 0056 07 .uleb128 0x7 + 1096 0057 0D .uleb128 0xd + 1097 0058 00 .byte 0 + 1098 0059 03 .uleb128 0x3 + 1099 005a 08 .uleb128 0x8 + 1100 005b 3A .uleb128 0x3a + 1101 005c 0B .uleb128 0xb + 1102 005d 3B .uleb128 0x3b + 1103 005e 0B .uleb128 0xb + 1104 005f 49 .uleb128 0x49 + 1105 0060 13 .uleb128 0x13 + 1106 0061 38 .uleb128 0x38 + 1107 0062 0A .uleb128 0xa + 1108 0063 00 .byte 0 + 1109 0064 00 .byte 0 + 1110 0065 08 .uleb128 0x8 + 1111 0066 13 .uleb128 0x13 + 1112 0067 01 .byte 0x1 + 1113 0068 0B .uleb128 0xb + 1114 0069 0B .uleb128 0xb + 1115 006a 3A .uleb128 0x3a + 1116 006b 0B .uleb128 0xb + 1117 006c 3B .uleb128 0x3b + 1118 006d 0B .uleb128 0xb + 1119 006e 01 .uleb128 0x1 + 1120 006f 13 .uleb128 0x13 + 1121 0070 00 .byte 0 + 1122 0071 00 .byte 0 + 1123 0072 09 .uleb128 0x9 + 1124 0073 0F .uleb128 0xf + 1125 0074 00 .byte 0 + 1126 0075 0B .uleb128 0xb + 1127 0076 0B .uleb128 0xb + 1128 0077 49 .uleb128 0x49 + 1129 0078 13 .uleb128 0x13 + 1130 0079 00 .byte 0 + 1131 007a 00 .byte 0 + 1132 007b 0A .uleb128 0xa + 1133 007c 0F .uleb128 0xf + 1134 007d 00 .byte 0 + 1135 007e 0B .uleb128 0xb + 1136 007f 0B .uleb128 0xb + 1137 0080 00 .byte 0 + 1138 0081 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 21 + + + 1139 0082 0B .uleb128 0xb + 1140 0083 0D .uleb128 0xd + 1141 0084 00 .byte 0 + 1142 0085 03 .uleb128 0x3 + 1143 0086 08 .uleb128 0x8 + 1144 0087 3A .uleb128 0x3a + 1145 0088 0B .uleb128 0xb + 1146 0089 3B .uleb128 0x3b + 1147 008a 05 .uleb128 0x5 + 1148 008b 49 .uleb128 0x49 + 1149 008c 13 .uleb128 0x13 + 1150 008d 38 .uleb128 0x38 + 1151 008e 0A .uleb128 0xa + 1152 008f 00 .byte 0 + 1153 0090 00 .byte 0 + 1154 0091 0C .uleb128 0xc + 1155 0092 13 .uleb128 0x13 + 1156 0093 01 .byte 0x1 + 1157 0094 03 .uleb128 0x3 + 1158 0095 0E .uleb128 0xe + 1159 0096 0B .uleb128 0xb + 1160 0097 0B .uleb128 0xb + 1161 0098 3A .uleb128 0x3a + 1162 0099 0B .uleb128 0xb + 1163 009a 3B .uleb128 0x3b + 1164 009b 05 .uleb128 0x5 + 1165 009c 01 .uleb128 0x1 + 1166 009d 13 .uleb128 0x13 + 1167 009e 00 .byte 0 + 1168 009f 00 .byte 0 + 1169 00a0 0D .uleb128 0xd + 1170 00a1 15 .uleb128 0x15 + 1171 00a2 01 .byte 0x1 + 1172 00a3 27 .uleb128 0x27 + 1173 00a4 0C .uleb128 0xc + 1174 00a5 01 .uleb128 0x1 + 1175 00a6 13 .uleb128 0x13 + 1176 00a7 00 .byte 0 + 1177 00a8 00 .byte 0 + 1178 00a9 0E .uleb128 0xe + 1179 00aa 05 .uleb128 0x5 + 1180 00ab 00 .byte 0 + 1181 00ac 49 .uleb128 0x49 + 1182 00ad 13 .uleb128 0x13 + 1183 00ae 00 .byte 0 + 1184 00af 00 .byte 0 + 1185 00b0 0F .uleb128 0xf + 1186 00b1 35 .uleb128 0x35 + 1187 00b2 00 .byte 0 + 1188 00b3 49 .uleb128 0x49 + 1189 00b4 13 .uleb128 0x13 + 1190 00b5 00 .byte 0 + 1191 00b6 00 .byte 0 + 1192 00b7 10 .uleb128 0x10 + 1193 00b8 17 .uleb128 0x17 + 1194 00b9 01 .byte 0x1 + 1195 00ba 0B .uleb128 0xb + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 22 + + + 1196 00bb 0B .uleb128 0xb + 1197 00bc 3A .uleb128 0x3a + 1198 00bd 0B .uleb128 0xb + 1199 00be 3B .uleb128 0x3b + 1200 00bf 0B .uleb128 0xb + 1201 00c0 01 .uleb128 0x1 + 1202 00c1 13 .uleb128 0x13 + 1203 00c2 00 .byte 0 + 1204 00c3 00 .byte 0 + 1205 00c4 11 .uleb128 0x11 + 1206 00c5 0D .uleb128 0xd + 1207 00c6 00 .byte 0 + 1208 00c7 03 .uleb128 0x3 + 1209 00c8 0E .uleb128 0xe + 1210 00c9 3A .uleb128 0x3a + 1211 00ca 0B .uleb128 0xb + 1212 00cb 3B .uleb128 0x3b + 1213 00cc 0B .uleb128 0xb + 1214 00cd 49 .uleb128 0x49 + 1215 00ce 13 .uleb128 0x13 + 1216 00cf 00 .byte 0 + 1217 00d0 00 .byte 0 + 1218 00d1 12 .uleb128 0x12 + 1219 00d2 26 .uleb128 0x26 + 1220 00d3 00 .byte 0 + 1221 00d4 49 .uleb128 0x49 + 1222 00d5 13 .uleb128 0x13 + 1223 00d6 00 .byte 0 + 1224 00d7 00 .byte 0 + 1225 00d8 13 .uleb128 0x13 + 1226 00d9 2E .uleb128 0x2e + 1227 00da 01 .byte 0x1 + 1228 00db 03 .uleb128 0x3 + 1229 00dc 0E .uleb128 0xe + 1230 00dd 3A .uleb128 0x3a + 1231 00de 0B .uleb128 0xb + 1232 00df 3B .uleb128 0x3b + 1233 00e0 0B .uleb128 0xb + 1234 00e1 27 .uleb128 0x27 + 1235 00e2 0C .uleb128 0xc + 1236 00e3 11 .uleb128 0x11 + 1237 00e4 01 .uleb128 0x1 + 1238 00e5 12 .uleb128 0x12 + 1239 00e6 01 .uleb128 0x1 + 1240 00e7 40 .uleb128 0x40 + 1241 00e8 06 .uleb128 0x6 + 1242 00e9 9742 .uleb128 0x2117 + 1243 00eb 0C .uleb128 0xc + 1244 00ec 01 .uleb128 0x1 + 1245 00ed 13 .uleb128 0x13 + 1246 00ee 00 .byte 0 + 1247 00ef 00 .byte 0 + 1248 00f0 14 .uleb128 0x14 + 1249 00f1 05 .uleb128 0x5 + 1250 00f2 00 .byte 0 + 1251 00f3 03 .uleb128 0x3 + 1252 00f4 08 .uleb128 0x8 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 23 + + + 1253 00f5 3A .uleb128 0x3a + 1254 00f6 0B .uleb128 0xb + 1255 00f7 3B .uleb128 0x3b + 1256 00f8 0B .uleb128 0xb + 1257 00f9 49 .uleb128 0x49 + 1258 00fa 13 .uleb128 0x13 + 1259 00fb 02 .uleb128 0x2 + 1260 00fc 06 .uleb128 0x6 + 1261 00fd 00 .byte 0 + 1262 00fe 00 .byte 0 + 1263 00ff 15 .uleb128 0x15 + 1264 0100 34 .uleb128 0x34 + 1265 0101 00 .byte 0 + 1266 0102 03 .uleb128 0x3 + 1267 0103 08 .uleb128 0x8 + 1268 0104 3A .uleb128 0x3a + 1269 0105 0B .uleb128 0xb + 1270 0106 3B .uleb128 0x3b + 1271 0107 0B .uleb128 0xb + 1272 0108 49 .uleb128 0x49 + 1273 0109 13 .uleb128 0x13 + 1274 010a 02 .uleb128 0x2 + 1275 010b 06 .uleb128 0x6 + 1276 010c 00 .byte 0 + 1277 010d 00 .byte 0 + 1278 010e 16 .uleb128 0x16 + 1279 010f 898201 .uleb128 0x4109 + 1280 0112 01 .byte 0x1 + 1281 0113 11 .uleb128 0x11 + 1282 0114 01 .uleb128 0x1 + 1283 0115 31 .uleb128 0x31 + 1284 0116 13 .uleb128 0x13 + 1285 0117 01 .uleb128 0x1 + 1286 0118 13 .uleb128 0x13 + 1287 0119 00 .byte 0 + 1288 011a 00 .byte 0 + 1289 011b 17 .uleb128 0x17 + 1290 011c 8A8201 .uleb128 0x410a + 1291 011f 00 .byte 0 + 1292 0120 02 .uleb128 0x2 + 1293 0121 0A .uleb128 0xa + 1294 0122 9142 .uleb128 0x2111 + 1295 0124 0A .uleb128 0xa + 1296 0125 00 .byte 0 + 1297 0126 00 .byte 0 + 1298 0127 18 .uleb128 0x18 + 1299 0128 898201 .uleb128 0x4109 + 1300 012b 01 .byte 0x1 + 1301 012c 11 .uleb128 0x11 + 1302 012d 01 .uleb128 0x1 + 1303 012e 9542 .uleb128 0x2115 + 1304 0130 0C .uleb128 0xc + 1305 0131 31 .uleb128 0x31 + 1306 0132 13 .uleb128 0x13 + 1307 0133 00 .byte 0 + 1308 0134 00 .byte 0 + 1309 0135 19 .uleb128 0x19 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 24 + + + 1310 0136 2E .uleb128 0x2e + 1311 0137 01 .byte 0x1 + 1312 0138 3F .uleb128 0x3f + 1313 0139 0C .uleb128 0xc + 1314 013a 03 .uleb128 0x3 + 1315 013b 0E .uleb128 0xe + 1316 013c 3A .uleb128 0x3a + 1317 013d 0B .uleb128 0xb + 1318 013e 3B .uleb128 0x3b + 1319 013f 0B .uleb128 0xb + 1320 0140 27 .uleb128 0x27 + 1321 0141 0C .uleb128 0xc + 1322 0142 11 .uleb128 0x11 + 1323 0143 01 .uleb128 0x1 + 1324 0144 12 .uleb128 0x12 + 1325 0145 01 .uleb128 0x1 + 1326 0146 40 .uleb128 0x40 + 1327 0147 06 .uleb128 0x6 + 1328 0148 9742 .uleb128 0x2117 + 1329 014a 0C .uleb128 0xc + 1330 014b 01 .uleb128 0x1 + 1331 014c 13 .uleb128 0x13 + 1332 014d 00 .byte 0 + 1333 014e 00 .byte 0 + 1334 014f 1A .uleb128 0x1a + 1335 0150 898201 .uleb128 0x4109 + 1336 0153 01 .byte 0x1 + 1337 0154 11 .uleb128 0x11 + 1338 0155 01 .uleb128 0x1 + 1339 0156 31 .uleb128 0x31 + 1340 0157 13 .uleb128 0x13 + 1341 0158 00 .byte 0 + 1342 0159 00 .byte 0 + 1343 015a 1B .uleb128 0x1b + 1344 015b 2E .uleb128 0x2e + 1345 015c 01 .byte 0x1 + 1346 015d 3F .uleb128 0x3f + 1347 015e 0C .uleb128 0xc + 1348 015f 03 .uleb128 0x3 + 1349 0160 0E .uleb128 0xe + 1350 0161 3A .uleb128 0x3a + 1351 0162 0B .uleb128 0xb + 1352 0163 3B .uleb128 0x3b + 1353 0164 0B .uleb128 0xb + 1354 0165 27 .uleb128 0x27 + 1355 0166 0C .uleb128 0xc + 1356 0167 3C .uleb128 0x3c + 1357 0168 0C .uleb128 0xc + 1358 0169 01 .uleb128 0x1 + 1359 016a 13 .uleb128 0x13 + 1360 016b 00 .byte 0 + 1361 016c 00 .byte 0 + 1362 016d 1C .uleb128 0x1c + 1363 016e 2E .uleb128 0x2e + 1364 016f 01 .byte 0x1 + 1365 0170 3F .uleb128 0x3f + 1366 0171 0C .uleb128 0xc + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 25 + + + 1367 0172 03 .uleb128 0x3 + 1368 0173 0E .uleb128 0xe + 1369 0174 3A .uleb128 0x3a + 1370 0175 0B .uleb128 0xb + 1371 0176 3B .uleb128 0x3b + 1372 0177 0B .uleb128 0xb + 1373 0178 27 .uleb128 0x27 + 1374 0179 0C .uleb128 0xc + 1375 017a 3C .uleb128 0x3c + 1376 017b 0C .uleb128 0xc + 1377 017c 00 .byte 0 + 1378 017d 00 .byte 0 + 1379 017e 00 .byte 0 + 1380 .section .debug_loc,"",%progbits + 1381 .Ldebug_loc0: + 1382 .LLST0: + 1383 0000 00000000 .4byte .LFB7 + 1384 0004 02000000 .4byte .LCFI0 + 1385 0008 0200 .2byte 0x2 + 1386 000a 7D .byte 0x7d + 1387 000b 00 .sleb128 0 + 1388 000c 02000000 .4byte .LCFI0 + 1389 0010 24000000 .4byte .LFE7 + 1390 0014 0200 .2byte 0x2 + 1391 0016 7D .byte 0x7d + 1392 0017 08 .sleb128 8 + 1393 0018 00000000 .4byte 0 + 1394 001c 00000000 .4byte 0 + 1395 .LLST1: + 1396 0020 00000000 .4byte .LVL0 + 1397 0024 0A000000 .4byte .LVL2 + 1398 0028 0100 .2byte 0x1 + 1399 002a 50 .byte 0x50 + 1400 002b 0A000000 .4byte .LVL2 + 1401 002f 24000000 .4byte .LFE7 + 1402 0033 0100 .2byte 0x1 + 1403 0035 54 .byte 0x54 + 1404 0036 00000000 .4byte 0 + 1405 003a 00000000 .4byte 0 + 1406 .LLST2: + 1407 003e 06000000 .4byte .LVL1 + 1408 0042 0A000000 .4byte .LVL2 + 1409 0046 0100 .2byte 0x1 + 1410 0048 50 .byte 0x50 + 1411 0049 0A000000 .4byte .LVL2 + 1412 004d 24000000 .4byte .LFE7 + 1413 0051 0100 .2byte 0x1 + 1414 0053 54 .byte 0x54 + 1415 0054 00000000 .4byte 0 + 1416 0058 00000000 .4byte 0 + 1417 .LLST3: + 1418 005c 00000000 .4byte .LFB8 + 1419 0060 02000000 .4byte .LCFI1 + 1420 0064 0200 .2byte 0x2 + 1421 0066 7D .byte 0x7d + 1422 0067 00 .sleb128 0 + 1423 0068 02000000 .4byte .LCFI1 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 26 + + + 1424 006c 20000000 .4byte .LFE8 + 1425 0070 0200 .2byte 0x2 + 1426 0072 7D .byte 0x7d + 1427 0073 08 .sleb128 8 + 1428 0074 00000000 .4byte 0 + 1429 0078 00000000 .4byte 0 + 1430 .LLST4: + 1431 007c 00000000 .4byte .LVL5 + 1432 0080 15000000 .4byte .LVL6-1 + 1433 0084 0100 .2byte 0x1 + 1434 0086 50 .byte 0x50 + 1435 0087 15000000 .4byte .LVL6-1 + 1436 008b 20000000 .4byte .LFE8 + 1437 008f 0400 .2byte 0x4 + 1438 0091 F3 .byte 0xf3 + 1439 0092 01 .uleb128 0x1 + 1440 0093 50 .byte 0x50 + 1441 0094 9F .byte 0x9f + 1442 0095 00000000 .4byte 0 + 1443 0099 00000000 .4byte 0 + 1444 .LLST5: + 1445 009d 00000000 .4byte .LFB9 + 1446 00a1 02000000 .4byte .LCFI2 + 1447 00a5 0200 .2byte 0x2 + 1448 00a7 7D .byte 0x7d + 1449 00a8 00 .sleb128 0 + 1450 00a9 02000000 .4byte .LCFI2 + 1451 00ad 10000000 .4byte .LFE9 + 1452 00b1 0200 .2byte 0x2 + 1453 00b3 7D .byte 0x7d + 1454 00b4 08 .sleb128 8 + 1455 00b5 00000000 .4byte 0 + 1456 00b9 00000000 .4byte 0 + 1457 .LLST6: + 1458 00bd 00000000 .4byte .LVL7 + 1459 00c1 0B000000 .4byte .LVL8-1 + 1460 00c5 0100 .2byte 0x1 + 1461 00c7 50 .byte 0x50 + 1462 00c8 0B000000 .4byte .LVL8-1 + 1463 00cc 10000000 .4byte .LFE9 + 1464 00d0 0400 .2byte 0x4 + 1465 00d2 F3 .byte 0xf3 + 1466 00d3 01 .uleb128 0x1 + 1467 00d4 50 .byte 0x50 + 1468 00d5 9F .byte 0x9f + 1469 00d6 00000000 .4byte 0 + 1470 00da 00000000 .4byte 0 + 1471 .section .debug_aranges,"",%progbits + 1472 0000 2C000000 .4byte 0x2c + 1473 0004 0200 .2byte 0x2 + 1474 0006 00000000 .4byte .Ldebug_info0 + 1475 000a 04 .byte 0x4 + 1476 000b 00 .byte 0 + 1477 000c 0000 .2byte 0 + 1478 000e 0000 .2byte 0 + 1479 0010 00000000 .4byte .LFB7 + 1480 0014 24000000 .4byte .LFE7-.LFB7 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 27 + + + 1481 0018 00000000 .4byte .LFB8 + 1482 001c 20000000 .4byte .LFE8-.LFB8 + 1483 0020 00000000 .4byte .LFB9 + 1484 0024 10000000 .4byte .LFE9-.LFB9 + 1485 0028 00000000 .4byte 0 + 1486 002c 00000000 .4byte 0 + 1487 .section .debug_ranges,"",%progbits + 1488 .Ldebug_ranges0: + 1489 0000 00000000 .4byte .LFB7 + 1490 0004 24000000 .4byte .LFE7 + 1491 0008 00000000 .4byte .LFB8 + 1492 000c 20000000 .4byte .LFE8 + 1493 0010 00000000 .4byte .LFB9 + 1494 0014 10000000 .4byte .LFE9 + 1495 0018 00000000 .4byte 0 + 1496 001c 00000000 .4byte 0 + 1497 .section .debug_line,"",%progbits + 1498 .Ldebug_line0: + 1499 0000 52010000 .section .debug_str,"MS",%progbits,1 + 1499 02000E01 + 1499 00000201 + 1499 FB0E0D00 + 1499 01010101 + 1500 .LASF68: + 1501 0000 65745F69 .ascii "et_interval\000" + 1501 6E746572 + 1501 76616C00 + 1502 .LASF33: + 1503 000c 705F6D73 .ascii "p_msg\000" + 1503 6700 + 1504 .LASF61: + 1505 0012 7264796D .ascii "rdymsg\000" + 1505 736700 + 1506 .LASF11: + 1507 0019 6C6F6E67 .ascii "long long unsigned int\000" + 1507 206C6F6E + 1507 6720756E + 1507 7369676E + 1507 65642069 + 1508 .LASF62: + 1509 0030 65786974 .ascii "exitcode\000" + 1509 636F6465 + 1509 00 + 1510 .LASF70: + 1511 0039 65767453 .ascii "evtStart\000" + 1511 74617274 + 1511 00 + 1512 .LASF22: + 1513 0042 705F7072 .ascii "p_prio\000" + 1513 696F00 + 1514 .LASF10: + 1515 0049 6C6F6E67 .ascii "long long int\000" + 1515 206C6F6E + 1515 6720696E + 1515 7400 + 1516 .LASF1: + 1517 0057 7369676E .ascii "signed char\000" + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 28 + + + 1517 65642063 + 1517 68617200 + 1518 .LASF69: + 1519 0063 45765469 .ascii "EvTimer\000" + 1519 6D657200 + 1520 .LASF37: + 1521 006b 705F6D70 .ascii "p_mpool\000" + 1521 6F6F6C00 + 1522 .LASF52: + 1523 0073 6D5F7175 .ascii "m_queue\000" + 1523 65756500 + 1524 .LASF7: + 1525 007b 6C6F6E67 .ascii "long int\000" + 1525 20696E74 + 1525 00 + 1526 .LASF13: + 1527 0084 74737461 .ascii "tstate_t\000" + 1527 74655F74 + 1527 00 + 1528 .LASF72: + 1529 008d 63684576 .ascii "chEvtBroadcastFlagsI\000" + 1529 7442726F + 1529 61646361 + 1529 7374466C + 1529 61677349 + 1530 .LASF24: + 1531 00a2 705F6E65 .ascii "p_newer\000" + 1531 77657200 + 1532 .LASF40: + 1533 00aa 72656761 .ascii "regarm_t\000" + 1533 726D5F74 + 1533 00 + 1534 .LASF47: + 1535 00b3 76745F70 .ascii "vt_prev\000" + 1535 72657600 + 1536 .LASF59: + 1537 00bb 4576656E .ascii "EventSource\000" + 1537 74536F75 + 1537 72636500 + 1538 .LASF0: + 1539 00c7 756E7369 .ascii "unsigned int\000" + 1539 676E6564 + 1539 20696E74 + 1539 00 + 1540 .LASF46: + 1541 00d4 76745F6E .ascii "vt_next\000" + 1541 65787400 + 1542 .LASF9: + 1543 00dc 6C6F6E67 .ascii "long unsigned int\000" + 1543 20756E73 + 1543 69676E65 + 1543 6420696E + 1543 7400 + 1544 .LASF42: + 1545 00ee 636F6E74 .ascii "context\000" + 1545 65787400 + 1546 .LASF4: + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 29 + + + 1547 00f6 73686F72 .ascii "short unsigned int\000" + 1547 7420756E + 1547 7369676E + 1547 65642069 + 1547 6E7400 + 1548 .LASF16: + 1549 0109 6D73675F .ascii "msg_t\000" + 1549 7400 + 1550 .LASF56: + 1551 010f 656C5F6E .ascii "el_next\000" + 1551 65787400 + 1552 .LASF12: + 1553 0117 746D6F64 .ascii "tmode_t\000" + 1553 655F7400 + 1554 .LASF39: + 1555 011f 54687265 .ascii "ThreadsList\000" + 1555 6164734C + 1555 69737400 + 1556 .LASF17: + 1557 012b 6576656E .ascii "eventmask_t\000" + 1557 746D6173 + 1557 6B5F7400 + 1558 .LASF51: + 1559 0137 4D757465 .ascii "Mutex\000" + 1559 7800 + 1560 .LASF48: + 1561 013d 76745F74 .ascii "vt_time\000" + 1561 696D6500 + 1562 .LASF67: + 1563 0145 65745F65 .ascii "et_es\000" + 1563 7300 + 1564 .LASF43: + 1565 014b 73697A65 .ascii "sizetype\000" + 1565 74797065 + 1565 00 + 1566 .LASF49: + 1567 0154 76745F66 .ascii "vt_func\000" + 1567 756E6300 + 1568 .LASF73: + 1569 015c 63685654 .ascii "chVTSetI\000" + 1569 53657449 + 1569 00 + 1570 .LASF25: + 1571 0165 705F6F6C .ascii "p_older\000" + 1571 64657200 + 1572 .LASF76: + 1573 016d 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 1573 73657273 + 1573 5C496D61 + 1573 6E6F6C5C + 1573 64657665 + 1574 019a 6C696361 .ascii "lications\\smartcities\000" + 1574 74696F6E + 1574 735C736D + 1574 61727463 + 1574 69746965 + 1575 .LASF38: + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 30 + + + 1576 01b0 54687265 .ascii "ThreadsQueue\000" + 1576 61647351 + 1576 75657565 + 1576 00 + 1577 .LASF74: + 1578 01bd 474E5520 .ascii "GNU C 4.7.2\000" + 1578 4320342E + 1578 372E3200 + 1579 .LASF58: + 1580 01c9 656C5F6D .ascii "el_mask\000" + 1580 61736B00 + 1581 .LASF14: + 1582 01d1 74726566 .ascii "trefs_t\000" + 1582 735F7400 + 1583 .LASF21: + 1584 01d9 705F7072 .ascii "p_prev\000" + 1584 657600 + 1585 .LASF15: + 1586 01e0 74707269 .ascii "tprio_t\000" + 1586 6F5F7400 + 1587 .LASF6: + 1588 01e8 696E7433 .ascii "int32_t\000" + 1588 325F7400 + 1589 .LASF2: + 1590 01f0 756E7369 .ascii "unsigned char\000" + 1590 676E6564 + 1590 20636861 + 1590 7200 + 1591 .LASF57: + 1592 01fe 656C5F6C .ascii "el_listener\000" + 1592 69737465 + 1592 6E657200 + 1593 .LASF35: + 1594 020a 705F6D74 .ascii "p_mtxlist\000" + 1594 786C6973 + 1594 7400 + 1595 .LASF3: + 1596 0214 73686F72 .ascii "short int\000" + 1596 7420696E + 1596 7400 + 1597 .LASF27: + 1598 021e 705F7374 .ascii "p_state\000" + 1598 61746500 + 1599 .LASF64: + 1600 0226 65776D61 .ascii "ewmask\000" + 1600 736B00 + 1601 .LASF20: + 1602 022d 705F6E65 .ascii "p_next\000" + 1602 787400 + 1603 .LASF28: + 1604 0234 705F666C .ascii "p_flags\000" + 1604 61677300 + 1605 .LASF19: + 1606 023c 54687265 .ascii "Thread\000" + 1606 616400 + 1607 .LASF78: + 1608 0243 63685654 .ascii "chVTResetI\000" + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 31 + + + 1608 52657365 + 1608 744900 + 1609 .LASF34: + 1610 024e 705F6570 .ascii "p_epending\000" + 1610 656E6469 + 1610 6E6700 + 1611 .LASF8: + 1612 0259 75696E74 .ascii "uint32_t\000" + 1612 33325F74 + 1612 00 + 1613 .LASF45: + 1614 0262 56697274 .ascii "VirtualTimer\000" + 1614 75616C54 + 1614 696D6572 + 1614 00 + 1615 .LASF65: + 1616 026f 63686172 .ascii "char\000" + 1616 00 + 1617 .LASF77: + 1618 0274 746D7263 .ascii "tmrcb\000" + 1618 6200 + 1619 .LASF54: + 1620 027a 6D5F6E65 .ascii "m_next\000" + 1620 787400 + 1621 .LASF18: + 1622 0281 73797374 .ascii "systime_t\000" + 1622 696D655F + 1622 7400 + 1623 .LASF36: + 1624 028b 705F7265 .ascii "p_realprio\000" + 1624 616C7072 + 1624 696F00 + 1625 .LASF44: + 1626 0296 76746675 .ascii "vtfunc_t\000" + 1626 6E635F74 + 1626 00 + 1627 .LASF71: + 1628 029f 65767453 .ascii "evtStop\000" + 1628 746F7000 + 1629 .LASF30: + 1630 02a7 705F7469 .ascii "p_time\000" + 1630 6D6500 + 1631 .LASF41: + 1632 02ae 696E7463 .ascii "intctx\000" + 1632 747800 + 1633 .LASF32: + 1634 02b5 705F6D73 .ascii "p_msgqueue\000" + 1634 67717565 + 1634 756500 + 1635 .LASF50: + 1636 02c0 76745F70 .ascii "vt_par\000" + 1636 617200 + 1637 .LASF75: + 1638 02c7 2E2E2F2E .ascii "../..//os/various/evtimer.c\000" + 1638 2E2F2F6F + 1638 732F7661 + 1638 72696F75 + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 32 + + + 1638 732F6576 + 1639 .LASF29: + 1640 02e3 705F7265 .ascii "p_refs\000" + 1640 667300 + 1641 .LASF5: + 1642 02ea 75696E74 .ascii "uint8_t\000" + 1642 385F7400 + 1643 .LASF55: + 1644 02f2 4576656E .ascii "EventListener\000" + 1644 744C6973 + 1644 74656E65 + 1644 7200 + 1645 .LASF63: + 1646 0300 77746F62 .ascii "wtobjp\000" + 1646 6A7000 + 1647 .LASF26: + 1648 0307 705F6E61 .ascii "p_name\000" + 1648 6D6500 + 1649 .LASF60: + 1650 030e 65735F6E .ascii "es_next\000" + 1650 65787400 + 1651 .LASF66: + 1652 0316 65745F76 .ascii "et_vt\000" + 1652 7400 + 1653 .LASF53: + 1654 031c 6D5F6F77 .ascii "m_owner\000" + 1654 6E657200 + 1655 .LASF23: + 1656 0324 705F6374 .ascii "p_ctx\000" + 1656 7800 + 1657 .LASF31: + 1658 032a 705F7761 .ascii "p_waiting\000" + 1658 6974696E + 1658 6700 + 1659 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\ccnN7peE.s page 33 + + +DEFINED SYMBOLS + *ABS*:00000000 evtimer.c +C:\cygwin\tmp\ccnN7peE.s:19 .text.tmrcb:00000000 $t +C:\cygwin\tmp\ccnN7peE.s:24 .text.tmrcb:00000000 tmrcb +C:\cygwin\tmp\ccnN7peE.s:62 .text.evtStart:00000000 $t +C:\cygwin\tmp\ccnN7peE.s:68 .text.evtStart:00000000 evtStart +C:\cygwin\tmp\ccnN7peE.s:111 .text.evtStart:0000001c $d +C:\cygwin\tmp\ccnN7peE.s:116 .text.evtStop:00000000 $t +C:\cygwin\tmp\ccnN7peE.s:122 .text.evtStop:00000000 evtStop + .debug_frame:00000010 $d + +UNDEFINED SYMBOLS +chEvtBroadcastFlagsI +chVTSetI +chVTResetI diff --git a/Project/applications/smartcities/build/lst/main.lst b/Project/applications/smartcities/build/lst/main.lst new file mode 100644 index 0000000..fd10868 --- /dev/null +++ b/Project/applications/smartcities/build/lst/main.lst @@ -0,0 +1,2724 @@ +ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "main.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text.NMIVector,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .global NMIVector + 22 .thumb + 23 .thumb_func + 24 .type NMIVector, %function + 25 NMIVector: + 26 .LFB62: + 27 .file 1 "../..//econais/inc/STM32F1/libwismart_irqs.h" + 28 .loc 1 26 0 + 29 .cfi_startproc + 30 @ Volatile: function does not return. + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 0000 08B5 push {r3, lr} + 34 .LCFI0: + 35 .cfi_def_cfa_offset 8 + 36 .cfi_offset 3, -8 + 37 .cfi_offset 14, -4 + 38 .loc 1 26 0 + 39 0002 0248 ldr r0, .L4 + 40 0004 FFF7FEFF bl print + 41 .LVL0: + 42 .L2: + 43 0008 FEE7 b .L2 + 44 .L5: + 45 000a 00BF .align 2 + 46 .L4: + 47 000c 00000000 .word .LC0 + 48 .cfi_endproc + 49 .LFE62: + 50 .size NMIVector, .-NMIVector + 51 .section .text.MemManageVector,"ax",%progbits + 52 .align 2 + 53 .p2align 4,,15 + 54 .global MemManageVector + 55 .thumb + 56 .thumb_func + 57 .type MemManageVector, %function + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 2 + + + 58 MemManageVector: + 59 .LFB63: + 60 .loc 1 27 0 + 61 .cfi_startproc + 62 @ Volatile: function does not return. + 63 @ args = 0, pretend = 0, frame = 0 + 64 @ frame_needed = 0, uses_anonymous_args = 0 + 65 0000 08B5 push {r3, lr} + 66 .LCFI1: + 67 .cfi_def_cfa_offset 8 + 68 .cfi_offset 3, -8 + 69 .cfi_offset 14, -4 + 70 .loc 1 27 0 + 71 0002 0248 ldr r0, .L8 + 72 0004 FFF7FEFF bl print + 73 .LVL1: + 74 .L7: + 75 0008 FEE7 b .L7 + 76 .L9: + 77 000a 00BF .align 2 + 78 .L8: + 79 000c 04000000 .word .LC1 + 80 .cfi_endproc + 81 .LFE63: + 82 .size MemManageVector, .-MemManageVector + 83 .section .text.BusFaultVector,"ax",%progbits + 84 .align 2 + 85 .p2align 4,,15 + 86 .global BusFaultVector + 87 .thumb + 88 .thumb_func + 89 .type BusFaultVector, %function + 90 BusFaultVector: + 91 .LFB64: + 92 .loc 1 28 0 + 93 .cfi_startproc + 94 @ Volatile: function does not return. + 95 @ args = 0, pretend = 0, frame = 0 + 96 @ frame_needed = 0, uses_anonymous_args = 0 + 97 0000 08B5 push {r3, lr} + 98 .LCFI2: + 99 .cfi_def_cfa_offset 8 + 100 .cfi_offset 3, -8 + 101 .cfi_offset 14, -4 + 102 .loc 1 28 0 + 103 0002 0248 ldr r0, .L12 + 104 0004 FFF7FEFF bl print + 105 .LVL2: + 106 .L11: + 107 0008 FEE7 b .L11 + 108 .L13: + 109 000a 00BF .align 2 + 110 .L12: + 111 000c 0C000000 .word .LC2 + 112 .cfi_endproc + 113 .LFE64: + 114 .size BusFaultVector, .-BusFaultVector + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 3 + + + 115 .section .text.UsageFaultVector,"ax",%progbits + 116 .align 2 + 117 .p2align 4,,15 + 118 .global UsageFaultVector + 119 .thumb + 120 .thumb_func + 121 .type UsageFaultVector, %function + 122 UsageFaultVector: + 123 .LFB65: + 124 .loc 1 29 0 + 125 .cfi_startproc + 126 @ Volatile: function does not return. + 127 @ args = 0, pretend = 0, frame = 0 + 128 @ frame_needed = 0, uses_anonymous_args = 0 + 129 0000 08B5 push {r3, lr} + 130 .LCFI3: + 131 .cfi_def_cfa_offset 8 + 132 .cfi_offset 3, -8 + 133 .cfi_offset 14, -4 + 134 .loc 1 29 0 + 135 0002 0248 ldr r0, .L16 + 136 0004 FFF7FEFF bl print + 137 .LVL3: + 138 .L15: + 139 0008 FEE7 b .L15 + 140 .L17: + 141 000a 00BF .align 2 + 142 .L16: + 143 000c 18000000 .word .LC3 + 144 .cfi_endproc + 145 .LFE65: + 146 .size UsageFaultVector, .-UsageFaultVector + 147 .section .text.HardFaultVector,"ax",%progbits + 148 .align 2 + 149 .p2align 4,,15 + 150 .global HardFaultVector + 151 .thumb + 152 .thumb_func + 153 .type HardFaultVector, %function + 154 HardFaultVector: + 155 .LFB66: + 156 .loc 1 30 0 + 157 .cfi_startproc + 158 @ args = 0, pretend = 0, frame = 0 + 159 @ frame_needed = 0, uses_anonymous_args = 0 + 160 @ link register save eliminated. + 161 0000 7047 bx lr + 162 .cfi_endproc + 163 .LFE66: + 164 .size HardFaultVector, .-HardFaultVector + 165 0002 00BFAFF3 .section .text.VectorD4,"ax",%progbits + 165 0080AFF3 + 165 0080AFF3 + 165 0080 + 166 .align 2 + 167 .p2align 4,,15 + 168 .global VectorD4 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 4 + + + 169 .thumb + 170 .thumb_func + 171 .type VectorD4, %function + 172 VectorD4: + 173 .LFB67: + 174 .loc 1 77 0 + 175 .cfi_startproc + 176 @ args = 0, pretend = 0, frame = 0 + 177 @ frame_needed = 0, uses_anonymous_args = 0 + 178 .loc 1 77 0 + 179 0000 08B5 push {r3, lr} + 180 .LCFI4: + 181 .cfi_def_cfa_offset 8 + 182 .cfi_offset 3, -8 + 183 .cfi_offset 14, -4 + 184 .loc 1 80 0 + 185 0002 FFF7FEFF bl libwismart_UART_IRQHandler + 186 .LVL4: + 187 .loc 1 83 0 + 188 0006 BDE80840 pop {r3, lr} + 189 .loc 1 82 0 + 190 000a FFF7FEBF b _port_irq_epilogue + 191 .LVL5: + 192 .cfi_endproc + 193 .LFE67: + 194 .size VectorD4, .-VectorD4 + 195 000e 00BF .section .text.Vector58,"ax",%progbits + 196 .align 2 + 197 .p2align 4,,15 + 198 .global Vector58 + 199 .thumb + 200 .thumb_func + 201 .type Vector58, %function + 202 Vector58: + 203 .LFB68: + 204 .loc 1 87 0 + 205 .cfi_startproc + 206 @ args = 0, pretend = 0, frame = 0 + 207 @ frame_needed = 0, uses_anonymous_args = 0 + 208 0000 08B5 push {r3, lr} + 209 .LCFI5: + 210 .cfi_def_cfa_offset 8 + 211 .cfi_offset 3, -8 + 212 .cfi_offset 14, -4 + 213 .loc 1 90 0 + 214 0002 FFF7FEFF bl libwismart_WiFi_IRQHandler + 215 .LVL6: + 216 .loc 1 93 0 + 217 0006 BDE80840 pop {r3, lr} + 218 .loc 1 92 0 + 219 000a FFF7FEBF b _port_irq_epilogue + 220 .LVL7: + 221 .cfi_endproc + 222 .LFE68: + 223 .size Vector58, .-Vector58 + 224 000e 00BF .section .text.Vector78,"ax",%progbits + 225 .align 2 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 5 + + + 226 .p2align 4,,15 + 227 .global Vector78 + 228 .thumb + 229 .thumb_func + 230 .type Vector78, %function + 231 Vector78: + 232 .LFB69: + 233 .loc 1 97 0 + 234 .cfi_startproc + 235 @ args = 0, pretend = 0, frame = 0 + 236 @ frame_needed = 0, uses_anonymous_args = 0 + 237 0000 08B5 push {r3, lr} + 238 .LCFI6: + 239 .cfi_def_cfa_offset 8 + 240 .cfi_offset 3, -8 + 241 .cfi_offset 14, -4 + 242 .loc 1 100 0 + 243 0002 FFF7FEFF bl libwismart_UART_TXDMA_IRQHandler + 244 .LVL8: + 245 .loc 1 103 0 + 246 0006 BDE80840 pop {r3, lr} + 247 .loc 1 102 0 + 248 000a FFF7FEBF b _port_irq_epilogue + 249 .LVL9: + 250 .cfi_endproc + 251 .LFE69: + 252 .size Vector78, .-Vector78 + 253 000e 00BF .section .text.Vector7C,"ax",%progbits + 254 .align 2 + 255 .p2align 4,,15 + 256 .global Vector7C + 257 .thumb + 258 .thumb_func + 259 .type Vector7C, %function + 260 Vector7C: + 261 .LFB70: + 262 .loc 1 108 0 + 263 .cfi_startproc + 264 @ args = 0, pretend = 0, frame = 0 + 265 @ frame_needed = 0, uses_anonymous_args = 0 + 266 0000 08B5 push {r3, lr} + 267 .LCFI7: + 268 .cfi_def_cfa_offset 8 + 269 .cfi_offset 3, -8 + 270 .cfi_offset 14, -4 + 271 .loc 1 111 0 + 272 0002 FFF7FEFF bl libwismart_UART_RXDMA_IRQHandler + 273 .LVL10: + 274 .loc 1 114 0 + 275 0006 BDE80840 pop {r3, lr} + 276 .loc 1 113 0 + 277 000a FFF7FEBF b _port_irq_epilogue + 278 .LVL11: + 279 .cfi_endproc + 280 .LFE70: + 281 .size Vector7C, .-Vector7C + 282 000e 00BF .section .text.initLibwismart,"ax",%progbits + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 6 + + + 283 .align 2 + 284 .p2align 4,,15 + 285 .global initLibwismart + 286 .thumb + 287 .thumb_func + 288 .type initLibwismart, %function + 289 initLibwismart: + 290 .LFB71: + 291 .file 2 "main.c" + 292 .loc 2 33 0 + 293 .cfi_startproc + 294 @ args = 0, pretend = 0, frame = 464 + 295 @ frame_needed = 0, uses_anonymous_args = 0 + 296 0000 10B5 push {r4, lr} + 297 .LCFI8: + 298 .cfi_def_cfa_offset 8 + 299 .cfi_offset 4, -8 + 300 .cfi_offset 14, -4 + 301 0002 ADF5647D sub sp, sp, #912 + 302 .LCFI9: + 303 .cfi_def_cfa_offset 920 + 304 .loc 2 38 0 + 305 0006 71AC add r4, sp, #452 + 306 0008 2046 mov r0, r4 + 307 000a FFF7FEFF bl libwismart_GetDefaultHWIF + 308 .LVL12: + 309 .loc 2 54 0 + 310 000e 75A9 add r1, sp, #468 + 311 0010 6846 mov r0, sp + 312 0012 4FF4DE72 mov r2, #444 + 313 0016 FFF7FEFF bl memcpy + 314 .LVL13: + 315 001a 94E80F00 ldmia r4, {r0, r1, r2, r3} + 316 001e FFF7FEFF bl libwismart_Init + 317 .LVL14: + 318 .loc 2 55 0 + 319 0022 0DF5647D add sp, sp, #912 + 320 0026 10BD pop {r4, pc} + 321 .cfi_endproc + 322 .LFE71: + 323 .size initLibwismart, .-initLibwismart + 324 0028 AFF30080 .section .text.startup.main,"ax",%progbits + 324 AFF30080 + 325 .align 2 + 326 .p2align 4,,15 + 327 .global main + 328 .thumb + 329 .thumb_func + 330 .type main, %function + 331 main: + 332 .LFB72: + 333 .loc 2 64 0 + 334 .cfi_startproc + 335 @ Volatile: function does not return. + 336 @ args = 0, pretend = 0, frame = 0 + 337 @ frame_needed = 0, uses_anonymous_args = 0 + 338 0000 08B5 push {r3, lr} + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 7 + + + 339 .LCFI10: + 340 .cfi_def_cfa_offset 8 + 341 .cfi_offset 3, -8 + 342 .cfi_offset 14, -4 + 343 .loc 2 69 0 + 344 0002 FFF7FEFF bl initLibwismart + 345 .LVL15: + 346 .loc 2 74 0 + 347 0006 FFF7FEFF bl libwismart_PowerSave_Enable + 348 .LVL16: + 349 .loc 2 75 0 + 350 000a 0120 movs r0, #1 + 351 000c FFF7FEFF bl libwismart_PowerSave_HigherProfile + 352 .LVL17: + 353 .loc 2 80 0 + 354 0010 FFF7FEFF bl buttons_init + 355 .LVL18: + 356 .L25: + 357 .loc 2 87 0 discriminator 1 + 358 0014 FFF7FEFF bl buttons_process + 359 .LVL19: + 360 .loc 2 90 0 discriminator 1 + 361 0018 4FF4FA70 mov r0, #500 + 362 001c FFF7FEFF bl chThdSleep + 363 .LVL20: + 364 0020 F8E7 b .L25 + 365 .cfi_endproc + 366 .LFE72: + 367 .size main, .-main + 368 0022 00BFAFF3 .section .rodata.str1.4,"aMS",%progbits,1 + 368 0080AFF3 + 368 0080AFF3 + 368 0080 + 369 .align 2 + 370 .LC0: + 371 0000 4E4D4900 .ascii "NMI\000" + 372 .LC1: + 373 0004 6D656D21 .ascii "mem!\000" + 373 00 + 374 0009 000000 .space 3 + 375 .LC2: + 376 000c 62757320 .ascii "bus fault!\000" + 376 6661756C + 376 742100 + 377 0017 00 .space 1 + 378 .LC3: + 379 0018 75736167 .ascii "usage fault!\000" + 379 65206661 + 379 756C7421 + 379 00 + 380 0025 000000 .text + 381 .Letext0: + 382 .file 3 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 383 .file 4 "../..//os/ports/GCC/ARMCMx/chtypes.h" + 384 .file 5 "../..//econais/libwismart.h" + 385 .file 6 "../..//os/ports/GCC/ARMCMx/chcore_v7m.h" + 386 .file 7 "buttonExample.h" + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 8 + + + 387 .file 8 "../..//os/ports/common/ARMCMx/CMSIS/include/core_cm3.h" + 388 .file 9 "../..//os/kernel/include/chthreads.h" + 389 .section .debug_info,"",%progbits + 390 .Ldebug_info0: + 391 0000 67070000 .4byte 0x767 + 392 0004 0200 .2byte 0x2 + 393 0006 00000000 .4byte .Ldebug_abbrev0 + 394 000a 04 .byte 0x4 + 395 000b 01 .uleb128 0x1 + 396 000c E8020000 .4byte .LASF87 + 397 0010 01 .byte 0x1 + 398 0011 C0030000 .4byte .LASF88 + 399 0015 EE000000 .4byte .LASF89 + 400 0019 00000000 .4byte .Ldebug_ranges0+0 + 401 001d 00000000 .4byte 0 + 402 0021 00000000 .4byte 0 + 403 0025 00000000 .4byte .Ldebug_line0 + 404 0029 02 .uleb128 0x2 + 405 002a 04 .byte 0x4 + 406 002b 05 .byte 0x5 + 407 002c 696E7400 .ascii "int\000" + 408 0030 03 .uleb128 0x3 + 409 0031 04 .byte 0x4 + 410 0032 07 .byte 0x7 + 411 0033 D1040000 .4byte .LASF0 + 412 0037 03 .uleb128 0x3 + 413 0038 01 .byte 0x1 + 414 0039 06 .byte 0x6 + 415 003a 9A020000 .4byte .LASF1 + 416 003e 04 .uleb128 0x4 + 417 003f 40010000 .4byte .LASF4 + 418 0043 03 .byte 0x3 + 419 0044 2A .byte 0x2a + 420 0045 49000000 .4byte 0x49 + 421 0049 03 .uleb128 0x3 + 422 004a 01 .byte 0x1 + 423 004b 08 .byte 0x8 + 424 004c 60020000 .4byte .LASF2 + 425 0050 03 .uleb128 0x3 + 426 0051 02 .byte 0x2 + 427 0052 05 .byte 0x5 + 428 0053 85000000 .4byte .LASF3 + 429 0057 04 .uleb128 0x4 + 430 0058 DF020000 .4byte .LASF5 + 431 005c 03 .byte 0x3 + 432 005d 36 .byte 0x36 + 433 005e 62000000 .4byte 0x62 + 434 0062 03 .uleb128 0x3 + 435 0063 02 .byte 0x2 + 436 0064 07 .byte 0x7 + 437 0065 1E030000 .4byte .LASF6 + 438 0069 04 .uleb128 0x4 + 439 006a 7F030000 .4byte .LASF7 + 440 006e 03 .byte 0x3 + 441 006f 4F .byte 0x4f + 442 0070 74000000 .4byte 0x74 + 443 0074 03 .uleb128 0x3 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 9 + + + 444 0075 04 .byte 0x4 + 445 0076 05 .byte 0x5 + 446 0077 CD010000 .4byte .LASF8 + 447 007b 04 .uleb128 0x4 + 448 007c CD020000 .4byte .LASF9 + 449 0080 03 .byte 0x3 + 450 0081 50 .byte 0x50 + 451 0082 86000000 .4byte 0x86 + 452 0086 03 .uleb128 0x3 + 453 0087 04 .byte 0x4 + 454 0088 07 .byte 0x7 + 455 0089 C7030000 .4byte .LASF10 + 456 008d 03 .uleb128 0x3 + 457 008e 08 .byte 0x8 + 458 008f 05 .byte 0x5 + 459 0090 7D010000 .4byte .LASF11 + 460 0094 03 .uleb128 0x3 + 461 0095 08 .byte 0x8 + 462 0096 07 .byte 0x7 + 463 0097 B0020000 .4byte .LASF12 + 464 009b 04 .uleb128 0x4 + 465 009c 3B030000 .4byte .LASF13 + 466 00a0 04 .byte 0x4 + 467 00a1 36 .byte 0x36 + 468 00a2 7B000000 .4byte 0x7b + 469 00a6 05 .uleb128 0x5 + 470 00a7 04 .byte 0x4 + 471 00a8 03 .uleb128 0x3 + 472 00a9 04 .byte 0x4 + 473 00aa 07 .byte 0x7 + 474 00ab 94000000 .4byte .LASF14 + 475 00af 06 .uleb128 0x6 + 476 00b0 04 .byte 0x4 + 477 00b1 B5000000 .4byte 0xb5 + 478 00b5 07 .uleb128 0x7 + 479 00b6 BA000000 .4byte 0xba + 480 00ba 03 .uleb128 0x3 + 481 00bb 01 .byte 0x1 + 482 00bc 08 .byte 0x8 + 483 00bd 59030000 .4byte .LASF15 + 484 00c1 08 .uleb128 0x8 + 485 00c2 10 .byte 0x10 + 486 00c3 05 .byte 0x5 + 487 00c4 50 .byte 0x50 + 488 00c5 10010000 .4byte 0x110 + 489 00c9 09 .uleb128 0x9 + 490 00ca BB030000 .4byte .LASF16 + 491 00ce 05 .byte 0x5 + 492 00cf 51 .byte 0x51 + 493 00d0 A6000000 .4byte 0xa6 + 494 00d4 02 .byte 0x2 + 495 00d5 23 .byte 0x23 + 496 00d6 00 .uleb128 0 + 497 00d7 0A .uleb128 0xa + 498 00d8 61686200 .ascii "ahb\000" + 499 00dc 05 .byte 0x5 + 500 00dd 52 .byte 0x52 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 10 + + + 501 00de 7B000000 .4byte 0x7b + 502 00e2 02 .byte 0x2 + 503 00e3 23 .byte 0x23 + 504 00e4 04 .uleb128 0x4 + 505 00e5 0A .uleb128 0xa + 506 00e6 70696E00 .ascii "pin\000" + 507 00ea 05 .byte 0x5 + 508 00eb 53 .byte 0x53 + 509 00ec 57000000 .4byte 0x57 + 510 00f0 02 .byte 0x2 + 511 00f1 23 .byte 0x23 + 512 00f2 08 .uleb128 0x8 + 513 00f3 09 .uleb128 0x9 + 514 00f4 1B020000 .4byte .LASF17 + 515 00f8 05 .byte 0x5 + 516 00f9 54 .byte 0x54 + 517 00fa 3E000000 .4byte 0x3e + 518 00fe 02 .byte 0x2 + 519 00ff 23 .byte 0x23 + 520 0100 0A .uleb128 0xa + 521 0101 09 .uleb128 0x9 + 522 0102 22020000 .4byte .LASF18 + 523 0106 05 .byte 0x5 + 524 0107 55 .byte 0x55 + 525 0108 7B000000 .4byte 0x7b + 526 010c 02 .byte 0x2 + 527 010d 23 .byte 0x23 + 528 010e 0C .uleb128 0xc + 529 010f 00 .byte 0 + 530 0110 04 .uleb128 0x4 + 531 0111 9D000000 .4byte .LASF19 + 532 0115 05 .byte 0x5 + 533 0116 56 .byte 0x56 + 534 0117 C1000000 .4byte 0xc1 + 535 011b 08 .uleb128 0x8 + 536 011c 3C .byte 0x3c + 537 011d 05 .byte 0x5 + 538 011e 58 .byte 0x58 + 539 011f 86010000 .4byte 0x186 + 540 0123 09 .uleb128 0x9 + 541 0124 48010000 .4byte .LASF20 + 542 0128 05 .byte 0x5 + 543 0129 5A .byte 0x5a + 544 012a 10010000 .4byte 0x110 + 545 012e 02 .byte 0x2 + 546 012f 23 .byte 0x23 + 547 0130 00 .uleb128 0 + 548 0131 09 .uleb128 0x9 + 549 0132 4B000000 .4byte .LASF21 + 550 0136 05 .byte 0x5 + 551 0137 5C .byte 0x5c + 552 0138 3E000000 .4byte 0x3e + 553 013c 02 .byte 0x2 + 554 013d 23 .byte 0x23 + 555 013e 10 .uleb128 0x10 + 556 013f 09 .uleb128 0x9 + 557 0140 2F020000 .4byte .LASF22 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 11 + + + 558 0144 05 .byte 0x5 + 559 0145 5D .byte 0x5d + 560 0146 3E000000 .4byte 0x3e + 561 014a 02 .byte 0x2 + 562 014b 23 .byte 0x23 + 563 014c 11 .uleb128 0x11 + 564 014d 09 .uleb128 0x9 + 565 014e 9B040000 .4byte .LASF23 + 566 0152 05 .byte 0x5 + 567 0153 5E .byte 0x5e + 568 0154 7B000000 .4byte 0x7b + 569 0158 02 .byte 0x2 + 570 0159 23 .byte 0x23 + 571 015a 14 .uleb128 0x14 + 572 015b 09 .uleb128 0x9 + 573 015c C8000000 .4byte .LASF24 + 574 0160 05 .byte 0x5 + 575 0161 5F .byte 0x5f + 576 0162 3E000000 .4byte 0x3e + 577 0166 02 .byte 0x2 + 578 0167 23 .byte 0x23 + 579 0168 18 .uleb128 0x18 + 580 0169 09 .uleb128 0x9 + 581 016a 96030000 .4byte .LASF25 + 582 016e 05 .byte 0x5 + 583 016f 62 .byte 0x62 + 584 0170 10010000 .4byte 0x110 + 585 0174 02 .byte 0x2 + 586 0175 23 .byte 0x23 + 587 0176 1C .uleb128 0x1c + 588 0177 09 .uleb128 0x9 + 589 0178 A6020000 .4byte .LASF26 + 590 017c 05 .byte 0x5 + 591 017d 65 .byte 0x65 + 592 017e 10010000 .4byte 0x110 + 593 0182 02 .byte 0x2 + 594 0183 23 .byte 0x23 + 595 0184 2C .uleb128 0x2c + 596 0185 00 .byte 0 + 597 0186 04 .uleb128 0x4 + 598 0187 45030000 .4byte .LASF27 + 599 018b 05 .byte 0x5 + 600 018c 66 .byte 0x66 + 601 018d 1B010000 .4byte 0x11b + 602 0191 08 .uleb128 0x8 + 603 0192 10 .byte 0x10 + 604 0193 05 .byte 0x5 + 605 0194 68 .byte 0x68 + 606 0195 D2010000 .4byte 0x1d2 + 607 0199 09 .uleb128 0x9 + 608 019a 5C000000 .4byte .LASF28 + 609 019e 05 .byte 0x5 + 610 019f 69 .byte 0x69 + 611 01a0 3E000000 .4byte 0x3e + 612 01a4 02 .byte 0x2 + 613 01a5 23 .byte 0x23 + 614 01a6 00 .uleb128 0 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 12 + + + 615 01a7 09 .uleb128 0x9 + 616 01a8 8E030000 .4byte .LASF29 + 617 01ac 05 .byte 0x5 + 618 01ad 6A .byte 0x6a + 619 01ae A6000000 .4byte 0xa6 + 620 01b2 02 .byte 0x2 + 621 01b3 23 .byte 0x23 + 622 01b4 04 .uleb128 0x4 + 623 01b5 0A .uleb128 0xa + 624 01b6 69727100 .ascii "irq\000" + 625 01ba 05 .byte 0x5 + 626 01bb 6B .byte 0x6b + 627 01bc 3E000000 .4byte 0x3e + 628 01c0 02 .byte 0x2 + 629 01c1 23 .byte 0x23 + 630 01c2 08 .uleb128 0x8 + 631 01c3 09 .uleb128 0x9 + 632 01c4 0B050000 .4byte .LASF30 + 633 01c8 05 .byte 0x5 + 634 01c9 6C .byte 0x6c + 635 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0x1 + 1087 051c A9060000 .4byte 0x6a9 + 1088 0520 00 .byte 0 + 1089 0521 11 .uleb128 0x11 + 1090 0522 01 .byte 0x1 + 1091 0523 30050000 .4byte .LASF72 + 1092 0527 01 .byte 0x1 + 1093 0528 56 .byte 0x56 + 1094 0529 01 .byte 0x1 + 1095 052a 00000000 .4byte .LFB68 + 1096 052e 0E000000 .4byte .LFE68 + 1097 0532 A0000000 .4byte .LLST5 + 1098 0536 01 .byte 0x1 + 1099 0537 4F050000 .4byte 0x54f + 1100 053b 15 .uleb128 0x15 + 1101 053c 06000000 .4byte .LVL6 + 1102 0540 B4060000 .4byte 0x6b4 + 1103 0544 16 .uleb128 0x16 + 1104 0545 0E000000 .4byte .LVL7 + 1105 0549 01 .byte 0x1 + 1106 054a A9060000 .4byte 0x6a9 + 1107 054e 00 .byte 0 + 1108 054f 11 .uleb128 0x11 + 1109 0550 01 .byte 0x1 + 1110 0551 7F020000 .4byte .LASF73 + 1111 0555 01 .byte 0x1 + 1112 0556 60 .byte 0x60 + 1113 0557 01 .byte 0x1 + 1114 0558 00000000 .4byte .LFB69 + 1115 055c 0E000000 .4byte .LFE69 + 1116 0560 C0000000 .4byte .LLST6 + 1117 0564 01 .byte 0x1 + 1118 0565 7D050000 .4byte 0x57d + 1119 0569 15 .uleb128 0x15 + 1120 056a 06000000 .4byte .LVL8 + 1121 056e BF060000 .4byte 0x6bf + 1122 0572 16 .uleb128 0x16 + 1123 0573 0E000000 .4byte .LVL9 + 1124 0577 01 .byte 0x1 + 1125 0578 A9060000 .4byte 0x6a9 + 1126 057c 00 .byte 0 + 1127 057d 11 .uleb128 0x11 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 21 + + + 1128 057e 01 .byte 0x1 + 1129 057f D6020000 .4byte .LASF74 + 1130 0583 01 .byte 0x1 + 1131 0584 6B .byte 0x6b + 1132 0585 01 .byte 0x1 + 1133 0586 00000000 .4byte .LFB70 + 1134 058a 0E000000 .4byte .LFE70 + 1135 058e E0000000 .4byte .LLST7 + 1136 0592 01 .byte 0x1 + 1137 0593 AB050000 .4byte 0x5ab + 1138 0597 15 .uleb128 0x15 + 1139 0598 06000000 .4byte .LVL10 + 1140 059c CA060000 .4byte 0x6ca + 1141 05a0 16 .uleb128 0x16 + 1142 05a1 0E000000 .4byte .LVL11 + 1143 05a5 01 .byte 0x1 + 1144 05a6 A9060000 .4byte 0x6a9 + 1145 05aa 00 .byte 0 + 1146 05ab 11 .uleb128 0x11 + 1147 05ac 01 .byte 0x1 + 1148 05ad 0F030000 .4byte .LASF75 + 1149 05b1 02 .byte 0x2 + 1150 05b2 21 .byte 0x21 + 1151 05b3 01 .byte 0x1 + 1152 05b4 00000000 .4byte .LFB71 + 1153 05b8 28000000 .4byte .LFE71 + 1154 05bc 00010000 .4byte .LLST8 + 1155 05c0 01 .byte 0x1 + 1156 05c1 14060000 .4byte 0x614 + 1157 05c5 17 .uleb128 0x17 + 1158 05c6 5F010000 .4byte .LASF91 + 1159 05ca 02 .byte 0x2 + 1160 05cb 26 .byte 0x26 + 1161 05cc 16040000 .4byte 0x416 + 1162 05d0 03 .byte 0x3 + 1163 05d1 91 .byte 0x91 + 1164 05d2 AC7C .sleb128 -468 + 1165 05d4 18 .uleb128 0x18 + 1166 05d5 0E000000 .4byte .LVL12 + 1167 05d9 D5060000 .4byte 0x6d5 + 1168 05dd E8050000 .4byte 0x5e8 + 1169 05e1 13 .uleb128 0x13 + 1170 05e2 01 .byte 0x1 + 1171 05e3 50 .byte 0x50 + 1172 05e4 02 .byte 0x2 + 1173 05e5 74 .byte 0x74 + 1174 05e6 00 .sleb128 0 + 1175 05e7 00 .byte 0 + 1176 05e8 18 .uleb128 0x18 + 1177 05e9 1A000000 .4byte .LVL13 + 1178 05ed E4060000 .4byte 0x6e4 + 1179 05f1 0A060000 .4byte 0x60a + 1180 05f5 13 .uleb128 0x13 + 1181 05f6 01 .byte 0x1 + 1182 05f7 52 .byte 0x52 + 1183 05f8 03 .byte 0x3 + 1184 05f9 0A .byte 0xa + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 22 + + + 1185 05fa BC01 .2byte 0x1bc + 1186 05fc 13 .uleb128 0x13 + 1187 05fd 01 .byte 0x1 + 1188 05fe 51 .byte 0x51 + 1189 05ff 03 .byte 0x3 + 1190 0600 91 .byte 0x91 + 1191 0601 BC7C .sleb128 -452 + 1192 0603 13 .uleb128 0x13 + 1193 0604 01 .byte 0x1 + 1194 0605 50 .byte 0x50 + 1195 0606 02 .byte 0x2 + 1196 0607 7D .byte 0x7d + 1197 0608 00 .sleb128 0 + 1198 0609 00 .byte 0 + 1199 060a 15 .uleb128 0x15 + 1200 060b 22000000 .4byte .LVL14 + 1201 060f 0C070000 .4byte 0x70c + 1202 0613 00 .byte 0 + 1203 0614 19 .uleb128 0x19 + 1204 0615 01 .byte 0x1 + 1205 0616 BC000000 .4byte .LASF92 + 1206 061a 02 .byte 0x2 + 1207 061b 40 .byte 0x40 + 1208 061c 01 .byte 0x1 + 1209 061d 29000000 .4byte 0x29 + 1210 0621 00000000 .4byte .LFB72 + 1211 0625 22000000 .4byte .LFE72 + 1212 0629 2D010000 .4byte .LLST9 + 1213 062d 01 .byte 0x1 + 1214 062e 7B060000 .4byte 0x67b + 1215 0632 15 .uleb128 0x15 + 1216 0633 06000000 .4byte .LVL15 + 1217 0637 AB050000 .4byte 0x5ab + 1218 063b 15 .uleb128 0x15 + 1219 063c 0A000000 .4byte .LVL16 + 1220 0640 25070000 .4byte 0x725 + 1221 0644 18 .uleb128 0x18 + 1222 0645 10000000 .4byte .LVL17 + 1223 0649 30070000 .4byte 0x730 + 1224 064d 57060000 .4byte 0x657 + 1225 0651 13 .uleb128 0x13 + 1226 0652 01 .byte 0x1 + 1227 0653 50 .byte 0x50 + 1228 0654 01 .byte 0x1 + 1229 0655 31 .byte 0x31 + 1230 0656 00 .byte 0 + 1231 0657 15 .uleb128 0x15 + 1232 0658 14000000 .4byte .LVL18 + 1233 065c 45070000 .4byte 0x745 + 1234 0660 15 .uleb128 0x15 + 1235 0661 18000000 .4byte .LVL19 + 1236 0665 4F070000 .4byte 0x74f + 1237 0669 12 .uleb128 0x12 + 1238 066a 20000000 .4byte .LVL20 + 1239 066e 59070000 .4byte 0x759 + 1240 0672 13 .uleb128 0x13 + 1241 0673 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 23 + + + 1242 0674 50 .byte 0x50 + 1243 0675 03 .byte 0x3 + 1244 0676 0A .byte 0xa + 1245 0677 F401 .2byte 0x1f4 + 1246 0679 00 .byte 0 + 1247 067a 00 .byte 0 + 1248 067b 1A .uleb128 0x1a + 1249 067c AC040000 .4byte .LASF93 + 1250 0680 08 .byte 0x8 + 1251 0681 9404 .2byte 0x494 + 1252 0683 21040000 .4byte 0x421 + 1253 0687 01 .byte 0x1 + 1254 0688 01 .byte 0x1 + 1255 0689 1B .uleb128 0x1b + 1256 068a 01 .byte 0x1 + 1257 068b C7020000 .4byte .LASF81 + 1258 068f 05 .byte 0x5 + 1259 0690 45 .byte 0x45 + 1260 0691 01 .byte 0x1 + 1261 0692 01 .byte 0x1 + 1262 0693 9E060000 .4byte 0x69e + 1263 0697 1C .uleb128 0x1c + 1264 0698 AF000000 .4byte 0xaf + 1265 069c 1D .uleb128 0x1d + 1266 069d 00 .byte 0 + 1267 069e 1E .uleb128 0x1e + 1268 069f 01 .byte 0x1 + 1269 06a0 56040000 .4byte .LASF76 + 1270 06a4 05 .byte 0x5 + 1271 06a5 F905 .2byte 0x5f9 + 1272 06a7 01 .byte 0x1 + 1273 06a8 01 .byte 0x1 + 1274 06a9 1E .uleb128 0x1e + 1275 06aa 01 .byte 0x1 + 1276 06ab 4D020000 .4byte .LASF77 + 1277 06af 06 .byte 0x6 + 1278 06b0 F501 .2byte 0x1f5 + 1279 06b2 01 .byte 0x1 + 1280 06b3 01 .byte 0x1 + 1281 06b4 1E .uleb128 0x1e + 1282 06b5 01 .byte 0x1 + 1283 06b6 A0030000 .4byte .LASF78 + 1284 06ba 05 .byte 0x5 + 1285 06bb F105 .2byte 0x5f1 + 1286 06bd 01 .byte 0x1 + 1287 06be 01 .byte 0x1 + 1288 06bf 1E .uleb128 0x1e + 1289 06c0 01 .byte 0x1 + 1290 06c1 5E030000 .4byte .LASF79 + 1291 06c5 05 .byte 0x5 + 1292 06c6 0006 .2byte 0x600 + 1293 06c8 01 .byte 0x1 + 1294 06c9 01 .byte 0x1 + 1295 06ca 1E .uleb128 0x1e + 1296 06cb 01 .byte 0x1 + 1297 06cc 71040000 .4byte .LASF80 + 1298 06d0 05 .byte 0x5 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 24 + + + 1299 06d1 0706 .2byte 0x607 + 1300 06d3 01 .byte 0x1 + 1301 06d4 01 .byte 0x1 + 1302 06d5 1F .uleb128 0x1f + 1303 06d6 01 .byte 0x1 + 1304 06d7 24040000 .4byte .LASF94 + 1305 06db 05 .byte 0x5 + 1306 06dc 2401 .2byte 0x124 + 1307 06de 01 .byte 0x1 + 1308 06df 16040000 .4byte 0x416 + 1309 06e3 01 .byte 0x1 + 1310 06e4 20 .uleb128 0x20 + 1311 06e5 01 .byte 0x1 + 1312 06e6 C1000000 .4byte .LASF82 + 1313 06ea 01 .byte 0x1 + 1314 06eb A6000000 .4byte 0xa6 + 1315 06ef 01 .byte 0x1 + 1316 06f0 01 .byte 0x1 + 1317 06f1 05070000 .4byte 0x705 + 1318 06f5 1C .uleb128 0x1c + 1319 06f6 A6000000 .4byte 0xa6 + 1320 06fa 1C .uleb128 0x1c + 1321 06fb 05070000 .4byte 0x705 + 1322 06ff 1C .uleb128 0x1c + 1323 0700 A8000000 .4byte 0xa8 + 1324 0704 00 .byte 0 + 1325 0705 06 .uleb128 0x6 + 1326 0706 04 .byte 0x4 + 1327 0707 0B070000 .4byte 0x70b + 1328 070b 21 .uleb128 0x21 + 1329 070c 22 .uleb128 0x22 + 1330 070d 01 .byte 0x1 + 1331 070e F4020000 .4byte .LASF95 + 1332 0712 05 .byte 0x5 + 1333 0713 3101 .2byte 0x131 + 1334 0715 01 .byte 0x1 + 1335 0716 29000000 .4byte 0x29 + 1336 071a 01 .byte 0x1 + 1337 071b 25070000 .4byte 0x725 + 1338 071f 1C .uleb128 0x1c + 1339 0720 16040000 .4byte 0x416 + 1340 0724 00 .byte 0 + 1341 0725 1E .uleb128 0x1e + 1342 0726 01 .byte 0x1 + 1343 0727 B1010000 .4byte .LASF83 + 1344 072b 05 .byte 0x5 + 1345 072c 0B04 .2byte 0x40b + 1346 072e 01 .byte 0x1 + 1347 072f 01 .byte 0x1 + 1348 0730 23 .uleb128 0x23 + 1349 0731 01 .byte 0x1 + 1350 0732 D6010000 .4byte .LASF84 + 1351 0736 05 .byte 0x5 + 1352 0737 6D04 .2byte 0x46d + 1353 0739 01 .byte 0x1 + 1354 073a 01 .byte 0x1 + 1355 073b 45070000 .4byte 0x745 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 25 + + + 1356 073f 1C .uleb128 0x1c + 1357 0740 3E000000 .4byte 0x3e + 1358 0744 00 .byte 0 + 1359 0745 24 .uleb128 0x24 + 1360 0746 01 .byte 0x1 + 1361 0747 64010000 .4byte .LASF85 + 1362 074b 07 .byte 0x7 + 1363 074c 25 .byte 0x25 + 1364 074d 01 .byte 0x1 + 1365 074e 01 .byte 0x1 + 1366 074f 24 .uleb128 0x24 + 1367 0750 01 .byte 0x1 + 1368 0751 39050000 .4byte .LASF86 + 1369 0755 07 .byte 0x7 + 1370 0756 26 .byte 0x26 + 1371 0757 01 .byte 0x1 + 1372 0758 01 .byte 0x1 + 1373 0759 25 .uleb128 0x25 + 1374 075a 01 .byte 0x1 + 1375 075b B1000000 .4byte .LASF96 + 1376 075f 09 .byte 0x9 + 1377 0760 6901 .2byte 0x169 + 1378 0762 01 .byte 0x1 + 1379 0763 01 .byte 0x1 + 1380 0764 1C .uleb128 0x1c + 1381 0765 9B000000 .4byte 0x9b + 1382 0769 00 .byte 0 + 1383 076a 00 .byte 0 + 1384 .section .debug_abbrev,"",%progbits + 1385 .Ldebug_abbrev0: + 1386 0000 01 .uleb128 0x1 + 1387 0001 11 .uleb128 0x11 + 1388 0002 01 .byte 0x1 + 1389 0003 25 .uleb128 0x25 + 1390 0004 0E .uleb128 0xe + 1391 0005 13 .uleb128 0x13 + 1392 0006 0B .uleb128 0xb + 1393 0007 03 .uleb128 0x3 + 1394 0008 0E .uleb128 0xe + 1395 0009 1B .uleb128 0x1b + 1396 000a 0E .uleb128 0xe + 1397 000b 55 .uleb128 0x55 + 1398 000c 06 .uleb128 0x6 + 1399 000d 11 .uleb128 0x11 + 1400 000e 01 .uleb128 0x1 + 1401 000f 52 .uleb128 0x52 + 1402 0010 01 .uleb128 0x1 + 1403 0011 10 .uleb128 0x10 + 1404 0012 06 .uleb128 0x6 + 1405 0013 00 .byte 0 + 1406 0014 00 .byte 0 + 1407 0015 02 .uleb128 0x2 + 1408 0016 24 .uleb128 0x24 + 1409 0017 00 .byte 0 + 1410 0018 0B .uleb128 0xb + 1411 0019 0B .uleb128 0xb + 1412 001a 3E .uleb128 0x3e + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 26 + + + 1413 001b 0B .uleb128 0xb + 1414 001c 03 .uleb128 0x3 + 1415 001d 08 .uleb128 0x8 + 1416 001e 00 .byte 0 + 1417 001f 00 .byte 0 + 1418 0020 03 .uleb128 0x3 + 1419 0021 24 .uleb128 0x24 + 1420 0022 00 .byte 0 + 1421 0023 0B .uleb128 0xb + 1422 0024 0B .uleb128 0xb + 1423 0025 3E .uleb128 0x3e + 1424 0026 0B .uleb128 0xb + 1425 0027 03 .uleb128 0x3 + 1426 0028 0E .uleb128 0xe + 1427 0029 00 .byte 0 + 1428 002a 00 .byte 0 + 1429 002b 04 .uleb128 0x4 + 1430 002c 16 .uleb128 0x16 + 1431 002d 00 .byte 0 + 1432 002e 03 .uleb128 0x3 + 1433 002f 0E .uleb128 0xe + 1434 0030 3A .uleb128 0x3a + 1435 0031 0B .uleb128 0xb + 1436 0032 3B .uleb128 0x3b + 1437 0033 0B .uleb128 0xb + 1438 0034 49 .uleb128 0x49 + 1439 0035 13 .uleb128 0x13 + 1440 0036 00 .byte 0 + 1441 0037 00 .byte 0 + 1442 0038 05 .uleb128 0x5 + 1443 0039 0F .uleb128 0xf + 1444 003a 00 .byte 0 + 1445 003b 0B .uleb128 0xb + 1446 003c 0B .uleb128 0xb + 1447 003d 00 .byte 0 + 1448 003e 00 .byte 0 + 1449 003f 06 .uleb128 0x6 + 1450 0040 0F .uleb128 0xf + 1451 0041 00 .byte 0 + 1452 0042 0B .uleb128 0xb + 1453 0043 0B .uleb128 0xb + 1454 0044 49 .uleb128 0x49 + 1455 0045 13 .uleb128 0x13 + 1456 0046 00 .byte 0 + 1457 0047 00 .byte 0 + 1458 0048 07 .uleb128 0x7 + 1459 0049 26 .uleb128 0x26 + 1460 004a 00 .byte 0 + 1461 004b 49 .uleb128 0x49 + 1462 004c 13 .uleb128 0x13 + 1463 004d 00 .byte 0 + 1464 004e 00 .byte 0 + 1465 004f 08 .uleb128 0x8 + 1466 0050 13 .uleb128 0x13 + 1467 0051 01 .byte 0x1 + 1468 0052 0B .uleb128 0xb + 1469 0053 0B .uleb128 0xb + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 27 + + + 1470 0054 3A .uleb128 0x3a + 1471 0055 0B .uleb128 0xb + 1472 0056 3B .uleb128 0x3b + 1473 0057 0B .uleb128 0xb + 1474 0058 01 .uleb128 0x1 + 1475 0059 13 .uleb128 0x13 + 1476 005a 00 .byte 0 + 1477 005b 00 .byte 0 + 1478 005c 09 .uleb128 0x9 + 1479 005d 0D .uleb128 0xd + 1480 005e 00 .byte 0 + 1481 005f 03 .uleb128 0x3 + 1482 0060 0E .uleb128 0xe + 1483 0061 3A .uleb128 0x3a + 1484 0062 0B .uleb128 0xb + 1485 0063 3B .uleb128 0x3b + 1486 0064 0B .uleb128 0xb + 1487 0065 49 .uleb128 0x49 + 1488 0066 13 .uleb128 0x13 + 1489 0067 38 .uleb128 0x38 + 1490 0068 0A .uleb128 0xa + 1491 0069 00 .byte 0 + 1492 006a 00 .byte 0 + 1493 006b 0A .uleb128 0xa + 1494 006c 0D .uleb128 0xd + 1495 006d 00 .byte 0 + 1496 006e 03 .uleb128 0x3 + 1497 006f 08 .uleb128 0x8 + 1498 0070 3A .uleb128 0x3a + 1499 0071 0B .uleb128 0xb + 1500 0072 3B .uleb128 0x3b + 1501 0073 0B .uleb128 0xb + 1502 0074 49 .uleb128 0x49 + 1503 0075 13 .uleb128 0x13 + 1504 0076 38 .uleb128 0x38 + 1505 0077 0A .uleb128 0xa + 1506 0078 00 .byte 0 + 1507 0079 00 .byte 0 + 1508 007a 0B .uleb128 0xb + 1509 007b 13 .uleb128 0x13 + 1510 007c 01 .byte 0x1 + 1511 007d 0B .uleb128 0xb + 1512 007e 05 .uleb128 0x5 + 1513 007f 3A .uleb128 0x3a + 1514 0080 0B .uleb128 0xb + 1515 0081 3B .uleb128 0x3b + 1516 0082 0B .uleb128 0xb + 1517 0083 01 .uleb128 0x1 + 1518 0084 13 .uleb128 0x13 + 1519 0085 00 .byte 0 + 1520 0086 00 .byte 0 + 1521 0087 0C .uleb128 0xc + 1522 0088 01 .uleb128 0x1 + 1523 0089 01 .byte 0x1 + 1524 008a 49 .uleb128 0x49 + 1525 008b 13 .uleb128 0x13 + 1526 008c 01 .uleb128 0x1 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 28 + + + 1527 008d 13 .uleb128 0x13 + 1528 008e 00 .byte 0 + 1529 008f 00 .byte 0 + 1530 0090 0D .uleb128 0xd + 1531 0091 21 .uleb128 0x21 + 1532 0092 00 .byte 0 + 1533 0093 49 .uleb128 0x49 + 1534 0094 13 .uleb128 0x13 + 1535 0095 2F .uleb128 0x2f + 1536 0096 0B .uleb128 0xb + 1537 0097 00 .byte 0 + 1538 0098 00 .byte 0 + 1539 0099 0E .uleb128 0xe + 1540 009a 04 .uleb128 0x4 + 1541 009b 01 .byte 0x1 + 1542 009c 0B .uleb128 0xb + 1543 009d 0B .uleb128 0xb + 1544 009e 3A .uleb128 0x3a + 1545 009f 0B .uleb128 0xb + 1546 00a0 3B .uleb128 0x3b + 1547 00a1 0B .uleb128 0xb + 1548 00a2 01 .uleb128 0x1 + 1549 00a3 13 .uleb128 0x13 + 1550 00a4 00 .byte 0 + 1551 00a5 00 .byte 0 + 1552 00a6 0F .uleb128 0xf + 1553 00a7 28 .uleb128 0x28 + 1554 00a8 00 .byte 0 + 1555 00a9 03 .uleb128 0x3 + 1556 00aa 0E .uleb128 0xe + 1557 00ab 1C .uleb128 0x1c + 1558 00ac 0D .uleb128 0xd + 1559 00ad 00 .byte 0 + 1560 00ae 00 .byte 0 + 1561 00af 10 .uleb128 0x10 + 1562 00b0 35 .uleb128 0x35 + 1563 00b1 00 .byte 0 + 1564 00b2 49 .uleb128 0x49 + 1565 00b3 13 .uleb128 0x13 + 1566 00b4 00 .byte 0 + 1567 00b5 00 .byte 0 + 1568 00b6 11 .uleb128 0x11 + 1569 00b7 2E .uleb128 0x2e + 1570 00b8 01 .byte 0x1 + 1571 00b9 3F .uleb128 0x3f + 1572 00ba 0C .uleb128 0xc + 1573 00bb 03 .uleb128 0x3 + 1574 00bc 0E .uleb128 0xe + 1575 00bd 3A .uleb128 0x3a + 1576 00be 0B .uleb128 0xb + 1577 00bf 3B .uleb128 0x3b + 1578 00c0 0B .uleb128 0xb + 1579 00c1 27 .uleb128 0x27 + 1580 00c2 0C .uleb128 0xc + 1581 00c3 11 .uleb128 0x11 + 1582 00c4 01 .uleb128 0x1 + 1583 00c5 12 .uleb128 0x12 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 29 + + + 1584 00c6 01 .uleb128 0x1 + 1585 00c7 40 .uleb128 0x40 + 1586 00c8 06 .uleb128 0x6 + 1587 00c9 9742 .uleb128 0x2117 + 1588 00cb 0C .uleb128 0xc + 1589 00cc 01 .uleb128 0x1 + 1590 00cd 13 .uleb128 0x13 + 1591 00ce 00 .byte 0 + 1592 00cf 00 .byte 0 + 1593 00d0 12 .uleb128 0x12 + 1594 00d1 898201 .uleb128 0x4109 + 1595 00d4 01 .byte 0x1 + 1596 00d5 11 .uleb128 0x11 + 1597 00d6 01 .uleb128 0x1 + 1598 00d7 31 .uleb128 0x31 + 1599 00d8 13 .uleb128 0x13 + 1600 00d9 00 .byte 0 + 1601 00da 00 .byte 0 + 1602 00db 13 .uleb128 0x13 + 1603 00dc 8A8201 .uleb128 0x410a + 1604 00df 00 .byte 0 + 1605 00e0 02 .uleb128 0x2 + 1606 00e1 0A .uleb128 0xa + 1607 00e2 9142 .uleb128 0x2111 + 1608 00e4 0A .uleb128 0xa + 1609 00e5 00 .byte 0 + 1610 00e6 00 .byte 0 + 1611 00e7 14 .uleb128 0x14 + 1612 00e8 2E .uleb128 0x2e + 1613 00e9 00 .byte 0 + 1614 00ea 3F .uleb128 0x3f + 1615 00eb 0C .uleb128 0xc + 1616 00ec 03 .uleb128 0x3 + 1617 00ed 0E .uleb128 0xe + 1618 00ee 3A .uleb128 0x3a + 1619 00ef 0B .uleb128 0xb + 1620 00f0 3B .uleb128 0x3b + 1621 00f1 0B .uleb128 0xb + 1622 00f2 27 .uleb128 0x27 + 1623 00f3 0C .uleb128 0xc + 1624 00f4 11 .uleb128 0x11 + 1625 00f5 01 .uleb128 0x1 + 1626 00f6 12 .uleb128 0x12 + 1627 00f7 01 .uleb128 0x1 + 1628 00f8 40 .uleb128 0x40 + 1629 00f9 0A .uleb128 0xa + 1630 00fa 9742 .uleb128 0x2117 + 1631 00fc 0C .uleb128 0xc + 1632 00fd 00 .byte 0 + 1633 00fe 00 .byte 0 + 1634 00ff 15 .uleb128 0x15 + 1635 0100 898201 .uleb128 0x4109 + 1636 0103 00 .byte 0 + 1637 0104 11 .uleb128 0x11 + 1638 0105 01 .uleb128 0x1 + 1639 0106 31 .uleb128 0x31 + 1640 0107 13 .uleb128 0x13 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 30 + + + 1641 0108 00 .byte 0 + 1642 0109 00 .byte 0 + 1643 010a 16 .uleb128 0x16 + 1644 010b 898201 .uleb128 0x4109 + 1645 010e 00 .byte 0 + 1646 010f 11 .uleb128 0x11 + 1647 0110 01 .uleb128 0x1 + 1648 0111 9542 .uleb128 0x2115 + 1649 0113 0C .uleb128 0xc + 1650 0114 31 .uleb128 0x31 + 1651 0115 13 .uleb128 0x13 + 1652 0116 00 .byte 0 + 1653 0117 00 .byte 0 + 1654 0118 17 .uleb128 0x17 + 1655 0119 34 .uleb128 0x34 + 1656 011a 00 .byte 0 + 1657 011b 03 .uleb128 0x3 + 1658 011c 0E .uleb128 0xe + 1659 011d 3A .uleb128 0x3a + 1660 011e 0B .uleb128 0xb + 1661 011f 3B .uleb128 0x3b + 1662 0120 0B .uleb128 0xb + 1663 0121 49 .uleb128 0x49 + 1664 0122 13 .uleb128 0x13 + 1665 0123 02 .uleb128 0x2 + 1666 0124 0A .uleb128 0xa + 1667 0125 00 .byte 0 + 1668 0126 00 .byte 0 + 1669 0127 18 .uleb128 0x18 + 1670 0128 898201 .uleb128 0x4109 + 1671 012b 01 .byte 0x1 + 1672 012c 11 .uleb128 0x11 + 1673 012d 01 .uleb128 0x1 + 1674 012e 31 .uleb128 0x31 + 1675 012f 13 .uleb128 0x13 + 1676 0130 01 .uleb128 0x1 + 1677 0131 13 .uleb128 0x13 + 1678 0132 00 .byte 0 + 1679 0133 00 .byte 0 + 1680 0134 19 .uleb128 0x19 + 1681 0135 2E .uleb128 0x2e + 1682 0136 01 .byte 0x1 + 1683 0137 3F .uleb128 0x3f + 1684 0138 0C .uleb128 0xc + 1685 0139 03 .uleb128 0x3 + 1686 013a 0E .uleb128 0xe + 1687 013b 3A .uleb128 0x3a + 1688 013c 0B .uleb128 0xb + 1689 013d 3B .uleb128 0x3b + 1690 013e 0B .uleb128 0xb + 1691 013f 27 .uleb128 0x27 + 1692 0140 0C .uleb128 0xc + 1693 0141 49 .uleb128 0x49 + 1694 0142 13 .uleb128 0x13 + 1695 0143 11 .uleb128 0x11 + 1696 0144 01 .uleb128 0x1 + 1697 0145 12 .uleb128 0x12 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 31 + + + 1698 0146 01 .uleb128 0x1 + 1699 0147 40 .uleb128 0x40 + 1700 0148 06 .uleb128 0x6 + 1701 0149 9742 .uleb128 0x2117 + 1702 014b 0C .uleb128 0xc + 1703 014c 01 .uleb128 0x1 + 1704 014d 13 .uleb128 0x13 + 1705 014e 00 .byte 0 + 1706 014f 00 .byte 0 + 1707 0150 1A .uleb128 0x1a + 1708 0151 34 .uleb128 0x34 + 1709 0152 00 .byte 0 + 1710 0153 03 .uleb128 0x3 + 1711 0154 0E .uleb128 0xe + 1712 0155 3A .uleb128 0x3a + 1713 0156 0B .uleb128 0xb + 1714 0157 3B .uleb128 0x3b + 1715 0158 05 .uleb128 0x5 + 1716 0159 49 .uleb128 0x49 + 1717 015a 13 .uleb128 0x13 + 1718 015b 3F .uleb128 0x3f + 1719 015c 0C .uleb128 0xc + 1720 015d 3C .uleb128 0x3c + 1721 015e 0C .uleb128 0xc + 1722 015f 00 .byte 0 + 1723 0160 00 .byte 0 + 1724 0161 1B .uleb128 0x1b + 1725 0162 2E .uleb128 0x2e + 1726 0163 01 .byte 0x1 + 1727 0164 3F .uleb128 0x3f + 1728 0165 0C .uleb128 0xc + 1729 0166 03 .uleb128 0x3 + 1730 0167 0E .uleb128 0xe + 1731 0168 3A .uleb128 0x3a + 1732 0169 0B .uleb128 0xb + 1733 016a 3B .uleb128 0x3b + 1734 016b 0B .uleb128 0xb + 1735 016c 27 .uleb128 0x27 + 1736 016d 0C .uleb128 0xc + 1737 016e 3C .uleb128 0x3c + 1738 016f 0C .uleb128 0xc + 1739 0170 01 .uleb128 0x1 + 1740 0171 13 .uleb128 0x13 + 1741 0172 00 .byte 0 + 1742 0173 00 .byte 0 + 1743 0174 1C .uleb128 0x1c + 1744 0175 05 .uleb128 0x5 + 1745 0176 00 .byte 0 + 1746 0177 49 .uleb128 0x49 + 1747 0178 13 .uleb128 0x13 + 1748 0179 00 .byte 0 + 1749 017a 00 .byte 0 + 1750 017b 1D .uleb128 0x1d + 1751 017c 18 .uleb128 0x18 + 1752 017d 00 .byte 0 + 1753 017e 00 .byte 0 + 1754 017f 00 .byte 0 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 32 + + + 1755 0180 1E .uleb128 0x1e + 1756 0181 2E .uleb128 0x2e + 1757 0182 00 .byte 0 + 1758 0183 3F .uleb128 0x3f + 1759 0184 0C .uleb128 0xc + 1760 0185 03 .uleb128 0x3 + 1761 0186 0E .uleb128 0xe + 1762 0187 3A .uleb128 0x3a + 1763 0188 0B .uleb128 0xb + 1764 0189 3B .uleb128 0x3b + 1765 018a 05 .uleb128 0x5 + 1766 018b 27 .uleb128 0x27 + 1767 018c 0C .uleb128 0xc + 1768 018d 3C .uleb128 0x3c + 1769 018e 0C .uleb128 0xc + 1770 018f 00 .byte 0 + 1771 0190 00 .byte 0 + 1772 0191 1F .uleb128 0x1f + 1773 0192 2E .uleb128 0x2e + 1774 0193 00 .byte 0 + 1775 0194 3F .uleb128 0x3f + 1776 0195 0C .uleb128 0xc + 1777 0196 03 .uleb128 0x3 + 1778 0197 0E .uleb128 0xe + 1779 0198 3A .uleb128 0x3a + 1780 0199 0B .uleb128 0xb + 1781 019a 3B .uleb128 0x3b + 1782 019b 05 .uleb128 0x5 + 1783 019c 27 .uleb128 0x27 + 1784 019d 0C .uleb128 0xc + 1785 019e 49 .uleb128 0x49 + 1786 019f 13 .uleb128 0x13 + 1787 01a0 3C .uleb128 0x3c + 1788 01a1 0C .uleb128 0xc + 1789 01a2 00 .byte 0 + 1790 01a3 00 .byte 0 + 1791 01a4 20 .uleb128 0x20 + 1792 01a5 2E .uleb128 0x2e + 1793 01a6 01 .byte 0x1 + 1794 01a7 3F .uleb128 0x3f + 1795 01a8 0C .uleb128 0xc + 1796 01a9 03 .uleb128 0x3 + 1797 01aa 0E .uleb128 0xe + 1798 01ab 27 .uleb128 0x27 + 1799 01ac 0C .uleb128 0xc + 1800 01ad 49 .uleb128 0x49 + 1801 01ae 13 .uleb128 0x13 + 1802 01af 34 .uleb128 0x34 + 1803 01b0 0C .uleb128 0xc + 1804 01b1 3C .uleb128 0x3c + 1805 01b2 0C .uleb128 0xc + 1806 01b3 01 .uleb128 0x1 + 1807 01b4 13 .uleb128 0x13 + 1808 01b5 00 .byte 0 + 1809 01b6 00 .byte 0 + 1810 01b7 21 .uleb128 0x21 + 1811 01b8 26 .uleb128 0x26 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 33 + + + 1812 01b9 00 .byte 0 + 1813 01ba 00 .byte 0 + 1814 01bb 00 .byte 0 + 1815 01bc 22 .uleb128 0x22 + 1816 01bd 2E .uleb128 0x2e + 1817 01be 01 .byte 0x1 + 1818 01bf 3F .uleb128 0x3f + 1819 01c0 0C .uleb128 0xc + 1820 01c1 03 .uleb128 0x3 + 1821 01c2 0E .uleb128 0xe + 1822 01c3 3A .uleb128 0x3a + 1823 01c4 0B .uleb128 0xb + 1824 01c5 3B .uleb128 0x3b + 1825 01c6 05 .uleb128 0x5 + 1826 01c7 27 .uleb128 0x27 + 1827 01c8 0C .uleb128 0xc + 1828 01c9 49 .uleb128 0x49 + 1829 01ca 13 .uleb128 0x13 + 1830 01cb 3C .uleb128 0x3c + 1831 01cc 0C .uleb128 0xc + 1832 01cd 01 .uleb128 0x1 + 1833 01ce 13 .uleb128 0x13 + 1834 01cf 00 .byte 0 + 1835 01d0 00 .byte 0 + 1836 01d1 23 .uleb128 0x23 + 1837 01d2 2E .uleb128 0x2e + 1838 01d3 01 .byte 0x1 + 1839 01d4 3F .uleb128 0x3f + 1840 01d5 0C .uleb128 0xc + 1841 01d6 03 .uleb128 0x3 + 1842 01d7 0E .uleb128 0xe + 1843 01d8 3A .uleb128 0x3a + 1844 01d9 0B .uleb128 0xb + 1845 01da 3B .uleb128 0x3b + 1846 01db 05 .uleb128 0x5 + 1847 01dc 27 .uleb128 0x27 + 1848 01dd 0C .uleb128 0xc + 1849 01de 3C .uleb128 0x3c + 1850 01df 0C .uleb128 0xc + 1851 01e0 01 .uleb128 0x1 + 1852 01e1 13 .uleb128 0x13 + 1853 01e2 00 .byte 0 + 1854 01e3 00 .byte 0 + 1855 01e4 24 .uleb128 0x24 + 1856 01e5 2E .uleb128 0x2e + 1857 01e6 00 .byte 0 + 1858 01e7 3F .uleb128 0x3f + 1859 01e8 0C .uleb128 0xc + 1860 01e9 03 .uleb128 0x3 + 1861 01ea 0E .uleb128 0xe + 1862 01eb 3A .uleb128 0x3a + 1863 01ec 0B .uleb128 0xb + 1864 01ed 3B .uleb128 0x3b + 1865 01ee 0B .uleb128 0xb + 1866 01ef 27 .uleb128 0x27 + 1867 01f0 0C .uleb128 0xc + 1868 01f1 3C .uleb128 0x3c + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 34 + + + 1869 01f2 0C .uleb128 0xc + 1870 01f3 00 .byte 0 + 1871 01f4 00 .byte 0 + 1872 01f5 25 .uleb128 0x25 + 1873 01f6 2E .uleb128 0x2e + 1874 01f7 01 .byte 0x1 + 1875 01f8 3F .uleb128 0x3f + 1876 01f9 0C .uleb128 0xc + 1877 01fa 03 .uleb128 0x3 + 1878 01fb 0E .uleb128 0xe + 1879 01fc 3A .uleb128 0x3a + 1880 01fd 0B .uleb128 0xb + 1881 01fe 3B .uleb128 0x3b + 1882 01ff 05 .uleb128 0x5 + 1883 0200 27 .uleb128 0x27 + 1884 0201 0C .uleb128 0xc + 1885 0202 3C .uleb128 0x3c + 1886 0203 0C .uleb128 0xc + 1887 0204 00 .byte 0 + 1888 0205 00 .byte 0 + 1889 0206 00 .byte 0 + 1890 .section .debug_loc,"",%progbits + 1891 .Ldebug_loc0: + 1892 .LLST0: + 1893 0000 00000000 .4byte .LFB62 + 1894 0004 02000000 .4byte .LCFI0 + 1895 0008 0200 .2byte 0x2 + 1896 000a 7D .byte 0x7d + 1897 000b 00 .sleb128 0 + 1898 000c 02000000 .4byte .LCFI0 + 1899 0010 10000000 .4byte .LFE62 + 1900 0014 0200 .2byte 0x2 + 1901 0016 7D .byte 0x7d + 1902 0017 08 .sleb128 8 + 1903 0018 00000000 .4byte 0 + 1904 001c 00000000 .4byte 0 + 1905 .LLST1: + 1906 0020 00000000 .4byte .LFB63 + 1907 0024 02000000 .4byte .LCFI1 + 1908 0028 0200 .2byte 0x2 + 1909 002a 7D .byte 0x7d + 1910 002b 00 .sleb128 0 + 1911 002c 02000000 .4byte .LCFI1 + 1912 0030 10000000 .4byte .LFE63 + 1913 0034 0200 .2byte 0x2 + 1914 0036 7D .byte 0x7d + 1915 0037 08 .sleb128 8 + 1916 0038 00000000 .4byte 0 + 1917 003c 00000000 .4byte 0 + 1918 .LLST2: + 1919 0040 00000000 .4byte .LFB64 + 1920 0044 02000000 .4byte .LCFI2 + 1921 0048 0200 .2byte 0x2 + 1922 004a 7D .byte 0x7d + 1923 004b 00 .sleb128 0 + 1924 004c 02000000 .4byte .LCFI2 + 1925 0050 10000000 .4byte .LFE64 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 35 + + + 1926 0054 0200 .2byte 0x2 + 1927 0056 7D .byte 0x7d + 1928 0057 08 .sleb128 8 + 1929 0058 00000000 .4byte 0 + 1930 005c 00000000 .4byte 0 + 1931 .LLST3: + 1932 0060 00000000 .4byte .LFB65 + 1933 0064 02000000 .4byte .LCFI3 + 1934 0068 0200 .2byte 0x2 + 1935 006a 7D .byte 0x7d + 1936 006b 00 .sleb128 0 + 1937 006c 02000000 .4byte .LCFI3 + 1938 0070 10000000 .4byte .LFE65 + 1939 0074 0200 .2byte 0x2 + 1940 0076 7D .byte 0x7d + 1941 0077 08 .sleb128 8 + 1942 0078 00000000 .4byte 0 + 1943 007c 00000000 .4byte 0 + 1944 .LLST4: + 1945 0080 00000000 .4byte .LFB67 + 1946 0084 02000000 .4byte .LCFI4 + 1947 0088 0200 .2byte 0x2 + 1948 008a 7D .byte 0x7d + 1949 008b 00 .sleb128 0 + 1950 008c 02000000 .4byte .LCFI4 + 1951 0090 0E000000 .4byte .LFE67 + 1952 0094 0200 .2byte 0x2 + 1953 0096 7D .byte 0x7d + 1954 0097 08 .sleb128 8 + 1955 0098 00000000 .4byte 0 + 1956 009c 00000000 .4byte 0 + 1957 .LLST5: + 1958 00a0 00000000 .4byte .LFB68 + 1959 00a4 02000000 .4byte .LCFI5 + 1960 00a8 0200 .2byte 0x2 + 1961 00aa 7D .byte 0x7d + 1962 00ab 00 .sleb128 0 + 1963 00ac 02000000 .4byte .LCFI5 + 1964 00b0 0E000000 .4byte .LFE68 + 1965 00b4 0200 .2byte 0x2 + 1966 00b6 7D .byte 0x7d + 1967 00b7 08 .sleb128 8 + 1968 00b8 00000000 .4byte 0 + 1969 00bc 00000000 .4byte 0 + 1970 .LLST6: + 1971 00c0 00000000 .4byte .LFB69 + 1972 00c4 02000000 .4byte .LCFI6 + 1973 00c8 0200 .2byte 0x2 + 1974 00ca 7D .byte 0x7d + 1975 00cb 00 .sleb128 0 + 1976 00cc 02000000 .4byte .LCFI6 + 1977 00d0 0E000000 .4byte .LFE69 + 1978 00d4 0200 .2byte 0x2 + 1979 00d6 7D .byte 0x7d + 1980 00d7 08 .sleb128 8 + 1981 00d8 00000000 .4byte 0 + 1982 00dc 00000000 .4byte 0 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 36 + + + 1983 .LLST7: + 1984 00e0 00000000 .4byte .LFB70 + 1985 00e4 02000000 .4byte .LCFI7 + 1986 00e8 0200 .2byte 0x2 + 1987 00ea 7D .byte 0x7d + 1988 00eb 00 .sleb128 0 + 1989 00ec 02000000 .4byte .LCFI7 + 1990 00f0 0E000000 .4byte .LFE70 + 1991 00f4 0200 .2byte 0x2 + 1992 00f6 7D .byte 0x7d + 1993 00f7 08 .sleb128 8 + 1994 00f8 00000000 .4byte 0 + 1995 00fc 00000000 .4byte 0 + 1996 .LLST8: + 1997 0100 00000000 .4byte .LFB71 + 1998 0104 02000000 .4byte .LCFI8 + 1999 0108 0200 .2byte 0x2 + 2000 010a 7D .byte 0x7d + 2001 010b 00 .sleb128 0 + 2002 010c 02000000 .4byte .LCFI8 + 2003 0110 06000000 .4byte .LCFI9 + 2004 0114 0200 .2byte 0x2 + 2005 0116 7D .byte 0x7d + 2006 0117 08 .sleb128 8 + 2007 0118 06000000 .4byte .LCFI9 + 2008 011c 28000000 .4byte .LFE71 + 2009 0120 0300 .2byte 0x3 + 2010 0122 7D .byte 0x7d + 2011 0123 9807 .sleb128 920 + 2012 0125 00000000 .4byte 0 + 2013 0129 00000000 .4byte 0 + 2014 .LLST9: + 2015 012d 00000000 .4byte .LFB72 + 2016 0131 02000000 .4byte .LCFI10 + 2017 0135 0200 .2byte 0x2 + 2018 0137 7D .byte 0x7d + 2019 0138 00 .sleb128 0 + 2020 0139 02000000 .4byte .LCFI10 + 2021 013d 22000000 .4byte .LFE72 + 2022 0141 0200 .2byte 0x2 + 2023 0143 7D .byte 0x7d + 2024 0144 08 .sleb128 8 + 2025 0145 00000000 .4byte 0 + 2026 0149 00000000 .4byte 0 + 2027 .section .debug_aranges,"",%progbits + 2028 0000 6C000000 .4byte 0x6c + 2029 0004 0200 .2byte 0x2 + 2030 0006 00000000 .4byte .Ldebug_info0 + 2031 000a 04 .byte 0x4 + 2032 000b 00 .byte 0 + 2033 000c 0000 .2byte 0 + 2034 000e 0000 .2byte 0 + 2035 0010 00000000 .4byte .LFB62 + 2036 0014 10000000 .4byte .LFE62-.LFB62 + 2037 0018 00000000 .4byte .LFB63 + 2038 001c 10000000 .4byte .LFE63-.LFB63 + 2039 0020 00000000 .4byte .LFB64 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 37 + + + 2040 0024 10000000 .4byte .LFE64-.LFB64 + 2041 0028 00000000 .4byte .LFB65 + 2042 002c 10000000 .4byte .LFE65-.LFB65 + 2043 0030 00000000 .4byte .LFB66 + 2044 0034 02000000 .4byte .LFE66-.LFB66 + 2045 0038 00000000 .4byte .LFB67 + 2046 003c 0E000000 .4byte .LFE67-.LFB67 + 2047 0040 00000000 .4byte .LFB68 + 2048 0044 0E000000 .4byte .LFE68-.LFB68 + 2049 0048 00000000 .4byte .LFB69 + 2050 004c 0E000000 .4byte .LFE69-.LFB69 + 2051 0050 00000000 .4byte .LFB70 + 2052 0054 0E000000 .4byte .LFE70-.LFB70 + 2053 0058 00000000 .4byte .LFB71 + 2054 005c 28000000 .4byte .LFE71-.LFB71 + 2055 0060 00000000 .4byte .LFB72 + 2056 0064 22000000 .4byte .LFE72-.LFB72 + 2057 0068 00000000 .4byte 0 + 2058 006c 00000000 .4byte 0 + 2059 .section .debug_ranges,"",%progbits + 2060 .Ldebug_ranges0: + 2061 0000 00000000 .4byte .LFB62 + 2062 0004 10000000 .4byte .LFE62 + 2063 0008 00000000 .4byte .LFB63 + 2064 000c 10000000 .4byte .LFE63 + 2065 0010 00000000 .4byte .LFB64 + 2066 0014 10000000 .4byte .LFE64 + 2067 0018 00000000 .4byte .LFB65 + 2068 001c 10000000 .4byte .LFE65 + 2069 0020 00000000 .4byte .LFB66 + 2070 0024 02000000 .4byte .LFE66 + 2071 0028 00000000 .4byte .LFB67 + 2072 002c 0E000000 .4byte .LFE67 + 2073 0030 00000000 .4byte .LFB68 + 2074 0034 0E000000 .4byte .LFE68 + 2075 0038 00000000 .4byte .LFB69 + 2076 003c 0E000000 .4byte .LFE69 + 2077 0040 00000000 .4byte .LFB70 + 2078 0044 0E000000 .4byte .LFE70 + 2079 0048 00000000 .4byte .LFB71 + 2080 004c 28000000 .4byte .LFE71 + 2081 0050 00000000 .4byte .LFB72 + 2082 0054 22000000 .4byte .LFE72 + 2083 0058 00000000 .4byte 0 + 2084 005c 00000000 .4byte 0 + 2085 .section .debug_line,"",%progbits + 2086 .Ldebug_line0: + 2087 0000 2F020000 .section .debug_str,"MS",%progbits,1 + 2087 02005801 + 2087 00000201 + 2087 FB0E0D00 + 2087 01010101 + 2088 .LASF55: + 2089 0000 5749534D .ascii "WISMART_MCU_FREQ_64_HSE\000" + 2089 4152545F + 2089 4D43555F + 2089 46524551 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 38 + + + 2089 5F36345F + 2090 .LASF36: + 2091 0018 6770696F .ascii "gpio_af\000" + 2091 5F616600 + 2092 .LASF63: + 2093 0020 7769736D .ascii "wismart_hwif_mcu_t\000" + 2093 6172745F + 2093 68776966 + 2093 5F6D6375 + 2093 5F7400 + 2094 .LASF59: + 2095 0033 5749534D .ascii "WISMART_MCU_FREQ_64_HSI\000" + 2095 4152545F + 2095 4D43555F + 2095 46524551 + 2095 5F36345F + 2096 .LASF21: + 2097 004b 65787469 .ascii "exti_port_source\000" + 2097 5F706F72 + 2097 745F736F + 2097 75726365 + 2097 00 + 2098 .LASF28: + 2099 005c 656E6162 .ascii "enable\000" + 2099 6C6500 + 2100 .LASF32: + 2101 0063 75736172 .ascii "usart\000" + 2101 7400 + 2102 .LASF68: + 2103 0069 4D656D4D .ascii "MemManageVector\000" + 2103 616E6167 + 2103 65566563 + 2103 746F7200 + 2104 .LASF44: + 2105 0079 75736555 .ascii "useULPI_PHY\000" + 2105 4C50495F + 2105 50485900 + 2106 .LASF3: + 2107 0085 73686F72 .ascii "short int\000" + 2107 7420696E + 2107 7400 + 2108 .LASF47: + 2109 008f 76627573 .ascii "vbus\000" + 2109 00 + 2110 .LASF14: + 2111 0094 73697A65 .ascii "sizetype\000" + 2111 74797065 + 2111 00 + 2112 .LASF19: + 2113 009d 7769736D .ascii "wismart_hwif_port_t\000" + 2113 6172745F + 2113 68776966 + 2113 5F706F72 + 2113 745F7400 + 2114 .LASF96: + 2115 00b1 63685468 .ascii "chThdSleep\000" + 2115 64536C65 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 39 + + + 2115 657000 + 2116 .LASF92: + 2117 00bc 6D61696E .ascii "main\000" + 2117 00 + 2118 .LASF82: + 2119 00c1 6D656D63 .ascii "memcpy\000" + 2119 707900 + 2120 .LASF24: + 2121 00c8 65787469 .ascii "exti_irq_number\000" + 2121 5F697271 + 2121 5F6E756D + 2121 62657200 + 2122 .LASF37: + 2123 00d8 6770696F .ascii "gpio_tx\000" + 2123 5F747800 + 2124 .LASF62: + 2125 00e0 656E6162 .ascii "enableWkupPin\000" + 2125 6C65576B + 2125 75705069 + 2125 6E00 + 2126 .LASF89: + 2127 00ee 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 2127 73657273 + 2127 5C496D61 + 2127 6E6F6C5C + 2127 64657665 + 2128 011b 6C696361 .ascii "lications\\smartcities\000" + 2128 74696F6E + 2128 735C736D + 2128 61727463 + 2128 69746965 + 2129 .LASF69: + 2130 0131 42757346 .ascii "BusFaultVector\000" + 2130 61756C74 + 2130 56656374 + 2130 6F7200 + 2131 .LASF4: + 2132 0140 75696E74 .ascii "uint8_t\000" + 2132 385F7400 + 2133 .LASF20: + 2134 0148 6770696F .ascii "gpio_ext_int\000" + 2134 5F657874 + 2134 5F696E74 + 2134 00 + 2135 .LASF33: + 2136 0155 62617564 .ascii "baud_rate\000" + 2136 5F726174 + 2136 6500 + 2137 .LASF91: + 2138 015f 68776966 .ascii "hwif\000" + 2138 00 + 2139 .LASF85: + 2140 0164 62757474 .ascii "buttons_init\000" + 2140 6F6E735F + 2140 696E6974 + 2140 00 + 2141 .LASF61: + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 40 + + + 2142 0171 66726571 .ascii "freq\000" + 2142 00 + 2143 .LASF50: + 2144 0176 68735F6E .ascii "hs_nxt\000" + 2144 787400 + 2145 .LASF11: + 2146 017d 6C6F6E67 .ascii "long long int\000" + 2146 206C6F6E + 2146 6720696E + 2146 7400 + 2147 .LASF53: + 2148 018b 5749534D .ascii "WISMART_MCU_FREQ_32_HSE\000" + 2148 4152545F + 2148 4D43555F + 2148 46524551 + 2148 5F33325F + 2149 .LASF35: + 2150 01a3 74785F72 .ascii "tx_rcc\000" + 2150 636300 + 2151 .LASF48: + 2152 01aa 68735F63 .ascii "hs_clk\000" + 2152 6C6B00 + 2153 .LASF83: + 2154 01b1 6C696277 .ascii "libwismart_PowerSave_Enable\000" + 2154 69736D61 + 2154 72745F50 + 2154 6F776572 + 2154 53617665 + 2155 .LASF8: + 2156 01cd 6C6F6E67 .ascii "long int\000" + 2156 20696E74 + 2156 00 + 2157 .LASF84: + 2158 01d6 6C696277 .ascii "libwismart_PowerSave_HigherProfile\000" + 2158 69736D61 + 2158 72745F50 + 2158 6F776572 + 2158 53617665 + 2159 .LASF66: + 2160 01f9 7769736D .ascii "wismart_hwif_t\000" + 2160 6172745F + 2160 68776966 + 2160 5F7400 + 2161 .LASF31: + 2162 0208 7769736D .ascii "wismart_hwif_dma_t\000" + 2162 6172745F + 2162 68776966 + 2162 5F646D61 + 2162 5F7400 + 2163 .LASF17: + 2164 021b 736F7572 .ascii "source\000" + 2164 636500 + 2165 .LASF18: + 2166 0222 72656D61 .ascii "remap\000" + 2166 7000 + 2167 .LASF39: + 2168 0228 646D615F .ascii "dma_tx\000" + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 41 + + + 2168 747800 + 2169 .LASF22: + 2170 022f 65787469 .ascii "exti_pin_source\000" + 2170 5F70696E + 2170 5F736F75 + 2170 72636500 + 2171 .LASF34: + 2172 023f 74785F69 .ascii "tx_irq\000" + 2172 727100 + 2173 .LASF51: + 2174 0246 68735F64 .ascii "hs_dir\000" + 2174 697200 + 2175 .LASF77: + 2176 024d 5F706F72 .ascii "_port_irq_epilogue\000" + 2176 745F6972 + 2176 715F6570 + 2176 696C6F67 + 2176 756500 + 2177 .LASF2: + 2178 0260 756E7369 .ascii "unsigned char\000" + 2178 676E6564 + 2178 20636861 + 2178 7200 + 2179 .LASF70: + 2180 026e 55736167 .ascii "UsageFaultVector\000" + 2180 65466175 + 2180 6C745665 + 2180 63746F72 + 2180 00 + 2181 .LASF73: + 2182 027f 56656374 .ascii "Vector78\000" + 2182 6F723738 + 2182 00 + 2183 .LASF64: + 2184 0288 77696669 .ascii "wifi\000" + 2184 00 + 2185 .LASF46: + 2186 028d 686F7374 .ascii "host_powersw\000" + 2186 5F706F77 + 2186 65727377 + 2186 00 + 2187 .LASF1: + 2188 029a 7369676E .ascii "signed char\000" + 2188 65642063 + 2188 68617200 + 2189 .LASF26: + 2190 02a6 6770696F .ascii "gpio_3_3v\000" + 2190 5F335F33 + 2190 7600 + 2191 .LASF12: + 2192 02b0 6C6F6E67 .ascii "long long unsigned int\000" + 2192 206C6F6E + 2192 6720756E + 2192 7369676E + 2192 65642069 + 2193 .LASF81: + 2194 02c7 7072696E .ascii "print\000" + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 42 + + + 2194 7400 + 2195 .LASF9: + 2196 02cd 75696E74 .ascii "uint32_t\000" + 2196 33325F74 + 2196 00 + 2197 .LASF74: + 2198 02d6 56656374 .ascii "Vector7C\000" + 2198 6F723743 + 2198 00 + 2199 .LASF5: + 2200 02df 75696E74 .ascii "uint16_t\000" + 2200 31365F74 + 2200 00 + 2201 .LASF87: + 2202 02e8 474E5520 .ascii "GNU C 4.7.2\000" + 2202 4320342E + 2202 372E3200 + 2203 .LASF95: + 2204 02f4 6C696277 .ascii "libwismart_Init\000" + 2204 69736D61 + 2204 72745F49 + 2204 6E697400 + 2205 .LASF65: + 2206 0304 64656275 .ascii "debug\000" + 2206 6700 + 2207 .LASF43: + 2208 030a 69734653 .ascii "isFS\000" + 2208 00 + 2209 .LASF75: + 2210 030f 696E6974 .ascii "initLibwismart\000" + 2210 4C696277 + 2210 69736D61 + 2210 727400 + 2211 .LASF6: + 2212 031e 73686F72 .ascii "short unsigned int\000" + 2212 7420756E + 2212 7369676E + 2212 65642069 + 2212 6E7400 + 2213 .LASF67: + 2214 0331 4E4D4956 .ascii "NMIVector\000" + 2214 6563746F + 2214 7200 + 2215 .LASF13: + 2216 033b 73797374 .ascii "systime_t\000" + 2216 696D655F + 2216 7400 + 2217 .LASF27: + 2218 0345 7769736D .ascii "wismart_hwif_wifi_t\000" + 2218 6172745F + 2218 68776966 + 2218 5F776966 + 2218 695F7400 + 2219 .LASF15: + 2220 0359 63686172 .ascii "char\000" + 2220 00 + 2221 .LASF79: + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 43 + + + 2222 035e 6C696277 .ascii "libwismart_UART_TXDMA_IRQHandler\000" + 2222 69736D61 + 2222 72745F55 + 2222 4152545F + 2222 5458444D + 2223 .LASF7: + 2224 037f 696E7433 .ascii "int32_t\000" + 2224 325F7400 + 2225 .LASF49: + 2226 0387 68735F73 .ascii "hs_stp\000" + 2226 747000 + 2227 .LASF29: + 2228 038e 6368616E .ascii "channel\000" + 2228 6E656C00 + 2229 .LASF25: + 2230 0396 6770696F .ascii "gpio_1_2v\000" + 2230 5F315F32 + 2230 7600 + 2231 .LASF78: + 2232 03a0 6C696277 .ascii "libwismart_WiFi_IRQHandler\000" + 2232 69736D61 + 2232 72745F57 + 2232 6946695F + 2232 49525148 + 2233 .LASF16: + 2234 03bb 706F7274 .ascii "port\000" + 2234 00 + 2235 .LASF88: + 2236 03c0 6D61696E .ascii "main.c\000" + 2236 2E6300 + 2237 .LASF10: + 2238 03c7 6C6F6E67 .ascii "long unsigned int\000" + 2238 20756E73 + 2238 69676E65 + 2238 6420696E + 2238 7400 + 2239 .LASF57: + 2240 03d9 5749534D .ascii "WISMART_MCU_FREQ_36_HSI\000" + 2240 4152545F + 2240 4D43555F + 2240 46524551 + 2240 5F33365F + 2241 .LASF38: + 2242 03f1 6770696F .ascii "gpio_rx\000" + 2242 5F727800 + 2243 .LASF52: + 2244 03f9 7769736D .ascii "wismart_hwif_usb_t\000" + 2244 6172745F + 2244 68776966 + 2244 5F757362 + 2244 5F7400 + 2245 .LASF56: + 2246 040c 5749534D .ascii "WISMART_MCU_FREQ_72_HSE\000" + 2246 4152545F + 2246 4D43555F + 2246 46524551 + 2246 5F37325F + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 44 + + + 2247 .LASF94: + 2248 0424 6C696277 .ascii "libwismart_GetDefaultHWIF\000" + 2248 69736D61 + 2248 72745F47 + 2248 65744465 + 2248 6661756C + 2249 .LASF60: + 2250 043e 7769736D .ascii "wismart_hwif_mcu_freq_t\000" + 2250 6172745F + 2250 68776966 + 2250 5F6D6375 + 2250 5F667265 + 2251 .LASF76: + 2252 0456 6C696277 .ascii "libwismart_UART_IRQHandler\000" + 2252 69736D61 + 2252 72745F55 + 2252 4152545F + 2252 49525148 + 2253 .LASF80: + 2254 0471 6C696277 .ascii "libwismart_UART_RXDMA_IRQHandler\000" + 2254 69736D61 + 2254 72745F55 + 2254 4152545F + 2254 5258444D + 2255 .LASF41: + 2256 0492 6770696F .ascii "gpio_rts\000" + 2256 5F727473 + 2256 00 + 2257 .LASF23: + 2258 049b 65787469 .ascii "exti_line\000" + 2258 5F6C696E + 2258 6500 + 2259 .LASF40: + 2260 04a5 646D615F .ascii "dma_rx\000" + 2260 727800 + 2261 .LASF93: + 2262 04ac 49544D5F .ascii "ITM_RxBuffer\000" + 2262 52784275 + 2262 66666572 + 2262 00 + 2263 .LASF54: + 2264 04b9 5749534D .ascii "WISMART_MCU_FREQ_48_HSE\000" + 2264 4152545F + 2264 4D43555F + 2264 46524551 + 2264 5F34385F + 2265 .LASF0: + 2266 04d1 756E7369 .ascii "unsigned int\000" + 2266 676E6564 + 2266 20696E74 + 2266 00 + 2267 .LASF42: + 2268 04de 7769736D .ascii "wismart_hwif_usart_t\000" + 2268 6172745F + 2268 68776966 + 2268 5F757361 + 2268 72745F74 + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 45 + + + 2269 .LASF58: + 2270 04f3 5749534D .ascii "WISMART_MCU_FREQ_48_HSI\000" + 2270 4152545F + 2270 4D43555F + 2270 46524551 + 2270 5F34385F + 2271 .LASF30: + 2272 050b 69745F63 .ascii "it_complete\000" + 2272 6F6D706C + 2272 65746500 + 2273 .LASF71: + 2274 0517 56656374 .ascii "VectorD4\000" + 2274 6F724434 + 2274 00 + 2275 .LASF90: + 2276 0520 48617264 .ascii "HardFaultVector\000" + 2276 4661756C + 2276 74566563 + 2276 746F7200 + 2277 .LASF72: + 2278 0530 56656374 .ascii "Vector58\000" + 2278 6F723538 + 2278 00 + 2279 .LASF86: + 2280 0539 62757474 .ascii "buttons_process\000" + 2280 6F6E735F + 2280 70726F63 + 2280 65737300 + 2281 .LASF45: + 2282 0549 66735F61 .ascii "fs_ahb\000" + 2282 686200 + 2283 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\cc5PSsIR.s page 46 + + +DEFINED SYMBOLS + *ABS*:00000000 main.c +C:\cygwin\tmp\cc5PSsIR.s:19 .text.NMIVector:00000000 $t +C:\cygwin\tmp\cc5PSsIR.s:25 .text.NMIVector:00000000 NMIVector +C:\cygwin\tmp\cc5PSsIR.s:47 .text.NMIVector:0000000c $d +C:\cygwin\tmp\cc5PSsIR.s:52 .text.MemManageVector:00000000 $t +C:\cygwin\tmp\cc5PSsIR.s:58 .text.MemManageVector:00000000 MemManageVector +C:\cygwin\tmp\cc5PSsIR.s:79 .text.MemManageVector:0000000c $d +C:\cygwin\tmp\cc5PSsIR.s:84 .text.BusFaultVector:00000000 $t +C:\cygwin\tmp\cc5PSsIR.s:90 .text.BusFaultVector:00000000 BusFaultVector +C:\cygwin\tmp\cc5PSsIR.s:111 .text.BusFaultVector:0000000c $d +C:\cygwin\tmp\cc5PSsIR.s:116 .text.UsageFaultVector:00000000 $t +C:\cygwin\tmp\cc5PSsIR.s:122 .text.UsageFaultVector:00000000 UsageFaultVector +C:\cygwin\tmp\cc5PSsIR.s:143 .text.UsageFaultVector:0000000c $d +C:\cygwin\tmp\cc5PSsIR.s:148 .text.HardFaultVector:00000000 $t +C:\cygwin\tmp\cc5PSsIR.s:154 .text.HardFaultVector:00000000 HardFaultVector +C:\cygwin\tmp\cc5PSsIR.s:166 .text.VectorD4:00000000 $t +C:\cygwin\tmp\cc5PSsIR.s:172 .text.VectorD4:00000000 VectorD4 +C:\cygwin\tmp\cc5PSsIR.s:196 .text.Vector58:00000000 $t +C:\cygwin\tmp\cc5PSsIR.s:202 .text.Vector58:00000000 Vector58 +C:\cygwin\tmp\cc5PSsIR.s:225 .text.Vector78:00000000 $t +C:\cygwin\tmp\cc5PSsIR.s:231 .text.Vector78:00000000 Vector78 +C:\cygwin\tmp\cc5PSsIR.s:254 .text.Vector7C:00000000 $t +C:\cygwin\tmp\cc5PSsIR.s:260 .text.Vector7C:00000000 Vector7C +C:\cygwin\tmp\cc5PSsIR.s:283 .text.initLibwismart:00000000 $t +C:\cygwin\tmp\cc5PSsIR.s:289 .text.initLibwismart:00000000 initLibwismart +C:\cygwin\tmp\cc5PSsIR.s:325 .text.startup.main:00000000 $t +C:\cygwin\tmp\cc5PSsIR.s:331 .text.startup.main:00000000 main +C:\cygwin\tmp\cc5PSsIR.s:369 .rodata.str1.4:00000000 $d + .debug_frame:00000010 $d + +UNDEFINED SYMBOLS +print +libwismart_UART_IRQHandler +_port_irq_epilogue +libwismart_WiFi_IRQHandler +libwismart_UART_TXDMA_IRQHandler +libwismart_UART_RXDMA_IRQHandler +libwismart_GetDefaultHWIF +memcpy +libwismart_Init +libwismart_PowerSave_Enable +libwismart_PowerSave_HigherProfile +buttons_init +buttons_process +chThdSleep diff --git a/Project/applications/smartcities/build/lst/nvic.lst b/Project/applications/smartcities/build/lst/nvic.lst new file mode 100644 index 0000000..09665ef --- /dev/null +++ b/Project/applications/smartcities/build/lst/nvic.lst @@ -0,0 +1,1508 @@ +ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "nvic.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text.nvicEnableVector,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .global nvicEnableVector + 22 .thumb + 23 .thumb_func + 24 .type nvicEnableVector, %function + 25 nvicEnableVector: + 26 .LFB7: + 27 .file 1 "../..//os/ports/common/ARMCMx/nvic.c" + 28 .loc 1 46 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .LVL0: + 34 .loc 1 47 0 + 35 0000 00F00303 and r3, r0, #3 + 36 .loc 1 46 0 + 37 0004 70B4 push {r4, r5, r6} + 38 .LCFI0: + 39 .cfi_def_cfa_offset 12 + 40 .cfi_offset 4, -12 + 41 .cfi_offset 5, -8 + 42 .cfi_offset 6, -4 + 43 .loc 1 47 0 + 44 0006 DB00 lsls r3, r3, #3 + 45 .LVL1: + 46 .loc 1 49 0 + 47 0008 FF25 movs r5, #255 + 48 000a 05FA03F5 lsl r5, r5, r3 + 49 000e 01FA03F1 lsl r1, r1, r3 + 50 .LVL2: + 51 .loc 1 50 0 + 52 0012 0122 movs r2, #1 + 53 0014 00F01F03 and r3, r0, #31 + 54 .LVL3: + 55 0018 02FA03F2 lsl r2, r2, r3 + 56 .loc 1 49 0 + 57 001c 8408 lsrs r4, r0, #2 + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 2 + + + 58 001e 4FF46143 mov r3, #57600 + 59 0022 CEF20003 movt r3, 57344 + 60 0026 C034 adds r4, r4, #192 + 61 0028 53F82460 ldr r6, [r3, r4, lsl #2] + 62 .loc 1 50 0 + 63 002c 4009 lsrs r0, r0, #5 + 64 .LVL4: + 65 .loc 1 49 0 + 66 002e 26EA0505 bic r5, r6, r5 + 67 0032 0D43 orrs r5, r5, r1 + 68 .loc 1 50 0 + 69 0034 00F16006 add r6, r0, #96 + 70 .loc 1 49 0 + 71 0038 43F82450 str r5, [r3, r4, lsl #2] + 72 .loc 1 50 0 + 73 003c 43F82620 str r2, [r3, r6, lsl #2] + 74 .loc 1 51 0 + 75 0040 43F82020 str r2, [r3, r0, lsl #2] + 76 .loc 1 52 0 + 77 0044 70BC pop {r4, r5, r6} + 78 0046 7047 bx lr + 79 .cfi_endproc + 80 .LFE7: + 81 .size nvicEnableVector, .-nvicEnableVector + 82 0048 AFF30080 .section .text.nvicDisableVector,"ax",%progbits + 82 AFF30080 + 83 .align 2 + 84 .p2align 4,,15 + 85 .global nvicDisableVector + 86 .thumb + 87 .thumb_func + 88 .type nvicDisableVector, %function + 89 nvicDisableVector: + 90 .LFB8: + 91 .loc 1 60 0 + 92 .cfi_startproc + 93 @ args = 0, pretend = 0, frame = 0 + 94 @ frame_needed = 0, uses_anonymous_args = 0 + 95 @ link register save eliminated. + 96 .LVL5: + 97 0000 10B4 push {r4} + 98 .LCFI1: + 99 .cfi_def_cfa_offset 4 + 100 .cfi_offset 4, -4 + 101 .loc 1 63 0 + 102 0002 00F01F03 and r3, r0, #31 + 103 0006 0124 movs r4, #1 + 104 0008 04FA03F4 lsl r4, r4, r3 + 105 .loc 1 61 0 + 106 000c 00F00302 and r2, r0, #3 + 107 .loc 1 64 0 + 108 0010 FF23 movs r3, #255 + 109 .loc 1 61 0 + 110 0012 D200 lsls r2, r2, #3 + 111 .LVL6: + 112 .loc 1 64 0 + 113 0014 03FA02F2 lsl r2, r3, r2 + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 3 + + + 114 .LVL7: + 115 .loc 1 63 0 + 116 0018 4109 lsrs r1, r0, #5 + 117 001a 4FF46143 mov r3, #57600 + 118 001e CEF20003 movt r3, 57344 + 119 0022 2031 adds r1, r1, #32 + 120 .loc 1 64 0 + 121 0024 8008 lsrs r0, r0, #2 + 122 .LVL8: + 123 .loc 1 63 0 + 124 0026 43F82140 str r4, [r3, r1, lsl #2] + 125 .loc 1 64 0 + 126 002a C030 adds r0, r0, #192 + 127 002c 53F82010 ldr r1, [r3, r0, lsl #2] + 128 0030 21EA0202 bic r2, r1, r2 + 129 0034 43F82020 str r2, [r3, r0, lsl #2] + 130 .loc 1 65 0 + 131 0038 10BC pop {r4} + 132 003a 7047 bx lr + 133 .cfi_endproc + 134 .LFE8: + 135 .size nvicDisableVector, .-nvicDisableVector + 136 003c AFF30080 .section .text.nvicSetSystemHandlerPriority,"ax",%progbits + 137 .align 2 + 138 .p2align 4,,15 + 139 .global nvicSetSystemHandlerPriority + 140 .thumb + 141 .thumb_func + 142 .type nvicSetSystemHandlerPriority, %function + 143 nvicSetSystemHandlerPriority: + 144 .LFB9: + 145 .loc 1 74 0 + 146 .cfi_startproc + 147 @ args = 0, pretend = 0, frame = 0 + 148 @ frame_needed = 0, uses_anonymous_args = 0 + 149 @ link register save eliminated. + 150 .LVL9: + 151 .loc 1 75 0 + 152 0000 00F00303 and r3, r0, #3 + 153 0004 DB00 lsls r3, r3, #3 + 154 .LVL10: + 155 .loc 1 78 0 + 156 0006 FF22 movs r2, #255 + 157 0008 02FA03F2 lsl r2, r2, r3 + 158 000c 01FA03F1 lsl r1, r1, r3 + 159 .LVL11: + 160 .loc 1 77 0 + 161 0010 8008 lsrs r0, r0, #2 + 162 .LVL12: + 163 0012 4FF46D43 mov r3, #60672 + 164 .LVL13: + 165 0016 CEF20003 movt r3, 57344 + 166 001a 0630 adds r0, r0, #6 + 167 .loc 1 74 0 + 168 001c 10B4 push {r4} + 169 .LCFI2: + 170 .cfi_def_cfa_offset 4 + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 4 + + + 171 .cfi_offset 4, -4 + 172 .loc 1 77 0 + 173 001e 53F82040 ldr r4, [r3, r0, lsl #2] + 174 0022 24EA0202 bic r2, r4, r2 + 175 .loc 1 78 0 + 176 0026 0A43 orrs r2, r2, r1 + 177 .loc 1 77 0 + 178 0028 43F82020 str r2, [r3, r0, lsl #2] + 179 .loc 1 79 0 + 180 002c 10BC pop {r4} + 181 002e 7047 bx lr + 182 .cfi_endproc + 183 .LFE9: + 184 .size nvicSetSystemHandlerPriority, .-nvicSetSystemHandlerPriority + 185 .text + 186 .Letext0: + 187 .file 2 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 188 .file 3 "../..//os/ports/common/ARMCMx/nvic.h" + 189 .section .debug_info,"",%progbits + 190 .Ldebug_info0: + 191 0000 4A040000 .4byte 0x44a + 192 0004 0200 .2byte 0x2 + 193 0006 00000000 .4byte .Ldebug_abbrev0 + 194 000a 04 .byte 0x4 + 195 000b 01 .uleb128 0x1 + 196 000c 9C010000 .4byte .LASF45 + 197 0010 01 .byte 0x1 + 198 0011 0A000000 .4byte .LASF46 + 199 0015 67000000 .4byte .LASF47 + 200 0019 00000000 .4byte .Ldebug_ranges0+0 + 201 001d 00000000 .4byte 0 + 202 0021 00000000 .4byte 0 + 203 0025 00000000 .4byte .Ldebug_line0 + 204 0029 02 .uleb128 0x2 + 205 002a 04 .byte 0x4 + 206 002b 05 .byte 0x5 + 207 002c 696E7400 .ascii "int\000" + 208 0030 03 .uleb128 0x3 + 209 0031 04 .byte 0x4 + 210 0032 07 .byte 0x7 + 211 0033 2C010000 .4byte .LASF0 + 212 0037 03 .uleb128 0x3 + 213 0038 01 .byte 0x1 + 214 0039 06 .byte 0x6 + 215 003a CF010000 .4byte .LASF1 + 216 003e 03 .uleb128 0x3 + 217 003f 01 .byte 0x1 + 218 0040 08 .byte 0x8 + 219 0041 AA000000 .4byte .LASF2 + 220 0045 03 .uleb128 0x3 + 221 0046 02 .byte 0x2 + 222 0047 05 .byte 0x5 + 223 0048 22010000 .4byte .LASF3 + 224 004c 03 .uleb128 0x3 + 225 004d 02 .byte 0x2 + 226 004e 07 .byte 0x7 + 227 004f E8000000 .4byte .LASF4 + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 5 + + + 228 0053 03 .uleb128 0x3 + 229 0054 04 .byte 0x4 + 230 0055 05 .byte 0x5 + 231 0056 C1010000 .4byte .LASF5 + 232 005a 04 .uleb128 0x4 + 233 005b B8010000 .4byte .LASF9 + 234 005f 02 .byte 0x2 + 235 0060 50 .byte 0x50 + 236 0061 65000000 .4byte 0x65 + 237 0065 03 .uleb128 0x3 + 238 0066 04 .byte 0x4 + 239 0067 07 .byte 0x7 + 240 0068 05010000 .4byte .LASF6 + 241 006c 03 .uleb128 0x3 + 242 006d 08 .byte 0x8 + 243 006e 05 .byte 0x5 + 244 006f 83010000 .4byte .LASF7 + 245 0073 03 .uleb128 0x3 + 246 0074 08 .byte 0x8 + 247 0075 07 .byte 0x7 + 248 0076 43010000 .4byte .LASF8 + 249 007a 04 .uleb128 0x4 + 250 007b 5F000000 .4byte .LASF10 + 251 007f 03 .byte 0x3 + 252 0080 3A .byte 0x3a + 253 0081 85000000 .4byte 0x85 + 254 0085 05 .uleb128 0x5 + 255 0086 5A000000 .4byte 0x5a + 256 008a 06 .uleb128 0x6 + 257 008b 040E .2byte 0xe04 + 258 008d 03 .byte 0x3 + 259 008e 6A .byte 0x6a + 260 008f 55010000 .4byte 0x155 + 261 0093 07 .uleb128 0x7 + 262 0094 A8010000 .4byte .LASF11 + 263 0098 03 .byte 0x3 + 264 0099 6B .byte 0x6b + 265 009a 6C010000 .4byte 0x16c + 266 009e 02 .byte 0x2 + 267 009f 23 .byte 0x23 + 268 00a0 00 .uleb128 0 + 269 00a1 07 .uleb128 0x7 + 270 00a2 B8000000 .4byte .LASF12 + 271 00a6 03 .byte 0x3 + 272 00a7 6C .byte 0x6c + 273 00a8 81010000 .4byte 0x181 + 274 00ac 02 .byte 0x2 + 275 00ad 23 .byte 0x23 + 276 00ae 20 .uleb128 0x20 + 277 00af 07 .uleb128 0x7 + 278 00b0 5A000000 .4byte .LASF13 + 279 00b4 03 .byte 0x3 + 280 00b5 6D .byte 0x6d + 281 00b6 86010000 .4byte 0x186 + 282 00ba 03 .byte 0x3 + 283 00bb 23 .byte 0x23 + 284 00bc 8001 .uleb128 0x80 + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 6 + + + 285 00be 07 .uleb128 0x7 + 286 00bf C0000000 .4byte .LASF14 + 287 00c3 03 .byte 0x3 + 288 00c4 6E .byte 0x6e + 289 00c5 8B010000 .4byte 0x18b + 290 00c9 03 .byte 0x3 + 291 00ca 23 .byte 0x23 + 292 00cb A001 .uleb128 0xa0 + 293 00cd 07 .uleb128 0x7 + 294 00ce 39010000 .4byte .LASF15 + 295 00d2 03 .byte 0x3 + 296 00d3 6F .byte 0x6f + 297 00d4 90010000 .4byte 0x190 + 298 00d8 03 .byte 0x3 + 299 00d9 23 .byte 0x23 + 300 00da 8002 .uleb128 0x100 + 301 00dc 07 .uleb128 0x7 + 302 00dd C8000000 .4byte .LASF16 + 303 00e1 03 .byte 0x3 + 304 00e2 70 .byte 0x70 + 305 00e3 95010000 .4byte 0x195 + 306 00e7 03 .byte 0x3 + 307 00e8 23 .byte 0x23 + 308 00e9 A002 .uleb128 0x120 + 309 00eb 07 .uleb128 0x7 + 310 00ec 05000000 .4byte .LASF17 + 311 00f0 03 .byte 0x3 + 312 00f1 71 .byte 0x71 + 313 00f2 9A010000 .4byte 0x19a + 314 00f6 03 .byte 0x3 + 315 00f7 23 .byte 0x23 + 316 00f8 8003 .uleb128 0x180 + 317 00fa 07 .uleb128 0x7 + 318 00fb D0000000 .4byte .LASF18 + 319 00ff 03 .byte 0x3 + 320 0100 72 .byte 0x72 + 321 0101 9F010000 .4byte 0x19f + 322 0105 03 .byte 0x3 + 323 0106 23 .byte 0x23 + 324 0107 A003 .uleb128 0x1a0 + 325 0109 07 .uleb128 0x7 + 326 010a F8010000 .4byte .LASF19 + 327 010e 03 .byte 0x3 + 328 010f 73 .byte 0x73 + 329 0110 A4010000 .4byte 0x1a4 + 330 0114 03 .byte 0x3 + 331 0115 23 .byte 0x23 + 332 0116 8004 .uleb128 0x200 + 333 0118 07 .uleb128 0x7 + 334 0119 D8000000 .4byte .LASF20 + 335 011d 03 .byte 0x3 + 336 011e 74 .byte 0x74 + 337 011f B9010000 .4byte 0x1b9 + 338 0123 03 .byte 0x3 + 339 0124 23 .byte 0x23 + 340 0125 A004 .uleb128 0x220 + 341 0127 08 .uleb128 0x8 + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 7 + + + 342 0128 49505200 .ascii "IPR\000" + 343 012c 03 .byte 0x3 + 344 012d 75 .byte 0x75 + 345 012e CE010000 .4byte 0x1ce + 346 0132 03 .byte 0x3 + 347 0133 23 .byte 0x23 + 348 0134 8006 .uleb128 0x300 + 349 0136 07 .uleb128 0x7 + 350 0137 E0000000 .4byte .LASF21 + 351 013b 03 .byte 0x3 + 352 013c 76 .byte 0x76 + 353 013d E4010000 .4byte 0x1e4 + 354 0141 03 .byte 0x3 + 355 0142 23 .byte 0x23 + 356 0143 F007 .uleb128 0x3f0 + 357 0145 07 .uleb128 0x7 + 358 0146 1D010000 .4byte .LASF22 + 359 014a 03 .byte 0x3 + 360 014b 77 .byte 0x77 + 361 014c 7A000000 .4byte 0x7a + 362 0150 03 .byte 0x3 + 363 0151 23 .byte 0x23 + 364 0152 801C .uleb128 0xe00 + 365 0154 00 .byte 0 + 366 0155 09 .uleb128 0x9 + 367 0156 7A000000 .4byte 0x7a + 368 015a 65010000 .4byte 0x165 + 369 015e 0A .uleb128 0xa + 370 015f 65010000 .4byte 0x165 + 371 0163 07 .byte 0x7 + 372 0164 00 .byte 0 + 373 0165 03 .uleb128 0x3 + 374 0166 04 .byte 0x4 + 375 0167 07 .byte 0x7 + 376 0168 7A010000 .4byte .LASF23 + 377 016c 05 .uleb128 0x5 + 378 016d 55010000 .4byte 0x155 + 379 0171 09 .uleb128 0x9 + 380 0172 7A000000 .4byte 0x7a + 381 0176 81010000 .4byte 0x181 + 382 017a 0A .uleb128 0xa + 383 017b 65010000 .4byte 0x165 + 384 017f 17 .byte 0x17 + 385 0180 00 .byte 0 + 386 0181 05 .uleb128 0x5 + 387 0182 71010000 .4byte 0x171 + 388 0186 05 .uleb128 0x5 + 389 0187 55010000 .4byte 0x155 + 390 018b 05 .uleb128 0x5 + 391 018c 71010000 .4byte 0x171 + 392 0190 05 .uleb128 0x5 + 393 0191 55010000 .4byte 0x155 + 394 0195 05 .uleb128 0x5 + 395 0196 71010000 .4byte 0x171 + 396 019a 05 .uleb128 0x5 + 397 019b 55010000 .4byte 0x155 + 398 019f 05 .uleb128 0x5 + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 8 + + + 399 01a0 71010000 .4byte 0x171 + 400 01a4 05 .uleb128 0x5 + 401 01a5 55010000 .4byte 0x155 + 402 01a9 09 .uleb128 0x9 + 403 01aa 7A000000 .4byte 0x7a + 404 01ae B9010000 .4byte 0x1b9 + 405 01b2 0A .uleb128 0xa + 406 01b3 65010000 .4byte 0x165 + 407 01b7 37 .byte 0x37 + 408 01b8 00 .byte 0 + 409 01b9 05 .uleb128 0x5 + 410 01ba A9010000 .4byte 0x1a9 + 411 01be 09 .uleb128 0x9 + 412 01bf 7A000000 .4byte 0x7a + 413 01c3 CE010000 .4byte 0x1ce + 414 01c7 0A .uleb128 0xa + 415 01c8 65010000 .4byte 0x165 + 416 01cc 3B .byte 0x3b + 417 01cd 00 .byte 0 + 418 01ce 05 .uleb128 0x5 + 419 01cf BE010000 .4byte 0x1be + 420 01d3 09 .uleb128 0x9 + 421 01d4 7A000000 .4byte 0x7a + 422 01d8 E4010000 .4byte 0x1e4 + 423 01dc 0B .uleb128 0xb + 424 01dd 65010000 .4byte 0x165 + 425 01e1 8302 .2byte 0x283 + 426 01e3 00 .byte 0 + 427 01e4 05 .uleb128 0x5 + 428 01e5 D3010000 .4byte 0x1d3 + 429 01e9 04 .uleb128 0x4 + 430 01ea 4C000000 .4byte .LASF24 + 431 01ee 03 .byte 0x3 + 432 01ef 78 .byte 0x78 + 433 01f0 8A000000 .4byte 0x8a + 434 01f4 0C .uleb128 0xc + 435 01f5 8C .byte 0x8c + 436 01f6 03 .byte 0x3 + 437 01f7 89 .byte 0x89 + 438 01f8 24030000 .4byte 0x324 + 439 01fc 07 .uleb128 0x7 + 440 01fd 91010000 .4byte .LASF25 + 441 0201 03 .byte 0x3 + 442 0202 8A .byte 0x8a + 443 0203 7A000000 .4byte 0x7a + 444 0207 02 .byte 0x2 + 445 0208 23 .byte 0x23 + 446 0209 00 .uleb128 0 + 447 020a 07 .uleb128 0x7 + 448 020b 5A010000 .4byte .LASF26 + 449 020f 03 .byte 0x3 + 450 0210 8B .byte 0x8b + 451 0211 7A000000 .4byte 0x7a + 452 0215 02 .byte 0x2 + 453 0216 23 .byte 0x23 + 454 0217 04 .uleb128 0x4 + 455 0218 07 .uleb128 0x7 + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 9 + + + 456 0219 55000000 .4byte .LASF27 + 457 021d 03 .byte 0x3 + 458 021e 8C .byte 0x8c + 459 021f 7A000000 .4byte 0x7a + 460 0223 02 .byte 0x2 + 461 0224 23 .byte 0x23 + 462 0225 08 .uleb128 0x8 + 463 0226 07 .uleb128 0x7 + 464 0227 67010000 .4byte .LASF28 + 465 022b 03 .byte 0x3 + 466 022c 8D .byte 0x8d + 467 022d 7A000000 .4byte 0x7a + 468 0231 02 .byte 0x2 + 469 0232 23 .byte 0x23 + 470 0233 0C .uleb128 0xc + 471 0234 08 .uleb128 0x8 + 472 0235 53435200 .ascii "SCR\000" + 473 0239 03 .byte 0x3 + 474 023a 8E .byte 0x8e + 475 023b 7A000000 .4byte 0x7a + 476 023f 02 .byte 0x2 + 477 0240 23 .byte 0x23 + 478 0241 10 .uleb128 0x10 + 479 0242 08 .uleb128 0x8 + 480 0243 43435200 .ascii "CCR\000" + 481 0247 03 .byte 0x3 + 482 0248 8F .byte 0x8f + 483 0249 7A000000 .4byte 0x7a + 484 024d 02 .byte 0x2 + 485 024e 23 .byte 0x23 + 486 024f 14 .uleb128 0x14 + 487 0250 07 .uleb128 0x7 + 488 0251 CA010000 .4byte .LASF29 + 489 0255 03 .byte 0x3 + 490 0256 90 .byte 0x90 + 491 0257 34030000 .4byte 0x334 + 492 025b 02 .byte 0x2 + 493 025c 23 .byte 0x23 + 494 025d 18 .uleb128 0x18 + 495 025e 07 .uleb128 0x7 + 496 025f 34000000 .4byte .LASF30 + 497 0263 03 .byte 0x3 + 498 0264 91 .byte 0x91 + 499 0265 7A000000 .4byte 0x7a + 500 0269 02 .byte 0x2 + 501 026a 23 .byte 0x23 + 502 026b 24 .uleb128 0x24 + 503 026c 07 .uleb128 0x7 + 504 026d FB000000 .4byte .LASF31 + 505 0271 03 .byte 0x3 + 506 0272 92 .byte 0x92 + 507 0273 7A000000 .4byte 0x7a + 508 0277 02 .byte 0x2 + 509 0278 23 .byte 0x23 + 510 0279 28 .uleb128 0x28 + 511 027a 07 .uleb128 0x7 + 512 027b 00010000 .4byte .LASF32 + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 10 + + + 513 027f 03 .byte 0x3 + 514 0280 93 .byte 0x93 + 515 0281 7A000000 .4byte 0x7a + 516 0285 02 .byte 0x2 + 517 0286 23 .byte 0x23 + 518 0287 2C .uleb128 0x2c + 519 0288 07 .uleb128 0x7 + 520 0289 3E010000 .4byte .LASF33 + 521 028d 03 .byte 0x3 + 522 028e 94 .byte 0x94 + 523 028f 7A000000 .4byte 0x7a + 524 0293 02 .byte 0x2 + 525 0294 23 .byte 0x23 + 526 0295 30 .uleb128 0x30 + 527 0296 07 .uleb128 0x7 + 528 0297 B2010000 .4byte .LASF34 + 529 029b 03 .byte 0x3 + 530 029c 95 .byte 0x95 + 531 029d 7A000000 .4byte 0x7a + 532 02a1 02 .byte 0x2 + 533 02a2 23 .byte 0x23 + 534 02a3 34 .uleb128 0x34 + 535 02a4 07 .uleb128 0x7 + 536 02a5 6D010000 .4byte .LASF35 + 537 02a9 03 .byte 0x3 + 538 02aa 96 .byte 0x96 + 539 02ab 7A000000 .4byte 0x7a + 540 02af 02 .byte 0x2 + 541 02b0 23 .byte 0x23 + 542 02b1 38 .uleb128 0x38 + 543 02b2 07 .uleb128 0x7 + 544 02b3 AD010000 .4byte .LASF36 + 545 02b7 03 .byte 0x3 + 546 02b8 97 .byte 0x97 + 547 02b9 7A000000 .4byte 0x7a + 548 02bd 02 .byte 0x2 + 549 02be 23 .byte 0x23 + 550 02bf 3C .uleb128 0x3c + 551 02c0 08 .uleb128 0x8 + 552 02c1 50465200 .ascii "PFR\000" + 553 02c5 03 .byte 0x3 + 554 02c6 98 .byte 0x98 + 555 02c7 49030000 .4byte 0x349 + 556 02cb 02 .byte 0x2 + 557 02cc 23 .byte 0x23 + 558 02cd 40 .uleb128 0x40 + 559 02ce 08 .uleb128 0x8 + 560 02cf 44465200 .ascii "DFR\000" + 561 02d3 03 .byte 0x3 + 562 02d4 99 .byte 0x99 + 563 02d5 7A000000 .4byte 0x7a + 564 02d9 02 .byte 0x2 + 565 02da 23 .byte 0x23 + 566 02db 48 .uleb128 0x48 + 567 02dc 08 .uleb128 0x8 + 568 02dd 41445200 .ascii "ADR\000" + 569 02e1 03 .byte 0x3 + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 11 + + + 570 02e2 9A .byte 0x9a + 571 02e3 7A000000 .4byte 0x7a + 572 02e7 02 .byte 0x2 + 573 02e8 23 .byte 0x23 + 574 02e9 4C .uleb128 0x4c + 575 02ea 07 .uleb128 0x7 + 576 02eb 2F000000 .4byte .LASF37 + 577 02ef 03 .byte 0x3 + 578 02f0 9B .byte 0x9b + 579 02f1 5E030000 .4byte 0x35e + 580 02f5 02 .byte 0x2 + 581 02f6 23 .byte 0x23 + 582 02f7 50 .uleb128 0x50 + 583 02f8 08 .uleb128 0x8 + 584 02f9 53415200 .ascii "SAR\000" + 585 02fd 03 .byte 0x3 + 586 02fe 9C .byte 0x9c + 587 02ff 73030000 .4byte 0x373 + 588 0303 02 .byte 0x2 + 589 0304 23 .byte 0x23 + 590 0305 60 .uleb128 0x60 + 591 0306 07 .uleb128 0x7 + 592 0307 B8000000 .4byte .LASF12 + 593 030b 03 .byte 0x3 + 594 030c 9D .byte 0x9d + 595 030d 78030000 .4byte 0x378 + 596 0311 02 .byte 0x2 + 597 0312 23 .byte 0x23 + 598 0313 74 .uleb128 0x74 + 599 0314 07 .uleb128 0x7 + 600 0315 17010000 .4byte .LASF38 + 601 0319 03 .byte 0x3 + 602 031a 9E .byte 0x9e + 603 031b 7A000000 .4byte 0x7a + 604 031f 03 .byte 0x3 + 605 0320 23 .byte 0x23 + 606 0321 8801 .uleb128 0x88 + 607 0323 00 .byte 0 + 608 0324 09 .uleb128 0x9 + 609 0325 7A000000 .4byte 0x7a + 610 0329 34030000 .4byte 0x334 + 611 032d 0A .uleb128 0xa + 612 032e 65010000 .4byte 0x165 + 613 0332 02 .byte 0x2 + 614 0333 00 .byte 0 + 615 0334 05 .uleb128 0x5 + 616 0335 24030000 .4byte 0x324 + 617 0339 09 .uleb128 0x9 + 618 033a 7A000000 .4byte 0x7a + 619 033e 49030000 .4byte 0x349 + 620 0342 0A .uleb128 0xa + 621 0343 65010000 .4byte 0x165 + 622 0347 01 .byte 0x1 + 623 0348 00 .byte 0 + 624 0349 05 .uleb128 0x5 + 625 034a 39030000 .4byte 0x339 + 626 034e 09 .uleb128 0x9 + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 12 + + + 627 034f 7A000000 .4byte 0x7a + 628 0353 5E030000 .4byte 0x35e + 629 0357 0A .uleb128 0xa + 630 0358 65010000 .4byte 0x165 + 631 035c 03 .byte 0x3 + 632 035d 00 .byte 0 + 633 035e 05 .uleb128 0x5 + 634 035f 4E030000 .4byte 0x34e + 635 0363 09 .uleb128 0x9 + 636 0364 7A000000 .4byte 0x7a + 637 0368 73030000 .4byte 0x373 + 638 036c 0A .uleb128 0xa + 639 036d 65010000 .4byte 0x165 + 640 0371 04 .byte 0x4 + 641 0372 00 .byte 0 + 642 0373 05 .uleb128 0x5 + 643 0374 63030000 .4byte 0x363 + 644 0378 05 .uleb128 0x5 + 645 0379 63030000 .4byte 0x363 + 646 037d 04 .uleb128 0x4 + 647 037e 5F010000 .4byte .LASF39 + 648 0382 03 .byte 0x3 + 649 0383 9F .byte 0x9f + 650 0384 F4010000 .4byte 0x1f4 + 651 0388 03 .uleb128 0x3 + 652 0389 01 .byte 0x1 + 653 038a 08 .byte 0x8 + 654 038b 97010000 .4byte .LASF40 + 655 038f 0D .uleb128 0xd + 656 0390 01 .byte 0x1 + 657 0391 FD010000 .4byte .LASF42 + 658 0395 01 .byte 0x1 + 659 0396 2E .byte 0x2e + 660 0397 01 .byte 0x1 + 661 0398 00000000 .4byte .LFB7 + 662 039c 48000000 .4byte .LFE7 + 663 03a0 00000000 .4byte .LLST0 + 664 03a4 01 .byte 0x1 + 665 03a5 D4030000 .4byte 0x3d4 + 666 03a9 0E .uleb128 0xe + 667 03aa 6E00 .ascii "n\000" + 668 03ac 01 .byte 0x1 + 669 03ad 2E .byte 0x2e + 670 03ae 5A000000 .4byte 0x5a + 671 03b2 20000000 .4byte .LLST1 + 672 03b6 0F .uleb128 0xf + 673 03b7 00000000 .4byte .LASF41 + 674 03bb 01 .byte 0x1 + 675 03bc 2E .byte 0x2e + 676 03bd 5A000000 .4byte 0x5a + 677 03c1 41000000 .4byte .LLST2 + 678 03c5 10 .uleb128 0x10 + 679 03c6 736800 .ascii "sh\000" + 680 03c9 01 .byte 0x1 + 681 03ca 2F .byte 0x2f + 682 03cb 30000000 .4byte 0x30 + 683 03cf 62000000 .4byte .LLST3 + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 13 + + + 684 03d3 00 .byte 0 + 685 03d4 0D .uleb128 0xd + 686 03d5 01 .byte 0x1 + 687 03d6 3A000000 .4byte .LASF43 + 688 03da 01 .byte 0x1 + 689 03db 3C .byte 0x3c + 690 03dc 01 .byte 0x1 + 691 03dd 00000000 .4byte .LFB8 + 692 03e1 3C000000 .4byte .LFE8 + 693 03e5 A9000000 .4byte .LLST4 + 694 03e9 01 .byte 0x1 + 695 03ea 0A040000 .4byte 0x40a + 696 03ee 0E .uleb128 0xe + 697 03ef 6E00 .ascii "n\000" + 698 03f1 01 .byte 0x1 + 699 03f2 3C .byte 0x3c + 700 03f3 5A000000 .4byte 0x5a + 701 03f7 C9000000 .4byte .LLST5 + 702 03fb 10 .uleb128 0x10 + 703 03fc 736800 .ascii "sh\000" + 704 03ff 01 .byte 0x1 + 705 0400 3D .byte 0x3d + 706 0401 30000000 .4byte 0x30 + 707 0405 EA000000 .4byte .LLST6 + 708 0409 00 .byte 0 + 709 040a 11 .uleb128 0x11 + 710 040b 01 .byte 0x1 + 711 040c DB010000 .4byte .LASF48 + 712 0410 01 .byte 0x1 + 713 0411 4A .byte 0x4a + 714 0412 01 .byte 0x1 + 715 0413 00000000 .4byte .LFB9 + 716 0417 30000000 .4byte .LFE9 + 717 041b 31010000 .4byte .LLST7 + 718 041f 01 .byte 0x1 + 719 0420 0F .uleb128 0xf + 720 0421 72010000 .4byte .LASF44 + 721 0425 01 .byte 0x1 + 722 0426 4A .byte 0x4a + 723 0427 5A000000 .4byte 0x5a + 724 042b 51010000 .4byte .LLST8 + 725 042f 0F .uleb128 0xf + 726 0430 00000000 .4byte .LASF41 + 727 0434 01 .byte 0x1 + 728 0435 4A .byte 0x4a + 729 0436 5A000000 .4byte 0x5a + 730 043a 72010000 .4byte .LLST9 + 731 043e 10 .uleb128 0x10 + 732 043f 736800 .ascii "sh\000" + 733 0442 01 .byte 0x1 + 734 0443 4B .byte 0x4b + 735 0444 30000000 .4byte 0x30 + 736 0448 93010000 .4byte .LLST10 + 737 044c 00 .byte 0 + 738 044d 00 .byte 0 + 739 .section .debug_abbrev,"",%progbits + 740 .Ldebug_abbrev0: + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 14 + + + 741 0000 01 .uleb128 0x1 + 742 0001 11 .uleb128 0x11 + 743 0002 01 .byte 0x1 + 744 0003 25 .uleb128 0x25 + 745 0004 0E .uleb128 0xe + 746 0005 13 .uleb128 0x13 + 747 0006 0B .uleb128 0xb + 748 0007 03 .uleb128 0x3 + 749 0008 0E .uleb128 0xe + 750 0009 1B .uleb128 0x1b + 751 000a 0E .uleb128 0xe + 752 000b 55 .uleb128 0x55 + 753 000c 06 .uleb128 0x6 + 754 000d 11 .uleb128 0x11 + 755 000e 01 .uleb128 0x1 + 756 000f 52 .uleb128 0x52 + 757 0010 01 .uleb128 0x1 + 758 0011 10 .uleb128 0x10 + 759 0012 06 .uleb128 0x6 + 760 0013 00 .byte 0 + 761 0014 00 .byte 0 + 762 0015 02 .uleb128 0x2 + 763 0016 24 .uleb128 0x24 + 764 0017 00 .byte 0 + 765 0018 0B .uleb128 0xb + 766 0019 0B .uleb128 0xb + 767 001a 3E .uleb128 0x3e + 768 001b 0B .uleb128 0xb + 769 001c 03 .uleb128 0x3 + 770 001d 08 .uleb128 0x8 + 771 001e 00 .byte 0 + 772 001f 00 .byte 0 + 773 0020 03 .uleb128 0x3 + 774 0021 24 .uleb128 0x24 + 775 0022 00 .byte 0 + 776 0023 0B .uleb128 0xb + 777 0024 0B .uleb128 0xb + 778 0025 3E .uleb128 0x3e + 779 0026 0B .uleb128 0xb + 780 0027 03 .uleb128 0x3 + 781 0028 0E .uleb128 0xe + 782 0029 00 .byte 0 + 783 002a 00 .byte 0 + 784 002b 04 .uleb128 0x4 + 785 002c 16 .uleb128 0x16 + 786 002d 00 .byte 0 + 787 002e 03 .uleb128 0x3 + 788 002f 0E .uleb128 0xe + 789 0030 3A .uleb128 0x3a + 790 0031 0B .uleb128 0xb + 791 0032 3B .uleb128 0x3b + 792 0033 0B .uleb128 0xb + 793 0034 49 .uleb128 0x49 + 794 0035 13 .uleb128 0x13 + 795 0036 00 .byte 0 + 796 0037 00 .byte 0 + 797 0038 05 .uleb128 0x5 + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 15 + + + 798 0039 35 .uleb128 0x35 + 799 003a 00 .byte 0 + 800 003b 49 .uleb128 0x49 + 801 003c 13 .uleb128 0x13 + 802 003d 00 .byte 0 + 803 003e 00 .byte 0 + 804 003f 06 .uleb128 0x6 + 805 0040 13 .uleb128 0x13 + 806 0041 01 .byte 0x1 + 807 0042 0B .uleb128 0xb + 808 0043 05 .uleb128 0x5 + 809 0044 3A .uleb128 0x3a + 810 0045 0B .uleb128 0xb + 811 0046 3B .uleb128 0x3b + 812 0047 0B .uleb128 0xb + 813 0048 01 .uleb128 0x1 + 814 0049 13 .uleb128 0x13 + 815 004a 00 .byte 0 + 816 004b 00 .byte 0 + 817 004c 07 .uleb128 0x7 + 818 004d 0D .uleb128 0xd + 819 004e 00 .byte 0 + 820 004f 03 .uleb128 0x3 + 821 0050 0E .uleb128 0xe + 822 0051 3A .uleb128 0x3a + 823 0052 0B .uleb128 0xb + 824 0053 3B .uleb128 0x3b + 825 0054 0B .uleb128 0xb + 826 0055 49 .uleb128 0x49 + 827 0056 13 .uleb128 0x13 + 828 0057 38 .uleb128 0x38 + 829 0058 0A .uleb128 0xa + 830 0059 00 .byte 0 + 831 005a 00 .byte 0 + 832 005b 08 .uleb128 0x8 + 833 005c 0D .uleb128 0xd + 834 005d 00 .byte 0 + 835 005e 03 .uleb128 0x3 + 836 005f 08 .uleb128 0x8 + 837 0060 3A .uleb128 0x3a + 838 0061 0B .uleb128 0xb + 839 0062 3B .uleb128 0x3b + 840 0063 0B .uleb128 0xb + 841 0064 49 .uleb128 0x49 + 842 0065 13 .uleb128 0x13 + 843 0066 38 .uleb128 0x38 + 844 0067 0A .uleb128 0xa + 845 0068 00 .byte 0 + 846 0069 00 .byte 0 + 847 006a 09 .uleb128 0x9 + 848 006b 01 .uleb128 0x1 + 849 006c 01 .byte 0x1 + 850 006d 49 .uleb128 0x49 + 851 006e 13 .uleb128 0x13 + 852 006f 01 .uleb128 0x1 + 853 0070 13 .uleb128 0x13 + 854 0071 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 16 + + + 855 0072 00 .byte 0 + 856 0073 0A .uleb128 0xa + 857 0074 21 .uleb128 0x21 + 858 0075 00 .byte 0 + 859 0076 49 .uleb128 0x49 + 860 0077 13 .uleb128 0x13 + 861 0078 2F .uleb128 0x2f + 862 0079 0B .uleb128 0xb + 863 007a 00 .byte 0 + 864 007b 00 .byte 0 + 865 007c 0B .uleb128 0xb + 866 007d 21 .uleb128 0x21 + 867 007e 00 .byte 0 + 868 007f 49 .uleb128 0x49 + 869 0080 13 .uleb128 0x13 + 870 0081 2F .uleb128 0x2f + 871 0082 05 .uleb128 0x5 + 872 0083 00 .byte 0 + 873 0084 00 .byte 0 + 874 0085 0C .uleb128 0xc + 875 0086 13 .uleb128 0x13 + 876 0087 01 .byte 0x1 + 877 0088 0B .uleb128 0xb + 878 0089 0B .uleb128 0xb + 879 008a 3A .uleb128 0x3a + 880 008b 0B .uleb128 0xb + 881 008c 3B .uleb128 0x3b + 882 008d 0B .uleb128 0xb + 883 008e 01 .uleb128 0x1 + 884 008f 13 .uleb128 0x13 + 885 0090 00 .byte 0 + 886 0091 00 .byte 0 + 887 0092 0D .uleb128 0xd + 888 0093 2E .uleb128 0x2e + 889 0094 01 .byte 0x1 + 890 0095 3F .uleb128 0x3f + 891 0096 0C .uleb128 0xc + 892 0097 03 .uleb128 0x3 + 893 0098 0E .uleb128 0xe + 894 0099 3A .uleb128 0x3a + 895 009a 0B .uleb128 0xb + 896 009b 3B .uleb128 0x3b + 897 009c 0B .uleb128 0xb + 898 009d 27 .uleb128 0x27 + 899 009e 0C .uleb128 0xc + 900 009f 11 .uleb128 0x11 + 901 00a0 01 .uleb128 0x1 + 902 00a1 12 .uleb128 0x12 + 903 00a2 01 .uleb128 0x1 + 904 00a3 40 .uleb128 0x40 + 905 00a4 06 .uleb128 0x6 + 906 00a5 9742 .uleb128 0x2117 + 907 00a7 0C .uleb128 0xc + 908 00a8 01 .uleb128 0x1 + 909 00a9 13 .uleb128 0x13 + 910 00aa 00 .byte 0 + 911 00ab 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 17 + + + 912 00ac 0E .uleb128 0xe + 913 00ad 05 .uleb128 0x5 + 914 00ae 00 .byte 0 + 915 00af 03 .uleb128 0x3 + 916 00b0 08 .uleb128 0x8 + 917 00b1 3A .uleb128 0x3a + 918 00b2 0B .uleb128 0xb + 919 00b3 3B .uleb128 0x3b + 920 00b4 0B .uleb128 0xb + 921 00b5 49 .uleb128 0x49 + 922 00b6 13 .uleb128 0x13 + 923 00b7 02 .uleb128 0x2 + 924 00b8 06 .uleb128 0x6 + 925 00b9 00 .byte 0 + 926 00ba 00 .byte 0 + 927 00bb 0F .uleb128 0xf + 928 00bc 05 .uleb128 0x5 + 929 00bd 00 .byte 0 + 930 00be 03 .uleb128 0x3 + 931 00bf 0E .uleb128 0xe + 932 00c0 3A .uleb128 0x3a + 933 00c1 0B .uleb128 0xb + 934 00c2 3B .uleb128 0x3b + 935 00c3 0B .uleb128 0xb + 936 00c4 49 .uleb128 0x49 + 937 00c5 13 .uleb128 0x13 + 938 00c6 02 .uleb128 0x2 + 939 00c7 06 .uleb128 0x6 + 940 00c8 00 .byte 0 + 941 00c9 00 .byte 0 + 942 00ca 10 .uleb128 0x10 + 943 00cb 34 .uleb128 0x34 + 944 00cc 00 .byte 0 + 945 00cd 03 .uleb128 0x3 + 946 00ce 08 .uleb128 0x8 + 947 00cf 3A .uleb128 0x3a + 948 00d0 0B .uleb128 0xb + 949 00d1 3B .uleb128 0x3b + 950 00d2 0B .uleb128 0xb + 951 00d3 49 .uleb128 0x49 + 952 00d4 13 .uleb128 0x13 + 953 00d5 02 .uleb128 0x2 + 954 00d6 06 .uleb128 0x6 + 955 00d7 00 .byte 0 + 956 00d8 00 .byte 0 + 957 00d9 11 .uleb128 0x11 + 958 00da 2E .uleb128 0x2e + 959 00db 01 .byte 0x1 + 960 00dc 3F .uleb128 0x3f + 961 00dd 0C .uleb128 0xc + 962 00de 03 .uleb128 0x3 + 963 00df 0E .uleb128 0xe + 964 00e0 3A .uleb128 0x3a + 965 00e1 0B .uleb128 0xb + 966 00e2 3B .uleb128 0x3b + 967 00e3 0B .uleb128 0xb + 968 00e4 27 .uleb128 0x27 + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 18 + + + 969 00e5 0C .uleb128 0xc + 970 00e6 11 .uleb128 0x11 + 971 00e7 01 .uleb128 0x1 + 972 00e8 12 .uleb128 0x12 + 973 00e9 01 .uleb128 0x1 + 974 00ea 40 .uleb128 0x40 + 975 00eb 06 .uleb128 0x6 + 976 00ec 9742 .uleb128 0x2117 + 977 00ee 0C .uleb128 0xc + 978 00ef 00 .byte 0 + 979 00f0 00 .byte 0 + 980 00f1 00 .byte 0 + 981 .section .debug_loc,"",%progbits + 982 .Ldebug_loc0: + 983 .LLST0: + 984 0000 00000000 .4byte .LFB7 + 985 0004 06000000 .4byte .LCFI0 + 986 0008 0200 .2byte 0x2 + 987 000a 7D .byte 0x7d + 988 000b 00 .sleb128 0 + 989 000c 06000000 .4byte .LCFI0 + 990 0010 48000000 .4byte .LFE7 + 991 0014 0200 .2byte 0x2 + 992 0016 7D .byte 0x7d + 993 0017 0C .sleb128 12 + 994 0018 00000000 .4byte 0 + 995 001c 00000000 .4byte 0 + 996 .LLST1: + 997 0020 00000000 .4byte .LVL0 + 998 0024 2E000000 .4byte .LVL4 + 999 0028 0100 .2byte 0x1 + 1000 002a 50 .byte 0x50 + 1001 002b 2E000000 .4byte .LVL4 + 1002 002f 48000000 .4byte .LFE7 + 1003 0033 0400 .2byte 0x4 + 1004 0035 F3 .byte 0xf3 + 1005 0036 01 .uleb128 0x1 + 1006 0037 50 .byte 0x50 + 1007 0038 9F .byte 0x9f + 1008 0039 00000000 .4byte 0 + 1009 003d 00000000 .4byte 0 + 1010 .LLST2: + 1011 0041 00000000 .4byte .LVL0 + 1012 0045 12000000 .4byte .LVL2 + 1013 0049 0100 .2byte 0x1 + 1014 004b 51 .byte 0x51 + 1015 004c 12000000 .4byte .LVL2 + 1016 0050 48000000 .4byte .LFE7 + 1017 0054 0400 .2byte 0x4 + 1018 0056 F3 .byte 0xf3 + 1019 0057 01 .uleb128 0x1 + 1020 0058 51 .byte 0x51 + 1021 0059 9F .byte 0x9f + 1022 005a 00000000 .4byte 0 + 1023 005e 00000000 .4byte 0 + 1024 .LLST3: + 1025 0062 00000000 .4byte .LVL0 + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 19 + + + 1026 0066 08000000 .4byte .LVL1 + 1027 006a 0700 .2byte 0x7 + 1028 006c 70 .byte 0x70 + 1029 006d 00 .sleb128 0 + 1030 006e 33 .byte 0x33 + 1031 006f 1A .byte 0x1a + 1032 0070 33 .byte 0x33 + 1033 0071 24 .byte 0x24 + 1034 0072 9F .byte 0x9f + 1035 0073 08000000 .4byte .LVL1 + 1036 0077 18000000 .4byte .LVL3 + 1037 007b 0100 .2byte 0x1 + 1038 007d 53 .byte 0x53 + 1039 007e 18000000 .4byte .LVL3 + 1040 0082 2E000000 .4byte .LVL4 + 1041 0086 0700 .2byte 0x7 + 1042 0088 70 .byte 0x70 + 1043 0089 00 .sleb128 0 + 1044 008a 33 .byte 0x33 + 1045 008b 1A .byte 0x1a + 1046 008c 33 .byte 0x33 + 1047 008d 24 .byte 0x24 + 1048 008e 9F .byte 0x9f + 1049 008f 2E000000 .4byte .LVL4 + 1050 0093 48000000 .4byte .LFE7 + 1051 0097 0800 .2byte 0x8 + 1052 0099 F3 .byte 0xf3 + 1053 009a 01 .uleb128 0x1 + 1054 009b 50 .byte 0x50 + 1055 009c 33 .byte 0x33 + 1056 009d 1A .byte 0x1a + 1057 009e 33 .byte 0x33 + 1058 009f 24 .byte 0x24 + 1059 00a0 9F .byte 0x9f + 1060 00a1 00000000 .4byte 0 + 1061 00a5 00000000 .4byte 0 + 1062 .LLST4: + 1063 00a9 00000000 .4byte .LFB8 + 1064 00ad 02000000 .4byte .LCFI1 + 1065 00b1 0200 .2byte 0x2 + 1066 00b3 7D .byte 0x7d + 1067 00b4 00 .sleb128 0 + 1068 00b5 02000000 .4byte .LCFI1 + 1069 00b9 3C000000 .4byte .LFE8 + 1070 00bd 0200 .2byte 0x2 + 1071 00bf 7D .byte 0x7d + 1072 00c0 04 .sleb128 4 + 1073 00c1 00000000 .4byte 0 + 1074 00c5 00000000 .4byte 0 + 1075 .LLST5: + 1076 00c9 00000000 .4byte .LVL5 + 1077 00cd 26000000 .4byte .LVL8 + 1078 00d1 0100 .2byte 0x1 + 1079 00d3 50 .byte 0x50 + 1080 00d4 26000000 .4byte .LVL8 + 1081 00d8 3C000000 .4byte .LFE8 + 1082 00dc 0400 .2byte 0x4 + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 20 + + + 1083 00de F3 .byte 0xf3 + 1084 00df 01 .uleb128 0x1 + 1085 00e0 50 .byte 0x50 + 1086 00e1 9F .byte 0x9f + 1087 00e2 00000000 .4byte 0 + 1088 00e6 00000000 .4byte 0 + 1089 .LLST6: + 1090 00ea 00000000 .4byte .LVL5 + 1091 00ee 14000000 .4byte .LVL6 + 1092 00f2 0700 .2byte 0x7 + 1093 00f4 70 .byte 0x70 + 1094 00f5 00 .sleb128 0 + 1095 00f6 33 .byte 0x33 + 1096 00f7 1A .byte 0x1a + 1097 00f8 33 .byte 0x33 + 1098 00f9 24 .byte 0x24 + 1099 00fa 9F .byte 0x9f + 1100 00fb 14000000 .4byte .LVL6 + 1101 00ff 18000000 .4byte .LVL7 + 1102 0103 0100 .2byte 0x1 + 1103 0105 52 .byte 0x52 + 1104 0106 18000000 .4byte .LVL7 + 1105 010a 26000000 .4byte .LVL8 + 1106 010e 0700 .2byte 0x7 + 1107 0110 70 .byte 0x70 + 1108 0111 00 .sleb128 0 + 1109 0112 33 .byte 0x33 + 1110 0113 1A .byte 0x1a + 1111 0114 33 .byte 0x33 + 1112 0115 24 .byte 0x24 + 1113 0116 9F .byte 0x9f + 1114 0117 26000000 .4byte .LVL8 + 1115 011b 3C000000 .4byte .LFE8 + 1116 011f 0800 .2byte 0x8 + 1117 0121 F3 .byte 0xf3 + 1118 0122 01 .uleb128 0x1 + 1119 0123 50 .byte 0x50 + 1120 0124 33 .byte 0x33 + 1121 0125 1A .byte 0x1a + 1122 0126 33 .byte 0x33 + 1123 0127 24 .byte 0x24 + 1124 0128 9F .byte 0x9f + 1125 0129 00000000 .4byte 0 + 1126 012d 00000000 .4byte 0 + 1127 .LLST7: + 1128 0131 00000000 .4byte .LFB9 + 1129 0135 1E000000 .4byte .LCFI2 + 1130 0139 0200 .2byte 0x2 + 1131 013b 7D .byte 0x7d + 1132 013c 00 .sleb128 0 + 1133 013d 1E000000 .4byte .LCFI2 + 1134 0141 30000000 .4byte .LFE9 + 1135 0145 0200 .2byte 0x2 + 1136 0147 7D .byte 0x7d + 1137 0148 04 .sleb128 4 + 1138 0149 00000000 .4byte 0 + 1139 014d 00000000 .4byte 0 + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 21 + + + 1140 .LLST8: + 1141 0151 00000000 .4byte .LVL9 + 1142 0155 12000000 .4byte .LVL12 + 1143 0159 0100 .2byte 0x1 + 1144 015b 50 .byte 0x50 + 1145 015c 12000000 .4byte .LVL12 + 1146 0160 30000000 .4byte .LFE9 + 1147 0164 0400 .2byte 0x4 + 1148 0166 F3 .byte 0xf3 + 1149 0167 01 .uleb128 0x1 + 1150 0168 50 .byte 0x50 + 1151 0169 9F .byte 0x9f + 1152 016a 00000000 .4byte 0 + 1153 016e 00000000 .4byte 0 + 1154 .LLST9: + 1155 0172 00000000 .4byte .LVL9 + 1156 0176 10000000 .4byte .LVL11 + 1157 017a 0100 .2byte 0x1 + 1158 017c 51 .byte 0x51 + 1159 017d 10000000 .4byte .LVL11 + 1160 0181 30000000 .4byte .LFE9 + 1161 0185 0400 .2byte 0x4 + 1162 0187 F3 .byte 0xf3 + 1163 0188 01 .uleb128 0x1 + 1164 0189 51 .byte 0x51 + 1165 018a 9F .byte 0x9f + 1166 018b 00000000 .4byte 0 + 1167 018f 00000000 .4byte 0 + 1168 .LLST10: + 1169 0193 00000000 .4byte .LVL9 + 1170 0197 06000000 .4byte .LVL10 + 1171 019b 0700 .2byte 0x7 + 1172 019d 70 .byte 0x70 + 1173 019e 00 .sleb128 0 + 1174 019f 33 .byte 0x33 + 1175 01a0 1A .byte 0x1a + 1176 01a1 33 .byte 0x33 + 1177 01a2 24 .byte 0x24 + 1178 01a3 9F .byte 0x9f + 1179 01a4 06000000 .4byte .LVL10 + 1180 01a8 16000000 .4byte .LVL13 + 1181 01ac 0100 .2byte 0x1 + 1182 01ae 53 .byte 0x53 + 1183 01af 16000000 .4byte .LVL13 + 1184 01b3 30000000 .4byte .LFE9 + 1185 01b7 0800 .2byte 0x8 + 1186 01b9 F3 .byte 0xf3 + 1187 01ba 01 .uleb128 0x1 + 1188 01bb 50 .byte 0x50 + 1189 01bc 33 .byte 0x33 + 1190 01bd 1A .byte 0x1a + 1191 01be 33 .byte 0x33 + 1192 01bf 24 .byte 0x24 + 1193 01c0 9F .byte 0x9f + 1194 01c1 00000000 .4byte 0 + 1195 01c5 00000000 .4byte 0 + 1196 .section .debug_aranges,"",%progbits + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 22 + + + 1197 0000 2C000000 .4byte 0x2c + 1198 0004 0200 .2byte 0x2 + 1199 0006 00000000 .4byte .Ldebug_info0 + 1200 000a 04 .byte 0x4 + 1201 000b 00 .byte 0 + 1202 000c 0000 .2byte 0 + 1203 000e 0000 .2byte 0 + 1204 0010 00000000 .4byte .LFB7 + 1205 0014 48000000 .4byte .LFE7-.LFB7 + 1206 0018 00000000 .4byte .LFB8 + 1207 001c 3C000000 .4byte .LFE8-.LFB8 + 1208 0020 00000000 .4byte .LFB9 + 1209 0024 30000000 .4byte .LFE9-.LFB9 + 1210 0028 00000000 .4byte 0 + 1211 002c 00000000 .4byte 0 + 1212 .section .debug_ranges,"",%progbits + 1213 .Ldebug_ranges0: + 1214 0000 00000000 .4byte .LFB7 + 1215 0004 48000000 .4byte .LFE7 + 1216 0008 00000000 .4byte .LFB8 + 1217 000c 3C000000 .4byte .LFE8 + 1218 0010 00000000 .4byte .LFB9 + 1219 0014 30000000 .4byte .LFE9 + 1220 0018 00000000 .4byte 0 + 1221 001c 00000000 .4byte 0 + 1222 .section .debug_line,"",%progbits + 1223 .Ldebug_line0: + 1224 0000 D7000000 .section .debug_str,"MS",%progbits,1 + 1224 02008400 + 1224 00000201 + 1224 FB0E0D00 + 1224 01010101 + 1225 .LASF41: + 1226 0000 7072696F .ascii "prio\000" + 1226 00 + 1227 .LASF17: + 1228 0005 49435052 .ascii "ICPR\000" + 1228 00 + 1229 .LASF46: + 1230 000a 2E2E2F2E .ascii "../..//os/ports/common/ARMCMx/nvic.c\000" + 1230 2E2F2F6F + 1230 732F706F + 1230 7274732F + 1230 636F6D6D + 1231 .LASF37: + 1232 002f 4D4D4652 .ascii "MMFR\000" + 1232 00 + 1233 .LASF30: + 1234 0034 53484353 .ascii "SHCSR\000" + 1234 5200 + 1235 .LASF43: + 1236 003a 6E766963 .ascii "nvicDisableVector\000" + 1236 44697361 + 1236 626C6556 + 1236 6563746F + 1236 7200 + 1237 .LASF24: + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 23 + + + 1238 004c 434D785F .ascii "CMx_NVIC\000" + 1238 4E564943 + 1238 00 + 1239 .LASF27: + 1240 0055 56544F52 .ascii "VTOR\000" + 1240 00 + 1241 .LASF13: + 1242 005a 49434552 .ascii "ICER\000" + 1242 00 + 1243 .LASF10: + 1244 005f 494F5245 .ascii "IOREG32\000" + 1244 47333200 + 1245 .LASF47: + 1246 0067 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 1246 73657273 + 1246 5C496D61 + 1246 6E6F6C5C + 1246 64657665 + 1247 0094 6C696361 .ascii "lications\\smartcities\000" + 1247 74696F6E + 1247 735C736D + 1247 61727463 + 1247 69746965 + 1248 .LASF2: + 1249 00aa 756E7369 .ascii "unsigned char\000" + 1249 676E6564 + 1249 20636861 + 1249 7200 + 1250 .LASF12: + 1251 00b8 756E7573 .ascii "unused1\000" + 1251 65643100 + 1252 .LASF14: + 1253 00c0 756E7573 .ascii "unused2\000" + 1253 65643200 + 1254 .LASF16: + 1255 00c8 756E7573 .ascii "unused3\000" + 1255 65643300 + 1256 .LASF18: + 1257 00d0 756E7573 .ascii "unused4\000" + 1257 65643400 + 1258 .LASF20: + 1259 00d8 756E7573 .ascii "unused5\000" + 1259 65643500 + 1260 .LASF21: + 1261 00e0 756E7573 .ascii "unused6\000" + 1261 65643600 + 1262 .LASF4: + 1263 00e8 73686F72 .ascii "short unsigned int\000" + 1263 7420756E + 1263 7369676E + 1263 65642069 + 1263 6E7400 + 1264 .LASF31: + 1265 00fb 43465352 .ascii "CFSR\000" + 1265 00 + 1266 .LASF32: + 1267 0100 48465352 .ascii "HFSR\000" + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 24 + + + 1267 00 + 1268 .LASF6: + 1269 0105 6C6F6E67 .ascii "long unsigned int\000" + 1269 20756E73 + 1269 69676E65 + 1269 6420696E + 1269 7400 + 1270 .LASF38: + 1271 0117 43504143 .ascii "CPACR\000" + 1271 5200 + 1272 .LASF22: + 1273 011d 53544952 .ascii "STIR\000" + 1273 00 + 1274 .LASF3: + 1275 0122 73686F72 .ascii "short int\000" + 1275 7420696E + 1275 7400 + 1276 .LASF0: + 1277 012c 756E7369 .ascii "unsigned int\000" + 1277 676E6564 + 1277 20696E74 + 1277 00 + 1278 .LASF15: + 1279 0139 49535052 .ascii "ISPR\000" + 1279 00 + 1280 .LASF33: + 1281 013e 44465352 .ascii "DFSR\000" + 1281 00 + 1282 .LASF8: + 1283 0143 6C6F6E67 .ascii "long long unsigned int\000" + 1283 206C6F6E + 1283 6720756E + 1283 7369676E + 1283 65642069 + 1284 .LASF26: + 1285 015a 49435352 .ascii "ICSR\000" + 1285 00 + 1286 .LASF39: + 1287 015f 434D785F .ascii "CMx_SCB\000" + 1287 53434200 + 1288 .LASF28: + 1289 0167 41495243 .ascii "AIRCR\000" + 1289 5200 + 1290 .LASF35: + 1291 016d 42464152 .ascii "BFAR\000" + 1291 00 + 1292 .LASF44: + 1293 0172 68616E64 .ascii "handler\000" + 1293 6C657200 + 1294 .LASF23: + 1295 017a 73697A65 .ascii "sizetype\000" + 1295 74797065 + 1295 00 + 1296 .LASF7: + 1297 0183 6C6F6E67 .ascii "long long int\000" + 1297 206C6F6E + 1297 6720696E + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 25 + + + 1297 7400 + 1298 .LASF25: + 1299 0191 43505549 .ascii "CPUID\000" + 1299 4400 + 1300 .LASF40: + 1301 0197 63686172 .ascii "char\000" + 1301 00 + 1302 .LASF45: + 1303 019c 474E5520 .ascii "GNU C 4.7.2\000" + 1303 4320342E + 1303 372E3200 + 1304 .LASF11: + 1305 01a8 49534552 .ascii "ISER\000" + 1305 00 + 1306 .LASF36: + 1307 01ad 41465352 .ascii "AFSR\000" + 1307 00 + 1308 .LASF34: + 1309 01b2 4D4D4641 .ascii "MMFAR\000" + 1309 5200 + 1310 .LASF9: + 1311 01b8 75696E74 .ascii "uint32_t\000" + 1311 33325F74 + 1311 00 + 1312 .LASF5: + 1313 01c1 6C6F6E67 .ascii "long int\000" + 1313 20696E74 + 1313 00 + 1314 .LASF29: + 1315 01ca 53485052 .ascii "SHPR\000" + 1315 00 + 1316 .LASF1: + 1317 01cf 7369676E .ascii "signed char\000" + 1317 65642063 + 1317 68617200 + 1318 .LASF48: + 1319 01db 6E766963 .ascii "nvicSetSystemHandlerPriority\000" + 1319 53657453 + 1319 79737465 + 1319 6D48616E + 1319 646C6572 + 1320 .LASF19: + 1321 01f8 49414252 .ascii "IABR\000" + 1321 00 + 1322 .LASF42: + 1323 01fd 6E766963 .ascii "nvicEnableVector\000" + 1323 456E6162 + 1323 6C655665 + 1323 63746F72 + 1323 00 + 1324 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\ccyR7jEn.s page 26 + + +DEFINED SYMBOLS + *ABS*:00000000 nvic.c +C:\cygwin\tmp\ccyR7jEn.s:19 .text.nvicEnableVector:00000000 $t +C:\cygwin\tmp\ccyR7jEn.s:25 .text.nvicEnableVector:00000000 nvicEnableVector +C:\cygwin\tmp\ccyR7jEn.s:83 .text.nvicDisableVector:00000000 $t +C:\cygwin\tmp\ccyR7jEn.s:89 .text.nvicDisableVector:00000000 nvicDisableVector +C:\cygwin\tmp\ccyR7jEn.s:137 .text.nvicSetSystemHandlerPriority:00000000 $t +C:\cygwin\tmp\ccyR7jEn.s:143 .text.nvicSetSystemHandlerPriority:00000000 nvicSetSystemHandlerPriority + .debug_frame:00000010 $d + +NO UNDEFINED SYMBOLS diff --git a/Project/applications/smartcities/build/lst/syscalls.lst b/Project/applications/smartcities/build/lst/syscalls.lst new file mode 100644 index 0000000..b83f84a --- /dev/null +++ b/Project/applications/smartcities/build/lst/syscalls.lst @@ -0,0 +1,5128 @@ +ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "syscalls.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text._read_r,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .global _read_r + 22 .thumb + 23 .thumb_func + 24 .type _read_r, %function + 25 _read_r: + 26 .LFB7: + 27 .file 1 "../..//os/various/syscalls.c" + 28 .loc 1 82 0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .LVL0: + 34 .loc 1 95 0 + 35 0000 1623 movs r3, #22 + 36 .LVL1: + 37 0002 0360 str r3, [r0, #0] + 38 .loc 1 98 0 + 39 0004 4FF0FF30 mov r0, #-1 + 40 .LVL2: + 41 0008 7047 bx lr + 42 .cfi_endproc + 43 .LFE7: + 44 .size _read_r, .-_read_r + 45 000a 00BFAFF3 .section .text._lseek_r,"ax",%progbits + 45 0080 + 46 .align 2 + 47 .p2align 4,,15 + 48 .global _lseek_r + 49 .thumb + 50 .thumb_func + 51 .type _lseek_r, %function + 52 _lseek_r: + 53 .LFB8: + 54 .loc 1 103 0 + 55 .cfi_startproc + 56 @ args = 0, pretend = 0, frame = 0 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 2 + + + 57 @ frame_needed = 0, uses_anonymous_args = 0 + 58 @ link register save eliminated. + 59 .LVL3: + 60 .loc 1 110 0 + 61 0000 0020 movs r0, #0 + 62 .LVL4: + 63 0002 7047 bx lr + 64 .cfi_endproc + 65 .LFE8: + 66 .size _lseek_r, .-_lseek_r + 67 0004 AFF30080 .section .text._write_r,"ax",%progbits + 67 AFF30080 + 67 AFF30080 + 68 .align 2 + 69 .p2align 4,,15 + 70 .global _write_r + 71 .thumb + 72 .thumb_func + 73 .type _write_r, %function + 74 _write_r: + 75 .LFB9: + 76 .loc 1 115 0 + 77 .cfi_startproc + 78 @ args = 0, pretend = 0, frame = 0 + 79 @ frame_needed = 0, uses_anonymous_args = 0 + 80 @ link register save eliminated. + 81 .LVL5: + 82 .loc 1 127 0 + 83 0000 1846 mov r0, r3 + 84 .LVL6: + 85 0002 7047 bx lr + 86 .cfi_endproc + 87 .LFE9: + 88 .size _write_r, .-_write_r + 89 0004 AFF30080 .section .text._close_r,"ax",%progbits + 89 AFF30080 + 89 AFF30080 + 90 .align 2 + 91 .p2align 4,,15 + 92 .global _close_r + 93 .thumb + 94 .thumb_func + 95 .type _close_r, %function + 96 _close_r: + 97 .LFB10: + 98 .loc 1 132 0 + 99 .cfi_startproc + 100 @ args = 0, pretend = 0, frame = 0 + 101 @ frame_needed = 0, uses_anonymous_args = 0 + 102 @ link register save eliminated. + 103 .LVL7: + 104 .loc 1 137 0 + 105 0000 0020 movs r0, #0 + 106 .LVL8: + 107 0002 7047 bx lr + 108 .cfi_endproc + 109 .LFE10: + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 3 + + + 110 .size _close_r, .-_close_r + 111 0004 AFF30080 .section .text._sbrk_r,"ax",%progbits + 111 AFF30080 + 111 AFF30080 + 112 .align 2 + 113 .p2align 4,,15 + 114 .global _sbrk_r + 115 .thumb + 116 .thumb_func + 117 .type _sbrk_r, %function + 118 _sbrk_r: + 119 .LFB11: + 120 .loc 1 142 0 + 121 .cfi_startproc + 122 @ args = 0, pretend = 0, frame = 0 + 123 @ frame_needed = 0, uses_anonymous_args = 0 + 124 .LVL9: + 125 0000 10B5 push {r4, lr} + 126 .LCFI0: + 127 .cfi_def_cfa_offset 8 + 128 .cfi_offset 4, -8 + 129 .cfi_offset 14, -4 + 130 .loc 1 142 0 + 131 0002 0446 mov r4, r0 + 132 .loc 1 149 0 + 133 0004 0846 mov r0, r1 + 134 .LVL10: + 135 0006 FFF7FEFF bl chCoreAlloc + 136 .LVL11: + 137 .loc 1 150 0 + 138 000a 00B1 cbz r0, .L8 + 139 .loc 1 159 0 + 140 000c 10BD pop {r4, pc} + 141 .L8: + 142 .loc 1 151 0 + 143 000e 0C23 movs r3, #12 + 144 0010 2360 str r3, [r4, #0] + 145 .loc 1 152 0 + 146 0012 4FF0FF30 mov r0, #-1 + 147 .LVL12: + 148 .loc 1 159 0 + 149 0016 10BD pop {r4, pc} + 150 .cfi_endproc + 151 .LFE11: + 152 .size _sbrk_r, .-_sbrk_r + 153 0018 AFF30080 .section .text._fstat_r,"ax",%progbits + 153 AFF30080 + 154 .align 2 + 155 .p2align 4,,15 + 156 .global _fstat_r + 157 .thumb + 158 .thumb_func + 159 .type _fstat_r, %function + 160 _fstat_r: + 161 .LFB12: + 162 .loc 1 164 0 + 163 .cfi_startproc + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 4 + + + 164 @ args = 0, pretend = 0, frame = 0 + 165 @ frame_needed = 0, uses_anonymous_args = 0 + 166 .LVL13: + 167 0000 10B5 push {r4, lr} + 168 .LCFI1: + 169 .cfi_def_cfa_offset 8 + 170 .cfi_offset 4, -8 + 171 .cfi_offset 14, -4 + 172 .loc 1 168 0 + 173 0002 1046 mov r0, r2 + 174 .LVL14: + 175 .loc 1 164 0 + 176 0004 1446 mov r4, r2 + 177 .loc 1 168 0 + 178 0006 0021 movs r1, #0 + 179 .LVL15: + 180 0008 3C22 movs r2, #60 + 181 .LVL16: + 182 000a FFF7FEFF bl memset + 183 .LVL17: + 184 .loc 1 169 0 + 185 000e 4FF40053 mov r3, #8192 + 186 0012 6360 str r3, [r4, #4] + 187 .loc 1 171 0 + 188 0014 0020 movs r0, #0 + 189 0016 10BD pop {r4, pc} + 190 .cfi_endproc + 191 .LFE12: + 192 .size _fstat_r, .-_fstat_r + 193 0018 AFF30080 .section .text._isatty_r,"ax",%progbits + 193 AFF30080 + 194 .align 2 + 195 .p2align 4,,15 + 196 .global _isatty_r + 197 .thumb + 198 .thumb_func + 199 .type _isatty_r, %function + 200 _isatty_r: + 201 .LFB13: + 202 .loc 1 176 0 + 203 .cfi_startproc + 204 @ args = 0, pretend = 0, frame = 0 + 205 @ frame_needed = 0, uses_anonymous_args = 0 + 206 @ link register save eliminated. + 207 .LVL18: + 208 .loc 1 181 0 + 209 0000 0120 movs r0, #1 + 210 .LVL19: + 211 0002 7047 bx lr + 212 .cfi_endproc + 213 .LFE13: + 214 .size _isatty_r, .-_isatty_r + 215 0004 AFF30080 .section .text._realloc_r,"ax",%progbits + 215 AFF30080 + 215 AFF30080 + 216 .align 2 + 217 .p2align 4,,15 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 5 + + + 218 .global _realloc_r + 219 .thumb + 220 .thumb_func + 221 .type _realloc_r, %function + 222 _realloc_r: + 223 .LFB14: + 224 .loc 1 183 0 + 225 .cfi_startproc + 226 @ args = 0, pretend = 0, frame = 0 + 227 @ frame_needed = 0, uses_anonymous_args = 0 + 228 .LVL20: + 229 0000 70B5 push {r4, r5, r6, lr} + 230 .LCFI2: + 231 .cfi_def_cfa_offset 16 + 232 .cfi_offset 4, -16 + 233 .cfi_offset 5, -12 + 234 .cfi_offset 6, -8 + 235 .cfi_offset 14, -4 + 236 .loc 1 186 0 + 237 0002 0020 movs r0, #0 + 238 .LVL21: + 239 .loc 1 183 0 + 240 0004 0D46 mov r5, r1 + 241 .loc 1 186 0 + 242 0006 1146 mov r1, r2 + 243 .LVL22: + 244 .loc 1 183 0 + 245 0008 1446 mov r4, r2 + 246 .loc 1 186 0 + 247 000a FFF7FEFF bl chHeapAlloc + 248 .LVL23: + 249 .loc 1 188 0 + 250 000e 0646 mov r6, r0 + 251 0010 30B1 cbz r0, .L12 + 252 .loc 1 192 0 + 253 0012 2946 mov r1, r5 + 254 0014 2246 mov r2, r4 + 255 0016 FFF7FEFF bl memcpy + 256 .LVL24: + 257 .loc 1 194 0 + 258 001a 2846 mov r0, r5 + 259 001c FFF7FEFF bl chHeapFree + 260 .LVL25: + 261 .L12: + 262 .loc 1 197 0 + 263 0020 3046 mov r0, r6 + 264 0022 70BD pop {r4, r5, r6, pc} + 265 .cfi_endproc + 266 .LFE14: + 267 .size _realloc_r, .-_realloc_r + 268 0024 AFF30080 .section .text._calloc_r,"ax",%progbits + 268 AFF30080 + 268 AFF30080 + 269 .align 2 + 270 .p2align 4,,15 + 271 .global _calloc_r + 272 .thumb + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 6 + + + 273 .thumb_func + 274 .type _calloc_r, %function + 275 _calloc_r: + 276 .LFB15: + 277 .loc 1 199 0 + 278 .cfi_startproc + 279 @ args = 0, pretend = 0, frame = 0 + 280 @ frame_needed = 0, uses_anonymous_args = 0 + 281 @ link register save eliminated. + 282 .LVL26: + 283 .loc 1 200 0 + 284 0000 01FB02F1 mul r1, r1, r2 + 285 .LVL27: + 286 0004 0020 movs r0, #0 + 287 .LVL28: + 288 .loc 1 201 0 + 289 .loc 1 200 0 + 290 0006 FFF7FEBF b chHeapAlloc + 291 .LVL29: + 292 .cfi_endproc + 293 .LFE15: + 294 .size _calloc_r, .-_calloc_r + 295 000a 00BFAFF3 .section .text._malloc_r,"ax",%progbits + 295 0080 + 296 .align 2 + 297 .p2align 4,,15 + 298 .global _malloc_r + 299 .thumb + 300 .thumb_func + 301 .type _malloc_r, %function + 302 _malloc_r: + 303 .LFB16: + 304 .loc 1 203 0 + 305 .cfi_startproc + 306 @ args = 0, pretend = 0, frame = 0 + 307 @ frame_needed = 0, uses_anonymous_args = 0 + 308 @ link register save eliminated. + 309 .LVL30: + 310 .loc 1 204 0 + 311 0000 0020 movs r0, #0 + 312 .LVL31: + 313 .loc 1 205 0 + 314 .loc 1 204 0 + 315 0002 FFF7FEBF b chHeapAlloc + 316 .LVL32: + 317 .cfi_endproc + 318 .LFE16: + 319 .size _malloc_r, .-_malloc_r + 320 0006 00BFAFF3 .section .text._free_r,"ax",%progbits + 320 0080AFF3 + 320 0080 + 321 .align 2 + 322 .p2align 4,,15 + 323 .global _free_r + 324 .thumb + 325 .thumb_func + 326 .type _free_r, %function + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 7 + + + 327 _free_r: + 328 .LFB17: + 329 .loc 1 207 0 + 330 .cfi_startproc + 331 @ args = 0, pretend = 0, frame = 0 + 332 @ frame_needed = 0, uses_anonymous_args = 0 + 333 @ link register save eliminated. + 334 .LVL33: + 335 .loc 1 208 0 + 336 0000 0846 mov r0, r1 + 337 .LVL34: + 338 .loc 1 209 0 + 339 .loc 1 208 0 + 340 0002 FFF7FEBF b chHeapFree + 341 .LVL35: + 342 .cfi_endproc + 343 .LFE17: + 344 .size _free_r, .-_free_r + 345 0006 00BFAFF3 .text + 345 0080AFF3 + 345 0080 + 346 .Letext0: + 347 .file 2 "c:\\yagarto\\bin\\../lib/gcc/arm-none-eabi/4.7.2/include/stddef.h" + 348 .file 3 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/lock.h" + 349 .file 4 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/_types.h" + 350 .file 5 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/reent.h" + 351 .file 6 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/types.h" + 352 .file 7 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/sys/stat.h" + 353 .file 8 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 354 .file 9 "../..//os/ports/GCC/ARMCMx/chtypes.h" + 355 .file 10 "../..//os/kernel/include/chlists.h" + 356 .file 11 "../..//os/kernel/include/chthreads.h" + 357 .file 12 "../..//os/ports/GCC/ARMCMx/chcore_v7m.h" + 358 .file 13 "../..//os/kernel/include/chmtx.h" + 359 .file 14 "../..//os/kernel/include/chmemcore.h" + 360 .file 15 "../..//os/kernel/include/chheap.h" + 361 .file 16 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdlib.h" + 362 .section .debug_info,"",%progbits + 363 .Ldebug_info0: + 364 0000 44130000 .4byte 0x1344 + 365 0004 0200 .2byte 0x2 + 366 0006 00000000 .4byte .Ldebug_abbrev0 + 367 000a 04 .byte 0x4 + 368 000b 01 .uleb128 0x1 + 369 000c AE010000 .4byte .LASF221 + 370 0010 01 .byte 0x1 + 371 0011 51050000 .4byte .LASF222 + 372 0015 A5000000 .4byte .LASF223 + 373 0019 00000000 .4byte .Ldebug_ranges0+0 + 374 001d 00000000 .4byte 0 + 375 0021 00000000 .4byte 0 + 376 0025 00000000 .4byte .Ldebug_line0 + 377 0029 02 .uleb128 0x2 + 378 002a 91020000 .4byte .LASF7 + 379 002e 02 .byte 0x2 + 380 002f D5 .byte 0xd5 + 381 0030 34000000 .4byte 0x34 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 8 + + + 382 0034 03 .uleb128 0x3 + 383 0035 04 .byte 0x4 + 384 0036 07 .byte 0x7 + 385 0037 93000000 .4byte .LASF0 + 386 003b 03 .uleb128 0x3 + 387 003c 01 .byte 0x1 + 388 003d 06 .byte 0x6 + 389 003e 60070000 .4byte .LASF1 + 390 0042 03 .uleb128 0x3 + 391 0043 01 .byte 0x1 + 392 0044 08 .byte 0x8 + 393 0045 EA060000 .4byte .LASF2 + 394 0049 03 .uleb128 0x3 + 395 004a 02 .byte 0x2 + 396 004b 05 .byte 0x5 + 397 004c 95050000 .4byte .LASF3 + 398 0050 03 .uleb128 0x3 + 399 0051 02 .byte 0x2 + 400 0052 07 .byte 0x7 + 401 0053 80070000 .4byte .LASF4 + 402 0057 04 .uleb128 0x4 + 403 0058 04 .byte 0x4 + 404 0059 05 .byte 0x5 + 405 005a 696E7400 .ascii "int\000" + 406 005e 03 .uleb128 0x3 + 407 005f 08 .byte 0x8 + 408 0060 05 .byte 0x5 + 409 0061 30040000 .4byte .LASF5 + 410 0065 03 .uleb128 0x3 + 411 0066 08 .byte 0x8 + 412 0067 07 .byte 0x7 + 413 0068 03020000 .4byte .LASF6 + 414 006c 02 .uleb128 0x2 + 415 006d 1D010000 .4byte .LASF8 + 416 0071 03 .byte 0x3 + 417 0072 07 .byte 0x7 + 418 0073 57000000 .4byte 0x57 + 419 0077 02 .uleb128 0x2 + 420 0078 BF070000 .4byte .LASF9 + 421 007c 04 .byte 0x4 + 422 007d 10 .byte 0x10 + 423 007e 82000000 .4byte 0x82 + 424 0082 03 .uleb128 0x3 + 425 0083 04 .byte 0x4 + 426 0084 05 .byte 0x5 + 427 0085 BE050000 .4byte .LASF10 + 428 0089 02 .uleb128 0x2 + 429 008a 5A040000 .4byte .LASF11 + 430 008e 04 .byte 0x4 + 431 008f 18 .byte 0x18 + 432 0090 49000000 .4byte 0x49 + 433 0094 02 .uleb128 0x2 + 434 0095 26060000 .4byte .LASF12 + 435 0099 04 .byte 0x4 + 436 009a 1D .byte 0x1d + 437 009b 50000000 .4byte 0x50 + 438 009f 02 .uleb128 0x2 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 9 + + + 439 00a0 2D050000 .4byte .LASF13 + 440 00a4 04 .byte 0x4 + 441 00a5 20 .byte 0x20 + 442 00a6 50000000 .4byte 0x50 + 443 00aa 02 .uleb128 0x2 + 444 00ab 5A010000 .4byte .LASF14 + 445 00af 04 .byte 0x4 + 446 00b0 2C .byte 0x2c + 447 00b1 82000000 .4byte 0x82 + 448 00b5 05 .uleb128 0x5 + 449 00b6 BF060000 .4byte .LASF15 + 450 00ba 02 .byte 0x2 + 451 00bb 6201 .2byte 0x162 + 452 00bd 34000000 .4byte 0x34 + 453 00c1 06 .uleb128 0x6 + 454 00c2 04 .byte 0x4 + 455 00c3 04 .byte 0x4 + 456 00c4 46 .byte 0x46 + 457 00c5 E0000000 .4byte 0xe0 + 458 00c9 07 .uleb128 0x7 + 459 00ca C2030000 .4byte .LASF16 + 460 00ce 04 .byte 0x4 + 461 00cf 48 .byte 0x48 + 462 00d0 B5000000 .4byte 0xb5 + 463 00d4 07 .uleb128 0x7 + 464 00d5 EF050000 .4byte .LASF17 + 465 00d9 04 .byte 0x4 + 466 00da 49 .byte 0x49 + 467 00db E0000000 .4byte 0xe0 + 468 00df 00 .byte 0 + 469 00e0 08 .uleb128 0x8 + 470 00e1 42000000 .4byte 0x42 + 471 00e5 F0000000 .4byte 0xf0 + 472 00e9 09 .uleb128 0x9 + 473 00ea F0000000 .4byte 0xf0 + 474 00ee 03 .byte 0x3 + 475 00ef 00 .byte 0 + 476 00f0 03 .uleb128 0x3 + 477 00f1 04 .byte 0x4 + 478 00f2 07 .byte 0x7 + 479 00f3 95060000 .4byte .LASF18 + 480 00f7 0A .uleb128 0xa + 481 00f8 08 .byte 0x8 + 482 00f9 04 .byte 0x4 + 483 00fa 43 .byte 0x43 + 484 00fb 1C010000 .4byte 0x11c + 485 00ff 0B .uleb128 0xb + 486 0100 BA010000 .4byte .LASF19 + 487 0104 04 .byte 0x4 + 488 0105 45 .byte 0x45 + 489 0106 57000000 .4byte 0x57 + 490 010a 02 .byte 0x2 + 491 010b 23 .byte 0x23 + 492 010c 00 .uleb128 0 + 493 010d 0B .uleb128 0xb + 494 010e FF020000 .4byte .LASF20 + 495 0112 04 .byte 0x4 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 10 + + + 496 0113 4A .byte 0x4a + 497 0114 C1000000 .4byte 0xc1 + 498 0118 02 .byte 0x2 + 499 0119 23 .byte 0x23 + 500 011a 04 .uleb128 0x4 + 501 011b 00 .byte 0 + 502 011c 02 .uleb128 0x2 + 503 011d B8040000 .4byte .LASF21 + 504 0121 04 .byte 0x4 + 505 0122 4B .byte 0x4b + 506 0123 F7000000 .4byte 0xf7 + 507 0127 02 .uleb128 0x2 + 508 0128 9B030000 .4byte .LASF22 + 509 012c 04 .byte 0x4 + 510 012d 4F .byte 0x4f + 511 012e 6C000000 .4byte 0x6c + 512 0132 0C .uleb128 0xc + 513 0133 04 .byte 0x4 + 514 0134 02 .uleb128 0x2 + 515 0135 68040000 .4byte .LASF23 + 516 0139 05 .byte 0x5 + 517 013a 15 .byte 0x15 + 518 013b 3F010000 .4byte 0x13f + 519 013f 03 .uleb128 0x3 + 520 0140 04 .byte 0x4 + 521 0141 07 .byte 0x7 + 522 0142 A6060000 .4byte .LASF24 + 523 0146 0D .uleb128 0xd + 524 0147 6F010000 .4byte .LASF29 + 525 014b 18 .byte 0x18 + 526 014c 05 .byte 0x5 + 527 014d 2C .byte 0x2c + 528 014e A5010000 .4byte 0x1a5 + 529 0152 0B .uleb128 0xb + 530 0153 C3020000 .4byte .LASF25 + 531 0157 05 .byte 0x5 + 532 0158 2E .byte 0x2e + 533 0159 A5010000 .4byte 0x1a5 + 534 015d 02 .byte 0x2 + 535 015e 23 .byte 0x23 + 536 015f 00 .uleb128 0 + 537 0160 0E .uleb128 0xe + 538 0161 5F6B00 .ascii "_k\000" + 539 0164 05 .byte 0x5 + 540 0165 2F .byte 0x2f + 541 0166 57000000 .4byte 0x57 + 542 016a 02 .byte 0x2 + 543 016b 23 .byte 0x23 + 544 016c 04 .uleb128 0x4 + 545 016d 0B .uleb128 0xb + 546 016e 4E060000 .4byte .LASF26 + 547 0172 05 .byte 0x5 + 548 0173 2F .byte 0x2f + 549 0174 57000000 .4byte 0x57 + 550 0178 02 .byte 0x2 + 551 0179 23 .byte 0x23 + 552 017a 08 .uleb128 0x8 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 11 + + + 553 017b 0B .uleb128 0xb + 554 017c CC050000 .4byte .LASF27 + 555 0180 05 .byte 0x5 + 556 0181 2F .byte 0x2f + 557 0182 57000000 .4byte 0x57 + 558 0186 02 .byte 0x2 + 559 0187 23 .byte 0x23 + 560 0188 0C .uleb128 0xc + 561 0189 0B .uleb128 0xb + 562 018a 39020000 .4byte .LASF28 + 563 018e 05 .byte 0x5 + 564 018f 2F .byte 0x2f + 565 0190 57000000 .4byte 0x57 + 566 0194 02 .byte 0x2 + 567 0195 23 .byte 0x23 + 568 0196 10 .uleb128 0x10 + 569 0197 0E .uleb128 0xe + 570 0198 5F7800 .ascii "_x\000" + 571 019b 05 .byte 0x5 + 572 019c 30 .byte 0x30 + 573 019d AB010000 .4byte 0x1ab + 574 01a1 02 .byte 0x2 + 575 01a2 23 .byte 0x23 + 576 01a3 14 .uleb128 0x14 + 577 01a4 00 .byte 0 + 578 01a5 0F .uleb128 0xf + 579 01a6 04 .byte 0x4 + 580 01a7 46010000 .4byte 0x146 + 581 01ab 08 .uleb128 0x8 + 582 01ac 34010000 .4byte 0x134 + 583 01b0 BB010000 .4byte 0x1bb + 584 01b4 09 .uleb128 0x9 + 585 01b5 F0000000 .4byte 0xf0 + 586 01b9 00 .byte 0 + 587 01ba 00 .byte 0 + 588 01bb 0D .uleb128 0xd + 589 01bc 83060000 .4byte .LASF30 + 590 01c0 24 .byte 0x24 + 591 01c1 05 .byte 0x5 + 592 01c2 34 .byte 0x34 + 593 01c3 46020000 .4byte 0x246 + 594 01c7 0B .uleb128 0xb + 595 01c8 9F020000 .4byte .LASF31 + 596 01cc 05 .byte 0x5 + 597 01cd 36 .byte 0x36 + 598 01ce 57000000 .4byte 0x57 + 599 01d2 02 .byte 0x2 + 600 01d3 23 .byte 0x23 + 601 01d4 00 .uleb128 0 + 602 01d5 0B .uleb128 0xb + 603 01d6 C2010000 .4byte .LASF32 + 604 01da 05 .byte 0x5 + 605 01db 37 .byte 0x37 + 606 01dc 57000000 .4byte 0x57 + 607 01e0 02 .byte 0x2 + 608 01e1 23 .byte 0x23 + 609 01e2 04 .uleb128 0x4 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 12 + + + 610 01e3 0B .uleb128 0xb + 611 01e4 98010000 .4byte .LASF33 + 612 01e8 05 .byte 0x5 + 613 01e9 38 .byte 0x38 + 614 01ea 57000000 .4byte 0x57 + 615 01ee 02 .byte 0x2 + 616 01ef 23 .byte 0x23 + 617 01f0 08 .uleb128 0x8 + 618 01f1 0B .uleb128 0xb + 619 01f2 58030000 .4byte .LASF34 + 620 01f6 05 .byte 0x5 + 621 01f7 39 .byte 0x39 + 622 01f8 57000000 .4byte 0x57 + 623 01fc 02 .byte 0x2 + 624 01fd 23 .byte 0x23 + 625 01fe 0C .uleb128 0xc + 626 01ff 0B .uleb128 0xb + 627 0200 1B050000 .4byte .LASF35 + 628 0204 05 .byte 0x5 + 629 0205 3A .byte 0x3a + 630 0206 57000000 .4byte 0x57 + 631 020a 02 .byte 0x2 + 632 020b 23 .byte 0x23 + 633 020c 10 .uleb128 0x10 + 634 020d 0B .uleb128 0xb + 635 020e 0D060000 .4byte .LASF36 + 636 0212 05 .byte 0x5 + 637 0213 3B .byte 0x3b + 638 0214 57000000 .4byte 0x57 + 639 0218 02 .byte 0x2 + 640 0219 23 .byte 0x23 + 641 021a 14 .uleb128 0x14 + 642 021b 0B .uleb128 0xb + 643 021c 77010000 .4byte .LASF37 + 644 0220 05 .byte 0x5 + 645 0221 3C .byte 0x3c + 646 0222 57000000 .4byte 0x57 + 647 0226 02 .byte 0x2 + 648 0227 23 .byte 0x23 + 649 0228 18 .uleb128 0x18 + 650 0229 0B .uleb128 0xb + 651 022a A8020000 .4byte .LASF38 + 652 022e 05 .byte 0x5 + 653 022f 3D .byte 0x3d + 654 0230 57000000 .4byte 0x57 + 655 0234 02 .byte 0x2 + 656 0235 23 .byte 0x23 + 657 0236 1C .uleb128 0x1c + 658 0237 0B .uleb128 0xb + 659 0238 C8040000 .4byte .LASF39 + 660 023c 05 .byte 0x5 + 661 023d 3E .byte 0x3e + 662 023e 57000000 .4byte 0x57 + 663 0242 02 .byte 0x2 + 664 0243 23 .byte 0x23 + 665 0244 20 .uleb128 0x20 + 666 0245 00 .byte 0 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 13 + + + 667 0246 10 .uleb128 0x10 + 668 0247 2D000000 .4byte .LASF40 + 669 024b 0801 .2byte 0x108 + 670 024d 05 .byte 0x5 + 671 024e 47 .byte 0x47 + 672 024f 8F020000 .4byte 0x28f + 673 0253 0B .uleb128 0xb + 674 0254 58070000 .4byte .LASF41 + 675 0258 05 .byte 0x5 + 676 0259 48 .byte 0x48 + 677 025a 8F020000 .4byte 0x28f + 678 025e 02 .byte 0x2 + 679 025f 23 .byte 0x23 + 680 0260 00 .uleb128 0 + 681 0261 0B .uleb128 0xb + 682 0262 CE060000 .4byte .LASF42 + 683 0266 05 .byte 0x5 + 684 0267 49 .byte 0x49 + 685 0268 8F020000 .4byte 0x28f + 686 026c 03 .byte 0x3 + 687 026d 23 .byte 0x23 + 688 026e 8001 .uleb128 0x80 + 689 0270 0B .uleb128 0xb + 690 0271 B0070000 .4byte .LASF43 + 691 0275 05 .byte 0x5 + 692 0276 4B .byte 0x4b + 693 0277 34010000 .4byte 0x134 + 694 027b 03 .byte 0x3 + 695 027c 23 .byte 0x23 + 696 027d 8002 .uleb128 0x100 + 697 027f 0B .uleb128 0xb + 698 0280 EF070000 .4byte .LASF44 + 699 0284 05 .byte 0x5 + 700 0285 4E .byte 0x4e + 701 0286 34010000 .4byte 0x134 + 702 028a 03 .byte 0x3 + 703 028b 23 .byte 0x23 + 704 028c 8402 .uleb128 0x104 + 705 028e 00 .byte 0 + 706 028f 08 .uleb128 0x8 + 707 0290 32010000 .4byte 0x132 + 708 0294 9F020000 .4byte 0x29f + 709 0298 09 .uleb128 0x9 + 710 0299 F0000000 .4byte 0xf0 + 711 029d 1F .byte 0x1f + 712 029e 00 .byte 0 + 713 029f 10 .uleb128 0x10 + 714 02a0 79050000 .4byte .LASF45 + 715 02a4 9001 .2byte 0x190 + 716 02a6 05 .byte 0x5 + 717 02a7 59 .byte 0x59 + 718 02a8 E6020000 .4byte 0x2e6 + 719 02ac 0B .uleb128 0xb + 720 02ad C3020000 .4byte .LASF25 + 721 02b1 05 .byte 0x5 + 722 02b2 5A .byte 0x5a + 723 02b3 E6020000 .4byte 0x2e6 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 14 + + + 724 02b7 02 .byte 0x2 + 725 02b8 23 .byte 0x23 + 726 02b9 00 .uleb128 0 + 727 02ba 0B .uleb128 0xb + 728 02bb B7020000 .4byte .LASF46 + 729 02bf 05 .byte 0x5 + 730 02c0 5B .byte 0x5b + 731 02c1 57000000 .4byte 0x57 + 732 02c5 02 .byte 0x2 + 733 02c6 23 .byte 0x23 + 734 02c7 04 .uleb128 0x4 + 735 02c8 0B .uleb128 0xb + 736 02c9 62010000 .4byte .LASF47 + 737 02cd 05 .byte 0x5 + 738 02ce 5D .byte 0x5d + 739 02cf EC020000 .4byte 0x2ec + 740 02d3 02 .byte 0x2 + 741 02d4 23 .byte 0x23 + 742 02d5 08 .uleb128 0x8 + 743 02d6 0B .uleb128 0xb + 744 02d7 2D000000 .4byte .LASF40 + 745 02db 05 .byte 0x5 + 746 02dc 5E .byte 0x5e + 747 02dd 46020000 .4byte 0x246 + 748 02e1 03 .byte 0x3 + 749 02e2 23 .byte 0x23 + 750 02e3 8801 .uleb128 0x88 + 751 02e5 00 .byte 0 + 752 02e6 0F .uleb128 0xf + 753 02e7 04 .byte 0x4 + 754 02e8 9F020000 .4byte 0x29f + 755 02ec 08 .uleb128 0x8 + 756 02ed FE020000 .4byte 0x2fe + 757 02f1 FC020000 .4byte 0x2fc + 758 02f5 09 .uleb128 0x9 + 759 02f6 F0000000 .4byte 0xf0 + 760 02fa 1F .byte 0x1f + 761 02fb 00 .byte 0 + 762 02fc 11 .uleb128 0x11 + 763 02fd 01 .byte 0x1 + 764 02fe 0F .uleb128 0xf + 765 02ff 04 .byte 0x4 + 766 0300 FC020000 .4byte 0x2fc + 767 0304 0D .uleb128 0xd + 768 0305 19070000 .4byte .LASF48 + 769 0309 08 .byte 0x8 + 770 030a 05 .byte 0x5 + 771 030b 69 .byte 0x69 + 772 030c 2D030000 .4byte 0x32d + 773 0310 0B .uleb128 0xb + 774 0311 4A040000 .4byte .LASF49 + 775 0315 05 .byte 0x5 + 776 0316 6A .byte 0x6a + 777 0317 2D030000 .4byte 0x32d + 778 031b 02 .byte 0x2 + 779 031c 23 .byte 0x23 + 780 031d 00 .uleb128 0 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 15 + + + 781 031e 0B .uleb128 0xb + 782 031f B9070000 .4byte .LASF50 + 783 0323 05 .byte 0x5 + 784 0324 6B .byte 0x6b + 785 0325 57000000 .4byte 0x57 + 786 0329 02 .byte 0x2 + 787 032a 23 .byte 0x23 + 788 032b 04 .uleb128 0x4 + 789 032c 00 .byte 0 + 790 032d 0F .uleb128 0xf + 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49000000 .4byte 0x49 + 828 0371 02 .byte 0x2 + 829 0372 23 .byte 0x23 + 830 0373 0C .uleb128 0xc + 831 0374 0B .uleb128 0xb + 832 0375 93040000 .4byte .LASF53 + 833 0379 05 .byte 0x5 + 834 037a AE .byte 0xae + 835 037b 49000000 .4byte 0x49 + 836 037f 02 .byte 0x2 + 837 0380 23 .byte 0x23 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 16 + + + 838 0381 0E .uleb128 0xe + 839 0382 0E .uleb128 0xe + 840 0383 5F626600 .ascii "_bf\000" + 841 0387 05 .byte 0x5 + 842 0388 AF .byte 0xaf + 843 0389 04030000 .4byte 0x304 + 844 038d 02 .byte 0x2 + 845 038e 23 .byte 0x23 + 846 038f 10 .uleb128 0x10 + 847 0390 0B .uleb128 0xb + 848 0391 F3000000 .4byte .LASF54 + 849 0395 05 .byte 0x5 + 850 0396 B0 .byte 0xb0 + 851 0397 57000000 .4byte 0x57 + 852 039b 02 .byte 0x2 + 853 039c 23 .byte 0x23 + 854 039d 18 .uleb128 0x18 + 855 039e 0B .uleb128 0xb + 856 039f 67010000 .4byte .LASF55 + 857 03a3 05 .byte 0x5 + 858 03a4 B7 .byte 0xb7 + 859 03a5 32010000 .4byte 0x132 + 860 03a9 02 .byte 0x2 + 861 03aa 23 .byte 0x23 + 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0427 02 .byte 0x2 + 933 0428 23 .byte 0x23 + 934 0429 43 .uleb128 0x43 + 935 042a 0E .uleb128 0xe + 936 042b 5F6C6200 .ascii "_lb\000" + 937 042f 05 .byte 0x5 + 938 0430 CA .byte 0xca + 939 0431 04030000 .4byte 0x304 + 940 0435 02 .byte 0x2 + 941 0436 23 .byte 0x23 + 942 0437 44 .uleb128 0x44 + 943 0438 0B .uleb128 0xb + 944 0439 7A060000 .4byte .LASF62 + 945 043d 05 .byte 0x5 + 946 043e CD .byte 0xcd + 947 043f 57000000 .4byte 0x57 + 948 0443 02 .byte 0x2 + 949 0444 23 .byte 0x23 + 950 0445 4C .uleb128 0x4c + 951 0446 0B .uleb128 0xb + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 18 + + + 952 0447 5E020000 .4byte .LASF63 + 953 044b 05 .byte 0x5 + 954 044c CE .byte 0xce + 955 044d 57000000 .4byte 0x57 + 956 0451 02 .byte 0x2 + 957 0452 23 .byte 0x23 + 958 0453 50 .uleb128 0x50 + 959 0454 0B .uleb128 0xb + 960 0455 E9050000 .4byte .LASF64 + 961 0459 05 .byte 0x5 + 962 045a D1 .byte 0xd1 + 963 045b AC040000 .4byte 0x4ac + 964 045f 02 .byte 0x2 + 965 0460 23 .byte 0x23 + 966 0461 54 .uleb128 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.uleb128 0x1a + 1565 0903 73070000 .4byte .LASF68 + 1566 0907 05 .byte 0x5 + 1567 0908 7802 .2byte 0x278 + 1568 090a 51070000 .4byte 0x751 + 1569 090e 1A .uleb128 0x1a + 1570 090f 11070000 .4byte .LASF120 + 1571 0913 05 .byte 0x5 + 1572 0914 8102 .2byte 0x281 + 1573 0916 B1080000 .4byte 0x8b1 + 1574 091a 00 .byte 0 + 1575 091b 08 .uleb128 0x8 + 1576 091c 16060000 .4byte 0x616 + 1577 0920 2B090000 .4byte 0x92b + 1578 0924 09 .uleb128 0x9 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 29 + + + 1579 0925 F0000000 .4byte 0xf0 + 1580 0929 18 .byte 0x18 + 1581 092a 00 .byte 0 + 1582 092b 1B .uleb128 0x1b + 1583 092c 01 .byte 0x1 + 1584 092d 37090000 .4byte 0x937 + 1585 0931 13 .uleb128 0x13 + 1586 0932 AC040000 .4byte 0x4ac + 1587 0936 00 .byte 0 + 1588 0937 0F .uleb128 0xf + 1589 0938 04 .byte 0x4 + 1590 0939 2B090000 .4byte 0x92b + 1591 093d 0F .uleb128 0xf + 1592 093e 04 .byte 0x4 + 1593 093f A5010000 .4byte 0x1a5 + 1594 0943 1B .uleb128 0x1b + 1595 0944 01 .byte 0x1 + 1596 0945 4F090000 .4byte 0x94f + 1597 0949 13 .uleb128 0x13 + 1598 094a 57000000 .4byte 0x57 + 1599 094e 00 .byte 0 + 1600 094f 0F .uleb128 0xf + 1601 0950 04 .byte 0x4 + 1602 0951 55090000 .4byte 0x955 + 1603 0955 0F .uleb128 0xf + 1604 0956 04 .byte 0x4 + 1605 0957 43090000 .4byte 0x943 + 1606 095b 08 .uleb128 0x8 + 1607 095c B3060000 .4byte 0x6b3 + 1608 0960 6B090000 .4byte 0x96b + 1609 0964 09 .uleb128 0x9 + 1610 0965 F0000000 .4byte 0xf0 + 1611 0969 02 .byte 0x2 + 1612 096a 00 .byte 0 + 1613 096b 02 .uleb128 0x2 + 1614 096c D6030000 .4byte .LASF121 + 1615 0970 06 .byte 0x6 + 1616 0971 6E .byte 0x6e + 1617 0972 82000000 .4byte 0x82 + 1618 0976 02 .uleb128 0x2 + 1619 0977 72060000 .4byte .LASF122 + 1620 097b 06 .byte 0x6 + 1621 097c 7F .byte 0x7f + 1622 097d 10060000 .4byte 0x610 + 1623 0981 02 .uleb128 0x2 + 1624 0982 89010000 .4byte .LASF123 + 1625 0986 06 .byte 0x6 + 1626 0987 86 .byte 0x86 + 1627 0988 50000000 .4byte 0x50 + 1628 098c 02 .uleb128 0x2 + 1629 098d 7A070000 .4byte .LASF124 + 1630 0991 06 .byte 0x6 + 1631 0992 A3 .byte 0xa3 + 1632 0993 77000000 .4byte 0x77 + 1633 0997 02 .uleb128 0x2 + 1634 0998 8D040000 .4byte .LASF125 + 1635 099c 06 .byte 0x6 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 30 + + + 1636 099d A4 .byte 0xa4 + 1637 099e 89000000 .4byte 0x89 + 1638 09a2 02 .uleb128 0x2 + 1639 09a3 87040000 .4byte .LASF126 + 1640 09a7 06 .byte 0x6 + 1641 09a8 A5 .byte 0xa5 + 1642 09a9 94000000 .4byte 0x94 + 1643 09ad 02 .uleb128 0x2 + 1644 09ae 4B050000 .4byte .LASF127 + 1645 09b2 06 .byte 0x6 + 1646 09b3 A6 .byte 0xa6 + 1647 09b4 9F000000 .4byte 0x9f + 1648 09b8 02 .uleb128 0x2 + 1649 09b9 6C070000 .4byte .LASF128 + 1650 09bd 06 .byte 0x6 + 1651 09be C4 .byte 0xc4 + 1652 09bf 34000000 .4byte 0x34 + 1653 09c3 02 .uleb128 0x2 + 1654 09c4 DA060000 .4byte .LASF129 + 1655 09c8 06 .byte 0x6 + 1656 09c9 C9 .byte 0xc9 + 1657 09ca 50000000 .4byte 0x50 + 1658 09ce 0D .uleb128 0xd + 1659 09cf 6E020000 .4byte .LASF130 + 1660 09d3 3C .byte 0x3c + 1661 09d4 07 .byte 0x7 + 1662 09d5 19 .byte 0x19 + 1663 09d6 C90A0000 .4byte 0xac9 + 1664 09da 0B .uleb128 0xb + 1665 09db 7E020000 .4byte .LASF131 + 1666 09df 07 .byte 0x7 + 1667 09e0 1B .byte 0x1b + 1668 09e1 97090000 .4byte 0x997 + 1669 09e5 02 .byte 0x2 + 1670 09e6 23 .byte 0x23 + 1671 09e7 00 .uleb128 0 + 1672 09e8 0B .uleb128 0xb + 1673 09e9 0D040000 .4byte .LASF132 + 1674 09ed 07 .byte 0x7 + 1675 09ee 1C .byte 0x1c + 1676 09ef 81090000 .4byte 0x981 + 1677 09f3 02 .byte 0x2 + 1678 09f4 23 .byte 0x23 + 1679 09f5 02 .uleb128 0x2 + 1680 09f6 0B .uleb128 0xb + 1681 09f7 C9020000 .4byte .LASF133 + 1682 09fb 07 .byte 0x7 + 1683 09fc 1D .byte 0x1d + 1684 09fd B8090000 .4byte 0x9b8 + 1685 0a01 02 .byte 0x2 + 1686 0a02 23 .byte 0x23 + 1687 0a03 04 .uleb128 0x4 + 1688 0a04 0B .uleb128 0xb + 1689 0a05 E2020000 .4byte .LASF134 + 1690 0a09 07 .byte 0x7 + 1691 0a0a 1E .byte 0x1e + 1692 0a0b C3090000 .4byte 0x9c3 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 31 + + + 1693 0a0f 02 .byte 0x2 + 1694 0a10 23 .byte 0x23 + 1695 0a11 08 .uleb128 0x8 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.byte 0x7 + 1731 0a50 30 .byte 0x30 + 1732 0a51 6B090000 .4byte 0x96b + 1733 0a55 02 .byte 0x2 + 1734 0a56 23 .byte 0x23 + 1735 0a57 14 .uleb128 0x14 + 1736 0a58 0B .uleb128 0xb + 1737 0a59 DC040000 .4byte .LASF140 + 1738 0a5d 07 .byte 0x7 + 1739 0a5e 31 .byte 0x31 + 1740 0a5f 82000000 .4byte 0x82 + 1741 0a63 02 .byte 0x2 + 1742 0a64 23 .byte 0x23 + 1743 0a65 18 .uleb128 0x18 + 1744 0a66 0B .uleb128 0xb + 1745 0a67 46020000 .4byte .LASF141 + 1746 0a6b 07 .byte 0x7 + 1747 0a6c 32 .byte 0x32 + 1748 0a6d 6B090000 .4byte 0x96b + 1749 0a71 02 .byte 0x2 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 32 + + + 1750 0a72 23 .byte 0x23 + 1751 0a73 1C .uleb128 0x1c + 1752 0a74 0B .uleb128 0xb + 1753 0a75 E6040000 .4byte .LASF142 + 1754 0a79 07 .byte 0x7 + 1755 0a7a 33 .byte 0x33 + 1756 0a7b 82000000 .4byte 0x82 + 1757 0a7f 02 .byte 0x2 + 1758 0a80 23 .byte 0x23 + 1759 0a81 20 .uleb128 0x20 + 1760 0a82 0B .uleb128 0xb + 1761 0a83 2E060000 .4byte .LASF143 + 1762 0a87 07 .byte 0x7 + 1763 0a88 34 .byte 0x34 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0x23 + 1799 0ac7 34 .uleb128 0x34 + 1800 0ac8 00 .byte 0 + 1801 0ac9 08 .uleb128 0x8 + 1802 0aca 82000000 .4byte 0x82 + 1803 0ace D90A0000 .4byte 0xad9 + 1804 0ad2 09 .uleb128 0x9 + 1805 0ad3 F0000000 .4byte 0xf0 + 1806 0ad7 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 33 + + + 1807 0ad8 00 .byte 0 + 1808 0ad9 02 .uleb128 0x2 + 1809 0ada CE030000 .4byte .LASF148 + 1810 0ade 08 .byte 0x8 + 1811 0adf 2A .byte 0x2a + 1812 0ae0 42000000 .4byte 0x42 + 1813 0ae4 02 .uleb128 0x2 + 1814 0ae5 C6060000 .4byte .LASF149 + 1815 0ae9 08 .byte 0x8 + 1816 0aea 4F .byte 0x4f + 1817 0aeb 82000000 .4byte 0x82 + 1818 0aef 02 .uleb128 0x2 + 1819 0af0 8F010000 .4byte .LASF150 + 1820 0af4 08 .byte 0x8 + 1821 0af5 50 .byte 0x50 + 1822 0af6 3F010000 .4byte 0x13f + 1823 0afa 02 .uleb128 0x2 + 1824 0afb F6050000 .4byte .LASF151 + 1825 0aff 08 .byte 0x8 + 1826 0b00 78 .byte 0x78 + 1827 0b01 65000000 .4byte 0x65 + 1828 0b05 02 .uleb128 0x2 + 1829 0b06 13050000 .4byte .LASF152 + 1830 0b0a 09 .byte 0x9 + 1831 0b0b 2F .byte 0x2f + 1832 0b0c D90A0000 .4byte 0xad9 + 1833 0b10 02 .uleb128 0x2 + 1834 0b11 92030000 .4byte .LASF153 + 1835 0b15 09 .byte 0x9 + 1836 0b16 30 .byte 0x30 + 1837 0b17 D90A0000 .4byte 0xad9 + 1838 0b1b 02 .uleb128 0x2 + 1839 0b1c 9E060000 .4byte .LASF154 + 1840 0b20 09 .byte 0x9 + 1841 0b21 31 .byte 0x31 + 1842 0b22 D90A0000 .4byte 0xad9 + 1843 0b26 02 .uleb128 0x2 + 1844 0b27 CB010000 .4byte .LASF155 + 1845 0b2b 09 .byte 0x9 + 1846 0b2c 32 .byte 0x32 + 1847 0b2d EF0A0000 .4byte 0xaef + 1848 0b31 02 .uleb128 0x2 + 1849 0b32 A1040000 .4byte .LASF156 + 1850 0b36 09 .byte 0x9 + 1851 0b37 33 .byte 0x33 + 1852 0b38 E40A0000 .4byte 0xae4 + 1853 0b3c 02 .uleb128 0x2 + 1854 0b3d A2010000 .4byte .LASF157 + 1855 0b41 09 .byte 0x9 + 1856 0b42 35 .byte 0x35 + 1857 0b43 EF0A0000 .4byte 0xaef + 1858 0b47 02 .uleb128 0x2 + 1859 0b48 49000000 .4byte .LASF158 + 1860 0b4c 09 .byte 0x9 + 1861 0b4d 36 .byte 0x36 + 1862 0b4e EF0A0000 .4byte 0xaef + 1863 0b52 02 .uleb128 0x2 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 34 + + + 1864 0b53 8B030000 .4byte .LASF159 + 1865 0b57 0A .byte 0xa + 1866 0b58 2A .byte 0x2a + 1867 0b59 5D0B0000 .4byte 0xb5d + 1868 0b5d 0D .uleb128 0xd + 1869 0b5e 8B030000 .4byte .LASF159 + 1870 0b62 48 .byte 0x48 + 1871 0b63 0B .byte 0xb + 1872 0b64 5E .byte 0x5e + 1873 0b65 740C0000 .4byte 0xc74 + 1874 0b69 0B .uleb128 0xb + 1875 0b6a E2050000 .4byte .LASF160 + 1876 0b6e 0B .byte 0xb + 1877 0b6f 5F .byte 0x5f + 1878 0b70 990C0000 .4byte 0xc99 + 1879 0b74 02 .byte 0x2 + 1880 0b75 23 .byte 0x23 + 1881 0b76 00 .uleb128 0 + 1882 0b77 0B .uleb128 0xb + 1883 0b78 8E060000 .4byte .LASF161 + 1884 0b7c 0B .byte 0xb + 1885 0b7d 61 .byte 0x61 + 1886 0b7e 990C0000 .4byte 0xc99 + 1887 0b82 02 .byte 0x2 + 1888 0b83 23 .byte 0x23 + 1889 0b84 04 .uleb128 0x4 + 1890 0b85 0B .uleb128 0xb + 1891 0b86 26000000 .4byte .LASF162 + 1892 0b8a 0B .byte 0xb + 1893 0b8b 63 .byte 0x63 + 1894 0b8c 260B0000 .4byte 0xb26 + 1895 0b90 02 .byte 0x2 + 1896 0b91 23 .byte 0x23 + 1897 0b92 08 .uleb128 0x8 + 1898 0b93 0B .uleb128 0xb + 1899 0b94 FF050000 .4byte .LASF163 + 1900 0b98 0B .byte 0xb + 1901 0b99 64 .byte 0x64 + 1902 0b9a 6F0D0000 .4byte 0xd6f + 1903 0b9e 02 .byte 0x2 + 1904 0b9f 23 .byte 0x23 + 1905 0ba0 0C .uleb128 0xc + 1906 0ba1 0B .uleb128 0xb + 1907 0ba2 66020000 .4byte .LASF164 + 1908 0ba6 0B .byte 0xb + 1909 0ba7 66 .byte 0x66 + 1910 0ba8 990C0000 .4byte 0xc99 + 1911 0bac 02 .byte 0x2 + 1912 0bad 23 .byte 0x23 + 1913 0bae 10 .uleb128 0x10 + 1914 0baf 0B .uleb128 0xb + 1915 0bb0 AD030000 .4byte .LASF165 + 1916 0bb4 0B .byte 0xb + 1917 0bb5 67 .byte 0x67 + 1918 0bb6 990C0000 .4byte 0xc99 + 1919 0bba 02 .byte 0x2 + 1920 0bbb 23 .byte 0x23 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 35 + + + 1921 0bbc 14 .uleb128 0x14 + 1922 0bbd 0B .uleb128 0xb + 1923 0bbe 0C030000 .4byte .LASF166 + 1924 0bc2 0B .byte 0xb + 1925 0bc3 6E .byte 0x6e + 1926 0bc4 42060000 .4byte 0x642 + 1927 0bc8 02 .byte 0x2 + 1928 0bc9 23 .byte 0x23 + 1929 0bca 18 .uleb128 0x18 + 1930 0bcb 0B .uleb128 0xb + 1931 0bcc B5030000 .4byte .LASF167 + 1932 0bd0 0B .byte 0xb + 1933 0bd1 79 .byte 0x79 + 1934 0bd2 100B0000 .4byte 0xb10 + 1935 0bd6 02 .byte 0x2 + 1936 0bd7 23 .byte 0x23 + 1937 0bd8 1C .uleb128 0x1c + 1938 0bd9 0B .uleb128 0xb + 1939 0bda 99040000 .4byte .LASF168 + 1940 0bde 0B .byte 0xb + 1941 0bdf 7D .byte 0x7d + 1942 0be0 050B0000 .4byte 0xb05 + 1943 0be4 02 .byte 0x2 + 1944 0be5 23 .byte 0x23 + 1945 0be6 1D .uleb128 0x1d + 1946 0be7 0B .uleb128 0xb + 1947 0be8 F8060000 .4byte .LASF169 + 1948 0bec 0B .byte 0xb + 1949 0bed 82 .byte 0x82 + 1950 0bee 1B0B0000 .4byte 0xb1b + 1951 0bf2 02 .byte 0x2 + 1952 0bf3 23 .byte 0x23 + 1953 0bf4 1E .uleb128 0x1e + 1954 0bf5 0B .uleb128 0xb + 1955 0bf6 16000000 .4byte .LASF170 + 1956 0bfa 0B .byte 0xb + 1957 0bfb 89 .byte 0x89 + 1958 0bfc 920D0000 .4byte 0xd92 + 1959 0c00 02 .byte 0x2 + 1960 0c01 23 .byte 0x23 + 1961 0c02 20 .uleb128 0x20 + 1962 0c03 0E .uleb128 0xe + 1963 0c04 705F7500 .ascii "p_u\000" + 1964 0c08 0B .byte 0xb + 1965 0c09 AE .byte 0xae + 1966 0c0a B10E0000 .4byte 0xeb1 + 1967 0c0e 02 .byte 0x2 + 1968 0c0f 23 .byte 0x23 + 1969 0c10 24 .uleb128 0x24 + 1970 0c11 0B .uleb128 0xb + 1971 0c12 0C000000 .4byte .LASF171 + 1972 0c16 0B .byte 0xb + 1973 0c17 B3 .byte 0xb3 + 1974 0c18 C10C0000 .4byte 0xcc1 + 1975 0c1c 02 .byte 0x2 + 1976 0c1d 23 .byte 0x23 + 1977 0c1e 28 .uleb128 0x28 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 36 + + + 1978 0c1f 0B .uleb128 0xb + 1979 0c20 74000000 .4byte .LASF172 + 1980 0c24 0B .byte 0xb + 1981 0c25 B9 .byte 0xb9 + 1982 0c26 9F0C0000 .4byte 0xc9f + 1983 0c2a 02 .byte 0x2 + 1984 0c2b 23 .byte 0x23 + 1985 0c2c 2C .uleb128 0x2c + 1986 0c2d 0B .uleb128 0xb + 1987 0c2e 0D050000 .4byte .LASF173 + 1988 0c32 0B .byte 0xb + 1989 0c33 BD .byte 0xbd + 1990 0c34 310B0000 .4byte 0xb31 + 1991 0c38 02 .byte 0x2 + 1992 0c39 23 .byte 0x23 + 1993 0c3a 34 .uleb128 0x34 + 1994 0c3b 0B .uleb128 0xb + 1995 0c3c AB050000 .4byte .LASF174 + 1996 0c40 0B .byte 0xb + 1997 0c41 C3 .byte 0xc3 + 1998 0c42 3C0B0000 .4byte 0xb3c + 1999 0c46 02 .byte 0x2 + 2000 0c47 23 .byte 0x23 + 2001 0c48 38 .uleb128 0x38 + 2002 0c49 0B .uleb128 0xb + 2003 0c4a F8030000 .4byte .LASF175 + 2004 0c4e 0B .byte 0xb + 2005 0c4f CA .byte 0xca + 2006 0c50 E60E0000 .4byte 0xee6 + 2007 0c54 02 .byte 0x2 + 2008 0c55 23 .byte 0x23 + 2009 0c56 3C .uleb128 0x3c + 2010 0c57 0B .uleb128 0xb + 2011 0c58 8A050000 .4byte .LASF176 + 2012 0c5c 0B .byte 0xb + 2013 0c5d CE .byte 0xce + 2014 0c5e 260B0000 .4byte 0xb26 + 2015 0c62 02 .byte 0x2 + 2016 0c63 23 .byte 0x23 + 2017 0c64 40 .uleb128 0x40 + 2018 0c65 0B .uleb128 0xb + 2019 0c66 F0030000 .4byte .LASF177 + 2020 0c6a 0B .byte 0xb + 2021 0c6b D4 .byte 0xd4 + 2022 0c6c 32010000 .4byte 0x132 + 2023 0c70 02 .byte 0x2 + 2024 0c71 23 .byte 0x23 + 2025 0c72 44 .uleb128 0x44 + 2026 0c73 00 .byte 0 + 2027 0c74 0A .uleb128 0xa + 2028 0c75 08 .byte 0x8 + 2029 0c76 0A .byte 0xa + 2030 0c77 61 .byte 0x61 + 2031 0c78 990C0000 .4byte 0xc99 + 2032 0c7c 0B .uleb128 0xb + 2033 0c7d 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.4byte .LLST6 + 2536 1047 25 .uleb128 0x25 + 2537 1048 FA020000 .4byte .LASF208 + 2538 104c 01 .byte 0x1 + 2539 104d 8D .byte 0x8d + 2540 104e 57000000 .4byte 0x57 + 2541 1052 E3000000 .4byte .LLST7 + 2542 1056 26 .uleb128 0x26 + 2543 1057 7000 .ascii "p\000" + 2544 1059 01 .byte 0x1 + 2545 105a 90 .byte 0x90 + 2546 105b 32010000 .4byte 0x132 + 2547 105f 04010000 .4byte .LLST8 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 46 + + + 2548 1063 27 .uleb128 0x27 + 2549 1064 0A000000 .4byte .LVL11 + 2550 1068 B9120000 .4byte 0x12b9 + 2551 106c 28 .uleb128 0x28 + 2552 106d 01 .byte 0x1 + 2553 106e 50 .byte 0x50 + 2554 106f 03 .byte 0x3 + 2555 1070 F3 .byte 0xf3 + 2556 1071 01 .uleb128 0x1 + 2557 1072 51 .byte 0x51 + 2558 1073 00 .byte 0 + 2559 1074 00 .byte 0 + 2560 1075 24 .uleb128 0x24 + 2561 1076 01 .byte 0x1 + 2562 1077 EB020000 .4byte .LASF209 + 2563 107b 01 .byte 0x1 + 2564 107c A3 .byte 0xa3 + 2565 107d 01 .byte 0x1 + 2566 107e 57000000 .4byte 0x57 + 2567 1082 00000000 .4byte .LFB12 + 2568 1086 18000000 .4byte .LFE12 + 2569 108a 17010000 .4byte .LLST9 + 2570 108e 01 .byte 0x1 + 2571 108f D9100000 .4byte 0x10d9 + 2572 1093 21 .uleb128 0x21 + 2573 1094 7200 .ascii "r\000" + 2574 1096 01 .byte 0x1 + 2575 1097 A3 .byte 0xa3 + 2576 1098 AC040000 .4byte 0x4ac + 2577 109c 37010000 .4byte .LLST10 + 2578 10a0 25 .uleb128 0x25 + 2579 10a1 BD030000 .4byte .LASF202 + 2580 10a5 01 .byte 0x1 + 2581 10a6 A3 .byte 0xa3 + 2582 10a7 57000000 .4byte 0x57 + 2583 10ab 58010000 .4byte .LLST11 + 2584 10af 21 .uleb128 0x21 + 2585 10b0 737400 .ascii "st\000" + 2586 10b3 01 .byte 0x1 + 2587 10b4 A3 .byte 0xa3 + 2588 10b5 D9100000 .4byte 0x10d9 + 2589 10b9 79010000 .4byte .LLST12 + 2590 10bd 27 .uleb128 0x27 + 2591 10be 0E000000 .4byte .LVL17 + 2592 10c2 D1120000 .4byte 0x12d1 + 2593 10c6 28 .uleb128 0x28 + 2594 10c7 01 .byte 0x1 + 2595 10c8 52 .byte 0x52 + 2596 10c9 02 .byte 0x2 + 2597 10ca 08 .byte 0x8 + 2598 10cb 3C .byte 0x3c + 2599 10cc 28 .uleb128 0x28 + 2600 10cd 01 .byte 0x1 + 2601 10ce 51 .byte 0x51 + 2602 10cf 01 .byte 0x1 + 2603 10d0 30 .byte 0x30 + 2604 10d1 28 .uleb128 0x28 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 47 + + + 2605 10d2 01 .byte 0x1 + 2606 10d3 50 .byte 0x50 + 2607 10d4 02 .byte 0x2 + 2608 10d5 74 .byte 0x74 + 2609 10d6 00 .sleb128 0 + 2610 10d7 00 .byte 0 + 2611 10d8 00 .byte 0 + 2612 10d9 0F .uleb128 0xf + 2613 10da 04 .byte 0x4 + 2614 10db CE090000 .4byte 0x9ce + 2615 10df 20 .uleb128 0x20 + 2616 10e0 01 .byte 0x1 + 2617 10e1 DA010000 .4byte .LASF210 + 2618 10e5 01 .byte 0x1 + 2619 10e6 AF .byte 0xaf + 2620 10e7 01 .byte 0x1 + 2621 10e8 57000000 .4byte 0x57 + 2622 10ec 00000000 .4byte .LFB13 + 2623 10f0 04000000 .4byte .LFE13 + 2624 10f4 02 .byte 0x2 + 2625 10f5 7D .byte 0x7d + 2626 10f6 00 .sleb128 0 + 2627 10f7 01 .byte 0x1 + 2628 10f8 16110000 .4byte 0x1116 + 2629 10fc 21 .uleb128 0x21 + 2630 10fd 7200 .ascii "r\000" + 2631 10ff 01 .byte 0x1 + 2632 1100 AF .byte 0xaf + 2633 1101 AC040000 .4byte 0x4ac + 2634 1105 A2010000 .4byte .LLST13 + 2635 1109 23 .uleb128 0x23 + 2636 110a 666400 .ascii "fd\000" + 2637 110d 01 .byte 0x1 + 2638 110e AF .byte 0xaf + 2639 110f 57000000 .4byte 0x57 + 2640 1113 01 .byte 0x1 + 2641 1114 51 .byte 0x51 + 2642 1115 00 .byte 0 + 2643 1116 24 .uleb128 0x24 + 2644 1117 01 .byte 0x1 + 2645 1118 6E050000 .4byte .LASF211 + 2646 111c 10 .byte 0x10 + 2647 111d D3 .byte 0xd3 + 2648 111e 01 .byte 0x1 + 2649 111f 32010000 .4byte 0x132 + 2650 1123 00000000 .4byte .LFB14 + 2651 1127 24000000 .4byte .LFE14 + 2652 112b C3010000 .4byte .LLST14 + 2653 112f 01 .byte 0x1 + 2654 1130 B9110000 .4byte 0x11b9 + 2655 1134 21 .uleb128 0x21 + 2656 1135 726500 .ascii "re\000" + 2657 1138 01 .byte 0x1 + 2658 1139 B7 .byte 0xb7 + 2659 113a AC040000 .4byte 0x4ac + 2660 113e E3010000 .4byte .LLST15 + 2661 1142 25 .uleb128 0x25 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 48 + + + 2662 1143 05060000 .4byte .LASF212 + 2663 1147 01 .byte 0x1 + 2664 1148 B7 .byte 0xb7 + 2665 1149 32010000 .4byte 0x132 + 2666 114d 04020000 .4byte .LLST16 + 2667 1151 25 .uleb128 0x25 + 2668 1152 8B000000 .4byte .LASF213 + 2669 1156 01 .byte 0x1 + 2670 1157 B7 .byte 0xb7 + 2671 1158 29000000 .4byte 0x29 + 2672 115c 22020000 .4byte .LLST17 + 2673 1160 29 .uleb128 0x29 + 2674 1161 56020000 .4byte .LASF214 + 2675 1165 01 .byte 0x1 + 2676 1166 B8 .byte 0xb8 + 2677 1167 32010000 .4byte 0x132 + 2678 116b 40020000 .4byte .LLST18 + 2679 116f 2A .uleb128 0x2a + 2680 1170 0E000000 .4byte .LVL23 + 2681 1174 F2120000 .4byte 0x12f2 + 2682 1178 88110000 .4byte 0x1188 + 2683 117c 28 .uleb128 0x28 + 2684 117d 01 .byte 0x1 + 2685 117e 51 .byte 0x51 + 2686 117f 02 .byte 0x2 + 2687 1180 74 .byte 0x74 + 2688 1181 00 .sleb128 0 + 2689 1182 28 .uleb128 0x28 + 2690 1183 01 .byte 0x1 + 2691 1184 50 .byte 0x50 + 2692 1185 01 .byte 0x1 + 2693 1186 30 .byte 0x30 + 2694 1187 00 .byte 0 + 2695 1188 2A .uleb128 0x2a + 2696 1189 1A000000 .4byte .LVL24 + 2697 118d 0F130000 .4byte 0x130f + 2698 1191 A8110000 .4byte 0x11a8 + 2699 1195 28 .uleb128 0x28 + 2700 1196 01 .byte 0x1 + 2701 1197 52 .byte 0x52 + 2702 1198 02 .byte 0x2 + 2703 1199 74 .byte 0x74 + 2704 119a 00 .sleb128 0 + 2705 119b 28 .uleb128 0x28 + 2706 119c 01 .byte 0x1 + 2707 119d 51 .byte 0x51 + 2708 119e 02 .byte 0x2 + 2709 119f 75 .byte 0x75 + 2710 11a0 00 .sleb128 0 + 2711 11a1 28 .uleb128 0x28 + 2712 11a2 01 .byte 0x1 + 2713 11a3 50 .byte 0x50 + 2714 11a4 02 .byte 0x2 + 2715 11a5 76 .byte 0x76 + 2716 11a6 00 .sleb128 0 + 2717 11a7 00 .byte 0 + 2718 11a8 27 .uleb128 0x27 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 49 + + + 2719 11a9 20000000 .4byte .LVL25 + 2720 11ad 37130000 .4byte 0x1337 + 2721 11b1 28 .uleb128 0x28 + 2722 11b2 01 .byte 0x1 + 2723 11b3 50 .byte 0x50 + 2724 11b4 02 .byte 0x2 + 2725 11b5 75 .byte 0x75 + 2726 11b6 00 .sleb128 0 + 2727 11b7 00 .byte 0 + 2728 11b8 00 .byte 0 + 2729 11b9 20 .uleb128 0x20 + 2730 11ba 01 .byte 0x1 + 2731 11bb 37060000 .4byte .LASF215 + 2732 11bf 10 .byte 0x10 + 2733 11c0 D1 .byte 0xd1 + 2734 11c1 01 .byte 0x1 + 2735 11c2 32010000 .4byte 0x132 + 2736 11c6 00000000 .4byte .LFB15 + 2737 11ca 0A000000 .4byte .LFE15 + 2738 11ce 02 .byte 0x2 + 2739 11cf 7D .byte 0x7d + 2740 11d0 00 .sleb128 0 + 2741 11d1 01 .byte 0x1 + 2742 11d2 1E120000 .4byte 0x121e + 2743 11d6 21 .uleb128 0x21 + 2744 11d7 726500 .ascii "re\000" + 2745 11da 01 .byte 0x1 + 2746 11db C7 .byte 0xc7 + 2747 11dc AC040000 .4byte 0x4ac + 2748 11e0 5E020000 .4byte .LLST19 + 2749 11e4 21 .uleb128 0x21 + 2750 11e5 6E756D00 .ascii "num\000" + 2751 11e9 01 .byte 0x1 + 2752 11ea C7 .byte 0xc7 + 2753 11eb 29000000 .4byte 0x29 + 2754 11ef 7F020000 .4byte .LLST20 + 2755 11f3 25 .uleb128 0x25 + 2756 11f4 C3040000 .4byte .LASF197 + 2757 11f8 01 .byte 0x1 + 2758 11f9 C7 .byte 0xc7 + 2759 11fa 29000000 .4byte 0x29 + 2760 11fe A0020000 .4byte .LLST21 + 2761 1202 2B .uleb128 0x2b + 2762 1203 0A000000 .4byte .LVL29 + 2763 1207 01 .byte 0x1 + 2764 1208 F2120000 .4byte 0x12f2 + 2765 120c 28 .uleb128 0x28 + 2766 120d 01 .byte 0x1 + 2767 120e 51 .byte 0x51 + 2768 120f 07 .byte 0x7 + 2769 1210 F3 .byte 0xf3 + 2770 1211 01 .uleb128 0x1 + 2771 1212 51 .byte 0x51 + 2772 1213 F3 .byte 0xf3 + 2773 1214 01 .uleb128 0x1 + 2774 1215 52 .byte 0x52 + 2775 1216 1E .byte 0x1e + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 50 + + + 2776 1217 28 .uleb128 0x28 + 2777 1218 01 .byte 0x1 + 2778 1219 50 .byte 0x50 + 2779 121a 01 .byte 0x1 + 2780 121b 30 .byte 0x30 + 2781 121c 00 .byte 0 + 2782 121d 00 .byte 0 + 2783 121e 20 .uleb128 0x20 + 2784 121f 01 .byte 0x1 + 2785 1220 13030000 .4byte .LASF216 + 2786 1224 10 .byte 0x10 + 2787 1225 D0 .byte 0xd0 + 2788 1226 01 .byte 0x1 + 2789 1227 32010000 .4byte 0x132 + 2790 122b 00000000 .4byte .LFB16 + 2791 122f 06000000 .4byte .LFE16 + 2792 1233 02 .byte 0x2 + 2793 1234 7D .byte 0x7d + 2794 1235 00 .sleb128 0 + 2795 1236 01 .byte 0x1 + 2796 1237 70120000 .4byte 0x1270 + 2797 123b 21 .uleb128 0x21 + 2798 123c 726500 .ascii "re\000" + 2799 123f 01 .byte 0x1 + 2800 1240 CB .byte 0xcb + 2801 1241 AC040000 .4byte 0x4ac + 2802 1245 C1020000 .4byte .LLST22 + 2803 1249 25 .uleb128 0x25 + 2804 124a C3040000 .4byte .LASF197 + 2805 124e 01 .byte 0x1 + 2806 124f CB .byte 0xcb + 2807 1250 29000000 .4byte 0x29 + 2808 1254 E2020000 .4byte .LLST23 + 2809 1258 2B .uleb128 0x2b + 2810 1259 06000000 .4byte .LVL32 + 2811 125d 01 .byte 0x1 + 2812 125e F2120000 .4byte 0x12f2 + 2813 1262 28 .uleb128 0x28 + 2814 1263 01 .byte 0x1 + 2815 1264 51 .byte 0x51 + 2816 1265 03 .byte 0x3 + 2817 1266 F3 .byte 0xf3 + 2818 1267 01 .uleb128 0x1 + 2819 1268 51 .byte 0x51 + 2820 1269 28 .uleb128 0x28 + 2821 126a 01 .byte 0x1 + 2822 126b 50 .byte 0x50 + 2823 126c 01 .byte 0x1 + 2824 126d 30 .byte 0x30 + 2825 126e 00 .byte 0 + 2826 126f 00 .byte 0 + 2827 1270 2C .uleb128 0x2c + 2828 1271 01 .byte 0x1 + 2829 1272 35010000 .4byte .LASF225 + 2830 1276 10 .byte 0x10 + 2831 1277 D2 .byte 0xd2 + 2832 1278 01 .byte 0x1 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 51 + + + 2833 1279 00000000 .4byte .LFB17 + 2834 127d 06000000 .4byte .LFE17 + 2835 1281 02 .byte 0x2 + 2836 1282 7D .byte 0x7d + 2837 1283 00 .sleb128 0 + 2838 1284 01 .byte 0x1 + 2839 1285 B9120000 .4byte 0x12b9 + 2840 1289 21 .uleb128 0x21 + 2841 128a 726500 .ascii "re\000" + 2842 128d 01 .byte 0x1 + 2843 128e CF .byte 0xcf + 2844 128f AC040000 .4byte 0x4ac + 2845 1293 03030000 .4byte .LLST24 + 2846 1297 21 .uleb128 0x21 + 2847 1298 70747200 .ascii "ptr\000" + 2848 129c 01 .byte 0x1 + 2849 129d CF .byte 0xcf + 2850 129e 32010000 .4byte 0x132 + 2851 12a2 24030000 .4byte .LLST25 + 2852 12a6 2B .uleb128 0x2b + 2853 12a7 06000000 .4byte .LVL35 + 2854 12ab 01 .byte 0x1 + 2855 12ac 37130000 .4byte 0x1337 + 2856 12b0 28 .uleb128 0x28 + 2857 12b1 01 .byte 0x1 + 2858 12b2 50 .byte 0x50 + 2859 12b3 03 .byte 0x3 + 2860 12b4 F3 .byte 0xf3 + 2861 12b5 01 .uleb128 0x1 + 2862 12b6 51 .byte 0x51 + 2863 12b7 00 .byte 0 + 2864 12b8 00 .byte 0 + 2865 12b9 2D .uleb128 0x2d + 2866 12ba 01 .byte 0x1 + 2867 12bb 3E040000 .4byte .LASF217 + 2868 12bf 0E .byte 0xe + 2869 12c0 52 .byte 0x52 + 2870 12c1 01 .byte 0x1 + 2871 12c2 32010000 .4byte 0x132 + 2872 12c6 01 .byte 0x1 + 2873 12c7 D1120000 .4byte 0x12d1 + 2874 12cb 13 .uleb128 0x13 + 2875 12cc 29000000 .4byte 0x29 + 2876 12d0 00 .byte 0 + 2877 12d1 2E .uleb128 0x2e + 2878 12d2 01 .byte 0x1 + 2879 12d3 A7040000 .4byte .LASF219 + 2880 12d7 01 .byte 0x1 + 2881 12d8 32010000 .4byte 0x132 + 2882 12dc 01 .byte 0x1 + 2883 12dd 01 .byte 0x1 + 2884 12de F2120000 .4byte 0x12f2 + 2885 12e2 13 .uleb128 0x13 + 2886 12e3 32010000 .4byte 0x132 + 2887 12e7 13 .uleb128 0x13 + 2888 12e8 57000000 .4byte 0x57 + 2889 12ec 13 .uleb128 0x13 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 52 + + + 2890 12ed F0000000 .4byte 0xf0 + 2891 12f1 00 .byte 0 + 2892 12f2 2D .uleb128 0x2d + 2893 12f3 01 .byte 0x1 + 2894 12f4 DD030000 .4byte .LASF218 + 2895 12f8 0F .byte 0xf + 2896 12f9 59 .byte 0x59 + 2897 12fa 01 .byte 0x1 + 2898 12fb 32010000 .4byte 0x132 + 2899 12ff 01 .byte 0x1 + 2900 1300 0F130000 .4byte 0x130f + 2901 1304 13 .uleb128 0x13 + 2902 1305 880E0000 .4byte 0xe88 + 2903 1309 13 .uleb128 0x13 + 2904 130a 29000000 .4byte 0x29 + 2905 130e 00 .byte 0 + 2906 130f 2E .uleb128 0x2e + 2907 1310 01 .byte 0x1 + 2908 1311 A9070000 .4byte .LASF220 + 2909 1315 01 .byte 0x1 + 2910 1316 32010000 .4byte 0x132 + 2911 131a 01 .byte 0x1 + 2912 131b 01 .byte 0x1 + 2913 131c 30130000 .4byte 0x1330 + 2914 1320 13 .uleb128 0x13 + 2915 1321 32010000 .4byte 0x132 + 2916 1325 13 .uleb128 0x13 + 2917 1326 30130000 .4byte 0x1330 + 2918 132a 13 .uleb128 0x13 + 2919 132b F0000000 .4byte 0xf0 + 2920 132f 00 .byte 0 + 2921 1330 0F .uleb128 0xf + 2922 1331 04 .byte 0x4 + 2923 1332 36130000 .4byte 0x1336 + 2924 1336 2F .uleb128 0x2f + 2925 1337 30 .uleb128 0x30 + 2926 1338 01 .byte 0x1 + 2927 1339 69000000 .4byte .LASF226 + 2928 133d 0F .byte 0xf + 2929 133e 5A .byte 0x5a + 2930 133f 01 .byte 0x1 + 2931 1340 01 .byte 0x1 + 2932 1341 13 .uleb128 0x13 + 2933 1342 32010000 .4byte 0x132 + 2934 1346 00 .byte 0 + 2935 1347 00 .byte 0 + 2936 .section .debug_abbrev,"",%progbits + 2937 .Ldebug_abbrev0: + 2938 0000 01 .uleb128 0x1 + 2939 0001 11 .uleb128 0x11 + 2940 0002 01 .byte 0x1 + 2941 0003 25 .uleb128 0x25 + 2942 0004 0E .uleb128 0xe + 2943 0005 13 .uleb128 0x13 + 2944 0006 0B .uleb128 0xb + 2945 0007 03 .uleb128 0x3 + 2946 0008 0E .uleb128 0xe + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 53 + + + 2947 0009 1B .uleb128 0x1b + 2948 000a 0E .uleb128 0xe + 2949 000b 55 .uleb128 0x55 + 2950 000c 06 .uleb128 0x6 + 2951 000d 11 .uleb128 0x11 + 2952 000e 01 .uleb128 0x1 + 2953 000f 52 .uleb128 0x52 + 2954 0010 01 .uleb128 0x1 + 2955 0011 10 .uleb128 0x10 + 2956 0012 06 .uleb128 0x6 + 2957 0013 00 .byte 0 + 2958 0014 00 .byte 0 + 2959 0015 02 .uleb128 0x2 + 2960 0016 16 .uleb128 0x16 + 2961 0017 00 .byte 0 + 2962 0018 03 .uleb128 0x3 + 2963 0019 0E .uleb128 0xe + 2964 001a 3A .uleb128 0x3a + 2965 001b 0B .uleb128 0xb + 2966 001c 3B .uleb128 0x3b + 2967 001d 0B .uleb128 0xb + 2968 001e 49 .uleb128 0x49 + 2969 001f 13 .uleb128 0x13 + 2970 0020 00 .byte 0 + 2971 0021 00 .byte 0 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0045 06 .uleb128 0x6 + 3008 0046 17 .uleb128 0x17 + 3009 0047 01 .byte 0x1 + 3010 0048 0B .uleb128 0xb + 3011 0049 0B .uleb128 0xb + 3012 004a 3A .uleb128 0x3a + 3013 004b 0B .uleb128 0xb + 3014 004c 3B .uleb128 0x3b + 3015 004d 0B .uleb128 0xb + 3016 004e 01 .uleb128 0x1 + 3017 004f 13 .uleb128 0x13 + 3018 0050 00 .byte 0 + 3019 0051 00 .byte 0 + 3020 0052 07 .uleb128 0x7 + 3021 0053 0D .uleb128 0xd + 3022 0054 00 .byte 0 + 3023 0055 03 .uleb128 0x3 + 3024 0056 0E .uleb128 0xe + 3025 0057 3A .uleb128 0x3a + 3026 0058 0B .uleb128 0xb + 3027 0059 3B .uleb128 0x3b + 3028 005a 0B .uleb128 0xb + 3029 005b 49 .uleb128 0x49 + 3030 005c 13 .uleb128 0x13 + 3031 005d 00 .byte 0 + 3032 005e 00 .byte 0 + 3033 005f 08 .uleb128 0x8 + 3034 0060 01 .uleb128 0x1 + 3035 0061 01 .byte 0x1 + 3036 0062 49 .uleb128 0x49 + 3037 0063 13 .uleb128 0x13 + 3038 0064 01 .uleb128 0x1 + 3039 0065 13 .uleb128 0x13 + 3040 0066 00 .byte 0 + 3041 0067 00 .byte 0 + 3042 0068 09 .uleb128 0x9 + 3043 0069 21 .uleb128 0x21 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.uleb128 0x15 + 3258 0140 01 .byte 0x1 + 3259 0141 27 .uleb128 0x27 + 3260 0142 0C .uleb128 0xc + 3261 0143 01 .uleb128 0x1 + 3262 0144 13 .uleb128 0x13 + 3263 0145 00 .byte 0 + 3264 0146 00 .byte 0 + 3265 0147 1C .uleb128 0x1c + 3266 0148 0D .uleb128 0xd + 3267 0149 00 .byte 0 + 3268 014a 03 .uleb128 0x3 + 3269 014b 08 .uleb128 0x8 + 3270 014c 3A .uleb128 0x3a + 3271 014d 0B .uleb128 0xb + 3272 014e 3B .uleb128 0x3b + 3273 014f 05 .uleb128 0x5 + 3274 0150 49 .uleb128 0x49 + 3275 0151 13 .uleb128 0x13 + 3276 0152 38 .uleb128 0x38 + 3277 0153 0A .uleb128 0xa + 3278 0154 00 .byte 0 + 3279 0155 00 .byte 0 + 3280 0156 1D .uleb128 0x1d + 3281 0157 35 .uleb128 0x35 + 3282 0158 00 .byte 0 + 3283 0159 49 .uleb128 0x49 + 3284 015a 13 .uleb128 0x13 + 3285 015b 00 .byte 0 + 3286 015c 00 .byte 0 + 3287 015d 1E .uleb128 0x1e + 3288 015e 17 .uleb128 0x17 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 59 + + + 3289 015f 01 .byte 0x1 + 3290 0160 03 .uleb128 0x3 + 3291 0161 0E .uleb128 0xe + 3292 0162 0B .uleb128 0xb + 3293 0163 0B .uleb128 0xb + 3294 0164 3A .uleb128 0x3a + 3295 0165 0B .uleb128 0xb + 3296 0166 3B .uleb128 0x3b + 3297 0167 0B .uleb128 0xb + 3298 0168 01 .uleb128 0x1 + 3299 0169 13 .uleb128 0x13 + 3300 016a 00 .byte 0 + 3301 016b 00 .byte 0 + 3302 016c 1F .uleb128 0x1f + 3303 016d 0D .uleb128 0xd + 3304 016e 00 .byte 0 + 3305 016f 03 .uleb128 0x3 + 3306 0170 08 .uleb128 0x8 + 3307 0171 3A .uleb128 0x3a + 3308 0172 0B .uleb128 0xb + 3309 0173 3B .uleb128 0x3b + 3310 0174 0B .uleb128 0xb + 3311 0175 49 .uleb128 0x49 + 3312 0176 13 .uleb128 0x13 + 3313 0177 00 .byte 0 + 3314 0178 00 .byte 0 + 3315 0179 20 .uleb128 0x20 + 3316 017a 2E .uleb128 0x2e + 3317 017b 01 .byte 0x1 + 3318 017c 3F .uleb128 0x3f + 3319 017d 0C .uleb128 0xc + 3320 017e 03 .uleb128 0x3 + 3321 017f 0E .uleb128 0xe + 3322 0180 3A .uleb128 0x3a + 3323 0181 0B .uleb128 0xb + 3324 0182 3B .uleb128 0x3b + 3325 0183 0B .uleb128 0xb + 3326 0184 27 .uleb128 0x27 + 3327 0185 0C .uleb128 0xc + 3328 0186 49 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01ce 0C .uleb128 0xc + 3400 01cf 49 .uleb128 0x49 + 3401 01d0 13 .uleb128 0x13 + 3402 01d1 11 .uleb128 0x11 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 61 + + + 3403 01d2 01 .uleb128 0x1 + 3404 01d3 12 .uleb128 0x12 + 3405 01d4 01 .uleb128 0x1 + 3406 01d5 40 .uleb128 0x40 + 3407 01d6 06 .uleb128 0x6 + 3408 01d7 9742 .uleb128 0x2117 + 3409 01d9 0C .uleb128 0xc + 3410 01da 01 .uleb128 0x1 + 3411 01db 13 .uleb128 0x13 + 3412 01dc 00 .byte 0 + 3413 01dd 00 .byte 0 + 3414 01de 25 .uleb128 0x25 + 3415 01df 05 .uleb128 0x5 + 3416 01e0 00 .byte 0 + 3417 01e1 03 .uleb128 0x3 + 3418 01e2 0E .uleb128 0xe + 3419 01e3 3A .uleb128 0x3a + 3420 01e4 0B .uleb128 0xb + 3421 01e5 3B .uleb128 0x3b + 3422 01e6 0B .uleb128 0xb + 3423 01e7 49 .uleb128 0x49 + 3424 01e8 13 .uleb128 0x13 + 3425 01e9 02 .uleb128 0x2 + 3426 01ea 06 .uleb128 0x6 + 3427 01eb 00 .byte 0 + 3428 01ec 00 .byte 0 + 3429 01ed 26 .uleb128 0x26 + 3430 01ee 34 .uleb128 0x34 + 3431 01ef 00 .byte 0 + 3432 01f0 03 .uleb128 0x3 + 3433 01f1 08 .uleb128 0x8 + 3434 01f2 3A .uleb128 0x3a + 3435 01f3 0B .uleb128 0xb + 3436 01f4 3B .uleb128 0x3b + 3437 01f5 0B .uleb128 0xb + 3438 01f6 49 .uleb128 0x49 + 3439 01f7 13 .uleb128 0x13 + 3440 01f8 02 .uleb128 0x2 + 3441 01f9 06 .uleb128 0x6 + 3442 01fa 00 .byte 0 + 3443 01fb 00 .byte 0 + 3444 01fc 27 .uleb128 0x27 + 3445 01fd 898201 .uleb128 0x4109 + 3446 0200 01 .byte 0x1 + 3447 0201 11 .uleb128 0x11 + 3448 0202 01 .uleb128 0x1 + 3449 0203 31 .uleb128 0x31 + 3450 0204 13 .uleb128 0x13 + 3451 0205 00 .byte 0 + 3452 0206 00 .byte 0 + 3453 0207 28 .uleb128 0x28 + 3454 0208 8A8201 .uleb128 0x410a + 3455 020b 00 .byte 0 + 3456 020c 02 .uleb128 0x2 + 3457 020d 0A .uleb128 0xa + 3458 020e 9142 .uleb128 0x2111 + 3459 0210 0A .uleb128 0xa + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 62 + + + 3460 0211 00 .byte 0 + 3461 0212 00 .byte 0 + 3462 0213 29 .uleb128 0x29 + 3463 0214 34 .uleb128 0x34 + 3464 0215 00 .byte 0 + 3465 0216 03 .uleb128 0x3 + 3466 0217 0E .uleb128 0xe + 3467 0218 3A .uleb128 0x3a + 3468 0219 0B .uleb128 0xb + 3469 021a 3B .uleb128 0x3b + 3470 021b 0B .uleb128 0xb + 3471 021c 49 .uleb128 0x49 + 3472 021d 13 .uleb128 0x13 + 3473 021e 02 .uleb128 0x2 + 3474 021f 06 .uleb128 0x6 + 3475 0220 00 .byte 0 + 3476 0221 00 .byte 0 + 3477 0222 2A .uleb128 0x2a + 3478 0223 898201 .uleb128 0x4109 + 3479 0226 01 .byte 0x1 + 3480 0227 11 .uleb128 0x11 + 3481 0228 01 .uleb128 0x1 + 3482 0229 31 .uleb128 0x31 + 3483 022a 13 .uleb128 0x13 + 3484 022b 01 .uleb128 0x1 + 3485 022c 13 .uleb128 0x13 + 3486 022d 00 .byte 0 + 3487 022e 00 .byte 0 + 3488 022f 2B .uleb128 0x2b + 3489 0230 898201 .uleb128 0x4109 + 3490 0233 01 .byte 0x1 + 3491 0234 11 .uleb128 0x11 + 3492 0235 01 .uleb128 0x1 + 3493 0236 9542 .uleb128 0x2115 + 3494 0238 0C .uleb128 0xc + 3495 0239 31 .uleb128 0x31 + 3496 023a 13 .uleb128 0x13 + 3497 023b 00 .byte 0 + 3498 023c 00 .byte 0 + 3499 023d 2C .uleb128 0x2c + 3500 023e 2E .uleb128 0x2e + 3501 023f 01 .byte 0x1 + 3502 0240 3F .uleb128 0x3f + 3503 0241 0C .uleb128 0xc + 3504 0242 03 .uleb128 0x3 + 3505 0243 0E .uleb128 0xe + 3506 0244 3A .uleb128 0x3a + 3507 0245 0B .uleb128 0xb + 3508 0246 3B .uleb128 0x3b + 3509 0247 0B .uleb128 0xb + 3510 0248 27 .uleb128 0x27 + 3511 0249 0C .uleb128 0xc + 3512 024a 11 .uleb128 0x11 + 3513 024b 01 .uleb128 0x1 + 3514 024c 12 .uleb128 0x12 + 3515 024d 01 .uleb128 0x1 + 3516 024e 40 .uleb128 0x40 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 63 + + + 3517 024f 0A .uleb128 0xa + 3518 0250 9742 .uleb128 0x2117 + 3519 0252 0C .uleb128 0xc + 3520 0253 01 .uleb128 0x1 + 3521 0254 13 .uleb128 0x13 + 3522 0255 00 .byte 0 + 3523 0256 00 .byte 0 + 3524 0257 2D .uleb128 0x2d + 3525 0258 2E .uleb128 0x2e + 3526 0259 01 .byte 0x1 + 3527 025a 3F .uleb128 0x3f + 3528 025b 0C .uleb128 0xc + 3529 025c 03 .uleb128 0x3 + 3530 025d 0E .uleb128 0xe + 3531 025e 3A .uleb128 0x3a + 3532 025f 0B .uleb128 0xb + 3533 0260 3B .uleb128 0x3b + 3534 0261 0B .uleb128 0xb + 3535 0262 27 .uleb128 0x27 + 3536 0263 0C .uleb128 0xc + 3537 0264 49 .uleb128 0x49 + 3538 0265 13 .uleb128 0x13 + 3539 0266 3C .uleb128 0x3c + 3540 0267 0C .uleb128 0xc + 3541 0268 01 .uleb128 0x1 + 3542 0269 13 .uleb128 0x13 + 3543 026a 00 .byte 0 + 3544 026b 00 .byte 0 + 3545 026c 2E .uleb128 0x2e + 3546 026d 2E .uleb128 0x2e + 3547 026e 01 .byte 0x1 + 3548 026f 3F .uleb128 0x3f + 3549 0270 0C .uleb128 0xc + 3550 0271 03 .uleb128 0x3 + 3551 0272 0E .uleb128 0xe + 3552 0273 27 .uleb128 0x27 + 3553 0274 0C .uleb128 0xc + 3554 0275 49 .uleb128 0x49 + 3555 0276 13 .uleb128 0x13 + 3556 0277 34 .uleb128 0x34 + 3557 0278 0C .uleb128 0xc + 3558 0279 3C .uleb128 0x3c + 3559 027a 0C .uleb128 0xc + 3560 027b 01 .uleb128 0x1 + 3561 027c 13 .uleb128 0x13 + 3562 027d 00 .byte 0 + 3563 027e 00 .byte 0 + 3564 027f 2F .uleb128 0x2f + 3565 0280 26 .uleb128 0x26 + 3566 0281 00 .byte 0 + 3567 0282 00 .byte 0 + 3568 0283 00 .byte 0 + 3569 0284 30 .uleb128 0x30 + 3570 0285 2E .uleb128 0x2e + 3571 0286 01 .byte 0x1 + 3572 0287 3F .uleb128 0x3f + 3573 0288 0C .uleb128 0xc + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 64 + + + 3574 0289 03 .uleb128 0x3 + 3575 028a 0E .uleb128 0xe + 3576 028b 3A .uleb128 0x3a + 3577 028c 0B .uleb128 0xb + 3578 028d 3B .uleb128 0x3b + 3579 028e 0B .uleb128 0xb + 3580 028f 27 .uleb128 0x27 + 3581 0290 0C .uleb128 0xc + 3582 0291 3C .uleb128 0x3c + 3583 0292 0C .uleb128 0xc + 3584 0293 00 .byte 0 + 3585 0294 00 .byte 0 + 3586 0295 00 .byte 0 + 3587 .section .debug_loc,"",%progbits + 3588 .Ldebug_loc0: + 3589 .LLST0: + 3590 0000 00000000 .4byte .LVL0 + 3591 0004 08000000 .4byte .LVL2 + 3592 0008 0100 .2byte 0x1 + 3593 000a 50 .byte 0x50 + 3594 000b 08000000 .4byte .LVL2 + 3595 000f 0A000000 .4byte .LFE7 + 3596 0013 0400 .2byte 0x4 + 3597 0015 F3 .byte 0xf3 + 3598 0016 01 .uleb128 0x1 + 3599 0017 50 .byte 0x50 + 3600 0018 9F .byte 0x9f + 3601 0019 00000000 .4byte 0 + 3602 001d 00000000 .4byte 0 + 3603 .LLST1: + 3604 0021 00000000 .4byte .LVL0 + 3605 0025 02000000 .4byte .LVL1 + 3606 0029 0100 .2byte 0x1 + 3607 002b 53 .byte 0x53 + 3608 002c 02000000 .4byte .LVL1 + 3609 0030 0A000000 .4byte .LFE7 + 3610 0034 0400 .2byte 0x4 + 3611 0036 F3 .byte 0xf3 + 3612 0037 01 .uleb128 0x1 + 3613 0038 53 .byte 0x53 + 3614 0039 9F .byte 0x9f + 3615 003a 00000000 .4byte 0 + 3616 003e 00000000 .4byte 0 + 3617 .LLST2: + 3618 0042 00000000 .4byte .LVL3 + 3619 0046 02000000 .4byte .LVL4 + 3620 004a 0100 .2byte 0x1 + 3621 004c 50 .byte 0x50 + 3622 004d 02000000 .4byte .LVL4 + 3623 0051 04000000 .4byte .LFE8 + 3624 0055 0400 .2byte 0x4 + 3625 0057 F3 .byte 0xf3 + 3626 0058 01 .uleb128 0x1 + 3627 0059 50 .byte 0x50 + 3628 005a 9F .byte 0x9f + 3629 005b 00000000 .4byte 0 + 3630 005f 00000000 .4byte 0 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 65 + + + 3631 .LLST3: + 3632 0063 00000000 .4byte .LVL5 + 3633 0067 02000000 .4byte .LVL6 + 3634 006b 0100 .2byte 0x1 + 3635 006d 50 .byte 0x50 + 3636 006e 02000000 .4byte .LVL6 + 3637 0072 04000000 .4byte .LFE9 + 3638 0076 0400 .2byte 0x4 + 3639 0078 F3 .byte 0xf3 + 3640 0079 01 .uleb128 0x1 + 3641 007a 50 .byte 0x50 + 3642 007b 9F .byte 0x9f + 3643 007c 00000000 .4byte 0 + 3644 0080 00000000 .4byte 0 + 3645 .LLST4: + 3646 0084 00000000 .4byte .LVL7 + 3647 0088 02000000 .4byte .LVL8 + 3648 008c 0100 .2byte 0x1 + 3649 008e 50 .byte 0x50 + 3650 008f 02000000 .4byte .LVL8 + 3651 0093 04000000 .4byte .LFE10 + 3652 0097 0400 .2byte 0x4 + 3653 0099 F3 .byte 0xf3 + 3654 009a 01 .uleb128 0x1 + 3655 009b 50 .byte 0x50 + 3656 009c 9F .byte 0x9f + 3657 009d 00000000 .4byte 0 + 3658 00a1 00000000 .4byte 0 + 3659 .LLST5: + 3660 00a5 00000000 .4byte .LFB11 + 3661 00a9 02000000 .4byte .LCFI0 + 3662 00ad 0200 .2byte 0x2 + 3663 00af 7D .byte 0x7d + 3664 00b0 00 .sleb128 0 + 3665 00b1 02000000 .4byte .LCFI0 + 3666 00b5 18000000 .4byte .LFE11 + 3667 00b9 0200 .2byte 0x2 + 3668 00bb 7D .byte 0x7d + 3669 00bc 08 .sleb128 8 + 3670 00bd 00000000 .4byte 0 + 3671 00c1 00000000 .4byte 0 + 3672 .LLST6: + 3673 00c5 00000000 .4byte .LVL9 + 3674 00c9 06000000 .4byte .LVL10 + 3675 00cd 0100 .2byte 0x1 + 3676 00cf 50 .byte 0x50 + 3677 00d0 06000000 .4byte .LVL10 + 3678 00d4 18000000 .4byte .LFE11 + 3679 00d8 0100 .2byte 0x1 + 3680 00da 54 .byte 0x54 + 3681 00db 00000000 .4byte 0 + 3682 00df 00000000 .4byte 0 + 3683 .LLST7: + 3684 00e3 00000000 .4byte .LVL9 + 3685 00e7 09000000 .4byte .LVL11-1 + 3686 00eb 0100 .2byte 0x1 + 3687 00ed 51 .byte 0x51 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 66 + + + 3688 00ee 09000000 .4byte .LVL11-1 + 3689 00f2 18000000 .4byte .LFE11 + 3690 00f6 0400 .2byte 0x4 + 3691 00f8 F3 .byte 0xf3 + 3692 00f9 01 .uleb128 0x1 + 3693 00fa 51 .byte 0x51 + 3694 00fb 9F .byte 0x9f + 3695 00fc 00000000 .4byte 0 + 3696 0100 00000000 .4byte 0 + 3697 .LLST8: + 3698 0104 0A000000 .4byte .LVL11 + 3699 0108 16000000 .4byte .LVL12 + 3700 010c 0100 .2byte 0x1 + 3701 010e 50 .byte 0x50 + 3702 010f 00000000 .4byte 0 + 3703 0113 00000000 .4byte 0 + 3704 .LLST9: + 3705 0117 00000000 .4byte .LFB12 + 3706 011b 02000000 .4byte .LCFI1 + 3707 011f 0200 .2byte 0x2 + 3708 0121 7D .byte 0x7d + 3709 0122 00 .sleb128 0 + 3710 0123 02000000 .4byte .LCFI1 + 3711 0127 18000000 .4byte .LFE12 + 3712 012b 0200 .2byte 0x2 + 3713 012d 7D .byte 0x7d + 3714 012e 08 .sleb128 8 + 3715 012f 00000000 .4byte 0 + 3716 0133 00000000 .4byte 0 + 3717 .LLST10: + 3718 0137 00000000 .4byte .LVL13 + 3719 013b 04000000 .4byte .LVL14 + 3720 013f 0100 .2byte 0x1 + 3721 0141 50 .byte 0x50 + 3722 0142 04000000 .4byte .LVL14 + 3723 0146 18000000 .4byte .LFE12 + 3724 014a 0400 .2byte 0x4 + 3725 014c F3 .byte 0xf3 + 3726 014d 01 .uleb128 0x1 + 3727 014e 50 .byte 0x50 + 3728 014f 9F .byte 0x9f + 3729 0150 00000000 .4byte 0 + 3730 0154 00000000 .4byte 0 + 3731 .LLST11: + 3732 0158 00000000 .4byte .LVL13 + 3733 015c 08000000 .4byte .LVL15 + 3734 0160 0100 .2byte 0x1 + 3735 0162 51 .byte 0x51 + 3736 0163 08000000 .4byte .LVL15 + 3737 0167 18000000 .4byte .LFE12 + 3738 016b 0400 .2byte 0x4 + 3739 016d F3 .byte 0xf3 + 3740 016e 01 .uleb128 0x1 + 3741 016f 51 .byte 0x51 + 3742 0170 9F .byte 0x9f + 3743 0171 00000000 .4byte 0 + 3744 0175 00000000 .4byte 0 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 67 + + + 3745 .LLST12: + 3746 0179 00000000 .4byte .LVL13 + 3747 017d 0A000000 .4byte .LVL16 + 3748 0181 0100 .2byte 0x1 + 3749 0183 52 .byte 0x52 + 3750 0184 0A000000 .4byte .LVL16 + 3751 0188 0D000000 .4byte .LVL17-1 + 3752 018c 0100 .2byte 0x1 + 3753 018e 50 .byte 0x50 + 3754 018f 0D000000 .4byte .LVL17-1 + 3755 0193 18000000 .4byte .LFE12 + 3756 0197 0100 .2byte 0x1 + 3757 0199 54 .byte 0x54 + 3758 019a 00000000 .4byte 0 + 3759 019e 00000000 .4byte 0 + 3760 .LLST13: + 3761 01a2 00000000 .4byte .LVL18 + 3762 01a6 02000000 .4byte .LVL19 + 3763 01aa 0100 .2byte 0x1 + 3764 01ac 50 .byte 0x50 + 3765 01ad 02000000 .4byte .LVL19 + 3766 01b1 04000000 .4byte .LFE13 + 3767 01b5 0400 .2byte 0x4 + 3768 01b7 F3 .byte 0xf3 + 3769 01b8 01 .uleb128 0x1 + 3770 01b9 50 .byte 0x50 + 3771 01ba 9F .byte 0x9f + 3772 01bb 00000000 .4byte 0 + 3773 01bf 00000000 .4byte 0 + 3774 .LLST14: + 3775 01c3 00000000 .4byte .LFB14 + 3776 01c7 02000000 .4byte .LCFI2 + 3777 01cb 0200 .2byte 0x2 + 3778 01cd 7D .byte 0x7d + 3779 01ce 00 .sleb128 0 + 3780 01cf 02000000 .4byte .LCFI2 + 3781 01d3 24000000 .4byte .LFE14 + 3782 01d7 0200 .2byte 0x2 + 3783 01d9 7D .byte 0x7d + 3784 01da 10 .sleb128 16 + 3785 01db 00000000 .4byte 0 + 3786 01df 00000000 .4byte 0 + 3787 .LLST15: + 3788 01e3 00000000 .4byte .LVL20 + 3789 01e7 04000000 .4byte .LVL21 + 3790 01eb 0100 .2byte 0x1 + 3791 01ed 50 .byte 0x50 + 3792 01ee 04000000 .4byte .LVL21 + 3793 01f2 24000000 .4byte .LFE14 + 3794 01f6 0400 .2byte 0x4 + 3795 01f8 F3 .byte 0xf3 + 3796 01f9 01 .uleb128 0x1 + 3797 01fa 50 .byte 0x50 + 3798 01fb 9F .byte 0x9f + 3799 01fc 00000000 .4byte 0 + 3800 0200 00000000 .4byte 0 + 3801 .LLST16: + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 68 + + + 3802 0204 00000000 .4byte .LVL20 + 3803 0208 08000000 .4byte .LVL22 + 3804 020c 0100 .2byte 0x1 + 3805 020e 51 .byte 0x51 + 3806 020f 08000000 .4byte .LVL22 + 3807 0213 24000000 .4byte .LFE14 + 3808 0217 0100 .2byte 0x1 + 3809 0219 55 .byte 0x55 + 3810 021a 00000000 .4byte 0 + 3811 021e 00000000 .4byte 0 + 3812 .LLST17: + 3813 0222 00000000 .4byte .LVL20 + 3814 0226 0D000000 .4byte .LVL23-1 + 3815 022a 0100 .2byte 0x1 + 3816 022c 52 .byte 0x52 + 3817 022d 0D000000 .4byte .LVL23-1 + 3818 0231 24000000 .4byte .LFE14 + 3819 0235 0100 .2byte 0x1 + 3820 0237 54 .byte 0x54 + 3821 0238 00000000 .4byte 0 + 3822 023c 00000000 .4byte 0 + 3823 .LLST18: + 3824 0240 0E000000 .4byte .LVL23 + 3825 0244 19000000 .4byte .LVL24-1 + 3826 0248 0100 .2byte 0x1 + 3827 024a 50 .byte 0x50 + 3828 024b 19000000 .4byte .LVL24-1 + 3829 024f 24000000 .4byte .LFE14 + 3830 0253 0100 .2byte 0x1 + 3831 0255 56 .byte 0x56 + 3832 0256 00000000 .4byte 0 + 3833 025a 00000000 .4byte 0 + 3834 .LLST19: + 3835 025e 00000000 .4byte .LVL26 + 3836 0262 06000000 .4byte .LVL28 + 3837 0266 0100 .2byte 0x1 + 3838 0268 50 .byte 0x50 + 3839 0269 06000000 .4byte .LVL28 + 3840 026d 0A000000 .4byte .LFE15 + 3841 0271 0400 .2byte 0x4 + 3842 0273 F3 .byte 0xf3 + 3843 0274 01 .uleb128 0x1 + 3844 0275 50 .byte 0x50 + 3845 0276 9F .byte 0x9f + 3846 0277 00000000 .4byte 0 + 3847 027b 00000000 .4byte 0 + 3848 .LLST20: + 3849 027f 00000000 .4byte .LVL26 + 3850 0283 04000000 .4byte .LVL27 + 3851 0287 0100 .2byte 0x1 + 3852 0289 51 .byte 0x51 + 3853 028a 04000000 .4byte .LVL27 + 3854 028e 0A000000 .4byte .LFE15 + 3855 0292 0400 .2byte 0x4 + 3856 0294 F3 .byte 0xf3 + 3857 0295 01 .uleb128 0x1 + 3858 0296 51 .byte 0x51 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 69 + + + 3859 0297 9F .byte 0x9f + 3860 0298 00000000 .4byte 0 + 3861 029c 00000000 .4byte 0 + 3862 .LLST21: + 3863 02a0 00000000 .4byte .LVL26 + 3864 02a4 09000000 .4byte .LVL29-1 + 3865 02a8 0100 .2byte 0x1 + 3866 02aa 52 .byte 0x52 + 3867 02ab 09000000 .4byte .LVL29-1 + 3868 02af 0A000000 .4byte .LFE15 + 3869 02b3 0400 .2byte 0x4 + 3870 02b5 F3 .byte 0xf3 + 3871 02b6 01 .uleb128 0x1 + 3872 02b7 52 .byte 0x52 + 3873 02b8 9F .byte 0x9f + 3874 02b9 00000000 .4byte 0 + 3875 02bd 00000000 .4byte 0 + 3876 .LLST22: + 3877 02c1 00000000 .4byte .LVL30 + 3878 02c5 02000000 .4byte .LVL31 + 3879 02c9 0100 .2byte 0x1 + 3880 02cb 50 .byte 0x50 + 3881 02cc 02000000 .4byte .LVL31 + 3882 02d0 06000000 .4byte .LFE16 + 3883 02d4 0400 .2byte 0x4 + 3884 02d6 F3 .byte 0xf3 + 3885 02d7 01 .uleb128 0x1 + 3886 02d8 50 .byte 0x50 + 3887 02d9 9F .byte 0x9f + 3888 02da 00000000 .4byte 0 + 3889 02de 00000000 .4byte 0 + 3890 .LLST23: + 3891 02e2 00000000 .4byte .LVL30 + 3892 02e6 05000000 .4byte .LVL32-1 + 3893 02ea 0100 .2byte 0x1 + 3894 02ec 51 .byte 0x51 + 3895 02ed 05000000 .4byte .LVL32-1 + 3896 02f1 06000000 .4byte .LFE16 + 3897 02f5 0400 .2byte 0x4 + 3898 02f7 F3 .byte 0xf3 + 3899 02f8 01 .uleb128 0x1 + 3900 02f9 51 .byte 0x51 + 3901 02fa 9F .byte 0x9f + 3902 02fb 00000000 .4byte 0 + 3903 02ff 00000000 .4byte 0 + 3904 .LLST24: + 3905 0303 00000000 .4byte .LVL33 + 3906 0307 02000000 .4byte .LVL34 + 3907 030b 0100 .2byte 0x1 + 3908 030d 50 .byte 0x50 + 3909 030e 02000000 .4byte .LVL34 + 3910 0312 06000000 .4byte .LFE17 + 3911 0316 0400 .2byte 0x4 + 3912 0318 F3 .byte 0xf3 + 3913 0319 01 .uleb128 0x1 + 3914 031a 50 .byte 0x50 + 3915 031b 9F .byte 0x9f + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 70 + + + 3916 031c 00000000 .4byte 0 + 3917 0320 00000000 .4byte 0 + 3918 .LLST25: + 3919 0324 00000000 .4byte .LVL33 + 3920 0328 05000000 .4byte .LVL35-1 + 3921 032c 0100 .2byte 0x1 + 3922 032e 51 .byte 0x51 + 3923 032f 05000000 .4byte .LVL35-1 + 3924 0333 06000000 .4byte .LFE17 + 3925 0337 0400 .2byte 0x4 + 3926 0339 F3 .byte 0xf3 + 3927 033a 01 .uleb128 0x1 + 3928 033b 51 .byte 0x51 + 3929 033c 9F .byte 0x9f + 3930 033d 00000000 .4byte 0 + 3931 0341 00000000 .4byte 0 + 3932 .section .debug_aranges,"",%progbits + 3933 0000 6C000000 .4byte 0x6c + 3934 0004 0200 .2byte 0x2 + 3935 0006 00000000 .4byte .Ldebug_info0 + 3936 000a 04 .byte 0x4 + 3937 000b 00 .byte 0 + 3938 000c 0000 .2byte 0 + 3939 000e 0000 .2byte 0 + 3940 0010 00000000 .4byte .LFB7 + 3941 0014 0A000000 .4byte .LFE7-.LFB7 + 3942 0018 00000000 .4byte .LFB8 + 3943 001c 04000000 .4byte .LFE8-.LFB8 + 3944 0020 00000000 .4byte .LFB9 + 3945 0024 04000000 .4byte .LFE9-.LFB9 + 3946 0028 00000000 .4byte .LFB10 + 3947 002c 04000000 .4byte .LFE10-.LFB10 + 3948 0030 00000000 .4byte .LFB11 + 3949 0034 18000000 .4byte .LFE11-.LFB11 + 3950 0038 00000000 .4byte .LFB12 + 3951 003c 18000000 .4byte .LFE12-.LFB12 + 3952 0040 00000000 .4byte .LFB13 + 3953 0044 04000000 .4byte .LFE13-.LFB13 + 3954 0048 00000000 .4byte .LFB14 + 3955 004c 24000000 .4byte .LFE14-.LFB14 + 3956 0050 00000000 .4byte .LFB15 + 3957 0054 0A000000 .4byte .LFE15-.LFB15 + 3958 0058 00000000 .4byte .LFB16 + 3959 005c 06000000 .4byte .LFE16-.LFB16 + 3960 0060 00000000 .4byte .LFB17 + 3961 0064 06000000 .4byte .LFE17-.LFB17 + 3962 0068 00000000 .4byte 0 + 3963 006c 00000000 .4byte 0 + 3964 .section .debug_ranges,"",%progbits + 3965 .Ldebug_ranges0: + 3966 0000 00000000 .4byte .LFB7 + 3967 0004 0A000000 .4byte .LFE7 + 3968 0008 00000000 .4byte .LFB8 + 3969 000c 04000000 .4byte .LFE8 + 3970 0010 00000000 .4byte .LFB9 + 3971 0014 04000000 .4byte .LFE9 + 3972 0018 00000000 .4byte .LFB10 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 71 + + + 3973 001c 04000000 .4byte .LFE10 + 3974 0020 00000000 .4byte .LFB11 + 3975 0024 18000000 .4byte .LFE11 + 3976 0028 00000000 .4byte .LFB12 + 3977 002c 18000000 .4byte .LFE12 + 3978 0030 00000000 .4byte .LFB13 + 3979 0034 04000000 .4byte .LFE13 + 3980 0038 00000000 .4byte .LFB14 + 3981 003c 24000000 .4byte .LFE14 + 3982 0040 00000000 .4byte .LFB15 + 3983 0044 0A000000 .4byte .LFE15 + 3984 0048 00000000 .4byte .LFB16 + 3985 004c 06000000 .4byte .LFE16 + 3986 0050 00000000 .4byte .LFB17 + 3987 0054 06000000 .4byte .LFE17 + 3988 0058 00000000 .4byte 0 + 3989 005c 00000000 .4byte 0 + 3990 .section .debug_line,"",%progbits + 3991 .Ldebug_line0: + 3992 0000 A2020000 .section .debug_str,"MS",%progbits,1 + 3992 0200C001 + 3992 00000201 + 3992 FB0E0D00 + 3992 01010101 + 3993 .LASF179: + 3994 0000 54687265 .ascii "ThreadsList\000" + 3994 6164734C + 3994 69737400 + 3995 .LASF171: + 3996 000c 705F7761 .ascii "p_waiting\000" + 3996 6974696E + 3996 6700 + 3997 .LASF170: + 3998 0016 705F7469 .ascii "p_time\000" + 3998 6D6500 + 3999 .LASF180: + 4000 001d 72656761 .ascii "regarm_t\000" + 4000 726D5F74 + 4000 00 + 4001 .LASF162: + 4002 0026 705F7072 .ascii "p_prio\000" + 4002 696F00 + 4003 .LASF40: + 4004 002d 5F6F6E5F .ascii "_on_exit_args\000" + 4004 65786974 + 4004 5F617267 + 4004 7300 + 4005 .LASF108: + 4006 003b 5F776374 .ascii "_wctomb_state\000" + 4006 6F6D625F + 4006 73746174 + 4006 6500 + 4007 .LASF158: + 4008 0049 73797374 .ascii "systime_t\000" + 4008 696D655F + 4008 7400 + 4009 .LASF105: + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 72 + + + 4010 0053 5F723438 .ascii "_r48\000" + 4010 00 + 4011 .LASF205: + 4012 0058 5F777269 .ascii "_write_r\000" + 4012 74655F72 + 4012 00 + 4013 .LASF186: + 4014 0061 6D5F6F77 .ascii "m_owner\000" + 4014 6E657200 + 4015 .LASF226: + 4016 0069 63684865 .ascii "chHeapFree\000" + 4016 61704672 + 4016 656500 + 4017 .LASF172: + 4018 0074 705F6D73 .ascii "p_msgqueue\000" + 4018 67717565 + 4018 756500 + 4019 .LASF110: + 4020 007f 5F736967 .ascii "_signal_buf\000" + 4020 6E616C5F + 4020 62756600 + 4021 .LASF213: + 4022 008b 6E657753 .ascii "newSize\000" + 4022 697A6500 + 4023 .LASF0: + 4024 0093 756E7369 .ascii "unsigned int\000" + 4024 676E6564 + 4024 20696E74 + 4024 00 + 4025 .LASF194: + 4026 00a0 6E657874 .ascii "next\000" + 4026 00 + 4027 .LASF223: + 4028 00a5 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 4028 73657273 + 4028 5C496D61 + 4028 6E6F6C5C + 4028 64657665 + 4029 00d2 6C696361 .ascii "lications\\smartcities\000" + 4029 74696F6E + 4029 735C736D + 4029 61727463 + 4029 69746965 + 4030 .LASF145: + 4031 00e8 73745F62 .ascii "st_blksize\000" + 4031 6C6B7369 + 4031 7A6500 + 4032 .LASF54: + 4033 00f3 5F6C6266 .ascii "_lbfsize\000" + 4033 73697A65 + 4033 00 + 4034 .LASF52: + 4035 00fc 5F666C61 .ascii "_flags\000" + 4035 677300 + 4036 .LASF192: + 4037 0103 685F6672 .ascii "h_free\000" + 4037 656500 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 73 + + + 4038 .LASF69: + 4039 010a 5F657272 .ascii "_errno\000" + 4039 6E6F00 + 4040 .LASF195: + 4041 0111 68656170 .ascii "heap\000" + 4041 00 + 4042 .LASF200: + 4043 0116 77746F62 .ascii "wtobjp\000" + 4043 6A7000 + 4044 .LASF8: + 4045 011d 5F4C4F43 .ascii "_LOCK_RECURSIVE_T\000" + 4045 4B5F5245 + 4045 43555253 + 4045 4956455F + 4045 5400 + 4046 .LASF56: + 4047 012f 5F726561 .ascii "_read\000" + 4047 6400 + 4048 .LASF225: + 4049 0135 5F667265 .ascii "_free_r\000" + 4049 655F7200 + 4050 .LASF201: + 4051 013d 65776D61 .ascii "ewmask\000" + 4051 736B00 + 4052 .LASF112: + 4053 0144 5F6D6272 .ascii "_mbrlen_state\000" + 4053 6C656E5F + 4053 73746174 + 4053 6500 + 4054 .LASF71: + 4055 0152 5F737464 .ascii "_stdout\000" + 4055 6F757400 + 4056 .LASF14: + 4057 015a 5F66706F .ascii "_fpos_t\000" + 4057 735F7400 + 4058 .LASF47: + 4059 0162 5F666E73 .ascii "_fns\000" + 4059 00 + 4060 .LASF55: + 4061 0167 5F636F6F .ascii "_cookie\000" + 4061 6B696500 + 4062 .LASF29: + 4063 016f 5F426967 .ascii "_Bigint\000" + 4063 696E7400 + 4064 .LASF37: + 4065 0177 5F5F746D .ascii "__tm_wday\000" + 4065 5F776461 + 4065 7900 + 4066 .LASF79: + 4067 0181 5F726573 .ascii "_result\000" + 4067 756C7400 + 4068 .LASF123: + 4069 0189 696E6F5F .ascii "ino_t\000" + 4069 7400 + 4070 .LASF150: + 4071 018f 75696E74 .ascii "uint32_t\000" + 4071 33325F74 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 74 + + + 4071 00 + 4072 .LASF33: + 4073 0198 5F5F746D .ascii "__tm_hour\000" + 4073 5F686F75 + 4073 7200 + 4074 .LASF157: + 4075 01a2 6576656E .ascii "eventmask_t\000" + 4075 746D6173 + 4075 6B5F7400 + 4076 .LASF221: + 4077 01ae 474E5520 .ascii "GNU C 4.7.2\000" + 4077 4320342E + 4077 372E3200 + 4078 .LASF19: + 4079 01ba 5F5F636F .ascii "__count\000" + 4079 756E7400 + 4080 .LASF32: + 4081 01c2 5F5F746D .ascii "__tm_min\000" + 4081 5F6D696E + 4081 00 + 4082 .LASF155: + 4083 01cb 74707269 .ascii "tprio_t\000" + 4083 6F5F7400 + 4084 .LASF118: + 4085 01d3 5F6E6578 .ascii "_nextf\000" + 4085 746600 + 4086 .LASF210: + 4087 01da 5F697361 .ascii "_isatty_r\000" + 4087 7474795F + 4087 7200 + 4088 .LASF95: + 4089 01e4 5F72616E .ascii "_rand48\000" + 4089 64343800 + 4090 .LASF80: + 4091 01ec 5F726573 .ascii "_result_k\000" + 4091 756C745F + 4091 6B00 + 4092 .LASF188: + 4093 01f6 6D656D67 .ascii "memgetfunc_t\000" + 4093 65746675 + 4093 6E635F74 + 4093 00 + 4094 .LASF6: + 4095 0203 6C6F6E67 .ascii "long long unsigned int\000" + 4095 206C6F6E + 4095 6720756E + 4095 7369676E + 4095 65642069 + 4096 .LASF146: + 4097 021a 73745F62 .ascii "st_blocks\000" + 4097 6C6F636B + 4097 7300 + 4098 .LASF101: + 4099 0224 5F617363 .ascii "_asctime_buf\000" + 4099 74696D65 + 4099 5F627566 + 4099 00 + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 75 + + + 4100 .LASF51: + 4101 0231 5F5F7346 .ascii "__sFILE\000" + 4101 494C4500 + 4102 .LASF28: + 4103 0239 5F776473 .ascii "_wds\000" + 4103 00 + 4104 .LASF207: + 4105 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"stkalign_t\000" + 4411 6C69676E + 4411 5F7400 + 4412 .LASF189: + 4413 079e 4D656D6F .ascii "MemoryHeap\000" + 4413 72794865 + 4413 617000 + 4414 .LASF220: + 4415 07a9 6D656D63 .ascii "memcpy\000" + 4415 707900 + 4416 .LASF43: + 4417 07b0 5F666E74 .ascii "_fntypes\000" + 4417 79706573 + 4417 00 + 4418 .LASF50: + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 85 + + + 4419 07b9 5F73697A .ascii "_size\000" + 4419 6500 + 4420 .LASF9: + 4421 07bf 5F6F6666 .ascii "_off_t\000" + 4421 5F7400 + 4422 .LASF61: + 4423 07c6 5F6E6275 .ascii "_nbuf\000" + 4423 6600 + 4424 .LASF99: + 4425 07cc 5F756E75 .ascii "_unused_rand\000" + 4425 7365645F + 4425 72616E64 + 4425 00 + 4426 .LASF137: + 4427 07d9 73745F72 .ascii "st_rdev\000" + 4427 64657600 + 4428 .LASF67: + 4429 07e1 5F666C61 .ascii "_flags2\000" + 4429 67733200 + 4430 .LASF196: + 4431 07e9 616C6967 .ascii "align\000" + 4431 6E00 + 4432 .LASF44: + 4433 07ef 5F69735F .ascii "_is_cxa\000" + 4433 63786100 + 4434 .LASF96: + 4435 07f7 5F736565 .ascii "_seed\000" + 4435 6400 + 4436 .LASF104: + 4437 07fd 5F72616E .ascii "_rand_next\000" + 4437 645F6E65 + 4437 787400 + 4438 .LASF199: + 4439 0808 65786974 .ascii "exitcode\000" + 4439 636F6465 + 4439 00 + 4440 .LASF58: + 4441 0811 5F736565 .ascii "_seek\000" + 4441 6B00 + 4442 .LASF72: + 4443 0817 5F737464 .ascii "_stderr\000" + 4443 65727200 + 4444 .LASF119: + 4445 081f 5F6E6D61 .ascii "_nmalloc\000" + 4445 6C6C6F63 + 4445 00 + 4446 .LASF60: + 4447 0828 5F756275 .ascii "_ubuf\000" + 4447 6600 + 4448 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\ccBOkGlc.s page 86 + + +DEFINED SYMBOLS + *ABS*:00000000 syscalls.c +C:\cygwin\tmp\ccBOkGlc.s:19 .text._read_r:00000000 $t +C:\cygwin\tmp\ccBOkGlc.s:25 .text._read_r:00000000 _read_r +C:\cygwin\tmp\ccBOkGlc.s:46 .text._lseek_r:00000000 $t +C:\cygwin\tmp\ccBOkGlc.s:52 .text._lseek_r:00000000 _lseek_r +C:\cygwin\tmp\ccBOkGlc.s:68 .text._write_r:00000000 $t +C:\cygwin\tmp\ccBOkGlc.s:74 .text._write_r:00000000 _write_r +C:\cygwin\tmp\ccBOkGlc.s:90 .text._close_r:00000000 $t +C:\cygwin\tmp\ccBOkGlc.s:96 .text._close_r:00000000 _close_r +C:\cygwin\tmp\ccBOkGlc.s:112 .text._sbrk_r:00000000 $t +C:\cygwin\tmp\ccBOkGlc.s:118 .text._sbrk_r:00000000 _sbrk_r +C:\cygwin\tmp\ccBOkGlc.s:154 .text._fstat_r:00000000 $t +C:\cygwin\tmp\ccBOkGlc.s:160 .text._fstat_r:00000000 _fstat_r +C:\cygwin\tmp\ccBOkGlc.s:194 .text._isatty_r:00000000 $t +C:\cygwin\tmp\ccBOkGlc.s:200 .text._isatty_r:00000000 _isatty_r +C:\cygwin\tmp\ccBOkGlc.s:216 .text._realloc_r:00000000 $t +C:\cygwin\tmp\ccBOkGlc.s:222 .text._realloc_r:00000000 _realloc_r +C:\cygwin\tmp\ccBOkGlc.s:269 .text._calloc_r:00000000 $t +C:\cygwin\tmp\ccBOkGlc.s:275 .text._calloc_r:00000000 _calloc_r +C:\cygwin\tmp\ccBOkGlc.s:296 .text._malloc_r:00000000 $t +C:\cygwin\tmp\ccBOkGlc.s:302 .text._malloc_r:00000000 _malloc_r +C:\cygwin\tmp\ccBOkGlc.s:321 .text._free_r:00000000 $t +C:\cygwin\tmp\ccBOkGlc.s:327 .text._free_r:00000000 _free_r + .debug_frame:00000010 $d + +UNDEFINED SYMBOLS +chCoreAlloc +memset +chHeapAlloc +memcpy +chHeapFree diff --git a/Project/applications/smartcities/build/lst/vectors.lst b/Project/applications/smartcities/build/lst/vectors.lst new file mode 100644 index 0000000..44cb2c1 --- /dev/null +++ b/Project/applications/smartcities/build/lst/vectors.lst @@ -0,0 +1,1192 @@ +ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 34, 1 + 12 .eabi_attribute 18, 4 + 13 .thumb + 14 .file "vectors.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .section .text._unhandled_exception,"ax",%progbits + 19 .align 2 + 20 .p2align 4,,15 + 21 .global _unhandled_exception + 22 .thumb + 23 .thumb_func + 24 .type _unhandled_exception, %function + 25 _unhandled_exception: + 26 .LFB7: + 27 .file 1 "../..//os/ports/GCC/ARMCMx/STM32F1xx/vectors.c" + 28 .loc 1 242 0 + 29 .cfi_startproc + 30 @ Volatile: function does not return. + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 0000 08B5 push {r3, lr} + 34 .LCFI0: + 35 .cfi_def_cfa_offset 8 + 36 .cfi_offset 3, -8 + 37 .cfi_offset 14, -4 + 38 .loc 1 244 0 + 39 0002 0248 ldr r0, .L4 + 40 0004 FFF7FEFF bl print + 41 .LVL0: + 42 .L2: + 43 0008 FEE7 b .L2 + 44 .L5: + 45 000a 00BF .align 2 + 46 .L4: + 47 000c 00000000 .word .LC0 + 48 .cfi_endproc + 49 .LFE7: + 50 .size _unhandled_exception, .-_unhandled_exception + 51 .weak HardFaultVector + 52 .thumb_set HardFaultVector,_unhandled_exception + 53 .weak MemManageVector + 54 .thumb_set MemManageVector,_unhandled_exception + 55 .weak BusFaultVector + 56 .thumb_set BusFaultVector,_unhandled_exception + 57 .weak UsageFaultVector + ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 2 + + + 58 .thumb_set UsageFaultVector,_unhandled_exception + 59 .weak Vector1C + 60 .thumb_set Vector1C,_unhandled_exception + 61 .weak Vector20 + 62 .thumb_set Vector20,_unhandled_exception + 63 .weak Vector24 + 64 .thumb_set Vector24,_unhandled_exception + 65 .weak Vector28 + 66 .thumb_set Vector28,_unhandled_exception + 67 .weak SVCallVector + 68 .thumb_set SVCallVector,_unhandled_exception + 69 .weak DebugMonitorVector + 70 .thumb_set DebugMonitorVector,_unhandled_exception + 71 .weak Vector34 + 72 .thumb_set Vector34,_unhandled_exception + 73 .weak PendSVVector + 74 .thumb_set PendSVVector,_unhandled_exception + 75 .weak SysTickVector + 76 .thumb_set SysTickVector,_unhandled_exception + 77 .weak Vector40 + 78 .thumb_set Vector40,_unhandled_exception + 79 .weak Vector44 + 80 .thumb_set Vector44,_unhandled_exception + 81 .weak Vector48 + 82 .thumb_set Vector48,_unhandled_exception + 83 .weak Vector4C + 84 .thumb_set Vector4C,_unhandled_exception + 85 .weak Vector50 + 86 .thumb_set Vector50,_unhandled_exception + 87 .weak Vector54 + 88 .thumb_set Vector54,_unhandled_exception + 89 .weak Vector58 + 90 .thumb_set Vector58,_unhandled_exception + 91 .weak Vector5C + 92 .thumb_set Vector5C,_unhandled_exception + 93 .weak Vector60 + 94 .thumb_set Vector60,_unhandled_exception + 95 .weak Vector64 + 96 .thumb_set Vector64,_unhandled_exception + 97 .weak Vector68 + 98 .thumb_set Vector68,_unhandled_exception + 99 .weak Vector6C + 100 .thumb_set Vector6C,_unhandled_exception + 101 .weak Vector70 + 102 .thumb_set Vector70,_unhandled_exception + 103 .weak Vector74 + 104 .thumb_set Vector74,_unhandled_exception + 105 .weak Vector78 + 106 .thumb_set Vector78,_unhandled_exception + 107 .weak Vector7C + 108 .thumb_set Vector7C,_unhandled_exception + 109 .weak Vector80 + 110 .thumb_set Vector80,_unhandled_exception + 111 .weak Vector84 + 112 .thumb_set Vector84,_unhandled_exception + 113 .weak Vector88 + 114 .thumb_set Vector88,_unhandled_exception + ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 3 + + + 115 .weak Vector8C + 116 .thumb_set Vector8C,_unhandled_exception + 117 .weak Vector90 + 118 .thumb_set Vector90,_unhandled_exception + 119 .weak Vector94 + 120 .thumb_set Vector94,_unhandled_exception + 121 .weak Vector98 + 122 .thumb_set Vector98,_unhandled_exception + 123 .weak Vector9C + 124 .thumb_set Vector9C,_unhandled_exception + 125 .weak VectorA0 + 126 .thumb_set VectorA0,_unhandled_exception + 127 .weak VectorA4 + 128 .thumb_set VectorA4,_unhandled_exception + 129 .weak VectorA8 + 130 .thumb_set VectorA8,_unhandled_exception + 131 .weak VectorAC + 132 .thumb_set VectorAC,_unhandled_exception + 133 .weak VectorB0 + 134 .thumb_set VectorB0,_unhandled_exception + 135 .weak VectorB4 + 136 .thumb_set VectorB4,_unhandled_exception + 137 .weak VectorB8 + 138 .thumb_set VectorB8,_unhandled_exception + 139 .weak VectorBC + 140 .thumb_set VectorBC,_unhandled_exception + 141 .weak VectorC0 + 142 .thumb_set VectorC0,_unhandled_exception + 143 .weak VectorC4 + 144 .thumb_set VectorC4,_unhandled_exception + 145 .weak VectorC8 + 146 .thumb_set VectorC8,_unhandled_exception + 147 .weak VectorCC + 148 .thumb_set VectorCC,_unhandled_exception + 149 .weak VectorD0 + 150 .thumb_set VectorD0,_unhandled_exception + 151 .weak VectorD4 + 152 .thumb_set VectorD4,_unhandled_exception + 153 .weak VectorD8 + 154 .thumb_set VectorD8,_unhandled_exception + 155 .weak VectorDC + 156 .thumb_set VectorDC,_unhandled_exception + 157 .weak VectorE0 + 158 .thumb_set VectorE0,_unhandled_exception + 159 .weak VectorE4 + 160 .thumb_set VectorE4,_unhandled_exception + 161 .weak VectorE8 + 162 .thumb_set VectorE8,_unhandled_exception + 163 .weak VectorEC + 164 .thumb_set VectorEC,_unhandled_exception + 165 .weak VectorF0 + 166 .thumb_set VectorF0,_unhandled_exception + 167 .weak VectorF4 + 168 .thumb_set VectorF4,_unhandled_exception + 169 .weak VectorF8 + 170 .thumb_set VectorF8,_unhandled_exception + 171 .weak VectorFC + ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 4 + + + 172 .thumb_set VectorFC,_unhandled_exception + 173 .weak Vector100 + 174 .thumb_set Vector100,_unhandled_exception + 175 .weak Vector104 + 176 .thumb_set Vector104,_unhandled_exception + 177 .weak Vector108 + 178 .thumb_set Vector108,_unhandled_exception + 179 .weak Vector10C + 180 .thumb_set Vector10C,_unhandled_exception + 181 .weak Vector110 + 182 .thumb_set Vector110,_unhandled_exception + 183 .weak Vector114 + 184 .thumb_set Vector114,_unhandled_exception + 185 .weak Vector118 + 186 .thumb_set Vector118,_unhandled_exception + 187 .weak Vector11C + 188 .thumb_set Vector11C,_unhandled_exception + 189 .weak Vector120 + 190 .thumb_set Vector120,_unhandled_exception + 191 .weak Vector124 + 192 .thumb_set Vector124,_unhandled_exception + 193 .weak Vector128 + 194 .thumb_set Vector128,_unhandled_exception + 195 .weak Vector12C + 196 .thumb_set Vector12C,_unhandled_exception + 197 .weak NMIVector + 198 .thumb_set NMIVector,_unhandled_exception + 199 .global _vectors + 200 .section .rodata.str1.4,"aMS",%progbits,1 + 201 .align 2 + 202 .LC0: + 203 0000 4552524F .ascii "ERROR:_unhandled_exception\012\000" + 203 523A5F75 + 203 6E68616E + 203 646C6564 + 203 5F657863 + 204 .section vectors,"aw",%progbits + 205 .align 2 + 206 .type _vectors, %object + 207 .size _vectors, 304 + 208 _vectors: + 209 0000 00000000 .word __main_stack_end__ + 210 0004 00000000 .word ResetHandler + 211 0008 00000000 .word NMIVector + 212 000c 00000000 .word HardFaultVector + 213 0010 00000000 .word MemManageVector + 214 0014 00000000 .word BusFaultVector + 215 0018 00000000 .word UsageFaultVector + 216 001c 00000000 .word Vector1C + 217 0020 00000000 .word Vector20 + 218 0024 00000000 .word Vector24 + 219 0028 00000000 .word Vector28 + 220 002c 00000000 .word SVCallVector + 221 0030 00000000 .word DebugMonitorVector + 222 0034 00000000 .word Vector34 + 223 0038 00000000 .word PendSVVector + 224 003c 00000000 .word SysTickVector + ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 5 + + + 225 0040 00000000 .word Vector40 + 226 0044 00000000 .word Vector44 + 227 0048 00000000 .word Vector48 + 228 004c 00000000 .word Vector4C + 229 0050 00000000 .word Vector50 + 230 0054 00000000 .word Vector54 + 231 0058 00000000 .word Vector58 + 232 005c 00000000 .word Vector5C + 233 0060 00000000 .word Vector60 + 234 0064 00000000 .word Vector64 + 235 0068 00000000 .word Vector68 + 236 006c 00000000 .word Vector6C + 237 0070 00000000 .word Vector70 + 238 0074 00000000 .word Vector74 + 239 0078 00000000 .word Vector78 + 240 007c 00000000 .word Vector7C + 241 0080 00000000 .word Vector80 + 242 0084 00000000 .word Vector84 + 243 0088 00000000 .word Vector88 + 244 008c 00000000 .word Vector8C + 245 0090 00000000 .word Vector90 + 246 0094 00000000 .word Vector94 + 247 0098 00000000 .word Vector98 + 248 009c 00000000 .word Vector9C + 249 00a0 00000000 .word VectorA0 + 250 00a4 00000000 .word VectorA4 + 251 00a8 00000000 .word VectorA8 + 252 00ac 00000000 .word VectorAC + 253 00b0 00000000 .word VectorB0 + 254 00b4 00000000 .word VectorB4 + 255 00b8 00000000 .word VectorB8 + 256 00bc 00000000 .word VectorBC + 257 00c0 00000000 .word VectorC0 + 258 00c4 00000000 .word VectorC4 + 259 00c8 00000000 .word VectorC8 + 260 00cc 00000000 .word VectorCC + 261 00d0 00000000 .word VectorD0 + 262 00d4 00000000 .word VectorD4 + 263 00d8 00000000 .word VectorD8 + 264 00dc 00000000 .word VectorDC + 265 00e0 00000000 .word VectorE0 + 266 00e4 00000000 .word VectorE4 + 267 00e8 00000000 .word VectorE8 + 268 00ec 00000000 .word VectorEC + 269 00f0 00000000 .word VectorF0 + 270 00f4 00000000 .word VectorF4 + 271 00f8 00000000 .word VectorF8 + 272 00fc 00000000 .word VectorFC + 273 0100 00000000 .word Vector100 + 274 0104 00000000 .word Vector104 + 275 0108 00000000 .word Vector108 + 276 010c 00000000 .word Vector10C + 277 0110 00000000 .word Vector110 + 278 0114 00000000 .word Vector114 + 279 0118 00000000 .word Vector118 + 280 011c 00000000 .word Vector11C + 281 0120 00000000 .word Vector120 + ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 6 + + + 282 0124 00000000 .word Vector124 + 283 0128 00000000 .word Vector128 + 284 012c 00000000 .word Vector12C + 285 .text + 286 .Letext0: + 287 .file 2 "c:/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 288 .section .debug_info,"",%progbits + 289 .Ldebug_info0: + 290 0000 1A020000 .4byte 0x21a + 291 0004 0200 .2byte 0x2 + 292 0006 00000000 .4byte .Ldebug_abbrev0 + 293 000a 04 .byte 0x4 + 294 000b 01 .uleb128 0x1 + 295 000c 93000000 .4byte .LASF33 + 296 0010 01 .byte 0x1 + 297 0011 DB000000 .4byte .LASF34 + 298 0015 09000000 .4byte .LASF35 + 299 0019 00000000 .4byte .Ldebug_ranges0+0 + 300 001d 00000000 .4byte 0 + 301 0021 00000000 .4byte 0 + 302 0025 00000000 .4byte .Ldebug_line0 + 303 0029 02 .uleb128 0x2 + 304 002a 04 .byte 0x4 + 305 002b 05 .byte 0x5 + 306 002c 696E7400 .ascii "int\000" + 307 0030 03 .uleb128 0x3 + 308 0031 04 .byte 0x4 + 309 0032 07 .byte 0x7 + 310 0033 0A010000 .4byte .LASF0 + 311 0037 03 .uleb128 0x3 + 312 0038 01 .byte 0x1 + 313 0039 06 .byte 0x6 + 314 003a 06020000 .4byte .LASF1 + 315 003e 03 .uleb128 0x3 + 316 003f 01 .byte 0x1 + 317 0040 08 .byte 0x8 + 318 0041 9F000000 .4byte .LASF2 + 319 0045 03 .uleb128 0x3 + 320 0046 02 .byte 0x2 + 321 0047 05 .byte 0x5 + 322 0048 DD010000 .4byte .LASF3 + 323 004c 03 .uleb128 0x3 + 324 004d 02 .byte 0x2 + 325 004e 07 .byte 0x7 + 326 004f BF000000 .4byte .LASF4 + 327 0053 03 .uleb128 0x3 + 328 0054 04 .byte 0x4 + 329 0055 05 .byte 0x5 + 330 0056 FD010000 .4byte .LASF5 + 331 005a 04 .uleb128 0x4 + 332 005b F4010000 .4byte .LASF11 + 333 005f 02 .byte 0x2 + 334 0060 50 .byte 0x50 + 335 0061 65000000 .4byte 0x65 + 336 0065 03 .uleb128 0x3 + 337 0066 04 .byte 0x4 + 338 0067 07 .byte 0x7 + ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 7 + + + 339 0068 AD000000 .4byte .LASF6 + 340 006c 03 .uleb128 0x3 + 341 006d 08 .byte 0x8 + 342 006e 05 .byte 0x5 + 343 006f 96010000 .4byte .LASF7 + 344 0073 03 .uleb128 0x3 + 345 0074 08 .byte 0x8 + 346 0075 07 .byte 0x7 + 347 0076 22010000 .4byte .LASF8 + 348 007a 03 .uleb128 0x3 + 349 007b 04 .byte 0x4 + 350 007c 07 .byte 0x7 + 351 007d 6E010000 .4byte .LASF9 + 352 0081 05 .uleb128 0x5 + 353 0082 04 .byte 0x4 + 354 0083 87000000 .4byte 0x87 + 355 0087 06 .uleb128 0x6 + 356 0088 8C000000 .4byte 0x8c + 357 008c 03 .uleb128 0x3 + 358 008d 01 .byte 0x1 + 359 008e 08 .byte 0x8 + 360 008f A4010000 .4byte .LASF10 + 361 0093 04 .uleb128 0x4 + 362 0094 4C000000 .4byte .LASF12 + 363 0098 01 .byte 0x1 + 364 0099 48 .byte 0x48 + 365 009a 9E000000 .4byte 0x9e + 366 009e 05 .uleb128 0x5 + 367 009f 04 .byte 0x4 + 368 00a0 A4000000 .4byte 0xa4 + 369 00a4 07 .uleb128 0x7 + 370 00a5 01 .byte 0x1 + 371 00a6 08 .uleb128 0x8 + 372 00a7 3001 .2byte 0x130 + 373 00a9 01 .byte 0x1 + 374 00aa 4D .byte 0x4d + 375 00ab 9E010000 .4byte 0x19e + 376 00af 09 .uleb128 0x9 + 377 00b0 6B000000 .4byte .LASF13 + 378 00b4 01 .byte 0x1 + 379 00b5 4E .byte 0x4e + 380 00b6 9E010000 .4byte 0x19e + 381 00ba 02 .byte 0x2 + 382 00bb 23 .byte 0x23 + 383 00bc 00 .uleb128 0 + 384 00bd 09 .uleb128 0x9 + 385 00be E7010000 .4byte .LASF14 + 386 00c2 01 .byte 0x1 + 387 00c3 4F .byte 0x4f + 388 00c4 93000000 .4byte 0x93 + 389 00c8 02 .byte 0x2 + 390 00c9 23 .byte 0x23 + 391 00ca 04 .uleb128 0x4 + 392 00cb 09 .uleb128 0x9 + 393 00cc 17010000 .4byte .LASF15 + 394 00d0 01 .byte 0x1 + 395 00d1 50 .byte 0x50 + ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 8 + + + 396 00d2 93000000 .4byte 0x93 + 397 00d6 02 .byte 0x2 + 398 00d7 23 .byte 0x23 + 399 00d8 08 .uleb128 0x8 + 400 00d9 09 .uleb128 0x9 + 401 00da 85010000 .4byte .LASF16 + 402 00de 01 .byte 0x1 + 403 00df 51 .byte 0x51 + 404 00e0 93000000 .4byte 0x93 + 405 00e4 02 .byte 0x2 + 406 00e5 23 .byte 0x23 + 407 00e6 0C .uleb128 0xc + 408 00e7 09 .uleb128 0x9 + 409 00e8 A9010000 .4byte .LASF17 + 410 00ec 01 .byte 0x1 + 411 00ed 52 .byte 0x52 + 412 00ee 93000000 .4byte 0x93 + 413 00f2 02 .byte 0x2 + 414 00f3 23 .byte 0x23 + 415 00f4 10 .uleb128 0x10 + 416 00f5 09 .uleb128 0x9 + 417 00f6 39010000 .4byte .LASF18 + 418 00fa 01 .byte 0x1 + 419 00fb 53 .byte 0x53 + 420 00fc 93000000 .4byte 0x93 + 421 0100 02 .byte 0x2 + 422 0101 23 .byte 0x23 + 423 0102 14 .uleb128 0x14 + 424 0103 09 .uleb128 0x9 + 425 0104 52010000 .4byte .LASF19 + 426 0108 01 .byte 0x1 + 427 0109 54 .byte 0x54 + 428 010a 93000000 .4byte 0x93 + 429 010e 02 .byte 0x2 + 430 010f 23 .byte 0x23 + 431 0110 18 .uleb128 0x18 + 432 0111 09 .uleb128 0x9 + 433 0112 D2000000 .4byte .LASF20 + 434 0116 01 .byte 0x1 + 435 0117 55 .byte 0x55 + 436 0118 93000000 .4byte 0x93 + 437 011c 02 .byte 0x2 + 438 011d 23 .byte 0x23 + 439 011e 1C .uleb128 0x1c + 440 011f 09 .uleb128 0x9 + 441 0120 26020000 .4byte .LASF21 + 442 0124 01 .byte 0x1 + 443 0125 56 .byte 0x56 + 444 0126 93000000 .4byte 0x93 + 445 012a 02 .byte 0x2 + 446 012b 23 .byte 0x23 + 447 012c 20 .uleb128 0x20 + 448 012d 09 .uleb128 0x9 + 449 012e 00000000 .4byte .LASF22 + 450 0132 01 .byte 0x1 + 451 0133 57 .byte 0x57 + 452 0134 93000000 .4byte 0x93 + ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 9 + + + 453 0138 02 .byte 0x2 + 454 0139 23 .byte 0x23 + 455 013a 24 .uleb128 0x24 + 456 013b 09 .uleb128 0x9 + 457 013c 49010000 .4byte .LASF23 + 458 0140 01 .byte 0x1 + 459 0141 58 .byte 0x58 + 460 0142 93000000 .4byte 0x93 + 461 0146 02 .byte 0x2 + 462 0147 23 .byte 0x23 + 463 0148 28 .uleb128 0x28 + 464 0149 09 .uleb128 0x9 + 465 014a 85000000 .4byte .LASF24 + 466 014e 01 .byte 0x1 + 467 014f 59 .byte 0x59 + 468 0150 93000000 .4byte 0x93 + 469 0154 02 .byte 0x2 + 470 0155 23 .byte 0x23 + 471 0156 2C .uleb128 0x2c + 472 0157 09 .uleb128 0x9 + 473 0158 12020000 .4byte .LASF25 + 474 015c 01 .byte 0x1 + 475 015d 5A .byte 0x5a + 476 015e 93000000 .4byte 0x93 + 477 0162 02 .byte 0x2 + 478 0163 23 .byte 0x23 + 479 0164 30 .uleb128 0x30 + 480 0165 09 .uleb128 0x9 + 481 0166 59000000 .4byte .LASF26 + 482 016a 01 .byte 0x1 + 483 016b 5B .byte 0x5b + 484 016c 93000000 .4byte 0x93 + 485 0170 02 .byte 0x2 + 486 0171 23 .byte 0x23 + 487 0172 34 .uleb128 0x34 + 488 0173 09 .uleb128 0x9 + 489 0174 77010000 .4byte .LASF27 + 490 0178 01 .byte 0x1 + 491 0179 5C .byte 0x5c + 492 017a 93000000 .4byte 0x93 + 493 017e 02 .byte 0x2 + 494 017f 23 .byte 0x23 + 495 0180 38 .uleb128 0x38 + 496 0181 09 .uleb128 0x9 + 497 0182 76000000 .4byte .LASF28 + 498 0186 01 .byte 0x1 + 499 0187 5D .byte 0x5d + 500 0188 93000000 .4byte 0x93 + 501 018c 02 .byte 0x2 + 502 018d 23 .byte 0x23 + 503 018e 3C .uleb128 0x3c + 504 018f 09 .uleb128 0x9 + 505 0190 D5010000 .4byte .LASF29 + 506 0194 01 .byte 0x1 + 507 0195 5E .byte 0x5e + 508 0196 A4010000 .4byte 0x1a4 + 509 019a 02 .byte 0x2 + ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 10 + + + 510 019b 23 .byte 0x23 + 511 019c 40 .uleb128 0x40 + 512 019d 00 .byte 0 + 513 019e 05 .uleb128 0x5 + 514 019f 04 .byte 0x4 + 515 01a0 5A000000 .4byte 0x5a + 516 01a4 0A .uleb128 0xa + 517 01a5 93000000 .4byte 0x93 + 518 01a9 B4010000 .4byte 0x1b4 + 519 01ad 0B .uleb128 0xb + 520 01ae 7A000000 .4byte 0x7a + 521 01b2 3B .byte 0x3b + 522 01b3 00 .byte 0 + 523 01b4 04 .uleb128 0x4 + 524 01b5 64010000 .4byte .LASF30 + 525 01b9 01 .byte 0x1 + 526 01ba 5F .byte 0x5f + 527 01bb A6000000 .4byte 0xa6 + 528 01bf 0C .uleb128 0xc + 529 01c0 01 .byte 0x1 + 530 01c1 C0010000 .4byte .LASF36 + 531 01c5 01 .byte 0x1 + 532 01c6 F2 .byte 0xf2 + 533 01c7 01 .byte 0x1 + 534 01c8 00000000 .4byte .LFB7 + 535 01cc 10000000 .4byte .LFE7 + 536 01d0 00000000 .4byte .LLST0 + 537 01d4 01 .byte 0x1 + 538 01d5 ED010000 .4byte 0x1ed + 539 01d9 0D .uleb128 0xd + 540 01da 08000000 .4byte .LVL0 + 541 01de 0C020000 .4byte 0x20c + 542 01e2 0E .uleb128 0xe + 543 01e3 01 .byte 0x1 + 544 01e4 50 .byte 0x50 + 545 01e5 05 .byte 0x5 + 546 01e6 03 .byte 0x3 + 547 01e7 00000000 .4byte .LC0 + 548 01eb 00 .byte 0 + 549 01ec 00 .byte 0 + 550 01ed 0F .uleb128 0xf + 551 01ee 2F020000 .4byte .LASF31 + 552 01f2 01 .byte 0x1 + 553 01f3 62 .byte 0x62 + 554 01f4 5A000000 .4byte 0x5a + 555 01f8 01 .byte 0x1 + 556 01f9 01 .byte 0x1 + 557 01fa 10 .uleb128 0x10 + 558 01fb 62000000 .4byte .LASF32 + 559 01ff 01 .byte 0x1 + 560 0200 C5 .byte 0xc5 + 561 0201 B4010000 .4byte 0x1b4 + 562 0205 01 .byte 0x1 + 563 0206 05 .byte 0x5 + 564 0207 03 .byte 0x3 + 565 0208 00000000 .4byte _vectors + 566 020c 11 .uleb128 0x11 + ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 11 + + + 567 020d 01 .byte 0x1 + 568 020e BA010000 .4byte .LASF37 + 569 0212 01 .byte 0x1 + 570 0213 F1 .byte 0xf1 + 571 0214 01 .byte 0x1 + 572 0215 01 .byte 0x1 + 573 0216 12 .uleb128 0x12 + 574 0217 81000000 .4byte 0x81 + 575 021b 13 .uleb128 0x13 + 576 021c 00 .byte 0 + 577 021d 00 .byte 0 + 578 .section .debug_abbrev,"",%progbits + 579 .Ldebug_abbrev0: + 580 0000 01 .uleb128 0x1 + 581 0001 11 .uleb128 0x11 + 582 0002 01 .byte 0x1 + 583 0003 25 .uleb128 0x25 + 584 0004 0E .uleb128 0xe + 585 0005 13 .uleb128 0x13 + 586 0006 0B .uleb128 0xb + 587 0007 03 .uleb128 0x3 + 588 0008 0E .uleb128 0xe + 589 0009 1B .uleb128 0x1b + 590 000a 0E .uleb128 0xe + 591 000b 55 .uleb128 0x55 + 592 000c 06 .uleb128 0x6 + 593 000d 11 .uleb128 0x11 + 594 000e 01 .uleb128 0x1 + 595 000f 52 .uleb128 0x52 + 596 0010 01 .uleb128 0x1 + 597 0011 10 .uleb128 0x10 + 598 0012 06 .uleb128 0x6 + 599 0013 00 .byte 0 + 600 0014 00 .byte 0 + 601 0015 02 .uleb128 0x2 + 602 0016 24 .uleb128 0x24 + 603 0017 00 .byte 0 + 604 0018 0B .uleb128 0xb + 605 0019 0B .uleb128 0xb + 606 001a 3E .uleb128 0x3e + 607 001b 0B .uleb128 0xb + 608 001c 03 .uleb128 0x3 + 609 001d 08 .uleb128 0x8 + 610 001e 00 .byte 0 + 611 001f 00 .byte 0 + 612 0020 03 .uleb128 0x3 + 613 0021 24 .uleb128 0x24 + 614 0022 00 .byte 0 + 615 0023 0B .uleb128 0xb + 616 0024 0B .uleb128 0xb + 617 0025 3E .uleb128 0x3e + 618 0026 0B .uleb128 0xb + 619 0027 03 .uleb128 0x3 + 620 0028 0E .uleb128 0xe + 621 0029 00 .byte 0 + 622 002a 00 .byte 0 + 623 002b 04 .uleb128 0x4 + ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 12 + + + 624 002c 16 .uleb128 0x16 + 625 002d 00 .byte 0 + 626 002e 03 .uleb128 0x3 + 627 002f 0E .uleb128 0xe + 628 0030 3A .uleb128 0x3a + 629 0031 0B .uleb128 0xb + 630 0032 3B .uleb128 0x3b + 631 0033 0B .uleb128 0xb + 632 0034 49 .uleb128 0x49 + 633 0035 13 .uleb128 0x13 + 634 0036 00 .byte 0 + 635 0037 00 .byte 0 + 636 0038 05 .uleb128 0x5 + 637 0039 0F .uleb128 0xf + 638 003a 00 .byte 0 + 639 003b 0B .uleb128 0xb + 640 003c 0B .uleb128 0xb + 641 003d 49 .uleb128 0x49 + 642 003e 13 .uleb128 0x13 + 643 003f 00 .byte 0 + 644 0040 00 .byte 0 + 645 0041 06 .uleb128 0x6 + 646 0042 26 .uleb128 0x26 + 647 0043 00 .byte 0 + 648 0044 49 .uleb128 0x49 + 649 0045 13 .uleb128 0x13 + 650 0046 00 .byte 0 + 651 0047 00 .byte 0 + 652 0048 07 .uleb128 0x7 + 653 0049 15 .uleb128 0x15 + 654 004a 00 .byte 0 + 655 004b 27 .uleb128 0x27 + 656 004c 0C .uleb128 0xc + 657 004d 00 .byte 0 + 658 004e 00 .byte 0 + 659 004f 08 .uleb128 0x8 + 660 0050 13 .uleb128 0x13 + 661 0051 01 .byte 0x1 + 662 0052 0B .uleb128 0xb + 663 0053 05 .uleb128 0x5 + 664 0054 3A .uleb128 0x3a + 665 0055 0B .uleb128 0xb + 666 0056 3B .uleb128 0x3b + 667 0057 0B .uleb128 0xb + 668 0058 01 .uleb128 0x1 + 669 0059 13 .uleb128 0x13 + 670 005a 00 .byte 0 + 671 005b 00 .byte 0 + 672 005c 09 .uleb128 0x9 + 673 005d 0D .uleb128 0xd + 674 005e 00 .byte 0 + 675 005f 03 .uleb128 0x3 + 676 0060 0E .uleb128 0xe + 677 0061 3A .uleb128 0x3a + 678 0062 0B .uleb128 0xb + 679 0063 3B .uleb128 0x3b + 680 0064 0B .uleb128 0xb + ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 13 + + + 681 0065 49 .uleb128 0x49 + 682 0066 13 .uleb128 0x13 + 683 0067 38 .uleb128 0x38 + 684 0068 0A .uleb128 0xa + 685 0069 00 .byte 0 + 686 006a 00 .byte 0 + 687 006b 0A .uleb128 0xa + 688 006c 01 .uleb128 0x1 + 689 006d 01 .byte 0x1 + 690 006e 49 .uleb128 0x49 + 691 006f 13 .uleb128 0x13 + 692 0070 01 .uleb128 0x1 + 693 0071 13 .uleb128 0x13 + 694 0072 00 .byte 0 + 695 0073 00 .byte 0 + 696 0074 0B .uleb128 0xb + 697 0075 21 .uleb128 0x21 + 698 0076 00 .byte 0 + 699 0077 49 .uleb128 0x49 + 700 0078 13 .uleb128 0x13 + 701 0079 2F .uleb128 0x2f + 702 007a 0B .uleb128 0xb + 703 007b 00 .byte 0 + 704 007c 00 .byte 0 + 705 007d 0C .uleb128 0xc + 706 007e 2E .uleb128 0x2e + 707 007f 01 .byte 0x1 + 708 0080 3F .uleb128 0x3f + 709 0081 0C .uleb128 0xc + 710 0082 03 .uleb128 0x3 + 711 0083 0E .uleb128 0xe + 712 0084 3A .uleb128 0x3a + 713 0085 0B .uleb128 0xb + 714 0086 3B .uleb128 0x3b + 715 0087 0B .uleb128 0xb + 716 0088 27 .uleb128 0x27 + 717 0089 0C .uleb128 0xc + 718 008a 11 .uleb128 0x11 + 719 008b 01 .uleb128 0x1 + 720 008c 12 .uleb128 0x12 + 721 008d 01 .uleb128 0x1 + 722 008e 40 .uleb128 0x40 + 723 008f 06 .uleb128 0x6 + 724 0090 9742 .uleb128 0x2117 + 725 0092 0C .uleb128 0xc + 726 0093 01 .uleb128 0x1 + 727 0094 13 .uleb128 0x13 + 728 0095 00 .byte 0 + 729 0096 00 .byte 0 + 730 0097 0D .uleb128 0xd + 731 0098 898201 .uleb128 0x4109 + 732 009b 01 .byte 0x1 + 733 009c 11 .uleb128 0x11 + 734 009d 01 .uleb128 0x1 + 735 009e 31 .uleb128 0x31 + 736 009f 13 .uleb128 0x13 + 737 00a0 00 .byte 0 + ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 14 + + + 738 00a1 00 .byte 0 + 739 00a2 0E .uleb128 0xe + 740 00a3 8A8201 .uleb128 0x410a + 741 00a6 00 .byte 0 + 742 00a7 02 .uleb128 0x2 + 743 00a8 0A .uleb128 0xa + 744 00a9 9142 .uleb128 0x2111 + 745 00ab 0A .uleb128 0xa + 746 00ac 00 .byte 0 + 747 00ad 00 .byte 0 + 748 00ae 0F .uleb128 0xf + 749 00af 34 .uleb128 0x34 + 750 00b0 00 .byte 0 + 751 00b1 03 .uleb128 0x3 + 752 00b2 0E .uleb128 0xe + 753 00b3 3A .uleb128 0x3a + 754 00b4 0B .uleb128 0xb + 755 00b5 3B .uleb128 0x3b + 756 00b6 0B .uleb128 0xb + 757 00b7 49 .uleb128 0x49 + 758 00b8 13 .uleb128 0x13 + 759 00b9 3F .uleb128 0x3f + 760 00ba 0C .uleb128 0xc + 761 00bb 3C .uleb128 0x3c + 762 00bc 0C .uleb128 0xc + 763 00bd 00 .byte 0 + 764 00be 00 .byte 0 + 765 00bf 10 .uleb128 0x10 + 766 00c0 34 .uleb128 0x34 + 767 00c1 00 .byte 0 + 768 00c2 03 .uleb128 0x3 + 769 00c3 0E .uleb128 0xe + 770 00c4 3A .uleb128 0x3a + 771 00c5 0B .uleb128 0xb + 772 00c6 3B .uleb128 0x3b + 773 00c7 0B .uleb128 0xb + 774 00c8 49 .uleb128 0x49 + 775 00c9 13 .uleb128 0x13 + 776 00ca 3F .uleb128 0x3f + 777 00cb 0C .uleb128 0xc + 778 00cc 02 .uleb128 0x2 + 779 00cd 0A .uleb128 0xa + 780 00ce 00 .byte 0 + 781 00cf 00 .byte 0 + 782 00d0 11 .uleb128 0x11 + 783 00d1 2E .uleb128 0x2e + 784 00d2 01 .byte 0x1 + 785 00d3 3F .uleb128 0x3f + 786 00d4 0C .uleb128 0xc + 787 00d5 03 .uleb128 0x3 + 788 00d6 0E .uleb128 0xe + 789 00d7 3A .uleb128 0x3a + 790 00d8 0B .uleb128 0xb + 791 00d9 3B .uleb128 0x3b + 792 00da 0B .uleb128 0xb + 793 00db 27 .uleb128 0x27 + 794 00dc 0C .uleb128 0xc + ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 15 + + + 795 00dd 3C .uleb128 0x3c + 796 00de 0C .uleb128 0xc + 797 00df 00 .byte 0 + 798 00e0 00 .byte 0 + 799 00e1 12 .uleb128 0x12 + 800 00e2 05 .uleb128 0x5 + 801 00e3 00 .byte 0 + 802 00e4 49 .uleb128 0x49 + 803 00e5 13 .uleb128 0x13 + 804 00e6 00 .byte 0 + 805 00e7 00 .byte 0 + 806 00e8 13 .uleb128 0x13 + 807 00e9 18 .uleb128 0x18 + 808 00ea 00 .byte 0 + 809 00eb 00 .byte 0 + 810 00ec 00 .byte 0 + 811 00ed 00 .byte 0 + 812 .section .debug_loc,"",%progbits + 813 .Ldebug_loc0: + 814 .LLST0: + 815 0000 00000000 .4byte .LFB7 + 816 0004 02000000 .4byte .LCFI0 + 817 0008 0200 .2byte 0x2 + 818 000a 7D .byte 0x7d + 819 000b 00 .sleb128 0 + 820 000c 02000000 .4byte .LCFI0 + 821 0010 10000000 .4byte .LFE7 + 822 0014 0200 .2byte 0x2 + 823 0016 7D .byte 0x7d + 824 0017 08 .sleb128 8 + 825 0018 00000000 .4byte 0 + 826 001c 00000000 .4byte 0 + 827 .section .debug_aranges,"",%progbits + 828 0000 1C000000 .4byte 0x1c + 829 0004 0200 .2byte 0x2 + 830 0006 00000000 .4byte .Ldebug_info0 + 831 000a 04 .byte 0x4 + 832 000b 00 .byte 0 + 833 000c 0000 .2byte 0 + 834 000e 0000 .2byte 0 + 835 0010 00000000 .4byte .LFB7 + 836 0014 10000000 .4byte .LFE7-.LFB7 + 837 0018 00000000 .4byte 0 + 838 001c 00000000 .4byte 0 + 839 .section .debug_ranges,"",%progbits + 840 .Ldebug_ranges0: + 841 0000 00000000 .4byte .LFB7 + 842 0004 10000000 .4byte .LFE7 + 843 0008 00000000 .4byte 0 + 844 000c 00000000 .4byte 0 + 845 .section .debug_line,"",%progbits + 846 .Ldebug_line0: + 847 0000 9B000000 .section .debug_str,"MS",%progbits,1 + 847 02008400 + 847 00000201 + 847 FB0E0D00 + 847 01010101 + ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 16 + + + 848 .LASF22: + 849 0000 76656374 .ascii "vector24\000" + 849 6F723234 + 849 00 + 850 .LASF35: + 851 0009 433A5C55 .ascii "C:\\Users\\Imanol\\devel\\smartcities\\Project\\app" + 851 73657273 + 851 5C496D61 + 851 6E6F6C5C + 851 64657665 + 852 0036 6C696361 .ascii "lications\\smartcities\000" + 852 74696F6E + 852 735C736D + 852 61727463 + 852 69746965 + 853 .LASF12: + 854 004c 6972715F .ascii "irq_vector_t\000" + 854 76656374 + 854 6F725F74 + 854 00 + 855 .LASF26: + 856 0059 76656374 .ascii "vector34\000" + 856 6F723334 + 856 00 + 857 .LASF32: + 858 0062 5F766563 .ascii "_vectors\000" + 858 746F7273 + 858 00 + 859 .LASF13: + 860 006b 696E6974 .ascii "init_stack\000" + 860 5F737461 + 860 636B00 + 861 .LASF28: + 862 0076 73797374 .ascii "systick_vector\000" + 862 69636B5F + 862 76656374 + 862 6F7200 + 863 .LASF24: + 864 0085 73766361 .ascii "svcall_vector\000" + 864 6C6C5F76 + 864 6563746F + 864 7200 + 865 .LASF33: + 866 0093 474E5520 .ascii "GNU C 4.7.2\000" + 866 4320342E + 866 372E3200 + 867 .LASF2: + 868 009f 756E7369 .ascii "unsigned char\000" + 868 676E6564 + 868 20636861 + 868 7200 + 869 .LASF6: + 870 00ad 6C6F6E67 .ascii "long unsigned int\000" + 870 20756E73 + 870 69676E65 + 870 6420696E + 870 7400 + ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 17 + + + 871 .LASF4: + 872 00bf 73686F72 .ascii "short unsigned int\000" + 872 7420756E + 872 7369676E + 872 65642069 + 872 6E7400 + 873 .LASF20: + 874 00d2 76656374 .ascii "vector1c\000" + 874 6F723163 + 874 00 + 875 .LASF34: + 876 00db 2E2E2F2E .ascii "../..//os/ports/GCC/ARMCMx/STM32F1xx/vectors.c\000" + 876 2E2F2F6F + 876 732F706F + 876 7274732F + 876 4743432F + 877 .LASF0: + 878 010a 756E7369 .ascii "unsigned int\000" + 878 676E6564 + 878 20696E74 + 878 00 + 879 .LASF15: + 880 0117 6E6D695F .ascii "nmi_vector\000" + 880 76656374 + 880 6F7200 + 881 .LASF8: + 882 0122 6C6F6E67 .ascii "long long unsigned int\000" + 882 206C6F6E + 882 6720756E + 882 7369676E + 882 65642069 + 883 .LASF18: + 884 0139 62757366 .ascii "busfault_vector\000" + 884 61756C74 + 884 5F766563 + 884 746F7200 + 885 .LASF23: + 886 0149 76656374 .ascii "vector28\000" + 886 6F723238 + 886 00 + 887 .LASF19: + 888 0152 75736167 .ascii "usagefault_vector\000" + 888 65666175 + 888 6C745F76 + 888 6563746F + 888 7200 + 889 .LASF30: + 890 0164 76656374 .ascii "vectors_t\000" + 890 6F72735F + 890 7400 + 891 .LASF9: + 892 016e 73697A65 .ascii "sizetype\000" + 892 74797065 + 892 00 + 893 .LASF27: + 894 0177 70656E64 .ascii "pendsv_vector\000" + 894 73765F76 + ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 18 + + + 894 6563746F + 894 7200 + 895 .LASF16: + 896 0185 68617264 .ascii "hardfault_vector\000" + 896 6661756C + 896 745F7665 + 896 63746F72 + 896 00 + 897 .LASF7: + 898 0196 6C6F6E67 .ascii "long long int\000" + 898 206C6F6E + 898 6720696E + 898 7400 + 899 .LASF10: + 900 01a4 63686172 .ascii "char\000" + 900 00 + 901 .LASF17: + 902 01a9 6D656D6D .ascii "memmanage_vector\000" + 902 616E6167 + 902 655F7665 + 902 63746F72 + 902 00 + 903 .LASF37: + 904 01ba 7072696E .ascii "print\000" + 904 7400 + 905 .LASF36: + 906 01c0 5F756E68 .ascii "_unhandled_exception\000" + 906 616E646C + 906 65645F65 + 906 78636570 + 906 74696F6E + 907 .LASF29: + 908 01d5 76656374 .ascii "vectors\000" + 908 6F727300 + 909 .LASF3: + 910 01dd 73686F72 .ascii "short int\000" + 910 7420696E + 910 7400 + 911 .LASF14: + 912 01e7 72657365 .ascii "reset_vector\000" + 912 745F7665 + 912 63746F72 + 912 00 + 913 .LASF11: + 914 01f4 75696E74 .ascii "uint32_t\000" + 914 33325F74 + 914 00 + 915 .LASF5: + 916 01fd 6C6F6E67 .ascii "long int\000" + 916 20696E74 + 916 00 + 917 .LASF1: + 918 0206 7369676E .ascii "signed char\000" + 918 65642063 + 918 68617200 + 919 .LASF25: + 920 0212 64656275 .ascii "debugmonitor_vector\000" + ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 19 + + + 920 676D6F6E + 920 69746F72 + 920 5F766563 + 920 746F7200 + 921 .LASF21: + 922 0226 76656374 .ascii "vector20\000" + 922 6F723230 + 922 00 + 923 .LASF31: + 924 022f 5F5F6D61 .ascii "__main_stack_end__\000" + 924 696E5F73 + 924 7461636B + 924 5F656E64 + 924 5F5F00 + 925 .ident "GCC: (GNU) 4.7.2" + ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 20 + + +DEFINED SYMBOLS + *ABS*:00000000 vectors.c +C:\cygwin\tmp\cc7Nk9HS.s:19 .text._unhandled_exception:00000000 $t +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 _unhandled_exception +C:\cygwin\tmp\cc7Nk9HS.s:47 .text._unhandled_exception:0000000c $d +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 HardFaultVector +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 MemManageVector +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 BusFaultVector +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 UsageFaultVector +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector1C +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector20 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector24 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector28 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 SVCallVector +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 DebugMonitorVector +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector34 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 PendSVVector +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 SysTickVector +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector40 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector44 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector48 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector4C +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector50 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector54 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector58 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector5C +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector60 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector64 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector68 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector6C +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector70 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector74 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector78 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector7C +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector80 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector84 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector88 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector8C +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector90 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector94 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector98 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector9C +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorA0 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorA4 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorA8 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorAC +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorB0 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorB4 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorB8 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorBC +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorC0 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorC4 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorC8 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorCC +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorD0 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorD4 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorD8 + ARM GAS C:\cygwin\tmp\cc7Nk9HS.s page 21 + + +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorDC +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorE0 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorE4 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorE8 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorEC +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorF0 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorF4 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorF8 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 VectorFC +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector100 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector104 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector108 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector10C +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector110 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector114 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector118 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector11C +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector120 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector124 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector128 +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 Vector12C +C:\cygwin\tmp\cc7Nk9HS.s:25 .text._unhandled_exception:00000000 NMIVector +C:\cygwin\tmp\cc7Nk9HS.s:208 vectors:00000000 _vectors +C:\cygwin\tmp\cc7Nk9HS.s:201 .rodata.str1.4:00000000 $d +C:\cygwin\tmp\cc7Nk9HS.s:205 vectors:00000000 $d + .debug_frame:00000010 $d + +UNDEFINED SYMBOLS +print +__main_stack_end__ +ResetHandler diff --git a/Project/applications/smartcities/buttonExample.c b/Project/applications/smartcities/buttonExample.c new file mode 100644 index 0000000..140ff45 --- /dev/null +++ b/Project/applications/smartcities/buttonExample.c @@ -0,0 +1,134 @@ +/* + * This software is copyrighted by and is the sole property of eConais. + * All rights, title, ownership, or other interests in the software remain + * the property of eConais. This software may only be used in accordance + * with the corresponding license agreement. Any unauthorized use, + * duplication, transmission, distribution, or disclosure of this software + * is expressly forbidden. + * + * This copyright notice may not be removed or modified without prior written + * consent of eConais. + * + * eConais reserves the right to modify this software without + * notice. + * + * eConais + * Patras Science Park support@econais.com + * 26504 Platani, Patras http://www.econais.com + * GREECE + + * + * This file is part of WiSmart SDK + * + * Author: eConais RnD Group + * + */ + +#include "buttonExample.h" + +#define DBG(fmt,...) if(1){printf("[DBG] "fmt"\r\n", ##__VA_ARGS__);}else{({});} + + +uint32_t sw1_irqs = 0; +uint32_t sw3_irqs = 0; + + +void buttons_process(){ + DBG("SW1 presses = %u, SW3 presses = %u",sw1_irqs, sw3_irqs); +} + +void buttons_init(){ + + GPIO_InitTypeDef GPIO_InitStructure; + EXTI_InitTypeDef EXTI_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + /* + * SW1 button configuration + */ + DBG("Setup SW1.."); + RCC_APB2PeriphClockCmd(SW1_APB, ENABLE); + + GPIO_InitStructure.GPIO_Pin = SW1_PIN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(SW1_PORT, &GPIO_InitStructure); + + NVIC_InitStructure.NVIC_IRQChannel = SW1_IRQ_CHANNEL; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + GPIO_EXTILineConfig(SW1_PORT_SOURCE, SW1_PIN_SOURCE); + + EXTI_InitStructure.EXTI_Line = SW1_EXTI_LINE; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_Init(&EXTI_InitStructure); + + /* + * SW3 button configuration + */ + DBG("Setup SW3.."); + RCC_APB2PeriphClockCmd(SW3_APB, ENABLE); + + GPIO_InitStructure.GPIO_Pin = SW3_PIN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(SW3_PORT, &GPIO_InitStructure); + + NVIC_InitStructure.NVIC_IRQChannel = SW3_IRQ_CHANNEL; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + GPIO_EXTILineConfig(SW3_PORT_SOURCE, SW3_PIN_SOURCE); + + EXTI_InitStructure.EXTI_Line = SW3_EXTI_LINE; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_Init(&EXTI_InitStructure); + + DBG("OK!\r\n"); +} + +/* +* SW1 IRQ handler +*/ +CH_IRQ_HANDLER(SW1_IRQ_HANDLER){ + CH_IRQ_PROLOGUE(); + chSysLockFromIsr(); + + /* + * !!! NOTE: The call of printf() from an IRQ routine is forbidden. + * Use printI() instead. + */ + + /* + * SW1 button pressed ? + */ + if(EXTI_GetITStatus(SW1_EXTI_LINE) != RESET){ + EXTI_ClearITPendingBit(SW1_EXTI_LINE); + printI("SW1 IRQ!\r\n"); + sw1_irqs++; + } + + /* + * SW3 button pressed ? + */ + if(EXTI_GetITStatus(SW3_EXTI_LINE) != RESET){ + EXTI_ClearITPendingBit(SW3_EXTI_LINE); + printI("SW3 IRQ!\r\n"); + sw3_irqs++; + } + + + chSysUnlockFromIsr(); + CH_IRQ_EPILOGUE(); +} + + diff --git a/Project/applications/smartcities/buttonExample.h b/Project/applications/smartcities/buttonExample.h new file mode 100644 index 0000000..fc1380a --- /dev/null +++ b/Project/applications/smartcities/buttonExample.h @@ -0,0 +1,74 @@ +/* + * This software is copyrighted by and is the sole property of eConais. + * All rights, title, ownership, or other interests in the software remain + * the property of eConais. This software may only be used in accordance + * with the corresponding license agreement. Any unauthorized use, + * duplication, transmission, distribution, or disclosure of this software + * is expressly forbidden. + * + * This copyright notice may not be removed or modified without prior written + * consent of eConais. + * + * eConais reserves the right to modify this software without + * notice. + * + * eConais + * Patras Science Park support@econais.com + * 26504 Platani, Patras http://www.econais.com + * GREECE + + * + * This file is part of WiSmart SDK + * + * Author: eConais RnD Group + * + */ + +#ifndef BUTTONS_EXAMPLE_H +#define BUTTONS_EXAMPLE_H + +#include "libwismart.h" +#include "ch.h" + +#include "stm32f10x_gpio.h" +#include "stm32f10x_rcc.h" +#include "stm32f10x_exti.h" + +void buttons_init(void); +void buttons_process(void); + +#ifdef SDK_REV_9_2 + /* + * SDK 9.2 + */ + + /* + * SW1 button definitions + */ + #define SW1_PORT GPIOC + #define SW1_APB RCC_APB2Periph_GPIOC + #define SW1_PORT_SOURCE GPIO_PortSourceGPIOC + #define SW1_PIN GPIO_Pin_14 + #define SW1_PIN_SOURCE GPIO_PinSource14 + #define SW1_EXTI_LINE EXTI_Line14 + #define SW1_IRQ_CHANNEL EXTI15_10_IRQn + #define SW1_IRQ_HANDLER VectorE0 /* Look in os/ports/GCC/ARMCMx/STM32F1xx/vectors.c for this definition */ + + /* + * SW2 button definitions + */ + #define SW3_PORT GPIOC + #define SW3_APB RCC_APB2Periph_GPIOC + #define SW3_PORT_SOURCE GPIO_PortSourceGPIOC + #define SW3_PIN GPIO_Pin_15 + #define SW3_PIN_SOURCE GPIO_PinSource15 + #define SW3_EXTI_LINE EXTI_Line15 + #define SW3_IRQ_CHANNEL EXTI15_10_IRQn + #define SW3_IRQ_HANDLER VectorE0 /* Look in os/ports/GCC/ARMCMx/STM32F1xx/vectors.c for this definition */ +#else + /* + * !!! Not supported SDK revision + */ +#endif + +#endif \ No newline at end of file diff --git a/Project/applications/smartcities/flash.bat b/Project/applications/smartcities/flash.bat new file mode 100644 index 0000000..8146deb --- /dev/null +++ b/Project/applications/smartcities/flash.bat @@ -0,0 +1,7 @@ + +::ECHO build +::make -j 12 + +:: -HardRst +ECHO flash +C:\ST-LINK_Utility\ST-LINK_CLI.exe -c SWD -p build/buttonExample.bin 0x08000000 -Run diff --git a/Project/applications/smartcities/main.c b/Project/applications/smartcities/main.c new file mode 100644 index 0000000..66851d7 --- /dev/null +++ b/Project/applications/smartcities/main.c @@ -0,0 +1,93 @@ +/* + * This software is copyrighted by eConais This software may only be used in accordance + * with the corresponding license agreement. Any unauthorized use, + * duplication, transmission, distribution, or disclosure of this software + * is expressly forbidden. + * + * This copyright notice may not be removed or modified without prior written + * consent of eConais. + * + * eConais + * Patras Science Park info@econais.com + * 26504 Platani, Patras http://www.econais.com + * GREECE + + * + * This file is part of the WFS Project + * + * Author: eConais RnD Group + * + */ + +#include "libwismart.h" +#include "libwismart_irqs.h" /* implement irq handlers */ +#include "lwip/inet.h" + +#include "buttonExample.h" + +void initLibwismart(void); + +/* + @brief Initializes the libwismart library according to user configuration +*/ +void initLibwismart(){ + + /* + Get the default hardware configuration + */ + wismart_hwif_t hwif = libwismart_GetDefaultHWIF(); + +#ifdef AUDIO_SDK_VERSION_1_X + +#endif + +#ifdef AUDIO_SDK_VERSION_2_X + hwif.wifi.gpio_3_3v.port = GPIOD; + hwif.wifi.gpio_3_3v.ahb = RCC_APB2Periph_GPIOD; + hwif.wifi.gpio_3_3v.pin = GPIO_Pin_0; + hwif.wifi.gpio_3_3v.remap = GPIO_Remap_PD01; +#endif + + /* + Init the wismart module + */ + libwismart_Init(hwif); +} + + + + + +/* + @brief Main Thread + */ +int main(void){ + + /* + * 1. Init the libwismart + */ + initLibwismart(); + + /* + * 2. Enable power save + */ + libwismart_PowerSave_Enable(); + libwismart_PowerSave_HigherProfile(TRUE); + + /* + * 3.Init our application + */ + buttons_init(); + + /* + * Main loop + */ + for(;;){ + + buttons_process(); + + /* Sleep and give priority to other threads */ + chThdSleepMilliseconds(500); + } +} + diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/CoreSupport/core_cm3.c b/Project/econais/STM32_Libs/F1/CMSIS/CM3/CoreSupport/core_cm3.c new file mode 100644 index 0000000..56fddc5 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/CoreSupport/core_cm3.c @@ -0,0 +1,784 @@ +/**************************************************************************//** + * @file core_cm3.c + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +__ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +__ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +__ASM void __CLREX(void) +{ + clrex +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +__ASM uint32_t __get_BASEPRI(void) +{ + mrs r0, basepri + bx lr +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +__ASM void __set_BASEPRI(uint32_t basePri) +{ + msr basepri, r0 + bx lr +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +__ASM uint32_t __get_FAULTMASK(void) +{ + mrs r0, faultmask + bx lr +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +__ASM void __set_FAULTMASK(uint32_t faultMask) +{ + msr faultmask, r0 + bx lr +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#pragma diag_suppress=Pe940 + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + __ASM("rev16 r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + __ASM("rbit r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +uint8_t __LDREXB(uint8_t *addr) +{ + __ASM("ldrexb r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + __ASM("ldrexh r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + __ASM("ldrex r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + __ASM("strexb r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + __ASM("strexh r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + __ASM("strex r0, r0, [r1]"); + __ASM("bx lr"); +} + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) __attribute__( ( naked ) ); +uint32_t __get_PSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, psp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n\t" + "BX lr \n\t" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) __attribute__( ( naked ) ); +uint32_t __get_MSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, msp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n\t" + "BX lr \n\t" : : "r" (topOfMainStack) ); +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +uint32_t __get_BASEPRI(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +uint32_t __get_FAULTMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +uint8_t __LDREXB(uint8_t *addr) +{ + uint8_t result=0; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + uint16_t result=0; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/CoreSupport/core_cm3.h b/Project/econais/STM32_Libs/F1/CMSIS/CM3/CoreSupport/core_cm3.h new file mode 100644 index 0000000..2b6b51a --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/CoreSupport/core_cm3.h @@ -0,0 +1,1818 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CM3_CORE_H__ +#define __CM3_CORE_H__ + +/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration + * + * List of Lint messages which will be suppressed and not shown: + * - Error 10: \n + * register uint32_t __regBasePri __asm("basepri"); \n + * Error 10: Expecting ';' + * . + * - Error 530: \n + * return(__regBasePri); \n + * Warning 530: Symbol '__regBasePri' (line 264) not initialized + * . + * - Error 550: \n + * __regBasePri = (basePri & 0x1ff); \n + * Warning 550: Symbol '__regBasePri' (line 271) not accessed + * . + * - Error 754: \n + * uint32_t RESERVED0[24]; \n + * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced + * . + * - Error 750: \n + * #define __CM3_CORE_H__ \n + * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced + * . + * - Error 528: \n + * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n + * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced + * . + * - Error 751: \n + * } InterruptType_Type; \n + * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced + * . + * Note: To re-enable a Message, insert a space before 'lint' * + * + */ + +/*lint -save */ +/*lint -e10 */ +/*lint -e530 */ +/*lint -e550 */ +/*lint -e754 */ +/*lint -e750 */ +/*lint -e528 */ +/*lint -e751 */ + + +/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core registers and bitfields + - Cortex-M core peripheral base address + @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + +#include /* Include standard types */ + +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ +#endif + + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register + @{ +*/ + + +/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ +} NVIC_Type; +/*@}*/ /* end of group CMSIS_CM3_NVIC */ + + +/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB + memory mapped structure for System Control Block (SCB) + @{ + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +/*@}*/ /* end of group CMSIS_CM3_SCB */ + + +/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick + memory mapped structure for SysTick + @{ + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +/*@}*/ /* end of group CMSIS_CM3_SysTick */ + + +/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM + memory mapped structure for Instrumentation Trace Macrocell (ITM) + @{ + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +/*@}*/ /* end of group CMSIS_CM3_ITM */ + + +/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type + memory mapped structure for Interrupt Type + @{ + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ +#else + uint32_t RESERVED1; +#endif +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ +/*@}*/ /* end of group CMSIS_CM3_InterruptType */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) +/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU + memory mapped structure for Memory Protection Unit (MPU) + @{ + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@}*/ /* end of group CMSIS_CM3_MPU */ +#endif + + +/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug + memory mapped structure for Core Debug Register + @{ + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ + + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_register */ + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#define __enable_fault_irq __enable_fiq +#define __disable_fault_irq __disable_fiq + +#define __NOP __nop +#define __WFI __wfi +#define __WFE __wfe +#define __SEV __sev +#define __ISB() __isb(0) +#define __DSB() __dsb(0) +#define __DMB() __dmb(0) +#define __REV __rev +#define __RBIT __rbit +#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) +#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) +#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) +#define __STREXB(value, ptr) __strex(value, ptr) +#define __STREXH(value, ptr) __strex(value, ptr) +#define __STREXW(value, ptr) __strex(value, ptr) + + +/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ +/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +extern void __CLREX(void); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +#else /* (__ARMCC_VERSION >= 400000) */ + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +#define __CLREX __clrex + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & 1); +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ +#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ + +static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } + +#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ +static __INLINE void __WFI() { __ASM ("wfi"); } +static __INLINE void __WFE() { __ASM ("wfe"); } +static __INLINE void __SEV() { __ASM ("sev"); } +static __INLINE void __CLREX() { __ASM ("clrex"); } + +/* intrinsic void __ISB(void) */ +/* intrinsic void __DSB(void) */ +/* intrinsic void __DMB(void) */ +/* intrinsic void __set_PRIMASK(); */ +/* intrinsic void __get_PRIMASK(); */ +/* intrinsic void __set_FAULTMASK(); */ +/* intrinsic void __get_FAULTMASK(); */ +/* intrinsic uint32_t __REV(uint32_t value); */ +/* intrinsic uint32_t __REVSH(uint32_t value); */ +/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ +/* intrinsic unsigned long __LDREX(unsigned long *); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } +static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } + +static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } + +static __INLINE void __NOP() { __ASM volatile ("nop"); } +static __INLINE void __WFI() { __ASM volatile ("wfi"); } +static __INLINE void __WFE() { __ASM volatile ("wfe"); } +static __INLINE void __SEV() { __ASM volatile ("sev"); } +static __INLINE void __ISB() { __ASM volatile ("isb"); } +static __INLINE void __DSB() { __ASM volatile ("dsb"); } +static __INLINE void __DMB() { __ASM volatile ("dmb"); } +static __INLINE void __CLREX() { __ASM volatile ("clrex"); } + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +extern uint32_t __REV(uint32_t value); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + + +/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface + Core Function Interface containing: + - Core NVIC Functions + - Core SysTick Functions + - Core Reset Functions +*/ +/*@{*/ + +/* ########################## NVIC functions #################################### */ + +/** + * @brief Set the Priority Grouping in NVIC Interrupt Controller + * + * @param PriorityGroup is priority grouping field + * + * Set the priority grouping field using the required unlock sequence. + * The parameter priority_grouping is assigned to the field + * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** + * @brief Get the Priority Grouping from NVIC Interrupt Controller + * + * @return priority grouping field + * + * Get the priority grouping from NVIC Interrupt Controller. + * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn The positive number of the external interrupt to enable + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn The positive number of the external interrupt to disable + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn The number of the device specifc interrupt + * @return 1 = interrupt pending, 0 = interrupt not pending + * + * Read the pending register in NVIC and return 1 if its status is pending, + * otherwise it returns 0 + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for set pending + * + * Set the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for clear pending + * + * Clear the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + +/** + * @brief Read the active bit for an external interrupt + * + * @param IRQn The number of the interrupt for read active bit + * @return 1 = interrupt active, 0 = interrupt not active + * + * Read the active register in NVIC and returns 1 if its status is active, + * otherwise it returns 0. + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn The number of the interrupt for set priority + * @param priority The priority to set + * + * Set the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + +/** + * @brief Read the priority for an interrupt + * + * @param IRQn The number of the interrupt for get priority + * @return The priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * The returned priority value is automatically aligned to the implemented + * priority bits of the microcontroller. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** + * @brief Encode the priority for an interrupt + * + * @param PriorityGroup The used priority group + * @param PreemptPriority The preemptive priority value (starting from 0) + * @param SubPriority The sub priority value (starting from 0) + * @return The encoded priority for the interrupt + * + * Encode the priority for an interrupt with the given priority group, + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The returned priority value can be used for NVIC_SetPriority(...) function + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** + * @brief Decode the priority of an interrupt + * + * @param Priority The priority for the interrupt + * @param PriorityGroup The used priority group + * @param pPreemptPriority The preemptive priority value (starting from 0) + * @param pSubPriority The sub priority value (starting from 0) + * + * Decode an interrupt priority value with the given priority group to + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The priority value can be retrieved with NVIC_GetPriority(...) function + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + + +/* ################################## SysTick function ############################################ */ + +#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) + +/** + * @brief Initialize and start the SysTick counter and its interrupt. + * + * @param ticks number of ticks between two interrupts + * @return 1 = failed, 0 = successful + * + * Initialise the system tick timer and its interrupt and start the + * system tick timer / counter in free running mode to generate + * periodical interrupts. + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + + + + +/* ################################## Reset function ############################################ */ + +/** + * @brief Initiate a system reset request. + * + * Initiate a system reset request to reset the MCU + */ +static __INLINE void NVIC_SystemReset(void) +{ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ + + + +/* ##################################### Debug In/Output function ########################################### */ + +/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface + Core Debug Interface containing: + - Core Debug Receive / Transmit Functions + - Core Debug Defines + - Core Debug Variables +*/ +/*@{*/ + +extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** + * @brief Outputs a character via the ITM channel 0 + * + * @param ch character to output + * @return character to output + * + * The function outputs a character via the ITM channel 0. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** + * @brief Inputs a character via variable ITM_RxBuffer + * + * @return received character, -1 = no character received + * + * The function inputs a character via variable ITM_RxBuffer. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE int ITM_ReceiveChar (void) { + int ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + * @brief Check if a character via variable ITM_RxBuffer is available + * + * @return 1 = character available, 0 = no character available + * + * The function checks variable ITM_RxBuffer whether a character is available or not. + * The function returns '1' if a character is available and '0' if no character is available. + */ +static __INLINE int ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_definitions */ + +#endif /* __CM3_CORE_H__ */ + +/*lint -restore */ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html new file mode 100644 index 0000000..b80f38d --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html @@ -0,0 +1,284 @@ + + + + + + + + + + + + +Release Notes for STM32F10x CMSIS + + + + + +
+


+

+
+ + + + + + +
+ + + + + + + + + +
Back to Release page
+

Release +Notes for STM32F10x CMSIS

+

Copyright 2011 STMicroelectronics

+

+
+

 

+ + + + + + +
+

Contents

+
    +
  1. STM32F10x CMSIS +update History
    2. +
  2. License
    3. +
+ +

STM32F10x CMSIS +update History


+

V3.5.0 / 11-March-2011

+

Main +Changes

+ +
    +
  • stm32f10x.h +and startup_stm32f10x_hd_vl.s files: remove the FSMC interrupt +definition for STM32F10x High-density Value line devices.
    +
    • +
  • system_stm32f10x.c file provided within the CMSIS folder.
    +
    • + +
+ +

3.4.0 +- 10/15/2010

+ +
    +
  1. General
    2. +
+ +
    +
  • Add support +for STM32F10x High-density Value line devices.
    • +
+
    +
  1. STM32F10x CMSIS Device Peripheral Access Layer
    2. +
+ + + +
    +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    +
    • Update to support High-density Value line devices
      • Add new define STM32F10X_HD_VL
        • +
      • RCC, AFIO, FSMC bits definition updated
        • +
      +
    • + + All +STM32 devices definitions are commented by default. User has to select the +appropriate device before starting else an error will be signaled on compile +time.
      • +
    • Add new IRQs definitons inside the IRQn_Type enumeration for STM23 High-density Value line devices.
      • +
    • "bool" type removed.
      +
      • +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    +
    • +
      +
    • "system_stm32f10x.c" moved to to "STM32F10x_StdPeriph_Template" directory. This file is also moved to each example directory under "STM32F10x_StdPeriph_Examples".
      +
      • +
    • SystemInit_ExtMemCtl() function: update to support High-density Value line devices.
      • +
    • Add "VECT_TAB_SRAM" inside "system_stm32f10x.c" +to select if the user want to place the Vector Table in internal SRAM. +An additional define is also to specify the Vector Table offset "VECT_TAB_OFFSET".
      +
      • + +
    +
  • STM32F10x CMSIS startup files:startup_stm32f10x_xx.s
    • Add three +startup files for STM32 High-density Value line devices: + startup_stm32f10x_hd_vl.s
    +
+

3.3.0 +- 04/16/2010

+ +
  1. General
+
  • Add support +for STM32F10x XL-density devices.
  • Add startup files for TrueSTUDIO toolchain
  1. STM32F10x CMSIS Device Peripheral Access Layer
+ +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    +
    • Update to support XL-density devices
      • Add new define STM32F10X_XL
      • Add new IRQs for TIM9..14
      • Update FLASH_TypeDef structure
      • Add new IP instances TIM9..14
      • RCC, AFIO, DBGMCU bits definition updated
    • Correct IRQs definition for MD-, LD-, MD_VL- and LD_VL-density devices (remove comma "," at the end of enum list)
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    +
    • SystemInit_ExtMemCtl() function: update to support XL-density devices
    • SystemInit() function: swap the order of SetSysClock() and SystemInit_ExtMemCtl() functions. 
      +
  • STM32F10x CMSIS startup files:
    • add three +startup files for STM32 XL-density devices: + startup_stm32f10x_xl.s
    • startup_stm32f10x_md_vl.s for RIDE7: add USART3 IRQ Handler (was missing in previous version)
    • Add startup files for TrueSTUDIO toolchain
+

3.2.0 +- 03/01/2010

+
    +
  1. General
    2. +
+
    + +
  • STM32F10x CMSIS files updated to CMSIS V1.30 release
    • +
  • Directory structure updated to be aligned with CMSIS V1.30
    +
    • +
  • Add support +for STM32 Low-density Value line (STM32F100x4/6) and +Medium-density Value line (STM32F100x8/B) devices. 
    • + +
+
    +
  1. CMSIS Core Peripheral Access Layer
+ +
    +
  1. STM32F10x CMSIS Device Peripheral Access Layer
    2. + +
+ +
    + +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    +
    • +
      +
    • Update +the stm32f10x.h file to support new Value line devices features: CEC +peripheral, new General purpose timers TIM15, TIM16 and TIM17.
      • +
    • Peripherals Bits definitions updated to be in line with Value line devices available features.
      +
      • +
    • HSE_Value, +HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE, +HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy +purposes.
      +
      • +
    +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    +
    • +
      +
    • SystemFrequency variable name changed to SystemCoreClock
      +
      • +
    • Default + SystemCoreClock is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.
      +
      • +
    • All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.
      +
      • +
    • Additional function void SystemCoreClockUpdate (void) is provided.
      +
      • +
    +
  • STM32F10x CMSIS Startup files: startup_stm32f10x_xx.s
    • +
      +
    • Add new +startup files for STM32 Low-density Value line devices: + startup_stm32f10x_ld_vl.s
      • +
    • Add new startup +files for STM32 Medium-density Value line devices: + startup_stm32f10x_md_vl.s
      • +
    • SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main.
      +To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file
      +
      • +
    • GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.
      +
      • +
    + +
+ +
    +
+

License

+

The +enclosed firmware and all the related documentation are not covered by +a License Agreement, if you need such License you can contact your +local STMicroelectronics office.

+

THE +PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO +SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR +ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY +CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY +CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH +THEIR PRODUCTS.

+

 

+
+
+

For +complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers +visit www.st.com/STM32

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s new file mode 100644 index 0000000..e34a520 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s @@ -0,0 +1,473 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_cl.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x Connectivity line Devices vector table for Atollic + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR + * address. + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word OTG_FS_WKUP_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word ETH_IRQHandler + .word ETH_WKUP_IRQHandler + .word CAN2_TX_IRQHandler + .word CAN2_RX0_IRQHandler + .word CAN2_RX1_IRQHandler + .word CAN2_SCE_IRQHandler + .word OTG_FS_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x Connectivity line Devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler ,Default_Handler + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s new file mode 100644 index 0000000..0aa9188 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s @@ -0,0 +1,469 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_hd.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x High Density Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Configure external SRAM mounted on STM3210E-EVAL board + * to be used as data memory (optional, to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FSMC_IRQHandler + .word SDIO_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x High Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s new file mode 100644 index 0000000..55aa398 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s @@ -0,0 +1,451 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_hd_vl.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x High Density Value Line Devices vector table for Atollic + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Configure external SRAM mounted on STM32100E-EVAL board + * to be used as data memory (optional, to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word CEC_IRQHandler + .word TIM12_IRQHandler + .word TIM13_IRQHandler + .word TIM14_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x High Density Value line devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak TIM13_IRQHandler + .thumb_set TIM13_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ + diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s new file mode 100644 index 0000000..2c5aaa0 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s @@ -0,0 +1,347 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_ld.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x Low Density Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address. + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word 0 + .word 0 + .word SPI1_IRQHandler + .word 0 + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F10x Low Density devices.*/ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s new file mode 100644 index 0000000..9af6e8b --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s @@ -0,0 +1,392 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_ld_vl.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x Low Density Value Line Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word 0 + .word 0 + .word SPI1_IRQHandler + .word 0 + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word CEC_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x01CC. This is for boot in RAM mode for + STM32F10x Medium Value Line Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ + diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s new file mode 100644 index 0000000..c14ba21 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s @@ -0,0 +1,363 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_md.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x Medium Density Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F10x Medium Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ + diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s new file mode 100644 index 0000000..4ac1230 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s @@ -0,0 +1,408 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_md_vl.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x Medium Density Value Line Devices vector table for Atollic + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word CEC_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x01CC. This is for boot in RAM mode for + STM32F10x Medium Value Line Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ + diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s new file mode 100644 index 0000000..19bdf5a --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s @@ -0,0 +1,467 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_xl.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x XL-Density Devices vector table for TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM3210E-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM9_IRQHandler + .word TIM1_UP_TIM10_IRQHandler + .word TIM1_TRG_COM_TIM11_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_TIM12_IRQHandler + .word TIM8_UP_TIM13_IRQHandler + .word TIM8_TRG_COM_TIM14_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FSMC_IRQHandler + .word SDIO_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x XL-Density devices. */ +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s new file mode 100644 index 0000000..8196e69 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s @@ -0,0 +1,368 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_cl.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C1 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s new file mode 100644 index 0000000..adc9b94 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s @@ -0,0 +1,358 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_hd.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x High Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system and also configure the external +;* SRAM mounted on STM3210E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_5_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd_vl.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd_vl.s new file mode 100644 index 0000000..d6082b0 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd_vl.s @@ -0,0 +1,346 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_hd_vl.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x High Density Value Line Devices vector table +;* for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system and also configure the external +;* SRAM mounted on STM32100E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD TIM12_IRQHandler ; TIM12 + DCD TIM13_IRQHandler ; TIM13 + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT TIM12_IRQHandler [WEAK] + EXPORT TIM13_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_5_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +CEC_IRQHandler +TIM12_IRQHandler +TIM13_IRQHandler +TIM14_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_5_IRQHandler +DMA2_Channel5_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s new file mode 100644 index 0000000..3f3ac2f --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s @@ -0,0 +1,297 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_ld.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x Low Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s new file mode 100644 index 0000000..fe22fc0 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s @@ -0,0 +1,304 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_ld_vl.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x Low Density Value Line Devices vector table +;* for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +CEC_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s new file mode 100644 index 0000000..3223fc9 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s @@ -0,0 +1,307 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s new file mode 100644 index 0000000..d3b8aa6 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s @@ -0,0 +1,315 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md_vl.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x Medium Density Value Line Devices vector table +;* for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +CEC_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s new file mode 100644 index 0000000..7970052 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s @@ -0,0 +1,358 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_xl.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system and also configure the external +;* SRAM mounted on STM3210E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_5_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s new file mode 100644 index 0000000..039ec06 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s @@ -0,0 +1,468 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_cl.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR + * address. + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word OTG_FS_WKUP_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word ETH_IRQHandler + .word ETH_WKUP_IRQHandler + .word CAN2_TX_IRQHandler + .word CAN2_RX0_IRQHandler + .word CAN2_RX1_IRQHandler + .word CAN2_SCE_IRQHandler + .word OTG_FS_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x Connectivity line Devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler ,Default_Handler + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s new file mode 100644 index 0000000..e4ba08c --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s @@ -0,0 +1,465 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_hd.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM3210E-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FSMC_IRQHandler + .word SDIO_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x High Density devices. */ +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s new file mode 100644 index 0000000..daad5cc --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s @@ -0,0 +1,442 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_hd_vl.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x High Density Value Line Devices vector table for RIDE7 + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM32100E-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word CEC_IRQHandler + .word TIM12_IRQHandler + .word TIM13_IRQHandler + .word TIM14_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x High Density Value line devices. */ + +/******************************************************************************* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak TIM13_IRQHandler + .thumb_set TIM13_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s new file mode 100644 index 0000000..aaa09ec --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s @@ -0,0 +1,343 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_ld.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word 0 + .word 0 + .word SPI1_IRQHandler + .word 0 + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F10x Low Density devices.*/ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s new file mode 100644 index 0000000..d4401be --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s @@ -0,0 +1,383 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_ld_vl.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x Low Density Value Line Devices vector table for RIDE7 + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word 0 + .word 0 + .word SPI1_IRQHandler + .word 0 + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word CEC_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x01CC. This is for boot in RAM mode for + STM32F10x Low Density Value Line devices. */ + +/******************************************************************************* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s new file mode 100644 index 0000000..4b4a050 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s @@ -0,0 +1,358 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_md.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F10x Medium Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s new file mode 100644 index 0000000..8bce997 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s @@ -0,0 +1,399 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_md_vl.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x Medium Density Value Line Devices vector table for RIDE7 + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word CEC_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x01CC. This is for boot in RAM mode for + STM32F10x Medium Value Line Density devices. */ + +/******************************************************************************* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s new file mode 100644 index 0000000..3d727a0 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s @@ -0,0 +1,465 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_xl.s + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief STM32F10x XL-Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM3210E-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM9_IRQHandler + .word TIM1_UP_TIM10_IRQHandler + .word TIM1_TRG_COM_TIM11_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_TIM12_IRQHandler + .word TIM8_UP_TIM13_IRQHandler + .word TIM8_TRG_COM_TIM14_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FSMC_IRQHandler + .word SDIO_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x XL Density devices. */ +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s new file mode 100644 index 0000000..55a7932 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s @@ -0,0 +1,507 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************* +;* File Name : startup_stm32f10x_cl.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x Connectivity line devices vector table for +;* EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C1 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + END +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s new file mode 100644 index 0000000..37ee7a2 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s @@ -0,0 +1,496 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_hd.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x High Density Devices vector table for EWARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system and the external SRAM +;* mounted on STM3210E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR address, +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_HP_CAN1_TX_IRQHandler + B USB_HP_CAN1_TX_IRQHandler + + PUBWEAK USB_LP_CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_LP_CAN1_RX0_IRQHandler + B USB_LP_CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:REORDER(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + PUBWEAK TIM8_BRK_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_BRK_IRQHandler + B TIM8_BRK_IRQHandler + + PUBWEAK TIM8_UP_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_UP_IRQHandler + B TIM8_UP_IRQHandler + + PUBWEAK TIM8_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_TRG_COM_IRQHandler + B TIM8_TRG_COM_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:REORDER(1) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel4_5_IRQHandler + B DMA2_Channel4_5_IRQHandler + + + END + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd_vl.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd_vl.s new file mode 100644 index 0000000..33f592f --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd_vl.s @@ -0,0 +1,461 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_hd_vl.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x High Density Value Line Devices vector table +;* for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system and the external SRAM +;* mounted on STM32100E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD TIM12_IRQHandler ; TIM12 + DCD TIM13_IRQHandler ; TIM13 + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK TIM12_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM12_IRQHandler + B TIM12_IRQHandler + + PUBWEAK TIM13_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM13_IRQHandler + B TIM13_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel4_5_IRQHandler + B DMA2_Channel4_5_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + END +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s new file mode 100644 index 0000000..e2b2b4d --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s @@ -0,0 +1,366 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_ld.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x Low Density Devices vector table for EWARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_HP_CAN1_TX_IRQHandler + B USB_HP_CAN1_TX_IRQHandler + + PUBWEAK USB_LP_CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_LP_CAN1_RX0_IRQHandler + B USB_LP_CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:REORDER(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + END +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s new file mode 100644 index 0000000..a4a4933 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s @@ -0,0 +1,369 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_ld_vl.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x Low Density Value Line Devices vector table +;* for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + END +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s new file mode 100644 index 0000000..5863eb9 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s @@ -0,0 +1,391 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x Medium Density Devices vector table for +;* EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_HP_CAN1_TX_IRQHandler + B USB_HP_CAN1_TX_IRQHandler + + PUBWEAK USB_LP_CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_LP_CAN1_RX0_IRQHandler + B USB_LP_CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:REORDER(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + END +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s new file mode 100644 index 0000000..add509d --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s @@ -0,0 +1,394 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md_vl.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x Medium Density Value Line Devices vector table +;* for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + END +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s new file mode 100644 index 0000000..a7f49c5 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s @@ -0,0 +1,496 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_xl.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x XL-Density Devices vector table for EWARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system and the external SRAM +;* mounted on STM3210E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR address, +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_HP_CAN1_TX_IRQHandler + B USB_HP_CAN1_TX_IRQHandler + + PUBWEAK USB_LP_CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_LP_CAN1_RX0_IRQHandler + B USB_LP_CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:REORDER(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:REORDER(1) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel4_5_IRQHandler + B DMA2_Channel4_5_IRQHandler + + + END + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h new file mode 100644 index 0000000..af0c7c9 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h @@ -0,0 +1,8336 @@ +/** + ****************************************************************************** + * @file stm32f10x.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F10x Connectivity line, + * High density, High density value line, Medium density, + * Medium density Value line, Low density, Low density Value line + * and XL-density devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x + * @{ + */ + +#ifndef __STM32F10x_H +#define __STM32F10x_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) + /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ + /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ + /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ + /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ + /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ + /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */ + /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */ + /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ +#endif +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + + - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers + where the Flash memory density ranges between 16 and 32 Kbytes. + - Low-density value line devices are STM32F100xx microcontrollers where the Flash + memory density ranges between 16 and 32 Kbytes. + - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers + where the Flash memory density ranges between 64 and 128 Kbytes. + - Medium-density value line devices are STM32F100xx microcontrollers where the + Flash memory density ranges between 64 and 128 Kbytes. + - High-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 256 and 512 Kbytes. + - High-density value line devices are STM32F100xx microcontrollers where the + Flash memory density ranges between 256 and 512 Kbytes. + - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 512 and 1024 Kbytes. + - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. + */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) + #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)" +#endif + +#if !defined USE_STDPERIPH_DRIVER +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined HSE_VALUE + #ifdef STM32F10X_CL + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ + #else + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #endif /* STM32F10X_CL */ +#endif /* HSE_VALUE */ + + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ + +#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ + +/** + * @brief STM32F10x Standard Peripheral Library version number + */ +#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F10X_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#ifdef STM32F10X_XL + #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ +#else + #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ +#endif /* STM32F10X_XL */ +#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @brief STM32F10x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + +#ifdef STM32F10X_LD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +#endif /* STM32F10X_LD */ + +#ifdef STM32F10X_LD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55 /*!< TIM7 Interrupt */ +#endif /* STM32F10X_LD_VL */ + +#ifdef STM32F10X_MD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +#endif /* STM32F10X_MD */ + +#ifdef STM32F10X_MD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55 /*!< TIM7 Interrupt */ +#endif /* STM32F10X_MD_VL */ + +#ifdef STM32F10X_HD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ +#endif /* STM32F10X_HD */ + +#ifdef STM32F10X_HD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ + TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ + TIM14_IRQn = 45, /*!< TIM14 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ + DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is + mapped at position 60 only if the MISC_REMAP bit in + the AFIO_MAPR2 register is set) */ +#endif /* STM32F10X_HD_VL */ + +#ifdef STM32F10X_XL + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ +#endif /* STM32F10X_XL */ + +#ifdef STM32F10X_CL + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ +#endif /* STM32F10X_CL */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32f10x.h" +#include + +/** @addtogroup Exported_types + * @{ + */ + +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT +#define HSE_Value HSE_VALUE +#define HSI_Value HSI_VALUE +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMPR1; + __IO uint32_t SMPR2; + __IO uint32_t JOFR1; + __IO uint32_t JOFR2; + __IO uint32_t JOFR3; + __IO uint32_t JOFR4; + __IO uint32_t HTR; + __IO uint32_t LTR; + __IO uint32_t SQR1; + __IO uint32_t SQR2; + __IO uint32_t SQR3; + __IO uint32_t JSQR; + __IO uint32_t JDR1; + __IO uint32_t JDR2; + __IO uint32_t JDR3; + __IO uint32_t JDR4; + __IO uint32_t DR; +} ADC_TypeDef; + +/** + * @brief Backup Registers + */ + +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DR1; + uint16_t RESERVED1; + __IO uint16_t DR2; + uint16_t RESERVED2; + __IO uint16_t DR3; + uint16_t RESERVED3; + __IO uint16_t DR4; + uint16_t RESERVED4; + __IO uint16_t DR5; + uint16_t RESERVED5; + __IO uint16_t DR6; + uint16_t RESERVED6; + __IO uint16_t DR7; + uint16_t RESERVED7; + __IO uint16_t DR8; + uint16_t RESERVED8; + __IO uint16_t DR9; + uint16_t RESERVED9; + __IO uint16_t DR10; + uint16_t RESERVED10; + __IO uint16_t RTCCR; + uint16_t RESERVED11; + __IO uint16_t CR; + uint16_t RESERVED12; + __IO uint16_t CSR; + uint16_t RESERVED13[5]; + __IO uint16_t DR11; + uint16_t RESERVED14; + __IO uint16_t DR12; + uint16_t RESERVED15; + __IO uint16_t DR13; + uint16_t RESERVED16; + __IO uint16_t DR14; + uint16_t RESERVED17; + __IO uint16_t DR15; + uint16_t RESERVED18; + __IO uint16_t DR16; + uint16_t RESERVED19; + __IO uint16_t DR17; + uint16_t RESERVED20; + __IO uint16_t DR18; + uint16_t RESERVED21; + __IO uint16_t DR19; + uint16_t RESERVED22; + __IO uint16_t DR20; + uint16_t RESERVED23; + __IO uint16_t DR21; + uint16_t RESERVED24; + __IO uint16_t DR22; + uint16_t RESERVED25; + __IO uint16_t DR23; + uint16_t RESERVED26; + __IO uint16_t DR24; + uint16_t RESERVED27; + __IO uint16_t DR25; + uint16_t RESERVED28; + __IO uint16_t DR26; + uint16_t RESERVED29; + __IO uint16_t DR27; + uint16_t RESERVED30; + __IO uint16_t DR28; + uint16_t RESERVED31; + __IO uint16_t DR29; + uint16_t RESERVED32; + __IO uint16_t DR30; + uint16_t RESERVED33; + __IO uint16_t DR31; + uint16_t RESERVED34; + __IO uint16_t DR32; + uint16_t RESERVED35; + __IO uint16_t DR33; + uint16_t RESERVED36; + __IO uint16_t DR34; + uint16_t RESERVED37; + __IO uint16_t DR35; + uint16_t RESERVED38; + __IO uint16_t DR36; + uint16_t RESERVED39; + __IO uint16_t DR37; + uint16_t RESERVED40; + __IO uint16_t DR38; + uint16_t RESERVED41; + __IO uint16_t DR39; + uint16_t RESERVED42; + __IO uint16_t DR40; + uint16_t RESERVED43; + __IO uint16_t DR41; + uint16_t RESERVED44; + __IO uint16_t DR42; + uint16_t RESERVED45; +} BKP_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; + __IO uint32_t TDTR; + __IO uint32_t TDLR; + __IO uint32_t TDHR; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; + __IO uint32_t RDTR; + __IO uint32_t RDLR; + __IO uint32_t RDHR; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; + __IO uint32_t MSR; + __IO uint32_t TSR; + __IO uint32_t RF0R; + __IO uint32_t RF1R; + __IO uint32_t IER; + __IO uint32_t ESR; + __IO uint32_t BTR; + uint32_t RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FMR; + __IO uint32_t FM1R; + uint32_t RESERVED2; + __IO uint32_t FS1R; + uint32_t RESERVED3; + __IO uint32_t FFA1R; + uint32_t RESERVED4; + __IO uint32_t FA1R; + uint32_t RESERVED5[8]; +#ifndef STM32F10X_CL + CAN_FilterRegister_TypeDef sFilterRegister[14]; +#else + CAN_FilterRegister_TypeDef sFilterRegister[28]; +#endif /* STM32F10X_CL */ +} CAN_TypeDef; + +/** + * @brief Consumer Electronics Control (CEC) + */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t OAR; + __IO uint32_t PRES; + __IO uint32_t ESR; + __IO uint32_t CSR; + __IO uint32_t TXD; + __IO uint32_t RXD; +} CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; + __IO uint8_t IDR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CR; +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SWTRIGR; + __IO uint32_t DHR12R1; + __IO uint32_t DHR12L1; + __IO uint32_t DHR8R1; + __IO uint32_t DHR12R2; + __IO uint32_t DHR12L2; + __IO uint32_t DHR8R2; + __IO uint32_t DHR12RD; + __IO uint32_t DHR12LD; + __IO uint32_t DHR8RD; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + __IO uint32_t SR; +#endif +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; + __IO uint32_t CR; +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t CNDTR; + __IO uint32_t CPAR; + __IO uint32_t CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t IFCR; +} DMA_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + uint32_t RESERVED8[567]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + uint32_t RESERVED9[9]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; + __IO uint32_t KEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t CR; + __IO uint32_t AR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WRPR; +#ifdef STM32F10X_XL + uint32_t RESERVED1[8]; + __IO uint32_t KEYR2; + uint32_t RESERVED2; + __IO uint32_t SR2; + __IO uint32_t CR2; + __IO uint32_t AR2; +#endif /* STM32F10X_XL */ +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint16_t RDP; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRP0; + __IO uint16_t WRP1; + __IO uint16_t WRP2; + __IO uint16_t WRP3; +} OB_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; + __IO uint32_t SR2; + __IO uint32_t PMEM2; + __IO uint32_t PATT2; + uint32_t RESERVED0; + __IO uint32_t ECCR2; +} FSMC_Bank2_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; + __IO uint32_t SR3; + __IO uint32_t PMEM3; + __IO uint32_t PATT3; + uint32_t RESERVED0; + __IO uint32_t ECCR3; +} FSMC_Bank3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; + __IO uint32_t SR4; + __IO uint32_t PMEM4; + __IO uint32_t PATT4; + __IO uint32_t PIO4; +} FSMC_Bank4_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t CRL; + __IO uint32_t CRH; + __IO uint32_t IDR; + __IO uint32_t ODR; + __IO uint32_t BSRR; + __IO uint32_t BRR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/** + * @brief Alternate Function I/O + */ + +typedef struct +{ + __IO uint32_t EVCR; + __IO uint32_t MAPR; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t MAPR2; +} AFIO_TypeDef; +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t OAR1; + uint16_t RESERVED2; + __IO uint16_t OAR2; + uint16_t RESERVED3; + __IO uint16_t DR; + uint16_t RESERVED4; + __IO uint16_t SR1; + uint16_t RESERVED5; + __IO uint16_t SR2; + uint16_t RESERVED6; + __IO uint16_t CCR; + uint16_t RESERVED7; + __IO uint16_t TRISE; + uint16_t RESERVED8; +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; + __IO uint32_t PR; + __IO uint32_t RLR; + __IO uint32_t SR; +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t APB2RSTR; + __IO uint32_t APB1RSTR; + __IO uint32_t AHBENR; + __IO uint32_t APB2ENR; + __IO uint32_t APB1ENR; + __IO uint32_t BDCR; + __IO uint32_t CSR; + +#ifdef STM32F10X_CL + __IO uint32_t AHBRSTR; + __IO uint32_t CFGR2; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + uint32_t RESERVED0; + __IO uint32_t CFGR2; +#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint16_t CRH; + uint16_t RESERVED0; + __IO uint16_t CRL; + uint16_t RESERVED1; + __IO uint16_t PRLH; + uint16_t RESERVED2; + __IO uint16_t PRLL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRH; + uint16_t RESERVED8; + __IO uint16_t ALRL; + uint16_t RESERVED9; +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; + __IO uint32_t CLKCR; + __IO uint32_t ARG; + __IO uint32_t CMD; + __I uint32_t RESPCMD; + __I uint32_t RESP1; + __I uint32_t RESP2; + __I uint32_t RESP3; + __I uint32_t RESP4; + __IO uint32_t DTIMER; + __IO uint32_t DLEN; + __IO uint32_t DCTRL; + __I uint32_t DCOUNT; + __I uint32_t STA; + __IO uint32_t ICR; + __IO uint32_t MASK; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCNT; + uint32_t RESERVED1[13]; + __IO uint32_t FIFO; +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SR; + uint16_t RESERVED2; + __IO uint16_t DR; + uint16_t RESERVED3; + __IO uint16_t CRCPR; + uint16_t RESERVED4; + __IO uint16_t RXCRCR; + uint16_t RESERVED5; + __IO uint16_t TXCRCR; + uint16_t RESERVED6; + __IO uint16_t I2SCFGR; + uint16_t RESERVED7; + __IO uint16_t I2SPR; + uint16_t RESERVED8; +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SMCR; + uint16_t RESERVED2; + __IO uint16_t DIER; + uint16_t RESERVED3; + __IO uint16_t SR; + uint16_t RESERVED4; + __IO uint16_t EGR; + uint16_t RESERVED5; + __IO uint16_t CCMR1; + uint16_t RESERVED6; + __IO uint16_t CCMR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ARR; + uint16_t RESERVED11; + __IO uint16_t RCR; + uint16_t RESERVED12; + __IO uint16_t CCR1; + uint16_t RESERVED13; + __IO uint16_t CCR2; + uint16_t RESERVED14; + __IO uint16_t CCR3; + uint16_t RESERVED15; + __IO uint16_t CCR4; + uint16_t RESERVED16; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DCR; + uint16_t RESERVED18; + __IO uint16_t DMAR; + uint16_t RESERVED19; +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; + uint16_t RESERVED0; + __IO uint16_t DR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CR1; + uint16_t RESERVED3; + __IO uint16_t CR2; + uint16_t RESERVED4; + __IO uint16_t CR3; + uint16_t RESERVED5; + __IO uint16_t GTPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFR; + __IO uint32_t SR; +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define CEC_BASE (APB1PERIPH_BASE + 0x7800) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) +#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) +#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) + +#define SDIO_BASE (PERIPH_BASE + 0x18000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ + +#define ETH_BASE (AHBPERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ + +#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define BKP ((BKP_TypeDef *) BKP_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) +#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ +#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ +#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ +#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ +#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ + +/*!< PVD level configuration */ +#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ +#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ +#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ +#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ +#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ +#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ +#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ +#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ + +#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR11 register *******************/ +#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR12 register *******************/ +#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR13 register *******************/ +#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR14 register *******************/ +#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR15 register *******************/ +#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR16 register *******************/ +#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR17 register *******************/ +#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_DR18 register ********************/ +#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR19 register *******************/ +#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR20 register *******************/ +#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR21 register *******************/ +#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR22 register *******************/ +#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR23 register *******************/ +#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR24 register *******************/ +#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR25 register *******************/ +#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR26 register *******************/ +#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR27 register *******************/ +#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR28 register *******************/ +#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR29 register *******************/ +#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR30 register *******************/ +#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR31 register *******************/ +#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR32 register *******************/ +#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR33 register *******************/ +#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR34 register *******************/ +#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR35 register *******************/ +#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR36 register *******************/ +#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR37 register *******************/ +#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR38 register *******************/ +#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR39 register *******************/ +#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR40 register *******************/ +#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR41 register *******************/ +#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR42 register *******************/ +#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ +#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ +#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ +#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ +#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ +#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ +#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ +#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ +#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ +#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ +#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ + +#ifdef STM32F10X_CL + #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ + #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ + #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ + #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ +#endif /* STM32F10X_CL */ + +/******************* Bit definition for RCC_CFGR register *******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ + +/*!< ADCPPRE configuration */ +#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ + +#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ + +#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ +#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ + +#ifdef STM32F10X_CL + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ + #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ + + #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ + #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ + #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ + #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#else + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#endif /* STM32F10X_CL */ + +/*!<****************** Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ + +#ifdef STM32F10X_CL + #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ + #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ + #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ + #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ + #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ + #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ +#endif /* STM32F10X_CL */ + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ +#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ +#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ +#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ +#endif + +#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ +#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ +#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ +#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ +#endif + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ + #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ + #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ + #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ + #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ +#endif + +#ifdef STM32F10X_XL + #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ + #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ + #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ +#endif /* STM32F10X_XL */ + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ +#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ +#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ +#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ +#endif + +#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ +#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ + #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ + #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ + #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) + #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) + #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ + #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ + #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ + #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ + #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ + #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ + #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ +#endif + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ + #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ + #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ + #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ + #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ + #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ + #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ + #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ + #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ + #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ +#endif + +#ifdef STM32F10X_CL + #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ +#endif /* STM32F10X_CL */ + +#ifdef STM32F10X_XL + #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ + #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ + #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ +#endif /* STM32F10X_XL */ + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ +#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ +#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) + #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ + #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ +#endif + +#ifdef STM32F10X_CL + #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ + #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ + #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ + #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ +#endif /* STM32F10X_CL */ + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ +#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ +#endif + +#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ +#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ +#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ +#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ +#endif + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ + #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ + #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ + #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ + #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ +#endif + +#ifdef STM32F10X_XL + #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ + #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ + #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ +#endif + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ +#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ +#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ +#endif + +#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ +#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ + #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ + #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ + #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) + #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) + #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ + #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ + #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ + #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ + #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ + #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ + #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ +#endif + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ + #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ + #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ + #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ +#endif + +#ifdef STM32F10X_HD_VL + #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ + #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ + #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ + #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ + #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ + #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ + #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ +#endif /* STM32F10X_HD_VL */ + +#ifdef STM32F10X_CL + #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ +#endif /* STM32F10X_CL */ + +#ifdef STM32F10X_XL + #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ + #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ + #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ +#endif /* STM32F10X_XL */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< RTC congiguration */ +#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ +#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ +#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ + +#ifdef STM32F10X_CL +/******************* Bit definition for RCC_AHBRSTR register ****************/ + #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ + #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ + +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ + +/*!< PREDIV2 configuration */ + #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ + #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ + #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ + +/*!< PLL2MUL configuration */ + #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ + #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ + #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + + #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ + #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ + #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ + #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ + #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ + #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ + #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ + #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ + #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ + +/*!< PLL3MUL configuration */ + #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ + #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ + #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ + + #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ + #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ + #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ + #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ + #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ + #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ + #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ + #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ + #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ + + #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ + #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ + #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ + #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ + #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ +#endif + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function I/O */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ +#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ +#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ +#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ +#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ +#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ +#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ +#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ +#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ +#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ +#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ +#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ +#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ +#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ +#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ +#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ +#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ +#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ +#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ +#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ +#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ +#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ +#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ +#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ +#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ +#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ +#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ +#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ +#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ +#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ +#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ +#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ +#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ +#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ +#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ +#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ +#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ +#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ +#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ +#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ +#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ +#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ +#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ +#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ +#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ +#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ + +#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ +#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ +#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ +#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ +#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ +#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ +#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ +#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ +#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ +#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ +#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ +#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ +#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ +#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ +#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ +#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ +#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ +#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ +#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ +#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ +#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ +#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ +#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ +#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ +#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ +#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ +#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ +#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ +#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ +#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ +#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for AFIO_EVCR register *******************/ +#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ +#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ +#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ + +/*!< PIN configuration */ +#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ +#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ +#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ +#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ +#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ +#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ +#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ +#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ +#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ +#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ +#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ +#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ +#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ +#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ +#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ +#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ + +#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ +#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ +#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ +#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ + +/*!< PORT configuration */ +#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ +#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ +#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ +#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ +#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ + +#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ + +/****************** Bit definition for AFIO_MAPR register *******************/ +#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ +#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ +#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ + +#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +/* USART3_REMAP configuration */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +/*!< TIM1_REMAP configuration */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< TIM2_REMAP configuration */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +/*!< TIM3_REMAP configuration */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ + +/*!< CAN_REMAP configuration */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ + +/*!< SWJ_CFG configuration */ +#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ + +#ifdef STM32F10X_CL +/*!< ETH_REMAP configuration */ + #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ + +/*!< CAN2_REMAP configuration */ + #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ + +/*!< MII_RMII_SEL configuration */ + #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ + +/*!< SPI3_REMAP configuration */ + #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ + +/*!< TIM2ITR1_IREMAP configuration */ + #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ + +/*!< PTP_PPS_REMAP configuration */ + #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ +#endif + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ + +/*!< EXTI1 configuration */ +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ + +/*!< EXTI2 configuration */ +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ + +/*!< EXTI3 configuration */ +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ + +/* EXTI5 configuration */ +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ + +/*!< EXTI6 configuration */ +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ + +/*!< EXTI7 configuration */ +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ + +/*!< EXTI9 configuration */ +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ + +/*!< EXTI10 configuration */ +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ + +/*!< EXTI11 configuration */ +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ + +/* EXTI13 configuration */ +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ + +/*!< EXTI14 configuration */ +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ + +/*!< EXTI15 configuration */ +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/****************** Bit definition for AFIO_MAPR2 register ******************/ +#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ +#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ +#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ +#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ +#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ +#endif + +#ifdef STM32F10X_HD_VL +#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ +#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ +#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ +#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */ +#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */ +#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */ +#endif + +#ifdef STM32F10X_XL +/****************** Bit definition for AFIO_MAPR2 register ******************/ +#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ +#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ +#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ +#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ +#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ +#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ +#endif + +/******************************************************************************/ +/* */ +/* SystemTick */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SysTick_CTRL register *****************/ +#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ +#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ +#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ + +/***************** Bit definition for SysTick_LOAD register *****************/ +#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ + +/***************** Bit definition for SysTick_VAL register ******************/ +#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ + +/***************** Bit definition for SysTick_CALIB register ****************/ +#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ + +/******************************************************************************/ +/* */ +/* Nested Vectored Interrupt Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for NVIC_ISER register *******************/ +#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICER register *******************/ +#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ISPR register *******************/ +#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICPR register *******************/ +#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_IABR register *******************/ +#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ +#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_PRI0 register *******************/ +#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ + +/****************** Bit definition for NVIC_PRI1 register *******************/ +#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ + +/****************** Bit definition for NVIC_PRI2 register *******************/ +#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ + +/****************** Bit definition for NVIC_PRI3 register *******************/ +#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ + +/****************** Bit definition for NVIC_PRI4 register *******************/ +#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ + +/****************** Bit definition for NVIC_PRI5 register *******************/ +#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ + +/****************** Bit definition for NVIC_PRI6 register *******************/ +#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ + +/****************** Bit definition for NVIC_PRI7 register *******************/ +#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ + +/****************** Bit definition for SCB_CPUID register *******************/ +#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ +#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ + +/******************* Bit definition for SCB_ICSR register *******************/ +#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ +#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ +#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ + +/******************* Bit definition for SCB_VTOR register *******************/ +#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ +#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ + +/*!<***************** Bit definition for SCB_AIRCR register *******************/ +#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ +#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ + +#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ +#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +/* prority group configuration */ +#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ +#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ + +#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ +#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ + +/******************* Bit definition for SCB_SCR register ********************/ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ + +/******************** Bit definition for SCB_CCR register *******************/ +#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ +#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ +#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ +#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ +#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ +#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + +/******************* Bit definition for SCB_SHPR register ********************/ +#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + +/****************** Bit definition for SCB_SHCSR register *******************/ +#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ +#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ +#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ +#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ +#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ +#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ +#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ +#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ +#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ +#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ +#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ +#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ +#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ +#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ + +/******************* Bit definition for SCB_CFSR register *******************/ +/*!< MFSR */ +#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ +#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ +#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ +#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ +#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ +/*!< BFSR */ +#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ +#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ +#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ +#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ +#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ +#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ +/*!< UFSR */ +#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ +#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ +#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ +#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ +#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ +#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ + +/******************* Bit definition for SCB_HFSR register *******************/ +#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ +#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ +#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ + +/******************* Bit definition for SCB_DFSR register *******************/ +#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ +#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ +#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ + +/******************* Bit definition for SCB_MMFAR register ******************/ +#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ + +/******************* Bit definition for SCB_BFAR register *******************/ +#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ + +/******************* Bit definition for SCB_afsr register *******************/ +#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ +#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ +#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ +#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ +#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ +#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ +#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ +#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ +#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ +#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ +#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ +#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ +#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ +#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ +#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ +#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ +#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ +#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ +#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ +#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ +#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR1 register *******************/ +#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ +#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR2 register *******************/ +#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR3 register *******************/ +#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/*!<****************** Bit definition for DMA_CCR4 register *******************/ +#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CCR5 register *******************/ +#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/******************* Bit definition for DMA_CCR6 register *******************/ +#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR7 register *******************/ +#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNDTR1 register ******************/ +#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR2 register ******************/ +#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR3 register ******************/ +#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR4 register ******************/ +#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR5 register ******************/ +#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR6 register ******************/ +#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR7 register ******************/ +#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR1 register *******************/ +#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR2 register *******************/ +#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR3 register *******************/ +#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR4 register *******************/ +#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR5 register *******************/ +#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR6 register *******************/ +#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR7 register *******************/ +#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR1 register *******************/ +#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR2 register *******************/ +#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR3 register *******************/ +#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + + +/****************** Bit definition for DMA_CMAR4 register *******************/ +#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR5 register *******************/ +#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR6 register *******************/ +#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR7 register *******************/ +#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint8_t)0x01) /*!< Analog watchdog flag */ +#define ADC_SR_EOC ((uint8_t)0x02) /*!< End of conversion */ +#define ADC_SR_JEOC ((uint8_t)0x04) /*!< Injected channel end of conversion */ +#define ADC_SR_JSTRT ((uint8_t)0x08) /*!< Injected channel Start flag */ +#define ADC_SR_STRT ((uint8_t)0x10) /*!< Regular channel Start flag */ + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ +#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ +#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ +#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ +#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ + +#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ + +#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ + + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ +#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ +#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */ +#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */ +#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ +#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ + +#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ + +#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ +#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ +#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ +#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */ + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */ + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ +#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ +#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ +#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ +#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ +#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ + +#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ +#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ +#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ +#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ + +#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ +#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ +#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ + +#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */ + +/***************** Bit definition for DAC_DHR12R1 register ******************/ +#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L1 register ******************/ +#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R1 register ******************/ +#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12R2 register ******************/ +#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L2 register ******************/ +#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R2 register ******************/ +#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12RD register ******************/ +#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12LD register ******************/ +#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8RD register ******************/ +#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */ + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */ + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */ + +/******************** Bit definition for DAC_SR register ********************/ +#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */ + +/******************************************************************************/ +/* */ +/* CEC */ +/* */ +/******************************************************************************/ +/******************** Bit definition for CEC_CFGR register ******************/ +#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ +#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */ +#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */ +#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */ + +/******************** Bit definition for CEC_OAR register ******************/ +#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */ +#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */ + +/******************** Bit definition for CEC_PRES register ******************/ +#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */ + +/******************** Bit definition for CEC_ESR register ******************/ +#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */ +#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */ +#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */ +#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */ +#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */ +#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */ +#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finished Error */ + +/******************** Bit definition for CEC_CSR register ******************/ +#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */ +#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */ +#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */ +#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */ +#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */ +#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */ +#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */ +#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */ + +/******************** Bit definition for CEC_TXD register ******************/ +#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */ + +/******************** Bit definition for CEC_RXD register ******************/ +#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN ((uint16_t)0x0001) /*!< Counter enable */ +#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!< Update disable */ +#define TIM_CR1_URS ((uint16_t)0x0004) /*!< Update request source */ +#define TIM_CR1_OPM ((uint16_t)0x0008) /*!< One pulse mode */ +#define TIM_CR1_DIR ((uint16_t)0x0010) /*!< Direction */ + +#define TIM_CR1_CMS ((uint16_t)0x0060) /*!< CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!< Bit 0 */ +#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!< Bit 1 */ + +#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!< Auto-reload preload enable */ + +#define TIM_CR1_CKD ((uint16_t)0x0300) /*!< CKD[1:0] bits (clock division) */ +#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +/******************* Bit definition for TIM_CR2 register ********************/ +#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!< Capture/Compare Preloaded Control */ +#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!< Capture/Compare Control Update Selection */ +#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!< Capture/Compare DMA Selection */ + +#define TIM_CR2_MMS ((uint16_t)0x0070) /*!< MMS[2:0] bits (Master Mode Selection) */ +#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!< TI1 Selection */ +#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!< Output Idle state 1 (OC1 output) */ +#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!< Output Idle state 1 (OC1N output) */ +#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!< Output Idle state 2 (OC2 output) */ +#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!< Output Idle state 2 (OC2N output) */ +#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!< Output Idle state 3 (OC3 output) */ +#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!< Output Idle state 3 (OC3N output) */ +#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!< Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCR register *******************/ +#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!< Bit 2 */ + +#define TIM_SMCR_TS ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */ +#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!< Master/slave mode */ + +#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */ +#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!< Bit 1 */ +#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!< Bit 2 */ +#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!< Bit 3 */ + +#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!< External clock enable */ +#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!< External trigger polarity */ + +/******************* Bit definition for TIM_DIER register *******************/ +#define TIM_DIER_UIE ((uint16_t)0x0001) /*!< Update interrupt enable */ +#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */ +#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */ +#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */ +#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */ +#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!< COM interrupt enable */ +#define TIM_DIER_TIE ((uint16_t)0x0040) /*!< Trigger interrupt enable */ +#define TIM_DIER_BIE ((uint16_t)0x0080) /*!< Break interrupt enable */ +#define TIM_DIER_UDE ((uint16_t)0x0100) /*!< Update DMA request enable */ +#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */ +#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */ +#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */ +#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */ +#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!< COM DMA request enable */ +#define TIM_DIER_TDE ((uint16_t)0x4000) /*!< Trigger DMA request enable */ + +/******************** Bit definition for TIM_SR register ********************/ +#define TIM_SR_UIF ((uint16_t)0x0001) /*!< Update interrupt Flag */ +#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt Flag */ +#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt Flag */ +#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt Flag */ +#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt Flag */ +#define TIM_SR_COMIF ((uint16_t)0x0020) /*!< COM interrupt Flag */ +#define TIM_SR_TIF ((uint16_t)0x0040) /*!< Trigger interrupt Flag */ +#define TIM_SR_BIF ((uint16_t)0x0080) /*!< Break interrupt Flag */ +#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!< Capture/Compare 1 Overcapture Flag */ +#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!< Capture/Compare 2 Overcapture Flag */ +#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!< Capture/Compare 3 Overcapture Flag */ +#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!< Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_EGR register ********************/ +#define TIM_EGR_UG ((uint8_t)0x01) /*!< Update Generation */ +#define TIM_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */ +#define TIM_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */ +#define TIM_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */ +#define TIM_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */ +#define TIM_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */ +#define TIM_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation */ +#define TIM_EGR_BG ((uint8_t)0x80) /*!< Break Generation */ + +/****************** Bit definition for TIM_CCMR1 register *******************/ +#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!< Bit 1 */ + +#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */ +#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */ + +#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */ + +#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */ +#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */ + +#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ +#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ + +#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */ +#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */ + +/****************** Bit definition for TIM_CCMR2 register *******************/ +#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!< Bit 1 */ + +#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */ +#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */ + +#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */ + +#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */ +#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */ + +#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ +#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ + +#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */ +#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!< Capture/Compare 1 output enable */ +#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!< Capture/Compare 1 output Polarity */ +#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!< Capture/Compare 1 Complementary output enable */ +#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!< Capture/Compare 1 Complementary output Polarity */ +#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!< Capture/Compare 2 output enable */ +#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!< Capture/Compare 2 output Polarity */ +#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!< Capture/Compare 2 Complementary output enable */ +#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!< Capture/Compare 2 Complementary output Polarity */ +#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!< Capture/Compare 3 output enable */ +#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!< Capture/Compare 3 output Polarity */ +#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!< Capture/Compare 3 Complementary output enable */ +#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!< Capture/Compare 3 Complementary output Polarity */ +#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!< Capture/Compare 4 output enable */ +#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!< Capture/Compare 4 output Polarity */ +#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!< Capture/Compare 4 Complementary output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */ + +/******************* Bit definition for TIM_ARR register ********************/ +#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */ + +/******************* Bit definition for TIM_RCR register ********************/ +#define TIM_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value */ + +/******************* Bit definition for TIM_CCR1 register *******************/ +#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CCR2 register *******************/ +#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CCR3 register *******************/ +#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CCR4 register *******************/ +#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!< Bit 7 */ + +#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */ +#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */ +#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */ +#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!< Break enable */ +#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!< Break Polarity */ +#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!< Automatic Output enable */ +#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!< Main Output enable */ + +/******************* Bit definition for TIM_DCR register ********************/ +#define TIM_DCR_DBA ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */ +#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!< Bit 4 */ + +#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!< Bit 1 */ +#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!< Bit 2 */ +#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!< Bit 3 */ +#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!< Bit 4 */ + +/******************* Bit definition for TIM_DMAR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */ + +/******************************************************************************/ +/* */ +/* Real-Time Clock */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CRH register ********************/ +#define RTC_CRH_SECIE ((uint8_t)0x01) /*!< Second Interrupt Enable */ +#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!< Alarm Interrupt Enable */ +#define RTC_CRH_OWIE ((uint8_t)0x04) /*!< OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CRL register ********************/ +#define RTC_CRL_SECF ((uint8_t)0x01) /*!< Second Flag */ +#define RTC_CRL_ALRF ((uint8_t)0x02) /*!< Alarm Flag */ +#define RTC_CRL_OWF ((uint8_t)0x04) /*!< OverfloW Flag */ +#define RTC_CRL_RSF ((uint8_t)0x08) /*!< Registers Synchronized Flag */ +#define RTC_CRL_CNF ((uint8_t)0x10) /*!< Configuration Flag */ +#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!< RTC operation OFF */ + +/******************* Bit definition for RTC_PRLH register *******************/ +#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!< RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PRLL register *******************/ +#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!< RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!< RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!< RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Low */ + +/******************* Bit definition for RTC_ALRH register *******************/ +#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm High */ + +/******************* Bit definition for RTC_ALRL register *******************/ +#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm Low */ + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PR register ********************/ +#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ + +/******************* Bit definition for IWDG_RLR register *******************/ +#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ + +/******************* Bit definition for IWDG_SR register ********************/ +#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ +#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ + +/******************************************************************************/ +/* */ +/* Window WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CR register ********************/ +#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */ +#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */ +#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */ +#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */ +#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */ +#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */ +#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */ + +#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */ + +/******************* Bit definition for WWDG_CFR register *******************/ +#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */ +#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */ + +#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */ +#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */ + +#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_SR register ********************/ +#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Flexible Static Memory Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for FSMC_BCR1 register *******************/ +#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BCR2 register *******************/ +#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BCR3 register *******************/ +#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */ +#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BCR4 register *******************/ +#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BTR1 register ******************/ +#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BTR2 register *******************/ +#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/******************* Bit definition for FSMC_BTR3 register *******************/ +#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BTR4 register *******************/ +#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR1 register ******************/ +#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR2 register ******************/ +#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/ +#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR3 register ******************/ +#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR4 register ******************/ +#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_PCR2 register *******************/ +#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!< Memory type */ + +#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */ +#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/****************** Bit definition for FSMC_PCR3 register *******************/ +#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!< Memory type */ + +#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ +#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/****************** Bit definition for FSMC_PCR4 register *******************/ +#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */ + +#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ +#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/******************* Bit definition for FSMC_SR2 register *******************/ +#define FSMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +#define FSMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +#define FSMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +#define FSMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ +#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ + +/******************* Bit definition for FSMC_SR3 register *******************/ +#define FSMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +#define FSMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +#define FSMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +#define FSMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ +#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ + +/******************* Bit definition for FSMC_SR4 register *******************/ +#define FSMC_SR4_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +#define FSMC_SR4_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +#define FSMC_SR4_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +#define FSMC_SR4_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ +#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ + +/****************** Bit definition for FSMC_PMEM2 register ******************/ +#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */ +#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */ +#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */ +#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ +#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PMEM3 register ******************/ +#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */ +#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */ +#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */ +#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ +#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PMEM4 register ******************/ +#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */ +#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */ +#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */ +#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ +#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PATT2 register ******************/ +#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */ +#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ +#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ +#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ +#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PATT3 register ******************/ +#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */ +#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ +#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ +#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ +#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PATT4 register ******************/ +#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */ +#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ +#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ +#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ +#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PIO4 register *******************/ +#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!< IOSET4[7:0] bits (I/O 4 setup time) */ +#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */ +#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */ +#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ +#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_ECCR2 register ******************/ +#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ + +/****************** Bit definition for FSMC_ECCR3 register ******************/ +#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ + +/******************************************************************************/ +/* */ +/* SD host Interface */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for SDIO_POWER register ******************/ +#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */ +#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */ + +/****************** Bit definition for SDIO_CLKCR register ******************/ +#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */ +#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */ +#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */ +#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */ + +#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ +#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */ +#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */ + +#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */ +#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */ + +/******************* Bit definition for SDIO_ARG register *******************/ +#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */ + +/******************* Bit definition for SDIO_CMD register *******************/ +#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */ + +#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */ +#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */ +#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */ + +#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */ +#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ +#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */ +#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */ +#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */ +#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */ +#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */ + +/***************** Bit definition for SDIO_RESPCMD register *****************/ +#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */ + +/****************** Bit definition for SDIO_RESP0 register ******************/ +#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP1 register ******************/ +#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP2 register ******************/ +#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP3 register ******************/ +#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP4 register ******************/ +#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_DTIMER register *****************/ +#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */ + +/****************** Bit definition for SDIO_DLEN register *******************/ +#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */ + +/****************** Bit definition for SDIO_DCTRL register ******************/ +#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */ +#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */ +#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */ +#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */ + +#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */ +#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */ +#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */ +#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */ +#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */ + +/****************** Bit definition for SDIO_DCOUNT register *****************/ +#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */ + +/****************** Bit definition for SDIO_STA register ********************/ +#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */ +#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */ +#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */ +#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */ +#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */ +#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */ +#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */ +#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */ +#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */ +#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */ +#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */ +#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */ +#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */ +#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */ +#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ +#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ +#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */ +#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */ +#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */ +#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */ +#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */ +#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */ +#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */ +#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */ + +/******************* Bit definition for SDIO_ICR register *******************/ +#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */ +#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */ +#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */ +#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */ +#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */ +#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */ +#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */ +#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */ +#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */ +#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */ +#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */ +#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */ +#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */ + +/****************** Bit definition for SDIO_MASK register *******************/ +#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */ +#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */ +#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */ +#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */ +#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */ +#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */ +#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */ +#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */ +#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */ +#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */ +#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */ +#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */ +#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */ +#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */ +#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */ +#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */ +#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */ +#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */ +#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */ +#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */ +#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */ +#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */ + +/***************** Bit definition for SDIO_FIFOCNT register *****************/ +#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */ + +/****************** Bit definition for SDIO_FIFO register *******************/ +#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */ + +/******************************************************************************/ +/* */ +/* USB Device FS */ +/* */ +/******************************************************************************/ + +/*!< Endpoint-specific registers */ +/******************* Bit definition for USB_EP0R register *******************/ +#define USB_EP0R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP1R register *******************/ +#define USB_EP1R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP2R register *******************/ +#define USB_EP2R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP3R register *******************/ +#define USB_EP3R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP4R register *******************/ +#define USB_EP4R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP5R register *******************/ +#define USB_EP5R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP6R register *******************/ +#define USB_EP6R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP7R register *******************/ +#define USB_EP7R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/*!< Common registers */ +/******************* Bit definition for USB_CNTR register *******************/ +#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB Reset */ +#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power down */ +#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */ +#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force suspend */ +#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< Resume request */ +#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */ +#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */ +#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */ +#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */ +#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< Error Interrupt Mask */ +#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */ + +/******************* Bit definition for USB_ISTR register *******************/ +#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */ +#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */ +#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */ +#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */ +#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< USB RESET request */ +#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< Suspend mode request */ +#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */ +#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< Error */ +#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */ +#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct Transfer */ + +/******************* Bit definition for USB_FNR register ********************/ +#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */ +#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */ +#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */ +#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< Receive Data - Line Status */ +#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< Receive Data + Line Status */ + +/****************** Bit definition for USB_DADDR register *******************/ +#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */ +#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!< Bit 0 */ +#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!< Bit 1 */ +#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!< Bit 2 */ +#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!< Bit 3 */ +#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!< Bit 4 */ +#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!< Bit 5 */ +#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!< Bit 6 */ + +#define USB_DADDR_EF ((uint8_t)0x80) /*!< Enable Function */ + +/****************** Bit definition for USB_BTABLE register ******************/ +#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!< Buffer Table */ + +/*!< Buffer descriptor table */ +/***************** Bit definition for USB_ADDR0_TX register *****************/ +#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_TX register *****************/ +#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_TX register *****************/ +#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_TX register *****************/ +#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_TX register *****************/ +#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_TX register *****************/ +#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_TX register *****************/ +#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_TX register *****************/ +#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_TX register ****************/ +#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */ + +/***************** Bit definition for USB_COUNT1_TX register ****************/ +#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */ + +/***************** Bit definition for USB_COUNT2_TX register ****************/ +#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */ + +/***************** Bit definition for USB_COUNT3_TX register ****************/ +#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */ + +/***************** Bit definition for USB_COUNT4_TX register ****************/ +#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */ + +/***************** Bit definition for USB_COUNT5_TX register ****************/ +#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */ + +/***************** Bit definition for USB_COUNT6_TX register ****************/ +#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */ + +/***************** Bit definition for USB_COUNT7_TX register ****************/ +#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ +#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */ + +/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ +#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */ + +/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ +#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */ + +/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ +#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */ + +/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ +#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */ + +/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ +#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */ + +/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ +#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */ + +/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ +#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */ + +/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ +#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */ + +/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ +#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */ + +/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ +#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */ + +/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ +#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */ + +/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ +#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */ + +/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ +#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */ + +/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ +#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */ + +/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ +#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_ADDR0_RX register *****************/ +#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_RX register *****************/ +#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_RX register *****************/ +#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_RX register *****************/ +#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_RX register *****************/ +#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_RX register *****************/ +#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_RX register *****************/ +#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_RX register *****************/ +#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_RX register ****************/ +#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT1_RX register ****************/ +#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT2_RX register ****************/ +#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT3_RX register ****************/ +#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT4_RX register ****************/ +#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT5_RX register ****************/ +#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT6_RX register ****************/ +#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT7_RX register ****************/ +#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ +#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ +#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ +#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ +#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ +#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ +#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ +#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ +#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ +#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ +#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ +#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ +#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ +#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ +#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ +#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ +#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/******************************************************************************/ +/* */ +/* Controller Area Network */ +/* */ +/******************************************************************************/ + +/*!< CAN control and status registers */ +/******************* Bit definition for CAN_MCR register ********************/ +#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!< Initialization Request */ +#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!< Sleep Mode Request */ +#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!< Transmit FIFO Priority */ +#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!< Receive FIFO Locked Mode */ +#define CAN_MCR_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */ +#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */ +#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */ +#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */ +#define CAN_MCR_RESET ((uint16_t)0x8000) /*!< CAN software master reset */ + +/******************* Bit definition for CAN_MSR register ********************/ +#define CAN_MSR_INAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */ +#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */ +#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!< Error Interrupt */ +#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!< Wakeup Interrupt */ +#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */ +#define CAN_MSR_TXM ((uint16_t)0x0100) /*!< Transmit Mode */ +#define CAN_MSR_RXM ((uint16_t)0x0200) /*!< Receive Mode */ +#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!< Last Sample Point */ +#define CAN_MSR_RX ((uint16_t)0x0800) /*!< CAN Rx Signal */ + +/******************* Bit definition for CAN_TSR register ********************/ +#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */ +#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */ +#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */ +#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */ +#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */ +#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */ +#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */ +#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */ +#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */ +#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */ +#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */ +#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */ +#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */ +#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */ +#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */ +#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */ + +#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */ +#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */ +#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */ +#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */ + +#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */ +#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RF0R register *******************/ +#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!< FIFO 0 Message Pending */ +#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!< FIFO 0 Full */ +#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!< FIFO 0 Overrun */ +#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!< Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RF1R register *******************/ +#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!< FIFO 1 Message Pending */ +#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!< FIFO 1 Full */ +#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!< FIFO 1 Overrun */ +#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!< Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_IER register *******************/ +#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */ +#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */ +#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */ +#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */ +#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */ +#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */ +#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */ +#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */ +#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */ +#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ESR register *******************/ +#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */ +#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */ +#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */ + +#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */ +#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + +#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */ + +/******************* Bit definition for CAN_BTR register ********************/ +#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */ +#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */ +#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */ +#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */ +#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */ +#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!< Silent Mode */ + +/*!< Mailbox registers */ +/****************** Bit definition for CAN_TI0R register ********************/ +#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TDT0R register *******************/ +#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/****************** Bit definition for CAN_TDL0R register *******************/ +#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/****************** Bit definition for CAN_TDH0R register *******************/ +#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_TI1R register *******************/ +#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT1R register ******************/ +#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_TDL1R register ******************/ +#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_TDH1R register ******************/ +#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_TI2R register *******************/ +#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ +#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT2R register ******************/ +#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_TDL2R register ******************/ +#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_TDH2R register ******************/ +#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_RI0R register *******************/ +#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT0R register ******************/ +#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ +#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_RDL0R register ******************/ +#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_RDH0R register ******************/ +#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_RI1R register *******************/ +#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ +#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT1R register ******************/ +#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ +#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_RDL1R register ******************/ +#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_RDH1R register ******************/ +#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/*!< CAN filter registers */ +/******************* Bit definition for CAN_FMR register ********************/ +#define CAN_FMR_FINIT ((uint8_t)0x01) /*!< Filter Init Mode */ + +/******************* Bit definition for CAN_FM1R register *******************/ +#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!< Filter Mode */ +#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */ +#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */ +#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */ +#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */ +#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */ +#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */ +#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */ +#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */ +#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */ +#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */ +#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */ +#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */ +#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */ +#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */ + +/******************* Bit definition for CAN_FS1R register *******************/ +#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */ +#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */ +#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */ +#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */ +#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */ +#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */ +#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */ +#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */ +#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */ +#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */ +#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */ +#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */ +#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */ +#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */ +#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */ + +/****************** Bit definition for CAN_FFA1R register *******************/ +#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!< Filter FIFO Assignment */ +#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!< Filter FIFO Assignment for Filter 0 */ +#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!< Filter FIFO Assignment for Filter 1 */ +#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!< Filter FIFO Assignment for Filter 2 */ +#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!< Filter FIFO Assignment for Filter 3 */ +#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!< Filter FIFO Assignment for Filter 4 */ +#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!< Filter FIFO Assignment for Filter 5 */ +#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!< Filter FIFO Assignment for Filter 6 */ +#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!< Filter FIFO Assignment for Filter 7 */ +#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!< Filter FIFO Assignment for Filter 8 */ +#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!< Filter FIFO Assignment for Filter 9 */ +#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!< Filter FIFO Assignment for Filter 10 */ +#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!< Filter FIFO Assignment for Filter 11 */ +#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!< Filter FIFO Assignment for Filter 12 */ +#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!< Filter FIFO Assignment for Filter 13 */ + +/******************* Bit definition for CAN_FA1R register *******************/ +#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!< Filter Active */ +#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!< Filter 0 Active */ +#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!< Filter 1 Active */ +#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!< Filter 2 Active */ +#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!< Filter 3 Active */ +#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!< Filter 4 Active */ +#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!< Filter 5 Active */ +#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!< Filter 6 Active */ +#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!< Filter 7 Active */ +#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!< Filter 8 Active */ +#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!< Filter 9 Active */ +#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!< Filter 10 Active */ +#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!< Filter 11 Active */ +#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!< Filter 12 Active */ +#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!< Filter 13 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */ +#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */ +#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */ + +#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ +#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */ +#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */ +#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */ + +#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */ +#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */ +#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */ +#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */ +#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */ +#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */ +#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ +#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CR2 register ********************/ +#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */ +#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */ +#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */ +#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_SR register ********************/ +#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */ +#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */ +#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */ +#define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */ +#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */ +#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */ +#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */ +#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */ + +/******************** Bit definition for SPI_DR register ********************/ +#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ + +/******************* Bit definition for SPI_CRCPR register ******************/ +#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ + +/****************** Bit definition for SPI_RXCRCR register ******************/ +#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */ + +/****************** Bit definition for SPI_TXCRCR register ******************/ +#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */ + +/****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!< DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!< Bit 0 */ +#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!< Bit 1 */ + +#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!< I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!< I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!< I2S Enable */ +#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!< I2S mode selection */ + +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */ +#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!< Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!< Master Clock Output Enable */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CR1 register ********************/ +#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ +#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */ +#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */ +#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */ +#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */ +#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */ +#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */ +#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */ +#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */ +#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */ +#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */ +#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */ +#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */ +#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */ + +/******************* Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */ + +#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */ +#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */ +#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */ +#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */ +#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */ + +/******************* Bit definition for I2C_OAR1 register *******************/ +#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */ +#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */ + +#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */ +#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */ +#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */ + +#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OAR2 register *******************/ +#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */ +#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */ + +/******************** Bit definition for I2C_DR register ********************/ +#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */ + +/******************* Bit definition for I2C_SR1 register ********************/ +#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */ +#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */ +#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */ +#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */ +#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */ +#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */ +#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */ +#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */ +#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */ +#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */ +#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */ +#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */ +#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */ +#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */ + +/******************* Bit definition for I2C_SR2 register ********************/ +#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */ +#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */ +#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */ +#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */ +#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */ +#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */ +#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */ +#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */ + +/******************* Bit definition for I2C_CCR register ********************/ +#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */ +#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */ + +/****************** Bit definition for I2C_TRISE register *******************/ +#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* */ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for USART_SR register *******************/ +#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */ +#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */ +#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */ +#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */ +#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */ +#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */ +#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */ +#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */ +#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */ +#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */ + +/******************* Bit definition for USART_DR register *******************/ +#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CR1 register *******************/ +#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */ +#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */ +#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */ +#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */ +#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */ +#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */ +#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */ +#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */ +#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */ +#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */ +#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */ +#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */ +#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< USART Oversmapling 8-bits */ + +/****************** Bit definition for USART_CR2 register *******************/ +#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */ +#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */ +#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */ +#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */ +#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */ +#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */ + +#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */ +#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */ + +/****************** Bit definition for USART_CR3 register *******************/ +#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */ +#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */ +#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */ +#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */ +#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */ +#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */ +#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */ +#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */ +#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */ +#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */ +#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */ +#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One Bit method */ + +/****************** Bit definition for USART_GTPR register ******************/ +#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ +#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */ + +#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for DBGMCU_IDCODE register *****************/ +#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */ + +#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ +#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */ +#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */ +#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */ +#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */ +#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */ +#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */ +#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */ +#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */ +#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */ + +/****************** Bit definition for DBGMCU_CR register *******************/ +#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */ +#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ +#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ +#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */ + +#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ +#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */ +#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */ +#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!< Debug CAN2 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!< Debug TIM12 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!< Debug TIM13 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!< Debug TIM14 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!< Debug TIM9 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!< Debug TIM10 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!< Debug TIM11 stopped when Core is halted */ + +/******************************************************************************/ +/* */ +/* FLASH and Option Bytes Registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACR register ******************/ +#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */ +#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */ +#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */ +#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */ + +#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */ +#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */ +#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!< Prefetch Buffer Status */ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ + +/***************** Bit definition for FLASH_OPTKEYR register ****************/ +#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ + +/****************** Bit definition for FLASH_SR register *******************/ +#define FLASH_SR_BSY ((uint8_t)0x01) /*!< Busy */ +#define FLASH_SR_PGERR ((uint8_t)0x04) /*!< Programming Error */ +#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!< Write Protection Error */ +#define FLASH_SR_EOP ((uint8_t)0x20) /*!< End of operation */ + +/******************* Bit definition for FLASH_CR register *******************/ +#define FLASH_CR_PG ((uint16_t)0x0001) /*!< Programming */ +#define FLASH_CR_PER ((uint16_t)0x0002) /*!< Page Erase */ +#define FLASH_CR_MER ((uint16_t)0x0004) /*!< Mass Erase */ +#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */ +#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */ +#define FLASH_CR_STRT ((uint16_t)0x0040) /*!< Start */ +#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!< Lock */ +#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */ +#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!< Error Interrupt Enable */ +#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!< End of operation interrupt enable */ + +/******************* Bit definition for FLASH_AR register *******************/ +#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!< Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!< Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!< User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!< nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */ +#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!< BFB2 */ + +/****************** Bit definition for FLASH_WRPR register ******************/ +#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for FLASH_RDP register *******************/ +#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ +#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRP0 register ******************/ +#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP1 register ******************/ +#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP2 register ******************/ +#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP3 register ******************/ +#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + +#ifdef STM32F10X_CL +/******************************************************************************/ +/* Ethernet MAC Registers bits definitions */ +/******************************************************************************/ +/* Bit definition for Ethernet MAC Control Register register */ +#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ +#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ +#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ + #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ + #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ + #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ + #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ + #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ + #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ + #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ + #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ +#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ +#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ +#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ +#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ +#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ +#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ +#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ +#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ +#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling + a transmission attempt during retries after a collision: 0 =< r <2^k */ + #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ + #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ + #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ + #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ +#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ +#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ +#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ + +/* Bit definition for Ethernet MAC Frame Filter Register */ +#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ +#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ +#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ +#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ +#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ + #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ + #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ + #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ +#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ +#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ +#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ +#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ +#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ +#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ + +/* Bit definition for Ethernet MAC Hash Table High Register */ +#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ + +/* Bit definition for Ethernet MAC Hash Table Low Register */ +#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ + +/* Bit definition for Ethernet MAC MII Address Register */ +#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ +#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ +#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ + #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ + #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ + #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ +#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ +#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ + +/* Bit definition for Ethernet MAC MII Data Register */ +#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ + +/* Bit definition for Ethernet MAC Flow Control Register */ +#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ +#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ +#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ + #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ + #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ + #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ + #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ +#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ +#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ +#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ +#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ + +/* Bit definition for Ethernet MAC VLAN Tag Register */ +#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ +#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ + +/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ +#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ +/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. + Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ +/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask + Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask + Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask + Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask + Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - + RSVD - Filter1 Command - RSVD - Filter0 Command + Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset + Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 + Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ + +/* Bit definition for Ethernet MAC PMT Control and Status Register */ +#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ +#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ +#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ +#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ +#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ +#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ + +/* Bit definition for Ethernet MAC Status Register */ +#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ +#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ +#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ +#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ +#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ + +/* Bit definition for Ethernet MAC Interrupt Mask Register */ +#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ +#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ + +/* Bit definition for Ethernet MAC Address0 High Register */ +#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ + +/* Bit definition for Ethernet MAC Address0 Low Register */ +#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ + +/* Bit definition for Ethernet MAC Address1 High Register */ +#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ +#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ +#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ + #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ + +/* Bit definition for Ethernet MAC Address1 Low Register */ +#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ + +/* Bit definition for Ethernet MAC Address2 High Register */ +#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ +#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ +#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ + #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ + +/* Bit definition for Ethernet MAC Address2 Low Register */ +#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ + +/* Bit definition for Ethernet MAC Address3 High Register */ +#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ +#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ +#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ + #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ + +/* Bit definition for Ethernet MAC Address3 Low Register */ +#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ + +/******************************************************************************/ +/* Ethernet MMC Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet MMC Contol Register */ +#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ +#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ +#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ +#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ + +/* Bit definition for Ethernet MMC Receive Interrupt Register */ +#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmit Interrupt Register */ +#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ +#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ +#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ +#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ +#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ +#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ + +/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ +#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ + +/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ +#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ + +/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ +#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ + +/******************************************************************************/ +/* Ethernet PTP Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet PTP Time Stamp Contol Register */ +#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ +#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ +#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ +#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ +#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ +#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ + +/* Bit definition for Ethernet PTP Sub-Second Increment Register */ +#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ + +/* Bit definition for Ethernet PTP Time Stamp High Register */ +#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ + +/* Bit definition for Ethernet PTP Time Stamp Low Register */ +#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ +#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ + +/* Bit definition for Ethernet PTP Time Stamp High Update Register */ +#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ + +/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ +#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ +#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ + +/* Bit definition for Ethernet PTP Time Stamp Addend Register */ +#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ + +/* Bit definition for Ethernet PTP Target Time High Register */ +#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ + +/* Bit definition for Ethernet PTP Target Time Low Register */ +#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ + +/******************************************************************************/ +/* Ethernet DMA Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet DMA Bus Mode Register */ +#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ +#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ +#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ +#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ + #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ + #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ + #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ + #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ +#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ + #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ + #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ + #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ + #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ +#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ +#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ + +/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ +#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ + +/* Bit definition for Ethernet DMA Receive Poll Demand Register */ +#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ + +/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ +#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ + +/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ +#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ + +/* Bit definition for Ethernet DMA Status Register */ +#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ + /* combination with EBS[2:0] for GetFlagStatus function */ + #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ + #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ + #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ + #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ + #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ + #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ + #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ + #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ + #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ + #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ + #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ + #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ + #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ + #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ + #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ + +/* Bit definition for Ethernet DMA Operation Mode Register */ +#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ +#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ +#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ +#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ +#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ +#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ + #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ + #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ + #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ + #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ + #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ + #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ + #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ + #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ +#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ +#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ +#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ + #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ + #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ + #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ + #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ +#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ +#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ + +/* Bit definition for Ethernet DMA Interrupt Enable Register */ +#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ +#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ +#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ +#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ +#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ +#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ +#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ +#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ +#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ +#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ +#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ +#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ +#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ +#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ +#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ + +/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ +#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ +#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ +#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ + +/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ +#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ + +/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ +#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ + +/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ +#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ + +/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ +#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ +#endif /* STM32F10X_CL */ + +/** + * @} + */ + + /** + * @} + */ + +#ifdef USE_STDPERIPH_DRIVER + #include "stm32f10x_conf.h" +#endif + +/** @addtogroup Exported_macro + * @{ + */ + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_H */ + +/** + * @} + */ + + /** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x_conf.h b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x_conf.h new file mode 100644 index 0000000..a2457c7 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x_conf.h @@ -0,0 +1,77 @@ +/** + ****************************************************************************** + * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h + * @author MCD Application Team + * @version V3.4.0 + * @date 10/15/2010 + * @brief Library configuration file. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CONF_H +#define __STM32F10x_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +/* #include "stm32f10x_adc.h" */ +/* #include "stm32f10x_bkp.h" */ +/* #include "stm32f10x_can.h" */ +#include "stm32f10x_cec.h" +/* #include "stm32f10x_crc.h" */ +/* #include "stm32f10x_dac.h" */ +/* #include "stm32f10x_dbgmcu.h" */ +#include "stm32f10x_dma.h" +#include "stm32f10x_exti.h" +#include "stm32f10x_flash.h" +#include "stm32f10x_fsmc.h" +#include "stm32f10x_gpio.h" +#include "stm32f10x_i2c.h" +/* #include "stm32f10x_iwdg.h" */ +#include "stm32f10x_pwr.h" +#include "stm32f10x_rcc.h" +/* #include "stm32f10x_rtc.h" */ +/* #include "stm32f10x_sdio.h" */ +#include "stm32f10x_spi.h" +#include "stm32f10x_tim.h" +#include "stm32f10x_usart.h" +/* #include "stm32f10x_wwdg.h" */ +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F10x_CONF_H */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c new file mode 100644 index 0000000..317599f --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c @@ -0,0 +1,1094 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +/* #define SYSCLK_FREQ_72MHz 72000000 */ /* ECONAIS: remain with the HSI clock */ +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depedning on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h new file mode 100644 index 0000000..739f332 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h @@ -0,0 +1,98 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F10X_H +#define __SYSTEM_STM32F10X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F10x_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F10x_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F10X_H */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/misc.h b/Project/econais/STM32_Libs/F1/inc/misc.h new file mode 100644 index 0000000..7d401ca --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/misc.h @@ -0,0 +1,220 @@ +/** + ****************************************************************************** + * @file misc.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the miscellaneous + * firmware library functions (add-on to CMSIS functions). + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MISC_H +#define __MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/** @defgroup MISC_Exported_Types + * @{ + */ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be a value of @ref IRQn_Type + (For the complete STM32 Devices IRQ Channels list, please + refer to stm32f10x.h file) */ + + uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup NVIC_Priority_Table + * @{ + */ + +/** +@code + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function + ============================================================================================================================ + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ============================================================================================================================ + NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority + | | | 4 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority + | | | 3 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bits for subpriority + ============================================================================================================================ +@endcode +*/ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Constants + * @{ + */ + +/** @defgroup Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @defgroup System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) + +/** + * @} + */ + +/** @defgroup SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Functions + * @{ + */ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_adc.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_adc.h new file mode 100644 index 0000000..d1b2653 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_adc.h @@ -0,0 +1,483 @@ +/** + ****************************************************************************** + * @file stm32f10x_adc.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the ADC firmware + * library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_ADC_H +#define __STM32F10x_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/** @defgroup ADC_Exported_Types + * @{ + */ + +/** + * @brief ADC Init structure definition + */ + +typedef struct +{ + uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ +}ADC_InitTypeDef; +/** + * @} + */ + +/** @defgroup ADC_Exported_Constants + * @{ + */ + +#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ + ((PERIPH) == ADC2) || \ + ((PERIPH) == ADC3)) + +#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ + ((PERIPH) == ADC3)) + +/** @defgroup ADC_mode + * @{ + */ + +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ + ((MODE) == ADC_Mode_RegInjecSimult) || \ + ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \ + ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \ + ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \ + ((MODE) == ADC_Mode_InjecSimult) || \ + ((MODE) == ADC_Mode_RegSimult) || \ + ((MODE) == ADC_Mode_FastInterl) || \ + ((MODE) == ADC_Mode_SlowInterl) || \ + ((MODE) == ADC_Mode_AlterTrig)) +/** + * @} + */ + +/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion + * @{ + */ + +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */ + +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */ + +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */ + +#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_None) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) +/** + * @} + */ + +/** @defgroup ADC_data_align + * @{ + */ + +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ + ((ALIGN) == ADC_DataAlign_Left)) +/** + * @} + */ + +/** @defgroup ADC_channels + * @{ + */ + +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) + +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ + ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ + ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ + ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ + ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \ + ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \ + ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \ + ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \ + ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) +/** + * @} + */ + +/** @defgroup ADC_sampling_time + * @{ + */ + +#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) +#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) +#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) +#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) +#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) +#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) +#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) +#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \ + ((TIME) == ADC_SampleTime_7Cycles5) || \ + ((TIME) == ADC_SampleTime_13Cycles5) || \ + ((TIME) == ADC_SampleTime_28Cycles5) || \ + ((TIME) == ADC_SampleTime_41Cycles5) || \ + ((TIME) == ADC_SampleTime_55Cycles5) || \ + ((TIME) == ADC_SampleTime_71Cycles5) || \ + ((TIME) == ADC_SampleTime_239Cycles5)) +/** + * @} + */ + +/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion + * @{ + */ + +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */ + +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */ + +#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */ + +#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) +/** + * @} + */ + +/** @defgroup ADC_injected_channel_selection + * @{ + */ + +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) +#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ + ((CHANNEL) == ADC_InjectedChannel_2) || \ + ((CHANNEL) == ADC_InjectedChannel_3) || \ + ((CHANNEL) == ADC_InjectedChannel_4)) +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_selection + * @{ + */ + +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_None)) +/** + * @} + */ + +/** @defgroup ADC_interrupts_definition + * @{ + */ + +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) + +#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ + ((IT) == ADC_IT_JEOC)) +/** + * @} + */ + +/** @defgroup ADC_flags_definition + * @{ + */ + +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) +#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00)) +#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ + ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \ + ((FLAG) == ADC_FLAG_STRT)) +/** + * @} + */ + +/** @defgroup ADC_thresholds + * @{ + */ + +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) + +/** + * @} + */ + +/** @defgroup ADC_injected_offset + * @{ + */ + +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) + +/** + * @} + */ + +/** @defgroup ADC_injected_length + * @{ + */ + +#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) + +/** + * @} + */ + +/** @defgroup ADC_injected_rank + * @{ + */ + +#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) + +/** + * @} + */ + + +/** @defgroup ADC_regular_length + * @{ + */ + +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) +/** + * @} + */ + +/** @defgroup ADC_regular_rank + * @{ + */ + +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) + +/** + * @} + */ + +/** @defgroup ADC_regular_discontinuous_mode_number + * @{ + */ + +#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions + * @{ + */ + +void ADC_DeInit(ADC_TypeDef* ADCx); +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_StartCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); +uint32_t ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_ADC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_bkp.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_bkp.h new file mode 100644 index 0000000..b620753 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_bkp.h @@ -0,0 +1,195 @@ +/** + ****************************************************************************** + * @file stm32f10x_bkp.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the BKP firmware + * library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_BKP_H +#define __STM32F10x_BKP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup BKP + * @{ + */ + +/** @defgroup BKP_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Constants + * @{ + */ + +/** @defgroup Tamper_Pin_active_level + * @{ + */ + +#define BKP_TamperPinLevel_High ((uint16_t)0x0000) +#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) +#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ + ((LEVEL) == BKP_TamperPinLevel_Low)) +/** + * @} + */ + +/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin + * @{ + */ + +#define BKP_RTCOutputSource_None ((uint16_t)0x0000) +#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) +#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) +#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) +#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ + ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ + ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ + ((SOURCE) == BKP_RTCOutputSource_Second)) +/** + * @} + */ + +/** @defgroup Data_Backup_Register + * @{ + */ + +#define BKP_DR1 ((uint16_t)0x0004) +#define BKP_DR2 ((uint16_t)0x0008) +#define BKP_DR3 ((uint16_t)0x000C) +#define BKP_DR4 ((uint16_t)0x0010) +#define BKP_DR5 ((uint16_t)0x0014) +#define BKP_DR6 ((uint16_t)0x0018) +#define BKP_DR7 ((uint16_t)0x001C) +#define BKP_DR8 ((uint16_t)0x0020) +#define BKP_DR9 ((uint16_t)0x0024) +#define BKP_DR10 ((uint16_t)0x0028) +#define BKP_DR11 ((uint16_t)0x0040) +#define BKP_DR12 ((uint16_t)0x0044) +#define BKP_DR13 ((uint16_t)0x0048) +#define BKP_DR14 ((uint16_t)0x004C) +#define BKP_DR15 ((uint16_t)0x0050) +#define BKP_DR16 ((uint16_t)0x0054) +#define BKP_DR17 ((uint16_t)0x0058) +#define BKP_DR18 ((uint16_t)0x005C) +#define BKP_DR19 ((uint16_t)0x0060) +#define BKP_DR20 ((uint16_t)0x0064) +#define BKP_DR21 ((uint16_t)0x0068) +#define BKP_DR22 ((uint16_t)0x006C) +#define BKP_DR23 ((uint16_t)0x0070) +#define BKP_DR24 ((uint16_t)0x0074) +#define BKP_DR25 ((uint16_t)0x0078) +#define BKP_DR26 ((uint16_t)0x007C) +#define BKP_DR27 ((uint16_t)0x0080) +#define BKP_DR28 ((uint16_t)0x0084) +#define BKP_DR29 ((uint16_t)0x0088) +#define BKP_DR30 ((uint16_t)0x008C) +#define BKP_DR31 ((uint16_t)0x0090) +#define BKP_DR32 ((uint16_t)0x0094) +#define BKP_DR33 ((uint16_t)0x0098) +#define BKP_DR34 ((uint16_t)0x009C) +#define BKP_DR35 ((uint16_t)0x00A0) +#define BKP_DR36 ((uint16_t)0x00A4) +#define BKP_DR37 ((uint16_t)0x00A8) +#define BKP_DR38 ((uint16_t)0x00AC) +#define BKP_DR39 ((uint16_t)0x00B0) +#define BKP_DR40 ((uint16_t)0x00B4) +#define BKP_DR41 ((uint16_t)0x00B8) +#define BKP_DR42 ((uint16_t)0x00BC) + +#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ + ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ + ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ + ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ + ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ + ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ + ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ + ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ + ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ + ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ + ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ + ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ + ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ + ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) + +#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Functions + * @{ + */ + +void BKP_DeInit(void); +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); +void BKP_TamperPinCmd(FunctionalState NewState); +void BKP_ITConfig(FunctionalState NewState); +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); +FlagStatus BKP_GetFlagStatus(void); +void BKP_ClearFlag(void); +ITStatus BKP_GetITStatus(void); +void BKP_ClearITPendingBit(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_BKP_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_can.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_can.h new file mode 100644 index 0000000..648f747 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_can.h @@ -0,0 +1,697 @@ +/** + ****************************************************************************** + * @file stm32f10x_can.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the CAN firmware + * library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CAN_H +#define __STM32F10x_CAN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/** @defgroup CAN_Exported_Types + * @{ + */ + +#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ + ((PERIPH) == CAN2)) + +/** + * @brief CAN init structure definition + */ + +typedef struct +{ + uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. + It ranges from 1 to 1024. */ + + uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_operating_mode */ + + uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CAN_synchronisation_jump_width */ + + uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit + Segment 2. + This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered + communication mode. This parameter can be set + either to ENABLE or DISABLE. */ + + FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off + management. This parameter can be set either + to ENABLE or DISABLE. */ + + FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or + DISABLE. */ + + FunctionalState CAN_NART; /*!< Enable or disable the no-automatic + retransmission mode. This parameter can be + set either to ENABLE or DISABLE. */ + + FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE + or DISABLE. */ +} CAN_InitTypeDef; + +/** + * @brief CAN filter init structure definition + */ + +typedef struct +{ + uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t CAN_FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitTypeDef; + +/** + * @brief CAN Tx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanTxMsg; + +/** + * @brief CAN Rx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t FMI; /*!< Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanRxMsg; + +/** + * @} + */ + +/** @defgroup CAN_Exported_Constants + * @{ + */ + +/** @defgroup CAN_sleep_constants + * @{ + */ + +#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ +#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ + +/** + * @} + */ + +/** @defgroup CAN_Mode + * @{ + */ + +#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ + ((MODE) == CAN_Mode_LoopBack)|| \ + ((MODE) == CAN_Mode_Silent) || \ + ((MODE) == CAN_Mode_Silent_LoopBack)) +/** + * @} + */ + + +/** + * @defgroup CAN_Operating_Mode + * @{ + */ +#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ +#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ +#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ + + +#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ + ((MODE) == CAN_OperatingMode_Normal)|| \ + ((MODE) == CAN_OperatingMode_Sleep)) +/** + * @} + */ + +/** + * @defgroup CAN_Mode_Status + * @{ + */ + +#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ +#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ + + +/** + * @} + */ + +/** @defgroup CAN_synchronisation_jump_width + * @{ + */ + +#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ + +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ + ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 + * @{ + */ + +#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ + +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 + * @{ + */ + +#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ + +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) + +/** + * @} + */ + +/** @defgroup CAN_clock_prescaler + * @{ + */ + +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) + +/** + * @} + */ + +/** @defgroup CAN_filter_number + * @{ + */ +#ifndef STM32F10X_CL + #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13) +#else + #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +/** @defgroup CAN_filter_mode + * @{ + */ + +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ + ((MODE) == CAN_FilterMode_IdList)) +/** + * @} + */ + +/** @defgroup CAN_filter_scale + * @{ + */ + +#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ + ((SCALE) == CAN_FilterScale_32bit)) + +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO + * @{ + */ + +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ + ((FIFO) == CAN_FilterFIFO1)) +/** + * @} + */ + +/** @defgroup Start_bank_filter_for_slave_CAN + * @{ + */ +#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) +/** + * @} + */ + +/** @defgroup CAN_Tx + * @{ + */ + +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + +/** + * @} + */ + +/** @defgroup CAN_identifier_type + * @{ + */ + +#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ + ((IDTYPE) == CAN_Id_Extended)) +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request + * @{ + */ + +#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) + +/** + * @} + */ + +/** @defgroup CAN_transmit_constants + * @{ + */ + +#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ +#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ +#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ +#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ + +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number_constants + * @{ + */ + +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ + +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) + +/** + * @} + */ + +/** @defgroup CAN_sleep_constants + * @{ + */ + +#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ +#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ + +/** + * @} + */ + +/** @defgroup CAN_wake_up_constants + * @{ + */ + +#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ +#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ + +/** + * @} + */ + +/** + * @defgroup CAN_Error_Code_constants + * @{ + */ + +#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ +#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ +#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ +#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ +#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ +#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ +#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ +#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ + + +/** + * @} + */ + +/** @defgroup CAN_flags + * @{ + */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + and CAN_ClearFlag() functions. */ +/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */ + +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ +#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ +#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ +#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ +/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. + In this case the SLAK bit can be polled.*/ + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ + +#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ + ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ + ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ + ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ + ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ + ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ + ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ + ((FLAG) == CAN_FLAG_SLAK )) + +#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ + ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ + ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ + ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ + ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) +/** + * @} + */ + + +/** @defgroup CAN_interrupts + * @{ + */ + + + +#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ +#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ +#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ +#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ +#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ +#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME + + +#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ + ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ + ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ + ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +/** + * @} + */ + +/** @defgroup CAN_Legacy + * @{ + */ +#define CANINITFAILED CAN_InitStatus_Failed +#define CANINITOK CAN_InitStatus_Success +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +#define CAN_ID_STD CAN_Id_Standard +#define CAN_ID_EXT CAN_Id_Extended +#define CAN_RTR_DATA CAN_RTR_Data +#define CAN_RTR_REMOTE CAN_RTR_Remote +#define CANTXFAILE CAN_TxStatus_Failed +#define CANTXOK CAN_TxStatus_Ok +#define CANTXPENDING CAN_TxStatus_Pending +#define CAN_NO_MB CAN_TxStatus_NoMailBox +#define CANSLEEPFAILED CAN_Sleep_Failed +#define CANSLEEPOK CAN_Sleep_Ok +#define CANWAKEUPFAILED CAN_WakeUp_Failed +#define CANWAKEUPOK CAN_WakeUp_Ok + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CAN_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions + * @{ + */ +/* Function used to set the CAN configuration to the default reset state *****/ +void CAN_DeInit(CAN_TypeDef* CANx); + +/* Initialization and Configuration functions *********************************/ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); +void CAN_SlaveStartBank(uint8_t CAN_BankNumber); +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); + +/* Transmit functions *********************************************************/ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); + +/* Receive functions **********************************************************/ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); + + +/* Operation modes functions **************************************************/ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); +uint8_t CAN_Sleep(CAN_TypeDef* CANx); +uint8_t CAN_WakeUp(CAN_TypeDef* CANx); + +/* Error management functions *************************************************/ +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); + +/* Interrupts and flags management functions **********************************/ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CAN_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_cec.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_cec.h new file mode 100644 index 0000000..a3f8fc7 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_cec.h @@ -0,0 +1,210 @@ +/** + ****************************************************************************** + * @file stm32f10x_cec.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the CEC firmware + * library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CEC_H +#define __STM32F10x_CEC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CEC + * @{ + */ + + +/** @defgroup CEC_Exported_Types + * @{ + */ + +/** + * @brief CEC Init structure definition + */ +typedef struct +{ + uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. + This parameter can be a value of @ref CEC_BitTiming_Mode */ + uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. + This parameter can be a value of @ref CEC_BitPeriod_Mode */ +}CEC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup CEC_Exported_Constants + * @{ + */ + +/** @defgroup CEC_BitTiming_Mode + * @{ + */ +#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ +#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ + +#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ + ((MODE) == CEC_BitTimingErrFreeMode)) +/** + * @} + */ + +/** @defgroup CEC_BitPeriod_Mode + * @{ + */ +#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ +#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ + +#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ + ((MODE) == CEC_BitPeriodFlexibleMode)) +/** + * @} + */ + + +/** @defgroup CEC_interrupts_definition + * @{ + */ +#define CEC_IT_TERR CEC_CSR_TERR +#define CEC_IT_TBTRF CEC_CSR_TBTRF +#define CEC_IT_RERR CEC_CSR_RERR +#define CEC_IT_RBTF CEC_CSR_RBTF +#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ + ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) +/** + * @} + */ + + +/** @defgroup CEC_Own_Address + * @{ + */ +#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) +/** + * @} + */ + +/** @defgroup CEC_Prescaler + * @{ + */ +#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) + +/** + * @} + */ + +/** @defgroup CEC_flags_definition + * @{ + */ + +/** + * @brief ESR register flags + */ +#define CEC_FLAG_BTE ((uint32_t)0x10010000) +#define CEC_FLAG_BPE ((uint32_t)0x10020000) +#define CEC_FLAG_RBTFE ((uint32_t)0x10040000) +#define CEC_FLAG_SBE ((uint32_t)0x10080000) +#define CEC_FLAG_ACKE ((uint32_t)0x10100000) +#define CEC_FLAG_LINE ((uint32_t)0x10200000) +#define CEC_FLAG_TBTFE ((uint32_t)0x10400000) + +/** + * @brief CSR register flags + */ +#define CEC_FLAG_TEOM ((uint32_t)0x00000002) +#define CEC_FLAG_TERR ((uint32_t)0x00000004) +#define CEC_FLAG_TBTRF ((uint32_t)0x00000008) +#define CEC_FLAG_RSOM ((uint32_t)0x00000010) +#define CEC_FLAG_REOM ((uint32_t)0x00000020) +#define CEC_FLAG_RERR ((uint32_t)0x00000040) +#define CEC_FLAG_RBTF ((uint32_t)0x00000080) + +#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) + +#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ + ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \ + ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \ + ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \ + ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \ + ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \ + ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CEC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CEC_Exported_Functions + * @{ + */ +void CEC_DeInit(void); +void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); +void CEC_Cmd(FunctionalState NewState); +void CEC_ITConfig(FunctionalState NewState); +void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); +void CEC_SetPrescaler(uint16_t CEC_Prescaler); +void CEC_SendDataByte(uint8_t Data); +uint8_t CEC_ReceiveDataByte(void); +void CEC_StartOfMessage(void); +void CEC_EndOfMessageCmd(FunctionalState NewState); +FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); +void CEC_ClearFlag(uint32_t CEC_FLAG); +ITStatus CEC_GetITStatus(uint8_t CEC_IT); +void CEC_ClearITPendingBit(uint16_t CEC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CEC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_crc.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_crc.h new file mode 100644 index 0000000..658a51c --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_crc.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file stm32f10x_crc.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the CRC firmware + * library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CRC_H +#define __STM32F10x_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/** @defgroup CRC_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions + * @{ + */ + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CRC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_dac.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_dac.h new file mode 100644 index 0000000..7106164 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_dac.h @@ -0,0 +1,317 @@ +/** + ****************************************************************************** + * @file stm32f10x_dac.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the DAC firmware + * library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DAC_H +#define __STM32F10x_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @defgroup DAC_Exported_Types + * @{ + */ + +/** + * @brief DAC Init structure definition + */ + +typedef struct +{ + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves + are generated, or whether no wave is generated. + This parameter can be a value of @ref DAC_wave_generation */ + + uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or + the maximum amplitude triangle generation for the DAC channel. + This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ + + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +}DAC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup DAC_Exported_Constants + * @{ + */ + +/** @defgroup DAC_trigger_selection + * @{ + */ + +#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel + only in High-density devices*/ +#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel + only in Connectivity line, Medium-density and Low-density Value Line devices */ +#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel + only in Medium-density and Low-density Value Line devices*/ +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ + ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ + ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ + ((TRIGGER) == DAC_Trigger_Software)) + +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_WaveGeneration_None ((uint32_t)0x00000000) +#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) +#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) +#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ + ((WAVE) == DAC_WaveGeneration_Noise) || \ + ((WAVE) == DAC_WaveGeneration_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_lfsrunmask_triangleamplitude + * @{ + */ + +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ + ((VALUE) == DAC_TriangleAmplitude_1) || \ + ((VALUE) == DAC_TriangleAmplitude_3) || \ + ((VALUE) == DAC_TriangleAmplitude_7) || \ + ((VALUE) == DAC_TriangleAmplitude_15) || \ + ((VALUE) == DAC_TriangleAmplitude_31) || \ + ((VALUE) == DAC_TriangleAmplitude_63) || \ + ((VALUE) == DAC_TriangleAmplitude_127) || \ + ((VALUE) == DAC_TriangleAmplitude_255) || \ + ((VALUE) == DAC_TriangleAmplitude_511) || \ + ((VALUE) == DAC_TriangleAmplitude_1023) || \ + ((VALUE) == DAC_TriangleAmplitude_2047) || \ + ((VALUE) == DAC_TriangleAmplitude_4095)) +/** + * @} + */ + +/** @defgroup DAC_output_buffer + * @{ + */ + +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ + ((STATE) == DAC_OutputBuffer_Disable)) +/** + * @} + */ + +/** @defgroup DAC_Channel_selection + * @{ + */ + +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define DAC_Channel_2 ((uint32_t)0x00000010) +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ + ((CHANNEL) == DAC_Channel_2)) +/** + * @} + */ + +/** @defgroup DAC_data_alignment + * @{ + */ + +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ + ((ALIGN) == DAC_Align_12b_L) || \ + ((ALIGN) == DAC_Align_8b_R)) +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_Wave_Noise ((uint32_t)0x00000040) +#define DAC_Wave_Triangle ((uint32_t)0x00000080) +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ + ((WAVE) == DAC_Wave_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_data + * @{ + */ + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +/** + * @} + */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/** @defgroup DAC_interrupts_definition + * @{ + */ + +#define DAC_IT_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) + +/** + * @} + */ + +/** @defgroup DAC_flags_definition + * @{ + */ + +#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) + +/** + * @} + */ +#endif + +/** + * @} + */ + +/** @defgroup DAC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions + * @{ + */ + +void DAC_DeInit(void); +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); +#endif +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_DAC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_dbgmcu.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_dbgmcu.h new file mode 100644 index 0000000..1e6a68a --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_dbgmcu.h @@ -0,0 +1,119 @@ +/** + ****************************************************************************** + * @file stm32f10x_dbgmcu.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the DBGMCU + * firmware library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DBGMCU_H +#define __STM32F10x_DBGMCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBGMCU + * @{ + */ + +/** @defgroup DBGMCU_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Constants + * @{ + */ + +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) +#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) +#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) +#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) +#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) +#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) +#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000) +#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000) +#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000) +#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000) +#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000) +#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000) +#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000) +#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000) +#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000) + +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Functions + * @{ + */ + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_DBGMCU_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_dma.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_dma.h new file mode 100644 index 0000000..b5dc6a8 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_dma.h @@ -0,0 +1,439 @@ +/** + ****************************************************************************** + * @file stm32f10x_dma.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the DMA firmware + * library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DMA_H +#define __STM32F10x_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** @defgroup DMA_Exported_Types + * @{ + */ + +/** + * @brief DMA Init structure definition + */ + +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +}DMA_InitTypeDef; + +/** + * @} + */ + +/** @defgroup DMA_Exported_Constants + * @{ + */ + +#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ + ((PERIPH) == DMA1_Channel2) || \ + ((PERIPH) == DMA1_Channel3) || \ + ((PERIPH) == DMA1_Channel4) || \ + ((PERIPH) == DMA1_Channel5) || \ + ((PERIPH) == DMA1_Channel6) || \ + ((PERIPH) == DMA1_Channel7) || \ + ((PERIPH) == DMA2_Channel1) || \ + ((PERIPH) == DMA2_Channel2) || \ + ((PERIPH) == DMA2_Channel3) || \ + ((PERIPH) == DMA2_Channel4) || \ + ((PERIPH) == DMA2_Channel5)) + +/** @defgroup DMA_data_transfer_direction + * @{ + */ + +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) +#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ + ((DIR) == DMA_DIR_PeripheralSRC)) +/** + * @} + */ + +/** @defgroup DMA_peripheral_incremented_mode + * @{ + */ + +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ + ((STATE) == DMA_PeripheralInc_Disable)) +/** + * @} + */ + +/** @defgroup DMA_memory_incremented_mode + * @{ + */ + +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ + ((STATE) == DMA_MemoryInc_Disable)) +/** + * @} + */ + +/** @defgroup DMA_peripheral_data_size + * @{ + */ + +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ + ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ + ((SIZE) == DMA_PeripheralDataSize_Word)) +/** + * @} + */ + +/** @defgroup DMA_memory_data_size + * @{ + */ + +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ + ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ + ((SIZE) == DMA_MemoryDataSize_Word)) +/** + * @} + */ + +/** @defgroup DMA_circular_normal_mode + * @{ + */ + +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) +#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) +/** + * @} + */ + +/** @defgroup DMA_priority_level + * @{ + */ + +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ + ((PRIORITY) == DMA_Priority_High) || \ + ((PRIORITY) == DMA_Priority_Medium) || \ + ((PRIORITY) == DMA_Priority_Low)) +/** + * @} + */ + +/** @defgroup DMA_memory_to_memory + * @{ + */ + +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) +#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) + +/** + * @} + */ + +/** @defgroup DMA_interrupts_definition + * @{ + */ + +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) +#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) + +#define DMA2_IT_GL1 ((uint32_t)0x10000001) +#define DMA2_IT_TC1 ((uint32_t)0x10000002) +#define DMA2_IT_HT1 ((uint32_t)0x10000004) +#define DMA2_IT_TE1 ((uint32_t)0x10000008) +#define DMA2_IT_GL2 ((uint32_t)0x10000010) +#define DMA2_IT_TC2 ((uint32_t)0x10000020) +#define DMA2_IT_HT2 ((uint32_t)0x10000040) +#define DMA2_IT_TE2 ((uint32_t)0x10000080) +#define DMA2_IT_GL3 ((uint32_t)0x10000100) +#define DMA2_IT_TC3 ((uint32_t)0x10000200) +#define DMA2_IT_HT3 ((uint32_t)0x10000400) +#define DMA2_IT_TE3 ((uint32_t)0x10000800) +#define DMA2_IT_GL4 ((uint32_t)0x10001000) +#define DMA2_IT_TC4 ((uint32_t)0x10002000) +#define DMA2_IT_HT4 ((uint32_t)0x10004000) +#define DMA2_IT_TE4 ((uint32_t)0x10008000) +#define DMA2_IT_GL5 ((uint32_t)0x10010000) +#define DMA2_IT_TC5 ((uint32_t)0x10020000) +#define DMA2_IT_HT5 ((uint32_t)0x10040000) +#define DMA2_IT_TE5 ((uint32_t)0x10080000) + +#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) + +#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ + ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ + ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ + ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ + ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ + ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ + ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ + ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ + ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ + ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ + ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ + ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ + ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ + ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ + ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ + ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ + ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ + ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ + ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ + ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ + ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ + ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ + ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ + ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) + +/** + * @} + */ + +/** @defgroup DMA_flags_definition + * @{ + */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + +#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) +#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) +#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) +#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) +#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) +#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) +#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) +#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) +#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) +#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) +#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) +#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) +#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) +#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) +#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) +#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) +#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) +#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) +#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) +#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) + +#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) + +#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ + ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ + ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ + ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ + ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ + ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ + ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ + ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ + ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ + ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ + ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ + ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ + ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ + ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ + ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ + ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ + ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ + ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ + ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ + ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ + ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ + ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ + ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ + ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) +/** + * @} + */ + +/** @defgroup DMA_Buffer_Size + * @{ + */ + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup DMA_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions + * @{ + */ + +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); +void DMA_ClearFlag(uint32_t DMAy_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_DMA_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_exti.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_exti.h new file mode 100644 index 0000000..a1ab7d0 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_exti.h @@ -0,0 +1,184 @@ +/** + ****************************************************************************** + * @file stm32f10x_exti.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the EXTI firmware + * library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_EXTI_H +#define __STM32F10x_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +/** @defgroup EXTI_Exported_Types + * @{ + */ + +/** + * @brief EXTI mode enumeration + */ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + +/** + * @brief EXTI Trigger enumeration + */ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ + ((TRIGGER) == EXTI_Trigger_Falling) || \ + ((TRIGGER) == EXTI_Trigger_Rising_Falling)) +/** + * @brief EXTI Init Structure definition + */ + +typedef struct +{ + uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +}EXTI_InitTypeDef; + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Constants + * @{ + */ + +/** @defgroup EXTI_Lines + * @{ + */ + +#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS + Wakeup from suspend event */ +#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ + +#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) +#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ + ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ + ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ + ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ + ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ + ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ + ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ + ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ + ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ + ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) + + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions + * @{ + */ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_EXTI_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_flash.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_flash.h new file mode 100644 index 0000000..f46d4e8 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_flash.h @@ -0,0 +1,426 @@ +/** + ****************************************************************************** + * @file stm32f10x_flash.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the FLASH + * firmware library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FLASH_H +#define __STM32F10x_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @defgroup FLASH_Exported_Types + * @{ + */ + +/** + * @brief FLASH Status + */ + +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT +}FLASH_Status; + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Constants + * @{ + */ + +/** @defgroup Flash_Latency + * @{ + */ + +#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ + ((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2)) +/** + * @} + */ + +/** @defgroup Half_Cycle_Enable_Disable + * @{ + */ + +#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */ +#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */ +#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ + ((STATE) == FLASH_HalfCycleAccess_Disable)) +/** + * @} + */ + +/** @defgroup Prefetch_Buffer_Enable_Disable + * @{ + */ + +#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ +#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ +#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ + ((STATE) == FLASH_PrefetchBuffer_Disable)) +/** + * @} + */ + +/** @defgroup Option_Bytes_Write_Protection + * @{ + */ + +/* Values to be used with STM32 Low and Medium density devices */ +#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */ +#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */ +#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */ +#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */ +#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */ +#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */ +#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */ +#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */ + +/* Values to be used with STM32 Medium-density devices */ +#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */ +#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */ +#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */ +#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */ +#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */ +#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */ +#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */ +#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */ +#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */ +#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */ +#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */ +#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */ +#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */ +#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */ +#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */ +#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */ +#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */ +#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */ +#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */ +#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */ +#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */ +#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */ +#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */ +#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */ + +/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */ +#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 0 to 1 */ +#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 2 to 3 */ +#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 4 to 5 */ +#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 6 to 7 */ +#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 8 to 9 */ +#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 10 to 11 */ +#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 12 to 13 */ +#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 14 to 15 */ +#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 16 to 17 */ +#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 18 to 19 */ +#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 20 to 21 */ +#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 22 to 23 */ +#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 24 to 25 */ +#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 26 to 27 */ +#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 28 to 29 */ +#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 30 to 31 */ +#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 32 to 33 */ +#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 34 to 35 */ +#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 36 to 37 */ +#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 38 to 39 */ +#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 40 to 41 */ +#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 42 to 43 */ +#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 44 to 45 */ +#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 46 to 47 */ +#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 48 to 49 */ +#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 50 to 51 */ +#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 52 to 53 */ +#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 54 to 55 */ +#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 56 to 57 */ +#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 58 to 59 */ +#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 60 to 61 */ +#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */ +#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */ +#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */ + +#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ + +#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) + +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_IWatchdog + * @{ + */ + +#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_nRST_STOP + * @{ + */ + +#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_nRST_STDBY + * @{ + */ + +#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) + +#ifdef STM32F10X_XL +/** + * @} + */ +/** @defgroup FLASH_Boot + * @{ + */ +#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position + and this parameter is selected the device will boot from Bank1(Default) */ +#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position + and this parameter is selected the device will boot from Bank 2 or Bank 1, + depending on the activation of the bank */ +#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2)) +#endif +/** + * @} + */ +/** @defgroup FLASH_Interrupts + * @{ + */ +#ifdef STM32F10X_XL +#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */ +#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */ + +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ + +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */ +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) +#else +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ + +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) +#endif + +/** + * @} + */ + +/** @defgroup FLASH_Flags + * @{ + */ +#ifdef STM32F10X_XL +#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */ +#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */ +#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */ +#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ + +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ + ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_OPTERR)|| \ + ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ + ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \ + ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR)) +#else +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ + ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ + ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_OPTERR)) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions + * @{ + */ + +/*------------ Functions used for all STM32F10x devices -----*/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +FlagStatus FLASH_GetPrefetchBufferStatus(void); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); + +/*------------ New function used for all STM32F10x devices -----*/ +void FLASH_UnlockBank1(void); +void FLASH_LockBank1(void); +FLASH_Status FLASH_EraseAllBank1Pages(void); +FLASH_Status FLASH_GetBank1Status(void); +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); + +#ifdef STM32F10X_XL +/*---- New Functions used only with STM32F10x_XL density devices -----*/ +void FLASH_UnlockBank2(void); +void FLASH_LockBank2(void); +FLASH_Status FLASH_EraseAllBank2Pages(void); +FLASH_Status FLASH_GetBank2Status(void); +FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout); +FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_FLASH_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_fsmc.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_fsmc.h new file mode 100644 index 0000000..ee707e7 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_fsmc.h @@ -0,0 +1,733 @@ +/** + ****************************************************************************** + * @file stm32f10x_fsmc.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the FSMC firmware + * library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FSMC_H +#define __STM32F10x_FSMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FSMC + * @{ + */ + +/** @defgroup FSMC_Exported_Types + * @{ + */ + +/** + * @brief Timing parameters For NOR/SRAM Banks + */ + +typedef struct +{ + uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories. */ + + uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories.*/ + + uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between 0 and 0xFF. + @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ + + uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between 0 and 0xF. + @note: It is only used for multiplexed NOR Flash memories. */ + + uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. + This parameter can be a value between 1 and 0xF. + @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ + + uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The value of this parameter depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between 0 and 0xF in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FSMC_Access_Mode */ +}FSMC_NORSRAMTimingInitTypeDef; + +/** + * @brief FSMC NOR/SRAM Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. + This parameter can be a value of @ref FSMC_NORSRAM_Bank */ + + uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the databus or not. + This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ + + uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory bank. + This parameter can be a value of @ref FSMC_Memory_Type */ + + uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref FSMC_Data_Width */ + + uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FSMC_Burst_Access_Mode */ + + uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FSMC_AsynchronousWait */ + + uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ + + uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash + memory, valid only when accessing Flash memories in burst mode. + This parameter can be a value of @ref FSMC_Wrap_Mode */ + + uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FSMC_Wait_Timing */ + + uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. + This parameter can be a value of @ref FSMC_Write_Operation */ + + uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal */ + + uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref FSMC_Extended_Mode */ + + uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref FSMC_Write_Burst */ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ +}FSMC_NORSRAMInitTypeDef; + +/** + * @brief Timing parameters For FSMC NAND and PCCARD Banks + */ + +typedef struct +{ + uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between 0 and 0xFF.*/ + + uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command deassertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the + databus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ +}FSMC_NAND_PCCARDTimingInitTypeDef; + +/** + * @brief FSMC NAND Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. + This parameter can be a value of @ref FSMC_NAND_Bank */ + + uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be any value of @ref FSMC_Data_Width */ + + uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. + This parameter can be any value of @ref FSMC_ECC */ + + uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. + This parameter can be any value of @ref FSMC_ECC_Page_Size */ + + uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ +}FSMC_NANDInitTypeDef; + +/** + * @brief FSMC PCCARD Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ +}FSMC_PCCARDInitTypeDef; + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Constants + * @{ + */ + +/** @defgroup FSMC_NORSRAM_Bank + * @{ + */ +#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) +#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) +#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) +#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) +/** + * @} + */ + +/** @defgroup FSMC_NAND_Bank + * @{ + */ +#define FSMC_Bank2_NAND ((uint32_t)0x00000010) +#define FSMC_Bank3_NAND ((uint32_t)0x00000100) +/** + * @} + */ + +/** @defgroup FSMC_PCCARD_Bank + * @{ + */ +#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) +/** + * @} + */ + +#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ + ((BANK) == FSMC_Bank1_NORSRAM2) || \ + ((BANK) == FSMC_Bank1_NORSRAM3) || \ + ((BANK) == FSMC_Bank1_NORSRAM4)) + +#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND)) + +#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +/** @defgroup NOR_SRAM_Controller + * @{ + */ + +/** @defgroup FSMC_Data_Address_Bus_Multiplexing + * @{ + */ + +#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) +#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) +#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ + ((MUX) == FSMC_DataAddressMux_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Memory_Type + * @{ + */ + +#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) +#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) +#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) +#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ + ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ + ((MEMORY) == FSMC_MemoryType_NOR)) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Width + * @{ + */ + +#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) +#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ + ((WIDTH) == FSMC_MemoryDataWidth_16b)) + +/** + * @} + */ + +/** @defgroup FSMC_Burst_Access_Mode + * @{ + */ + +#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) +#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) +#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ + ((STATE) == FSMC_BurstAccessMode_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_AsynchronousWait + * @{ + */ +#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) +#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) +#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ + ((STATE) == FSMC_AsynchronousWait_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal_Polarity + * @{ + */ + +#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) +#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) +#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ + ((POLARITY) == FSMC_WaitSignalPolarity_High)) + +/** + * @} + */ + +/** @defgroup FSMC_Wrap_Mode + * @{ + */ + +#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) +#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) +#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ + ((MODE) == FSMC_WrapMode_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Timing + * @{ + */ + +#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) +#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) +#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ + ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) + +/** + * @} + */ + +/** @defgroup FSMC_Write_Operation + * @{ + */ + +#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) +#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) +#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ + ((OPERATION) == FSMC_WriteOperation_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal + * @{ + */ + +#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) +#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) +#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ + ((SIGNAL) == FSMC_WaitSignal_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Extended_Mode + * @{ + */ + +#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) +#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) + +#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ + ((MODE) == FSMC_ExtendedMode_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Write_Burst + * @{ + */ + +#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) +#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) +#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ + ((BURST) == FSMC_WriteBurst_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Address_Setup_Time + * @{ + */ + +#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Address_Hold_Time + * @{ + */ + +#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Setup_Time + * @{ + */ + +#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) + +/** + * @} + */ + +/** @defgroup FSMC_Bus_Turn_around_Duration + * @{ + */ + +#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_CLK_Division + * @{ + */ + +#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Latency + * @{ + */ + +#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Access_Mode + * @{ + */ + +#define FSMC_AccessMode_A ((uint32_t)0x00000000) +#define FSMC_AccessMode_B ((uint32_t)0x10000000) +#define FSMC_AccessMode_C ((uint32_t)0x20000000) +#define FSMC_AccessMode_D ((uint32_t)0x30000000) +#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ + ((MODE) == FSMC_AccessMode_B) || \ + ((MODE) == FSMC_AccessMode_C) || \ + ((MODE) == FSMC_AccessMode_D)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup NAND_PCCARD_Controller + * @{ + */ + +/** @defgroup FSMC_Wait_feature + * @{ + */ + +#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) +#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) +#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ + ((FEATURE) == FSMC_Waitfeature_Enable)) + +/** + * @} + */ + + +/** @defgroup FSMC_ECC + * @{ + */ + +#define FSMC_ECC_Disable ((uint32_t)0x00000000) +#define FSMC_ECC_Enable ((uint32_t)0x00000040) +#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ + ((STATE) == FSMC_ECC_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_ECC_Page_Size + * @{ + */ + +#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) +#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) +#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) +#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) +#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) +#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) +#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_8192Bytes)) + +/** + * @} + */ + +/** @defgroup FSMC_TCLR_Setup_Time + * @{ + */ + +#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_TAR_Setup_Time + * @{ + */ + +#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Setup_Time + * @{ + */ + +#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Setup_Time + * @{ + */ + +#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Hold_Setup_Time + * @{ + */ + +#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_HiZ_Setup_Time + * @{ + */ + +#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Interrupt_sources + * @{ + */ + +#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) +#define FSMC_IT_Level ((uint32_t)0x00000010) +#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) +#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) +#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ + ((IT) == FSMC_IT_Level) || \ + ((IT) == FSMC_IT_FallingEdge)) +/** + * @} + */ + +/** @defgroup FSMC_Flags + * @{ + */ + +#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) +#define FSMC_FLAG_Level ((uint32_t)0x00000002) +#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) +#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) +#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ + ((FLAG) == FSMC_FLAG_Level) || \ + ((FLAG) == FSMC_FLAG_FallingEdge) || \ + ((FLAG) == FSMC_FLAG_FEMPT)) + +#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Functions + * @{ + */ + +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); +void FSMC_NANDDeInit(uint32_t FSMC_Bank); +void FSMC_PCCARDDeInit(void); +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_PCCARDCmd(FunctionalState NewState); +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); +uint32_t FSMC_GetECC(uint32_t FSMC_Bank); +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_FSMC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_gpio.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_gpio.h new file mode 100644 index 0000000..b8aa49a --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_gpio.h @@ -0,0 +1,385 @@ +/** + ****************************************************************************** + * @file stm32f10x_gpio.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the GPIO + * firmware library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_GPIO_H +#define __STM32F10x_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** @defgroup GPIO_Exported_Types + * @{ + */ + +#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ + ((PERIPH) == GPIOB) || \ + ((PERIPH) == GPIOC) || \ + ((PERIPH) == GPIOD) || \ + ((PERIPH) == GPIOE) || \ + ((PERIPH) == GPIOF) || \ + ((PERIPH) == GPIOG)) + +/** + * @brief Output Maximum frequency selection + */ + +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +}GPIOSpeed_TypeDef; +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ + ((SPEED) == GPIO_Speed_50MHz)) + +/** + * @brief Configuration Mode enumeration + */ + +typedef enum +{ GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +}GPIOMode_TypeDef; + +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ + ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ + ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ + ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) + +/** + * @brief GPIO Init structure definition + */ + +typedef struct +{ + uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +}GPIO_InitTypeDef; + + +/** + * @brief Bit_SET and Bit_RESET enumeration + */ + +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; + +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Constants + * @{ + */ + +/** @defgroup GPIO_pins_define + * @{ + */ + +#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ + +#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) + +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) + +/** + * @} + */ + +/** @defgroup GPIO_Remap_define + * @{ + */ + +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */ +#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */ +#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */ +#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */ +#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */ +#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */ +#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */ +#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ +#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ +#define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ +#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected + to TIM2 Internal Trigger 1 for calibration + (only for Connectivity line devices) */ +#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ + +#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */ + +#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */ +#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */ +#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */ + +#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */ +#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */ +#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, + only for High density Value line devices) */ + +#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ + ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ + ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ + ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ + ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ + ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ + ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ + ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \ + ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ + ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ + ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ + ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \ + ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \ + ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \ + ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \ + ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \ + ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \ + ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \ + ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \ + ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \ + ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \ + ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC)) + +/** + * @} + */ + +/** @defgroup GPIO_Port_Sources + * @{ + */ + +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOE ((uint8_t)0x04) +#define GPIO_PortSourceGPIOF ((uint8_t)0x05) +#define GPIO_PortSourceGPIOG ((uint8_t)0x06) +#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOE)) + +#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOG)) + +/** + * @} + */ + +/** @defgroup GPIO_Pin_sources + * @{ + */ + +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ + ((PINSOURCE) == GPIO_PinSource1) || \ + ((PINSOURCE) == GPIO_PinSource2) || \ + ((PINSOURCE) == GPIO_PinSource3) || \ + ((PINSOURCE) == GPIO_PinSource4) || \ + ((PINSOURCE) == GPIO_PinSource5) || \ + ((PINSOURCE) == GPIO_PinSource6) || \ + ((PINSOURCE) == GPIO_PinSource7) || \ + ((PINSOURCE) == GPIO_PinSource8) || \ + ((PINSOURCE) == GPIO_PinSource9) || \ + ((PINSOURCE) == GPIO_PinSource10) || \ + ((PINSOURCE) == GPIO_PinSource11) || \ + ((PINSOURCE) == GPIO_PinSource12) || \ + ((PINSOURCE) == GPIO_PinSource13) || \ + ((PINSOURCE) == GPIO_PinSource14) || \ + ((PINSOURCE) == GPIO_PinSource15)) + +/** + * @} + */ + +/** @defgroup Ethernet_Media_Interface + * @{ + */ +#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) +#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) + +#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \ + ((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) + +/** + * @} + */ +/** + * @} + */ + +/** @defgroup GPIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions + * @{ + */ + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_GPIO_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_i2c.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_i2c.h new file mode 100644 index 0000000..2d42e5c --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_i2c.h @@ -0,0 +1,684 @@ +/** + ****************************************************************************** + * @file stm32f10x_i2c.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the I2C firmware + * library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_I2C_H +#define __STM32F10x_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @defgroup I2C_Exported_Types + * @{ + */ + +/** + * @brief I2C Init structure definition + */ + +typedef struct +{ + uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /*!< Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +}I2C_InitTypeDef; + +/** + * @} + */ + + +/** @defgroup I2C_Exported_Constants + * @{ + */ + +#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ + ((PERIPH) == I2C2)) +/** @defgroup I2C_mode + * @{ + */ + +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) +#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ + ((MODE) == I2C_Mode_SMBusDevice) || \ + ((MODE) == I2C_Mode_SMBusHost)) +/** + * @} + */ + +/** @defgroup I2C_duty_cycle_in_fast_mode + * @{ + */ + +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ + ((CYCLE) == I2C_DutyCycle_2)) +/** + * @} + */ + +/** @defgroup I2C_acknowledgement + * @{ + */ + +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) +#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ + ((STATE) == I2C_Ack_Disable)) +/** + * @} + */ + +/** @defgroup I2C_transfer_direction + * @{ + */ + +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) +#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ + ((DIRECTION) == I2C_Direction_Receiver)) +/** + * @} + */ + +/** @defgroup I2C_acknowledged_address + * @{ + */ + +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ + ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) +/** + * @} + */ + +/** @defgroup I2C_registers + * @{ + */ + +#define I2C_Register_CR1 ((uint8_t)0x00) +#define I2C_Register_CR2 ((uint8_t)0x04) +#define I2C_Register_OAR1 ((uint8_t)0x08) +#define I2C_Register_OAR2 ((uint8_t)0x0C) +#define I2C_Register_DR ((uint8_t)0x10) +#define I2C_Register_SR1 ((uint8_t)0x14) +#define I2C_Register_SR2 ((uint8_t)0x18) +#define I2C_Register_CCR ((uint8_t)0x1C) +#define I2C_Register_TRISE ((uint8_t)0x20) +#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ + ((REGISTER) == I2C_Register_CR2) || \ + ((REGISTER) == I2C_Register_OAR1) || \ + ((REGISTER) == I2C_Register_OAR2) || \ + ((REGISTER) == I2C_Register_DR) || \ + ((REGISTER) == I2C_Register_SR1) || \ + ((REGISTER) == I2C_Register_SR2) || \ + ((REGISTER) == I2C_Register_CCR) || \ + ((REGISTER) == I2C_Register_TRISE)) +/** + * @} + */ + +/** @defgroup I2C_SMBus_alert_pin_level + * @{ + */ + +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) +#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ + ((ALERT) == I2C_SMBusAlert_High)) +/** + * @} + */ + +/** @defgroup I2C_PEC_position + * @{ + */ + +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) +#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ + ((POSITION) == I2C_PECPosition_Current)) +/** + * @} + */ + +/** @defgroup I2C_NCAK_position + * @{ + */ + +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) +#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ + ((POSITION) == I2C_NACKPosition_Current)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) +#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) + +#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ + ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ + ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ + ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ + ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ + ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ + ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) +/** + * @} + */ + +/** @defgroup I2C_flags_definition + * @{ + */ + +/** + * @brief SR2 register flags + */ + +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/** + * @brief SR1 register flags + */ + +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ + ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ + ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ + ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ + ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ + ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ + ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ + ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ + ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ + ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ + ((FLAG) == I2C_FLAG_SB)) +/** + * @} + */ + +/** @defgroup I2C_Events + * @{ + */ + +/*======================================== + + I2C Master Events (Events grouped in order of communication) + ==========================================*/ +/** + * @brief Communication start + * + * After sending the START condition (I2C_GenerateSTART() function) the master + * has to wait for this event. It means that the Start condition has been correctly + * released on the I2C bus (the bus is free, no other devices is communicating). + * + */ +/* --EV5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/** + * @brief Address Acknowledge + * + * After checking on EV5 (start condition correctly released on the bus), the + * master sends the address of the slave(s) with which it will communicate + * (I2C_Send7bitAddress() function, it also determines the direction of the communication: + * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will + * be set: + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (just after generating the START + * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() + * function). Then master should wait on EV9. It means that the 10-bit addressing + * header has been correctly sent on the bus. Then master should send the second part of + * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master + * should wait for event EV6. + * + */ + +/* --EV6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/* --EV9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/** + * @brief Communication events + * + * If a communication is established (START condition generated and slave address + * acknowledged) then the master has to check on one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EV7 then to read + * the data received from the slave (I2C_ReceiveData() function). + * + * 2) Master Transmitter mode: The master has to send data (I2C_SendData() + * function) then to wait on event EV8 or EV8_2. + * These two events are similar: + * - EV8 means that the data has been written in the data register and is + * being shifted out. + * - EV8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EV8 is sufficient for the application. + * Using EV8_2 leads to a slower communication but ensure more reliable test. + * EV8_2 is also more suitable than EV8 for testing on the last data transmission + * (before Stop condition generation). + * + * @note In case the user software does not guarantee that this event EV7 is + * managed before the current byte end of transfer, then user may check on EV7 + * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). + * In this case the communication may be slower. + * + */ + +/* Master RECEIVER mode -----------------------------*/ +/* --EV7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master TRANSMITTER mode --------------------------*/ +/* --EV8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* --EV8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + + +/*======================================== + + I2C Slave Events (Events grouped in order of communication) + ==========================================*/ + +/** + * @brief Communication start events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a Start condition on the bus (generated by master + * device) followed by the peripheral address. The peripheral generates an ACK + * condition on the bus (if the acknowledge feature is enabled through function + * I2C_AcknowledgeConfig()) and the events listed above are set : + * + * 1) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * 2) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * 3) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* --EV1 (all the events below are variants of EV1) */ +/* 1) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* 2) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* 3) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/** + * @brief Communication events + * + * Wait on one of these events when EV1 has already been checked and: + * + * - Slave RECEIVER mode: + * - EV2: When the application is expecting a data byte to be received. + * - EV4: When the application is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EV3: When a byte has been transmitted by the slave and the application is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be + * used when the user software doesn't guarantee the EV3 is managed before the + * current byte end of transfer. + * - EV3_2: When the master sends a NACK in order to tell slave that data transmission + * shall end (before sending the STOP condition). In this case slave has to stop sending + * data bytes and expect a Stop condition on the bus. + * + * @note In case the user software does not guarantee that the event EV2 is + * managed before the current byte end of transfer, then user may check on EV2 + * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). + * In this case the communication may be slower. + * + */ + +/* Slave RECEIVER mode --------------------------*/ +/* --EV2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* --EV4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave TRANSMITTER mode -----------------------*/ +/* --EV3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/* --EV3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + +/*=========================== End of Events Description ==========================================*/ + +#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ + ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ + ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) +/** + * @} + */ + +/** @defgroup I2C_own_address1 + * @{ + */ + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) +/** + * @} + */ + +/** @defgroup I2C_clock_speed + * @{ + */ + +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions + * @{ + */ + +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); + +/** + * @brief + **************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * depending on the application requirements and constraints: + * + * + * 1) Basic state monitoring: + * Using I2C_CheckEvent() function: + * It compares the status registers (SR1 and SR2) content to a given event + * (can be the combination of one or more flags). + * It returns SUCCESS if the current status includes the given flags + * and returns ERROR if one or more flags are missing in the current status. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (RM0008). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs (ie. error flags are set besides to the monitored flags), + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * hold or corrupted real state. + * In this case, it is advised to use error interrupts to monitor the error + * events and handle them in the interrupt IRQ handler. + * + * @note + * For error management, it is advised to use the following functions: + * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). + * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() + * in order to determine which error occurred. + * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() + * and/or I2C_GenerateStop() in order to clear the error flag and source, + * and return to correct communication status. + * + * + * 2) Advanced state monitoring: + * Using the function I2C_GetLastEvent() which returns the image of both status + * registers in a single word (uint32_t) (Status Register 2 value is shifted left + * by 16 bits and concatenated to Status Register 1). + * - When to use: + * - This function is suitable for the same applications above but it allows to + * overcome the limitations of I2C_GetFlagStatus() function (see below). + * The returned value could be compared to events already defined in the + * library (stm32f10x_i2c.h) or to custom values defined by user. + * - This function is suitable when multiple flags are monitored at the same time. + * - At the opposite of I2C_CheckEvent() function, this function allows user to + * choose when an event is accepted (when all events flags are set and no + * other flags are set or just when the needed flags are set like + * I2C_CheckEvent() function). + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * 3) Flag-based state monitoring: + * Using the function I2C_GetFlagStatus() which simply returns the status of + * one single flag (ie. I2C_FLAG_RXNE ...). + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed (most I2C events + * are monitored through multiple flags). + * - Limitations: + * - When calling this function, the Status register is accessed. Some flags are + * cleared when the status register is accessed. So checking the status + * of one Flag, may clear other ones. + * - Function may need to be called twice or more in order to monitor one + * single event. + * + */ + +/** + * + * 1) Basic state monitoring + ******************************************************************************* + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/** + * + * 2) Advanced state monitoring + ******************************************************************************* + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/** + * + * 3) Flag-based state monitoring + ******************************************************************************* + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +/** + * + ******************************************************************************* + */ + +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_I2C_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_iwdg.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_iwdg.h new file mode 100644 index 0000000..7f5ab76 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_iwdg.h @@ -0,0 +1,140 @@ +/** + ****************************************************************************** + * @file stm32f10x_iwdg.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the IWDG + * firmware library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_IWDG_H +#define __STM32F10x_IWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup IWDG + * @{ + */ + +/** @defgroup IWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Constants + * @{ + */ + +/** @defgroup IWDG_WriteAccess + * @{ + */ + +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) +#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ + ((ACCESS) == IWDG_WriteAccess_Disable)) +/** + * @} + */ + +/** @defgroup IWDG_prescaler + * @{ + */ + +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) +#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ + ((PRESCALER) == IWDG_Prescaler_8) || \ + ((PRESCALER) == IWDG_Prescaler_16) || \ + ((PRESCALER) == IWDG_Prescaler_32) || \ + ((PRESCALER) == IWDG_Prescaler_64) || \ + ((PRESCALER) == IWDG_Prescaler_128)|| \ + ((PRESCALER) == IWDG_Prescaler_256)) +/** + * @} + */ + +/** @defgroup IWDG_Flag + * @{ + */ + +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) +#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) +#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Functions + * @{ + */ + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_IWDG_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_pwr.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_pwr.h new file mode 100644 index 0000000..76e6ce9 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_pwr.h @@ -0,0 +1,156 @@ +/** + ****************************************************************************** + * @file stm32f10x_pwr.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the PWR firmware + * library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_PWR_H +#define __STM32F10x_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/** @defgroup PWR_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Constants + * @{ + */ + +/** @defgroup PVD_detection_level + * @{ + */ + +#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) +#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) +#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) +#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) +#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) +#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ + ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ + ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ + ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) +/** + * @} + */ + +/** @defgroup Regulator_state_is_STOP_mode + * @{ + */ + +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000001) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ + ((REGULATOR) == PWR_Regulator_LowPower)) +/** + * @} + */ + +/** @defgroup STOP_mode_entry + * @{ + */ + +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) + +/** + * @} + */ + +/** @defgroup PWR_Flag + * @{ + */ + +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) +#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ + ((FLAG) == PWR_FLAG_PVDO)) + +#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions + * @{ + */ + +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_PWR_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_rcc.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_rcc.h new file mode 100644 index 0000000..b3b7d82 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_rcc.h @@ -0,0 +1,727 @@ +/** + ****************************************************************************** + * @file stm32f10x_rcc.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the RCC firmware + * library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RCC_H +#define __STM32F10x_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @defgroup RCC_Exported_Types + * @{ + */ + +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ + uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ +}RCC_ClocksTypeDef; + +/** + * @} + */ + +/** @defgroup RCC_Exported_Constants + * @{ + */ + +/** @defgroup HSE_configuration + * @{ + */ + +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_Bypass)) + +/** + * @} + */ + +/** @defgroup PLL_entry_clock_source + * @{ + */ + +#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL) + #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) + #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) + #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div2)) +#else + #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) + #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ + ((SOURCE) == RCC_PLLSource_PREDIV1)) +#endif /* STM32F10X_CL */ + +/** + * @} + */ + +/** @defgroup PLL_multiplication_factor + * @{ + */ +#ifndef STM32F10X_CL + #define RCC_PLLMul_2 ((uint32_t)0x00000000) + #define RCC_PLLMul_3 ((uint32_t)0x00040000) + #define RCC_PLLMul_4 ((uint32_t)0x00080000) + #define RCC_PLLMul_5 ((uint32_t)0x000C0000) + #define RCC_PLLMul_6 ((uint32_t)0x00100000) + #define RCC_PLLMul_7 ((uint32_t)0x00140000) + #define RCC_PLLMul_8 ((uint32_t)0x00180000) + #define RCC_PLLMul_9 ((uint32_t)0x001C0000) + #define RCC_PLLMul_10 ((uint32_t)0x00200000) + #define RCC_PLLMul_11 ((uint32_t)0x00240000) + #define RCC_PLLMul_12 ((uint32_t)0x00280000) + #define RCC_PLLMul_13 ((uint32_t)0x002C0000) + #define RCC_PLLMul_14 ((uint32_t)0x00300000) + #define RCC_PLLMul_15 ((uint32_t)0x00340000) + #define RCC_PLLMul_16 ((uint32_t)0x00380000) + #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ + ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ + ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ + ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ + ((MUL) == RCC_PLLMul_16)) + +#else + #define RCC_PLLMul_4 ((uint32_t)0x00080000) + #define RCC_PLLMul_5 ((uint32_t)0x000C0000) + #define RCC_PLLMul_6 ((uint32_t)0x00100000) + #define RCC_PLLMul_7 ((uint32_t)0x00140000) + #define RCC_PLLMul_8 ((uint32_t)0x00180000) + #define RCC_PLLMul_9 ((uint32_t)0x001C0000) + #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) + + #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_6_5)) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +/** @defgroup PREDIV1_division_factor + * @{ + */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) + #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) + #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) + #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) + #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) + #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) + #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) + #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) + #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) + #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) + #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) + #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) + #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) + #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) + #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) + #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) + #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) + + #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ + ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ + ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ + ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ + ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ + ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ + ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ + ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) +#endif +/** + * @} + */ + + +/** @defgroup PREDIV1_clock_source + * @{ + */ +#ifdef STM32F10X_CL +/* PREDIV1 clock source (for STM32 connectivity line devices) */ + #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) + #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) + + #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ + ((SOURCE) == RCC_PREDIV1_Source_PLL2)) +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/* PREDIV1 clock source (for STM32 Value line devices) */ + #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) + + #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) +#endif +/** + * @} + */ + +#ifdef STM32F10X_CL +/** @defgroup PREDIV2_division_factor + * @{ + */ + + #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) + #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) + #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) + #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) + #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) + #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) + #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) + #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) + #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) + #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) + #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) + #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) + #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) + #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) + #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) + #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) + + #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ + ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ + ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ + ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ + ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ + ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ + ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ + ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) +/** + * @} + */ + + +/** @defgroup PLL2_multiplication_factor + * @{ + */ + + #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) + #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) + #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) + #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) + #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) + #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) + #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) + #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) + #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) + + #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ + ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ + ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ + ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ + ((MUL) == RCC_PLL2Mul_20)) +/** + * @} + */ + + +/** @defgroup PLL3_multiplication_factor + * @{ + */ + + #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) + #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) + #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) + #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) + #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) + #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) + #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) + #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) + #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) + + #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ + ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ + ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ + ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ + ((MUL) == RCC_PLL3Mul_20)) +/** + * @} + */ + +#endif /* STM32F10X_CL */ + + +/** @defgroup System_clock_source + * @{ + */ + +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) +/** + * @} + */ + +/** @defgroup AHB_clock_source + * @{ + */ + +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ + ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ + ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ + ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ + ((HCLK) == RCC_SYSCLK_Div512)) +/** + * @} + */ + +/** @defgroup APB1_APB2_clock_source + * @{ + */ + +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ + ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ + ((PCLK) == RCC_HCLK_Div16)) +/** + * @} + */ + +/** @defgroup RCC_Interrupt_source + * @{ + */ + +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +#ifndef STM32F10X_CL + #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) + #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) + #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) +#else + #define RCC_IT_PLL2RDY ((uint8_t)0x20) + #define RCC_IT_PLL3RDY ((uint8_t)0x40) + #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) + #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ + ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) + #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) +#endif /* STM32F10X_CL */ + + +/** + * @} + */ + +#ifndef STM32F10X_CL +/** @defgroup USB_Device_clock_source + * @{ + */ + + #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) + #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) + + #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ + ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) +/** + * @} + */ +#else +/** @defgroup USB_OTG_FS_clock_source + * @{ + */ + #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) + #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) + + #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ + ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) +/** + * @} + */ +#endif /* STM32F10X_CL */ + + +#ifdef STM32F10X_CL +/** @defgroup I2S2_clock_source + * @{ + */ + #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) + #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) + + #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ + ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) +/** + * @} + */ + +/** @defgroup I2S3_clock_source + * @{ + */ + #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) + #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) + + #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ + ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) +/** + * @} + */ +#endif /* STM32F10X_CL */ + + +/** @defgroup ADC_clock_source + * @{ + */ + +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) +#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ + ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) +/** + * @} + */ + +/** @defgroup LSE_configuration + * @{ + */ + +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_Bypass)) +/** + * @} + */ + +/** @defgroup RTC_clock_source + * @{ + */ + +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ + ((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) +/** + * @} + */ + +/** @defgroup AHB_peripheral + * @{ + */ + +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) +#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) + +#ifndef STM32F10X_CL + #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) + #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) + #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) +#else + #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) + #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) + #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) + #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) + + #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) + #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +/** @defgroup APB2_peripheral + * @{ + */ + +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) +#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) +#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) +#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) +#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) +#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) +#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) +#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) + +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup APB1_peripheral + * @{ + */ + +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) +#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) +#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_USB ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) +#define RCC_APB1Periph_CEC ((uint32_t)0x40000000) + +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @defgroup Clock_source_to_output_on_MCO_pin + * @{ + */ + +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) + +#ifndef STM32F10X_CL + #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ + ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ + ((MCO) == RCC_MCO_PLLCLK_Div2)) +#else + #define RCC_MCO_PLL2CLK ((uint8_t)0x08) + #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) + #define RCC_MCO_XT1 ((uint8_t)0x0A) + #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) + + #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ + ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ + ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ + ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ + ((MCO) == RCC_MCO_PLL3CLK)) +#endif /* STM32F10X_CL */ + +/** + * @} + */ + +/** @defgroup RCC_Flag + * @{ + */ + +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +#ifndef STM32F10X_CL + #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ + ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ + ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ + ((FLAG) == RCC_FLAG_LPWRRST)) +#else + #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) + #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) + #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ + ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ + ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ + ((FLAG) == RCC_FLAG_LPWRRST)) +#endif /* STM32F10X_CL */ + +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RCC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions + * @{ + */ + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) + void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); +#endif + +#ifdef STM32F10X_CL + void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); + void RCC_PLL2Config(uint32_t RCC_PLL2Mul); + void RCC_PLL2Cmd(FunctionalState NewState); + void RCC_PLL3Config(uint32_t RCC_PLL3Mul); + void RCC_PLL3Cmd(FunctionalState NewState); +#endif /* STM32F10X_CL */ + +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); + +#ifndef STM32F10X_CL + void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); +#else + void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); +#endif /* STM32F10X_CL */ + +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); + +#ifdef STM32F10X_CL + void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); + void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); +#endif /* STM32F10X_CL */ + +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); + +#ifdef STM32F10X_CL +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +#endif /* STM32F10X_CL */ + +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_RCC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_rtc.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_rtc.h new file mode 100644 index 0000000..214a589 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_rtc.h @@ -0,0 +1,135 @@ +/** + ****************************************************************************** + * @file stm32f10x_rtc.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the RTC firmware + * library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RTC_H +#define __STM32F10x_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/** @defgroup RTC_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Constants + * @{ + */ + +/** @defgroup RTC_interrupts_define + * @{ + */ + +#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */ +#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00)) +#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ + ((IT) == RTC_IT_SEC)) +/** + * @} + */ + +/** @defgroup RTC_interrupts_flags + * @{ + */ + +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */ +#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00)) +#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ + ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ + ((FLAG) == RTC_FLAG_SEC)) +#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions + * @{ + */ + +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +uint32_t RTC_GetCounter(void); +void RTC_SetCounter(uint32_t CounterValue); +void RTC_SetPrescaler(uint32_t PrescalerValue); +void RTC_SetAlarm(uint32_t AlarmValue); +uint32_t RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); +void RTC_ClearFlag(uint16_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint16_t RTC_IT); +void RTC_ClearITPendingBit(uint16_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_RTC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_sdio.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_sdio.h new file mode 100644 index 0000000..40cfded --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_sdio.h @@ -0,0 +1,531 @@ +/** + ****************************************************************************** + * @file stm32f10x_sdio.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the SDIO firmware + * library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SDIO_H +#define __STM32F10x_SDIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SDIO + * @{ + */ + +/** @defgroup SDIO_Exported_Types + * @{ + */ + +typedef struct +{ + uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SDIO_Clock_Edge */ + + uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is + enabled or disabled. + This parameter can be a value of @ref SDIO_Clock_Bypass */ + + uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or + disabled when the bus is idle. + This parameter can be a value of @ref SDIO_Clock_Power_Save */ + + uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. + This parameter can be a value of @ref SDIO_Bus_Wide */ + + uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. + This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ + + uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. + This parameter can be a value between 0x00 and 0xFF. */ + +} SDIO_InitTypeDef; + +typedef struct +{ + uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register */ + + uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ + + uint32_t SDIO_Response; /*!< Specifies the SDIO response type. + This parameter can be a value of @ref SDIO_Response_Type */ + + uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. + This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ + + uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_CPSM_State */ +} SDIO_CmdInitTypeDef; + +typedef struct +{ + uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ + + uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ + + uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. + This parameter can be a value of @ref SDIO_Data_Block_Size */ + + uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDIO_Transfer_Direction */ + + uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. + This parameter can be a value of @ref SDIO_Transfer_Type */ + + uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_DPSM_State */ +} SDIO_DataInitTypeDef; + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constants + * @{ + */ + +/** @defgroup SDIO_Clock_Edge + * @{ + */ + +#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) +#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) +#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ + ((EDGE) == SDIO_ClockEdge_Falling)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Bypass + * @{ + */ + +#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) +#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ + ((BYPASS) == SDIO_ClockBypass_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Power_Save + * @{ + */ + +#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) +#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) +#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ + ((SAVE) == SDIO_ClockPowerSave_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Bus_Wide + * @{ + */ + +#define SDIO_BusWide_1b ((uint32_t)0x00000000) +#define SDIO_BusWide_4b ((uint32_t)0x00000800) +#define SDIO_BusWide_8b ((uint32_t)0x00001000) +#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ + ((WIDE) == SDIO_BusWide_8b)) + +/** + * @} + */ + +/** @defgroup SDIO_Hardware_Flow_Control + * @{ + */ + +#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) +#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) +#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ + ((CONTROL) == SDIO_HardwareFlowControl_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Power_State + * @{ + */ + +#define SDIO_PowerState_OFF ((uint32_t)0x00000000) +#define SDIO_PowerState_ON ((uint32_t)0x00000003) +#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) +/** + * @} + */ + + +/** @defgroup SDIO_Interrupt_sources + * @{ + */ + +#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) +#define SDIO_IT_CMDREND ((uint32_t)0x00000040) +#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) +#define SDIO_IT_DATAEND ((uint32_t)0x00000100) +#define SDIO_IT_STBITERR ((uint32_t)0x00000200) +#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) +#define SDIO_IT_CMDACT ((uint32_t)0x00000800) +#define SDIO_IT_TXACT ((uint32_t)0x00001000) +#define SDIO_IT_RXACT ((uint32_t)0x00002000) +#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) +#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) +#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) +#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) +/** + * @} + */ + +/** @defgroup SDIO_Command_Index + * @{ + */ + +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) +/** + * @} + */ + +/** @defgroup SDIO_Response_Type + * @{ + */ + +#define SDIO_Response_No ((uint32_t)0x00000000) +#define SDIO_Response_Short ((uint32_t)0x00000040) +#define SDIO_Response_Long ((uint32_t)0x000000C0) +#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ + ((RESPONSE) == SDIO_Response_Short) || \ + ((RESPONSE) == SDIO_Response_Long)) +/** + * @} + */ + +/** @defgroup SDIO_Wait_Interrupt_State + * @{ + */ + +#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ +#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ +#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ +#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ + ((WAIT) == SDIO_Wait_Pend)) +/** + * @} + */ + +/** @defgroup SDIO_CPSM_State + * @{ + */ + +#define SDIO_CPSM_Disable ((uint32_t)0x00000000) +#define SDIO_CPSM_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Response_Registers + * @{ + */ + +#define SDIO_RESP1 ((uint32_t)0x00000000) +#define SDIO_RESP2 ((uint32_t)0x00000004) +#define SDIO_RESP3 ((uint32_t)0x00000008) +#define SDIO_RESP4 ((uint32_t)0x0000000C) +#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ + ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) +/** + * @} + */ + +/** @defgroup SDIO_Data_Length + * @{ + */ + +#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) +/** + * @} + */ + +/** @defgroup SDIO_Data_Block_Size + * @{ + */ + +#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) +#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) +#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) +#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) +#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) +#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) +#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) +#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) +#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) +#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) +#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) +#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) +#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) +#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) +#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) +#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ + ((SIZE) == SDIO_DataBlockSize_2b) || \ + ((SIZE) == SDIO_DataBlockSize_4b) || \ + ((SIZE) == SDIO_DataBlockSize_8b) || \ + ((SIZE) == SDIO_DataBlockSize_16b) || \ + ((SIZE) == SDIO_DataBlockSize_32b) || \ + ((SIZE) == SDIO_DataBlockSize_64b) || \ + ((SIZE) == SDIO_DataBlockSize_128b) || \ + ((SIZE) == SDIO_DataBlockSize_256b) || \ + ((SIZE) == SDIO_DataBlockSize_512b) || \ + ((SIZE) == SDIO_DataBlockSize_1024b) || \ + ((SIZE) == SDIO_DataBlockSize_2048b) || \ + ((SIZE) == SDIO_DataBlockSize_4096b) || \ + ((SIZE) == SDIO_DataBlockSize_8192b) || \ + ((SIZE) == SDIO_DataBlockSize_16384b)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Direction + * @{ + */ + +#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) +#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) +#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ + ((DIR) == SDIO_TransferDir_ToSDIO)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Type + * @{ + */ + +#define SDIO_TransferMode_Block ((uint32_t)0x00000000) +#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) +#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ + ((MODE) == SDIO_TransferMode_Block)) +/** + * @} + */ + +/** @defgroup SDIO_DPSM_State + * @{ + */ + +#define SDIO_DPSM_Disable ((uint32_t)0x00000000) +#define SDIO_DPSM_Enable ((uint32_t)0x00000001) +#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Flags + * @{ + */ + +#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) +#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) +#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) +#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) +#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) +#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) +#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) +#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) +#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) +#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) +#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) +#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_TXUNDERR) || \ + ((FLAG) == SDIO_FLAG_RXOVERR) || \ + ((FLAG) == SDIO_FLAG_CMDREND) || \ + ((FLAG) == SDIO_FLAG_CMDSENT) || \ + ((FLAG) == SDIO_FLAG_DATAEND) || \ + ((FLAG) == SDIO_FLAG_STBITERR) || \ + ((FLAG) == SDIO_FLAG_DBCKEND) || \ + ((FLAG) == SDIO_FLAG_CMDACT) || \ + ((FLAG) == SDIO_FLAG_TXACT) || \ + ((FLAG) == SDIO_FLAG_RXACT) || \ + ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOF) || \ + ((FLAG) == SDIO_FLAG_RXFIFOF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOE) || \ + ((FLAG) == SDIO_FLAG_TXDAVL) || \ + ((FLAG) == SDIO_FLAG_RXDAVL) || \ + ((FLAG) == SDIO_FLAG_SDIOIT) || \ + ((FLAG) == SDIO_FLAG_CEATAEND)) + +#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) + +#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ + ((IT) == SDIO_IT_DCRCFAIL) || \ + ((IT) == SDIO_IT_CTIMEOUT) || \ + ((IT) == SDIO_IT_DTIMEOUT) || \ + ((IT) == SDIO_IT_TXUNDERR) || \ + ((IT) == SDIO_IT_RXOVERR) || \ + ((IT) == SDIO_IT_CMDREND) || \ + ((IT) == SDIO_IT_CMDSENT) || \ + ((IT) == SDIO_IT_DATAEND) || \ + ((IT) == SDIO_IT_STBITERR) || \ + ((IT) == SDIO_IT_DBCKEND) || \ + ((IT) == SDIO_IT_CMDACT) || \ + ((IT) == SDIO_IT_TXACT) || \ + ((IT) == SDIO_IT_RXACT) || \ + ((IT) == SDIO_IT_TXFIFOHE) || \ + ((IT) == SDIO_IT_RXFIFOHF) || \ + ((IT) == SDIO_IT_TXFIFOF) || \ + ((IT) == SDIO_IT_RXFIFOF) || \ + ((IT) == SDIO_IT_TXFIFOE) || \ + ((IT) == SDIO_IT_RXFIFOE) || \ + ((IT) == SDIO_IT_TXDAVL) || \ + ((IT) == SDIO_IT_RXDAVL) || \ + ((IT) == SDIO_IT_SDIOIT) || \ + ((IT) == SDIO_IT_CEATAEND)) + +#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) + +/** + * @} + */ + +/** @defgroup SDIO_Read_Wait_Mode + * @{ + */ + +#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) +#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) +#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ + ((MODE) == SDIO_ReadWaitMode_DATA2)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions + * @{ + */ + +void SDIO_DeInit(void); +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockCmd(FunctionalState NewState); +void SDIO_SetPowerState(uint32_t SDIO_PowerState); +uint32_t SDIO_GetPowerState(void); +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); +void SDIO_DMACmd(FunctionalState NewState); +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); +uint8_t SDIO_GetCommandResponse(void); +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +uint32_t SDIO_GetDataCounter(void); +uint32_t SDIO_ReadData(void); +void SDIO_WriteData(uint32_t Data); +uint32_t SDIO_GetFIFOCount(void); +void SDIO_StartSDIOReadWait(FunctionalState NewState); +void SDIO_StopSDIOReadWait(FunctionalState NewState); +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); +void SDIO_SetSDIOOperation(FunctionalState NewState); +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); +void SDIO_CommandCompletionCmd(FunctionalState NewState); +void SDIO_CEATAITCmd(FunctionalState NewState); +void SDIO_SendCEATACmd(FunctionalState NewState); +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); +void SDIO_ClearFlag(uint32_t SDIO_FLAG); +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); +void SDIO_ClearITPendingBit(uint32_t SDIO_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_SDIO_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_spi.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_spi.h new file mode 100644 index 0000000..6056c4c --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_spi.h @@ -0,0 +1,487 @@ +/** + ****************************************************************************** + * @file stm32f10x_spi.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the SPI firmware + * library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SPI_H +#define __STM32F10x_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @defgroup SPI_Exported_Types + * @{ + */ + +/** + * @brief SPI Init structure definition + */ + +typedef struct +{ + uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ +}SPI_InitTypeDef; + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + + uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +}I2S_InitTypeDef; + +/** + * @} + */ + +/** @defgroup SPI_Exported_Constants + * @{ + */ + +#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ + ((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +/** @defgroup SPI_data_direction + * @{ + */ + +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) +#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ + ((MODE) == SPI_Direction_2Lines_RxOnly) || \ + ((MODE) == SPI_Direction_1Line_Rx) || \ + ((MODE) == SPI_Direction_1Line_Tx)) +/** + * @} + */ + +/** @defgroup SPI_mode + * @{ + */ + +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) +/** + * @} + */ + +/** @defgroup SPI_data_size + * @{ + */ + +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ + ((DATASIZE) == SPI_DataSize_8b)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management + * @{ + */ + +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ + ((NSS) == SPI_NSS_Hard)) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler + * @{ + */ + +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_256)) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission + * @{ + */ + +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ + ((BIT) == SPI_FirstBit_LSB)) +/** + * @} + */ + +/** @defgroup I2S_Mode + * @{ + */ + +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) +#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ + ((MODE) == I2S_Mode_SlaveRx) || \ + ((MODE) == I2S_Mode_MasterTx) || \ + ((MODE) == I2S_Mode_MasterRx) ) +/** + * @} + */ + +/** @defgroup I2S_Standard + * @{ + */ + +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) +#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ + ((STANDARD) == I2S_Standard_MSB) || \ + ((STANDARD) == I2S_Standard_LSB) || \ + ((STANDARD) == I2S_Standard_PCMShort) || \ + ((STANDARD) == I2S_Standard_PCMLong)) +/** + * @} + */ + +/** @defgroup I2S_Data_Format + * @{ + */ + +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) +#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ + ((FORMAT) == I2S_DataFormat_16bextended) || \ + ((FORMAT) == I2S_DataFormat_24b) || \ + ((FORMAT) == I2S_DataFormat_32b)) +/** + * @} + */ + +/** @defgroup I2S_MCLK_Output + * @{ + */ + +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) +#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ + ((OUTPUT) == I2S_MCLKOutput_Disable)) +/** + * @} + */ + +/** @defgroup I2S_Audio_Frequency + * @{ + */ + +#define I2S_AudioFreq_192k ((uint32_t)192000) +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) + +#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ + ((FREQ) <= I2S_AudioFreq_192k)) || \ + ((FREQ) == I2S_AudioFreq_Default)) +/** + * @} + */ + +/** @defgroup I2S_Clock_Polarity + * @{ + */ + +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) +#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ + ((CPOL) == I2S_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_I2S_DMA_transfer_requests + * @{ + */ + +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) +#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) +/** + * @} + */ + +/** @defgroup SPI_NSS_internal_software_management + * @{ + */ + +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ + ((INTERNAL) == SPI_NSSInternalSoft_Reset)) +/** + * @} + */ + +/** @defgroup SPI_CRC_Transmit_Receive + * @{ + */ + +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) +/** + * @} + */ + +/** @defgroup SPI_direction_transmit_receive + * @{ + */ + +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ + ((DIRECTION) == SPI_Direction_Tx)) +/** + * @} + */ + +/** @defgroup SPI_I2S_interrupts_definition + * @{ + */ + +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_I2S_IT_RXNE) || \ + ((IT) == SPI_I2S_IT_ERR)) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) +#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) +#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \ + ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) +/** + * @} + */ + +/** @defgroup SPI_I2S_flags_definition + * @{ + */ + +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) +#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) +#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ + ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ + ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ + ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) +/** + * @} + */ + +/** @defgroup SPI_CRC_polynomial + * @{ + */ + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SPI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions + * @{ + */ + +void SPI_I2S_DeInit(SPI_TypeDef* SPIx); +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_SPI_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_tim.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_tim.h new file mode 100644 index 0000000..cd7ac3e --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_tim.h @@ -0,0 +1,1164 @@ +/** + ****************************************************************************** + * @file stm32f10x_tim.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the TIM firmware + * library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_TIM_H +#define __STM32F10x_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/** @defgroup TIM_Exported_Types + * @{ + */ + +/** + * @brief TIM Time Base Init structure definition + * @note This structure is used with all TIMx except for TIM6 and TIM7. + */ + +typedef struct +{ + uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/** + * @brief TIM Output Compare Init structure definition + */ + +typedef struct +{ + uint16_t TIM_OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/** + * @brief TIM Input Capture Init structure definition + */ + +typedef struct +{ + + uint16_t TIM_Channel; /*!< Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/** + * @brief BDTR structure definition + * @note This structure is used only with TIM1 and TIM8. + */ + +typedef struct +{ + + uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/** @defgroup TIM_Exported_constants + * @{ + */ + +#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM10)|| \ + ((PERIPH) == TIM11)|| \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM13)|| \ + ((PERIPH) == TIM14)|| \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST1: TIM 1 and 8 */ +#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM8)) + +/* LIST2: TIM 1, 8, 15 16 and 17 */ +#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */ +#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8)) + +/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */ +#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */ +#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)) + +/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */ +#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM15)) + +/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */ +#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM15)) + +/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */ +#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM10)|| \ + ((PERIPH) == TIM11)|| \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM13)|| \ + ((PERIPH) == TIM14)|| \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */ +#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes + * @{ + */ + +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2)) +#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2) || \ + ((MODE) == TIM_ForcedAction_Active) || \ + ((MODE) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode + * @{ + */ + +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ + ((MODE) == TIM_OPMode_Repetitive)) +/** + * @} + */ + +/** @defgroup TIM_Channel + * @{ + */ + +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) +#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3) || \ + ((CHANNEL) == TIM_Channel_4)) +#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2)) +#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3)) +/** + * @} + */ + +/** @defgroup TIM_Clock_Division_CKD + * @{ + */ + +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) +#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ + ((DIV) == TIM_CKD_DIV2) || \ + ((DIV) == TIM_CKD_DIV4)) +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode + * @{ + */ + +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ + ((MODE) == TIM_CounterMode_Down) || \ + ((MODE) == TIM_CounterMode_CenterAligned1) || \ + ((MODE) == TIM_CounterMode_CenterAligned2) || \ + ((MODE) == TIM_CounterMode_CenterAligned3)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity + * @{ + */ + +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ + ((POLARITY) == TIM_OCPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity + * @{ + */ + +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ + ((POLARITY) == TIM_OCNPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_state + * @{ + */ + +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ + ((STATE) == TIM_OutputState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_state + * @{ + */ + +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) +#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ + ((STATE) == TIM_OutputNState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_state + * @{ + */ + +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) +#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ + ((CCX) == TIM_CCx_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_N_state + * @{ + */ + +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) +#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ + ((CCXN) == TIM_CCxN_Disable)) +/** + * @} + */ + +/** @defgroup Break_Input_enable_disable + * @{ + */ + +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ + ((STATE) == TIM_Break_Disable)) +/** + * @} + */ + +/** @defgroup Break_Polarity + * @{ + */ + +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ + ((POLARITY) == TIM_BreakPolarity_High)) +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset + * @{ + */ + +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ + ((STATE) == TIM_AutomaticOutput_Disable)) +/** + * @} + */ + +/** @defgroup Lock_level + * @{ + */ + +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ + ((LEVEL) == TIM_LOCKLevel_1) || \ + ((LEVEL) == TIM_LOCKLevel_2) || \ + ((LEVEL) == TIM_LOCKLevel_3)) +/** + * @} + */ + +/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state + * @{ + */ + +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ + ((STATE) == TIM_OSSIState_Disable)) +/** + * @} + */ + +/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state + * @{ + */ + +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ + ((STATE) == TIM_OSSRState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State + * @{ + */ + +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ + ((STATE) == TIM_OCIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State + * @{ + */ + +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ + ((STATE) == TIM_OCNIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity + * @{ + */ + +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ + ((POLARITY) == TIM_ICPolarity_Falling)) +#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ + ((POLARITY) == TIM_ICPolarity_Falling)|| \ + ((POLARITY) == TIM_ICPolarity_BothEdge)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection + * @{ + */ + +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ + ((SELECTION) == TIM_ICSelection_IndirectTI) || \ + ((SELECTION) == TIM_ICSelection_TRC)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler + * @{ + */ + +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_interrupt_sources + * @{ + */ + +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) +#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) + +#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ + ((IT) == TIM_IT_CC1) || \ + ((IT) == TIM_IT_CC2) || \ + ((IT) == TIM_IT_CC3) || \ + ((IT) == TIM_IT_CC4) || \ + ((IT) == TIM_IT_COM) || \ + ((IT) == TIM_IT_Trigger) || \ + ((IT) == TIM_IT_Break)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address + * @{ + */ + +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ + ((BASE) == TIM_DMABase_CR2) || \ + ((BASE) == TIM_DMABase_SMCR) || \ + ((BASE) == TIM_DMABase_DIER) || \ + ((BASE) == TIM_DMABase_SR) || \ + ((BASE) == TIM_DMABase_EGR) || \ + ((BASE) == TIM_DMABase_CCMR1) || \ + ((BASE) == TIM_DMABase_CCMR2) || \ + ((BASE) == TIM_DMABase_CCER) || \ + ((BASE) == TIM_DMABase_CNT) || \ + ((BASE) == TIM_DMABase_PSC) || \ + ((BASE) == TIM_DMABase_ARR) || \ + ((BASE) == TIM_DMABase_RCR) || \ + ((BASE) == TIM_DMABase_CCR1) || \ + ((BASE) == TIM_DMABase_CCR2) || \ + ((BASE) == TIM_DMABase_CCR3) || \ + ((BASE) == TIM_DMABase_CCR4) || \ + ((BASE) == TIM_DMABase_BDTR) || \ + ((BASE) == TIM_DMABase_DCR)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length + * @{ + */ + +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ + ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_18Transfers)) +/** + * @} + */ + +/** @defgroup TIM_DMA_sources + * @{ + */ + +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Prescaler + * @{ + */ + +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) +#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_Internal_Trigger_Selection + * @{ + */ + +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) +/** + * @} + */ + +/** @defgroup TIM_TIx_External_Clock_Source + * @{ + */ + +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) +#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ + ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ + ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Polarity + * @{ + */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) +#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ + ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) +/** + * @} + */ + +/** @defgroup TIM_Prescaler_Reload_Mode + * @{ + */ + +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) +#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ + ((RELOAD) == TIM_PSCReloadMode_Immediate)) +/** + * @} + */ + +/** @defgroup TIM_Forced_Action + * @{ + */ + +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) +#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ + ((ACTION) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode + * @{ + */ + +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ + ((MODE) == TIM_EncoderMode_TI2) || \ + ((MODE) == TIM_EncoderMode_TI12)) +/** + * @} + */ + + +/** @defgroup TIM_Event_Source + * @{ + */ + +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_Update_Source + * @{ + */ + +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ +#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ + ((SOURCE) == TIM_UpdateSource_Regular)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Preload_State + * @{ + */ + +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) +#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ + ((STATE) == TIM_OCPreload_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Fast_State + * @{ + */ + +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) +#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ + ((STATE) == TIM_OCFast_Disable)) + +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Clear_State + * @{ + */ + +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) +#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ + ((STATE) == TIM_OCClear_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Output_Source + * @{ + */ + +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ + ((SOURCE) == TIM_TRGOSource_Enable) || \ + ((SOURCE) == TIM_TRGOSource_Update) || \ + ((SOURCE) == TIM_TRGOSource_OC1) || \ + ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC4Ref)) +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode + * @{ + */ + +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ + ((MODE) == TIM_SlaveMode_Gated) || \ + ((MODE) == TIM_SlaveMode_Trigger) || \ + ((MODE) == TIM_SlaveMode_External1)) +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode + * @{ + */ + +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ + ((STATE) == TIM_MasterSlaveMode_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Flags + * @{ + */ + +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) +#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ + ((FLAG) == TIM_FLAG_CC1) || \ + ((FLAG) == TIM_FLAG_CC2) || \ + ((FLAG) == TIM_FLAG_CC3) || \ + ((FLAG) == TIM_FLAG_CC4) || \ + ((FLAG) == TIM_FLAG_COM) || \ + ((FLAG) == TIM_FLAG_Trigger) || \ + ((FLAG) == TIM_FLAG_Break) || \ + ((FLAG) == TIM_FLAG_CC1OF) || \ + ((FLAG) == TIM_FLAG_CC2OF) || \ + ((FLAG) == TIM_FLAG_CC3OF) || \ + ((FLAG) == TIM_FLAG_CC4OF)) + + +#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Filer_Value + * @{ + */ + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Filter + * @{ + */ + +#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_Legacy + * @{ + */ + +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions + * @{ + */ + +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); +uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_TIM_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_usart.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_usart.h new file mode 100644 index 0000000..61ae249 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_usart.h @@ -0,0 +1,412 @@ +/** + ****************************************************************************** + * @file stm32f10x_usart.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the USART + * firmware library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_USART_H +#define __STM32F10x_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/** @defgroup USART_Exported_Types + * @{ + */ + +/** + * @brief USART Init Structure definition + */ + +typedef struct +{ + uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/** + * @brief USART Clock Init Structure definition + */ + +typedef struct +{ + + uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/** + * @} + */ + +/** @defgroup USART_Exported_Constants + * @{ + */ + +#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == UART4) || \ + ((PERIPH) == UART5)) + +#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3)) + +#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == UART4)) +/** @defgroup USART_Word_Length + * @{ + */ + +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ + ((LENGTH) == USART_WordLength_9b)) +/** + * @} + */ + +/** @defgroup USART_Stop_Bits + * @{ + */ + +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ + ((STOPBITS) == USART_StopBits_0_5) || \ + ((STOPBITS) == USART_StopBits_2) || \ + ((STOPBITS) == USART_StopBits_1_5)) +/** + * @} + */ + +/** @defgroup USART_Parity + * @{ + */ + +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ + ((PARITY) == USART_Parity_Even) || \ + ((PARITY) == USART_Parity_Odd)) +/** + * @} + */ + +/** @defgroup USART_Mode + * @{ + */ + +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) +#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) +/** + * @} + */ + +/** @defgroup USART_Hardware_Flow_Control + * @{ + */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == USART_HardwareFlowControl_None) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS) || \ + ((CONTROL) == USART_HardwareFlowControl_CTS) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) +/** + * @} + */ + +/** @defgroup USART_Clock + * @{ + */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ + ((CLOCK) == USART_Clock_Enable)) +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity + * @{ + */ + +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) +#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) + +/** + * @} + */ + +/** @defgroup USART_Clock_Phase + * @{ + */ + +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) +#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) + +/** + * @} + */ + +/** @defgroup USART_Last_Bit + * @{ + */ + +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ + ((LASTBIT) == USART_LastBit_Enable)) +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition + * @{ + */ + +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) +#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) +#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ + ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) +#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) +/** + * @} + */ + +/** @defgroup USART_DMA_Requests + * @{ + */ + +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** + * @} + */ + +/** @defgroup USART_WakeUp_methods + * @{ + */ + +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) +#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ + ((WAKEUP) == USART_WakeUp_AddressMark)) +/** + * @} + */ + +/** @defgroup USART_LIN_Break_Detection_Length + * @{ + */ + +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ + (((LENGTH) == USART_LINBreakDetectLength_10b) || \ + ((LENGTH) == USART_LINBreakDetectLength_11b)) +/** + * @} + */ + +/** @defgroup USART_IrDA_Low_Power + * @{ + */ + +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) +#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ + ((MODE) == USART_IrDAMode_Normal)) +/** + * @} + */ + +/** @defgroup USART_Flags + * @{ + */ + +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) +#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ + ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ + ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ + ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ + ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) +#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\ + ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \ + || ((USART_FLAG) != USART_FLAG_CTS)) +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) +#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) +#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup USART_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions + * @{ + */ + +void USART_DeInit(USART_TypeDef* USARTx); +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef* USARTx); +void USART_SendBreak(USART_TypeDef* USARTx); +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_USART_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/inc/stm32f10x_wwdg.h b/Project/econais/STM32_Libs/F1/inc/stm32f10x_wwdg.h new file mode 100644 index 0000000..cd573da --- /dev/null +++ b/Project/econais/STM32_Libs/F1/inc/stm32f10x_wwdg.h @@ -0,0 +1,115 @@ +/** + ****************************************************************************** + * @file stm32f10x_wwdg.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file contains all the functions prototypes for the WWDG firmware + * library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_WWDG_H +#define __STM32F10x_WWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ + +/** @defgroup WWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Exported_Constants + * @{ + */ + +/** @defgroup WWDG_Prescaler + * @{ + */ + +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) +#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ + ((PRESCALER) == WWDG_Prescaler_2) || \ + ((PRESCALER) == WWDG_Prescaler_4) || \ + ((PRESCALER) == WWDG_Prescaler_8)) +#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup WWDG_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup WWDG_Exported_Functions + * @{ + */ + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_WWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/misc.c b/Project/econais/STM32_Libs/F1/src/misc.c new file mode 100644 index 0000000..ec9165f --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/misc.c @@ -0,0 +1,225 @@ +/** + ****************************************************************************** + * @file misc.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the miscellaneous firmware functions (add-on + * to CMSIS functions). + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "misc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup MISC + * @brief MISC driver modules + * @{ + */ + +/** @defgroup MISC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Defines + * @{ + */ + +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) +/** + * @} + */ + +/** @defgroup MISC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Functions + * @{ + */ + +/** + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * @param NVIC_PriorityGroup: specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @retval None + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains + * the configuration information for the specified NVIC peripheral. + * @retval None + */ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. + * This parameter can be one of the following values: + * @arg NVIC_VectTab_RAM + * @arg NVIC_VectTab_FLASH + * @param Offset: Vector Table base offset field. This value must be a multiple + * of 0x200. + * @retval None + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + /* Check the parameters */ + assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND + * @arg NVIC_LP_SLEEPDEEP + * @arg NVIC_LP_SLEEPONEXIT + * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** + * @brief Configures the SysTick clock source. + * @param SysTick_CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_adc.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_adc.c new file mode 100644 index 0000000..916a096 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_adc.c @@ -0,0 +1,1307 @@ +/** + ****************************************************************************** + * @file stm32f10x_adc.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the ADC firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_adc.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup ADC + * @brief ADC driver modules + * @{ + */ + +/** @defgroup ADC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Defines + * @{ + */ + +/* ADC DISCNUM mask */ +#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CR1_DISCEN_Set ((uint32_t)0x00000800) +#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CR1_JAUTO_Set ((uint32_t)0x00000400) +#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CR1 register Mask */ +#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) + +/* ADC ADON mask */ +#define CR2_ADON_Set ((uint32_t)0x00000001) +#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CR2_DMA_Set ((uint32_t)0x00000100) +#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CR2 register Mask */ +#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define SQR3_SQ_Set ((uint32_t)0x0000001F) +#define SQR2_SQ_Set ((uint32_t)0x0000001F) +#define SQR1_SQ_Set ((uint32_t)0x0000001F) + +/* SQR1 register Mask */ +#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define JSQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define JSQR_JL_Set ((uint32_t)0x00300000) +#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SMPR1_SMP_Set ((uint32_t)0x00000007) +#define SMPR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC JDRx registers offset */ +#define JDR_Offset ((uint8_t)0x28) + +/* ADC1 DR register base address */ +#define DR_ADDRESS ((uint32_t)0x4001244C) + +/** + * @} + */ + +/** @defgroup ADC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the ADCx peripheral registers to their default reset values. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_DeInit(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + if (ADCx == ADC1) + { + /* Enable ADC1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + /* Release ADC1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + } + else if (ADCx == ADC2) + { + /* Enable ADC2 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); + /* Release ADC2 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); + } + else + { + if (ADCx == ADC3) + { + /* Enable ADC3 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE); + /* Release ADC3 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE); + } + } +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains + * the configuration information for the specified ADC peripheral. + * @retval None + */ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); + assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); + assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); + + /*---------------------------- ADCx CR1 Configuration -----------------*/ + /* Get the ADCx CR1 value */ + tmpreg1 = ADCx->CR1; + /* Clear DUALMOD and SCAN bits */ + tmpreg1 &= CR1_CLEAR_Mask; + /* Configure ADCx: Dual mode and scan conversion mode */ + /* Set DUALMOD bits according to ADC_Mode value */ + /* Set SCAN bit according to ADC_ScanConvMode value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + /* Write to ADCx CR1 */ + ADCx->CR1 = tmpreg1; + + /*---------------------------- ADCx CR2 Configuration -----------------*/ + /* Get the ADCx CR2 value */ + tmpreg1 = ADCx->CR2; + /* Clear CONT, ALIGN and EXTSEL bits */ + tmpreg1 &= CR2_CLEAR_Mask; + /* Configure ADCx: external trigger event and continuous conversion mode */ + /* Set ALIGN bit according to ADC_DataAlign value */ + /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ + /* Set CONT bit according to ADC_ContinuousConvMode value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + /* Write to ADCx CR2 */ + ADCx->CR2 = tmpreg1; + + /*---------------------------- ADCx SQR1 Configuration -----------------*/ + /* Get the ADCx SQR1 value */ + tmpreg1 = ADCx->SQR1; + /* Clear L bits */ + tmpreg1 &= SQR1_CLEAR_Mask; + /* Configure ADCx: regular channel sequence length */ + /* Set L bits according to ADC_NbrOfChannel value */ + tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + /* Write to ADCx SQR1 */ + ADCx->SQR1 = tmpreg1; +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized. + * @retval None + */ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Reset ADC init structure parameters values */ + /* Initialize the ADC_Mode member */ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + /* initialize the ADC_ScanConvMode member */ + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + /* Initialize the ADC_ContinuousConvMode member */ + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + /* Initialize the ADC_ExternalTrigConv member */ + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + /* Initialize the ADC_DataAlign member */ + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + /* Initialize the ADC_NbrOfChannel member */ + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/** + * @brief Enables or disables the specified ADC peripheral. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the ADCx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the ADON bit to wake up the ADC from power down mode */ + ADCx->CR2 |= CR2_ADON_Set; + } + else + { + /* Disable the selected ADC peripheral */ + ADCx->CR2 &= CR2_ADON_Reset; + } +} + +/** + * @brief Enables or disables the specified ADC DMA request. + * @param ADCx: where x can be 1 or 3 to select the ADC peripheral. + * Note: ADC2 hasn't a DMA capability. + * @param NewState: new state of the selected ADC DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_DMA_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CR2 |= CR2_DMA_Set; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CR2 &= CR2_DMA_Reset; + } +} + +/** + * @brief Enables or disables the specified ADC interrupts. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @param NewState: new state of the specified ADC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)ADC_IT; + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->CR1 |= itmask; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->CR1 &= (~(uint32_t)itmask); + } +} + +/** + * @brief Resets the selected ADC calibration registers. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_ResetCalibration(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Resets the selected ADC calibration registers */ + ADCx->CR2 |= CR2_RSTCAL_Set; +} + +/** + * @brief Gets the selected ADC reset calibration registers status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC reset calibration registers (SET or RESET). + */ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of RSTCAL bit */ + if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET) + { + /* RSTCAL bit is set */ + bitstatus = SET; + } + else + { + /* RSTCAL bit is reset */ + bitstatus = RESET; + } + /* Return the RSTCAL bit status */ + return bitstatus; +} + +/** + * @brief Starts the selected ADC calibration process. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_StartCalibration(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Enable the selected ADC calibration process */ + ADCx->CR2 |= CR2_CAL_Set; +} + +/** + * @brief Gets the selected ADC calibration status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC calibration (SET or RESET). + */ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of CAL bit */ + if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET) + { + /* CAL bit is set: calibration on going */ + bitstatus = SET; + } + else + { + /* CAL bit is reset: end of calibration */ + bitstatus = RESET; + } + /* Return the CAL bit status */ + return bitstatus; +} + +/** + * @brief Enables or disables the selected ADC software start conversion . + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC software start conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event and start the selected + ADC conversion */ + ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set; + } + else + { + /* Disable the selected ADC conversion on external event and stop the selected + ADC conversion */ + ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; + } +} + +/** + * @brief Gets the selected ADC Software start conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of SWSTART bit */ + if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET) + { + /* SWSTART bit is set */ + bitstatus = SET; + } + else + { + /* SWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the SWSTART bit status */ + return bitstatus; +} + +/** + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Number: specifies the discontinuous mode regular channel + * count value. This number must be between 1 and 8. + * @retval None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); + /* Get the old register value */ + tmpreg1 = ADCx->CR1; + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= CR1_DISCNUM_Reset; + /* Set the discontinuous mode channel count */ + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + /* Store the new register value */ + ADCx->CR1 = tmpreg1; +} + +/** + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode + * on regular group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + ADCx->CR1 |= CR1_DISCEN_Set; + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + ADCx->CR1 &= CR1_DISCEN_Reset; + } +} + +/** + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles + * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles + * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles + * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles + * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles + * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles + * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles + * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles + * @retval None + */ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_REGULAR_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* For Rank 1 to 6 */ + if (Rank < 7) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR3; + /* Calculate the mask to clear */ + tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR3 = tmpreg1; + } + /* For Rank 7 to 12 */ + else if (Rank < 13) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR2; + /* Calculate the mask to clear */ + tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR2 = tmpreg1; + } + /* For Rank 13 to 16 */ + else + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR1; + /* Calculate the mask to clear */ + tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR1 = tmpreg1; + } +} + +/** + * @brief Enables or disables the ADCx conversion through external trigger. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC external trigger start of conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event */ + ADCx->CR2 |= CR2_EXTTRIG_Set; + } + else + { + /* Disable the selected ADC conversion on external event */ + ADCx->CR2 &= CR2_EXTTRIG_Reset; + } +} + +/** + * @brief Returns the last ADCx conversion result data for regular channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Return the selected ADC conversion value */ + return (uint16_t) ADCx->DR; +} + +/** + * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. + * @retval The Data conversion value. + */ +uint32_t ADC_GetDualModeConversionValue(void) +{ + /* Return the dual mode conversion value */ + return (*(__IO uint32_t *) DR_ADDRESS); +} + +/** + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC auto injected conversion + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + ADCx->CR1 |= CR1_JAUTO_Set; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + ADCx->CR1 &= CR1_JAUTO_Reset; + } +} + +/** + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode + * on injected group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + ADCx->CR1 |= CR1_JDISCEN_Set; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + ADCx->CR1 &= CR1_JDISCEN_Reset; + } +} + +/** + * @brief Configures the ADCx external trigger for injected channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. + * This parameter can be one of the following values: + * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3) + * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3) + * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8 + * capture compare4 event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not + * by external trigger (for ADC1, ADC2 and ADC3) + * @retval None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); + /* Get the old register value */ + tmpreg = ADCx->CR2; + /* Clear the old external event selection for injected group */ + tmpreg &= CR2_JEXTSEL_Reset; + /* Set the external event selection for injected group */ + tmpreg |= ADC_ExternalTrigInjecConv; + /* Store the new register value */ + ADCx->CR2 = tmpreg; +} + +/** + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC external trigger start of + * injected conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC external event selection for injected group */ + ADCx->CR2 |= CR2_JEXTTRIG_Set; + } + else + { + /* Disable the selected ADC external event selection for injected group */ + ADCx->CR2 &= CR2_JEXTTRIG_Reset; + } +} + +/** + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC software start injected conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion for injected group on external event and start the selected + ADC injected conversion */ + ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set; + } + else + { + /* Disable the selected ADC conversion on external event for injected group and stop the selected + ADC injected conversion */ + ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/** + * @brief Gets the selected ADC Software start injected conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start injected conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of JSWSTART bit */ + if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET) + { + /* JSWSTART bit is set */ + bitstatus = SET; + } + else + { + /* JSWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the JSWSTART bit status */ + return bitstatus; +} + +/** + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles + * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles + * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles + * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles + * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles + * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles + * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles + * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles + * @retval None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_INJECTED_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* Rank configuration */ + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Get JL value: Number = JL+1 */ + tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20; + /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Clear the old JSQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Set the JSQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Configures the sequencer length for injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Length: The sequencer length. + * This parameter must be a number between 1 to 4. + * @retval None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_LENGTH(Length)); + + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Clear the old injected sequnence lenght JL bits */ + tmpreg1 &= JSQR_JL_Reset; + /* Set the injected sequnence lenght JL bits */ + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Set the injected channels conversion value offset + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the ADC injected channel to set its offset. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @param Offset: the offset value for the selected ADC injected channel + * This parameter must be a 12bit value. + * @retval None + */ +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + assert_param(IS_ADC_OFFSET(Offset)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + /* Set the selected injected channel data offset */ + *(__IO uint32_t *) tmp = (uint32_t)Offset; +} + +/** + * @brief Returns the ADC injected channel conversion result + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the converted ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @retval The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + JDR_Offset; + + /* Returns the selected injected channel conversion data value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} + +/** + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. + * This parameter can be one of the following values: + * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel + * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel + * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel + * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel + * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel + * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels + * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog + * @retval None + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); + /* Get the old register value */ + tmpreg = ADCx->CR1; + /* Clear AWDEN, AWDENJ and AWDSGL bits */ + tmpreg &= CR1_AWDMode_Reset; + /* Set the analog watchdog enable mode */ + tmpreg |= ADC_AnalogWatchdog; + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/** + * @brief Configures the high and low thresholds of the analog watchdog. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param HighThreshold: the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * @param LowThreshold: the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * @retval None + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_THRESHOLD(HighThreshold)); + assert_param(IS_ADC_THRESHOLD(LowThreshold)); + /* Set the ADCx high threshold */ + ADCx->HTR = HighThreshold; + /* Set the ADCx low threshold */ + ADCx->LTR = LowThreshold; +} + +/** + * @brief Configures the analog watchdog guarded single channel + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure for the analog watchdog. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @retval None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + /* Get the old register value */ + tmpreg = ADCx->CR1; + /* Clear the Analog watchdog channel select bits */ + tmpreg &= CR1_AWDCH_Reset; + /* Set the Analog watchdog channel */ + tmpreg |= ADC_Channel; + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/** + * @brief Enables or disables the temperature sensor and Vrefint channel. + * @param NewState: new state of the temperature sensor. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the temperature sensor and Vrefint channel*/ + ADC1->CR2 |= CR2_TSVREFE_Set; + } + else + { + /* Disable the temperature sensor and Vrefint channel*/ + ADC1->CR2 &= CR2_TSVREFE_Reset; + } +} + +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @retval The new state of ADC_FLAG (SET or RESET). + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); + /* Check the status of the specified ADC flag */ + if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's pending flags. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @retval None + */ +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); + /* Clear the selected ADC flags */ + ADCx->SR = ~(uint32_t)ADC_FLAG; +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt source to check. + * This parameter can be one of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @retval The new state of ADC_IT (SET or RESET). + */ +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = ADC_IT >> 8; + /* Get the ADC_IT enable bit status */ + enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ; + /* Check the status of the specified ADC interrupt */ + if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's interrupt pending bits. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @retval None + */ +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)(ADC_IT >> 8); + /* Clear the selected ADC interrupt pending bits */ + ADCx->SR = ~(uint32_t)itmask; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_bkp.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_bkp.c new file mode 100644 index 0000000..3004b9e --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_bkp.c @@ -0,0 +1,308 @@ +/** + ****************************************************************************** + * @file stm32f10x_bkp.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the BKP firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_bkp.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup BKP + * @brief BKP driver modules + * @{ + */ + +/** @defgroup BKP_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Defines + * @{ + */ + +/* ------------ BKP registers bit address in the alias region --------------- */ +#define BKP_OFFSET (BKP_BASE - PERIPH_BASE) + +/* --- CR Register ----*/ + +/* Alias word address of TPAL bit */ +#define CR_OFFSET (BKP_OFFSET + 0x30) +#define TPAL_BitNumber 0x01 +#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) + +/* Alias word address of TPE bit */ +#define TPE_BitNumber 0x00 +#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of TPIE bit */ +#define CSR_OFFSET (BKP_OFFSET + 0x34) +#define TPIE_BitNumber 0x02 +#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) + +/* Alias word address of TIF bit */ +#define TIF_BitNumber 0x09 +#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) + +/* Alias word address of TEF bit */ +#define TEF_BitNumber 0x08 +#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) + +/* ---------------------- BKP registers bit mask ------------------------ */ + +/* RTCCR register bit mask */ +#define RTCCR_CAL_MASK ((uint16_t)0xFF80) +#define RTCCR_MASK ((uint16_t)0xFC7F) + +/** + * @} + */ + + +/** @defgroup BKP_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the BKP peripheral registers to their default reset values. + * @param None + * @retval None + */ +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +/** + * @brief Configures the Tamper Pin active level. + * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. + * This parameter can be one of the following values: + * @arg BKP_TamperPinLevel_High: Tamper pin active on high level + * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level + * @retval None + */ +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) +{ + /* Check the parameters */ + assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); + *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel; +} + +/** + * @brief Enables or disables the Tamper Pin activation. + * @param NewState: new state of the Tamper Pin activation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void BKP_TamperPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Tamper Pin Interrupt. + * @param NewState: new state of the Tamper Pin Interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void BKP_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState; +} + +/** + * @brief Select the RTC output source to output on the Tamper pin. + * @param BKP_RTCOutputSource: specifies the RTC output source. + * This parameter can be one of the following values: + * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin. + * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency + * divided by 64 on the Tamper pin. + * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on + * the Tamper pin. + * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on + * the Tamper pin. + * @retval None + */ +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource)); + tmpreg = BKP->RTCCR; + /* Clear CCO, ASOE and ASOS bits */ + tmpreg &= RTCCR_MASK; + + /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */ + tmpreg |= BKP_RTCOutputSource; + /* Store the new value */ + BKP->RTCCR = tmpreg; +} + +/** + * @brief Sets RTC Clock Calibration value. + * @param CalibrationValue: specifies the RTC Clock Calibration value. + * This parameter must be a number between 0 and 0x7F. + * @retval None + */ +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); + tmpreg = BKP->RTCCR; + /* Clear CAL[6:0] bits */ + tmpreg &= RTCCR_CAL_MASK; + /* Set CAL[6:0] bits according to CalibrationValue value */ + tmpreg |= CalibrationValue; + /* Store the new value */ + BKP->RTCCR = tmpreg; +} + +/** + * @brief Writes user data to the specified Data Backup Register. + * @param BKP_DR: specifies the Data Backup Register. + * This parameter can be BKP_DRx where x:[1, 42] + * @param Data: data to write + * @retval None + */ +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_BKP_DR(BKP_DR)); + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + *(__IO uint32_t *) tmp = Data; +} + +/** + * @brief Reads data from the specified Data Backup Register. + * @param BKP_DR: specifies the Data Backup Register. + * This parameter can be BKP_DRx where x:[1, 42] + * @retval The content of the specified Data Backup Register + */ +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_BKP_DR(BKP_DR)); + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + return (*(__IO uint16_t *) tmp); +} + +/** + * @brief Checks whether the Tamper Pin Event flag is set or not. + * @param None + * @retval The new state of the Tamper Pin Event flag (SET or RESET). + */ +FlagStatus BKP_GetFlagStatus(void) +{ + return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB); +} + +/** + * @brief Clears Tamper Pin Event pending flag. + * @param None + * @retval None + */ +void BKP_ClearFlag(void) +{ + /* Set CTE bit to clear Tamper Pin Event flag */ + BKP->CSR |= BKP_CSR_CTE; +} + +/** + * @brief Checks whether the Tamper Pin Interrupt has occurred or not. + * @param None + * @retval The new state of the Tamper Pin Interrupt (SET or RESET). + */ +ITStatus BKP_GetITStatus(void) +{ + return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB); +} + +/** + * @brief Clears Tamper Pin Interrupt pending bit. + * @param None + * @retval None + */ +void BKP_ClearITPendingBit(void) +{ + /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ + BKP->CSR |= BKP_CSR_CTI; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_can.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_can.c new file mode 100644 index 0000000..607d692 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_can.c @@ -0,0 +1,1415 @@ +/** + ****************************************************************************** + * @file stm32f10x_can.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the CAN firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_can.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CAN + * @brief CAN driver modules + * @{ + */ + +/** @defgroup CAN_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_Defines + * @{ + */ + +/* CAN Master Control Register bits */ + +#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ + +/* CAN Filter Master Register bits */ +#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ + +/* Time out for INAK bit */ +#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) + + + +/* Flags in TSR register */ +#define CAN_FLAGS_TSR ((uint32_t)0x08000000) +/* Flags in RF1R register */ +#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) +/* Flags in RF0R register */ +#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) +/* Flags in MSR register */ +#define CAN_FLAGS_MSR ((uint32_t)0x01000000) +/* Flags in ESR register */ +#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + + + +#define CAN_MODE_MASK ((uint32_t) 0x00000003) +/** + * @} + */ + +/** @defgroup CAN_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_FunctionPrototypes + * @{ + */ + +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); + +/** + * @} + */ + +/** @defgroup CAN_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the CAN peripheral registers to their default reset values. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @retval None. + */ +void CAN_DeInit(CAN_TypeDef* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + if (CANx == CAN1) + { + /* Enable CAN1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); + /* Release CAN1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); + } + else + { + /* Enable CAN2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); + /* Release CAN2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); + } +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param CANx: where x can be 1 or 2 to to select the CAN + * peripheral. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that + * contains the configuration information for the + * CAN peripheral. + * @retval Constant indicates initialization succeed which will be + * CAN_InitStatus_Failed or CAN_InitStatus_Success. + */ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) +{ + uint8_t InitStatus = CAN_InitStatus_Failed; + uint32_t wait_ack = 0x00000000; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); + assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); + assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); + assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); + assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); + assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); + + /* Exit from sleep mode */ + CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); + + /* Request initialisation */ + CANx->MCR |= CAN_MCR_INRQ ; + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + /* Check acknowledge */ + if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + /* Set the time triggered communication mode */ + if (CAN_InitStruct->CAN_TTCM == ENABLE) + { + CANx->MCR |= CAN_MCR_TTCM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (CAN_InitStruct->CAN_ABOM == ENABLE) + { + CANx->MCR |= CAN_MCR_ABOM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (CAN_InitStruct->CAN_AWUM == ENABLE) + { + CANx->MCR |= CAN_MCR_AWUM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (CAN_InitStruct->CAN_NART == ENABLE) + { + CANx->MCR |= CAN_MCR_NART; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (CAN_InitStruct->CAN_RFLM == ENABLE) + { + CANx->MCR |= CAN_MCR_RFLM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (CAN_InitStruct->CAN_TXFP == ENABLE) + { + CANx->MCR |= CAN_MCR_TXFP; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; + } + + /* Set the bit timing register */ + CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ + ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ + ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ + ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ + ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); + + /* Request leave initialisation */ + CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; + + /* Wait the acknowledge */ + wait_ack = 0; + + while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + /* ...and check acknowledged */ + if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + InitStatus = CAN_InitStatus_Success ; + } + } + + /* At this step, return the status of initialization */ + return InitStatus; +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_FilterInitStruct. + * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef + * structure that contains the configuration + * information. + * @retval None. + */ +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) +{ + uint32_t filter_number_bit_pos = 0; + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); + assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); + + filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; + + /* Initialisation mode for the filter */ + CAN1->FMR |= FMR_FINIT; + + /* Filter Deactivation */ + CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; + + /* Filter Scale */ + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + /* 16-bit scale for the filter */ + CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); + } + + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + /* 32-bit scale for the filter */ + CAN1->FS1R |= filter_number_bit_pos; + /* 32-bit identifier or First 32-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); + } + + /* Filter Mode */ + if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + /*Id/Mask mode for the filter*/ + CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + CAN1->FM1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter FIFO assignment */ + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) + { + /* FIFO 1 assignation for the filter */ + CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter activation */ + if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN1->FA1R |= filter_number_bit_pos; + } + + /* Leave the initialisation mode for the filter */ + CAN1->FMR &= ~FMR_FINIT; +} + +/** + * @brief Fills each CAN_InitStruct member with its default value. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which + * will be initialized. + * @retval None. + */ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ + /* Reset CAN init structure parameters values */ + + /* Initialize the time triggered communication mode */ + CAN_InitStruct->CAN_TTCM = DISABLE; + + /* Initialize the automatic bus-off management */ + CAN_InitStruct->CAN_ABOM = DISABLE; + + /* Initialize the automatic wake-up mode */ + CAN_InitStruct->CAN_AWUM = DISABLE; + + /* Initialize the no automatic retransmission */ + CAN_InitStruct->CAN_NART = DISABLE; + + /* Initialize the receive FIFO locked mode */ + CAN_InitStruct->CAN_RFLM = DISABLE; + + /* Initialize the transmit FIFO priority */ + CAN_InitStruct->CAN_TXFP = DISABLE; + + /* Initialize the CAN_Mode member */ + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + + /* Initialize the CAN_SJW member */ + CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + + /* Initialize the CAN_BS1 member */ + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + + /* Initialize the CAN_BS2 member */ + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + + /* Initialize the CAN_Prescaler member */ + CAN_InitStruct->CAN_Prescaler = 1; +} + +/** + * @brief Select the start bank filter for slave CAN. + * @note This function applies only to STM32 Connectivity line devices. + * @param CAN_BankNumber: Select the start slave bank filter from 1..27. + * @retval None. + */ +void CAN_SlaveStartBank(uint8_t CAN_BankNumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); + + /* Enter Initialisation mode for the filter */ + CAN1->FMR |= FMR_FINIT; + + /* Select the start slave bank */ + CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; + CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; + + /* Leave Initialisation mode for the filter */ + CAN1->FMR &= ~FMR_FINIT; +} + +/** + * @brief Enables or disables the DBG Freeze for CAN. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param NewState: new state of the CAN peripheral. This parameter can + * be: ENABLE or DISABLE. + * @retval None. + */ +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Debug Freeze */ + CANx->MCR |= MCR_DBF; + } + else + { + /* Disable Debug Freeze */ + CANx->MCR &= ~MCR_DBF; + } +} + + +/** + * @brief Enables or disabes the CAN Time TriggerOperation communication mode. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param NewState : Mode new state , can be one of @ref FunctionalState. + * @note when enabled, Time stamp (TIME[15:0]) value is sent in the last + * two data bytes of the 8-byte message: TIME[7:0] in data byte 6 + * and TIME[15:8] in data byte 7 + * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be + * sent over the CAN bus. + * @retval None + */ +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the TTCM mode */ + CANx->MCR |= CAN_MCR_TTCM; + + /* Set TGT bits */ + CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT); + CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT); + CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT); + } + else + { + /* Disable the TTCM mode */ + CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); + + /* Reset TGT bits */ + CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT); + CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT); + CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT); + } +} +/** + * @brief Initiates the transmission of a message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param TxMessage: pointer to a structure which contains CAN Id, CAN + * DLC and CAN data. + * @retval The number of the mailbox that is used for transmission + * or CAN_TxStatus_NoMailBox if there is no empty mailbox. + */ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) +{ + uint8_t transmit_mailbox = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); + assert_param(IS_CAN_RTR(TxMessage->RTR)); + assert_param(IS_CAN_DLC(TxMessage->DLC)); + + /* Select one empty transmit mailbox */ + if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxStatus_NoMailBox; + } + + if (transmit_mailbox != CAN_TxStatus_NoMailBox) + { + /* Set up the Id */ + CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_Id_Standard) + { + assert_param(IS_CAN_STDID(TxMessage->StdId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \ + TxMessage->RTR); + } + else + { + assert_param(IS_CAN_EXTID(TxMessage->ExtId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \ + TxMessage->IDE | \ + TxMessage->RTR); + } + + /* Set up the DLC */ + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; + + /* Set up the data field */ + CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | + ((uint32_t)TxMessage->Data[2] << 16) | + ((uint32_t)TxMessage->Data[1] << 8) | + ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | + ((uint32_t)TxMessage->Data[6] << 16) | + ((uint32_t)TxMessage->Data[5] << 8) | + ((uint32_t)TxMessage->Data[4])); + /* Request transmission */ + CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; + } + return transmit_mailbox; +} + +/** + * @brief Checks the transmission of a message. + * @param CANx: where x can be 1 or 2 to to select the + * CAN peripheral. + * @param TransmitMailbox: the number of the mailbox that is used for + * transmission. + * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed + * in an other case. + */ +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) +{ + uint32_t state = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); + + switch (TransmitMailbox) + { + case (CAN_TXMAILBOX_0): + state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); + break; + case (CAN_TXMAILBOX_1): + state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); + break; + case (CAN_TXMAILBOX_2): + state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); + break; + default: + state = CAN_TxStatus_Failed; + break; + } + switch (state) + { + /* transmit pending */ + case (0x0): state = CAN_TxStatus_Pending; + break; + /* transmit failed */ + case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed; + break; + case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed; + break; + case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed; + break; + /* transmit succeeded */ + case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok; + break; + case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok; + break; + case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok; + break; + default: state = CAN_TxStatus_Failed; + break; + } + return (uint8_t) state; +} + +/** + * @brief Cancels a transmit request. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param Mailbox: Mailbox number. + * @retval None. + */ +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); + /* abort transmission */ + switch (Mailbox) + { + case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0; + break; + case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1; + break; + case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2; + break; + default: + break; + } +} + + +/** + * @brief Receives a message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @param RxMessage: pointer to a structure receive message which contains + * CAN Id, CAN DLC, CAN datas and FMI number. + * @retval None. + */ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Get the Id */ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; + if (RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); + /* Get the data field */ + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); + /* Release the FIFO */ + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CANx->RF0R |= CAN_RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CANx->RF1R |= CAN_RF1R_RFOM1; + } +} + +/** + * @brief Releases the specified FIFO. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. + * @retval None. + */ +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CANx->RF0R |= CAN_RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CANx->RF1R |= CAN_RF1R_RFOM1; + } +} + +/** + * @brief Returns the number of pending messages. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval NbMessage : which is the number of pending message. + */ +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + uint8_t message_pending=0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + if (FIFONumber == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); + } + else if (FIFONumber == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); + } + else + { + message_pending = 0; + } + return message_pending; +} + + +/** + * @brief Select the CAN Operation mode. + * @param CAN_OperatingMode : CAN Operating Mode. This parameter can be one + * of @ref CAN_OperatingMode_TypeDef enumeration. + * @retval status of the requested mode which can be + * - CAN_ModeStatus_Failed CAN failed entering the specific mode + * - CAN_ModeStatus_Success CAN Succeed entering the specific mode + + */ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) +{ + uint8_t status = CAN_ModeStatus_Failed; + + /* Timeout for INAK or also for SLAK bits*/ + uint32_t timeout = INAK_TIMEOUT; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); + + if (CAN_OperatingMode == CAN_OperatingMode_Initialization) + { + /* Request initialisation */ + CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Normal) + { + /* Request leave initialisation and sleep mode and enter Normal mode */ + CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != 0) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) + { + /* Request Sleep mode */ + CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else + { + status = CAN_ModeStatus_Failed; + } + + return (uint8_t) status; +} + +/** + * @brief Enters the low power mode. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval status: CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an + * other case. + */ +uint8_t CAN_Sleep(CAN_TypeDef* CANx) +{ + uint8_t sleepstatus = CAN_Sleep_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Request Sleep mode */ + CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Sleep mode status */ + if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) + { + /* Sleep mode not entered */ + sleepstatus = CAN_Sleep_Ok; + } + /* return sleep mode status */ + return (uint8_t)sleepstatus; +} + +/** + * @brief Wakes the CAN up. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval status: CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an + * other case. + */ +uint8_t CAN_WakeUp(CAN_TypeDef* CANx) +{ + uint32_t wait_slak = SLAK_TIMEOUT; + uint8_t wakeupstatus = CAN_WakeUp_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Wake up request */ + CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + + /* Sleep mode status */ + while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) + { + wait_slak--; + } + if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) + { + /* wake up done : Sleep mode exited */ + wakeupstatus = CAN_WakeUp_Ok; + } + /* return wakeup status */ + return (uint8_t)wakeupstatus; +} + + +/** + * @brief Returns the CANx's last error code (LEC). + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval CAN_ErrorCode: specifies the Error code : + * - CAN_ERRORCODE_NoErr No Error + * - CAN_ERRORCODE_StuffErr Stuff Error + * - CAN_ERRORCODE_FormErr Form Error + * - CAN_ERRORCODE_ACKErr Acknowledgment Error + * - CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error + * - CAN_ERRORCODE_BitDominantErr Bit Dominant Error + * - CAN_ERRORCODE_CRCErr CRC Error + * - CAN_ERRORCODE_SoftwareSetErr Software Set Error + */ + +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) +{ + uint8_t errorcode=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the error code*/ + errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); + + /* Return the error code*/ + return errorcode; +} +/** + * @brief Returns the CANx Receive Error Counter (REC). + * @note In case of an error during reception, this counter is incremented + * by 1 or by 8 depending on the error condition as defined by the CAN + * standard. After every successful reception, the counter is + * decremented by 1 or reset to 120 if its value was higher than 128. + * When the counter value exceeds 127, the CAN controller enters the + * error passive state. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval CAN Receive Error Counter. + */ +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the Receive Error Counter*/ + counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24); + + /* Return the Receive Error Counter*/ + return counter; +} + + +/** + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval LSB of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16); + + /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + return counter; +} + + +/** + * @brief Enables or disables the specified CANx interrupts. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. + * This parameter can be: + * - CAN_IT_TME, + * - CAN_IT_FMP0, + * - CAN_IT_FF0, + * - CAN_IT_FOV0, + * - CAN_IT_FMP1, + * - CAN_IT_FF1, + * - CAN_IT_FOV1, + * - CAN_IT_EWG, + * - CAN_IT_EPV, + * - CAN_IT_LEC, + * - CAN_IT_ERR, + * - CAN_IT_WKU or + * - CAN_IT_SLK. + * @param NewState: new state of the CAN interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IT(CAN_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CANx interrupt */ + CANx->IER |= CAN_IT; + } + else + { + /* Disable the selected CANx interrupt */ + CANx->IER &= ~CAN_IT; + } +} +/** + * @brief Checks whether the specified CAN flag is set or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to check. + * This parameter can be one of the following flags: + * - CAN_FLAG_EWG + * - CAN_FLAG_EPV + * - CAN_FLAG_BOF + * - CAN_FLAG_RQCP0 + * - CAN_FLAG_RQCP1 + * - CAN_FLAG_RQCP2 + * - CAN_FLAG_FMP1 + * - CAN_FLAG_FF1 + * - CAN_FLAG_FOV1 + * - CAN_FLAG_FMP0 + * - CAN_FLAG_FF0 + * - CAN_FLAG_FOV0 + * - CAN_FLAG_WKU + * - CAN_FLAG_SLAK + * - CAN_FLAG_LEC + * @retval The new state of CAN_FLAG (SET or RESET). + */ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); + + + if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ + { + /* Check the status of the specified CAN flag */ + if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + /* Return the CAN_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CAN's pending flags. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to clear. + * This parameter can be one of the following flags: + * - CAN_FLAG_RQCP0 + * - CAN_FLAG_RQCP1 + * - CAN_FLAG_RQCP2 + * - CAN_FLAG_FF1 + * - CAN_FLAG_FOV1 + * - CAN_FLAG_FF0 + * - CAN_FLAG_FOV0 + * - CAN_FLAG_WKU + * - CAN_FLAG_SLAK + * - CAN_FLAG_LEC + * @retval None. + */ +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + uint32_t flagtmp=0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); + + if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ + { + /* Clear the selected CAN flags */ + CANx->ESR = (uint32_t)RESET; + } + else /* MSR or TSR or RF0R or RF1R */ + { + flagtmp = CAN_FLAG & 0x000FFFFF; + + if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET) + { + /* Receive Flags */ + CANx->RF0R = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) + { + /* Receive Flags */ + CANx->RF1R = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) + { + /* Transmit Flags */ + CANx->TSR = (uint32_t)(flagtmp); + } + else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ + { + /* Operating mode Flags */ + CANx->MSR = (uint32_t)(flagtmp); + } + } +} + +/** + * @brief Checks whether the specified CANx interrupt has occurred or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt source to check. + * This parameter can be one of the following flags: + * - CAN_IT_TME + * - CAN_IT_FMP0 + * - CAN_IT_FF0 + * - CAN_IT_FOV0 + * - CAN_IT_FMP1 + * - CAN_IT_FF1 + * - CAN_IT_FOV1 + * - CAN_IT_WKU + * - CAN_IT_SLK + * - CAN_IT_EWG + * - CAN_IT_EPV + * - CAN_IT_BOF + * - CAN_IT_LEC + * - CAN_IT_ERR + * @retval The current state of CAN_IT (SET or RESET). + */ +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + ITStatus itstatus = RESET; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IT(CAN_IT)); + + /* check the enable interrupt bit */ + if((CANx->IER & CAN_IT) != RESET) + { + /* in case the Interrupt is enabled, .... */ + switch (CAN_IT) + { + case CAN_IT_TME: + /* Check CAN_TSR_RQCPx bits */ + itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); + break; + case CAN_IT_FMP0: + /* Check CAN_RF0R_FMP0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); + break; + case CAN_IT_FF0: + /* Check CAN_RF0R_FULL0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); + break; + case CAN_IT_FOV0: + /* Check CAN_RF0R_FOVR0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); + break; + case CAN_IT_FMP1: + /* Check CAN_RF1R_FMP1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); + break; + case CAN_IT_FF1: + /* Check CAN_RF1R_FULL1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); + break; + case CAN_IT_FOV1: + /* Check CAN_RF1R_FOVR1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); + break; + case CAN_IT_WKU: + /* Check CAN_MSR_WKUI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); + break; + case CAN_IT_SLK: + /* Check CAN_MSR_SLAKI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); + break; + case CAN_IT_EWG: + /* Check CAN_ESR_EWGF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); + break; + case CAN_IT_EPV: + /* Check CAN_ESR_EPVF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); + break; + case CAN_IT_BOF: + /* Check CAN_ESR_BOFF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); + break; + case CAN_IT_LEC: + /* Check CAN_ESR_LEC bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); + break; + case CAN_IT_ERR: + /* Check CAN_MSR_ERRI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); + break; + default : + /* in case of error, return RESET */ + itstatus = RESET; + break; + } + } + else + { + /* in case the Interrupt is not enabled, return RESET */ + itstatus = RESET; + } + + /* Return the CAN_IT status */ + return itstatus; +} + +/** + * @brief Clears the CANx's interrupt pending bits. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the interrupt pending bit to clear. + * - CAN_IT_TME + * - CAN_IT_FF0 + * - CAN_IT_FOV0 + * - CAN_IT_FF1 + * - CAN_IT_FOV1 + * - CAN_IT_WKU + * - CAN_IT_SLK + * - CAN_IT_EWG + * - CAN_IT_EPV + * - CAN_IT_BOF + * - CAN_IT_LEC + * - CAN_IT_ERR + * @retval None. + */ +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_IT(CAN_IT)); + + switch (CAN_IT) + { + case CAN_IT_TME: + /* Clear CAN_TSR_RQCPx (rc_w1)*/ + CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; + break; + case CAN_IT_FF0: + /* Clear CAN_RF0R_FULL0 (rc_w1)*/ + CANx->RF0R = CAN_RF0R_FULL0; + break; + case CAN_IT_FOV0: + /* Clear CAN_RF0R_FOVR0 (rc_w1)*/ + CANx->RF0R = CAN_RF0R_FOVR0; + break; + case CAN_IT_FF1: + /* Clear CAN_RF1R_FULL1 (rc_w1)*/ + CANx->RF1R = CAN_RF1R_FULL1; + break; + case CAN_IT_FOV1: + /* Clear CAN_RF1R_FOVR1 (rc_w1)*/ + CANx->RF1R = CAN_RF1R_FOVR1; + break; + case CAN_IT_WKU: + /* Clear CAN_MSR_WKUI (rc_w1)*/ + CANx->MSR = CAN_MSR_WKUI; + break; + case CAN_IT_SLK: + /* Clear CAN_MSR_SLAKI (rc_w1)*/ + CANx->MSR = CAN_MSR_SLAKI; + break; + case CAN_IT_EWG: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_IT_EPV: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_IT_BOF: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_IT_LEC: + /* Clear LEC bits */ + CANx->ESR = RESET; + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + break; + case CAN_IT_ERR: + /*Clear LEC bits */ + CANx->ESR = RESET; + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending + of the CAN Bus status*/ + break; + default : + break; + } +} + +/** + * @brief Checks whether the CAN interrupt has occurred or not. + * @param CAN_Reg: specifies the CAN interrupt register to check. + * @param It_Bit: specifies the interrupt source bit to check. + * @retval The new state of the CAN Interrupt (SET or RESET). + */ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if ((CAN_Reg & It_Bit) != (uint32_t)RESET) + { + /* CAN_IT is set */ + pendingbitstatus = SET; + } + else + { + /* CAN_IT is reset */ + pendingbitstatus = RESET; + } + return pendingbitstatus; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_cec.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_cec.c new file mode 100644 index 0000000..08b501a --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_cec.c @@ -0,0 +1,433 @@ +/** + ****************************************************************************** + * @file stm32f10x_cec.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the CEC firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_cec.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CEC + * @brief CEC driver modules + * @{ + */ + +/** @defgroup CEC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Defines + * @{ + */ + +/* ------------ CEC registers bit address in the alias region ----------- */ +#define CEC_OFFSET (CEC_BASE - PERIPH_BASE) + +/* --- CFGR Register ---*/ + +/* Alias word address of PE bit */ +#define CFGR_OFFSET (CEC_OFFSET + 0x00) +#define PE_BitNumber 0x00 +#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4)) + +/* Alias word address of IE bit */ +#define IE_BitNumber 0x01 +#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of TSOM bit */ +#define CSR_OFFSET (CEC_OFFSET + 0x10) +#define TSOM_BitNumber 0x00 +#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4)) + +/* Alias word address of TEOM bit */ +#define TEOM_BitNumber 0x01 +#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4)) + +#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Macros + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Variables + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the CEC peripheral registers to their default reset + * values. + * @param None + * @retval None + */ +void CEC_DeInit(void) +{ + /* Enable CEC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); + /* Release CEC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); +} + + +/** + * @brief Initializes the CEC peripheral according to the specified + * parameters in the CEC_InitStruct. + * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that + * contains the configuration information for the specified + * CEC peripheral. + * @retval None + */ +void CEC_Init(CEC_InitTypeDef* CEC_InitStruct) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); + assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode)); + + /*---------------------------- CEC CFGR Configuration -----------------*/ + /* Get the CEC CFGR value */ + tmpreg = CEC->CFGR; + + /* Clear BTEM and BPEM bits */ + tmpreg &= CFGR_CLEAR_Mask; + + /* Configure CEC: Bit Timing Error and Bit Period Error */ + tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode); + + /* Write to CEC CFGR register*/ + CEC->CFGR = tmpreg; + +} + +/** + * @brief Enables or disables the specified CEC peripheral. + * @param NewState: new state of the CEC peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState; + + if(NewState == DISABLE) + { + /* Wait until the PE bit is cleared by hardware (Idle Line detected) */ + while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET) + { + } + } +} + +/** + * @brief Enables or disables the CEC interrupt. + * @param NewState: new state of the CEC interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState; +} + +/** + * @brief Defines the Own Address of the CEC device. + * @param CEC_OwnAddress: The CEC own address + * @retval None + */ +void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress) +{ + /* Check the parameters */ + assert_param(IS_CEC_ADDRESS(CEC_OwnAddress)); + + /* Set the CEC own address */ + CEC->OAR = CEC_OwnAddress; +} + +/** + * @brief Sets the CEC prescaler value. + * @param CEC_Prescaler: CEC prescaler new value + * @retval None + */ +void CEC_SetPrescaler(uint16_t CEC_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_CEC_PRESCALER(CEC_Prescaler)); + + /* Set the Prescaler value*/ + CEC->PRES = CEC_Prescaler; +} + +/** + * @brief Transmits single data through the CEC peripheral. + * @param Data: the data to transmit. + * @retval None + */ +void CEC_SendDataByte(uint8_t Data) +{ + /* Transmit Data */ + CEC->TXD = Data ; +} + + +/** + * @brief Returns the most recent received data by the CEC peripheral. + * @param None + * @retval The received data. + */ +uint8_t CEC_ReceiveDataByte(void) +{ + /* Receive Data */ + return (uint8_t)(CEC->RXD); +} + +/** + * @brief Starts a new message. + * @param None + * @retval None + */ +void CEC_StartOfMessage(void) +{ + /* Starts of new message */ + *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1; +} + +/** + * @brief Transmits message with or without an EOM bit. + * @param NewState: new state of the CEC Tx End Of Message. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_EndOfMessageCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* The data byte will be transmitted with or without an EOM bit*/ + *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState; +} + +/** + * @brief Gets the CEC flag status + * @param CEC_FLAG: specifies the CEC flag to check. + * This parameter can be one of the following values: + * @arg CEC_FLAG_BTE: Bit Timing Error + * @arg CEC_FLAG_BPE: Bit Period Error + * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error + * @arg CEC_FLAG_SBE: Start Bit Error + * @arg CEC_FLAG_ACKE: Block Acknowledge Error + * @arg CEC_FLAG_LINE: Line Error + * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error + * @arg CEC_FLAG_TEOM: Tx End Of Message + * @arg CEC_FLAG_TERR: Tx Error + * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished + * @arg CEC_FLAG_RSOM: Rx Start Of Message + * @arg CEC_FLAG_REOM: Rx End Of Message + * @arg CEC_FLAG_RERR: Rx Error + * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished + * @retval The new state of CEC_FLAG (SET or RESET) + */ +FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t cecreg = 0, cecbase = 0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_FLAG(CEC_FLAG)); + + /* Get the CEC peripheral base address */ + cecbase = (uint32_t)(CEC_BASE); + + /* Read flag register index */ + cecreg = CEC_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + CEC_FLAG &= FLAG_Mask; + + if(cecreg != 0) + { + /* Flag in CEC ESR Register */ + CEC_FLAG = (uint32_t)(CEC_FLAG >> 16); + + /* Get the CEC ESR register address */ + cecbase += 0xC; + } + else + { + /* Get the CEC CSR register address */ + cecbase += 0x10; + } + + if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET) + { + /* CEC_FLAG is set */ + bitstatus = SET; + } + else + { + /* CEC_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the CEC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CEC's pending flags. + * @param CEC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg CEC_FLAG_TERR: Tx Error + * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished + * @arg CEC_FLAG_RSOM: Rx Start Of Message + * @arg CEC_FLAG_REOM: Rx End Of Message + * @arg CEC_FLAG_RERR: Rx Error + * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished + * @retval None + */ +void CEC_ClearFlag(uint32_t CEC_FLAG) +{ + uint32_t tmp = 0x0; + + /* Check the parameters */ + assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG)); + + tmp = CEC->CSR & 0x2; + + /* Clear the selected CEC flags */ + CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp); +} + +/** + * @brief Checks whether the specified CEC interrupt has occurred or not. + * @param CEC_IT: specifies the CEC interrupt source to check. + * This parameter can be one of the following values: + * @arg CEC_IT_TERR: Tx Error + * @arg CEC_IT_TBTF: Tx Block Transfer Finished + * @arg CEC_IT_RERR: Rx Error + * @arg CEC_IT_RBTF: Rx Block Transfer Finished + * @retval The new state of CEC_IT (SET or RESET). + */ +ITStatus CEC_GetITStatus(uint8_t CEC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_IT(CEC_IT)); + + /* Get the CEC IT enable bit status */ + enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ; + + /* Check the status of the specified CEC interrupt */ + if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus) + { + /* CEC_IT is set */ + bitstatus = SET; + } + else + { + /* CEC_IT is reset */ + bitstatus = RESET; + } + /* Return the CEC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the CEC's interrupt pending bits. + * @param CEC_IT: specifies the CEC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg CEC_IT_TERR: Tx Error + * @arg CEC_IT_TBTF: Tx Block Transfer Finished + * @arg CEC_IT_RERR: Rx Error + * @arg CEC_IT_RBTF: Rx Block Transfer Finished + * @retval None + */ +void CEC_ClearITPendingBit(uint16_t CEC_IT) +{ + uint32_t tmp = 0x0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_IT(CEC_IT)); + + tmp = CEC->CSR & 0x2; + + /* Clear the selected CEC interrupt pending bits */ + CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_crc.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_crc.c new file mode 100644 index 0000000..ef0c047 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_crc.c @@ -0,0 +1,160 @@ +/** + ****************************************************************************** + * @file stm32f10x_crc.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the CRC firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_crc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRC + * @brief CRC driver modules + * @{ + */ + +/** @defgroup CRC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Functions + * @{ + */ + +/** + * @brief Resets the CRC Data register (DR). + * @param None + * @retval None + */ +void CRC_ResetDR(void) +{ + /* Reset CRC generator */ + CRC->CR = CRC_CR_RESET; +} + +/** + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * @param Data: data word(32-bit) to compute its CRC + * @retval 32-bit CRC + */ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DR = Data; + + return (CRC->DR); +} + +/** + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * @param pBuffer: pointer to the buffer containing the data to be computed + * @param BufferLength: length of the buffer to be computed + * @retval 32-bit CRC + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++) + { + CRC->DR = pBuffer[index]; + } + return (CRC->DR); +} + +/** + * @brief Returns the current CRC value. + * @param None + * @retval 32-bit CRC + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DR); +} + +/** + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * @param IDValue: 8-bit value to be stored in the ID register + * @retval None + */ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDR = IDValue; +} + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register + * @param None + * @retval 8-bit value of the ID register + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDR); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_dac.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_dac.c new file mode 100644 index 0000000..025b8e2 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_dac.c @@ -0,0 +1,571 @@ +/** + ****************************************************************************** + * @file stm32f10x_dac.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the DAC firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dac.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DAC + * @brief DAC driver modules + * @{ + */ + +/** @defgroup DAC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Defines + * @{ + */ + +/* CR register Mask */ +#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) + +/* DAC Dual Channels SWTRIG masks */ +#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) +#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) + +/* DHR registers offsets */ +#define DHR12R1_OFFSET ((uint32_t)0x00000008) +#define DHR12R2_OFFSET ((uint32_t)0x00000014) +#define DHR12RD_OFFSET ((uint32_t)0x00000020) + +/* DOR register offset */ +#define DOR_OFFSET ((uint32_t)0x0000002C) +/** + * @} + */ + +/** @defgroup DAC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DAC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void DAC_DeInit(void) +{ + /* Enable DAC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); + /* Release DAC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); +} + +/** + * @brief Initializes the DAC peripheral according to the specified + * parameters in the DAC_InitStruct. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that + * contains the configuration information for the specified DAC channel. + * @retval None + */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); + assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); +/*---------------------------- DAC CR Configuration --------------------------*/ + /* Get the DAC CR value */ + tmpreg1 = DAC->CR; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); + /* Configure for the selected DAC channel: buffer output, trigger, wave generation, + mask/amplitude for wave generation */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set WAVEx bits according to DAC_WaveGeneration value */ + /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << DAC_Channel; + /* Write to DAC CR */ + DAC->CR = tmpreg1; +} + +/** + * @brief Fills each DAC_InitStruct member with its default value. + * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) +{ +/*--------------- Reset DAC init structure parameters values -----------------*/ + /* Initialize the DAC_Trigger member */ + DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; + /* Initialize the DAC_WaveGeneration member */ + DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; + /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; + /* Initialize the DAC_OutputBuffer member */ + DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +} + +/** + * @brief Enables or disables the specified DAC channel. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the DAC channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DAC channel */ + DAC->CR |= (DAC_CR_EN1 << DAC_Channel); + } + else + { + /* Disable the selected DAC channel */ + DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel); + } +} +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/** + * @brief Enables or disables the specified DAC interrupts. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @param NewState: new state of the specified DAC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_DAC_IT(DAC_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC interrupts */ + DAC->CR |= (DAC_IT << DAC_Channel); + } + else + { + /* Disable the selected DAC interrupts */ + DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); + } +} +#endif + +/** + * @brief Enables or disables the specified DAC channel DMA request. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel DMA request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DAC channel DMA request */ + DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); + } + else + { + /* Disable the selected DAC channel DMA request */ + DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel); + } +} + +/** + * @brief Enables or disables the selected DAC channel software trigger. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel software trigger. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable software trigger for the selected DAC channel */ + DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); + } + else + { + /* Disable software trigger for the selected DAC channel */ + DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); + } +} + +/** + * @brief Enables or disables simultaneously the two DAC channels software + * triggers. + * @param NewState: new state of the DAC channels software triggers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable software trigger for both DAC channels */ + DAC->SWTRIGR |= DUAL_SWTRIG_SET ; + } + else + { + /* Disable software trigger for both DAC channels */ + DAC->SWTRIGR &= DUAL_SWTRIG_RESET; + } +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_Wave: Specifies the wave type to enable or disable. + * This parameter can be one of the following values: + * @arg DAC_Wave_Noise: noise wave generation + * @arg DAC_Wave_Triangle: triangle wave generation + * @param NewState: new state of the selected DAC channel wave generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_WAVE(DAC_Wave)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected wave generation for the selected DAC channel */ + DAC->CR |= DAC_Wave << DAC_Channel; + } + else + { + /* Disable the selected wave generation for the selected DAC channel */ + DAC->CR &= ~(DAC_Wave << DAC_Channel); + } +} + +/** + * @brief Set the specified data holding register value for DAC channel1. + * @param DAC_Align: Specifies the data alignment for DAC channel1. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data : Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R1_OFFSET + DAC_Align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t *) tmp = Data; +} + +/** + * @brief Set the specified data holding register value for DAC channel2. + * @param DAC_Align: Specifies the data alignment for DAC channel2. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data : Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R2_OFFSET + DAC_Align; + + /* Set the DAC channel2 selected data holding register */ + *(__IO uint32_t *)tmp = Data; +} + +/** + * @brief Set the specified data holding register value for dual channel + * DAC. + * @param DAC_Align: Specifies the data alignment for dual channel DAC. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data2: Data for DAC Channel2 to be loaded in the selected data + * holding register. + * @param Data1: Data for DAC Channel1 to be loaded in the selected data + * holding register. + * @retval None + */ +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) +{ + uint32_t data = 0, tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (DAC_Align == DAC_Align_8b_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12RD_OFFSET + DAC_Align; + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; +} + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @retval The selected DAC channel data output value. + */ +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + + tmp = (uint32_t) DAC_BASE ; + tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); + + /* Returns the DAC channel data output register value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/** + * @brief Checks whether the specified DAC flag is set or not. + * @param DAC_Channel: thee selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to check. + * This parameter can be only of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @retval The new state of DAC_FLAG (SET or RESET). + */ +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Check the status of the specified DAC flag */ + if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) + { + /* DAC_FLAG is set */ + bitstatus = SET; + } + else + { + /* DAC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the DAC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channelx's pending flags. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to clear. + * This parameter can be of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @retval None + */ +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Clear the selected DAC flags */ + DAC->SR = (DAC_FLAG << DAC_Channel); +} + +/** + * @brief Checks whether the specified DAC interrupt has occurred or not. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt source to check. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @retval The new state of DAC_IT (SET or RESET). + */ +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Get the DAC_IT enable bit status */ + enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; + + /* Check the status of the specified DAC interrupt */ + if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) + { + /* DAC_IT is set */ + bitstatus = SET; + } + else + { + /* DAC_IT is reset */ + bitstatus = RESET; + } + /* Return the DAC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channelx's interrupt pending bits. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt pending bit to clear. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @retval None + */ +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Clear the selected DAC interrupt pending bits */ + DAC->SR = (DAC_IT << DAC_Channel); +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_dbgmcu.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_dbgmcu.c new file mode 100644 index 0000000..d34307b --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_dbgmcu.c @@ -0,0 +1,162 @@ +/** + ****************************************************************************** + * @file stm32f10x_dbgmcu.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the DBGMCU firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dbgmcu.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DBGMCU + * @brief DBGMCU driver modules + * @{ + */ + +/** @defgroup DBGMCU_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Defines + * @{ + */ + +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Functions + * @{ + */ + +/** + * @brief Returns the device revision identifier. + * @param None + * @retval Device revision identifier + */ +uint32_t DBGMCU_GetREVID(void) +{ + return(DBGMCU->IDCODE >> 16); +} + +/** + * @brief Returns the device identifier. + * @param None + * @retval Device identifier + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); +} + +/** + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * @param DBGMCU_Periph: specifies the peripheral and low power mode. + * This parameter can be any combination of the following values: + * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode + * @arg DBGMCU_STOP: Keep debugger connection during STOP mode + * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode + * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted + * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted + * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted + * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted + * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted + * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted + * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted + * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted + * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted + * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted + * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted + * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted + * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted + * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted + * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted + * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted + * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted + * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted + * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted + * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted + * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted + * @param NewState: new state of the specified peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->CR |= DBGMCU_Periph; + } + else + { + DBGMCU->CR &= ~DBGMCU_Periph; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_dma.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_dma.c new file mode 100644 index 0000000..0c86f90 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_dma.c @@ -0,0 +1,714 @@ +/** + ****************************************************************************** + * @file stm32f10x_dma.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the DMA firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dma.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DMA + * @brief DMA driver modules + * @{ + */ + +/** @defgroup DMA_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup DMA_Private_Defines + * @{ + */ + + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) + +/* DMA2 Channelx interrupt pending bit masks */ +#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) +#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) +#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) +#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) +#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) + +/* DMA2 FLAG mask */ +#define FLAG_Mask ((uint32_t)0x10000000) + +/* DMA registers Masks */ +#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/** + * @} + */ + +/** @defgroup DMA_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DMAy Channelx registers to their default reset + * values. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @retval None + */ +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); + + /* Reset DMAy Channelx control register */ + DMAy_Channelx->CCR = 0; + + /* Reset DMAy Channelx remaining bytes register */ + DMAy_Channelx->CNDTR = 0; + + /* Reset DMAy Channelx peripheral address register */ + DMAy_Channelx->CPAR = 0; + + /* Reset DMAy Channelx memory address register */ + DMAy_Channelx->CMAR = 0; + + if (DMAy_Channelx == DMA1_Channel1) + { + /* Reset interrupt pending bits for DMA1 Channel1 */ + DMA1->IFCR |= DMA1_Channel1_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel2) + { + /* Reset interrupt pending bits for DMA1 Channel2 */ + DMA1->IFCR |= DMA1_Channel2_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel3) + { + /* Reset interrupt pending bits for DMA1 Channel3 */ + DMA1->IFCR |= DMA1_Channel3_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel4) + { + /* Reset interrupt pending bits for DMA1 Channel4 */ + DMA1->IFCR |= DMA1_Channel4_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel5) + { + /* Reset interrupt pending bits for DMA1 Channel5 */ + DMA1->IFCR |= DMA1_Channel5_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel6) + { + /* Reset interrupt pending bits for DMA1 Channel6 */ + DMA1->IFCR |= DMA1_Channel6_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel7) + { + /* Reset interrupt pending bits for DMA1 Channel7 */ + DMA1->IFCR |= DMA1_Channel7_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel1) + { + /* Reset interrupt pending bits for DMA2 Channel1 */ + DMA2->IFCR |= DMA2_Channel1_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel2) + { + /* Reset interrupt pending bits for DMA2 Channel2 */ + DMA2->IFCR |= DMA2_Channel2_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel3) + { + /* Reset interrupt pending bits for DMA2 Channel3 */ + DMA2->IFCR |= DMA2_Channel3_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel4) + { + /* Reset interrupt pending bits for DMA2 Channel4 */ + DMA2->IFCR |= DMA2_Channel4_IT_Mask; + } + else + { + if (DMAy_Channelx == DMA2_Channel5) + { + /* Reset interrupt pending bits for DMA2 Channel5 */ + DMA2->IFCR |= DMA2_Channel5_IT_Mask; + } + } +} + +/** + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that + * contains the configuration information for the specified DMA Channel. + * @retval None + */ +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); + assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); + assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); + assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); + +/*--------------------------- DMAy Channelx CCR Configuration -----------------*/ + /* Get the DMAy_Channelx CCR value */ + tmpreg = DMAy_Channelx->CCR; + /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpreg &= CCR_CLEAR_Mask; + /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ + /* Set DIR bit according to DMA_DIR value */ + /* Set CIRC bit according to DMA_Mode value */ + /* Set PINC bit according to DMA_PeripheralInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to DMA_PeripheralDataSize value */ + /* Set MSIZE bits according to DMA_MemoryDataSize value */ + /* Set PL bits according to DMA_Priority value */ + /* Set the MEM2MEM bit according to DMA_M2M value */ + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + /* Write to DMAy Channelx CCR */ + DMAy_Channelx->CCR = tmpreg; + +/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; + +/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ + /* Write to DMAy Channelx CPAR */ + DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; + +/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ + /* Write to DMAy Channelx CMAR */ + DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/** + * @brief Fills each DMA_InitStruct member with its default value. + * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ +/*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + /* Initialize the DMA_MemoryBaseAddr member */ + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + /* Initialize the DMA_MemoryInc member */ + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + /* Initialize the DMA_Priority member */ + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + /* Initialize the DMA_M2M member */ + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/** + * @brief Enables or disables the specified DMAy Channelx. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param NewState: new state of the DMAy Channelx. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMAy Channelx */ + DMAy_Channelx->CCR |= DMA_CCR1_EN; + } + else + { + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); + } +} + +/** + * @brief Enables or disables the specified DMAy Channelx interrupts. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DMA_IT: specifies the DMA interrupts sources to be enabled + * or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @param NewState: new state of the specified DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_CONFIG_IT(DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMAy_Channelx->CCR |= DMA_IT; + } + else + { + /* Disable the selected DMA interrupts */ + DMAy_Channelx->CCR &= ~DMA_IT; + } +} + +/** + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DataNumber: The number of data units in the current DMAy Channelx + * transfer. + * @note This function can only be used when the DMAy_Channelx is disabled. + * @retval None. + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + +/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DataNumber; +} + +/** + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @retval The number of remaining data units in the current DMAy Channelx + * transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + /* Return the number of remaining data units for DMAy Channelx */ + return ((uint16_t)(DMAy_Channelx->CNDTR)); +} + +/** + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * @param DMAy_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. + * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. + * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. + * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. + * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. + * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. + * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. + * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. + * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. + * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. + * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. + * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. + * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. + * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. + * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. + * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. + * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. + * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. + * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. + * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. + * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. + * @retval The new state of DMAy_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_GET_FLAG(DMAy_FLAG)); + + /* Calculate the used DMAy */ + if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + /* Get DMA2 ISR register value */ + tmpreg = DMA2->ISR ; + } + else + { + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR ; + } + + /* Check the status of the specified DMAy flag */ + if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET) + { + /* DMAy_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMAy_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the DMAy_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelx's pending flags. + * @param DMAy_FLAG: specifies the flag to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. + * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. + * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. + * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. + * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. + * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. + * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. + * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. + * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. + * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. + * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. + * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. + * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. + * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. + * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. + * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. + * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. + * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. + * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. + * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. + * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. + * @retval None + */ +void DMA_ClearFlag(uint32_t DMAy_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG)); + + /* Calculate the used DMAy */ + if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + /* Clear the selected DMAy flags */ + DMA2->IFCR = DMAy_FLAG; + } + else + { + /* Clear the selected DMAy flags */ + DMA1->IFCR = DMAy_FLAG; + } +} + +/** + * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. + * @param DMAy_IT: specifies the DMAy interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. + * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. + * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. + * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. + * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. + * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. + * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. + * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. + * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. + * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. + * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. + * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. + * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. + * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. + * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. + * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. + * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. + * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. + * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. + * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. + * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. + * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. + * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. + * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. + * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. + * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. + * @retval The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_GET_IT(DMAy_IT)); + + /* Calculate the used DMA */ + if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) + { + /* Get DMA2 ISR register value */ + tmpreg = DMA2->ISR; + } + else + { + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR; + } + + /* Check the status of the specified DMAy interrupt */ + if ((tmpreg & DMAy_IT) != (uint32_t)RESET) + { + /* DMAy_IT is set */ + bitstatus = SET; + } + else + { + /* DMAy_IT is reset */ + bitstatus = RESET; + } + /* Return the DMA_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelx's interrupt pending bits. + * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. + * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. + * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. + * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. + * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. + * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. + * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. + * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. + * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. + * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. + * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. + * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. + * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. + * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. + * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. + * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. + * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. + * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. + * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. + * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. + * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. + * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. + * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. + * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. + * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. + * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. + * @retval None + */ +void DMA_ClearITPendingBit(uint32_t DMAy_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_IT(DMAy_IT)); + + /* Calculate the used DMAy */ + if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) + { + /* Clear the selected DMAy interrupt pending bits */ + DMA2->IFCR = DMAy_IT; + } + else + { + /* Clear the selected DMAy interrupt pending bits */ + DMA1->IFCR = DMAy_IT; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_exti.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_exti.c new file mode 100644 index 0000000..ab73462 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_exti.c @@ -0,0 +1,269 @@ +/** + ****************************************************************************** + * @file stm32f10x_exti.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the EXTI firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_exti.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup EXTI + * @brief EXTI driver modules + * @{ + */ + +/** @defgroup EXTI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Defines + * @{ + */ + +#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the EXTI peripheral registers to their default reset values. + * @param None + * @retval None + */ +void EXTI_DeInit(void) +{ + EXTI->IMR = 0x00000000; + EXTI->EMR = 0x00000000; + EXTI->RTSR = 0x00000000; + EXTI->FTSR = 0x00000000; + EXTI->PR = 0x000FFFFF; +} + +/** + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * that contains the configuration information for the EXTI peripheral. + * @retval None + */ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + tmp = (uint32_t)EXTI_BASE; + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; + + tmp += EXTI_InitStruct->EXTI_Mode; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + + /* Disable the selected external lines */ + *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/** + * @brief Fills each EXTI_InitStruct member with its reset value. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** + * @brief Generates a Software interrupt. + * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIER |= EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param EXTI_Line: specifies the EXTI line flag to check. + * This parameter can be: + * @arg EXTI_Linex: External interrupt line x where x(0..19) + * @retval The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending flags. + * @param EXTI_Line: specifies the EXTI lines flags to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param EXTI_Line: specifies the EXTI line to check. + * This parameter can be: + * @arg EXTI_Linex: External interrupt line x where x(0..19) + * @retval The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + enablestatus = EXTI->IMR & EXTI_Line; + if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending bits. + * @param EXTI_Line: specifies the EXTI lines to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_flash.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_flash.c new file mode 100644 index 0000000..f6c7bf1 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_flash.c @@ -0,0 +1,1684 @@ +/** + ****************************************************************************** + * @file stm32f10x_flash.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the FLASH firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_flash.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup FLASH + * @brief FLASH driver modules + * @{ + */ + +/** @defgroup FLASH_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Defines + * @{ + */ + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0x00000038) +#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7) +#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF) + +/* Flash Access Control Register bits */ +#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0x00001FFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0x00001FFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0x00001FFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0x00001FEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0x00001FDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) +#define OB_USER_BFB2 ((uint16_t)0x0008) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) +/** + * @} + */ + +/** @defgroup FLASH_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Functions + * @{ + */ + +/** +@code + + This driver provides functions to configure and program the Flash memory of all STM32F10x devices, + including the latest STM32F10x_XL density devices. + + STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability: + - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each) + - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each) + While other STM32F10x devices features only one bank with memory up to 512 Kbytes. + + In version V3.3.0, some functions were updated and new ones were added to support + STM32F10x_XL devices. Thus some functions manages all devices, while other are + dedicated for XL devices only. + + The table below presents the list of available functions depending on the used STM32F10x devices. + + *************************************************** + * Legacy functions used for all STM32F10x devices * + *************************************************** + +----------------------------------------------------------------------------------------------------------------------------------+ + | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | + | | devices | devices | | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_SetLatency | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_HalfCycleAccessCmd | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_PrefetchBufferCmd | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_Unlock | Yes | Yes | - For STM32F10X_XL devices: unlock Bank1 and Bank2. | + | | | | - For other devices: unlock Bank1 and it is equivalent | + | | | | to FLASH_UnlockBank1 function. | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_Lock | Yes | Yes | - For STM32F10X_XL devices: lock Bank1 and Bank2. | + | | | | - For other devices: lock Bank1 and it is equivalent | + | | | | to FLASH_LockBank1 function. | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ErasePage | Yes | Yes | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2 | + | | | | - For other devices: erase a page in Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_EraseAllPages | Yes | Yes | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 | + | | | | - For other devices: erase all pages in Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_EraseOptionBytes | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ProgramWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ProgramHalfWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ProgramOptionByteData | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_EnableWriteProtection | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ReadOutProtection | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_UserOptionByteConfig | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetUserOptionByte | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetWriteProtectionOptionByte | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetReadOutProtectionStatus | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetPrefetchBufferStatus | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ITConfig | Yes | Yes | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts| + | | | | - For other devices: enable Bank1's interrupts | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetFlagStatus | Yes | Yes | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status| + | | | | - For other devices: return Bank1's flag status | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ClearFlag | Yes | Yes | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag | + | | | | - For other devices: clear Bank1's flag | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetStatus | Yes | Yes | - Return the status of Bank1 (for all devices) | + | | | | equivalent to FLASH_GetBank1Status function | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_WaitForLastOperation | Yes | Yes | - Wait for Bank1 last operation (for all devices) | + | | | | equivalent to: FLASH_WaitForLastBank1Operation function | + +----------------------------------------------------------------------------------------------------------------------------------+ + + ************************************************************************************************************************ + * New functions used for all STM32F10x devices to manage Bank1: * + * - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 * + * - For other devices, these functions are optional (covered by functions listed above) * + ************************************************************************************************************************ + +----------------------------------------------------------------------------------------------------------------------------------+ + | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | + | | devices | devices | | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_UnlockBank1 | Yes | Yes | - Unlock Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_LockBank1 | Yes | Yes | - Lock Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_EraseAllBank1Pages | Yes | Yes | - Erase all pages in Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_GetBank1Status | Yes | Yes | - Return the status of Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_WaitForLastBank1Operation | Yes | Yes | - Wait for Bank1 last operation | + +----------------------------------------------------------------------------------------------------------------------------------+ + + ***************************************************************************** + * New Functions used only with STM32F10x_XL density devices to manage Bank2 * + ***************************************************************************** + +----------------------------------------------------------------------------------------------------------------------------------+ + | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | + | | devices | devices | | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_UnlockBank2 | Yes | No | - Unlock Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_LockBank2 | Yes | No | - Lock Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_EraseAllBank2Pages | Yes | No | - Erase all pages in Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_GetBank2Status | Yes | No | - Return the status of Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_WaitForLastBank2Operation | Yes | No | - Wait for Bank2 last operation | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_BootConfig | Yes | No | - Configure to boot from Bank1 or Bank2 | + +----------------------------------------------------------------------------------------------------------------------------------+ +@endcode +*/ + + +/** + * @brief Sets the code latency value. + * @note This function can be used for all STM32F10x devices. + * @param FLASH_Latency: specifies the FLASH Latency value. + * This parameter can be one of the following values: + * @arg FLASH_Latency_0: FLASH Zero Latency cycle + * @arg FLASH_Latency_1: FLASH One Latency cycle + * @arg FLASH_Latency_2: FLASH Two Latency cycles + * @retval None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + /* Read the ACR register */ + tmpreg = FLASH->ACR; + + /* Sets the Latency value */ + tmpreg &= ACR_LATENCY_Mask; + tmpreg |= FLASH_Latency; + + /* Write the ACR register */ + FLASH->ACR = tmpreg; +} + +/** + * @brief Enables or disables the Half cycle flash access. + * @note This function can be used for all STM32F10x devices. + * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode. + * This parameter can be one of the following values: + * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable + * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable + * @retval None + */ +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess) +{ + /* Check the parameters */ + assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess)); + + /* Enable or disable the Half cycle access */ + FLASH->ACR &= ACR_HLFCYA_Mask; + FLASH->ACR |= FLASH_HalfCycleAccess; +} + +/** + * @brief Enables or disables the Prefetch Buffer. + * @note This function can be used for all STM32F10x devices. + * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status. + * This parameter can be one of the following values: + * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable + * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable + * @retval None + */ +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer) +{ + /* Check the parameters */ + assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer)); + + /* Enable or disable the Prefetch Buffer */ + FLASH->ACR &= ACR_PRFTBE_Mask; + FLASH->ACR |= FLASH_PrefetchBuffer; +} + +/** + * @brief Unlocks the FLASH Program Erase Controller. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function unlocks Bank1 and Bank2. + * - For all other devices it unlocks Bank1 and it is equivalent + * to FLASH_UnlockBank1 function.. + * @param None + * @retval None + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + +#ifdef STM32F10X_XL + /* Authorize the FPEC of Bank2 Access */ + FLASH->KEYR2 = FLASH_KEY1; + FLASH->KEYR2 = FLASH_KEY2; +#endif /* STM32F10X_XL */ +} +/** + * @brief Unlocks the FLASH Bank1 Program Erase Controller. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function unlocks Bank1. + * - For all other devices it unlocks Bank1 and it is + * equivalent to FLASH_Unlock function. + * @param None + * @retval None + */ +void FLASH_UnlockBank1(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +#ifdef STM32F10X_XL +/** + * @brief Unlocks the FLASH Bank2 Program Erase Controller. + * @note This function can be used only for STM32F10X_XL density devices. + * @param None + * @retval None + */ +void FLASH_UnlockBank2(void) +{ + /* Authorize the FPEC of Bank2 Access */ + FLASH->KEYR2 = FLASH_KEY1; + FLASH->KEYR2 = FLASH_KEY2; + +} +#endif /* STM32F10X_XL */ + +/** + * @brief Locks the FLASH Program Erase Controller. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function Locks Bank1 and Bank2. + * - For all other devices it Locks Bank1 and it is equivalent + * to FLASH_LockBank1 function. + * @param None + * @retval None + */ +void FLASH_Lock(void) +{ + /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */ + FLASH->CR |= CR_LOCK_Set; + +#ifdef STM32F10X_XL + /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ + FLASH->CR2 |= CR_LOCK_Set; +#endif /* STM32F10X_XL */ +} + +/** + * @brief Locks the FLASH Bank1 Program Erase Controller. + * @note this function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function Locks Bank1. + * - For all other devices it Locks Bank1 and it is equivalent + * to FLASH_Lock function. + * @param None + * @retval None + */ +void FLASH_LockBank1(void) +{ + /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */ + FLASH->CR |= CR_LOCK_Set; +} + +#ifdef STM32F10X_XL +/** + * @brief Locks the FLASH Bank2 Program Erase Controller. + * @note This function can be used only for STM32F10X_XL density devices. + * @param None + * @retval None + */ +void FLASH_LockBank2(void) +{ + /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ + FLASH->CR2 |= CR_LOCK_Set; +} +#endif /* STM32F10X_XL */ + +/** + * @brief Erases a specified FLASH page. + * @note This function can be used for all STM32F10x devices. + * @param Page_Address: The page address to be erased. + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Page_Address)); + +#ifdef STM32F10X_XL + if(Page_Address < FLASH_BANK1_END_ADDRESS) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR|= CR_PER_Set; + FLASH->AR = Page_Address; + FLASH->CR|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + /* Disable the PER Bit */ + FLASH->CR &= CR_PER_Reset; + } + } + else + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR2|= CR_PER_Set; + FLASH->AR2 = Page_Address; + FLASH->CR2|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + + /* Disable the PER Bit */ + FLASH->CR2 &= CR_PER_Reset; + } + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR|= CR_PER_Set; + FLASH->AR = Page_Address; + FLASH->CR|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + /* Disable the PER Bit */ + FLASH->CR &= CR_PER_Reset; + } +#endif /* STM32F10X_XL */ + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all FLASH pages. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + +#ifdef STM32F10X_XL + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR2 |= CR_MER_Set; + FLASH->CR2 |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CR2 &= CR_MER_Reset; + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } +#endif /* STM32F10X_XL */ + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all Bank1 FLASH pages. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function erases all Bank1 pages. + * - For all other devices it erases all Bank1 pages and it is equivalent + * to FLASH_EraseAllPages function. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllBank1Pages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } + /* Return the Erase Status */ + return status; +} + +#ifdef STM32F10X_XL +/** + * @brief Erases all Bank2 FLASH pages. + * @note This function can be used only for STM32F10x_XL density devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllBank2Pages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR2 |= CR_MER_Set; + FLASH->CR2 |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CR2 &= CR_MER_Reset; + } + /* Return the Erase Status */ + return status; +} +#endif /* STM32F10X_XL */ + +/** + * @brief Erases the FLASH option bytes. + * @note This functions erases all option bytes except the Read protection (RDP). + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + uint16_t rdptmp = RDP_Key; + + FLASH_Status status = FLASH_COMPLETE; + + /* Get the actual read protection Option Byte value */ + if(FLASH_GetReadOutProtectionStatus() != RESET) + { + rdptmp = 0x00; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CR |= CR_OPTER_Set; + FLASH->CR |= CR_STRT_Set; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + /* Restore the last read protection Option Byte value */ + OB->RDP = (uint16_t)rdptmp; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + } + /* Return the erase status */ + return status; +} + +/** + * @brief Programs a word at a specified address. + * @note This function can be used for all STM32F10x devices. + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + +#ifdef STM32F10X_XL + if(Address < FLASH_BANK1_END_ADDRESS - 2) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + else + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + } + else if(Address == (FLASH_BANK1_END_ADDRESS - 1)) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + else + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + FLASH->CR2 |= CR_PG_Set; + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + else + { + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } + else + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR2 |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + else + { + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + else + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } +#endif /* STM32F10X_XL */ + + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified address. + * @note This function can be used for all STM32F10x devices. + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + +#ifdef STM32F10X_XL + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(Address < FLASH_BANK1_END_ADDRESS) + { + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + else + { + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR2 |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } +#endif /* STM32F10X_XL */ + + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @note This function can be used for all STM32F10x devices. + * @param Address: specifies the address to be programmed. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + /* Enables the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Write protects the desired pages + * @note This function can be used for all STM32F10x devices. + * @param FLASH_Pages: specifies the address of the pages to be write protected. + * This parameter can be: + * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31 + * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3 + * and FLASH_WRProt_Pages124to127 + * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and + * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255 + * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and + * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127 + * @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and + * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511 + * @arg FLASH_WRProt_AllPages + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages)); + + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask); + WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8); + WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16); + WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + FLASH->CR |= CR_OPTPG_Set; + if(WRP0_Data != 0xFF) + { + OB->WRP0 = WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) + { + OB->WRP1 = WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) + { + OB->WRP2 = WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF)) + { + OB->WRP3 = WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the write protection operation Status */ + return status; +} + +/** + * @brief Enables or disables the read out protection. + * @note If the user has already programmed the other option bytes before calling + * this function, he must re-program them since this function erases all option bytes. + * @note This function can be used for all STM32F10x devices. + * @param Newstate: new state of the ReadOut Protection. + * This parameter can be: ENABLE or DISABLE. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + FLASH->CR |= CR_OPTER_Set; + FLASH->CR |= CR_STRT_Set; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + if(NewState != DISABLE) + { + OB->RDP = 0x00; + } + else + { + OB->RDP = RDP_Key; + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + } + } + } + /* Return the protection operation Status */ + return status; +} + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @note This function can be used for all STM32F10x devices. + * @param OB_IWDG: Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param OB_STOP: Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NoRST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param OB_STDBY: Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP_SOURCE(OB_STOP)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + + OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte program Status */ + return status; +} + +#ifdef STM32F10X_XL +/** + * @brief Configures to boot from Bank1 or Bank2. + * @note This function can be used only for STM32F10x_XL density devices. + * @param FLASH_BOOT: select the FLASH Bank to boot from. + * This parameter can be one of the following values: + * @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash + * position and this parameter is selected the device will boot from Bank1(Default). + * @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash + * position and this parameter is selected the device will boot from Bank2 or Bank1, + * depending on the activation of the bank. The active banks are checked in + * the following order: Bank2, followed by Bank1. + * The active bank is recognized by the value programmed at the base address + * of the respective bank (corresponding to the initial stack pointer value + * in the interrupt vector table). + * For more information, please refer to AN2606 from www.st.com. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT) +{ + FLASH_Status status = FLASH_COMPLETE; + assert_param(IS_FLASH_BOOT(FLASH_BOOT)); + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + + if(FLASH_BOOT == FLASH_BOOT_Bank1) + { + OB->USER |= OB_USER_BFB2; + } + else + { + OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2)); + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte program Status */ + return status; +} +#endif /* STM32F10X_XL */ + +/** + * @brief Returns the FLASH User Option Bytes values. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + /* Return the User Option Byte */ + return (uint32_t)(FLASH->OBR >> 2); +} + +/** + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval The FLASH Write Protection Option Bytes Register value + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + /* Return the Flash write protection Register value */ + return (uint32_t)(FLASH->WRPR); +} + +/** + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/** + * @brief Checks whether the FLASH Prefetch Buffer status is set or not. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH Prefetch Buffer Status (SET or RESET). + */ +FlagStatus FLASH_GetPrefetchBufferStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Enables or disables the specified FLASH interrupts. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts + for Bank1 and Bank2. + * - For other devices it enables or disables the specified FLASH interrupts for Bank1. + * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FLASH_IT_ERROR: FLASH Error Interrupt + * @arg FLASH_IT_EOP: FLASH end of operation Interrupt + * @param NewState: new state of the specified Flash interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ +#ifdef STM32F10X_XL + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if((FLASH_IT & 0x80000000) != 0x0) + { + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF); + } + else + { + /* Disable the interrupt sources */ + FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF); + } + } + else + { + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(uint32_t)FLASH_IT; + } + } +#else + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(uint32_t)FLASH_IT; + } +#endif /* STM32F10X_XL */ +} + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices, this function checks whether the specified + * Bank1 or Bank2 flag is set or not. + * - For other devices, it checks whether the specified Bank1 flag is + * set or not. + * @param FLASH_FLAG: specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_BSY: FLASH Busy flag + * @arg FLASH_FLAG_PGERR: FLASH Program error flag + * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + +#ifdef STM32F10X_XL + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH_FLAG & 0x80000000) != 0x0) + { + if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + } +#else + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } +#endif /* STM32F10X_XL */ + + /* Return the new state of FLASH_FLAG (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Clears the FLASH's pending flags. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices, this function clears Bank1 or Bank2’s pending flags + * - For other devices, it clears Bank1’s pending flags. + * @param FLASH_FLAG: specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_PGERR: FLASH Program error flag + * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @retval None + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ +#ifdef STM32F10X_XL + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; + + if((FLASH_FLAG & 0x80000000) != 0x0) + { + /* Clear the flags */ + FLASH->SR2 = FLASH_FLAG; + } + else + { + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; + } + +#else + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; + + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; +#endif /* STM32F10X_XL */ +} + +/** + * @brief Returns the FLASH Status. + * @note This function can be used for all STM32F10x devices, it is equivalent + * to FLASH_GetBank1Status function. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR & FLASH_FLAG_PGERR) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 ) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} + +/** + * @brief Returns the FLASH Bank1 Status. + * @note This function can be used for all STM32F10x devices, it is equivalent + * to FLASH_GetStatus function. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetBank1Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 ) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} + +#ifdef STM32F10X_XL +/** + * @brief Returns the FLASH Bank2 Status. + * @note This function can be used for STM32F10x_XL density devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetBank2Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 ) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} +#endif /* STM32F10X_XL */ +/** + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * @note This function can be used for all STM32F10x devices, + * it is equivalent to FLASH_WaitForLastBank1Operation. + * - For STM32F10X_XL devices this function waits for a Bank1 Flash operation + * to complete or a TIMEOUT to occur. + * - For all other devices it waits for a Flash operation to complete + * or a TIMEOUT to occur. + * @param Timeout: FLASH programming Timeout + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetBank1Status(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +/** + * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. + * @note This function can be used for all STM32F10x devices, + * it is equivalent to FLASH_WaitForLastOperation. + * @param Timeout: FLASH programming Timeout + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetBank1Status(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +#ifdef STM32F10X_XL +/** + * @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur. + * @note This function can be used only for STM32F10x_XL density devices. + * @param Timeout: FLASH programming Timeout + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetBank2Status(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00)) + { + status = FLASH_GetBank2Status(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} +#endif /* STM32F10X_XL */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_fsmc.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_fsmc.c new file mode 100644 index 0000000..c75137c --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_fsmc.c @@ -0,0 +1,866 @@ +/** + ****************************************************************************** + * @file stm32f10x_fsmc.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the FSMC firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_fsmc.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup FSMC + * @brief FSMC driver modules + * @{ + */ + +/** @defgroup FSMC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup FSMC_Private_Defines + * @{ + */ + +/* --------------------- FSMC registers bit mask ---------------------------- */ + +/* FSMC BCRx Mask */ +#define BCR_MBKEN_Set ((uint32_t)0x00000001) +#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) +#define BCR_FACCEN_Set ((uint32_t)0x00000040) + +/* FSMC PCRx Mask */ +#define PCR_PBKEN_Set ((uint32_t)0x00000004) +#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) +#define PCR_ECCEN_Set ((uint32_t)0x00000040) +#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) +#define PCR_MemoryType_NAND ((uint32_t)0x00000008) +/** + * @} + */ + +/** @defgroup FSMC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default + * reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @retval None + */ +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + + /* FSMC_Bank1_NORSRAM1 */ + if(FSMC_Bank == FSMC_Bank1_NORSRAM1) + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; + } + /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ + else + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; + } + FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; + FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; +} + +/** + * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval None + */ +void FSMC_NANDDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Set the FSMC_Bank2 registers to their reset values */ + FSMC_Bank2->PCR2 = 0x00000018; + FSMC_Bank2->SR2 = 0x00000040; + FSMC_Bank2->PMEM2 = 0xFCFCFCFC; + FSMC_Bank2->PATT2 = 0xFCFCFCFC; + } + /* FSMC_Bank3_NAND */ + else + { + /* Set the FSMC_Bank3 registers to their reset values */ + FSMC_Bank3->PCR3 = 0x00000018; + FSMC_Bank3->SR3 = 0x00000040; + FSMC_Bank3->PMEM3 = 0xFCFCFCFC; + FSMC_Bank3->PATT3 = 0xFCFCFCFC; + } +} + +/** + * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. + * @param None + * @retval None + */ +void FSMC_PCCARDDeInit(void) +{ + /* Set the FSMC_Bank4 registers to their reset values */ + FSMC_Bank4->PCR4 = 0x00000018; + FSMC_Bank4->SR4 = 0x00000000; + FSMC_Bank4->PMEM4 = 0xFCFCFCFC; + FSMC_Bank4->PATT4 = 0xFCFCFCFC; + FSMC_Bank4->PIO4 = 0xFCFCFCFC; +} + +/** + * @brief Initializes the FSMC NOR/SRAM Banks according to the specified + * parameters in the FSMC_NORSRAMInitStruct. + * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef + * structure that contains the configuration information for + * the FSMC NOR/SRAM specified Banks. + * @retval None + */ +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); + assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); + assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); + assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); + assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); + assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); + assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); + assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); + assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); + assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); + assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); + assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); + assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); + + /* Bank1 NOR/SRAM control register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | + FSMC_NORSRAMInitStruct->FSMC_MemoryType | + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | + FSMC_NORSRAMInitStruct->FSMC_WrapMode | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | + FSMC_NORSRAMInitStruct->FSMC_WriteOperation | + FSMC_NORSRAMInitStruct->FSMC_WaitSignal | + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | + FSMC_NORSRAMInitStruct->FSMC_WriteBurst; + + if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) + { + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; + } + + /* Bank1 NOR/SRAM timing register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; + + + /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) + { + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; + } + else + { + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; + } +} + +/** + * @brief Initializes the FSMC NAND Banks according to the specified + * parameters in the FSMC_NANDInitStruct. + * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef + * structure that contains the configuration information for the FSMC + * NAND specified Banks. + * @retval None + */ +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + /* Check the parameters */ + assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); + assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); + assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); + assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); + assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); + assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); + assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ + tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | + PCR_MemoryType_NAND | + FSMC_NANDInitStruct->FSMC_MemoryDataWidth | + FSMC_NANDInitStruct->FSMC_ECC | + FSMC_NANDInitStruct->FSMC_ECCPageSize | + (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| + (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); + + /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ + tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ + tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) + { + /* FSMC_Bank2_NAND registers configuration */ + FSMC_Bank2->PCR2 = tmppcr; + FSMC_Bank2->PMEM2 = tmppmem; + FSMC_Bank2->PATT2 = tmppatt; + } + else + { + /* FSMC_Bank3_NAND registers configuration */ + FSMC_Bank3->PCR3 = tmppcr; + FSMC_Bank3->PMEM3 = tmppmem; + FSMC_Bank3->PATT3 = tmppatt; + } +} + +/** + * @brief Initializes the FSMC PCCARD Bank according to the specified + * parameters in the FSMC_PCCARDInitStruct. + * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef + * structure that contains the configuration information for the FSMC + * PCCARD Bank. + * @retval None + */ +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); + assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); + assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ + FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | + FSMC_MemoryDataWidth_16b | + (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | + (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); + + /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ + FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ + FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ + FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); +} + +/** + * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. + * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Reset NOR/SRAM Init structure parameters values */ + FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; + FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; + FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; +} + +/** + * @brief Fills each FSMC_NANDInitStruct member with its default value. + * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + /* Reset NAND Init structure parameters values */ + FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; + FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; + FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; + FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Fills each FSMC_PCCARDInitStruct member with its default value. + * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Reset PCCARD Init structure parameters values */ + FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Enables or disables the specified NOR/SRAM Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; + } + else + { + /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; + } +} + +/** + * @brief Enables or disables the specified NAND Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; + } + else + { + FSMC_Bank3->PCR3 |= PCR_PBKEN_Set; + } + } + else + { + /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; + } + else + { + FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset; + } + } +} + +/** + * @brief Enables or disables the PCCARD Memory Bank. + * @param NewState: new state of the PCCARD Memory Bank. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_PCCARDCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 |= PCR_PBKEN_Set; + } + else + { + /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset; + } +} + +/** + * @brief Enables or disables the FSMC NAND ECC feature. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC NAND ECC feature. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; + } + else + { + FSMC_Bank3->PCR3 |= PCR_ECCEN_Set; + } + } + else + { + /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; + } + else + { + FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset; + } + } +} + +/** + * @brief Returns the error correction code register value. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval The Error Correction Code (ECC) value. + */ +uint32_t FSMC_GetECC(uint32_t FSMC_Bank) +{ + uint32_t eccval = 0x00000000; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Get the ECCR2 register value */ + eccval = FSMC_Bank2->ECCR2; + } + else + { + /* Get the ECCR3 register value */ + eccval = FSMC_Bank3->ECCR3; + } + /* Return the error correction code value */ + return(eccval); +} + +/** + * @brief Enables or disables the specified FSMC interrupts. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @param NewState: new state of the specified FSMC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) +{ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 |= FSMC_IT; + } + } + else + { + /* Disable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + + FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; + } + } +} + +/** + * @brief Checks whether the specified FSMC flag is set or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. + * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. + * @retval The new state of FSMC_FLAG (SET or RESET). + */ +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpsr = 0x00000000; + + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + /* Get the flag status */ + if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the FSMC's pending flags. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. + * @retval None + */ +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~FSMC_FLAG; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~FSMC_FLAG; + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~FSMC_FLAG; + } +} + +/** + * @brief Checks whether the specified FSMC interrupt has occurred or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt source to check. + * This parameter can be one of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval The new state of FSMC_IT (SET or RESET). + */ +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; + + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + itstatus = tmpsr & FSMC_IT; + + itenable = tmpsr & (FSMC_IT >> 3); + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the FSMC's interrupt pending bits. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval None + */ +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_gpio.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_gpio.c new file mode 100644 index 0000000..93dbcd7 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_gpio.c @@ -0,0 +1,650 @@ +/** + ****************************************************************************** + * @file stm32f10x_gpio.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the GPIO firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_gpio.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup GPIO + * @brief GPIO driver modules + * @{ + */ + +/** @defgroup GPIO_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------------*/ +#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) + +/* --- EVENTCR Register -----*/ + +/* Alias word address of EVOE bit */ +#define EVCR_OFFSET (AFIO_OFFSET + 0x00) +#define EVOE_BitNumber ((uint8_t)0x07) +#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) + + +/* --- MAPR Register ---*/ +/* Alias word address of MII_RMII_SEL bit */ +#define MAPR_OFFSET (AFIO_OFFSET + 0x04) +#define MII_RMII_SEL_BitNumber ((u8)0x17) +#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) + + +#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) +/** + * @} + */ + +/** @defgroup GPIO_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval None + */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + if (GPIOx == GPIOA) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + } + else if (GPIOx == GPIOB) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); + } + else if (GPIOx == GPIOC) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + } + else if (GPIOx == GPIOD) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); + } + else if (GPIOx == GPIOE) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); + } + else if (GPIOx == GPIOF) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); + } + else + { + if (GPIOx == GPIOG) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); + } + } +} + +/** + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * @param None + * @retval None + */ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/** + * @brief Initializes the GPIOx peripheral according to the specified + * parameters in the GPIO_InitStruct. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * @retval None + */ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + +/*---------------------------- GPIO Mode Configuration -----------------------*/ + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + /* Check the parameters */ + assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + /* Output mode */ + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } +/*---------------------------- GPIO CRL Configuration ------------------------*/ + /* Configure the eight low port pins */ + if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CRL; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding low control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((uint32_t)0x01) << pinpos); + } + else + { + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CRL = tmpreg; + } +/*---------------------------- GPIO CRH Configuration ------------------------*/ + /* Configure the eight high port pins */ + if (GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CRH; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + /* Get the port pins position */ + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding high control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CRH = tmpreg; + } +} + +/** + * @brief Fills each GPIO_InitStruct member with its default value. + * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO input data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval GPIO input data port value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->IDR); +} + +/** + * @brief Reads the specified output data port bit. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The output port pin value. + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval GPIO output data port value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->ODR); +} + +/** + * @brief Sets the selected data port bits. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRR = GPIO_Pin; +} + +/** + * @brief Clears the selected data port bits. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BRR = GPIO_Pin; +} + +/** + * @brief Sets or clears the selected data port bit. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * @param BitVal: specifies the value to be written to the selected bit. + * This parameter can be one of the BitAction enum values: + * @arg Bit_RESET: to clear the port pin + * @arg Bit_SET: to set the port pin + * @retval None + */ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BRR = GPIO_Pin; + } +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param PortVal: specifies the value to be written to the port output data register. + * @retval None + */ +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR = PortVal; +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; +} + +/** + * @brief Selects the GPIO pin used as Event output. + * @param GPIO_PortSource: selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). + * @param GPIO_PinSource: specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @retval None + */ +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmpreg = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmpreg = AFIO->EVCR; + /* Clear the PORT[6:4] and PIN[3:0] bits */ + tmpreg &= EVCR_PORTPINCONFIG_MASK; + tmpreg |= (uint32_t)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + AFIO->EVCR = tmpreg; +} + +/** + * @brief Enables or disables the Event Output. + * @param NewState: new state of the Event output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState; +} + +/** + * @brief Changes the mapping of the specified pin. + * @param GPIO_Remap: selects the pin to remap. + * This parameter can be one of the following values: + * @arg GPIO_Remap_SPI1 : SPI1 Alternate Function mapping + * @arg GPIO_Remap_I2C1 : I2C1 Alternate Function mapping + * @arg GPIO_Remap_USART1 : USART1 Alternate Function mapping + * @arg GPIO_Remap_USART2 : USART2 Alternate Function mapping + * @arg GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping + * @arg GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping + * @arg GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping + * @arg GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping + * @arg GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping + * @arg GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping + * @arg GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping + * @arg GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping + * @arg GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping + * @arg GPIO_Remap_TIM4 : TIM4 Alternate Function mapping + * @arg GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping + * @arg GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping + * @arg GPIO_Remap_PD01 : PD01 Alternate Function mapping + * @arg GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration + * @arg GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping + * @arg GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping + * @arg GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping + * @arg GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping + * @arg GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices) + * @arg GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices) + * @arg GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST + * @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled + * @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP) + * @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) + * When the SPI3/I2S3 is remapped using this function, the SWJ is configured + * to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST. + * @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected + * to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices) + * If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to + * Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output. + * @arg GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) + * @arg GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices) + * @arg GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices) + * @arg GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices) + * @arg GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices) + * @arg GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices) + * @arg GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices) + * @arg GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices) + * @arg GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices) + * @arg GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) + * @arg GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) + * @arg GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) + * @arg GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) + * @arg GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices) + * @arg GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, + * only for High density Value line devices) + * @param NewState: new state of the port pin remapping. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_REMAP(GPIO_Remap)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + tmpreg = AFIO->MAPR2; + } + else + { + tmpreg = AFIO->MAPR; + } + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) + { + tmpreg &= DBGAFR_SWJCFG_MASK; + AFIO->MAPR &= DBGAFR_SWJCFG_MASK; + } + else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + else + { + tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10)); + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + + if (NewState != DISABLE) + { + tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10)); + } + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + AFIO->MAPR2 = tmpreg; + } + else + { + AFIO->MAPR = tmpreg; + } +} + +/** + * @brief Selects the GPIO pin used as EXTI Line. + * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). + * @param GPIO_PinSource: specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @retval None + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); +} + +/** + * @brief Selects the Ethernet media interface. + * @note This function applies only to STM32 Connectivity line devices. + * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode. + * This parameter can be one of the following values: + * @arg GPIO_ETH_MediaInterface_MII: MII mode + * @arg GPIO_ETH_MediaInterface_RMII: RMII mode + * @retval None + */ +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) +{ + assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); + + /* Configure MII_RMII selection bit */ + *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_i2c.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_i2c.c new file mode 100644 index 0000000..8896726 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_i2c.c @@ -0,0 +1,1331 @@ +/** + ****************************************************************************** + * @file stm32f10x_i2c.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the I2C firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_i2c.h" +#include "stm32f10x_rcc.h" + + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup I2C + * @brief I2C driver modules + * @{ + */ + +/** @defgroup I2C_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Defines + * @{ + */ + +/* I2C SPE mask */ +#define CR1_PE_Set ((uint16_t)0x0001) +#define CR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CR1_START_Set ((uint16_t)0x0100) +#define CR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CR1_STOP_Set ((uint16_t)0x0200) +#define CR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CR1_ACK_Set ((uint16_t)0x0400) +#define CR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CR1_ENGC_Set ((uint16_t)0x0040) +#define CR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CR1_SWRST_Set ((uint16_t)0x8000) +#define CR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CR1_PEC_Set ((uint16_t)0x1000) +#define CR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CR1_ENPEC_Set ((uint16_t)0x0020) +#define CR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CR1_ENARP_Set ((uint16_t)0x0010) +#define CR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CR2_DMAEN_Set ((uint16_t)0x0800) +#define CR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CR2_LAST_Set ((uint16_t)0x1000) +#define CR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OAR1_ADD0_Set ((uint16_t)0x0001) +#define OAR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OAR2_ENDUAL_Set ((uint16_t)0x0001) +#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OAR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CCR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CCR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/** + * @} + */ + +/** @defgroup I2C_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the I2Cx peripheral registers to their default reset values. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval None + */ +void I2C_DeInit(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + if (I2Cx == I2C1) + { + /* Enable I2C1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + /* Release I2C1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + } + else + { + /* Enable I2C2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); + /* Release I2C2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); + } +} + +/** + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * @retval None + */ +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + RCC_ClocksTypeDef rcc_clocks; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed)); + assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); + assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); + assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); + assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); + +/*---------------------------- I2Cx CR2 Configuration ------------------------*/ + /* Get the I2Cx CR2 value */ + tmpreg = I2Cx->CR2; + /* Clear frequency FREQ[5:0] bits */ + tmpreg &= CR2_FREQ_Reset; + /* Get pclk1 frequency value */ + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + /* Set frequency bits depending on pclk1 value */ + freqrange = (uint16_t)(pclk1 / 1000000); + tmpreg |= freqrange; + /* Write to I2Cx CR2 */ + I2Cx->CR2 = tmpreg; + +/*---------------------------- I2Cx CCR Configuration ------------------------*/ + /* Disable the selected I2C peripheral to configure TRISE */ + I2Cx->CR1 &= CR1_PE_Reset; + /* Reset tmpreg value */ + /* Clear F/S, DUTY and CCR[11:0] bits */ + tmpreg = 0; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + /* Standard mode speed calculate */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + /* Test if CCR value is under 0x4*/ + if (result < 0x04) + { + /* Set minimum allowed value */ + result = 0x04; + } + /* Set speed value for standard mode */ + tmpreg |= result; + /* Set Maximum Rise Time for standard mode */ + I2Cx->TRISE = freqrange + 1; + } + /* Configure speed in fast mode */ + else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ + { + if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + /* Fast mode speed calculate: Tlow/Thigh = 2 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ + { + /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + /* Set DUTY bit */ + result |= I2C_DutyCycle_16_9; + } + + /* Test if CCR value is under 0x1*/ + if ((result & CCR_CCR_Set) == 0) + { + /* Set minimum allowed value */ + result |= (uint16_t)0x0001; + } + /* Set speed value and set F/S bit for fast mode */ + tmpreg |= (uint16_t)(result | CCR_FS_Set); + /* Set Maximum Rise Time for fast mode */ + I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + + /* Write to I2Cx CCR */ + I2Cx->CCR = tmpreg; + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= CR1_PE_Set; + +/*---------------------------- I2Cx CR1 Configuration ------------------------*/ + /* Get the I2Cx CR1 value */ + tmpreg = I2Cx->CR1; + /* Clear ACK, SMBTYPE and SMBUS bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure I2Cx: mode and acknowledgement */ + /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ + /* Set ACK bit according to I2C_Ack value */ + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + /* Write to I2Cx CR1 */ + I2Cx->CR1 = tmpreg; + +/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ + /* Set I2Cx Own Address1 and acknowledged address */ + I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/** + * @brief Fills each I2C_InitStruct member with its default value. + * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ +/*---------------- Reset I2C init structure parameters values ----------------*/ + /* initialize the I2C_ClockSpeed member */ + I2C_InitStruct->I2C_ClockSpeed = 5000; + /* Initialize the I2C_Mode member */ + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + /* Initialize the I2C_DutyCycle member */ + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + /* Initialize the I2C_OwnAddress1 member */ + I2C_InitStruct->I2C_OwnAddress1 = 0; + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + /* Initialize the I2C_AcknowledgedAddress member */ + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/** + * @brief Enables or disables the specified I2C peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= CR1_PE_Set; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CR1 &= CR1_PE_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C DMA requests. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C DMA requests */ + I2Cx->CR2 |= CR2_DMAEN_Set; + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->CR2 &= CR2_DMAEN_Reset; + } +} + +/** + * @brief Specifies if the next DMA transfer will be the last one. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C DMA last transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Next DMA transfer is the last transfer */ + I2Cx->CR2 |= CR2_LAST_Set; + } + else + { + /* Next DMA transfer is not the last transfer */ + I2Cx->CR2 &= CR2_LAST_Reset; + } +} + +/** + * @brief Generates I2Cx communication START condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C START condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a START condition */ + I2Cx->CR1 |= CR1_START_Set; + } + else + { + /* Disable the START condition generation */ + I2Cx->CR1 &= CR1_START_Reset; + } +} + +/** + * @brief Generates I2Cx communication STOP condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C STOP condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CR1 |= CR1_STOP_Set; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR1 &= CR1_STOP_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C acknowledge feature. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C Acknowledgement. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the acknowledgement */ + I2Cx->CR1 |= CR1_ACK_Set; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CR1 &= CR1_ACK_Reset; + } +} + +/** + * @brief Configures the specified I2C own address2. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Address: specifies the 7bit I2C own address2. + * @retval None. + */ +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Get the old register value */ + tmpreg = I2Cx->OAR2; + + /* Reset I2Cx Own address2 bit [7:1] */ + tmpreg &= OAR2_ADD2_Reset; + + /* Set I2Cx Own address2 */ + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + + /* Store the new register value */ + I2Cx->OAR2 = tmpreg; +} + +/** + * @brief Enables or disables the specified I2C dual addressing mode. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C dual addressing mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable dual addressing mode */ + I2Cx->OAR2 |= OAR2_ENDUAL_Set; + } + else + { + /* Disable dual addressing mode */ + I2Cx->OAR2 &= OAR2_ENDUAL_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C general call feature. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C General call. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable generall call */ + I2Cx->CR1 |= CR1_ENGC_Set; + } + else + { + /* Disable generall call */ + I2Cx->CR1 &= CR1_ENGC_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C interrupts. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_IT_BUF: Buffer interrupt mask + * @arg I2C_IT_EVT: Event interrupt mask + * @arg I2C_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified I2C interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2C_CONFIG_IT(I2C_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CR2 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CR2 &= (uint16_t)~I2C_IT; + } +} + +/** + * @brief Sends a data byte through the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Data: Byte to be transmitted.. + * @retval None + */ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Write in the DR register the data to be sent */ + I2Cx->DR = Data; +} + +/** + * @brief Returns the most recent received data by the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the data in the DR register */ + return (uint8_t)I2Cx->DR; +} + +/** + * @brief Transmits the address byte to select the slave device. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Address: specifies the slave address which will be transmitted + * @param I2C_Direction: specifies whether the I2C device will be a + * Transmitter or a Receiver. This parameter can be one of the following values + * @arg I2C_Direction_Transmitter: Transmitter mode + * @arg I2C_Direction_Receiver: Receiver mode + * @retval None. + */ +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DIRECTION(I2C_Direction)); + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction != I2C_Direction_Transmitter) + { + /* Set the address bit0 for read */ + Address |= OAR1_ADD0_Set; + } + else + { + /* Reset the address bit0 for write */ + Address &= OAR1_ADD0_Reset; + } + /* Send the address */ + I2Cx->DR = Address; +} + +/** + * @brief Reads the specified I2C register and returns its value. + * @param I2C_Register: specifies the register to read. + * This parameter can be one of the following values: + * @arg I2C_Register_CR1: CR1 register. + * @arg I2C_Register_CR2: CR2 register. + * @arg I2C_Register_OAR1: OAR1 register. + * @arg I2C_Register_OAR2: OAR2 register. + * @arg I2C_Register_DR: DR register. + * @arg I2C_Register_SR1: SR1 register. + * @arg I2C_Register_SR2: SR2 register. + * @arg I2C_Register_CCR: CCR register. + * @arg I2C_Register_TRISE: TRISE register. + * @retval The value of the read register. + */ +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_REGISTER(I2C_Register)); + + tmp = (uint32_t) I2Cx; + tmp += I2C_Register; + + /* Return the selected register value */ + return (*(__IO uint16_t *) tmp); +} + +/** + * @brief Enables or disables the specified I2C software reset. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C software reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Peripheral under reset */ + I2Cx->CR1 |= CR1_SWRST_Set; + } + else + { + /* Peripheral not under reset */ + I2Cx->CR1 &= CR1_SWRST_Reset; + } +} + +/** + * @brief Selects the specified I2C NACK position in master receiver mode. + * This function is useful in I2C Master Receiver mode when the number + * of data to be received is equal to 2. In this case, this function + * should be called (with parameter I2C_NACKPosition_Next) before data + * reception starts,as described in the 2-byte reception procedure + * recommended in Reference Manual in Section: Master receiver. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_NACKPosition: specifies the NACK position. + * This parameter can be one of the following values: + * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last + * received byte. + * @arg I2C_NACKPosition_Current: indicates that current byte is the last + * received byte. + * + * @note This function configures the same bit (POS) as I2C_PECPositionConfig() + * but is intended to be used in I2C mode while I2C_PECPositionConfig() + * is intended to used in SMBUS mode. + * + * @retval None + */ +void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition)); + + /* Check the input parameter */ + if (I2C_NACKPosition == I2C_NACKPosition_Next) + { + /* Next byte in shift register is the last received byte */ + I2Cx->CR1 |= I2C_NACKPosition_Next; + } + else + { + /* Current byte in shift register is the last received byte */ + I2Cx->CR1 &= I2C_NACKPosition_Current; + } +} + +/** + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_SMBusAlert: specifies SMBAlert pin level. + * This parameter can be one of the following values: + * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low + * @arg I2C_SMBusAlert_High: SMBAlert pin driven high + * @retval None + */ +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); + if (I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + /* Drive the SMBusAlert pin Low */ + I2Cx->CR1 |= I2C_SMBusAlert_Low; + } + else + { + /* Drive the SMBusAlert pin High */ + I2Cx->CR1 &= I2C_SMBusAlert_High; + } +} + +/** + * @brief Enables or disables the specified I2C PEC transfer. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C PEC transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC transmission */ + I2Cx->CR1 |= CR1_PEC_Set; + } + else + { + /* Disable the selected I2C PEC transmission */ + I2Cx->CR1 &= CR1_PEC_Reset; + } +} + +/** + * @brief Selects the specified I2C PEC position. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_PECPosition: specifies the PEC position. + * This parameter can be one of the following values: + * @arg I2C_PECPosition_Next: indicates that the next byte is PEC + * @arg I2C_PECPosition_Current: indicates that current byte is PEC + * + * @note This function configures the same bit (POS) as I2C_NACKPositionConfig() + * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() + * is intended to used in I2C mode. + * + * @retval None + */ +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); + if (I2C_PECPosition == I2C_PECPosition_Next) + { + /* Next byte in shift register is PEC */ + I2Cx->CR1 |= I2C_PECPosition_Next; + } + else + { + /* Current byte in shift register is PEC */ + I2Cx->CR1 &= I2C_PECPosition_Current; + } +} + +/** + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx PEC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC calculation */ + I2Cx->CR1 |= CR1_ENPEC_Set; + } + else + { + /* Disable the selected I2C PEC calculation */ + I2Cx->CR1 &= CR1_ENPEC_Reset; + } +} + +/** + * @brief Returns the PEC value for the specified I2C. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the selected I2C PEC value */ + return ((I2Cx->SR2) >> 8); +} + +/** + * @brief Enables or disables the specified I2C ARP. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx ARP. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C ARP */ + I2Cx->CR1 |= CR1_ENARP_Set; + } + else + { + /* Disable the selected I2C ARP */ + I2Cx->CR1 &= CR1_ENARP_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C Clock stretching. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx Clock stretching. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState == DISABLE) + { + /* Enable the selected I2C Clock stretching */ + I2Cx->CR1 |= CR1_NOSTRETCH_Set; + } + else + { + /* Disable the selected I2C Clock stretching */ + I2Cx->CR1 &= CR1_NOSTRETCH_Reset; + } +} + +/** + * @brief Selects the specified I2C fast mode duty cycle. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_DutyCycle: specifies the fast mode duty cycle. + * This parameter can be one of the following values: + * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 + * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 + * @retval None + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); + if (I2C_DutyCycle != I2C_DutyCycle_16_9) + { + /* I2C fast mode Tlow/Thigh=2 */ + I2Cx->CCR &= I2C_DutyCycle_2; + } + else + { + /* I2C fast mode Tlow/Thigh=16/9 */ + I2Cx->CCR |= I2C_DutyCycle_16_9; + } +} + + + +/** + * @brief + **************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * depending on the application requirements and constraints: + * + * + * 1) Basic state monitoring: + * Using I2C_CheckEvent() function: + * It compares the status registers (SR1 and SR2) content to a given event + * (can be the combination of one or more flags). + * It returns SUCCESS if the current status includes the given flags + * and returns ERROR if one or more flags are missing in the current status. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (RM0008). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs (ie. error flags are set besides to the monitored flags), + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * hold or corrupted real state. + * In this case, it is advised to use error interrupts to monitor the error + * events and handle them in the interrupt IRQ handler. + * + * @note + * For error management, it is advised to use the following functions: + * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). + * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() + * in order to determine which error occured. + * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() + * and/or I2C_GenerateStop() in order to clear the error flag and source, + * and return to correct communication status. + * + * + * 2) Advanced state monitoring: + * Using the function I2C_GetLastEvent() which returns the image of both status + * registers in a single word (uint32_t) (Status Register 2 value is shifted left + * by 16 bits and concatenated to Status Register 1). + * - When to use: + * - This function is suitable for the same applications above but it allows to + * overcome the mentioned limitation of I2C_GetFlagStatus() function. + * The returned value could be compared to events already defined in the + * library (stm32f10x_i2c.h) or to custom values defined by user. + * - This function is suitable when multiple flags are monitored at the same time. + * - At the opposite of I2C_CheckEvent() function, this function allows user to + * choose when an event is accepted (when all events flags are set and no + * other flags are set or just when the needed flags are set like + * I2C_CheckEvent() function). + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * 3) Flag-based state monitoring: + * Using the function I2C_GetFlagStatus() which simply returns the status of + * one single flag (ie. I2C_FLAG_RXNE ...). + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed (most I2C events + * are monitored through multiple flags). + * - Limitations: + * - When calling this function, the Status register is accessed. Some flags are + * cleared when the status register is accessed. So checking the status + * of one Flag, may clear other ones. + * - Function may need to be called twice or more in order to monitor one + * single event. + * + * For detailed description of Events, please refer to section I2C_Events in + * stm32f10x_i2c.h file. + * + */ + +/** + * + * 1) Basic state monitoring + ******************************************************************************* + */ + +/** + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_EVENT: specifies the event to be checked. + * This parameter can be one of the following values: + * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2 + * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2 + * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2 + * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3 + * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3 + * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3 + * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2 + * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4 + * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5 + * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 + * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6 + * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2 + * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9 + * + * @note: For detailed description of Events, please refer to section + * I2C_Events in stm32f10x_i2c.h file. + * + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Last event is equal to the I2C_EVENT + * - ERROR: Last event is different from the I2C_EVENT + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_EVENT(I2C_EVENT)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_Mask; + + /* Check whether the last event contains the I2C_EVENT */ + if ((lastevent & I2C_EVENT) == I2C_EVENT) + { + /* SUCCESS: last event is equal to I2C_EVENT */ + status = SUCCESS; + } + else + { + /* ERROR: last event is different from I2C_EVENT */ + status = ERROR; + } + /* Return status */ + return status; +} + +/** + * + * 2) Advanced state monitoring + ******************************************************************************* + */ + +/** + * @brief Returns the last I2Cx Event. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * + * @note: For detailed description of Events, please refer to section + * I2C_Events in stm32f10x_i2c.h file. + * + * @retval The last event + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_Mask; + + /* Return status */ + return lastevent; +} + +/** + * + * 3) Flag-based state monitoring + ******************************************************************************* + */ + +/** + * @brief Checks whether the specified I2C flag is set or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) + * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) + * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) + * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) + * @arg I2C_FLAG_TRA: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY: Bus busy flag + * @arg I2C_FLAG_MSL: Master/Slave flag + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) + * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag + * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) + * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) + * @arg I2C_FLAG_BTF: Byte transfer finished flag + * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA" + * @arg I2C_FLAG_SB: Start bit flag (Master mode) + * @retval The new state of I2C_FLAG (SET or RESET). + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); + + /* Get the I2Cx peripheral base address */ + i2cxbase = (uint32_t)I2Cx; + + /* Read flag register index */ + i2creg = I2C_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x14; + } + else + { + /* Flag in I2Cx SR2 Register */ + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + /* Get the I2Cx SR2 register address */ + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the I2C_FLAG status */ + return bitstatus; +} + + + +/** + * @brief Clears the I2Cx's pending flags. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR + * register (I2C_SendData()). + * @retval None + */ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); + /* Get the I2C flag position */ + flagpos = I2C_FLAG & FLAG_Mask; + /* Clear the selected I2C flag */ + I2Cx->SR1 = (uint16_t)~flagpos; +} + +/** + * @brief Checks whether the specified I2C interrupt has occurred or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_SMBALERT: SMBus Alert flag + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_IT_PECERR: PEC error in reception flag + * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_IT_AF: Acknowledge failure flag + * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_IT_BERR: Bus error flag + * @arg I2C_IT_TXE: Data register empty flag (Transmitter) + * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag + * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) + * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) + * @arg I2C_IT_BTF: Byte transfer finished flag + * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDAD" + * @arg I2C_IT_SB: Start bit flag (Master mode) + * @retval The new state of I2C_IT (SET or RESET). + */ +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_IT(I2C_IT)); + + /* Check if the interrupt source is enabled or not */ + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ; + + /* Get bit[23:0] of the flag */ + I2C_IT &= FLAG_Mask; + + /* Check the status of the specified I2C flag */ + if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + /* Return the I2C_IT status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx’s interrupt pending bits. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg I2C_IT_SMBALERT: SMBus Alert interrupt + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt + * @arg I2C_IT_PECERR: PEC error in reception interrupt + * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) + * @arg I2C_IT_AF: Acknowledge failure interrupt + * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) + * @arg I2C_IT_BERR: Bus error interrupt + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_SR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DR register (I2C_SendData()). + * @retval None + */ +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_IT(I2C_IT)); + /* Get the I2C flag position */ + flagpos = I2C_IT & FLAG_Mask; + /* Clear the selected I2C flag */ + I2Cx->SR1 = (uint16_t)~flagpos; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_iwdg.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_iwdg.c new file mode 100644 index 0000000..9d3b0e8 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_iwdg.c @@ -0,0 +1,190 @@ +/** + ****************************************************************************** + * @file stm32f10x_iwdg.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the IWDG firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_iwdg.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup IWDG + * @brief IWDG driver modules + * @{ + */ + +/** @defgroup IWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Defines + * @{ + */ + +/* ---------------------- IWDG registers bit mask ----------------------------*/ + +/* KR register bit mask */ +#define KR_KEY_Reload ((uint16_t)0xAAAA) +#define KR_KEY_Enable ((uint16_t)0xCCCC) + +/** + * @} + */ + +/** @defgroup IWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. + * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. + * This parameter can be one of the following values: + * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers + * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers + * @retval None + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); + IWDG->KR = IWDG_WriteAccess; +} + +/** + * @brief Sets IWDG Prescaler value. + * @param IWDG_Prescaler: specifies the IWDG Prescaler value. + * This parameter can be one of the following values: + * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 + * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 + * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 + * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 + * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 + * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 + * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 + * @retval None + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); + IWDG->PR = IWDG_Prescaler; +} + +/** + * @brief Sets IWDG Reload value. + * @param Reload: specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * @retval None + */ +void IWDG_SetReload(uint16_t Reload) +{ + /* Check the parameters */ + assert_param(IS_IWDG_RELOAD(Reload)); + IWDG->RLR = Reload; +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_ReloadCounter(void) +{ + IWDG->KR = KR_KEY_Reload; +} + +/** + * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_Enable(void) +{ + IWDG->KR = KR_KEY_Enable; +} + +/** + * @brief Checks whether the specified IWDG flag is set or not. + * @param IWDG_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg IWDG_FLAG_PVU: Prescaler Value Update on going + * @arg IWDG_FLAG_RVU: Reload Value Update on going + * @retval The new state of IWDG_FLAG (SET or RESET). + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_IWDG_FLAG(IWDG_FLAG)); + if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_pwr.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_pwr.c new file mode 100644 index 0000000..147bf0f --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_pwr.c @@ -0,0 +1,307 @@ +/** + ****************************************************************************** + * @file stm32f10x_pwr.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the PWR firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_pwr.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup PWR + * @brief PWR driver modules + * @{ + */ + +/** @defgroup PWR_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Defines + * @{ + */ + +/* --------- PWR registers bit address in the alias region ---------- */ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of DBP bit */ +#define CR_OFFSET (PWR_OFFSET + 0x00) +#define DBP_BitNumber 0x08 +#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) + +/* Alias word address of PVDE bit */ +#define PVDE_BitNumber 0x04 +#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of EWUP bit */ +#define CSR_OFFSET (PWR_OFFSET + 0x04) +#define EWUP_BitNumber 0x08 +#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) + +/* ------------------ PWR registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) + + +/** + * @} + */ + +/** @defgroup PWR_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @param None + * @retval None + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/** + * @brief Enables or disables access to the RTC and backup registers. + * @param NewState: new state of the access to the RTC and backup registers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Power Voltage Detector(PVD). + * @param NewState: new state of the PVD. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param PWR_PVDLevel: specifies the PVD detection level + * This parameter can be one of the following values: + * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V + * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V + * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V + * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V + * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V + * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V + * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V + * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V + * @retval None + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + tmpreg = PWR->CR; + /* Clear PLS[7:5] bits */ + tmpreg &= CR_PLS_MASK; + /* Set PLS[7:5] bits according to PWR_PVDLevel value */ + tmpreg |= PWR_PVDLevel; + /* Store the new value */ + PWR->CR = tmpreg; +} + +/** + * @brief Enables or disables the WakeUp Pin functionality. + * @param NewState: new state of the WakeUp Pin functionality. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; +} + +/** + * @brief Enters STOP mode. + * @param PWR_Regulator: specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_Regulator_ON: STOP mode with regulator ON + * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode + * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction + * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction + * @retval None + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(PWR_Regulator)); + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + /* Clear PDDS and LPDS bits */ + tmpreg &= CR_DS_MASK; + /* Set LPDS bit according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + /* Store the new value */ + PWR->CR = tmpreg; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); +} + +/** + * @brief Enters STANDBY mode. + * @param None + * @retval None + */ +void PWR_EnterSTANDBYMode(void) +{ + /* Clear Wake-up flag */ + PWR->CR |= PWR_CR_CWUF; + /* Select STANDBY mode */ + PWR->CR |= PWR_CR_PDDS; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; +/* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM ) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief Checks whether the specified PWR flag is set or not. + * @param PWR_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @arg PWR_FLAG_PVDO: PVD Output + * @retval The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + + if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the PWR's pending flags. + * @param PWR_FLAG: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @retval None + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + PWR->CR |= PWR_FLAG << 2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_rcc.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_rcc.c new file mode 100644 index 0000000..4b2ec1f --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_rcc.c @@ -0,0 +1,1470 @@ +/** + ****************************************************************************** + * @file stm32f10x_rcc.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the RCC firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup RCC + * @brief RCC driver modules + * @{ + */ + +/** @defgroup RCC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of HSION bit */ +#define CR_OFFSET (RCC_OFFSET + 0x00) +#define HSION_BitNumber 0x00 +#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) + +/* Alias word address of PLLON bit */ +#define PLLON_BitNumber 0x18 +#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) + +#ifdef STM32F10X_CL + /* Alias word address of PLL2ON bit */ + #define PLL2ON_BitNumber 0x1A + #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4)) + + /* Alias word address of PLL3ON bit */ + #define PLL3ON_BitNumber 0x1C + #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* Alias word address of CSSON bit */ +#define CSSON_BitNumber 0x13 +#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) + +/* --- CFGR Register ---*/ + +/* Alias word address of USBPRE bit */ +#define CFGR_OFFSET (RCC_OFFSET + 0x04) + +#ifndef STM32F10X_CL + #define USBPRE_BitNumber 0x16 + #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) +#else + #define OTGFSPRE_BitNumber 0x16 + #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* --- BDCR Register ---*/ + +/* Alias word address of RTCEN bit */ +#define BDCR_OFFSET (RCC_OFFSET + 0x20) +#define RTCEN_BitNumber 0x0F +#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) + +/* Alias word address of BDRST bit */ +#define BDRST_BitNumber 0x10 +#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of LSION bit */ +#define CSR_OFFSET (RCC_OFFSET + 0x24) +#define LSION_BitNumber 0x00 +#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) + +#ifdef STM32F10X_CL +/* --- CFGR2 Register ---*/ + + /* Alias word address of I2S2SRC bit */ + #define CFGR2_OFFSET (RCC_OFFSET + 0x2C) + #define I2S2SRC_BitNumber 0x11 + #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4)) + + /* Alias word address of I2S3SRC bit */ + #define I2S3SRC_BitNumber 0x12 + #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* ---------------------- RCC registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CR_HSEBYP_Set ((uint32_t)0x00040000) +#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CR_HSEON_Set ((uint32_t)0x00010000) +#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +/* CFGR register bit mask */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) + #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF) +#else + #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) +#endif /* STM32F10X_CL */ + +#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) +#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) + +/* CSR register bit mask */ +#define CSR_RMVF_Set ((uint32_t)0x01000000) + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) +/* CFGR2 register bit mask */ + #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) + #define CFGR2_PREDIV1 ((uint32_t)0x0000000F) +#endif +#ifdef STM32F10X_CL + #define CFGR2_PREDIV2 ((uint32_t)0x000000F0) + #define CFGR2_PLL2MUL ((uint32_t)0x00000F00) + #define CFGR2_PLL3MUL ((uint32_t)0x0000F000) +#endif /* STM32F10X_CL */ + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* CIR register byte 2 (Bits[15:8]) base address */ +#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR register byte 4 (Bits[31:24]) base address */ +#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCR register base address */ +#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) + +/** + * @} + */ + +/** @defgroup RCC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Variables + * @{ + */ + +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + +/** + * @} + */ + +/** @defgroup RCC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Functions + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @param None + * @retval None + */ +void RCC_DeInit(void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +} + +/** + * @brief Configures the External High Speed oscillator (HSE). + * @note HSE can not be stopped if it is used directly or through the PLL as system clock. + * @param RCC_HSE: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: HSE oscillator OFF + * @arg RCC_HSE_ON: HSE oscillator ON + * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock + * @retval None + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + /* Reset HSEON bit */ + RCC->CR &= CR_HSEON_Reset; + /* Reset HSEBYP bit */ + RCC->CR &= CR_HSEBYP_Reset; + /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ + switch(RCC_HSE) + { + case RCC_HSE_ON: + /* Set HSEON bit */ + RCC->CR |= CR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + /* Set HSEBYP and HSEON bits */ + RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; + break; + + default: + break; + } +} + +/** + * @brief Waits for HSE start-up. + * @param None + * @retval An ErrorStatus enumuration value: + * - SUCCESS: HSE oscillator is stable and ready to use + * - ERROR: HSE oscillator not yet ready + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSEStatus = RESET; + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * @param HSICalibrationValue: specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); + tmpreg = RCC->CR; + /* Clear HSITRIM[4:0] bits */ + tmpreg &= CR_HSITRIM_Mask; + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpreg |= (uint32_t)HSICalibrationValue << 3; + /* Store the new value */ + RCC->CR = tmpreg; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * @note HSI can not be stopped if it is used directly or through the PLL as system clock. + * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the PLL clock source and multiplication factor. + * @note This function must be used only when the PLL is disabled. + * @param RCC_PLLSource: specifies the PLL entry clock source. + * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, + * this parameter can be one of the following values: + * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry + * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry + * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry + * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry + * @param RCC_PLLMul: specifies the PLL multiplication factor. + * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} + * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] + * @retval None + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); + + tmpreg = RCC->CFGR; + /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + tmpreg &= CFGR_PLL_Mask; + /* Set the PLL configuration bits */ + tmpreg |= RCC_PLLSource | RCC_PLLMul; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Enables or disables the PLL. + * @note The PLL can not be disabled if it is used as system clock. + * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; +} + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) +/** + * @brief Configures the PREDIV1 division factor. + * @note + * - This function must be used only when the PLL is disabled. + * - This function applies only to STM32 Connectivity line and Value line + * devices. + * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source. + * This parameter can be one of the following values: + * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock + * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock + * @note + * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE + * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. + * This parameter can be RCC_PREDIV1_Divx where x:[1,16] + * @retval None + */ +void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source)); + assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); + + tmpreg = RCC->CFGR2; + /* Clear PREDIV1[3:0] and PREDIV1SRC bits */ + tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); + /* Set the PREDIV1 clock source and division factor */ + tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} +#endif + +#ifdef STM32F10X_CL +/** + * @brief Configures the PREDIV2 division factor. + * @note + * - This function must be used only when both PLL2 and PLL3 are disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor. + * This parameter can be RCC_PREDIV2_Divx where x:[1,16] + * @retval None + */ +void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div)); + + tmpreg = RCC->CFGR2; + /* Clear PREDIV2[3:0] bits */ + tmpreg &= ~CFGR2_PREDIV2; + /* Set the PREDIV2 division factor */ + tmpreg |= RCC_PREDIV2_Div; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + +/** + * @brief Configures the PLL2 multiplication factor. + * @note + * - This function must be used only when the PLL2 is disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor. + * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} + * @retval None + */ +void RCC_PLL2Config(uint32_t RCC_PLL2Mul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul)); + + tmpreg = RCC->CFGR2; + /* Clear PLL2Mul[3:0] bits */ + tmpreg &= ~CFGR2_PLL2MUL; + /* Set the PLL2 configuration bits */ + tmpreg |= RCC_PLL2Mul; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + + +/** + * @brief Enables or disables the PLL2. + * @note + * - The PLL2 can not be disabled if it is used indirectly as system clock + * (i.e. it is used as PLL clock entry that is used as System clock). + * - This function applies only to STM32 Connectivity line devices. + * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLL2Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState; +} + + +/** + * @brief Configures the PLL3 multiplication factor. + * @note + * - This function must be used only when the PLL3 is disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor. + * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20} + * @retval None + */ +void RCC_PLL3Config(uint32_t RCC_PLL3Mul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul)); + + tmpreg = RCC->CFGR2; + /* Clear PLL3Mul[3:0] bits */ + tmpreg &= ~CFGR2_PLL3MUL; + /* Set the PLL3 configuration bits */ + tmpreg |= RCC_PLL3Mul; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + + +/** + * @brief Enables or disables the PLL3. + * @note This function applies only to STM32 Connectivity line devices. + * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLL3Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the system clock (SYSCLK). + * @param RCC_SYSCLKSource: specifies the clock source used as system clock. + * This parameter can be one of the following values: + * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock + * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock + * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock + * @retval None + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + tmpreg = RCC->CFGR; + /* Clear SW[1:0] bits */ + tmpreg &= CFGR_SW_Mask; + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the clock source used as system clock. + * @param None + * @retval The clock source used as system clock. The returned value can + * be one of the following: + * - 0x00: HSI used as system clock + * - 0x04: HSE used as system clock + * - 0x08: PLL used as system clock + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask)); +} + +/** + * @brief Configures the AHB clock (HCLK). + * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK + * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 + * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 + * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 + * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 + * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 + * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 + * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 + * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 + * @retval None + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_HCLK(RCC_SYSCLK)); + tmpreg = RCC->CFGR; + /* Clear HPRE[3:0] bits */ + tmpreg &= CFGR_HPRE_Reset_Mask; + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpreg |= RCC_SYSCLK; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the Low Speed APB clock (PCLK1). + * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB1 clock = HCLK + * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + tmpreg = RCC->CFGR; + /* Clear PPRE1[2:0] bits */ + tmpreg &= CFGR_PPRE1_Reset_Mask; + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the High Speed APB clock (PCLK2). + * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB2 clock = HCLK + * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + tmpreg = RCC->CFGR; + /* Clear PPRE2[2:0] bits */ + tmpreg &= CFGR_PPRE2_Reset_Mask; + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK << 3; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Enables or disables the specified RCC interrupts. + * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * + * @param NewState: new state of the specified RCC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +#ifndef STM32F10X_CL +/** + * @brief Configures the USB clock (USBCLK). + * @param RCC_USBCLKSource: specifies the USB clock source. This clock is + * derived from the PLL output. + * This parameter can be one of the following values: + * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB + * clock source + * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source + * @retval None + */ +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); + + *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource; +} +#else +/** + * @brief Configures the USB OTG FS clock (OTGFSCLK). + * This function applies only to STM32 Connectivity line devices. + * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source. + * This clock is derived from the PLL output. + * This parameter can be one of the following values: + * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source + * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source + * @retval None + */ +void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource)); + + *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the ADC clock (ADCCLK). + * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from + * the APB2 clock (PCLK2). + * This parameter can be one of the following values: + * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2 + * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4 + * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6 + * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8 + * @retval None + */ +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); + tmpreg = RCC->CFGR; + /* Clear ADCPRE[1:0] bits */ + tmpreg &= CFGR_ADCPRE_Reset_Mask; + /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ + tmpreg |= RCC_PCLK2; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +#ifdef STM32F10X_CL +/** + * @brief Configures the I2S2 clock source(I2S2CLK). + * @note + * - This function must be called before enabling I2S2 APB clock. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_I2S2CLKSource: specifies the I2S2 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry + * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry + * @retval None + */ +void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource)); + + *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource; +} + +/** + * @brief Configures the I2S3 clock source(I2S2CLK). + * @note + * - This function must be called before enabling I2S3 APB clock. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_I2S3CLKSource: specifies the I2S3 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry + * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry + * @retval None + */ +void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource)); + + *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the External Low Speed oscillator (LSE). + * @param RCC_LSE: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: LSE oscillator OFF + * @arg RCC_LSE_ON: LSE oscillator ON + * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock + * @retval None + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + /* Reset LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + /* Reset LSEBYP bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ + switch(RCC_LSE) + { + case RCC_LSE_ON: + /* Set LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + /* Set LSEBYP and LSEON bits */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/** + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the RTC clock (RTCCLK). + * @note Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * @param RCC_RTCCLKSource: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock + * @retval None + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + /* Select the RTC clock source */ + RCC->BDCR |= RCC_RTCCLKSource; +} + +/** + * @brief Enables or disables the RTC clock. + * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function. + * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; +} + +/** + * @brief Returns the frequencies of different on chip clocks. + * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * @note The result of this function could be not correct when using + * fractional value for HSE crystal. + * @retval None + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & CFGR_SWS_Mask; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & CFGR_PLLMull_Mask; + pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { /* HSE oscillator clock selected as PREDIV1 clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; + RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + + /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ + /* Get HCLK prescaler */ + tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + /* Get PCLK1 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + /* Get PCLK2 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = APBAHBPrescTable[tmp]; + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + /* Get ADCCLK prescaler */ + tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + /* ADCCLK clock frequency */ + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/** + * @brief Enables or disables the AHB peripheral clock. + * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values: + * @arg RCC_AHBPeriph_DMA1 + * @arg RCC_AHBPeriph_DMA2 + * @arg RCC_AHBPeriph_SRAM + * @arg RCC_AHBPeriph_FLITF + * @arg RCC_AHBPeriph_CRC + * @arg RCC_AHBPeriph_OTG_FS + * @arg RCC_AHBPeriph_ETH_MAC + * @arg RCC_AHBPeriph_ETH_MAC_Tx + * @arg RCC_AHBPeriph_ETH_MAC_Rx + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values: + * @arg RCC_AHBPeriph_DMA1 + * @arg RCC_AHBPeriph_DMA2 + * @arg RCC_AHBPeriph_SRAM + * @arg RCC_AHBPeriph_FLITF + * @arg RCC_AHBPeriph_CRC + * @arg RCC_AHBPeriph_FSMC + * @arg RCC_AHBPeriph_SDIO + * + * @note SRAM and FLITF clock can be disabled only during sleep mode. + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBENR &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, + * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, + * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, + * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, + * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, + * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, + * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, + * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, + * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, + * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, + * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, + * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, + * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, + * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +#ifdef STM32F10X_CL +/** + * @brief Forces or releases AHB peripheral reset. + * @note This function applies only to STM32 Connectivity line devices. + * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHBPeriph_OTG_FS + * @arg RCC_AHBPeriph_ETH_MAC + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBRSTR |= RCC_AHBPeriph; + } + else + { + RCC->AHBRSTR &= ~RCC_AHBPeriph; + } +} +#endif /* STM32F10X_CL */ + +/** + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, + * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, + * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, + * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, + * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, + * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, + * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, + * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, + * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, + * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, + * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, + * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, + * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, + * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases the Backup domain reset. + * @param NewState: new state of the Backup domain reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Clock Security System. + * @param NewState: new state of the Clock Security System.. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; +} + +/** + * @brief Selects the clock source to output on MCO pin. + * @param RCC_MCO: specifies the clock source to output. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_MCO_NoClock: No clock selected + * @arg RCC_MCO_SYSCLK: System clock selected + * @arg RCC_MCO_HSI: HSI oscillator clock selected + * @arg RCC_MCO_HSE: HSE oscillator clock selected + * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected + * @arg RCC_MCO_PLL2CLK: PLL2 clock selected + * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected + * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected + * @arg RCC_MCO_PLL3CLK: PLL3 clock selected + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_MCO_NoClock: No clock selected + * @arg RCC_MCO_SYSCLK: System clock selected + * @arg RCC_MCO_HSI: HSI oscillator clock selected + * @arg RCC_MCO_HSE: HSE oscillator clock selected + * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected + * + * @retval None + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCO)); + + /* Perform Byte access to MCO bits to select the MCO source */ + *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO; +} + +/** + * @brief Checks whether the specified RCC flag is set or not. + * @param RCC_FLAG: specifies the flag to check. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: PLL clock ready + * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready + * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: PLL clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * + * @retval The new state of RCC_FLAG (SET or RESET). + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + if (tmp == 1) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else if (tmp == 2) /* The flag to check is in BDCR register */ + { + statusreg = RCC->BDCR; + } + else /* The flag to check is in CSR register */ + { + statusreg = RCC->CSR; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_Mask; + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC reset flags. + * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @param None + * @retval None + */ +void RCC_ClearFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CSR |= CSR_RMVF_Set; +} + +/** + * @brief Checks whether the specified RCC interrupt has occurred or not. + * @param RCC_IT: specifies the RCC interrupt source to check. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * @retval The new state of RCC_IT (SET or RESET). + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_GET_IT(RCC_IT)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the RCC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the RCC's interrupt pending bits. + * @param RCC_IT: specifies the interrupt pending bit to clear. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval None + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLEAR_IT(RCC_IT)); + + /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt + pending bits */ + *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_rtc.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_rtc.c new file mode 100644 index 0000000..f798d2b --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_rtc.c @@ -0,0 +1,339 @@ +/** + ****************************************************************************** + * @file stm32f10x_rtc.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the RTC firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_rtc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup RTC + * @brief RTC driver modules + * @{ + */ + +/** @defgroup RTC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup RTC_Private_Defines + * @{ + */ +#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */ +#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables the specified RTC interrupts. + * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @param NewState: new state of the specified RTC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT(RTC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RTC->CRH |= RTC_IT; + } + else + { + RTC->CRH &= (uint16_t)~RTC_IT; + } +} + +/** + * @brief Enters the RTC configuration mode. + * @param None + * @retval None + */ +void RTC_EnterConfigMode(void) +{ + /* Set the CNF flag to enter in the Configuration Mode */ + RTC->CRL |= RTC_CRL_CNF; +} + +/** + * @brief Exits from the RTC configuration mode. + * @param None + * @retval None + */ +void RTC_ExitConfigMode(void) +{ + /* Reset the CNF flag to exit from the Configuration Mode */ + RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF); +} + +/** + * @brief Gets the RTC counter value. + * @param None + * @retval RTC counter value. + */ +uint32_t RTC_GetCounter(void) +{ + uint16_t tmp = 0; + tmp = RTC->CNTL; + return (((uint32_t)RTC->CNTH << 16 ) | tmp) ; +} + +/** + * @brief Sets the RTC counter value. + * @param CounterValue: RTC counter new value. + * @retval None + */ +void RTC_SetCounter(uint32_t CounterValue) +{ + RTC_EnterConfigMode(); + /* Set RTC COUNTER MSB word */ + RTC->CNTH = CounterValue >> 16; + /* Set RTC COUNTER LSB word */ + RTC->CNTL = (CounterValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/** + * @brief Sets the RTC prescaler value. + * @param PrescalerValue: RTC prescaler new value. + * @retval None + */ +void RTC_SetPrescaler(uint32_t PrescalerValue) +{ + /* Check the parameters */ + assert_param(IS_RTC_PRESCALER(PrescalerValue)); + + RTC_EnterConfigMode(); + /* Set RTC PRESCALER MSB word */ + RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16; + /* Set RTC PRESCALER LSB word */ + RTC->PRLL = (PrescalerValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/** + * @brief Sets the RTC alarm value. + * @param AlarmValue: RTC alarm new value. + * @retval None + */ +void RTC_SetAlarm(uint32_t AlarmValue) +{ + RTC_EnterConfigMode(); + /* Set the ALARM MSB word */ + RTC->ALRH = AlarmValue >> 16; + /* Set the ALARM LSB word */ + RTC->ALRL = (AlarmValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/** + * @brief Gets the RTC divider value. + * @param None + * @retval RTC Divider value. + */ +uint32_t RTC_GetDivider(void) +{ + uint32_t tmp = 0x00; + tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; + tmp |= RTC->DIVL; + return tmp; +} + +/** + * @brief Waits until last write operation on RTC registers has finished. + * @note This function must be called before any write to RTC registers. + * @param None + * @retval None + */ +void RTC_WaitForLastTask(void) +{ + /* Loop until RTOFF flag is set */ + while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) + { + } +} + +/** + * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) + * are synchronized with RTC APB clock. + * @note This function must be called before any read operation after an APB reset + * or an APB clock stop. + * @param None + * @retval None + */ +void RTC_WaitForSynchro(void) +{ + /* Clear RSF flag */ + RTC->CRL &= (uint16_t)~RTC_FLAG_RSF; + /* Loop until RSF flag is set */ + while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET) + { + } +} + +/** + * @brief Checks whether the specified RTC flag is set or not. + * @param RTC_FLAG: specifies the flag to check. + * This parameter can be one the following values: + * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag + * @arg RTC_FLAG_RSF: Registers Synchronized flag + * @arg RTC_FLAG_OW: Overflow flag + * @arg RTC_FLAG_ALR: Alarm flag + * @arg RTC_FLAG_SEC: Second flag + * @retval The new state of RTC_FLAG (SET or RESET). + */ +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); + + if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's pending flags. + * @param RTC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after + * an APB reset or an APB Clock stop. + * @arg RTC_FLAG_OW: Overflow flag + * @arg RTC_FLAG_ALR: Alarm flag + * @arg RTC_FLAG_SEC: Second flag + * @retval None + */ +void RTC_ClearFlag(uint16_t RTC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + + /* Clear the corresponding RTC flag */ + RTC->CRL &= (uint16_t)~RTC_FLAG; +} + +/** + * @brief Checks whether the specified RTC interrupt has occurred or not. + * @param RTC_IT: specifies the RTC interrupts sources to check. + * This parameter can be one of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @retval The new state of the RTC_IT (SET or RESET). + */ +ITStatus RTC_GetITStatus(uint16_t RTC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RTC_GET_IT(RTC_IT)); + + bitstatus = (ITStatus)(RTC->CRL & RTC_IT); + if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's interrupt pending bits. + * @param RTC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @retval None + */ +void RTC_ClearITPendingBit(uint16_t RTC_IT) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT(RTC_IT)); + + /* Clear the corresponding RTC pending bit */ + RTC->CRL &= (uint16_t)~RTC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_sdio.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_sdio.c new file mode 100644 index 0000000..d1870ce --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_sdio.c @@ -0,0 +1,799 @@ +/** + ****************************************************************************** + * @file stm32f10x_sdio.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the SDIO firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_sdio.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup SDIO + * @brief SDIO driver modules + * @{ + */ + +/** @defgroup SDIO_Private_TypesDefinitions + * @{ + */ + +/* ------------ SDIO registers bit address in the alias region ----------- */ +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* --- CLKCR Register ---*/ + +/* Alias word address of CLKEN bit */ +#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) +#define CLKEN_BitNumber 0x08 +#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) + +/* --- CMD Register ---*/ + +/* Alias word address of SDIOSUSPEND bit */ +#define CMD_OFFSET (SDIO_OFFSET + 0x0C) +#define SDIOSUSPEND_BitNumber 0x0B +#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) + +/* Alias word address of ENCMDCOMPL bit */ +#define ENCMDCOMPL_BitNumber 0x0C +#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) + +/* Alias word address of NIEN bit */ +#define NIEN_BitNumber 0x0D +#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) + +/* Alias word address of ATACMD bit */ +#define ATACMD_BitNumber 0x0E +#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) + +/* --- DCTRL Register ---*/ + +/* Alias word address of DMAEN bit */ +#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) +#define DMAEN_BitNumber 0x03 +#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) + +/* Alias word address of RWSTART bit */ +#define RWSTART_BitNumber 0x08 +#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) + +/* Alias word address of RWSTOP bit */ +#define RWSTOP_BitNumber 0x09 +#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) + +/* Alias word address of RWMOD bit */ +#define RWMOD_BitNumber 0x0A +#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) + +/* Alias word address of SDIOEN bit */ +#define SDIOEN_BitNumber 0x0B +#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) + +/* ---------------------- SDIO registers bit mask ------------------------ */ + +/* --- CLKCR Register ---*/ + +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) + +/* --- PWRCTRL Register ---*/ + +/* SDIO PWRCTRL Mask */ +#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) + +/* --- DCTRL Register ---*/ + +/* SDIO DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) + +/* --- CMD Register ---*/ + +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) + +/* SDIO RESP Registers Address */ +#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) + +/** + * @} + */ + +/** @defgroup SDIO_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SDIO peripheral registers to their default reset values. + * @param None + * @retval None + */ +void SDIO_DeInit(void) +{ + SDIO->POWER = 0x00000000; + SDIO->CLKCR = 0x00000000; + SDIO->ARG = 0x00000000; + SDIO->CMD = 0x00000000; + SDIO->DTIMER = 0x00000000; + SDIO->DLEN = 0x00000000; + SDIO->DCTRL = 0x00000000; + SDIO->ICR = 0x00C007FF; + SDIO->MASK = 0x00000000; +} + +/** + * @brief Initializes the SDIO peripheral according to the specified + * parameters in the SDIO_InitStruct. + * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure + * that contains the configuration information for the SDIO peripheral. + * @retval None + */ +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); + assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); + assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); + assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); + assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); + +/*---------------------------- SDIO CLKCR Configuration ------------------------*/ + /* Get the SDIO CLKCR value */ + tmpreg = SDIO->CLKCR; + + /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ + tmpreg &= CLKCR_CLEAR_MASK; + + /* Set CLKDIV bits according to SDIO_ClockDiv value */ + /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ + /* Set BYPASS bit according to SDIO_ClockBypass value */ + /* Set WIDBUS bits according to SDIO_BusWide value */ + /* Set NEGEDGE bits according to SDIO_ClockEdge value */ + /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ + tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | + SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | + SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); + + /* Write to SDIO CLKCR */ + SDIO->CLKCR = tmpreg; +} + +/** + * @brief Fills each SDIO_InitStruct member with its default value. + * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which + * will be initialized. + * @retval None + */ +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) +{ + /* SDIO_InitStruct members default value */ + SDIO_InitStruct->SDIO_ClockDiv = 0x00; + SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; +} + +/** + * @brief Enables or disables the SDIO Clock. + * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_ClockCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; +} + +/** + * @brief Sets the power status of the controller. + * @param SDIO_PowerState: new state of the Power state. + * This parameter can be one of the following values: + * @arg SDIO_PowerState_OFF + * @arg SDIO_PowerState_ON + * @retval None + */ +void SDIO_SetPowerState(uint32_t SDIO_PowerState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); + + SDIO->POWER &= PWR_PWRCTRL_MASK; + SDIO->POWER |= SDIO_PowerState; +} + +/** + * @brief Gets the power status of the controller. + * @param None + * @retval Power status of the controller. The returned value can + * be one of the following: + * - 0x00: Power OFF + * - 0x02: Power UP + * - 0x03: Power ON + */ +uint32_t SDIO_GetPowerState(void) +{ + return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); +} + +/** + * @brief Enables or disables the SDIO interrupts. + * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @param NewState: new state of the specified SDIO interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_IT(SDIO_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the SDIO interrupts */ + SDIO->MASK |= SDIO_IT; + } + else + { + /* Disable the SDIO interrupts */ + SDIO->MASK &= ~SDIO_IT; + } +} + +/** + * @brief Enables or disables the SDIO DMA request. + * @param NewState: new state of the selected SDIO DMA request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_DMACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; +} + +/** + * @brief Initializes the SDIO Command according to the specified + * parameters in the SDIO_CmdInitStruct and send the command. + * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef + * structure that contains the configuration information for the SDIO command. + * @retval None + */ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); + assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); + assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); + assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); + +/*---------------------------- SDIO ARG Configuration ------------------------*/ + /* Set the SDIO Argument value */ + SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; + +/*---------------------------- SDIO CMD Configuration ------------------------*/ + /* Get the SDIO CMD value */ + tmpreg = SDIO->CMD; + /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ + tmpreg &= CMD_CLEAR_MASK; + /* Set CMDINDEX bits according to SDIO_CmdIndex value */ + /* Set WAITRESP bits according to SDIO_Response value */ + /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ + /* Set CPSMEN bits according to SDIO_CPSM value */ + tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response + | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; + + /* Write to SDIO CMD */ + SDIO->CMD = tmpreg; +} + +/** + * @brief Fills each SDIO_CmdInitStruct member with its default value. + * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef + * structure which will be initialized. + * @retval None + */ +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) +{ + /* SDIO_CmdInitStruct members default value */ + SDIO_CmdInitStruct->SDIO_Argument = 0x00; + SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; + SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; + SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; +} + +/** + * @brief Returns command index of last command for which response received. + * @param None + * @retval Returns the command index of the last command response received. + */ +uint8_t SDIO_GetCommandResponse(void) +{ + return (uint8_t)(SDIO->RESPCMD); +} + +/** + * @brief Returns response received from the card for the last command. + * @param SDIO_RESP: Specifies the SDIO response register. + * This parameter can be one of the following values: + * @arg SDIO_RESP1: Response Register 1 + * @arg SDIO_RESP2: Response Register 2 + * @arg SDIO_RESP3: Response Register 3 + * @arg SDIO_RESP4: Response Register 4 + * @retval The Corresponding response register value. + */ +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_RESP(SDIO_RESP)); + + tmp = SDIO_RESP_ADDR + SDIO_RESP; + + return (*(__IO uint32_t *) tmp); +} + +/** + * @brief Initializes the SDIO data path according to the specified + * parameters in the SDIO_DataInitStruct. + * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that + * contains the configuration information for the SDIO command. + * @retval None + */ +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); + assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); + assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); + assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); + assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); + +/*---------------------------- SDIO DTIMER Configuration ---------------------*/ + /* Set the SDIO Data TimeOut value */ + SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; + +/*---------------------------- SDIO DLEN Configuration -----------------------*/ + /* Set the SDIO DataLength value */ + SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; + +/*---------------------------- SDIO DCTRL Configuration ----------------------*/ + /* Get the SDIO DCTRL value */ + tmpreg = SDIO->DCTRL; + /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ + tmpreg &= DCTRL_CLEAR_MASK; + /* Set DEN bit according to SDIO_DPSM value */ + /* Set DTMODE bit according to SDIO_TransferMode value */ + /* Set DTDIR bit according to SDIO_TransferDir value */ + /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ + tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir + | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; + + /* Write to SDIO DCTRL */ + SDIO->DCTRL = tmpreg; +} + +/** + * @brief Fills each SDIO_DataInitStruct member with its default value. + * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which + * will be initialized. + * @retval None + */ +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + /* SDIO_DataInitStruct members default value */ + SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; + SDIO_DataInitStruct->SDIO_DataLength = 0x00; + SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; +} + +/** + * @brief Returns number of remaining data bytes to be transferred. + * @param None + * @retval Number of remaining data bytes to be transferred + */ +uint32_t SDIO_GetDataCounter(void) +{ + return SDIO->DCOUNT; +} + +/** + * @brief Read one data word from Rx FIFO. + * @param None + * @retval Data received + */ +uint32_t SDIO_ReadData(void) +{ + return SDIO->FIFO; +} + +/** + * @brief Write one data word to Tx FIFO. + * @param Data: 32-bit data word to write. + * @retval None + */ +void SDIO_WriteData(uint32_t Data) +{ + SDIO->FIFO = Data; +} + +/** + * @brief Returns the number of words left to be written to or read from FIFO. + * @param None + * @retval Remaining number of words. + */ +uint32_t SDIO_GetFIFOCount(void) +{ + return SDIO->FIFOCNT; +} + +/** + * @brief Starts the SD I/O Read Wait operation. + * @param NewState: new state of the Start SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_StartSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; +} + +/** + * @brief Stops the SD I/O Read Wait operation. + * @param NewState: new state of the Stop SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_StopSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; +} + +/** + * @brief Sets one of the two options of inserting read wait interval. + * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. + * This parameter can be: + * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK + * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 + * @retval None + */ +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) +{ + /* Check the parameters */ + assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); + + *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; +} + +/** + * @brief Enables or disables the SD I/O Mode Operation. + * @param NewState: new state of SDIO specific operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SetSDIOOperation(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the SD I/O Mode suspend command sending. + * @param NewState: new state of the SD I/O Mode suspend command. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the command completion signal. + * @param NewState: new state of command completion signal. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_CommandCompletionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the CE-ATA interrupt. + * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_CEATAITCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); +} + +/** + * @brief Sends CE-ATA command (CMD61). + * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SendCEATACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; +} + +/** + * @brief Checks whether the specified SDIO flag is set or not. + * @param SDIO_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide + * bus mode. + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_CMDACT: Command transfer in progress + * @arg SDIO_FLAG_TXACT: Data transmit in progress + * @arg SDIO_FLAG_RXACT: Data receive in progress + * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full + * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval The new state of SDIO_FLAG (SET or RESET). + */ +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_FLAG(SDIO_FLAG)); + + if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO's pending flags. + * @param SDIO_FLAG: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide + * bus mode + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +void SDIO_ClearFlag(uint32_t SDIO_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); + + SDIO->ICR = SDIO_FLAG; +} + +/** + * @brief Checks whether the specified SDIO interrupt has occurred or not. + * @param SDIO_IT: specifies the SDIO interrupt source to check. + * This parameter can be one of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @retval The new state of SDIO_IT (SET or RESET). + */ +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_GET_IT(SDIO_IT)); + if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO's interrupt pending bits. + * @param SDIO_IT: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +void SDIO_ClearITPendingBit(uint32_t SDIO_IT) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); + + SDIO->ICR = SDIO_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_spi.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_spi.c new file mode 100644 index 0000000..51a9cce --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_spi.c @@ -0,0 +1,908 @@ +/** + ****************************************************************************** + * @file stm32f10x_spi.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the SPI firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_spi.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup SPI + * @brief SPI driver modules + * @{ + */ + +/** @defgroup SPI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup SPI_Private_Defines + * @{ + */ + +/* SPI SPE mask */ +#define CR1_SPE_Set ((uint16_t)0x0040) +#define CR1_SPE_Reset ((uint16_t)0xFFBF) + +/* I2S I2SE mask */ +#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) +#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) + +/* SPI CRCNext mask */ +#define CR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CR1_CRCEN_Set ((uint16_t)0x2000) +#define CR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CR2_SSOE_Set ((uint16_t)0x0004) +#define CR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_Mode_Select ((uint16_t)0xF7FF) +#define I2S_Mode_Select ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) +#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) +#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) +#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) + +/** + * @} + */ + +/** @defgroup SPI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values (Affects also the I2Ss). + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval None + */ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + if (SPIx == SPI1) + { + /* Enable SPI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } + else if (SPIx == SPI2) + { + /* Enable SPI2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + } + else + { + if (SPIx == SPI3) + { + /* Enable SPI3 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); + /* Release SPI3 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + } + } +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * @retval None + */ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + /* check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); + +/*---------------------------- SPIx CR1 Configuration ------------------------*/ + /* Get the SPIx CR1 value */ + tmpreg = SPIx->CR1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ + /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ + /* Set LSBFirst bit according to SPI_FirstBit value */ + /* Set BR bits according to SPI_BaudRatePrescaler value */ + /* Set CPOL bit according to SPI_CPOL value */ + /* Set CPHA bit according to SPI_CPHA value */ + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + /* Write to SPIx CR1 */ + SPIx->CR1 = tmpreg; + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + SPIx->I2SCFGR &= SPI_Mode_Select; + +/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral + * (configured in I2S mode). + * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * @note + * The function calculates the optimal prescaler needed to obtain the most + * accurate audio frequency (depending on the I2S clock source, the PLL values + * and the product configuration). But in case the prescaler value is greater + * than 511, the default value (0x02) will be configured instead. * + * @retval None + */ +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; + RCC_ClocksTypeDef RCC_Clocks; + uint32_t sourceclock = 0; + + /* Check the I2S parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); + assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); + assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); + +/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; + SPIx->I2SPR = 0x0002; + + /* Get the I2SCFGR register value */ + tmpreg = SPIx->I2SCFGR; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) */ + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + + /* Get the I2S clock source mask depending on the peripheral number */ + if(((uint32_t)SPIx) == SPI2_BASE) + { + /* The mask is relative to I2S2 */ + tmp = I2S2_CLOCK_SRC; + } + else + { + /* The mask is relative to I2S3 */ + tmp = I2S3_CLOCK_SRC; + } + + /* Check the I2S clock source configuration depending on the Device: + Only Connectivity line devices have the PLL3 VCO clock */ +#ifdef STM32F10X_CL + if((RCC->CFGR2 & tmp) != 0) + { + /* Get the configuration bits of RCC PLL3 multiplier */ + tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12); + + /* Get the value of the PLL3 multiplier */ + if((tmp > 5) && (tmp < 15)) + { + /* Multiplier is between 8 and 14 (value 15 is forbidden) */ + tmp += 2; + } + else + { + if (tmp == 15) + { + /* Multiplier is 20 */ + tmp = 20; + } + } + /* Get the PREDIV2 value */ + sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1); + + /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */ + sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); + } + else + { + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreq(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SYSCLK_Frequency; + } +#else /* STM32F10X_HD */ + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreq(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SYSCLK_Frequency; +#endif /* STM32F10X_CL */ + + /* Compute the Real divider depending on the MCLK output state with a floating point */ + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + /* Remove the floating point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint16_t) (i2sodd << 8); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to SPIx I2SPR register the computed value */ + SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); + + /* Configure the I2S with the SPI_InitStruct values */ + tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \ + (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ + (uint16_t)I2S_InitStruct->I2S_CPOL)))); + + /* Write to SPIx I2SCFGR */ + SPIx->I2SCFGR = tmpreg; +} + +/** + * @brief Fills each SPI_InitStruct member with its default value. + * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized. + * @retval None + */ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ +/*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the SPI_Direction member */ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + /* initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + /* initialize the SPI_DataSize member */ + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + /* Initialize the SPI_NSS member */ + SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; + /* Initialize the SPI_BaudRatePrescaler member */ + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + /* Initialize the SPI_CRCPolynomial member */ + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/** + * @brief Fills each I2S_InitStruct member with its default value. + * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) +{ +/*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2S_Mode member */ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + + /* Initialize the I2S_Standard member */ + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + + /* Initialize the I2S_DataFormat member */ + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + + /* Initialize the I2S_MCLKOutput member */ + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + + /* Initialize the I2S_AudioFreq member */ + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + + /* Initialize the I2S_CPOL member */ + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/** + * @brief Enables or disables the specified SPI peripheral. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR1 |= CR1_SPE_Set; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR1 &= CR1_SPE_Reset; + } +} + +/** + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; + } + else + { + /* Disable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; + } +} + +/** + * @brief Enables or disables the specified SPI/I2S interrupts. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask + * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask + * @arg SPI_I2S_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified SPI/I2S interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0 ; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (NewState != DISABLE) + { + /* Enable the selected SPI/I2S interrupt */ + SPIx->CR2 |= itmask; + } + else + { + /* Disable the selected SPI/I2S interrupt */ + SPIx->CR2 &= (uint16_t)~itmask; + } +} + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request + * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request + * @param NewState: new state of the selected SPI/I2S DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); + if (NewState != DISABLE) + { + /* Enable the selected SPI/I2S DMA requests */ + SPIx->CR2 |= SPI_I2S_DMAReq; + } + else + { + /* Disable the selected SPI/I2S DMA requests */ + SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param Data : Data to be transmitted. + * @retval None + */ +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Write in the DR register the data to be sent */ + SPIx->DR = Data; +} + +/** + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @retval The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the data in the DR register */ + return SPIx->DR; +} + +/** + * @brief Configures internally by software the NSS pin for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. + * This parameter can be one of the following values: + * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally + * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally + * @retval None + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + /* Set NSS pin internally by software */ + SPIx->CR1 |= SPI_NSSInternalSoft_Set; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/** + * @brief Enables or disables the SS output for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx SS output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CR2 |= CR2_SSOE_Set; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CR2 &= CR2_SSOE_Reset; + } +} + +/** + * @brief Configures the data size for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_DataSize: specifies the SPI data size. + * This parameter can be one of the following values: + * @arg SPI_DataSize_16b: Set data frame format to 16bit + * @arg SPI_DataSize_8b: Set data frame format to 8bit + * @retval None + */ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(SPI_DataSize)); + /* Clear DFF bit */ + SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; + /* Set new DFF bit value */ + SPIx->CR1 |= SPI_DataSize; +} + +/** + * @brief Transmit the SPIx CRC value. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval None + */ +void SPI_TransmitCRC(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Enable the selected SPI CRC transmission */ + SPIx->CR1 |= CR1_CRCNext_Set; +} + +/** + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx CRC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CR1 |= CR1_CRCEN_Set; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CR1 &= CR1_CRCEN_Reset; + } +} + +/** + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_CRC: specifies the CRC register to be read. + * This parameter can be one of the following values: + * @arg SPI_CRC_Tx: Selects Tx CRC register + * @arg SPI_CRC_Rx: Selects Rx CRC register + * @retval The selected CRC register value.. + */ +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CRC(SPI_CRC)); + if (SPI_CRC != SPI_CRC_Rx) + { + /* Get the Tx CRC register */ + crcreg = SPIx->TXCRCR; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->RXCRCR; + } + /* Return the selected CRC register */ + return crcreg; +} + +/** + * @brief Returns the CRC Polynomial register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the CRC polynomial register */ + return SPIx->CRCPR; +} + +/** + * @brief Selects the data transfer direction in bi-directional mode for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_Direction: specifies the data transfer direction in bi-directional mode. + * This parameter can be one of the following values: + * @arg SPI_Direction_Tx: Selects Tx transmission direction + * @arg SPI_Direction_Rx: Selects Rx receive direction + * @retval None + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + if (SPI_Direction == SPI_Direction_Tx) + { + /* Set the Tx only mode */ + SPIx->CR1 |= SPI_Direction_Tx; + } + else + { + /* Set the Rx only mode */ + SPIx->CR1 &= SPI_Direction_Rx; + } +} + +/** + * @brief Checks whether the specified SPI/I2S flag is set or not. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. + * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. + * @arg SPI_I2S_FLAG_BSY: Busy flag. + * @arg SPI_I2S_FLAG_OVR: Overrun flag. + * @arg SPI_FLAG_MODF: Mode Fault flag. + * @arg SPI_FLAG_CRCERR: CRC Error flag. + * @arg I2S_FLAG_UDR: Underrun Error flag. + * @arg I2S_FLAG_CHSIDE: Channel Side flag. + * @retval The new state of SPI_I2S_FLAG (SET or RESET). + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); + /* Check the status of the specified SPI/I2S flag */ + if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * @param SPI_I2S_FLAG: specifies the SPI flag to clear. + * This function clears only CRCERR flag. + * @note + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_SR register (SPI_I2S_GetFlagStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). + * @retval None + */ +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); + + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->SR = (uint16_t)~SPI_I2S_FLAG; +} + +/** + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. + * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. + * @arg SPI_I2S_IT_OVR: Overrun interrupt. + * @arg SPI_IT_MODF: Mode Fault interrupt. + * @arg SPI_IT_CRCERR: CRC Error interrupt. + * @arg I2S_IT_UDR: Underrun Error interrupt. + * @retval The new state of SPI_I2S_IT (SET or RESET). + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Get the SPI/I2S IT mask */ + itmask = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (SPIx->CR2 & itmask) ; + + /* Check the status of the specified SPI/I2S interrupt */ + if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. + * This function clears only CRCERR interrupt pending bit. + * @note + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_SR register (SPI_I2S_GetITStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable + * the SPI). + * @retval None + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); + + /* Get the SPI IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ + SPIx->SR = (uint16_t)~itpos; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_tim.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_tim.c new file mode 100644 index 0000000..81c8484 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_tim.c @@ -0,0 +1,2890 @@ +/** + ****************************************************************************** + * @file stm32f10x_tim.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the TIM firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_tim.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup TIM + * @brief TIM driver modules + * @{ + */ + +/** @defgroup TIM_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Defines + * @{ + */ + +/* ---------------------- TIM registers bit mask ------------------------ */ +#define SMCR_ETR_Mask ((uint16_t)0x00FF) +#define CCMR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +/** + * @} + */ + +/** @defgroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_FunctionPrototypes + * @{ + */ + +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +/** + * @} + */ + +/** @defgroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the TIMx peripheral registers to their default reset values. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @retval None + */ +void TIM_DeInit(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + if (TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if (TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if (TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if (TIMx == TIM4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + } + else if (TIMx == TIM5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); + } + else if (TIMx == TIM6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); + } + else if (TIMx == TIM7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); + } + else if (TIMx == TIM8) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); + } + else if (TIMx == TIM9) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); + } + else if (TIMx == TIM10) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); + } + else if (TIMx == TIM11) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); + } + else if (TIMx == TIM12) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); + } + else if (TIMx == TIM13) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); + } + else if (TIMx == TIM14) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); + } + else if (TIMx == TIM15) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); + } + else if (TIMx == TIM16) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); + } + else + { + if (TIMx == TIM17) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); + } + } +} + +/** + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef + * structure that contains the configuration information for the + * specified TIM peripheral. + * @retval None + */ +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); + assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + + tmpcr1 = TIMx->CR1; + + if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)|| + (TIMx == TIM4) || (TIMx == TIM5)) + { + /* Select the Counter Mode */ + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + if((TIMx != TIM6) && (TIMx != TIM7)) + { + /* Set the clock division */ + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + } + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler and the Repetition counter + values immediately */ + TIMx->EGR = TIM_PSCReloadMode_Immediate; +} + +/** + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E); + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P)); + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| + (TIMx == TIM16)|| (TIMx == TIM17)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N)); + + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select + * the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); + + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE)); + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + /* Reset the Output Compare IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4)); + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); + assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) ||(TIMx == TIM5)) + { + assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); + } + else + { + assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity)); + } + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* TI3 Configuration */ + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* TI4 Configuration */ + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external PWM signal. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + /* Select the Opposite Input */ + if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI2 Configuration */ + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI1 Configuration */ + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * @param TIMx: where x can be 1 or 8 to select the TIM + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @retval None + */ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); + assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); + assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); + assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); + assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); + /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/** + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef + * structure which will be initialized. + * @retval None + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/** + * @brief Fills each TIM_OCInitStruct member with its default value. + * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/** + * @brief Fills each TIM_ICInitStruct member with its default value. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/** + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which + * will be initialized. + * @retval None + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/** + * @brief Enables or disables the specified TIM peripheral. + * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. + * @param NewState: new state of the TIMx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CR1 |= TIM_CR1_CEN; + } + else + { + /* Disable the TIM Counter */ + TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); + } +} + +/** + * @brief Enables or disables the TIM peripheral Main Outputs. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral. + * @param NewState: new state of the TIM peripheral Main Outputs. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BDTR |= TIM_BDTR_MOE; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); + } +} + +/** + * @brief Enables or disables the specified TIM interrupts. + * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. + * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can only generate an update interrupt. + * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @param NewState: new state of the TIM interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DIER |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DIER &= (uint16_t)~TIM_IT; + } +} + +/** + * @brief Configures the TIMx event to be generate by software. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_EventSource: specifies the event source. + * This parameter can be one or more of the following values: + * @arg TIM_EventSource_Update: Timer update Event source + * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EventSource_COM: Timer COM event source + * @arg TIM_EventSource_Trigger: Timer Trigger Event source + * @arg TIM_EventSource_Break: Timer Break event source + * @note + * - TIM6 and TIM7 can only generate an update event. + * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. + * @retval None + */ +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); + + /* Set the event sources */ + TIMx->EGR = TIM_EventSource; +} + +/** + * @brief Configures the TIMx's DMA interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select + * the TIM peripheral. + * @param TIM_DMABase: DMA Base address. + * This parameter can be one of the following values: + * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, + * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, + * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, + * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, + * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, + * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, + * TIM_DMABase_DCR. + * @param TIM_DMABurstLength: DMA Burst length. + * This parameter can be one value between: + * TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * @retval None + */ +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); + assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; +} + +/** + * @brief Enables or disables the TIMx's DMA Requests. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 + * to select the TIM peripheral. + * @param TIM_DMASource: specifies the DMA Request sources. + * This parameter can be any combination of the following values: + * @arg TIM_DMA_Update: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_Trigger: TIM Trigger DMA source + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST9_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DIER |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DIER &= (uint16_t)~TIM_DMASource; + } +} + +/** + * @brief Configures the TIMx internal Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 + * to select the TIM peripheral. + * @retval None + */ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); +} + +/** + * @brief Configures the TIMx Internal Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ITRSource: Trigger source. + * This parameter can be one of the following values: + * @param TIM_TS_ITR0: Internal Trigger 0 + * @param TIM_TS_ITR1: Internal Trigger 1 + * @param TIM_TS_ITR2: Internal Trigger 2 + * @param TIM_TS_ITR3: Internal Trigger 3 + * @retval None + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); + /* Select the Internal Trigger */ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the TIMx Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_TIxExternalCLKSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector + * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 + * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 + * @param TIM_ICPolarity: specifies the TIx Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param ICFilter : specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * @retval None + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); + assert_param(IS_TIM_IC_FILTER(ICFilter)); + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + /* Select the Trigger source */ + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the External clock Mode1 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the SMS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SlaveMode_External1; + /* Select the Trigger selection : ETRF */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); + tmpsmcr |= TIM_TS_ETRF; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the External clock Mode2 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + /* Enable the External clock mode2 */ + TIMx->SMCR |= TIM_SMCR_ECE; +} + +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + tmpsmcr = TIMx->SMCR; + /* Reset the ETR Bits */ + tmpsmcr &= SMCR_ETR_Mask; + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the TIMx Prescaler. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param Prescaler: specifies the Prescaler Register value + * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode + * This parameter can be one of the following values: + * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. + * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately. + * @retval None + */ +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EGR = TIM_PSCReloadMode; +} + +/** + * @brief Specifies the TIMx Counter Mode to be used. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_CounterMode: specifies the Counter Mode to be used + * This parameter can be one of the following values: + * @arg TIM_CounterMode_Up: TIM Up Counting Mode + * @arg TIM_CounterMode_Down: TIM Down Counting Mode + * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 + * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 + * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 + * @retval None + */ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); + tmpcr1 = TIMx->CR1; + /* Reset the CMS and DIR Bits */ + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); + /* Set the Counter Mode */ + tmpcr1 |= TIM_CounterMode; + /* Write to TIMx CR1 register */ + TIMx->CR1 = tmpcr1; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_InputTriggerSource: The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the TIMx Encoder Interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. + * This parameter can be one of the following values: + * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. + * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. + * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending + * on the level of the other input. + * @param TIM_IC1Polarity: specifies the IC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @param TIM_IC2Polarity: specifies the IC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @retval None + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Set the encoder Mode */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); + tmpsmcr |= TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S))); + tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC1REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. + * @retval None + */ +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1M Bits */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC2REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. + * @retval None + */ +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2M Bits */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M); + /* Configure The Forced output Mode */ + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC3REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. + * @retval None + */ +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC1M Bits */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M); + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC4REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. + * @retval None + */ +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC2M Bits */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M); + /* Configure The Forced output Mode */ + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param NewState: new state of the TIMx peripheral Preload register + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the ARR Preload Bit */ + TIMx->CR1 |= TIM_CR1_ARPE; + } + else + { + /* Reset the ARR Preload Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); + } +} + +/** + * @brief Selects the TIM peripheral Commutation event. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral + * @param NewState: new state of the Commutation event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the COM Bit */ + TIMx->CR2 |= TIM_CR2_CCUS; + } + else + { + /* Reset the COM Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS); + } +} + +/** + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select + * the TIM peripheral. + * @param NewState: new state of the Capture Compare DMA source + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CR2 |= TIM_CR2_CCDS; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); + } +} + +/** + * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15 + * to select the TIMx peripheral + * @param NewState: new state of the Capture Compare Preload Control bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CR2 |= TIM_CR2_CCPC; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC); + } +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1PE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select + * the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2PE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3PE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4PE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 1 Fast feature. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1FE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 2 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select + * the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2FE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 3 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3FE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 4 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4FE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF1 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1CE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF2 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2CE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF3 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3CE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF4 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4CE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx channel 1 polarity. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC1P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P); + tmpccer |= TIM_OCPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 1N polarity. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC1N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC1NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); + tmpccer |= TIM_OCNPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 2 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC2P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 2N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC2N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC2NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 3 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC3 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC3P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 3N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC3N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC3NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 4 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC4 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC4P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. + * @retval None + */ +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCX(TIM_CCx)); + + tmp = CCER_CCE_Set << TIM_Channel; + + /* Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t)~ tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. + * @retval None + */ +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCXN(TIM_CCxN)); + + tmp = CCER_CCNE_Set << TIM_Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCER &= (uint16_t) ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/** + * @brief Selects the TIM Output Compare Mode. + * @note This function disables the selected channel before changing the Output + * Compare Mode. + * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_OCMode: specifies the TIM Output Compare Mode. + * This parameter can be one of the following values: + * @arg TIM_OCMode_Timing + * @arg TIM_OCMode_Active + * @arg TIM_OCMode_Toggle + * @arg TIM_OCMode_PWM1 + * @arg TIM_OCMode_PWM2 + * @arg TIM_ForcedAction_Active + * @arg TIM_ForcedAction_InActive + * @retval None + */ +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_OCM(TIM_OCMode)); + + tmp = (uint32_t) TIMx; + tmp += CCMR_Offset; + + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t) ~tmp1; + + if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel>>1); + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/** + * @brief Enables or Disables the TIMx Update event. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param NewState: new state of the TIMx UDIS bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CR1 |= TIM_CR1_UDIS; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); + } +} + +/** + * @brief Configures the TIMx Update Request Interrupt source. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_UpdateSource: specifies the Update source. + * This parameter can be one of the following values: + * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. + * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. + * @retval None + */ +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); + if (TIM_UpdateSource != TIM_UpdateSource_Global) + { + /* Set the URS Bit */ + TIMx->CR1 |= TIM_CR1_URS; + } + else + { + /* Reset the URS Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); + } +} + +/** + * @brief Enables or disables the TIMx's Hall sensor interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param NewState: new state of the TIMx Hall sensor interface. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CR2 |= TIM_CR2_TI1S; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); + } +} + +/** + * @brief Selects the TIMx's One Pulse Mode. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_OPMode: specifies the OPM Mode to be used. + * This parameter can be one of the following values: + * @arg TIM_OPMode_Single + * @arg TIM_OPMode_Repetitive + * @retval None + */ +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); + /* Reset the OPM Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM); + /* Configure the OPM Mode */ + TIMx->CR1 |= TIM_OPMode; +} + +/** + * @brief Selects the TIMx Trigger Output Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_TRGOSource: specifies the Trigger Output source. + * This paramter can be one of the following values: + * + * - For all TIMx + * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). + * + * - For all TIMx except TIM6 and TIM7 + * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag + * is to be set, as soon as a capture or compare match occurs (TRGO). + * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). + * + * @retval None + */ +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST7_PERIPH(TIMx)); + assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); + /* Reset the MMS Bits */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS); + /* Select the TRGO source */ + TIMx->CR2 |= TIM_TRGOSource; +} + +/** + * @brief Selects the TIMx Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_SlaveMode: specifies the Timer Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes + * the counter and triggers an update of the registers. + * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. + * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. + * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. + * @retval None + */ +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); + /* Reset the SMS Bits */ + TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS); + /* Select the Slave Mode */ + TIMx->SMCR |= TIM_SlaveMode; +} + +/** + * @brief Sets or Resets the TIMx Master/Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer + * and its slaves (through TRGO). + * @arg TIM_MasterSlaveMode_Disable: No action + * @retval None + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); + /* Reset the MSM Bit */ + TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM); + + /* Set or Reset the MSM Bit */ + TIMx->SMCR |= TIM_MasterSlaveMode; +} + +/** + * @brief Sets the TIMx Counter Register value + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param Counter: specifies the Counter register new value. + * @retval None + */ +void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/** + * @brief Sets the TIMx Autoreload Register value + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param Autoreload: specifies the Autoreload register new value. + * @retval None + */ +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Set the Autoreload Register value */ + TIMx->ARR = Autoreload; +} + +/** + * @brief Sets the TIMx Capture Compare1 Register value + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param Compare1: specifies the Capture Compare1 register new value. + * @retval None + */ +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + /* Set the Capture Compare1 Register value */ + TIMx->CCR1 = Compare1; +} + +/** + * @brief Sets the TIMx Capture Compare2 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param Compare2: specifies the Capture Compare2 register new value. + * @retval None + */ +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Set the Capture Compare2 Register value */ + TIMx->CCR2 = Compare2; +} + +/** + * @brief Sets the TIMx Capture Compare3 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare3: specifies the Capture Compare3 register new value. + * @retval None + */ +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Set the Capture Compare3 Register value */ + TIMx->CCR3 = Compare3; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare4: specifies the Capture Compare4 register new value. + * @retval None + */ +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Set the Capture Compare4 Register value */ + TIMx->CCR4 = Compare4; +} + +/** + * @brief Sets the TIMx Input Capture 1 prescaler. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC1PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); + /* Set the IC1PSC value */ + TIMx->CCMR1 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 2 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC2PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); + /* Set the IC2PSC value */ + TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Input Capture 3 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC3PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); + /* Set the IC3PSC value */ + TIMx->CCMR2 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 4 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC4PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); + /* Set the IC4PSC value */ + TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Clock Division value. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select + * the TIM peripheral. + * @param TIM_CKD: specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CKD_DIV1: TDTS = Tck_tim + * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim + * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim + * @retval None + */ +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_CKD_DIV(TIM_CKD)); + /* Reset the CKD Bits */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD); + /* Set the CKD value */ + TIMx->CR1 |= TIM_CKD; +} + +/** + * @brief Gets the TIMx Input Capture 1 value. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @retval Capture Compare 1 Register value. + */ +uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + /* Get the Capture 1 Register value */ + return TIMx->CCR1; +} + +/** + * @brief Gets the TIMx Input Capture 2 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @retval Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Get the Capture 2 Register value */ + return TIMx->CCR2; +} + +/** + * @brief Gets the TIMx Input Capture 3 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 3 Register value. + */ +uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Get the Capture 3 Register value */ + return TIMx->CCR3; +} + +/** + * @brief Gets the TIMx Input Capture 4 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 4 Register value. + */ +uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Get the Capture 4 Register value */ + return TIMx->CCR4; +} + +/** + * @brief Gets the TIMx Counter value. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @retval Counter Register value. + */ +uint16_t TIM_GetCounter(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @retval Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, + * TIM_FLAG_CC2 or TIM_FLAG_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. + * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); + + if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's pending flags. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, + * TIM_FLAG_CC2 or TIM_FLAG_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. + * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval None + */ +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); + + /* Clear the flags */ + TIMx->SR = (uint16_t)~TIM_FLAG; +} + +/** + * @brief Checks whether the TIM interrupt has occurred or not. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_IT: specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval The new state of the TIM_IT(SET or RESET). + */ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_IT(TIM_IT)); + + itstatus = TIMx->SR & TIM_IT; + + itenable = TIMx->DIER & TIM_IT; + if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's interrupt pending bits. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_IT: specifies the pending bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM1 update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval None + */ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + /* Clear the IT pending Bit */ + TIMx->SR = (uint16_t)~TIM_IT; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) ||(TIMx == TIM5)) + { + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); + } + else + { + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); + } + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) ||(TIMx == TIM5)) + { + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); + } + else + { + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E); + } + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) ||(TIMx == TIM5)) + { + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); + } + else + { + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E); + } + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) ||(TIMx == TIM5)) + { + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); + } + else + { + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E); + } + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_usart.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_usart.c new file mode 100644 index 0000000..a3f16f1 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_usart.c @@ -0,0 +1,1058 @@ +/** + ****************************************************************************** + * @file stm32f10x_usart.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the USART firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_usart.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup USART + * @brief USART driver modules + * @{ + */ + +/** @defgroup USART_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Defines + * @{ + */ + +#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */ +#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */ + +#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */ + +#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */ +#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */ +#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */ +#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */ +#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */ + +#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */ +#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */ + +#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */ +#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */ +#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */ + +#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */ +#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */ + +#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */ +#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */ + +#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */ +#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */ + +#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */ +#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */ + +#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */ +#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */ +#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */ +#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */ + +/* USART OverSampling-8 Mask */ +#define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */ +#define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */ + +/* USART One Bit Sampling Mask */ +#define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */ + +/** + * @} + */ + +/** @defgroup USART_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the USARTx peripheral registers to their default reset values. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @retval None + */ +void USART_DeInit(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + if (USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if (USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if (USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if (USARTx == UART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); + } + else + { + if (USARTx == UART5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); + } + } +} + +/** + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct . + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified USART + * peripheral. + * @retval None + */ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); + /* The hardware flow control is available only for USART1, USART2 and USART3 */ + if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear STOP[13:12] bits */ + tmpreg &= CR2_STOP_CLEAR_Mask; + /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ + /* Set STOP[13:12] bits according to USART_StopBits value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; + +/*---------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = USARTx->CR1; + /* Clear M, PCE, PS, TE and RE bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure the USART Word Length, Parity and mode ----------------------- */ + /* Set the M bits according to USART_WordLength value */ + /* Set PCE and PS bits according to USART_Parity value */ + /* Set TE and RE bits according to USART_Mode value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + /* Write to USART CR1 */ + USARTx->CR1 = (uint16_t)tmpreg; + +/*---------------------------- USART CR3 Configuration -----------------------*/ + tmpreg = USARTx->CR3; + /* Clear CTSE and RTSE bits */ + tmpreg &= CR3_CLEAR_Mask; + /* Configure the USART HFC -------------------------------------------------*/ + /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + /* Write to USART CR3 */ + USARTx->CR3 = (uint16_t)tmpreg; + +/*---------------------------- USART BRR Configuration -----------------------*/ + /* Configure the USART Baud Rate -------------------------------------------*/ + RCC_GetClocksFreq(&RCC_ClocksStatus); + if (usartxbase == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + /* Determine the integer part */ + if ((USARTx->CR1 & CR1_OVER8_Set) != 0) + { + /* Integer part computing in case Oversampling mode is 8 Samples */ + integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); + } + else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ + { + /* Integer part computing in case Oversampling mode is 16 Samples */ + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + } + tmpreg = (integerdivider / 100) << 4; + + /* Determine the fractional part */ + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + + /* Implement the fractional part in the register */ + if ((USARTx->CR1 & CR1_OVER8_Set) != 0) + { + tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); + } + else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ + { + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + } + + /* Write to USART BRR */ + USARTx->BRR = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_InitStruct member with its default value. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * @retval None + */ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No ; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/** + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. + * @retval None + */ +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); + assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); + assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); + assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear CLKEN, CPOL, CPHA and LBCL bits */ + tmpreg &= CR2_CLOCK_CLEAR_Mask; + /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ + /* Set CLKEN bit according to USART_Clock value */ + /* Set CPOL bit according to USART_CPOL value */ + /* Set CPHA bit according to USART_CPHA value */ + /* Set LBCL bit according to USART_LastBit value */ + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_ClockInitStruct member with its default value. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * @retval None + */ +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/** + * @brief Enables or disables the specified USART peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USARTx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected USART by setting the UE bit in the CR1 register */ + USARTx->CR1 |= CR1_UE_Set; + } + else + { + /* Disable the selected USART by clearing the UE bit in the CR1 register */ + USARTx->CR1 &= CR1_UE_Reset; + } +} + +/** + * @brief Enables or disables the specified USART interrupts. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Transmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @param NewState: new state of the specified USARTx interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CONFIG_IT(USART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + + /* Get the interrupt position */ + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + usartxbase += 0x0C; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + usartxbase += 0x10; + } + else /* The IT is in CR3 register */ + { + usartxbase += 0x14; + } + if (NewState != DISABLE) + { + *(__IO uint32_t*)usartxbase |= itmask; + } + else + { + *(__IO uint32_t*)usartxbase &= ~itmask; + } +} + +/** + * @brief Enables or disables the USART’s DMA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_DMAReq: specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg USART_DMAReq_Tx: USART DMA transmit request + * @arg USART_DMAReq_Rx: USART DMA receive request + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @note The DMA mode is not available for UART5 except in the STM32 + * High density value line devices(STM32F10X_HD_VL). + * @retval None + */ +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DMAREQ(USART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 &= (uint16_t)~USART_DMAReq; + } +} + +/** + * @brief Sets the address of the USART node. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_Address: Indicates the address of the USART node. + * @retval None + */ +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ADDRESS(USART_Address)); + + /* Clear the USART address */ + USARTx->CR2 &= CR2_Address_Mask; + /* Set the USART address node */ + USARTx->CR2 |= USART_Address; +} + +/** + * @brief Selects the USART WakeUp method. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_WakeUp: specifies the USART wakeup method. + * This parameter can be one of the following values: + * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection + * @arg USART_WakeUp_AddressMark: WakeUp by an address mark + * @retval None + */ +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_WAKEUP(USART_WakeUp)); + + USARTx->CR1 &= CR1_WAKE_Mask; + USARTx->CR1 |= USART_WakeUp; +} + +/** + * @brief Determines if the USART is in mute mode or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART mute mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ + USARTx->CR1 |= CR1_RWU_Set; + } + else + { + /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ + USARTx->CR1 &= CR1_RWU_Reset; + } +} + +/** + * @brief Sets the USART LIN Break detection length. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_LINBreakDetectLength: specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg USART_LINBreakDetectLength_10b: 10-bit break detection + * @arg USART_LINBreakDetectLength_11b: 11-bit break detection + * @retval None + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); + + USARTx->CR2 &= CR2_LBDL_Mask; + USARTx->CR2 |= USART_LINBreakDetectLength; +} + +/** + * @brief Enables or disables the USART’s LIN mode. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART LIN mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + USARTx->CR2 |= CR2_LINEN_Set; + } + else + { + /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ + USARTx->CR2 &= CR2_LINEN_Reset; + } +} + +/** + * @brief Transmits single data through the USARTx peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Data: the data to transmit. + * @retval None + */ +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->DR = (Data & (uint16_t)0x01FF); +} + +/** + * @brief Returns the most recent received data by the USARTx peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @retval The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Receive Data */ + return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); +} + +/** + * @brief Transmits break characters. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @retval None + */ +void USART_SendBreak(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Send break characters */ + USARTx->CR1 |= CR1_SBK_Set; +} + +/** + * @brief Sets the specified USART guard time. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param USART_GuardTime: specifies the guard time. + * @note The guard time bits are not available for UART4 and UART5. + * @retval None + */ +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + + /* Clear the USART Guard time */ + USARTx->GTPR &= GTPR_LSB_Mask; + /* Set the USART guard time */ + USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/** + * @brief Sets the system clock prescaler. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_Prescaler: specifies the prescaler clock. + * @note The function is used for IrDA mode with UART4 and UART5. + * @retval None + */ +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Clear the USART prescaler */ + USARTx->GTPR &= GTPR_MSB_Mask; + /* Set the USART prescaler */ + USARTx->GTPR |= USART_Prescaler; +} + +/** + * @brief Enables or disables the USART’s Smart Card mode. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param NewState: new state of the Smart Card mode. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4 and UART5. + * @retval None + */ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CR3 register */ + USARTx->CR3 |= CR3_SCEN_Set; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ + USARTx->CR3 &= CR3_SCEN_Reset; + } +} + +/** + * @brief Enables or disables NACK transmission. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param NewState: new state of the NACK transmission. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4 and UART5. + * @retval None + */ +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ + USARTx->CR3 |= CR3_NACK_Set; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ + USARTx->CR3 &= CR3_NACK_Reset; + } +} + +/** + * @brief Enables or disables the USART’s Half Duplex communication. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART Communication. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + USARTx->CR3 |= CR3_HDSEL_Set; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ + USARTx->CR3 &= CR3_HDSEL_Reset; + } +} + + +/** + * @brief Enables or disables the USART's 8x oversampling mode. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART one bit sampling method. + * This parameter can be: ENABLE or DISABLE. + * @note + * This function has to be called before calling USART_Init() + * function in order to have correct baudrate Divider value. + * @retval None + */ +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ + USARTx->CR1 |= CR1_OVER8_Set; + } + else + { + /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ + USARTx->CR1 &= CR1_OVER8_Reset; + } +} + +/** + * @brief Enables or disables the USART's one bit sampling method. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART one bit sampling method. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ + USARTx->CR3 |= CR3_ONEBITE_Set; + } + else + { + /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */ + USARTx->CR3 &= CR3_ONEBITE_Reset; + } +} + +/** + * @brief Configures the USART's IrDA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IrDAMode: specifies the IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IrDAMode_LowPower + * @arg USART_IrDAMode_Normal + * @retval None + */ +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + USARTx->CR3 &= CR3_IRLP_Mask; + USARTx->CR3 |= USART_IrDAMode; +} + +/** + * @brief Enables or disables the USART's IrDA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the IrDA mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ + USARTx->CR3 |= CR3_IREN_Set; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ + USARTx->CR3 &= CR3_IREN_Reset; + } +} + +/** + * @brief Checks whether the specified USART flag is set or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LBD: LIN Break detection flag + * @arg USART_FLAG_TXE: Transmit data register empty flag + * @arg USART_FLAG_TC: Transmission Complete flag + * @arg USART_FLAG_RXNE: Receive data register not empty flag + * @arg USART_FLAG_IDLE: Idle Line detection flag + * @arg USART_FLAG_ORE: OverRun Error flag + * @arg USART_FLAG_NE: Noise Error flag + * @arg USART_FLAG_FE: Framing Error flag + * @arg USART_FLAG_PE: Parity Error flag + * @retval The new state of USART_FLAG (SET or RESET). + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4 and UART5 */ + if (USART_FLAG == USART_FLAG_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the USARTx's pending flags. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). + * @arg USART_FLAG_LBD: LIN Break detection flag. + * @arg USART_FLAG_TC: Transmission Complete flag. + * @arg USART_FLAG_RXNE: Receive data register not empty flag. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_SR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DR register + * (USART_SendData()). + * @retval None + */ +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4 and UART5 */ + if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + USARTx->SR = (uint16_t)~USART_FLAG; +} + +/** + * @brief Checks whether the specified USART interrupt has occurred or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Tansmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_ORE: OverRun Error interrupt + * @arg USART_IT_NE: Noise Error interrupt + * @arg USART_IT_FE: Framing Error interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @retval The new state of USART_IT (SET or RESET). + */ +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_GET_IT(USART_IT)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + /* Get the interrupt position */ + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + itmask &= USARTx->CR1; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + itmask &= USARTx->CR2; + } + else /* The IT is in CR3 register */ + { + itmask &= USARTx->CR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->SR; + if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Clears the USARTx's interrupt pending bits. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TC: Transmission complete interrupt. + * @arg USART_IT_RXNE: Receive Data register not empty interrupt. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_SR register + * (USART_GetITStatus()) followed by a read operation to USART_DR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_SR register (USART_GetITStatus()) followed by a write + * operation to USART_DR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DR register + * (USART_SendData()). + * @retval None + */ +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_IT(USART_IT)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->SR = (uint16_t)~itmask; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/src/stm32f10x_wwdg.c b/Project/econais/STM32_Libs/F1/src/stm32f10x_wwdg.c new file mode 100644 index 0000000..77a7ce5 --- /dev/null +++ b/Project/econais/STM32_Libs/F1/src/stm32f10x_wwdg.c @@ -0,0 +1,224 @@ +/** + ****************************************************************************** + * @file stm32f10x_wwdg.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the WWDG firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_wwdg.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup WWDG + * @brief WWDG driver modules + * @{ + */ + +/** @defgroup WWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Defines + * @{ + */ + +/* ----------- WWDG registers bit address in the alias region ----------- */ +#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) + +/* Alias word address of EWI bit */ +#define CFR_OFFSET (WWDG_OFFSET + 0x04) +#define EWI_BitNumber 0x09 +#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) + +/* --------------------- WWDG registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_WDGA_Set ((uint32_t)0x00000080) + +/* CFR register bit mask */ +#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/** + * @} + */ + +/** @defgroup WWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the WWDG peripheral registers to their default reset values. + * @param None + * @retval None + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/** + * @brief Sets the WWDG Prescaler. + * @param WWDG_Prescaler: specifies the WWDG Prescaler. + * This parameter can be one of the following values: + * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 + * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 + * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 + * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 + * @retval None + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); + /* Clear WDGTB[1:0] bits */ + tmpreg = WWDG->CFR & CFR_WDGTB_Mask; + /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ + tmpreg |= WWDG_Prescaler; + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Sets the WWDG window value. + * @param WindowValue: specifies the window value to be compared to the downcounter. + * This parameter value must be lower than 0x80. + * @retval None + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); + /* Clear W[6:0] bits */ + + tmpreg = WWDG->CFR & CFR_W_Mask; + + /* Set W[6:0] bits according to WindowValue value */ + tmpreg |= WindowValue & (uint32_t) BIT_Mask; + + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Enables the WWDG Early Wakeup interrupt(EWI). + * @param None + * @retval None + */ +void WWDG_EnableIT(void) +{ + *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; +} + +/** + * @brief Sets the WWDG counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + * @retval None + */ +void WWDG_SetCounter(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CR = Counter & BIT_Mask; +} + +/** + * @brief Enables WWDG and load the counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + * @retval None + */ +void WWDG_Enable(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + WWDG->CR = CR_WDGA_Set | Counter; +} + +/** + * @brief Checks whether the Early Wakeup interrupt flag is set or not. + * @param None + * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->SR); +} + +/** + * @brief Clears Early Wakeup interrupt flag. + * @param None + * @retval None + */ +void WWDG_ClearFlag(void) +{ + WWDG->SR = (uint32_t)RESET; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/econais/STM32_Libs/F1/stm32f1Library.mk b/Project/econais/STM32_Libs/F1/stm32f1Library.mk new file mode 100644 index 0000000..a9b663f --- /dev/null +++ b/Project/econais/STM32_Libs/F1/stm32f1Library.mk @@ -0,0 +1,32 @@ +STM_LIBRARY_FOLDER = $(CHIBIOS)/econais/STM32_Libs/F1 + +STM_LIBRARY_SRC = $(STM_LIBRARY_FOLDER)/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c \ + $(STM_LIBRARY_FOLDER)/src/misc.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_adc.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_bkp.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_can.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_cec.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_crc.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_dac.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_dma.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_exti.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_flash.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_fsmc.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_gpio.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_i2c.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_iwdg.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_pwr.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_rcc.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_rtc.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_spi.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_sdio.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_tim.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_dbgmcu.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_usart.c \ + $(STM_LIBRARY_FOLDER)/src/stm32f10x_wwdg.c + +# Required include directories +STM_LIBRARY_INC = \ + $(STM_LIBRARY_FOLDER)/CMSIS/CM3/CoreSupport \ + $(STM_LIBRARY_FOLDER)/CMSIS/CM3/DeviceSupport/ST/STM32F10x \ + $(STM_LIBRARY_FOLDER)/inc \ No newline at end of file diff --git a/Project/econais/build/configs.inc b/Project/econais/build/configs.inc new file mode 100644 index 0000000..9375926 --- /dev/null +++ b/Project/econais/build/configs.inc @@ -0,0 +1,8 @@ +LIB_CONFIG = release +LIB_BOOTLOADER = BOOTLOADER_NONE +LIB_PLAT = STM32F1 +LIB_USE_DEBUGER = false +LIB_RF_TEST = no +LIB_USE_UPNP = yes +LIB_USE_WPS = yes +LIB_USE_8021X = yes diff --git a/Project/econais/inc/STM32F1/chconf.h b/Project/econais/inc/STM32F1/chconf.h new file mode 100644 index 0000000..1547fbd --- /dev/null +++ b/Project/econais/inc/STM32F1/chconf.h @@ -0,0 +1,572 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +// Simplified the priority +#define CORTEX_SIMPLIFIED_PRIORITY TRUE +#define CORTEX_ENABLE_WFI_IDLE TRUE + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#if defined(LIBWISMART_RELEASE) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#else +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#if defined(LIBWISMART_RELEASE) +#define CH_DBG_ENABLE_CHECKS FALSE +#else +#define CH_DBG_ENABLE_CHECKS TRUE +#endif +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#if defined(LIBWISMART_RELEASE) +#define CH_DBG_ENABLE_ASSERTS FALSE +#else +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#if defined(LIBWISMART_RELEASE) +#define CH_DBG_ENABLE_TRACE FALSE +#else +#define CH_DBG_ENABLE_TRACE TRUE +#endif +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#if defined(LIBWISMART_RELEASE) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#else +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#if defined(LIBWISMART_RELEASE) +#define CH_DBG_FILL_THREADS FALSE +#else +#define CH_DBG_FILL_THREADS TRUE +#endif +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#define CORTEX_USE_FPU FALSE + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/Project/econais/inc/STM32F1/libwismart_irqs.h b/Project/econais/inc/STM32F1/libwismart_irqs.h new file mode 100644 index 0000000..4a1e1dc --- /dev/null +++ b/Project/econais/inc/STM32F1/libwismart_irqs.h @@ -0,0 +1,116 @@ + +/*****************************************************************************/ +/* */ +/* Copyright (C) 2010-2012 eConais */ +/* */ +/* Irq Handlers Module */ +/* */ +/*****************************************************************************/ + +#include "libwismart.h" + +/* include the platform hdrs */ +#include "stm32f10x.h" + +#define PRINT print + +void memp_status(void); + +/* ---------------------------------------------------------------------------------- */ +/* Errors IRQ Handlers */ +/* ---------------------------------------------------------------------------------- */ +#if !defined(LIBWISMART_RELEASE) +static const char *states[] = {THD_STATE_NAMES}; +#endif + +void NMIVector(void) {PRINT("NMI");while(1){};} +void MemManageVector(void) {PRINT("mem!");while(1){};} +void BusFaultVector(void) {PRINT("bus fault!");while(1){};} +void UsageFaultVector(void) {PRINT("usage fault!");while(1){};} +void HardFaultVector(void) { +#if !defined(LIBWISMART_RELEASE) + size_t nFrag, nSize; + Thread *tp; + + nFrag = chHeapStatus(NULL, &nSize); + + PRINT("\r\n<======= hard! =======>\r\n"); + PRINT("[Heap Statistics] FreeFrags:%d , FreeSize: %d bytes Core:%d bytes\r\n",nFrag,nSize,chCoreStatus()); + + /* ---------------- lwip pools info ------------- */ + + /* print statistics of the lwip mem pool */ + memp_status(); + + /* ---------------- Threads info ---------------- */ + PRINT(" addr stack prio refs state time StkUnused Name\r\n"); + tp = chRegFirstThread(); + do { + PRINT("0x%x 0x%x %u %u %s %lu ", + (uint32_t)tp, (uint32_t)tp->p_ctx.r13, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + +#if CH_DBG_ENABLE_STACK_CHECK + /* print the unused stack size */ + PRINT("%lu ", (uint32_t)((uint8_t *)tp->p_ctx.r13 - (uint8_t *)tp->p_stklimit)); +#endif + + PRINT("%s ", tp->p_name); + + PRINT("\r\n"); + tp = chRegNextThread(tp); + } while (tp != NULL); + + while(1){}; +#endif +} + + +/* ---------------------------------------------------------------------------------- */ +/* IRQ Handlers */ +/* ---------------------------------------------------------------------------------- */ + +#ifndef USER_IRQS +// UART recv handler +CH_IRQ_HANDLER(USART1_IRQHandler) +{ + CH_IRQ_PROLOGUE(); + + libwismart_UART_IRQHandler(); + + CH_IRQ_EPILOGUE(); +} + +// WiFi external irq +CH_IRQ_HANDLER(EXTI0_IRQHandler) +{ + CH_IRQ_PROLOGUE(); + + libwismart_WiFi_IRQHandler(); + + CH_IRQ_EPILOGUE(); +} + +// UART TX dma irq +CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) +{ + CH_IRQ_PROLOGUE(); + + libwismart_UART_TXDMA_IRQHandler(); + + CH_IRQ_EPILOGUE(); +} + + +// UART RX dma irq +CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) +{ + CH_IRQ_PROLOGUE(); + + libwismart_UART_RXDMA_IRQHandler(); + + CH_IRQ_EPILOGUE(); +} + +#endif diff --git a/Project/econais/inc/STM32F1/mcuconf.h b/Project/econais/inc/STM32F1/mcuconf.h new file mode 100644 index 0000000..637d4b2 --- /dev/null +++ b/Project/econais/inc/STM32F1/mcuconf.h @@ -0,0 +1,206 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32F1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C3_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_I2C3_DMA_PRIORITY 1 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/Project/econais/libwismart.h b/Project/econais/libwismart.h new file mode 100644 index 0000000..bc7e5b9 --- /dev/null +++ b/Project/econais/libwismart.h @@ -0,0 +1,2477 @@ + +/** + * \file libwismart.h + * WiSmart library header file. + * \author + * eConais RnD Group + */ + +/* + * This software is copyrighted by and is the sole property of eConais. + * All rights, title, ownership, or other interests in the software remain + * the property of eConais. This software may only be used in accordance + * with the corresponding license agreement. Any unauthorized use, + * duplication, transmission, distribution, or disclosure of this software + * is expressly forbidden. + * + * This copyright notice may not be removed or modified without prior written + * consent of eConais. + * + * eConais reserves the right to modify this software without + * notice. + * + * eConais + * Patras Science Park support@econais.com + * 26504 Platani, Patras http://www.econais.com + * GREECE + + * + * This file is part of WiSmart SDK + * + * Author: eConais RnD Group + * + */ + +#ifndef LIBWISMART_H_ +#define LIBWISMART_H_ + +#include "ch.h" +#include +#include +#include +#include +#include /* chprintf */ + +/* include file with mcu specific defines */ +#include "libwismart_mcu.h" + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef NULL +#define NULL (void *)0 +#endif + +#ifndef WISMART_SUCCESS +#define WISMART_SUCCESS 1 +#endif + +#ifndef WISMART_FAILURE +#define WISMART_FAILURE 0 +#endif + +/* generic print function */ +void print(const char *fmt, ...); +#define printf print +#ifndef PRINT +#define PRINT print +#endif + +/** \addtogroup WSL_SYSTEM +* +* @{ +*/ + +typedef struct { + void * port; /* type GPIO_TypeDef* */ + uint32_t ahb; + uint16_t pin; + uint8_t source; + uint32_t remap; +} wismart_hwif_port_t; + +typedef struct { + /* external interrupt */ + wismart_hwif_port_t gpio_ext_int; + + uint8_t exti_port_source; + uint8_t exti_pin_source; + uint32_t exti_line; + uint8_t exti_irq_number; /* type IRQn_Type */ + + /* 1.2v wifi regulator */ + wismart_hwif_port_t gpio_1_2v; + + /* 3.3v wifi regulator */ + wismart_hwif_port_t gpio_3_3v; +} wismart_hwif_wifi_t; + +typedef struct { + uint8_t enable; + void * channel; + uint8_t irq; + uint32_t it_complete; +} wismart_hwif_dma_t; + +typedef struct { + void * usart; /* type USART_TypeDef* */ + uint32_t baud_rate; + uint8_t tx_irq; /* type IRQn_Type */ + uint32_t tx_rcc; + uint8_t gpio_af; + + /* GPIO Configurations */ + wismart_hwif_port_t gpio_tx; + wismart_hwif_port_t gpio_rx; + + /* DMA Configurations */ + wismart_hwif_dma_t dma_tx; + wismart_hwif_dma_t dma_rx; + + /* GPIO Configurations */ + wismart_hwif_port_t gpio_rts; + +} wismart_hwif_usart_t; + +typedef struct { + uint8_t isFS; /* enable or disable FS */ + uint8_t useULPI_PHY; + + /* FS pins- HS pins without PHY */ + uint32_t fs_ahb; + wismart_hwif_port_t host_powersw; + + wismart_hwif_port_t sof; + wismart_hwif_port_t vbus; + wismart_hwif_port_t id; + wismart_hwif_port_t dm; + wismart_hwif_port_t dp; + + /* HS pins with PHY*/ + wismart_hwif_port_t D[8]; + wismart_hwif_port_t hs_clk; + wismart_hwif_port_t hs_stp; + wismart_hwif_port_t hs_nxt; + wismart_hwif_port_t hs_dir; + +} wismart_hwif_usb_t; + +typedef enum { +#ifdef STM32F1 + /* + HSE + */ + WISMART_MCU_FREQ_32_HSE = 1, + WISMART_MCU_FREQ_48_HSE = 3, + WISMART_MCU_FREQ_64_HSE = 5, + WISMART_MCU_FREQ_72_HSE = 7, + + /* + HSI + */ + WISMART_MCU_FREQ_36_HSI = 0, + WISMART_MCU_FREQ_48_HSI = 2, + WISMART_MCU_FREQ_64_HSI = 4, +#endif + +#ifdef STM32F4 +/* TODO: Add the frequency that F4 support */ +#endif +} wismart_hwif_mcu_freq_t; + +typedef struct { + wismart_hwif_mcu_freq_t freq; + uint8_t enableWkupPin; +} wismart_hwif_mcu_t; + +typedef struct { + wismart_hwif_mcu_t mcu; + wismart_hwif_wifi_t wifi; + wismart_hwif_usart_t debug; + wismart_hwif_usb_t usb; +} wismart_hwif_t; + +typedef enum { + WISMART_ENCRYPTION_OPEN, + WISMART_ENCRYPTION_WEP, + WISMART_ENCRYPTION_WPAWPA2 +} wismart_bss_encryption_t; + +typedef struct { + uint8_t ssid[32]; + uint8_t ssid_len; + uint8_t mac_address[6]; + int32_t rssi; + int32_t snr; + uint8_t channel; + uint8_t encryption; /* wismart_bss_encryption_t */ + uint8_t bssType; +} wismart_scan_result_t; + +typedef struct { + uint8_t min_channel_time; + uint8_t max_channel_time; + char ssid[33]; + uint16_t channels; +} wismart_scan_parms_t; + + +enum { + WISMART_PERIPHERAL_DMA2, /* DMA2 is used by SDIO peripheral. SDIO must be the only owner of DMA2 or else TX underruns/RX overruns will occur */ +}; + +/** @} */ + + +#define RAM_CCM_SECTION __attribute__ ((section(".ccm"))) +enum { + WISMART_WIFI_DISCONNECTED, + WISMART_WIFI_CONNECTED, + WISMART_WRONG_PASSPHRASE, + WISMART_WIFI_CONN_TIMEOUT, + WISMART_WIFI_CONN_FAILED +}; + +enum { + WISMART_DHCP_SUCCESS, + WISMART_DHCP_FAILED +}; + +typedef enum { + WISMART_MODE_SOFTAP, + WISMART_MODE_CLIENT, + WISMART_MODE_ADHOC +} wismart_mode_e; + + +/* + Below are the return status codes of libwismart_IsConnected(): + + WISMART_NOT_CONNECTED: WiFi not connected yet + WISMART_ASSOCIATED: WiFi connected, no IP connectivity yet + WISMART_CONNECT: WiFi connected, IP connection completed + */ +enum { + WISMART_NOT_CONNECTED, + WISMART_ASSOCIATED, + WISMART_CONNECTED +}; + +enum +{ + LIBWISMART_DHCP_START=0, + LIBWISMART_DHCP_WAIT_ADDRESS, + LIBWISMART_DHCP_ADDRESS_ASSIGNED, + LIBWISMART_DHCP_TIMEOUT +}; +/** @} */ + +/*---------------------------------------------------------------------------*/ +/** \defgroup WSL_INIT Initialization +* +* \brief The group of functions to initialize library, Wi-Fi, TPC/IP and shutdown the Wi-Fi +* @{ +*/ + +/** + * \fn const char* libwismart_GetVersion(void); + * \brief Get the version of libwismart + * + * This function can be used to get the version of libwismart + * + * @return version the libwismart version string, e.g "1.0.0" + * +*/ +const char* libwismart_GetVersion(void); + + +/*---------------------------------------------------------------------------*/ +/** \brief Get the Default HW interface of the wismart. + * + * This function return the default HW interface that we can use on init + * function. We can use this function to get the default hwif and then modify + * it for our platform. + * + * +*/ +wismart_hwif_t libwismart_GetDefaultHWIF(void); + +/*---------------------------------------------------------------------------*/ +/** \brief Initialize the library. + * + * This function will take care the device initialization + * This includes initialization for MCU, Sensors, I/O and Wi-FI. + * This is the first function to call before anything else, + * otherwise the device will not function properly. + * + * @param user_hw The HW stuct for all internal modules. + * +*/ +int libwismart_Init(wismart_hwif_t user_hw); + +/*---------------------------------------------------------------------------*/ +/** \brief Init WiFi Module + * + * This function initialize WiFi module and prepares the hardware to be ready + * for connection. + * + */ +int libwismart_WiFiInit(void); + +/*---------------------------------------------------------------------------*/ +/** \brief Set WiFi MAC Address + * + * This function set the WiFi mac address. + * This function must be called before libwismart_WiFiInit to be valid. + * To disable the user defined mac address you must set the mac to ff:ff:ff:ff:ff:ff. + * The selected mac is remaining and after rebooting or shutdown. + * + */ +void libwismart_WiFi_Set_MAC(char *mac); + +/*---------------------------------------------------------------------------*/ +/** \brief Get WiFi MAC Address + * + * This function return the WiFi mac address. + * The mac address is valid only when the WiFi is on, + * otherwise is return 00:00:00:00:00:00. + * + */ +void libwismart_WiFi_Get_MAC(char *mac); + + +/*---------------------------------------------------------------------------*/ +/** \brief Shutdown WiFi Module + * + * This function closes the WiFi module. It can be used to limit the power + * consumption. To re-enable the WiFi, run libwismart_WiFiInit() + * + */ +int libwismart_WiFiShutdown(void); + +/*---------------------------------------------------------------------------*/ +/** \brief Get WiFi MAC Address + * + * This function returns the wifi mode of operation. + * \retval WISMART_MODE_CLIENT + * \retval WISMART_MODE_SOFTAP + * \retval WISMART_MODE_ADHOC + */ +uint8_t libwismart_GetWiFiMode(void); +/** @} */ + +/*---------------------------------------------------------------------------*/ +/** \defgroup WSL_SYSTEM System management +* +* \brief Set of library functions to manage system resources, reboot the system, +* handle IRQs and I/O ports like USB +* @{ +*/ + +/** + * A timer. + * + * This structure is used for declaring a timer. The timer must be set + * with libwismart_TimerSet() before it can be used. + * + * \hideinitializer + */ +typedef unsigned long wismart_time_t; +struct wismart_timer { + VirtualTimer vt; + vtfunc_t func; + void *params; + wismart_time_t interval; +}; + +typedef struct wismart_timer wismart_timer_t; + +/*---------------------------------------------------------------------------*/ +/** + * Set a timer. + * + * This function is used to set a timer for a time sometime in the + * future. + * + * \param t A pointer to the timer + * \param interval The interval before the timer expires + * \param func callback function that is called when the timer expires + * \param params extra data to pass in func + */ +void libwismart_TimerSet(wismart_timer_t *t, wismart_time_t interval, vtfunc_t func, void * params); + +/*---------------------------------------------------------------------------*/ +/** + * Set a timer from within an IRQ handler. + * + * This function is used to set a timer for a time sometime in the + * future. It should be used only when a timer must be set from within + * an IRQ handler. + * + * \param t A pointer to the timer + * \param interval The interval before the timer expires + * \param func callback function that is called when the timer expires + * \param params extra data to pass in func + */ +void libwismart_TimerSetI(wismart_timer_t *t, wismart_time_t interval, vtfunc_t func, void * params); + +/*---------------------------------------------------------------------------*/ +/** + * Reset the timer with the same interval. + * + * This function resets the timer with the same interval that was + * given to the libwismart_TimerSet() function. The start point of the interval + * is the exact time that the timer last expired. + * + * \param t A pointer to the timer. + * + */ +void libwismart_TimerReset(wismart_timer_t *t); + +/*---------------------------------------------------------------------------*/ +/** + * Stop a timer. + * + * This function stops a running timer + * + * \param t A pointer to the timer + * + */ +void libwismart_TimerStop(wismart_timer_t *t); + +/** \brief Reset the device. + * + * This function resets the device + * + */ +void libwismart_Reboot(void); + +/*---------------------------------------------------------------------------*/ + + + + +/** \brief Get the number of free pbufs from pool. + * + * This function returns the number of free pbufs that you + * can allocate from pool. + * + */ +uint8_t libwismart_GetMemFree_PBufPool(void); + +/* Memory statistics. All values are in bytes. */ +typedef struct{ + size_t free; /* The size of Core and Chibios free memory */ + size_t free_core; /* The size of free memery thet the chibios never use and it can be used from chibios */ + size_t free_chibios; /* The sum of all free fragments that the chibios have. Note this is not a continue buffer unless we have only one fragment. */ + size_t max_free_frag; /* The size of the bigger fragment */ + size_t min_free_frag; /* The size of the smaller fragment */ + size_t num_free_frag; /* Number of free memory fragments that the chibios have. The fragments are not continue memory chank. */ +} wismart_mem_stat_ram_t; + +/** \brief Get statistics about the main heap/ram. + * + * This function returns the statistics about the main heap/ram. + * + */ +wismart_mem_stat_ram_t libwismart_GetMemFree_Ram(void); + + + +/** @} */ + +/*---------------------------------------------------------------------------*/ +/** \defgroup WSL_WIFI Wi-Fi related functions +* +* \brief Library functions related to Wi-Fi client mode +* @{ +*/ +/** \brief callback used to inform applications about the connection result + * with a Wi-Fi Network. + * + * @param result returns WISMART_WIFI_CONNECTED or WISMART_WIFI_FAILED + */ +typedef void (*wificonnect_callback)(int result); + + +typedef void (*wifiscanresult_callback)(wismart_scan_result_t* scan_result); + + +/*---------------------------------------------------------------------------*/ +/** \addtogroup WSL_WIFI +* +* @{ +*/ +/**\brief Create a new 802.11 WiFi Ad-Hoc network + * + * This function will create a new 802.11 WiFi Ad-Hoc (IBSS) network. + * Other clients will be able to connect to this Ad-Hoc network. After the + * WiFi connection has been established, usually both ends need to have a + * static IP address. In WiSmart, you can use the API function + * libwismart_SetStaticIP(), documented later in this file. + * + * Using Ad-Hoc mode you can also configure the device by accessing the + * builtin web server. + * + * @param ibss_ssid the name of the Ad-Hoc (IBSS) network. + * @param ibss_ssid the preferred channel (1-11). + */ +void libwismart_WiFiCreateAdHoc(char *ibss_ssid, + int channel, + wificonnect_callback wificb); +/** @} */ + + +/*---------------------------------------------------------------------------*/ +/** \brief Connect to a WiFi network. + * + * This function will initiate a connection with a WiFi Network. + * It can be used for a new connection or for switching to another + * WiFi network. + * + * @param ssid (unsigned char *) The SSID (network name) of the Access Point. + * @param key (unsigned char *) PSK(raw key) or passphrase. Pass NULL for + * open networks. + * @param cb callback used to inform applications about the connection result. + * Pass NULL if you don't care about the connection result. + * + */ +int libwismart_WiFiConnect(char* ssid, + char* key, + wificonnect_callback cb); + +/*---------------------------------------------------------------------------*/ +/** \brief Connect to a WiFi network with a specific MAC Address. + * + * This function will initiate a connection with a WiFi Network. + * It can be used for a new connection or for switching to another + * WiFi network. It is different from libwismart_WiFiConnect in that it tries + * to connect to specific BSSID + * + * @param ssid (unsigned char *) The SSID (network name) of the Access Point. + * @param bssid (unsigned char *) The BSSID (mac address) of the Access Point. + * @param key (unsigned char *) PSK(raw key) or passphrase. Pass NULL for + * open networks. + * @param cb callback used to inform applications about the connection result. + * Pass NULL if you don't care about the connection result. + * + */ +int libwismart_WiFiConnectBSSID(char* ssid, + char* bssid, + char* key, + wificonnect_callback wificb); + +/*---------------------------------------------------------------------------*/ +/** \brief Connect to a WPS network with a specific SSID. + * + * This function will initiate a connection with a WiFi Network with + * Wi-Fi Protected Setup (WPS) support + * + * @param ssid (unsigned char *) The SSID (network name) of the Access Point. + * @param pin (unsigned char *) The PIN number in case WPS PIN Method has + * been selected. + * @param cb callback used to inform applications about the connection result. + * Pass NULL if you don't care about the connection result. + * + */ +int libwismart_WiFiConnectWPS(char* ssid, + char* pin, + wificonnect_callback wificb); + + +/*---------------------------------------------------------------------------*/ +/* WPA ENTERPRISE SECTION */ +/*---------------------------------------------------------------------------*/ + +/* we need to obtain certificates from somewhere, for now, assume this + is a filename */ +typedef const char *certificate_t; + +/* the same goes for the private key.. */ +typedef const char *private_key_t; + +/* EAP-TLS Parameters */ +struct tls_data { + const char *identity; /* the identity to use */ + certificate_t client_cert; /* the client certificate to use */ + private_key_t private_key; /* private key to use */ + const char *private_key_password; /* ...and its password */ + certificate_t ca_cert; /* root CA certificate */ +}; + +/* EAP-TTLS Parameters */ +struct ttls_data { + const char *identity; /* the identity to use */ + const char *password; /* password to use */ + certificate_t ca_cert; /* root CA certificate */ +}; + +/* EAP-PEAP Parameters */ +struct peap_data { + const char *identity; /* the identity to use */ + const char *password; /* password to use */ + certificate_t ca_cert; /* root CA certificate */ +}; + +/* EAP Method */ +typedef enum { + WISMART_EAP_METHOD_TTLS = 1, + WISMART_EAP_METHOD_PEAP, + WISMART_EAP_METHOD_TLS +} eap_method_t; + +/* this struct contains all the parameters needed for WPA/WPA2 Enterprise */ +struct wpa_param { + eap_method_t eap_method; /* this specifies which EAP Peer Method to use */ + union { + struct tls_data tls; /* EAP-TLS */ + struct ttls_data ttls; /* EAP-TTLS */ + struct peap_data peap; /* EAP-PEAP */ + } u; +}; + +/*---------------------------------------------------------------------------*/ +/** \brief Connect to a WPA/WPA Enterprise network with a specific SSID. + * + * This function will initiate a connection with a WPA/WPA2 Enterprise + * network (802.1x authentication). Make sure that a radius server has been + * configured and you have been provided with a username and a password. + * EAP-TTLS and EAP-PEAP methods are supported. + * + * @param ssid (unsigned char *) The SSID (network name) of the Access Point. + * @param wp (const struct wpa_param *) All the required parameters for + * WPA/WPA2 Enterprise authentication. + * @param cb callback used to inform applications about the connection result. + */ +int libwismart_WiFiConnectEnterprise(char* ssid, + const struct wpa_param *wp, + wificonnect_callback wificb); + + +/*---------------------------------------------------------------------------*/ +/** \brief Disconnect from the WiFi network + * + * This function will disconnect the device from the WiFi network that + * we are connected. + * + */ +int libwismart_WiFiDisconnect(void); + + +/*---------------------------------------------------------------------------*/ +/** \brief Set a connection timeout. + * + * Set the number of scan requests after which the device will send + * a connection timeout indication. + */ +void libwismart_SetScanRunsForConnTimeout(int scan_runs); + +/*---------------------------------------------------------------------------*/ +/** \brief Set WEP Key. + * + * This function will set the preferred WEP Key and WEP Key Index. It should + * be called after libwismart_WiFiConnect(). + * + * @param wepkey (unsigned char *) The selected WEP key. + * @param keyindex (int) The selected WEP key index (1-4) + * + */ +int libwismart_WiFiSetWep(char *wepkey, int keyindex); + + +/*---------------------------------------------------------------------------*/ +/* Packet Filtering Mechanism */ +/*---------------------------------------------------------------------------*/ +typedef enum{ + FILTERS_CMD =(1<<0), /* data cfm is included in this filter as well*/ + FILTERS_DATA =(1<<1), + FILTERS_EAPOL =(1<<2), + FILTERS_BROADCAST =(1<<3), + FILTERS_MULTICAST =(1<<4), + FILTERS_UDP =(1<<5), + FILTERS_TCP =(1<<6), + FILTERS_ICMP =(1<<7), + FILTERS_IGMP =(1<<8), + FILTERS_UNKNOWN_IP=(1<<9), + FILTERS_NOT_IP =(1<<11), /* it's not IP or ARP packet */ + FILTERS_ARP =(1<<12), +}wismart_wifi_filters_t; + +/** \brief Check a specific type of packets whether is filtered-out + * + * This function will check whether the specific type of packets is filtered-out. + * + * @param filter (wismart_wifi_filters_t) The packet type that we want to check if it's filtered-out. + * + */ +uint8_t libwismart_WiFi_Filter_Get(wismart_wifi_filters_t filter); + +/** \brief Remove filter from specific type of packet . + * + * This function will remove from filters a specific type of packets + * + * @param filter (wismart_wifi_filters_t) The packet type that we don't want to filter-out. + * + */ +void libwismart_WiFi_Filter_Clean(wismart_wifi_filters_t filter); + +/** \brief Filter-out the specific type of packets. + * + * This function will filter-out the speific type of packets + * + * @param filter (wismart_wifi_filters_t) The packet type to filter-out. + * + */ +void libwismart_WiFi_Filter_Set(wismart_wifi_filters_t filter); + + +/*---------------------------------------------------------------------------*/ +/* Roaming Mechanism */ +/*---------------------------------------------------------------------------*/ +/** + * \brief Enables Roaming Mechanism + * + * This function enables the roaming mechanism. Only if this mechanism is enabled + * the user will be informed about triggering events. + * + */ +void libwismart_EnableRoaming(void); + +/** + * \brief Disables Roaming Mechanism + * + * This function disables the roaming mechanism. After disabling this mechanism the + * user is no longer be informed about triggering events. + * + */ +void libwismart_DisableRoaming(void); + +/** + * \brief Check if Roaming is enabled + * + * @param result returns 1 if roaming is enabled or 0 if it's disabled + */ +int libwismart_isRoamingEnabled(void); + +/*! Below are the states/zones of the roaming mechanism */ +typedef enum { + ROAM_STATE_NORM, + ROAM_STATE_ALERT, + ROAM_STATE_PANIC, +} roam_state_t; + +/*! Below are the types of the roaming events */ +typedef enum { + ROAM_TYPE_ALERT = 0, + ROAM_TYPE_PANIC = 1, +} roam_type_t; + +/*! Below are the ID's of the roaming events */ +typedef enum { + ROAM_ID_RSSI = 0, + ROAM_ID_SNR = 1, + ROAM_ID_D = 2, +} roam_id_t; + +/*! Below are the ID's of the roaming events */ +typedef enum { + ROAM_TREND_ASCENDING = 0, + ROAM_TREND_DESCENDING = 1, +} roam_trend_t; + +/*! Below are the mode of roaming */ +typedef enum { + ROAM_MODE_CONTINUOUS = 0, + ROAM_MODE_ONETIME_SHOT = 1, +} roam_mode_t; + +/*---------------------------------------------------------------------------*/ +/** \brief This function set the BG scan time for specific roaming state. + * + * @param state The Roaming state tha we want to set the bg scan time. + * @param sec The BG scan time in Seconds. + * + */ +void libwismart_Roam_SetBGScanTime(roam_state_t state, uint8_t sec); + +/*---------------------------------------------------------------------------*/ +/** \brief This function Get the BG scan time for specific roaming state. + * + * @param state The Roaming state tha we want to get the bg scan time. + * + */ +uint8_t libwismart_Roam_GetBGScanTime(roam_state_t state); + +/*---------------------------------------------------------------------------*/ +/** + * \brief This function adds a roaming event trigger threshold + * + * + * \param ID Specifies if this is an RSSI, SNR or DS trigger + * \param Value Actual triggering value + * \param Type Defines whether when this threshold is reached, a scan or a roaming + * action will take place + * \param Type Specifies if a trigger is needed when the value of the specified + * parameter(rssi, snr, ds) is increased over the specified threshold or decreased + * under the specified threshold + * \param Mode Specifies whether this is a continuous or one shot trigger + */ +uint8_t libwismart_AddRoamingEventThreshold(roam_id_t ID, + uint32_t Value, + roam_type_t Type, + roam_trend_t Trend, + roam_mode_t Mode); + +/*---------------------------------------------------------------------------*/ +/** + * \brief This function removes a roaming event trigger threshold + * + * + * \param ID Specifies trigger ID that is to be removed + */ +uint8_t libwismart_RemoveRoamingEventThreshold(uint8_t ID); + +/*---------------------------------------------------------------------------*/ +/** \brief callback used to inform applications about the returned snr value + * + * @param result returns WISMART_WIFI_CONNECTED or WISMART_WIFI_FAILED + */ +typedef void (*snr_callback)(int32_t result); + +/*---------------------------------------------------------------------------*/ +/** \brief callback used to inform applications about the returned rssi value + * + * @param result returns WISMART_WIFI_CONNECTED or WISMART_WIFI_FAILED + */ +typedef void (*rssi_callback)(int32_t result); + + +/*---------------------------------------------------------------------------*/ +/** \brief Programms the aquisition of current rssi value + * + * This function will initiate the procedure of the aquisition of the current + * rssi value. The actual value will be sent to the calling application to the + * specified callback function + * + * @param rssicb callback used to inform applications about the rssi value. + * + */ +void libwismart_GetRssi(rssi_callback rssicb); + + +/** @} */ + +/*---------------------------------------------------------------------------*/ +/** \brief Performs a Scan Request + * + * This function performs a scan request + * + * @param scan_result_cb The callback that will be invoked when receiving a scan result + * @param parms Scan parameters + */ +void libwismart_ScanRequest(wifiscanresult_callback scan_result_cb, wismart_scan_parms_t* parms); + +/*---------------------------------------------------------------------------*/ +/** \brief Enable a BG scaning mechanism. + * + * This function enable the BG scan mechanism + * + * @param scan_period The period of scanning in seconds. + */ +void libwismart_Scan_Enable_BG(uint8_t scan_period); + +/*---------------------------------------------------------------------------*/ +/** \addtogroup WSL_SYSTEM +* +* @{ +*/ +/** \brief Get the Mac Address of WiSmart + * + * This function will retrieve the mac address of the device. + * It's useful for status reporting and for using it as + * something that uniquely identify this device. + * + * @param mac The mac address of WiSmart + * + */ +void libwismart_GetMac(unsigned char *mac); + + +/*---------------------------------------------------------------------------*/ +/** \brief Get the BSSID of the WiFi Access Point + * + * This function will retrieve the BSSID (usually mac address) + * of the WiFi Access Point that the device is connected. + * + * @param bssid The bssid of Access Point + * + */ +int libwismart_GetApMac(unsigned char *bssid); +/** @} */ + + +/** \addtogroup WSL_TCP_IP +* +* @{ +*/ + +/*---------------------------------------------------------------------------*/ +/** \brief callback used to inform applications about the result + * of the DHCP procedure. + * + * @param result returns WISMART_DHCP_SUCCESS or WISMART_DHCP_FAILED + */ +typedef void (*dhcp_result_callback)(int result); + +/*---------------------------------------------------------------------------*/ +/** \brief Register DHCP callback. + * + * + * @param cb callback used to inform applications about the DHCP result. + * Pass NULL if you don't care about the DHCP result. + * + */ +void libwismart_RegisterDhcpCB(dhcp_result_callback cb); + +/*---------------------------------------------------------------------------*/ +/** \brief Start DHCP Server. + * + * This function is used to start the dhcp server, used in SoftAP mode + + * @param ipaddress The server ip address + * @param netmask The server netmask + * @param gateway The server gateway + * @param dhcp_pool_size The size of pool of client IP addresses + * + */ + +void libwismart_StartDhcpServer(char* ipaddress, + char* netmask, + char* gateway, + int dhcp_pool_size); + + +/*---------------------------------------------------------------------------*/ + +typedef struct +{ + uint8_t addr[4]; +} libwismart_ip_addr_t; + +/** \brief Enable/Disable DHCP mechanism. + * + * This function will Enable/Disable DHCP mechanism. + * + * By default the DHCP mechanism is enabled. + * + * @param enable To enable the dhcp mechanism or not. + * + */ +void libwismart_DhcpEnable(uint8_t enable); + +/** \brief Set Static IP + * + * This function will set a static IP address to WiSmart + * + * Currently only setting a static IPv4 address is supported. + * + * @param ip_address The selected IP Address, e.g 192.168.1.100 + * @param netmask The selected Netmask, e.g 255.255.255.0 + * @param gateway The IP Address of the Gateway, e.g 192.168.1.1 + * + */ +void libwismart_SetStaticIP(libwismart_ip_addr_t *ip_address, libwismart_ip_addr_t *netmask, libwismart_ip_addr_t* gateway); + +/*---------------------------------------------------------------------------*/ +/** \brief Get Current IP + * + * This function gets the current IP address + * + * @param ip_address Struct containing the current IP Address,e.g 192.168.1.100 + * @param netmask Struct containing the current Netmask, e.g 255.255.255.0 + * @param gateway Struct containing the current Gateway, e.g 192.168.1.1 + * + */ +void libwismart_GetCurrentIP(libwismart_ip_addr_t *ip_address, libwismart_ip_addr_t *netmask, libwismart_ip_addr_t *gateway); + +/** @} */ + +/*---------------------------------------------------------------------------*/ +/** \addtogroup WSL_WIFI +* +* @{ +*/ + +/** \brief Returns the connection status of the device + * + * \return WISMART_NOT_CONNECTED: WiFi not connected yet + * \return WISMART_ASSOCIATED: WiFi connected, no IP connectivity yet + * \return WISMART_CONNECT: WiFi connected, IP connection completed + * + */ +int libwismart_IsConnected(void); +/** @} */ + +/*---------------------------------------------------------------------------*/ +/* Power Save Mechanism */ +/*---------------------------------------------------------------------------*/ +/** \defgroup WSL_POWER_MGMT Power Management +* +* @{ +*/ + +/*! Below are the power resources of power mgmt */ +typedef enum power_resource{ + POWER_RES_APP = 0, /*!< Resource for User applications */ + POWER_RES_DATA = 1, /*!< LwIP Data traffic(Internal library USE)*/ + POWER_RES_CMD = 2, /*!< RX WiFi CMD (Internal USE)*/ + POWER_RES_DMA = 3, /*!< Using DMA controller*/ + POWER_RES_SDIO = 4, /*!< Internal library USE*/ + POWER_RES_WIFI = 5, /*!< Internal library USE*/ +}power_resource_t; + +/*---------------------------------------------------------------------------*/ +/** \brief Enable power save of the device. + * + * This function will enable the Power Save + * scheme of the device. + * +*/ +void libwismart_PowerSave_Enable(void); + + +/*---------------------------------------------------------------------------*/ +/** \brief Disable the power save of the device. + * + * This function will disable the Power Save + * scheme of the device. + * +*/ +void libwismart_PowerSave_Disable(void); + + +/*---------------------------------------------------------------------------*/ +/** \brief Get the state of power save. + * + * This function will return the state of the Power Save. + * +*/ +uint8_t libwismart_PowerSave_isEnable(void); + +/*---------------------------------------------------------------------------*/ +/** \brief Get the state of the higher power save mode. + * + * This function will return the state + * of the higher power save mode. + * +*/ +uint8_t libwismart_PowerSave_isHigherProfile(void); + + +/*---------------------------------------------------------------------------*/ +/** \brief Request resource from the chip. + * + * This function increases the request resource counter. + * The one that requests the resource must release it as soon as + * it finishes the work that has to do. Automatically the system + * will be go to sleep if no one need the resource. + * +*/ +void libwismart_PowerSave_ReqResource(power_resource_t res); + + +/*---------------------------------------------------------------------------*/ +/** \brief Release resource from the chip. + * + * This function decreases the request resource counter. + * +*/ +void libwismart_PowerSave_RelResource(power_resource_t res); + +/*---------------------------------------------------------------------------*/ +/** \brief Reset a resource. + * + * This function reset the resource counter. + * Automatically the system will be go to sleep if no one need the resource. + * NOTE: Use this with CAUTION. +*/ +void libwismart_PowerSave_ResetResource(power_resource_t res); + +/*---------------------------------------------------------------------------*/ +/** \brief Request resource from the chip. For IRQ context. + * + * This function increases the request resource counter. + * The one that requests the resource must release it as soon as + * it finishes the work that has to do. Automatically the system + * will be go to sleep if no one need the resource. + * +*/ +void libwismart_PowerSave_ReqResourceI(power_resource_t res); + + +/*---------------------------------------------------------------------------*/ +/** \brief Release resource from the chip. For IRQ context. + * + * This function decreases the request resource counter. + * +*/ +void libwismart_PowerSave_RelResourceI(power_resource_t res); + + + +/*---------------------------------------------------------------------------*/ +/** \brief Reset a resource. + * + * This function reset the resource counter. + * Automatically the system will be go to sleep if no one need the resource. + * NOTE: Use this with CAUTION. +*/ +void libwismart_PowerSave_ResetResourceI(power_resource_t res); + +/*---------------------------------------------------------------------------*/ +/** \brief Enable or Disable the higher power save mode. + * + * This function enables or disables the higher power save profile. + * When this mode is enabled, the device can wake-up only from external irq or rtc. + * + */ +void libwismart_PowerSave_HigherProfile(uint8_t enable); + + +/*---------------------------------------------------------------------------*/ +/** \brief Shutdown the MCU. + * + * This function shutdowns the mcu and sets rtc for wake-up (reset),timeout + * is in secs. When we enable this mode, the device can wake-up(reset) only + * from external irq or rtc. If you selected source of wake-up is rtc then, + * it's not possible to set the wake-up pin as source. To select the wake-up + * pin as a source set the timeout to TIME_INFINITE. + * + */ +void libwismart_PowerSave_MCUShutdown(systime_t timeout); + +/*---------------------------------------------------------------------------*/ +/** \brief Disable the WiFi Power save. + * + * This function disable the wifi power save. + * By default the wifi power save is on. + * Note: must be called after libwismart_WiFiInit(). + * + */ +void libwismart_WiFi_PSDisable(void); + +/*---------------------------------------------------------------------------*/ +/** \brief Enable the WiFi Power save. + * + * This function Enable the wifi power save. + * By default the wifi power save is on. + * Note: must be called after libwismart_WiFiInit(). + * + */ +void libwismart_WiFi_PSEnable(void); +/** @} */ + +/** +* \defgroup WSL_DEBUG Debugging +* +* \brief Functions and structures used for debugging +* +* @{ +*/ + +typedef void (*debugport_rx_callback)(char); + +/*---------------------------------------------------------------------------*/ +/** \brief Set Callback function for received characters over debug port + * + * This function will initialize the receive path of WiSmart UART interface + * from the DEBUG port. + * + * @param uartrcv_callback This function callback will be called when we + * receive one character in debug uart. + * + */ +void libwismart_UART_InitRecv(debugport_rx_callback cb); + + +/*---------------------------------------------------------------------------*/ +/** \brief Sends a Char to the Default output Port (USART1). + * + * This function sends the provided byte to the DEBUG UART port. + * The function waits until the byte is transfered. + * + * @param data Char to be written to DEBUG UART port + * + */ +void libwismart_UART_SendChar(unsigned char data); + +/*---------------------------------------------------------------------------*/ +/** \brief Sends a Char to the Default output Port (USART1) from irq context. + * + * This function sends the provided byte to the DEBUG UART port from irq context. + * The function waits until the byte is transfered. + * + * @param data Char to be written to DEBUG UART port + * + */ +void libwismart_UART_SendCharI(char data); + +/*---------------------------------------------------------------------------*/ +/** \brief Sends a Char Buff to the Default output Port (USART1). + * + * This function sends the provided bytes to the DEBUG UART port. + * The function waits until the bytes is transfered. + * + * @param data Char to be written to DEBUG UART port + * @param len Lenength of char to be written to DEBUG UART port + * + */ +void libwismart_UART_SendBuff(unsigned char *data, uint16_t len); + +/*---------------------------------------------------------------------------*/ +/** \brief Recv a Char Buff from the Default output Port (USART1). + * + * This function recv the provided bytes from the DEBUG UART port. + * + * If we know from before the number of chars that we are going to + * recv we must use this function because is optimal for power + * consuption and performance. + * + * The function waits until the bytes is received or the user abort the DMA. + * + * @param buff Array with the buffer that we are going to write the received data. + * @param len Number of the characters that we are going to recv. + * @param timeout The timeout for the DMA receive call. The time is in ms. To disable + * the timeout set it to TIME_INFINITE. + * + * @return The number of the received bytes. + * + */ +uint16_t libwismart_UART_RecvBuff(unsigned char *buff, uint16_t len, systime_t timeout); + +/*---------------------------------------------------------------------------*/ +/** \brief Abort any DMA RX waiting in default output port (USART1). + * + * This function abort any DMA RX waiting. The @libwismart_UART_RecvBuff + * will be return the number of data that it have be recv until now. + * + */ +void libwismart_UART_RecvBuff_Abort(void); + +/*---------------------------------------------------------------------------*/ +/** \brief Abort any DMA RX waiting in default output port (USART1) from IRQ context. + * + * This function abort any DMA RX waiting. The @libwismart_UART_RecvBuff + * will be return the number of data that it have be recv until now. + * + */ +void libwismart_UART_RecvBuff_AbortI(void); + + +/** @} */ + +/*---------------------------------------------------------------------------*/ +/* Delay Functions */ +/*---------------------------------------------------------------------------*/ +/** \addtogroup WSL_SYSTEM +* +* @{ +*/ +/** \brief Perform a delay expressed in milliseconds +* The maximum possible delay is 262.14 ms / cpu_speed in MHz. +* +* @param delay Milliseconds to delay +*/ +void libwismart_Delay_ms(unsigned long delay); + +/*---------------------------------------------------------------------------*/ +/** + * \brief Get the time in ms. + * + * This function returns the time in ms. The time is measured from the start + * of the device. + * + */ +uint32_t libwismart_GetTime(void); + +/*---------------------------------------------------------------------------*/ +/** + * \brief This function returns the elpased time in ms. + * + * Calculate the elapsed time between startTimeMs and Now, taking into + * account possible timer overflow conditions. + * This function returns the elpased time in ms. + * + * NOTE: startTimeMs must be a time returned from libwismart_GetTime() for this + * function to work properly. + */ +uint32_t libwismart_ElapsedTime(uint32_t startTimeMs); + +/*---------------------------------------------------------------------------*/ +typedef enum{ + TR_ALWAYS = (~0), + TR_ALL = (~0), + TR_WIFI = (1 << 0), + TR_WPA = (1 << 1), + TR_WPA_EXTREME = (1 << 2), + TR_TRANS = (1 << 3), + TR_UART = (1 << 4), + TR_TIMER = (1 << 5), + TR_SOFTAP = (1 << 6), + TR_SOFTAP_PS = (1 << 7), + TR_PS = (1 << 8), + TR_DHCP = (1 << 9), + TR_ROAM = (1 << 10), + TR_SCAN = (1 << 11), +} trace_mask_e; + +/** + * \brief Enable debug trace bit + * + * This function enables a specific trace bit from trace_mask_e. + * + */ +void libwismart_SetTraceMask(trace_mask_e bit_field); + +/** + * \brief Clear trace bit + * + * This function clears a specific trace bit from trace_mask_e + * + */ +void libwismart_ClearTraceMask(trace_mask_e bit_field); + +/** + * \brief Get current trace mask + * + * This function return the current trace mask. + * + */ +trace_mask_e libwismart_GetTraceMask(void); + +/** + * \brief eConais implementation of snprintf + * + * This function implements the snprintf because the + * standard implementation has a bug with chibios stack. + * + */ +size_t libwismart_snprintf(char *str, size_t size, const char *fmt, ...); + +/** + * \brief eConais implementation of sprintf + * + * This function implements the sprintf because the + * standard implementation has a bug with chibios stack + * + */ +size_t libwismart_sprintf(char *str, const char *fmt, ...); + +/** @} */ + +/*---------------------------------------------------------------------------*/ + + +/** \addtogroup WSL_WIFI +* +* @{ +*/ + + +/** \brief Below are the power resources of power mgmt */ +typedef enum { + WISMART_WIFI_AP_CLIENT_CONNECTED = 0, /*!< */ + WISMART_WIFI_AP_CLIENT_DISCONNECTED = 1, /*!< */ + WISMART_WIFI_AP_CLIENT_EXPIRED = 2, /*!< To be added */ + WISMART_WIFI_AP_CLIENT_GET_IP = 3, /*!< */ +} wismart_softap_cb_t; + +/** \brief callback used to inform applications about new wifi clients. + */ +typedef void (*wismart_softap_clients_cb)(wismart_softap_cb_t reason, + const uint8_t *mac, + const libwismart_ip_addr_t *ip); + + +/** \brief Create a WiFi network (Access Point mode) + * + * This function will create a new a WiFi Network. Other WiFi clients + * will be able to connect to it. + * + * @param ssid (unsigned char *) The SSID (network name) of the Access Point. + * @param key (unsigned char *) PSK(raw key) or passphrase. Pass NULL for + * open networks. + * @param wificb callback will inform the application whether the new WiFi + * network has been created or not. + * @param clientscb callback will inform the application about the connection + * changes of clients (added/deleted etc) + */ +int libwismart_WiFi_SoftAP_Start(char *ssid, + uint8_t channel, + unsigned char* key, + wificonnect_callback wificb, + wismart_softap_clients_cb clientscb); + + +/** \brief Stop SoftAP. + * + * This function will Stop the SoftAP and it will clean all the resources + * that it's using. After that, the wifi module will be in shutdown mode. + * + */ +int libwismart_WiFi_SoftAP_Stop(void); +/** @} */ + +/*---------------------------------------------------------------------------*/ +/** +* \defgroup WSL_TCP_IP TCP/IP (LwIP) +* +* \brief Function related to TCP/IP stack which is based on LwIP open source project. +* The API is kept the same as in original LwIP project, but the code is heavily +* modified and integrated with the Wi-Fi driver. +* +* @{ +*/ + +/** \brief Lock the LwIP module for atomic access + * + * This function will lock the LwIP module for atomic access. + * + */ +void libwismart_LwIP_lock(void); + + +/*---------------------------------------------------------------------------*/ +/** \brief Unlock the LwIP module. + * + * This function will unlock the LwIP module for atomic access. + * + */ +void libwismart_LwIP_unlock(void); + +/*---------------------------------------------------------------------------*/ +/** \brief Enabled BSD Socket API + * + * This function enables the BSD-like socket API of wismart and it's the + * first function to call before using the API. Check tcp_socket.c for an + * example. + * + */ +void libwismart_EnableBsdSocketAPI(void); + + +/*---------------------------------------------------------------------------*/ +/** \brief Set a hostname for this device + * + * This function set the hostname of this device. + * NOTE: this must be called after libwismart_WiFi_Init() + * and before the wifi connection. + * + */ +void libwismart_LwIP_SetHostname(char *hostname); + +/** @} */ + +/** \addtogroup WSL_SYSTEM +* +* @{ +*/ + + +/*---------------------------------------------------------------------------*/ +/** \brief USB configuration function + */ +void libwismart_USB_Init(void); + +/** \brief USB processing function + */ +void libwismart_USB_Process(void); + +#ifdef USB_LOCK + +/** \brief USB lock function + */ +void libwismart_USB_lock(void); + +/** \brief USB unlock function + */ +void libwismart_USB_unlock(void); +#endif /* USB_LOCK */ + +#ifdef FF_LOCK + +/** \brief FF lock function + */ +void libwismart_FF_lock(void); + +/** \brief FF unlock function + */ +void libwismart_FF_unlock(void); +#endif /* FF_LOCK */ + +/** \brief Return the hwif struct that define the selected hw defines. + */ +wismart_hwif_t libwismart_GetWismartHWIF(void); + +/*---------------------------------------------------------------------------*/ +/* IRQ Handlers */ +/*---------------------------------------------------------------------------*/ + + +/*! \brief This function handles the WiFi Interrupt from FW + * + * This function Handles the WiFi Interrupt from FW. + * This function must be called from the user for the selected external wifi irq. + */ +void libwismart_WiFi_IRQHandler(void); + + +/*! \brief This function handles the UART Rx Interrupt from debug serial port. + * + * This function handles the UART Rx Interrupt from debug serial port. + * This function must be called from the user for the selected uart irq. + */ +void libwismart_UART_IRQHandler(void); + +/*! \brief This function handles the UART Rx Interrupt from debug serial port. + * + * This function handles the UART Rx Interrupt from debug serial port. + * This function must be called from the user for the selected uart irq. + */ +void libwismart_UART_TXDMA_IRQHandler(void); + +/*! \brief This function handles the UART Rx Interrupt from debug serial port. + * + * This function handles the UART Rx Interrupt from debug serial port. + * This function must be called from the user for the selected uart irq. + */ +void libwismart_UART_RXDMA_IRQHandler(void); + +/*! \brief This function handles USB-On-The-Go FS/HS global interrupt request. + * + * This function must be called from OTG_FS_IRQHandler or OTG_HS_IRQHandler irqs. + */ +void libwismart_USB_IRQHandling(void); + +/** @} */ + + +/*---------------------------------------------------------------------------*/ +/* Commander Module (UART CLI application helper functions) */ +/*---------------------------------------------------------------------------*/ + +/** \addtogroup COMMANDER_MODULE Commander Module +* +* \brief The group of functions used by the Commander application +* @{ +*/ + +typedef void (*libwismart_cmd_execute)(char *argv[], uint8_t argc); + +typedef struct{ + const char *cmd_name; + libwismart_cmd_execute func; + const char *cmd_help; +} libwismart_cmd_struct_t; + + +/*! + * \brief Init the commander module with specific cmd table + * + * This function init the commander module with specific cmd table. + * + */ +void libwismart_Commander_Init(libwismart_cmd_struct_t *cmd_table, uint8_t cmd_num ); + + +/*! + * \brief Send a char to the commander module. + * + * This function Send a char to the commander module. If the input is enter the cmd will be execute. + * + */ +void libwismart_Commander_Input(char data); + + +/*! + * \brief Send a char to the commander module from irq. + * + * This function Send a char to the commander module from irq context. If the input is enter the cmd will be execute. + * + */ +void libwismart_Commander_InputI(char data); + +/*! + * \brief Proccess the executed cmd. + * + * This function process the executed cmd. + * This function must be called inside of the main loop. + * + */ +void libwismart_Commander_Proccess(void); + +/*! + * \brief Proccess the executed cmd. + * + * This function process the executed cmd. + * This function must be called inside of the main loop. + * This function will block until a cmd arive. + * This is the best choise for power consuption. + * + */ +void libwismart_Commander_Block_Proccess(void); + +/** @} */ + +/*---------------------------------------------------------------------------*/ +/* Pbuf Queues Manager Module */ +/*---------------------------------------------------------------------------*/ + +/** \defgroup PBUF_QUEUES Pbuf Queues +* +* \brief The group of functions that supports PBUF Queues operations +* @{ +*/ + +/** +* \brief The structures below are used to store pbuf queues. +*/ +typedef struct{ + struct pbuf **queue; + uint8_t head_index; + uint8_t tail_index; + uint8_t len; + uint8_t max_len; + Semaphore sem; +} wismart_pbuf_queue_t; + +/*! + * \brief Init the pbuf queue. + * + * @param queue (data_queue_t *) The pbuf queue. + * @param max_len (uint8_t *) The max number of pbuf in queues. + * + */ +void libwismart_PBufQueue_Init(wismart_pbuf_queue_t * queue, uint8_t max_len); + +/*! + * \brief Deinit the pbuf queue. + * + * Cleans the queue and will free any pbufs that have been stored. + * + * @param queue (data_queue_t *) The pbuf queue. + * + */ +void libwismart_PBufQueue_Deinit(wismart_pbuf_queue_t * queue); + +/*! + * \brief Add a pbuf to the queue + * + * Add a pbuf to the queue if we have free space available. + * Otherwise return WISMART_FAILURE. + * This function increases the pbuf reference. Because of this, + * the user must free the pbuf after the use of this function. + * + * @param queue (data_queue_t *) The pbuf queue. + * @param p (struct pbuf *) The pbuf that we want to store. + * + * @return WISMART_SUCCESS if we add the pbuf successful. + * + */ +uint8_t libwismart_PBufQueue_Add(wismart_pbuf_queue_t * queue,struct pbuf *p); + +#define libwismart_PBufQueue_Add_Debug(q,p, _status) if(!(*_status=libwismart_PBufQueue_Add(q,p))) EC_DBG(TR_WIFI, "[%s][%d] Fail adding %x pbuf to "#q" queue\r\n", __func__, __LINE__, p) + +/*! + * \brief Get pbuf from the queue + * + * This funcion retrieves a pbuf from the queue but without remove it from the queue. + * In case that the queue is empty the function returns NULL. + * + * @param queue (data_queue_t *) The pbuf queue. + * + * @return (struct pbuf *) The pbuf. + * + */ +struct pbuf *libwismart_PBufQueue_GetLast(wismart_pbuf_queue_t * queue); + + +/*! + * \brief Remove the last pbuf from the queue + * + * This function removes the last pbuf from the queue but without freeing it. + * The user must free the pbuf when he has finished with the pbuf. + * + * @param queue (data_queue_t *) The pbuf queue. + * + * @return (struct pbuf *) The pbuf. + * + */ +struct pbuf *libwismart_PBufQueue_RemoveLast(wismart_pbuf_queue_t * queue); + +/*! + * \brief Remove and free the last pbuf from the queue + * + * This function will remove and free the last pbuf from the queue. + * + * @param queue (data_queue_t *) The pbuf queue. + * + * @return (struct pbuf *) The pbuf. + * + */ +void libwismart_PBufQueue_RemoveFreeLast(wismart_pbuf_queue_t * queue); + +/*! + * \brief Return the state of the queue. + * + * This function will return whether the queue is full or not + * + * @param queue (data_queue_t *) The pbuf queue. + * + * @return TRUE/FALSE + * + */ +uint8_t libwismart_PBufQueue_isFull(wismart_pbuf_queue_t * queue); + + +/*! + * \brief Return the state of the queue if is Empty + * + * This function will return whether the queue is empty or not + * + * @param queue (data_queue_t *) The pbuf queue. + * + * @return TRUE/FALSE + * + */ +uint8_t libwismart_PBufQueue_isEmpty(wismart_pbuf_queue_t * queue); + +/** @} */ + +/*---------------------------------------------------------------------------*/ +/* WiFi Profile Configuration Module */ +/*---------------------------------------------------------------------------*/ + +/** \defgroup WIFI_PROFILES WiFi Profiles +* +* \brief The group of functions used by the WiFi profiles module +* @{ +*/ + +/* + Values for 'profile_enabled' profile configuration option + */ +enum { + PROFILE_DISABLED, + PROFILE_ENABLED +}; + +/* + Values for 'wifi_mode' profile configuration option + */ +enum { + PROFILE_WIFI_MODE_CLIENT = 1, + PROFILE_WIFI_MODE_SOFTAP, + PROFILE_WIFI_MODE_ADHOC, + PROFILE_WIFI_MODE_WPS +}; + +/* + Values for 'security' profile configuration option + */ +enum { + PROFILE_SECURITY_OPEN = 1, + PROFILE_SECURITY_WEP40, + PROFILE_SECURITY_WEP104, + PROFILE_SECURITY_WPA_WPA2 +}; + +/* + Values for 'dhcp_mode' profile configuration option + + PROFILE_DHCP_CLIENT_MODE: Enables the dhcp client, used in WiFi client mode and WPS + PROFILE_STATIC_IP_MODE: Use a static IP configuration, used in WiFi client mode, AD-Hoc and WPS + PROFILE_DHCP_SERVER_MODE: Enables the DHCP Server, used in WiFi SoftAP Mode only + */ +enum { + PROFILE_DHCP_CLIENT_MODE = 1, + PROFILE_STATIC_IP_MODE, + PROFILE_DHCP_SERVER_MODE +}; + +/* + Values for 'wps_method' profile configuration option + */ +enum { + PROFILE_WPS_PIN_METHOD = 1, + PROFILE_WPS_PUSH_BUTTON_METHOD +}; + +/* + Values for 'fixed_rate' profile configuration option + */ +enum { + PROFILE_AUTO_RATE = 0, /* Auto rate */ + PROFILE_RATE_2MBPS = 0x84, /* 2 Mbps */ + PROFILE_RATE_5_5_MBPS = 0x8b, /* 5.5 Mbps */ + PROFILE_RATE_11_MBPS = 0x96, /* 11 Mbps */ + PROFILE_RATE_9_MBPS = 0x12, /* 9 Mbps */ + PROFILE_RATE_18_MBPS = 0x24, /* 18 Mbps */ + PROFILE_RATE_36_MBPS = 0x48, /* 36 Mbps */ + PROFILE_RATE_54_MBPS = 0x6c /* 54 Mbps */ +}; + +/*! + * \brief Store a buffer in the profile + * + * This function will store a buffer in the configuration profile + * + */ +int libwismart_ProfileSet_Buf(char* config_var, char* value); + +/*! + * \brief Store a string value in the profile + * + * This function will store a string value in the configuration profile + * + */ +int libwismart_ProfileSet_Str(char* config_var, char* value); + +/*! + * \brief Store an integer value in the profile + * + * This function will store an integer value in the configuration profile + * + */ +int libwismart_ProfileSet_Int(char* config_var, uint16_t value); + +/*! + * \brief Get a string value from the profile + * + * This function will get a string value from the configuration profile + * + */ +int libwismart_ProfileGet_Str(char* config_var, char* out_value); + +/*! + * \brief Get an integer value in the profile + * + * This function will get an integer value in the configuration profile + * + */ +int libwismart_ProfileGet_Int(char* config_var, uint16_t* out_value); + +/*! + * \brief Read a buffer from a profile + * + * This function will gread a buffer from a configuration profile + * + */ +int libwismart_ProfileGet_Buf(char* config_var, char* out_value); +/** @} */ + +/*---------------------------------------------------------------------------*/ +/* User Registry Module */ +/*---------------------------------------------------------------------------*/ + +/** \defgroup Registry Registry +* + * \brief The group of functions used by the Registry module +* @{ +*/ + +typedef struct { + uint16_t size; + uint16_t address; + uint16_t registryFile; +} wismart_registryKey_t; + +/*! + * \brief Create a registry key for a generic data type of size 'key_size'. + * + * This function will return a registry key for a specific data type that + * needs to be stored in registry. E.g if you have one struct and one + * array, this function should be called 2 times, one for each data type. + * + * Note that this function must be called before libwismart_RegistryOpen(). + * + * @param key (wismart_registryKey_t *) The returned registry key. + * @param registryFile The registry file with which this key is related. + * @param key_size The size of the registry key. + * + * @return WISMART_SUCCESS on success + * @return WISMART_FAILURE if the data type does not fit in memory + */ +int libwismart_RegistryCreateKey(wismart_registryKey_t *key, uint16_t registryFile, uint32_t key_size); + +/*! + * \brief Opens a registry file + * + * This function must be called only after all registry values have been + * registered with libwismart_RegistryCreateKey(). + * + * After calling this function the rest API is unlocked, and user can call + * libwismart_RegistryGet(),libwismart_RegistrySet() and + * libwismart_RegistryIsValueEmpty(). + * + * @param registryFile The registry file which is going to be opened. + * + * @return WISMART_SUCCESS on success + * @return WISMART_FAILURE if the registry file fails to open + */ +int libwismart_RegistryOpen(uint16_t registryFile); + +/*! + * \brief Sets the value of a registry item. + * + * This function will set the value of the selected registry + * item using the registry key that has been created with + * libwismart_RegistryCreateKey() + * + * @param key (wismart_registryKey_t *) The registry key. + * @param pdata_in (void *) The address of data type containing + * the data to save + * + * @return WISMART_SUCCESS on success + * @return WISMART_FAILURE on write error + */ +int libwismart_RegistrySet(wismart_registryKey_t *key, void *pdata_in); + +/*! + * \brief Gets the value of a registry item. + * + * This function will get the value of the selected registry + * item using the registry key that has been created with + * libwismart_RegistryCreateKey() + * + * @param key (wismart_registryKey_t *) The registry key. + * @param pdata_out (void *) Buffer containing the retrieved data + * + * @return WISMART_SUCCESS on success + * @return WISMART_FAILURE on write error + */ +int libwismart_RegistryGet(wismart_registryKey_t *key, void *pdata_out); + + +/*! + * \brief Checks if a registry item has a value. + * + * This is true only if libwismart_RegistrySet() has been called at + * least once. + * + * @param key (wismart_registryKey_t *) The registry key. + * + * @retval 0 : if the registry item has a value + * @retval 1 : if the registry item has not a value + */ +int libwismart_RegistryIsValueEmpty(wismart_registryKey_t* key); + +/*! + * \brief This function formats the registry. All settings will be lost. + * + * @param registryFile The registry file which is going to be formatted. + * + * @retval WISMART_FAILURE if there was an error while formating + * the registry file + * @retval WISMART_SUCCESS if the registry file was formated succesfully + */ +int libwismart_RegistryFormat(uint16_t registryFile); + +/** @} */ +/*---------------------------------------------------------------------------*/ +/* TCP Statistics */ +/*---------------------------------------------------------------------------*/ + +typedef struct { + uint16_t xmit; + uint16_t drop; + uint16_t chkerr; + uint16_t err; + uint16_t rterr; +} wismart_tcp_stats_t; + +/*! + * \brief Clears the TCP Statistics + * + * This function clears the TCP statistics + * + */ +void libwismart_ClearTcpStats(void); + +/*! + * \brief Prints the TCP Statistics + * + * This function prints TCP statistics + * + */ +void libwismart_PrintTcpStats(void); + +/*! + * \brief Retrieve TCP Statistics + * + * This function can be used to retrieve TCP statistics + * + * @param stats Structure containing the statistics + */ +void libwismart_GetTcpStats(wismart_tcp_stats_t* stats); + +/** @} */ +/*---------------------------------------------------------------------------*/ +/* Console Commands */ +/*---------------------------------------------------------------------------*/ +/*! + * \brief Send a Console Cmd + * + * This function Sends a console command to wifi fw + * + * @param command Buffer containing the command itself + * @param command_len size of buffer + */ +void libwismart_SendConsoleRequest(unsigned char* command, uint16_t command_len); + +/*---------------------------------------------------------------------------*/ +/* DLNA API */ +/*---------------------------------------------------------------------------*/ +/** \defgroup DLNA DLNA API +* +* \brief The group of functions to initialize library, Wi-Fi, TPC/IP and +* shutdown the Wi-Fi +* @{ +*/ + +/** + @brief Definiton for the setVolumeCb_t. + @param volumeValue The value to which the volume must be set to. Values + range from 0 to 100. + */ +typedef void (*setVolumeCb_t)(uint32_t volumeValue); + +/** + @brief Definiton for the getVolumeCb_t. + @retval The current value of the volume. Values range from 0 to 100. + */ +typedef uint32_t (*getVolumeCb_t)(void); + +/** + @brief Definiton for the setMuteCb_t. + @param muteValue The current status of the mute. Can be LW_DLNA_MUTE_ON or LW_DLNA_MUTE_OFF + */ +typedef void (*setMuteCb_t)(uint32_t muteValue); + +/** + @brief Definiton for the getMuteCb_t. + @retval The current status of the mute. Can be LW_DLNA_MUTE_ON or LW_DLNA_MUTE_OFF + */ +typedef uint32_t (*getMuteCb_t)(void); + +/** + @brief Definiton for the setUriCb_t. + @param uri The uri of the audio file + @param ip The IP of the server in which the resource is located + @param port The port of the server that user must connect to in order to retrieve the audio file + */ +typedef void (*setUriCb_t)(uint8_t* uri); + +/** + @brief Definiton for the playCb_t. + @note User application should start playing the audio file from the current URI when this callback + is called. Normally, the control device sends a STOP soap action, then a SET_URI soap action + and finally a PLAY soap action. Some control devices send only the SET_URI and STOP actions. + This means that when receiving a PLAY soap action, user application must stop the playback + of the current audio file, and start playing the new file received from the SET_URI action. + */ +typedef void (*playCb_t)(void); + +/** + @brief Definiton for the pauseCb_t. + */ +typedef void (*pauseCb_t)(void); + +/** + @brief Definiton for the stopCb_t. + */ +typedef void (*stopCb_t)(void); + +/** + @brief Definiton for the seekCb_t. + @param bytePos The byte number from which the playback must be continued. + */ +typedef void (*seekCb_t)(uint32_t bytePos); + +/** + @brief Definition for DLNA_MUTE_ON + */ +#define DLNA_MUTE_ON (1) + +/** + @brief Definition for DLNA_MUTE_OFF + */ +#define DLNA_MUTE_OFF (0) + + +/** + @brief Initializes the DLNA stack. This includes all DLNA servers, connections + and the related memory modules. Must be called when wismart's wifi is connected. + @param dmrFriendlyName Registers the name with which the wismart DMR(speaker) will be listed when + control devices scan for media renderers. + @param dmsFriendlyName Registers the name with which the wismart DMS(server) will be listed when + control devices scan for media server. Pass NULL if DMS functionality is not needed. + @param manufacturer The name of the manufacturer. This name will be sent when control devices + ask for the device descriptor. + @param manufacturerUrl the URL of the manufacturer + @param udn The unique identifier of the device. It is not permitted two dlna devices to share the same + UDN. + \nUUIDs are 128 bit numbers that MUST be formatted as specified by the following grammar: + + \nUUID = 4 * - 2 * - 2 * - 2 * - 6 * + \nhexOctet = hexDigit = 0|1|2|3|4|5|6|7|8|9|a|b|c|d|e|f|A|B|C|D|E|F + + \nThe following is an example of the string representation of a UUID: + \n2fac1234-31f8-11b4-a222-08002b34c003 + @retval 0 on success + @retval negative on error +*/ +uint32_t libwismart_dlna_init(uint8_t * dmrFriendlyName, uint8_t * dmsFriendlyName, uint8_t* manufacturer, uint8_t* manufacturerUrl, uint8_t* udn); + +uint32_t libwismart_dlna_connect(void); + + +/** + @brief After calling this function the device will restart in softAp mode + with SSID "WisAudio" and open encryption. User can connect to this + network from his device, and by typing 192.168.1.1:50000 in device's + web browser the configuration web page will show up. + */ +void dlnaEnterConfigurationMode(void); + + +/** + @brief Enables DLNA's debug messages + */ +void libwismart_dlna_debugEnable(void); + +/** + @brief Disables DLNA's debug messages + */ +void libwismart_dlna_debugDisable(void); + + +/** + @brief Informs the DLNA stack that the playback of the current audio file finished. This function + must be called when the user application retrieved and played the whole file. The + DLNA stack will then inform all subscribers that the current state of the audio/video + transport is STOPPED, so they can update their GUIs (Stop their playback progress bar for example). + */ +void libwismart_dlna_playbackFinished(void); + +/** + @brief Informs the DLNA stack for the current byte position of the + playback. With this function the DLNA stack updates the corresponding + state variables, and all control points know the exact position of the playback, so + they can update their seek bars. + @param currentByte The current byte number that is be played. + @param totalBytes The total size of the audio file. This is received from the HTTP response. + */ +void libwismart_dlna_updatePositionInfo(uint32_t currentByte, uint32_t totalBytes); + + +/** + @brief Callback function tha DLNA stack uses to inform the user application + that the volume must be set in a spesific level. + */ +void libwismart_dlna_setVolumeCb(setVolumeCb_t funcPtr); + +/** + @brief Callback function tha DLNA stack uses in order to get from the the user application + the current volume level. + */ +void libwismart_dlna_getVolumeCb(getVolumeCb_t funcPtr); + +/** + @brief Callback function tha DLNA stack uses in order to inform the user application + that the volume must muted + */ +void libwismart_dlna_setMuteCb(setMuteCb_t funcPtr); + +/** + @brief Callback function tha DLNA stack uses in order to get from the the user application + the current mute state. + */ +void libwismart_dlna_getMuteCb(getMuteCb_t funcPtr); + +/** + @brief Callback function tha DLNA stack uses in order to inform the user application + that it must start playing the the audio file from the current URI. + */ +void libwismart_dlna_playCb(playCb_t funcPtr); + +/** + @brief Callback function tha DLNA stack uses in order to inform the user application + that the playback must be paused. + */ +void libwismart_dlna_pauseCb(pauseCb_t funcPtr); + +/** + @brief Callback function tha DLNA stack uses in order to inform the user application + that the volume must be stopped. + */ +void libwismart_dlna_stopCb(stopCb_t funcPtr); + +/** + @brief Callback function tha DLNA stack uses in order to inform the user application + that the playback must be continued from a certain point + */ +void libwismart_dlna_seekCb(seekCb_t funcPtr); + +/** + @brief Callback function tha DLNA stack uses in order to inform the user application + that a the current URI was updated. + */ +void libwismart_dlna_setUriCb(setUriCb_t funcPtr); + +/** + @brief Opens a file from DMS. + + @param fileUri The url of the file to be opened + @param seekPos The initial byte position from which the read will start + @param fileSize Stores the size of the opened file in bytes + + @retval 0 on success + @retval positive on error + */ +uint32_t libwismart_dlna_dmsFile_open(uint8_t* fileUri, uint32_t seekPos, uint32_t* fileSize ); + + +/** + @brief Closes the file opened with libwismart_dlna_dmsFile_open() + + @retval 0 on success + @retval positive on error + */ +uint32_t libwismart_dlna_dmsFile_close(void); + + +/** + @brief Reads data from DMS. + + @param dataBuffer The buffer in which the read data will be stored + @param bytesRequested The size of 'dataBuffer' in bytes + @param bytesReturned How many bytes where actually read + + @retval 0 on success + @retval positive on error + */ +uint32_t libwismart_dlna_dmsFile_read(uint8_t* dataBuffer, uint32_t bytesRequested, uint32_t* bytesReturned); + + +/** + @brief Locks the sychronization object for dms open/read/close operations + */ +void libwismart_dlna_dmsFile_lock(void); + + +/** + @brief Unlocks the sychronization object for dms open/read/close operations + */ +void libwismart_dlna_dmsFile_unlock(void); + + +/** @} */ + + + +/*---------------------------------------------------------------------------*/ +/* HTTP SERVER API */ +/*---------------------------------------------------------------------------*/ +/** \defgroup HTTP_SERVER_API HTTP Server API +* +* \brief The group of functions to initialize and use the internal HTTP server +* @{ +*/ + +/** + @brief Memory allocation types for buffers passed into the HTTP server + */ +enum WISMART_SERVER_ALLOC_T{ + WISMART_SERVER_ALLOC_STATIC = 0, ///< Inform server that the specific buffer is static, and no de-allocation should be made + WISMART_SERVER_ALLOC_DYNAMIC, ///< Inform server that the specific buffer is dynamic, and the server should call the wismart_server_free_cb_t function in order to free the memory +}; + +/** + @brief HTTP server's callback return values + */ +enum WISMART_SERVER_ERR_T{ + WISMART_SERVER_ERR_OK = 0, + WISMART_SERVER_ERR_MEM, + WISMART_SERVER_ERR_NOT_READY, + WISMART_SERVER_ERR_FATAL, + WISMART_SERVER_ERR_NOT_FOUND, + WISMART_SERVER_ERR_STRING_NOT_FOUND = 0xffffff00, + WISMART_SERVER_ERR_OTHER +}; + +/** + @brief This struct is used to describe the HTTP resources + that are to be handled by the HTTP Server + */ +typedef struct { + /** + @brief The name of the resource + */ + char* name; + /** + @brief Specifies if the resource has dynamic content + */ + uint8_t hasDynamicContent; + /** + @brief Specifies any function that should be called when the resource is requested + */ + void (*scriptCb)(void); + /** + @brief Pointer to resource's data + */ + uint8_t* dataPtr; + /** + @brief The file size of the resource + */ + uint32_t dataSize; + /** + @brief The mime type of the resource + */ + char* mimeType; + /** + @brief Specifies if the browser is allowed to cache the resource locally + in order the page to be loaded faster + */ + uint8_t canBeCached; +}wismart_server_resource_t; + +/** + @brief Type definition of the callback function to be called when the dynamic + content should be processed + */ +typedef uint32_t (*wismart_server_dynamic_cb_t)(char* varName, char** varValue, uint8_t* varAllocType); + +/** + @brief Type definition of the callback function to be called when dynamically allocated memory should be freed + */ +typedef void (*wismart_server_free_cb_t)(void*); + +/** + @brief This function allocates memory for the HTTP server and starts the server thread. + + @param serverPort Server's listening port (Usually 80) + @param serverName Desired server's name, used in HTTP responses + @param dynamicCb callback function to be called when the dynamic content should be processed + @param freeCb callback function to be called when dynamically allocated memory should be freed + @param resources An array of the HTTP resources to be handled by the server. The last resource should + have the 'name' field point to NULL in order the server to know the number of the resources. + */ +uint32_t libwismart_server_start(uint16_t serverPort, char* serverName, wismart_server_dynamic_cb_t dynamicCb, wismart_server_free_cb_t freeCb, wismart_server_resource_t* resources); +uint32_t libwismart_server_connect(void); +uint32_t libwismart_server_GET(char* variableName, char* variableValue, uint32_t maxVariableValueLen); +uint32_t libwismart_server_POST(char* variableName, char* variableValue, uint32_t maxVariableValueLen); + + +/** @} */ + + + + +/*---------------------------------------------------------------------------*/ +/* Link List Util */ +/*---------------------------------------------------------------------------*/ +/** \defgroup STM32_PERIPHERALS MCU Peripheral locks +* +* \brief The group of functions that make thread safe some peripheral resources. +* @{ +*/ + +void libwismart_peripheral_lock(uint8_t wimsartPeripheral); +void libwismart_peripheral_unlock(uint8_t wimsartPeripheral); + +/** @} */ + +/*---------------------------------------------------------------------------*/ +/* Link List Util */ +/*---------------------------------------------------------------------------*/ +/** \defgroup STM32_PERIPHERALS Over The Air (OTA) Upgrade +* +* \brief The group of functions that make possible to upgrade firmware over the air +* @{ +*/ +uint8_t libwismart_set_ota_ftp_parameters(char* wifi_ssid, char* wifi_passphrase, char* ftp_server_ip, uint16_t ftp_server_port, char* ftp_username, char* ftp_password, char* ftp_filename, uint8_t keepApplicationRegistrySettings); +/** @} */ + +/*---------------------------------------------------------------------------*/ +/* Link List Util */ +/*---------------------------------------------------------------------------*/ +/** \defgroup LINK_LIST Linked Lists API +* +* \brief The group of functions to initialize and use of thread save of link list API. +* @{ +*/ + +typedef struct wismart_link_list_node{ + struct wismart_link_list_node *next; + void *data; +} wismart_link_list_node_t; + +typedef struct wismart_link_list{ + wismart_link_list_node_t *root; + Semaphore sem; + uint16_t len; +} wismart_link_list_t; + +wismart_link_list_t* libwismart_LinkList_Init(void); + +uint8_t libwismart_LinkList_AddLast(wismart_link_list_t *list,void *data); + +uint8_t libwismart_LinkList_AddFirst(wismart_link_list_t *list,void *data); + +uint8_t libwismart_LinkList_AddAfter(wismart_link_list_t *list,void *preData,void *data); + +uint8_t libwismart_LinkList_Exist(wismart_link_list_t *list,void *data); + +uint8_t libwismart_LinkList_Remove(wismart_link_list_t *list,void *data); + +void *libwismart_LinkList_RemoveFirst(wismart_link_list_t *list); + +void *libwismart_LinkList_RemoveLast(wismart_link_list_t *list); + +void *libwismart_LinkList_GetLast(wismart_link_list_t *list); + +void *libwismart_LinkList_GetFirst(wismart_link_list_t *list); + +void *libwismart_LinkList_GetFirstNode(wismart_link_list_t *list); + + +uint8_t libwismart_LinkList_FilterExec(wismart_link_list_t *list, + uint8_t (*selection)(void *data), + void (*func)(void *data)); + +void +libwismart_LinkList_Exec(wismart_link_list_t *list, + void *priv_data, + void (*func)(void *priv_data, void *data)); + +void * +libwismart_LinkList_Find(wismart_link_list_t *list, + void *priv_data, + uint8_t (*func)(void *priv_data, void *data)); + +void * +libwismart_LinkList_FindAndRemove(wismart_link_list_t *list, + void *priv_data, + uint8_t (*func)(void *priv_data, void *data)); + +uint16_t +libwismart_LinkList_Count(wismart_link_list_t *list); + +/** @} */ + +/** + @brief WiSmart Recover Mechanism +*/ +int libwismart_WiFiReInit(void); + + +#endif /* LIBWISMART_H_ */ + + +/** @} */ diff --git a/Project/econais/libwismart_mcu.h b/Project/econais/libwismart_mcu.h new file mode 100644 index 0000000..a281f6d --- /dev/null +++ b/Project/econais/libwismart_mcu.h @@ -0,0 +1,224 @@ + +/** +* \defgroup libwismart WiSmart MCU specific library +* +* The libwismart library provides definitions for the MCU. +* +* @{ +*/ + + +/** + * \file + * WiSmart library header file. + * \author + * eConais RnD Group + */ + +/* + * This software is copyrighted by and is the sole property of eConais. + * All rights, title, ownership, or other interests in the software remain + * the property of eConais. This software may only be used in accordance + * with the corresponding license agreement. Any unauthorized use, + * duplication, transmission, distribution, or disclosure of this software + * is expressly forbidden. + * + * This copyright notice may not be removed or modified without prior written + * consent of eConais. + * + * eConais reserves the right to modify this software without + * notice. + * + * eConais + * Patras Science Park support@econais.com + * 26504 Platani, Patras http://www.econais.com + * GREECE + + * + * This file is part of WiSmart SDK + * + * Author: eConais RnD Group + * + */ + +#ifndef LIBWISMART_MCU_H_ +#define LIBWISMART_MCU_H_ + +/*===========================================================================*/ +/* STM32F4 */ +/*===========================================================================*/ + +#ifdef STM32F4 + +/*===========================================================================*/ +/* Platform specific friendly IRQ names. */ +/*===========================================================================*/ + +#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ +#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line detect.*/ +#define TAMP_STAMP_IRQHandler Vector48 /**< Tamper and TimeStamp through EXTI Line.*/ +#define RTC_WKUP_IRQHandler Vector4C /**< RTC wakeup EXTI Line. */ +#define FLASH_IRQHandler Vector50 /**< Flash. */ +#define RCC_IRQHandler Vector54 /**< RCC. */ +#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ +#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ +#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ +#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ +#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ +#define DMA1_Stream0_IRQHandler Vector6C /**< DMA1 Stream 0. */ +#define DMA1_Stream1_IRQHandler Vector70 /**< DMA1 Stream 1. */ +#define DMA1_Stream2_IRQHandler Vector74 /**< DMA1 Stream 2. */ +#define DMA1_Stream3_IRQHandler Vector78 /**< DMA1 Stream 3. */ +#define DMA1_Stream4_IRQHandler Vector7C /**< DMA1 Stream 4. */ +#define DMA1_Stream5_IRQHandler Vector80 /**< DMA1 Stream 5. */ +#define DMA1_Stream6_IRQHandler Vector84 /**< DMA1 Stream 6. */ +#define ADC1_2_3_IRQHandler Vector88 /**< ADC1, ADC2 and ADC3. */ +#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */ +#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */ +#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ +#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ +#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ +#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ +#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ +#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and Commutation.*/ +#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ +#define TIM2_IRQHandler VectorB0 /**< TIM2. */ +#define TIM3_IRQHandler VectorB4 /**< TIM3. */ +#define TIM4_IRQHandler VectorB8 /**< TIM4. */ +#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ +#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ +#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ +#define I2C2_ER_IRQHandler VectorC8 /**< I2C1 Error. */ +#define SPI1_IRQHandler VectorCC /**< SPI1. */ +#define SPI2_IRQHandler VectorD0 /**< SPI2. */ +#define USART1_IRQHandler VectorD4 /**< USART1. */ +#define USART2_IRQHandler VectorD8 /**< USART2. */ +#define USART3_IRQHandler VectorDC /**< USART3. */ +#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ +#define RTC_Alarm_IRQHandler VectorE4 /**< RTC alarms (A and B) through EXTI line.*/ +#define OTG_FS_WKUP_IRQHandler VectorE8 /**< USB OTG FS Wakeup through EXTI line.*/ +#define TIM8_BRK_IRQHandler VectorEC /**< TIM8 Break. */ +#define TIM8_UP_IRQHandler VectorF0 /**< TIM8 Update. */ +#define TIM8_TRG_COM_IRQHandler VectorF4 /**< TIM8 Trigger and Commutation.*/ +#define TIM8_CC_IRQHandler VectorF8 /**< TIM8 Capture Compare. */ +#define DMA1_Stream7_IRQHandler VectorFC /**< DMA1 Stream 7. */ +#define FSMC_IRQHandler Vector100 /**< FSMC. */ +#define SDIO_IRQHandler Vector104 /**< SDIO. */ +#define TIM5_IRQHandler Vector108 /**< TIM5. */ +#define SPI3_IRQHandler Vector10C /**< SPI3. */ +#define UART4_IRQHandler Vector110 /**< UART4. */ +#define UART5_IRQHandler Vector114 /**< UART5. */ +#define TIM6_IRQHandler Vector118 /**< TIM6. */ +#define TIM7_IRQHandler Vector11C /**< TIM7. */ +#define DMA2_Stream0_IRQHandler Vector120 /**< DMA2 Stream0. */ +#define DMA2_Stream1_IRQHandler Vector124 /**< DMA2 Stream1. */ +#define DMA2_Stream2_IRQHandler Vector128 /**< DMA2 Stream2. */ +#define DMA2_Stream3_IRQHandler Vector12C /**< DMA2 Stream3. */ +#define DMA2_Stream4_IRQHandler Vector130 /**< DMA2 Stream4. */ +#define ETH_IRQHandler Vector134 /**< Ethernet. */ +#define ETH_WKUP_IRQHandler Vector138 /**< Ethernet Wakeup through EXTI line. */ +#define CAN2_TX_IRQHandler Vector13C /**< CAN2 TX. */ +#define CAN2_RX0_IRQHandler Vector140 /**< CAN2 RX0. */ +#define CAN2_RX1_IRQHandler Vector144 /**< CAN2 RX1. */ +#define CAN2_SCE_IRQHandler Vector148 /**< CAN2 SCE. */ +#define OTG_FS_IRQHandler Vector14C /**< USB OTG FS. */ +#define DMA2_Stream5_IRQHandler Vector150 /**< DMA2 Stream5. */ +#define DMA2_Stream6_IRQHandler Vector154 /**< DMA2 Stream6. */ +#define DMA2_Stream7_IRQHandler Vector158 /**< DMA2 Stream7. */ +#define USART6_IRQHandler Vector15C /**< USART6. */ +#define I2C3_EV_IRQHandler Vector160 /**< I2C3 Event. */ +#define I2C3_ER_IRQHandler Vector164 /**< I2C3 Error. */ +#define OTG_HS_EP1_OUT_IRQHandler Vector168 /**< USB OTG HS End Point 1 Out.*/ +#define OTG_HS_EP1_IN_IRQHandler Vector16C /**< USB OTG HS End Point 1 In. */ +#define OTG_HS_WKUP_IRQHandler Vector170 /**< USB OTG HS Wakeup through EXTI line.*/ +#define OTG_HS_IRQHandler Vector174 /**< USB OTG HS. */ +#define DCMI_IRQHandler Vector178 /**< DCMI. */ +#define CRYP_IRQHandler Vector17C /**< CRYP. */ +#define HASH_RNG_IRQHandler Vector180 /**< Hash and Rng. */ + +#endif /* STM32F4 */ + + + +/*===========================================================================*/ +/* STM32F1 */ +/*===========================================================================*/ + +#ifdef STM32F1 + +/*===========================================================================*/ +/* Platform specific friendly IRQ names. */ +/*===========================================================================*/ + +#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ +#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line detect.*/ +#define TAMPER_IRQHandler Vector48 /**< Tamper. */ +#define RTC_IRQHandler Vector4C /**< RTC. */ +#define FLASH_IRQHandler Vector50 /**< Flash. */ +#define RCC_IRQHandler Vector54 /**< RCC. */ +#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ +#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ +#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ +#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ +#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ +#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ +#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ +#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ +#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ +#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ +#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ +#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ +#define ADC1_2_IRQHandler Vector88 /**< ADC1_2. */ +#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */ +#define USB_HP_IRQHandler Vector8C /**< USB High Priority, CAN1 TX.*/ +#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */ +#define USB_LP_IRQHandler Vector90 /**< USB Low Priority, CAN1 RX0.*/ +#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ +#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ +#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ +#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ +#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ +#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and Commutation.*/ +#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ +#define TIM2_IRQHandler VectorB0 /**< TIM2. */ +#define TIM3_IRQHandler VectorB4 /**< TIM3. */ +#define TIM4_IRQHandler VectorB8 /**< TIM4. */ +#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ +#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ +#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ +#define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */ +#define SPI1_IRQHandler VectorCC /**< SPI1. */ +#define SPI2_IRQHandler VectorD0 /**< SPI2. */ +#define USART1_IRQHandler VectorD4 /**< USART1. */ +#define USART2_IRQHandler VectorD8 /**< USART2. */ +#define USART3_IRQHandler VectorDC /**< USART3. */ +#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ +#define RTC_Alarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ +#define USB_FS_WKUP_IRQHandler VectorE8 /**< USB Wakeup from suspend. */ +#define TIM8_BRK_IRQHandler VectorEC /**< TIM8 Break. */ +#define TIM8_UP_IRQHandler VectorF0 /**< TIM8 Update. */ +#define TIM8_TRG_COM_IRQHandler VectorF4 /**< TIM8 Trigger and Commutation.*/ +#define TIM8_CC_IRQHandler VectorF8 /**< TIM8 Capture Compare. */ +#define ADC3_IRQHandler VectorFC /**< ADC3. */ +#define FSMC_IRQHandler Vector100 /**< FSMC. */ +#define SDIO_IRQHandler Vector104 /**< SDIO. */ +#define TIM5_IRQHandler Vector108 /**< TIM5. */ +#define SPI3_IRQHandler Vector10C /**< SPI3. */ +#define UART4_IRQHandler Vector110 /**< UART4. */ +#define UART5_IRQHandler Vector114 /**< UART5. */ +#define TIM6_IRQHandler Vector118 /**< TIM6. */ +#define TIM7_IRQHandler Vector11C /**< TIM7. */ +#define DMA2_Ch1_IRQHandler Vector120 /**< DMA2 Channel1. */ +#define DMA2_Ch2_IRQHandler Vector124 /**< DMA2 Channel2. */ +#define DMA2_Ch3_IRQHandler Vector128 /**< DMA2 Channel3. */ +#define DMA2_Ch4_5_IRQHandler Vector12C /**< DMA2 Channel4 & Channel5. */ + +#endif /* STM32F1 */ + + + + + + + +#endif /* LIBWISMART_MCU_H_ */ diff --git a/Project/externalModules/lwip_v141/lwip_include.mk b/Project/externalModules/lwip_v141/lwip_include.mk new file mode 100644 index 0000000..7c0fb3e --- /dev/null +++ b/Project/externalModules/lwip_v141/lwip_include.mk @@ -0,0 +1,6 @@ +LWIP_FOLDER = $(CHIBIOS)/externalModules/lwip_v141 + +LWIP_INC = $(LWIP_FOLDER)/src/include \ + $(LWIP_FOLDER)/src/include/ipv4 \ + $(LWIP_FOLDER)/port \ + $(LWIP_FOLDER)/port/arch diff --git a/Project/externalModules/lwip_v141/port/arch/cc.h b/Project/externalModules/lwip_v141/port/arch/cc.h new file mode 100644 index 0000000..b5b3b34 --- /dev/null +++ b/Project/externalModules/lwip_v141/port/arch/cc.h @@ -0,0 +1,96 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ +/* + * **** This file incorporates work covered by the following copyright and **** + * **** permission notice: **** + * + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __CC_H__ +#define __CC_H__ + +#include "libwismart.h" +#include + +typedef uint8_t u8_t; +typedef int8_t s8_t; +typedef uint16_t u16_t; +typedef int16_t s16_t; +typedef uint32_t u32_t; +typedef int32_t s32_t; +typedef uint32_t mem_ptr_t; + +#define LWIP_PLATFORM_DIAG(x) print("%s\r\n",x); +#define LWIP_PLATFORM_ASSERT(x) { \ + print("assert!!%s\r\n",x);chSysHalt(); \ +} + +#define BYTE_ORDER LITTLE_ENDIAN +#define LWIP_PROVIDE_ERRNO + +#define PACK_STRUCT_BEGIN +#ifdef PACK_STRUCT_STRUCT +#undef PACK_STRUCT_STRUCT +#endif + + +#define PACK_STRUCT_STRUCT __attribute__ ((__packed__)) + +#define PACK_STRUCT_END +#define PACK_STRUCT_FIELD(x) x + +#define LWIP_RAND() ((u32_t)rand()) +#endif /* __CC_H__ */ diff --git a/Project/externalModules/lwip_v141/port/arch/perf.h b/Project/externalModules/lwip_v141/port/arch/perf.h new file mode 100644 index 0000000..244dffc --- /dev/null +++ b/Project/externalModules/lwip_v141/port/arch/perf.h @@ -0,0 +1,68 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ +/* + * **** This file incorporates work covered by the following copyright and **** + * **** permission notice: **** + * + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __PERF_H__ +#define __PERF_H__ + +#define PERF_START +#define PERF_STOP(x) + +#endif /* __PERF_H__ */ diff --git a/Project/externalModules/lwip_v141/port/arch/sys_arch.h b/Project/externalModules/lwip_v141/port/arch/sys_arch.h new file mode 100644 index 0000000..4135ea1 --- /dev/null +++ b/Project/externalModules/lwip_v141/port/arch/sys_arch.h @@ -0,0 +1,80 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ +/* + * **** This file incorporates work covered by the following copyright and **** + * **** permission notice: **** + * + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include + +#ifndef __SYS_ARCH_H__ +#define __SYS_ARCH_H__ +#if !NO_SYS +typedef Semaphore * sys_sem_t; +typedef Mailbox * sys_mbox_t; +typedef Thread * sys_thread_t; +typedef int sys_prot_t; +#endif + +#define SYS_MBOX_NULL (Mailbox *)0 +#define SYS_THREAD_NULL (Thread *)0 +#define SYS_SEM_NULL (Semaphore *)0 + +/* let sys.h use binary semaphores for mutexes */ +#define LWIP_COMPAT_MUTEX 1 + +#endif /* __SYS_ARCH_H__ */ diff --git a/Project/externalModules/lwip_v141/port/ethernetif.h b/Project/externalModules/lwip_v141/port/ethernetif.h new file mode 100644 index 0000000..0db858b --- /dev/null +++ b/Project/externalModules/lwip_v141/port/ethernetif.h @@ -0,0 +1,11 @@ +#ifndef __ETHERNETIF_H__ +#define __ETHERNETIF_H__ + + +#include "lwip/err.h" +#include "lwip/netif.h" + +err_t ethernetif_init(struct netif *netif); +err_t ethernetif_input(struct netif *netif); + +#endif diff --git a/Project/externalModules/lwip_v141/port/lwipopts.h b/Project/externalModules/lwip_v141/port/lwipopts.h new file mode 100644 index 0000000..f36b006 --- /dev/null +++ b/Project/externalModules/lwip_v141/port/lwipopts.h @@ -0,0 +1,1842 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIPOPT_H__ +#define __LWIPOPT_H__ + +/* + ----------------------------------------------- + ---------- Platform specific locking ---------- + ----------------------------------------------- +*/ + +/** + * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain + * critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#ifndef SYS_LIGHTWEIGHT_PROT +#define SYS_LIGHTWEIGHT_PROT 1 +#endif + +/** + * NO_SYS==1: Provides VERY minimal functionality. Otherwise, + * use lwIP facilities. + */ +#ifndef NO_SYS +#define NO_SYS 0 +#endif + +/** + * MEMCPY: override this if you have a faster implementation at hand than the + * one included in your C library + */ +#ifndef MEMCPY +#define MEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/** + * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a + * call to memcpy() if the length is known at compile time and is small. + */ +#ifndef SMEMCPY +#define SMEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/* + ------------------------------------ + ---------- Memory options ---------- + ------------------------------------ +*/ +/** + * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library + * instead of the lwip internal allocator. Can save code size if you + * already use it. + */ +#ifndef MEM_LIBC_MALLOC +#define MEM_LIBC_MALLOC 1 +#endif + +/** +* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator. +* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution +* speed and usage from interrupts! +*/ +#ifndef MEMP_MEM_MALLOC +#define MEMP_MEM_MALLOC 0 +#endif + +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> #define MEM_ALIGNMENT 4 + * 2 byte alignment -> #define MEM_ALIGNMENT 2 + */ +#ifndef MEM_ALIGNMENT +#define MEM_ALIGNMENT 4 +#endif + +/** + * MEM_SIZE: the size of the heap memory. If the application will send + * a lot of data that needs to be copied, this should be set high. + */ +#ifndef MEM_SIZE +//#define MEM_SIZE 1600 +#define MEM_SIZE 6*1600 +#endif + +/** + * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable + * amount of bytes before and after each memp element in every pool and fills + * it with a prominent default value. + * MEMP_OVERFLOW_CHECK == 0 no checking + * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed + * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time + * memp_malloc() or memp_free() is called (useful but slow!) + */ +#ifndef MEMP_OVERFLOW_CHECK +#define MEMP_OVERFLOW_CHECK 0 +#endif + +/** + * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make + * sure that there are no cycles in the linked lists. + */ +#ifndef MEMP_SANITY_CHECK +#define MEMP_SANITY_CHECK 0 +#endif + +/** + * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set + * of memory pools of various sizes. When mem_malloc is called, an element of + * the smallest pool that can provide the length needed is returned. + * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled. + */ +#ifndef MEM_USE_POOLS +#define MEM_USE_POOLS 0 +#endif + +/** + * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next + * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more + * reliable. */ +#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL +#define MEM_USE_POOLS_TRY_BIGGER_POOL 0 +#endif + +/** + * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h + * that defines additional pools beyond the "standard" ones required + * by lwIP. If you set this to 1, you must have lwippools.h in your + * inlude path somewhere. + */ +#ifndef MEMP_USE_CUSTOM_POOLS +#define MEMP_USE_CUSTOM_POOLS 0 +#endif + +/** + * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from + * interrupt context (or another context that doesn't allow waiting for a + * semaphore). + * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT, + * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs + * with each loop so that mem_free can run. + * + * ATTENTION: As you can see from the above description, this leads to dis-/ + * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc + * can need longer. + * + * If you don't want that, at least for NO_SYS=0, you can still use the following + * functions to enqueue a deallocation call which then runs in the tcpip_thread + * context: + * - pbuf_free_callback(p); + * - mem_free_callback(m); + */ +#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT +#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0 +#endif + +/* + ------------------------------------------------ + ---------- Internal Memory Pool Sizes ---------- + ------------------------------------------------ +*/ +/** + * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). + * If the application sends a lot of data out of ROM (or other static memory), + * this should be set high. + */ +#ifndef MEMP_NUM_PBUF +#define MEMP_NUM_PBUF 16 +#endif + +/** + * MEMP_NUM_RAW_PCB: Number of raw connection PCBs + * (requires the LWIP_RAW option) + */ +#ifndef MEMP_NUM_RAW_PCB +#define MEMP_NUM_RAW_PCB 16 +#endif + +/** + * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + * per active UDP "connection". + * (requires the LWIP_UDP option) + */ +#ifndef MEMP_NUM_UDP_PCB +#define MEMP_NUM_UDP_PCB 4 +#endif + +/** + * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB + #ifdef LWIP_UPNP + #define MEMP_NUM_TCP_PCB 12 + #else + #define MEMP_NUM_TCP_PCB 8 + #endif +#endif + +/** + * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB_LISTEN +#define MEMP_NUM_TCP_PCB_LISTEN 8 +#endif + +/** + * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_SEG +#define MEMP_NUM_TCP_SEG 64 +#endif + +/** + * MEMP_NUM_REASSDATA: the number of simultaneously IP packets queued for + * reassembly (whole packets, not fragments!) + */ +#ifndef MEMP_NUM_REASSDATA +#define MEMP_NUM_REASSDATA 5 +#endif + +/** + * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing + * packets (pbufs) that are waiting for an ARP request (to resolve + * their destination address) to finish. + * (requires the ARP_QUEUEING option) + */ +#ifndef MEMP_NUM_ARP_QUEUE +#define MEMP_NUM_ARP_QUEUE 30 +#endif + +/** + * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces + * can be members et the same time (one per netif - allsystems group -, plus one + * per netif membership). + * (requires the LWIP_IGMP option) + */ +#ifndef MEMP_NUM_IGMP_GROUP +#define MEMP_NUM_IGMP_GROUP 8 +#endif + +/** + * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts. + * (requires NO_SYS==0) + * The default number of timeouts is calculated here for all enabled modules. + * The formula expects settings to be either '0' or '1'. + */ +#ifndef MEMP_NUM_SYS_TIMEOUT +#define MEMP_NUM_SYS_TIMEOUT (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_SUPPORT) +#endif + +/** + * MEMP_NUM_NETBUF: the number of struct netbufs. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETBUF +#define MEMP_NUM_NETBUF 2 +#endif + +/** + * MEMP_NUM_NETCONN: the number of struct netconns. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETCONN +//#define MEMP_NUM_NETCONN 4 +#define MEMP_NUM_NETCONN 10 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used + * for callback/timeout API communication. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_API +#define MEMP_NUM_TCPIP_MSG_API 8 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used + * for incoming packets. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_INPKT +#define MEMP_NUM_TCPIP_MSG_INPKT 8 +#endif + +/** + * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + */ +#ifndef PBUF_POOL_SIZE + +#ifdef STM32F4 +#define PBUF_POOL_SIZE 24 +#endif + +#ifdef STM32F1 + #ifdef LWIP_UPNP + #define PBUF_POOL_SIZE 16 + #else + #define PBUF_POOL_SIZE 18 + #endif +#endif + +#endif + +/* + --------------------------------- + ---------- ARP options ---------- + --------------------------------- +*/ +/** + * LWIP_ARP==1: Enable ARP functionality. + */ +#ifndef LWIP_ARP +#define LWIP_ARP 1 +#endif + +/** + * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached. + */ +#ifndef ARP_TABLE_SIZE +#define ARP_TABLE_SIZE 10 +#endif + +/** + * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address + * resolution. By default, only the most recent packet is queued per IP address. + * This is sufficient for most protocols and mainly reduces TCP connection + * startup time. Set this to 1 if you know your application sends more than one + * packet in a row to an IP address that is not in the ARP cache. + */ +#ifndef ARP_QUEUEING +#define ARP_QUEUEING 1 +#endif + +/** + * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be + * updated with the source MAC and IP addresses supplied in the packet. + * You may want to disable this if you do not trust LAN peers to have the + * correct addresses, or as a limited approach to attempt to handle + * spoofing. If disabled, lwIP will need to make a new ARP request if + * the peer is not already in the ARP table, adding a little latency. + * The peer *is* in the ARP table if it requested our address before. + * Also notice that this slows down input processing of every IP packet! + */ +#ifndef ETHARP_TRUST_IP_MAC +#define ETHARP_TRUST_IP_MAC 1 +#endif + +/* + -------------------------------- + ---------- IP options ---------- + -------------------------------- +*/ +/** + * IP_FORWARD==1: Enables the ability to forward IP packets across network + * interfaces. If you are going to run lwIP on a device with only one network + * interface, define this to 0. + */ +#ifndef IP_FORWARD +#define IP_FORWARD 0 +#endif + +/** + * IP_OPTIONS_ALLOWED: Defines the behavior for IP options. + * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped. + * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed). + */ +#ifndef IP_OPTIONS_ALLOWED +#define IP_OPTIONS_ALLOWED 1 +#endif + +/** + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via IP_FRAG. + */ +#ifndef IP_REASSEMBLY +#define IP_REASSEMBLY 1 +#endif + +/** + * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#ifndef IP_FRAG +#define IP_FRAG 1 +#endif + +/** + * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) + * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived + * in this time, the whole packet is discarded. + */ +#ifndef IP_REASS_MAXAGE +#define IP_REASS_MAXAGE 3 +#endif + +/** + * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. + * Since the received pbufs are enqueued, be sure to configure + * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive + * packets even if the maximum amount of fragments is enqueued for reassembly! + */ +#ifndef IP_REASS_MAX_PBUFS +#define IP_REASS_MAX_PBUFS 10 +#endif + +/** + * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP + * fragmentation. Otherwise pbufs are allocated and reference the original + * packet data to be fragmented (or with LWIP_NETIF_TX_SINGLE_PBUF==1, + * new PBUF_RAM pbufs are used for fragments). + * ATTENTION: IP_FRAG_USES_STATIC_BUF==1 may not be used for DMA-enabled MACs! + */ +#ifndef IP_FRAG_USES_STATIC_BUF +#define IP_FRAG_USES_STATIC_BUF 0 +#endif + +/** + * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer + * (requires IP_FRAG_USES_STATIC_BUF==1) + */ +#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU) +#define IP_FRAG_MAX_MTU 1500 +#endif + +/** + * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers. + */ +#ifndef IP_DEFAULT_TTL +#define IP_DEFAULT_TTL 255 +#endif + +/** + * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast + * filter per pcb on udp and raw send operations. To enable broadcast filter + * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1. + */ +#ifndef IP_SOF_BROADCAST +#define IP_SOF_BROADCAST 0 +#endif + +/** + * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast + * filter on recv operations. + */ +#ifndef IP_SOF_BROADCAST_RECV +#define IP_SOF_BROADCAST_RECV 0 +#endif + +/* + ---------------------------------- + ---------- ICMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_ICMP==1: Enable ICMP module inside the IP stack. + * Be careful, disable that make your product non-compliant to RFC1122 + */ +#ifndef LWIP_ICMP +#define LWIP_ICMP 1 +#endif + +/** + * ICMP_TTL: Default value for Time-To-Live used by ICMP packets. + */ +#ifndef ICMP_TTL +#define ICMP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only) + */ +#ifndef LWIP_BROADCAST_PING +#define LWIP_BROADCAST_PING 0 +#endif + +/** + * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only) + */ +#ifndef LWIP_MULTICAST_PING +#define LWIP_MULTICAST_PING 0 +#endif + +/* + --------------------------------- + ---------- RAW options ---------- + --------------------------------- +*/ +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef LWIP_RAW +#define LWIP_RAW 1 +#endif + +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef RAW_TTL +#define RAW_TTL (IP_DEFAULT_TTL) +#endif + +/* + ---------------------------------- + ---------- DHCP options ---------- + ---------------------------------- +*/ +/** + * LWIP_DHCP==1: Enable DHCP module. + */ +#ifndef LWIP_DHCP +#define LWIP_DHCP 1 +#endif + +/** + * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address. + */ +#ifndef DHCP_DOES_ARP_CHECK +#define DHCP_DOES_ARP_CHECK ((LWIP_DHCP) && (LWIP_ARP)) +#endif + +/* + ------------------------------------ + ---------- AUTOIP options ---------- + ------------------------------------ +*/ +/** + * LWIP_AUTOIP==1: Enable AUTOIP module. + */ +#ifndef LWIP_AUTOIP +#define LWIP_AUTOIP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on + * the same interface at the same time. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP +#define LWIP_DHCP_AUTOIP_COOP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes + * that should be sent before falling back on AUTOIP. This can be set + * as low as 1 to get an AutoIP address very quickly, but you should + * be prepared to handle a changing IP address when DHCP overrides + * AutoIP. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES +#define LWIP_DHCP_AUTOIP_COOP_TRIES 9 +#endif + +/* + ---------------------------------- + ---------- SNMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP + * transport. + */ +#ifndef LWIP_SNMP +#define LWIP_SNMP 0 +#endif + +/** + * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will + * allow. At least one request buffer is required. + */ +#ifndef SNMP_CONCURRENT_REQUESTS +#define SNMP_CONCURRENT_REQUESTS 1 +#endif + +/** + * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap + * destination is required + */ +#ifndef SNMP_TRAP_DESTINATIONS +#define SNMP_TRAP_DESTINATIONS 1 +#endif + +/** + * SNMP_PRIVATE_MIB: + * When using a private MIB, you have to create a file 'private_mib.h' that contains + * a 'struct mib_array_node mib_private' which contains your MIB. + */ +#ifndef SNMP_PRIVATE_MIB +#define SNMP_PRIVATE_MIB 0 +#endif + +/** + * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not + * a safe action and disabled when SNMP_SAFE_REQUESTS = 1). + * Unsafe requests are disabled by default! + */ +#ifndef SNMP_SAFE_REQUESTS +#define SNMP_SAFE_REQUESTS 1 +#endif + +/* + ---------------------------------- + ---------- IGMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_IGMP==1: Turn on IGMP module. + */ +#ifndef LWIP_IGMP + +#ifdef LWIP_UPNP + #define LWIP_IGMP 1 +#else + #define LWIP_IGMP 0 +#endif + +#endif + +/* + ---------------------------------- + ---------- DNS options ----------- + ---------------------------------- +*/ +/** + * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS + * transport. + */ +#ifndef LWIP_DNS +#define LWIP_DNS 1 +#endif + +/** DNS maximum number of entries to maintain locally. */ +#ifndef DNS_TABLE_SIZE +#define DNS_TABLE_SIZE 4 +#endif + +/** DNS maximum host name length supported in the name table. */ +#ifndef DNS_MAX_NAME_LENGTH +#define DNS_MAX_NAME_LENGTH 256 +#endif + +/** The maximum of DNS servers */ +#ifndef DNS_MAX_SERVERS +#define DNS_MAX_SERVERS 2 +#endif + +/** DNS do a name checking between the query and the response. */ +#ifndef DNS_DOES_NAME_CHECK +#define DNS_DOES_NAME_CHECK 1 +#endif + +/** DNS message max. size. Default value is RFC compliant. */ +#ifndef DNS_MSG_SIZE +#define DNS_MSG_SIZE 512 +#endif + +/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, + * you have to define + * #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}} + * (an array of structs name/address, where address is an u32_t in network + * byte order). + * + * Instead, you can also use an external function: + * #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name) + * that returns the IP address or INADDR_NONE if not found. + */ +#ifndef DNS_LOCAL_HOSTLIST +#define DNS_LOCAL_HOSTLIST 0 +#endif /* DNS_LOCAL_HOSTLIST */ + +/** If this is turned on, the local host-list can be dynamically changed + * at runtime. */ +#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC +#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0 +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +/* + --------------------------------- + ---------- UDP options ---------- + --------------------------------- +*/ +/** + * LWIP_UDP==1: Turn on UDP. + */ +#ifndef LWIP_UDP +#define LWIP_UDP 1 +#endif + +/** + * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP) + */ +#ifndef LWIP_UDPLITE +#define LWIP_UDPLITE 0 +#endif + +/** + * UDP_TTL: Default Time-To-Live value. + */ +#ifndef UDP_TTL +#define UDP_TTL (IP_DEFAULT_TTL) +#endif + +/* + --------------------------------- + ---------- TCP options ---------- + --------------------------------- +*/ +/** + * LWIP_TCP==1: Turn on TCP. + */ +#ifndef LWIP_TCP +#define LWIP_TCP 1 +#endif + +/** + * TCP_TTL: Default Time-To-Live value. + */ +#ifndef TCP_TTL +#define TCP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * TCP_MSS: TCP Maximum segment size. (default is 128, a *very* + * conservative default.) + * For the receive side, this MSS is advertised to the remote side + * when opening a connection. For the transmit size, this MSS sets + * an upper limit on the MSS advertised by the remote host. + */ +#ifndef TCP_MSS +#define TCP_MSS 1460 +#endif + +/** + * TCP_WND: The size of a TCP window. This must be at least + * (2 * TCP_MSS) for things to work well + */ +#ifndef TCP_WND + #ifdef LWIP_UPNP + #define TCP_WND (8 * TCP_MSS) /* (4 * TCP_MSS) */ + #else + #define TCP_WND (8 * TCP_MSS) /* (4 * TCP_MSS) */ + #endif +#endif + +/** + * TCP_MAXRTX: Maximum number of retransmissions of data segments. + */ +#ifndef TCP_MAXRTX +#define TCP_MAXRTX 12 +#endif + +/** + * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. + */ +#ifndef TCP_SYNMAXRTX +#define TCP_SYNMAXRTX 6 +#endif + +/** + * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order. + * Define to 0 if your device is low on memory. + */ +#ifndef TCP_QUEUE_OOSEQ +#define TCP_QUEUE_OOSEQ (LWIP_TCP) +#endif + +/** + * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really + * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which + * reflects the available reassembly buffer size at the remote host) and the + * largest size permitted by the IP layer" (RFC 1122) + * Setting this to 1 enables code that checks TCP_MSS against the MTU of the + * netif used for a connection and limits the MSS if it would be too big otherwise. + */ +#ifndef TCP_CALCULATE_EFF_SEND_MSS +#define TCP_CALCULATE_EFF_SEND_MSS 1 +#endif + + +/** + * TCP_SND_BUF: TCP sender buffer space (bytes). + */ +#ifndef TCP_SND_BUF + +#ifdef STM32F4 +#define TCP_SND_BUF (20*TCP_MSS) +#endif + +#ifdef STM32F1 + #ifdef LWIP_UPNP + #define TCP_SND_BUF (15*TCP_MSS) + #else + #define TCP_SND_BUF (16*TCP_MSS) + #endif +#endif + +#endif + +/** + * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb. + */ +#ifndef TCP_LISTEN_BACKLOG +#define TCP_LISTEN_BACKLOG 0 +#endif + +/** + * The maximum allowed backlog for TCP listen netconns. + * This backlog is used unless another is explicitly specified. + * 0xff is the maximum (u8_t). + */ +#ifndef TCP_DEFAULT_LISTEN_BACKLOG +#define TCP_DEFAULT_LISTEN_BACKLOG 0xff +#endif + +/** + * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option. + */ +#ifndef LWIP_TCP_TIMESTAMPS +#define LWIP_TCP_TIMESTAMPS 0 +#endif + +#if LWIP_TCP_TIMESTAMPS +#define TCP_SACK +#endif + +/** + * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an + * explicit window update + */ +#ifndef TCP_WND_UPDATE_THRESHOLD +#define TCP_WND_UPDATE_THRESHOLD (TCP_WND / 4) +#endif + +/** + * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1. + * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all + * events (accept, sent, etc) that happen in the system. + * LWIP_CALLBACK_API==1: The PCB callback function is called directly + * for the event. + */ +//#define LWIP_EVENT_API + +/* + ---------------------------------- + ---------- Pbuf options ---------- + ---------------------------------- +*/ +/** + * PBUF_LINK_HLEN: the number of bytes that should be allocated for a + * link level header. The default is 14, the standard value for + * Ethernet. + */ +#ifndef PBUF_LINK_HLEN +#define PBUF_LINK_HLEN (14 + ETH_PAD_SIZE) +#endif + +/** + * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is + * designed to accomodate single full size TCP frame in one pbuf, including + * TCP_MSS, IP header, and link header. + */ +#ifndef PBUF_POOL_BUFSIZE +#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN + 16 + 128) /* hic header + 128 safe packet*/ +#endif + +/* + ------------------------------------------------ + ---------- Network Interfaces options ---------- + ------------------------------------------------ +*/ +/** + * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname + * field. + */ +#ifndef LWIP_NETIF_HOSTNAME +#define LWIP_NETIF_HOSTNAME 1 +#endif + +/** + * LWIP_NETIF_API==1: Support netif api (in netifapi.c) + */ +#ifndef LWIP_NETIF_API +#define LWIP_NETIF_API 0 +#endif + +/** + * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface + * changes its up/down status (i.e., due to DHCP IP acquistion) + */ +#ifndef LWIP_NETIF_STATUS_CALLBACK +#define LWIP_NETIF_STATUS_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface + * whenever the link changes (i.e., link down) + */ +#ifndef LWIP_NETIF_LINK_CALLBACK +#define LWIP_NETIF_LINK_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table + * indices) in struct netif. TCP and UDP can make use of this to prevent + * scanning the ARP table for every sent packet. While this is faster for big + * ARP tables or many concurrent connections, it might be counterproductive + * if you have a tiny ARP table or if there never are concurrent connections. + */ +#ifndef LWIP_NETIF_HWADDRHINT +#define LWIP_NETIF_HWADDRHINT 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP + * address equal to the netif IP address, looping them back up the stack. + */ +#ifndef LWIP_NETIF_LOOPBACK +#define LWIP_NETIF_LOOPBACK 0 +#endif + +/** + * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback + * sending for each netif (0 = disabled) + */ +#ifndef LWIP_LOOPBACK_MAX_PBUFS +#define LWIP_LOOPBACK_MAX_PBUFS 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in + * the system, as netifs must change how they behave depending on this setting + * for the LWIP_NETIF_LOOPBACK option to work. + * Setting this is needed to avoid reentering non-reentrant functions like + * tcp_input(). + * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a + * multithreaded environment like tcpip.c. In this case, netif->input() + * is called directly. + * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup. + * The packets are put on a list and netif_poll() must be called in + * the main application loop. + */ +#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING +#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS) +#endif + +/** + * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data + * to be sent into one single pbuf. This is for compatibility with DMA-enabled + * MACs that do not support scatter-gather. + * Beware that this might involve CPU-memcpy before transmitting that would not + * be needed without this flag! Use this only if you need to! + * + * @todo: TCP and IP-frag do not work with this, yet: + */ +#ifndef LWIP_NETIF_TX_SINGLE_PBUF +#define LWIP_NETIF_TX_SINGLE_PBUF 1 +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + +/* + ------------------------------------ + ---------- LOOPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c + */ +#ifndef LWIP_HAVE_LOOPIF +#define LWIP_HAVE_LOOPIF 0 +#endif + +/* + ------------------------------------ + ---------- SLIPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c + */ +#ifndef LWIP_HAVE_SLIPIF +#define LWIP_HAVE_SLIPIF 0 +#endif + +/* + ------------------------------------ + ---------- Thread options ---------- + ------------------------------------ +*/ +/** + * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread. + */ +#ifndef TCPIP_THREAD_NAME +#define TCPIP_THREAD_NAME "tcpip_thread" +#endif + +/** + * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_STACKSIZE +#define TCPIP_THREAD_STACKSIZE 1024 +#endif + +/** + * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_PRIO +//#define TCPIP_THREAD_PRIO (LOWPRIO + 1) +#define TCPIP_THREAD_PRIO (NORMALPRIO) +#endif + +/** + * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when tcpip_init is called. + */ +#ifndef TCPIP_MBOX_SIZE +#define TCPIP_MBOX_SIZE 4 +#endif + +/** + * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread. + */ +#ifndef SLIPIF_THREAD_NAME +#define SLIPIF_THREAD_NAME "slipif_loop" +#endif + +/** + * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_STACKSIZE +#define SLIPIF_THREAD_STACKSIZE 1024 +#endif + +/** + * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_PRIO +#define SLIPIF_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * PPP_THREAD_NAME: The name assigned to the pppMain thread. + */ +#ifndef PPP_THREAD_NAME +#define PPP_THREAD_NAME "pppMain" +#endif + +/** + * PPP_THREAD_STACKSIZE: The stack size used by the pppMain thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_STACKSIZE +#define PPP_THREAD_STACKSIZE 1024 +#endif + +/** + * PPP_THREAD_PRIO: The priority assigned to the pppMain thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_PRIO +#define PPP_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread. + */ +#ifndef DEFAULT_THREAD_NAME +#define DEFAULT_THREAD_NAME "lwIP" +#endif + +/** + * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_STACKSIZE +#define DEFAULT_THREAD_STACKSIZE 1024 +#endif + +/** + * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_PRIO +#define DEFAULT_THREAD_PRIO (NORMALPRIO) +#endif + +/** + * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_RAW_RECVMBOX_SIZE +#define DEFAULT_RAW_RECVMBOX_SIZE 4 +#endif + +/** + * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_UDP_RECVMBOX_SIZE +#define DEFAULT_UDP_RECVMBOX_SIZE 4 +#endif + +/** + * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_TCP_RECVMBOX_SIZE +#define DEFAULT_TCP_RECVMBOX_SIZE 40 +#endif + +/** + * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when the acceptmbox is created. + */ +#ifndef DEFAULT_ACCEPTMBOX_SIZE +#define DEFAULT_ACCEPTMBOX_SIZE 4 +#endif + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +/** + * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING +#define LWIP_TCPIP_CORE_LOCKING 0 +#endif + +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#ifndef LWIP_NETCONN +#define LWIP_NETCONN 1 +#endif + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#ifndef LWIP_SOCKET +#define LWIP_SOCKET 1 +#endif + +/** + * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names. + * (only used if you use sockets.c) + */ +#ifndef LWIP_COMPAT_SOCKETS +#define LWIP_COMPAT_SOCKETS 1 +#endif + +/** + * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names. + * Disable this option if you use a POSIX operating system that uses the same + * names (read, write & close). (only used if you use sockets.c) + */ +#ifndef LWIP_POSIX_SOCKETS_IO_NAMES +#define LWIP_POSIX_SOCKETS_IO_NAMES 1 +#endif + +/** + * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT + * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set + * in seconds. (does not require sockets.c, and will affect tcp.c) + */ +#ifndef LWIP_TCP_KEEPALIVE +#define LWIP_TCP_KEEPALIVE 0 +#endif + +/** + * LWIP_SO_RCVTIMEO==1: Enable SO_RCVTIMEO processing. + */ +#ifndef LWIP_SO_RCVTIMEO +//#define LWIP_SO_RCVTIMEO 0 +#define LWIP_SO_RCVTIMEO 1 +#endif + +/** + * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing. + */ +#ifndef LWIP_SO_RCVBUF +#define LWIP_SO_RCVBUF 0 +#endif + +/** + * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize. + */ +#ifndef RECV_BUFSIZE_DEFAULT +#define RECV_BUFSIZE_DEFAULT INT_MAX +#endif + +/** + * SO_REUSE==1: Enable SO_REUSEADDR and SO_REUSEPORT options. DO NOT USE! + */ +#ifndef SO_REUSE +#define SO_REUSE 0 +#endif + +/* + ---------------------------------------- + ---------- Statistics options ---------- + ---------------------------------------- +*/ +/** + * LWIP_STATS==1: Enable statistics collection in lwip_stats. + */ +#ifndef LWIP_STATS +#define LWIP_STATS 1 +#endif + +#if LWIP_STATS + +/** + * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. + */ +#ifndef LWIP_STATS_DISPLAY +#define LWIP_STATS_DISPLAY 0 +#endif + +/** + * LINK_STATS==1: Enable link stats. + */ +#ifndef LINK_STATS +#define LINK_STATS 0 +#endif + +/** + * ETHARP_STATS==1: Enable etharp stats. + */ +#ifndef ETHARP_STATS +#define ETHARP_STATS (LWIP_ARP) +#endif + +/** + * IP_STATS==1: Enable IP stats. + */ +#ifndef IP_STATS +#define IP_STATS 0 +#endif + +/** + * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is + * on if using either frag or reass. + */ +#ifndef IPFRAG_STATS +#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG) +#endif + +/** + * ICMP_STATS==1: Enable ICMP stats. + */ +#ifndef ICMP_STATS +#define ICMP_STATS 0 +#endif + +/** + * IGMP_STATS==1: Enable IGMP stats. + */ +#ifndef IGMP_STATS +#define IGMP_STATS (LWIP_IGMP) +#endif + +/** + * UDP_STATS==1: Enable UDP stats. Default is on if + * UDP enabled, otherwise off. + */ +#ifndef UDP_STATS +#define UDP_STATS (LWIP_UDP) +#endif + +/** + * TCP_STATS==1: Enable TCP stats. Default is on if TCP + * enabled, otherwise off. + */ +#ifndef TCP_STATS +#define TCP_STATS (LWIP_TCP) +#endif + +/** + * MEM_STATS==1: Enable mem.c stats. + */ +#ifndef MEM_STATS +#define MEM_STATS 0 +#endif + +/** + * MEMP_STATS==1: Enable memp.c pool stats. + */ +#ifndef MEMP_STATS +#define MEMP_STATS 1 +#endif + +/** + * SYS_STATS==1: Enable system stats (sem and mbox counts, etc). + */ +#ifndef SYS_STATS +#define SYS_STATS 0 +#endif + +#else + +#define LINK_STATS 0 +#define IP_STATS 0 +#define IPFRAG_STATS 0 +#define ICMP_STATS 0 +#define IGMP_STATS 0 +#define UDP_STATS 0 +#define TCP_STATS 0 +#define MEM_STATS 0 +#define MEMP_STATS 0 +#define SYS_STATS 0 +#define LWIP_STATS_DISPLAY 0 + +#endif /* LWIP_STATS */ + +/* + --------------------------------- + ---------- PPP options ---------- + --------------------------------- +*/ +/** + * PPP_SUPPORT==1: Enable PPP. + */ +#ifndef PPP_SUPPORT +#define PPP_SUPPORT 0 +#endif + +/** + * PPPOE_SUPPORT==1: Enable PPP Over Ethernet + */ +#ifndef PPPOE_SUPPORT +#define PPPOE_SUPPORT 0 +#endif + +/** + * PPPOS_SUPPORT==1: Enable PPP Over Serial + */ +#ifndef PPPOS_SUPPORT +#define PPPOS_SUPPORT PPP_SUPPORT +#endif + +#if PPP_SUPPORT + +/** + * NUM_PPP: Max PPP sessions. + */ +#ifndef NUM_PPP +#define NUM_PPP 1 +#endif + +/** + * PAP_SUPPORT==1: Support PAP. + */ +#ifndef PAP_SUPPORT +#define PAP_SUPPORT 0 +#endif + +/** + * CHAP_SUPPORT==1: Support CHAP. + */ +#ifndef CHAP_SUPPORT +#define CHAP_SUPPORT 0 +#endif + +/** + * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef MSCHAP_SUPPORT +#define MSCHAP_SUPPORT 0 +#endif + +/** + * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CBCP_SUPPORT +#define CBCP_SUPPORT 0 +#endif + +/** + * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CCP_SUPPORT +#define CCP_SUPPORT 0 +#endif + +/** + * VJ_SUPPORT==1: Support VJ header compression. + */ +#ifndef VJ_SUPPORT +#define VJ_SUPPORT 0 +#endif + +/** + * MD5_SUPPORT==1: Support MD5 (see also CHAP). + */ +#ifndef MD5_SUPPORT +#define MD5_SUPPORT 0 +#endif + +/* + * Timeouts + */ +#ifndef FSM_DEFTIMEOUT +#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef FSM_DEFMAXTERMREQS +#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXCONFREQS +#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXNAKLOOPS +#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */ +#endif + +#ifndef UPAP_DEFTIMEOUT +#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */ +#endif + +#ifndef UPAP_DEFREQTIME +#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */ +#endif + +#ifndef CHAP_DEFTIMEOUT +#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef CHAP_DEFTRANSMITS +#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */ +#endif + +/* Interval in seconds between keepalive echo requests, 0 to disable. */ +#ifndef LCP_ECHOINTERVAL +#define LCP_ECHOINTERVAL 0 +#endif + +/* Number of unanswered echo requests before failure. */ +#ifndef LCP_MAXECHOFAILS +#define LCP_MAXECHOFAILS 3 +#endif + +/* Max Xmit idle time (in jiffies) before resend flag char. */ +#ifndef PPP_MAXIDLEFLAG +#define PPP_MAXIDLEFLAG 100 +#endif + +/* + * Packet sizes + * + * Note - lcp shouldn't be allowed to negotiate stuff outside these + * limits. See lcp.h in the pppd directory. + * (XXX - these constants should simply be shared by lcp.c instead + * of living in lcp.h) + */ +#define PPP_MTU 1500 /* Default MTU (size of Info field) */ +#ifndef PPP_MAXMTU +/* #define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) */ +#define PPP_MAXMTU 1500 /* Largest MTU we allow */ +#endif +#define PPP_MINMTU 64 +#define PPP_MRU 1500 /* default MRU = max length of info field */ +#define PPP_MAXMRU 1500 /* Largest MRU we allow */ +#ifndef PPP_DEFMRU +#define PPP_DEFMRU 296 /* Try for this */ +#endif +#define PPP_MINMRU 128 /* No MRUs below this */ + + +#define MAXNAMELEN 256 /* max length of hostname or name for auth */ +#define MAXSECRETLEN 256 /* max length of password or secret */ + +#endif /* PPP_SUPPORT */ + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ +#define CHECKSUM_BY_HARDWARE +/** + * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets. + * copi: if this is disabled, dhcp discover fails. +*/ +#ifndef CHECKSUM_GEN_IP +#define CHECKSUM_GEN_IP 1 +#endif + +/** + * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets. + */ +#ifndef CHECKSUM_GEN_UDP +#define CHECKSUM_GEN_UDP 1 +#endif + +/** + * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets. + */ +#ifndef CHECKSUM_GEN_TCP +#define CHECKSUM_GEN_TCP 1 +#endif + +/** + * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets. + */ +#ifndef CHECKSUM_CHECK_IP +#define CHECKSUM_CHECK_IP 0 +#endif + +/** + * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets. + */ +#ifndef CHECKSUM_CHECK_UDP +#define CHECKSUM_CHECK_UDP 0 +#endif + +/** + * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets. + */ +#ifndef CHECKSUM_CHECK_TCP +#define CHECKSUM_CHECK_TCP 0 +#endif + +/* + --------------------------------------- + ---------- Debugging options ---------- + --------------------------------------- +*/ +/** + * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is + * compared against this value. If it is smaller, then debugging + * messages are written. + */ +#ifndef LWIP_DBG_MIN_LEVEL +#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_OFF +#endif + +/** + * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable + * debug messages of certain types. + */ +#ifndef LWIP_DBG_TYPES_ON +#define LWIP_DBG_TYPES_ON LWIP_DBG_ON +#endif + +/** + * ETHARP_DEBUG: Enable debugging in etharp.c. + */ +#ifndef ETHARP_DEBUG +#define ETHARP_DEBUG LWIP_DBG_OFF +#endif + +/** + * NETIF_DEBUG: Enable debugging in netif.c. + */ +#ifndef NETIF_DEBUG +#define NETIF_DEBUG LWIP_DBG_ON +#endif + +/** + * PBUF_DEBUG: Enable debugging in pbuf.c. + */ +#ifndef PBUF_DEBUG +#define PBUF_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_LIB_DEBUG: Enable debugging in api_lib.c. + */ +#ifndef API_LIB_DEBUG +#define API_LIB_DEBUG LWIP_DBG_ON +#endif + +/** + * API_MSG_DEBUG: Enable debugging in api_msg.c. + */ +#ifndef API_MSG_DEBUG +#define API_MSG_DEBUG LWIP_DBG_ON +#endif + +/** + * SOCKETS_DEBUG: Enable debugging in sockets.c. + */ +#ifndef SOCKETS_DEBUG +#define SOCKETS_DEBUG LWIP_DBG_ON +#endif + +/** + * ICMP_DEBUG: Enable debugging in icmp.c. + */ +#ifndef ICMP_DEBUG +#define ICMP_DEBUG LWIP_DBG_ON +#endif + +/** + * IGMP_DEBUG: Enable debugging in igmp.c. + */ +#ifndef IGMP_DEBUG +#define IGMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * INET_DEBUG: Enable debugging in inet.c. + */ +#ifndef INET_DEBUG +#define INET_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_DEBUG: Enable debugging for IP. + */ +#ifndef IP_DEBUG +#define IP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass. + */ +#ifndef IP_REASS_DEBUG +#define IP_REASS_DEBUG LWIP_DBG_OFF +#endif + +/** + * RAW_DEBUG: Enable debugging in raw.c. + */ +#ifndef RAW_DEBUG +#define RAW_DEBUG LWIP_DBG_ON +#endif + +/** + * MEM_DEBUG: Enable debugging in mem.c. + */ +#ifndef MEM_DEBUG +#define MEM_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEMP_DEBUG: Enable debugging in memp.c. + */ +#ifndef MEMP_DEBUG +#define MEMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SYS_DEBUG: Enable debugging in sys.c. + */ +#ifndef SYS_DEBUG +#define SYS_DEBUG LWIP_DBG_ON +#endif + +/** + * TIMERS_DEBUG: Enable debugging in timers.c. + */ +#ifndef TIMERS_DEBUG +#define TIMERS_DEBUG LWIP_DBG_ON +#endif + +/** + * TCP_DEBUG: Enable debugging for TCP. + */ +#ifndef TCP_DEBUG +#define TCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug. + */ +#ifndef TCP_INPUT_DEBUG +#define TCP_INPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit. + */ +#ifndef TCP_FR_DEBUG +#define TCP_FR_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit + * timeout. + */ +#ifndef TCP_RTO_DEBUG +#define TCP_RTO_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_CWND_DEBUG: Enable debugging for TCP congestion window. + */ +#ifndef TCP_CWND_DEBUG +#define TCP_CWND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating. + */ +#ifndef TCP_WND_DEBUG +#define TCP_WND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions. + */ +#ifndef TCP_OUTPUT_DEBUG +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RST_DEBUG: Enable debugging for TCP with the RST message. + */ +#ifndef TCP_RST_DEBUG +#define TCP_RST_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths. + */ +#ifndef TCP_QLEN_DEBUG +#define TCP_QLEN_DEBUG LWIP_DBG_OFF +#endif + +/** + * UDP_DEBUG: Enable debugging in UDP. + */ +#ifndef UDP_DEBUG +#define UDP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCPIP_DEBUG: Enable debugging in tcpip.c. + */ +#ifndef TCPIP_DEBUG +#define TCPIP_DEBUG LWIP_DBG_ON +#endif + +/** + * PPP_DEBUG: Enable debugging for PPP. + */ +#ifndef PPP_DEBUG +#define PPP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SLIP_DEBUG: Enable debugging in slipif.c. + */ +#ifndef SLIP_DEBUG +#define SLIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * DHCP_DEBUG: Enable debugging in dhcp.c. + */ +#ifndef DHCP_DEBUG +#define DHCP_DEBUG LWIP_DBG_ON +#endif + +/** + * AUTOIP_DEBUG: Enable debugging in autoip.c. + */ +#ifndef AUTOIP_DEBUG +#define AUTOIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MSG_DEBUG: Enable debugging for SNMP messages. + */ +#ifndef SNMP_MSG_DEBUG +#define SNMP_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs. + */ +#ifndef SNMP_MIB_DEBUG +#define SNMP_MIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * DNS_DEBUG: Enable debugging for DNS. + */ +#ifndef DNS_DEBUG +#define DNS_DEBUG LWIP_DBG_ON +#endif + +#endif /* __LWIPOPT_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/ipv4/lwip/autoip.h b/Project/externalModules/lwip_v141/src/include/ipv4/lwip/autoip.h new file mode 100644 index 0000000..064ef87 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/ipv4/lwip/autoip.h @@ -0,0 +1,118 @@ +/** + * @file + * + * AutoIP Automatic LinkLocal IP Configuration + */ + +/* + * + * Copyright (c) 2007 Dominik Spies + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Dominik Spies + * + * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform + * with RFC 3927. + * + * + * Please coordinate changes and requests with Dominik Spies + * + */ + +#ifndef __LWIP_AUTOIP_H__ +#define __LWIP_AUTOIP_H__ + +#include "lwip/opt.h" + +#if LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/netif.h" +#include "lwip/udp.h" +#include "netif/etharp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* AutoIP Timing */ +#define AUTOIP_TMR_INTERVAL 100 +#define AUTOIP_TICKS_PER_SECOND (1000 / AUTOIP_TMR_INTERVAL) + +/* RFC 3927 Constants */ +#define PROBE_WAIT 1 /* second (initial random delay) */ +#define PROBE_MIN 1 /* second (minimum delay till repeated probe) */ +#define PROBE_MAX 2 /* seconds (maximum delay till repeated probe) */ +#define PROBE_NUM 3 /* (number of probe packets) */ +#define ANNOUNCE_NUM 2 /* (number of announcement packets) */ +#define ANNOUNCE_INTERVAL 2 /* seconds (time between announcement packets) */ +#define ANNOUNCE_WAIT 2 /* seconds (delay before announcing) */ +#define MAX_CONFLICTS 10 /* (max conflicts before rate limiting) */ +#define RATE_LIMIT_INTERVAL 60 /* seconds (delay between successive attempts) */ +#define DEFEND_INTERVAL 10 /* seconds (min. wait between defensive ARPs) */ + +/* AutoIP client states */ +#define AUTOIP_STATE_OFF 0 +#define AUTOIP_STATE_PROBING 1 +#define AUTOIP_STATE_ANNOUNCING 2 +#define AUTOIP_STATE_BOUND 3 + +struct autoip +{ + ip_addr_t llipaddr; /* the currently selected, probed, announced or used LL IP-Address */ + u8_t state; /* current AutoIP state machine state */ + u8_t sent_num; /* sent number of probes or announces, dependent on state */ + u16_t ttw; /* ticks to wait, tick is AUTOIP_TMR_INTERVAL long */ + u8_t lastconflict; /* ticks until a conflict can be solved by defending */ + u8_t tried_llipaddr; /* total number of probed/used Link Local IP-Addresses */ +}; + + +#define autoip_init() /* Compatibility define, no init needed. */ + +/** Set a struct autoip allocated by the application to work with */ +void autoip_set_struct(struct netif *netif, struct autoip *autoip); + +/** Start AutoIP client */ +err_t autoip_start(struct netif *netif); + +/** Stop AutoIP client */ +err_t autoip_stop(struct netif *netif); + +/** Handles every incoming ARP Packet, called by etharp_arp_input */ +void autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr); + +/** Has to be called in loop every AUTOIP_TMR_INTERVAL milliseconds */ +void autoip_tmr(void); + +/** Handle a possible change in the network configuration */ +void autoip_network_changed(struct netif *netif); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_AUTOIP */ + +#endif /* __LWIP_AUTOIP_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/ipv4/lwip/icmp.h b/Project/externalModules/lwip_v141/src/include/ipv4/lwip/icmp.h new file mode 100644 index 0000000..c937c63 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/ipv4/lwip/icmp.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_ICMP_H__ +#define __LWIP_ICMP_H__ + +#include "lwip/opt.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ICMP_ER 0 /* echo reply */ +#define ICMP_DUR 3 /* destination unreachable */ +#define ICMP_SQ 4 /* source quench */ +#define ICMP_RD 5 /* redirect */ +#define ICMP_ECHO 8 /* echo */ +#define ICMP_TE 11 /* time exceeded */ +#define ICMP_PP 12 /* parameter problem */ +#define ICMP_TS 13 /* timestamp */ +#define ICMP_TSR 14 /* timestamp reply */ +#define ICMP_IRQ 15 /* information request */ +#define ICMP_IR 16 /* information reply */ + +enum icmp_dur_type { + ICMP_DUR_NET = 0, /* net unreachable */ + ICMP_DUR_HOST = 1, /* host unreachable */ + ICMP_DUR_PROTO = 2, /* protocol unreachable */ + ICMP_DUR_PORT = 3, /* port unreachable */ + ICMP_DUR_FRAG = 4, /* fragmentation needed and DF set */ + ICMP_DUR_SR = 5 /* source route failed */ +}; + +enum icmp_te_type { + ICMP_TE_TTL = 0, /* time to live exceeded in transit */ + ICMP_TE_FRAG = 1 /* fragment reassembly time exceeded */ +}; + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +/** This is the standard ICMP header only that the u32_t data + * is splitted to two u16_t like ICMP echo needs it. + * This header is also used for other ICMP types that do not + * use the data part. + */ +PACK_STRUCT_BEGIN +struct icmp_echo_hdr { + PACK_STRUCT_FIELD(u8_t type); + PACK_STRUCT_FIELD(u8_t code); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u16_t id); + PACK_STRUCT_FIELD(u16_t seqno); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define ICMPH_TYPE(hdr) ((hdr)->type) +#define ICMPH_CODE(hdr) ((hdr)->code) + +/** Combines type and code to an u16_t */ +#define ICMPH_TYPE_SET(hdr, t) ((hdr)->type = (t)) +#define ICMPH_CODE_SET(hdr, c) ((hdr)->code = (c)) + + +#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */ + +void icmp_input(struct pbuf *p, struct netif *inp); +void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t); +void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t); + +#endif /* LWIP_ICMP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_ICMP_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/ipv4/lwip/igmp.h b/Project/externalModules/lwip_v141/src/include/ipv4/lwip/igmp.h new file mode 100644 index 0000000..b65cb5f --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/ipv4/lwip/igmp.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2002 CITEL Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS'' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is a contribution to the lwIP TCP/IP stack. + * The Swedish Institute of Computer Science and Adam Dunkels + * are specifically granted permission to redistribute this + * source code. +*/ + +#ifndef __LWIP_IGMP_H__ +#define __LWIP_IGMP_H__ + +#include "lwip/opt.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/pbuf.h" + +#if LWIP_IGMP /* don't build if not configured for use in lwipopts.h */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/* IGMP timer */ +#define IGMP_TMR_INTERVAL 200 /* Milliseconds */ +#define IGMP_V1_DELAYING_MEMBER_TMR (1000/IGMP_TMR_INTERVAL) +#define IGMP_JOIN_DELAYING_MEMBER_TMR (500 /IGMP_TMR_INTERVAL) + +/* MAC Filter Actions, these are passed to a netif's + * igmp_mac_filter callback function. */ +#define IGMP_DEL_MAC_FILTER 0 +#define IGMP_ADD_MAC_FILTER 1 + + +/** + * igmp group structure - there is + * a list of groups for each interface + * these should really be linked from the interface, but + * if we keep them separate we will not affect the lwip original code + * too much + * + * There will be a group for the all systems group address but this + * will not run the state machine as it is used to kick off reports + * from all the other groups + */ +struct igmp_group { + /** next link */ + struct igmp_group *next; + /** interface on which the group is active */ + struct netif *netif; + /** multicast address */ + ip_addr_t group_address; + /** signifies we were the last person to report */ + u8_t last_reporter_flag; + /** current state of the group */ + u8_t group_state; + /** timer for reporting, negative is OFF */ + u16_t timer; + /** counter of simultaneous uses */ + u8_t use; +}; + +#if LWIP_UPNP +extern ip_addr_t ssdp_mcast_group; +#endif + + +/* Prototypes */ +void igmp_init(void); +err_t igmp_start(struct netif *netif); +err_t igmp_stop(struct netif *netif); +void igmp_report_groups(struct netif *netif); +struct igmp_group *igmp_lookfor_group(struct netif *ifp, ip_addr_t *addr); +void igmp_input(struct pbuf *p, struct netif *inp, ip_addr_t *dest); +err_t igmp_joingroup(ip_addr_t *ifaddr, ip_addr_t *groupaddr); +err_t igmp_leavegroup(ip_addr_t *ifaddr, ip_addr_t *groupaddr); +void igmp_tmr(void); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IGMP */ + +#endif /* __LWIP_IGMP_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/ipv4/lwip/inet.h b/Project/externalModules/lwip_v141/src/include/ipv4/lwip/inet.h new file mode 100644 index 0000000..61084a4 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/ipv4/lwip/inet.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_INET_H__ +#define __LWIP_INET_H__ + +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/ip_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** For compatibility with BSD code */ +struct in_addr { + u32_t s_addr; +}; + +/** 255.255.255.255 */ +#define INADDR_NONE IPADDR_NONE +/** 127.0.0.1 */ +#define INADDR_LOOPBACK IPADDR_LOOPBACK +/** 0.0.0.0 */ +#define INADDR_ANY IPADDR_ANY +/** 255.255.255.255 */ +#define INADDR_BROADCAST IPADDR_BROADCAST + +/* Definitions of the bits in an Internet address integer. + + On subnets, host and network parts are found according to + the subnet mask, not these masks. */ +#define IN_CLASSA(a) IP_CLASSA(a) +#define IN_CLASSA_NET IP_CLASSA_NET +#define IN_CLASSA_NSHIFT IP_CLASSA_NSHIFT +#define IN_CLASSA_HOST IP_CLASSA_HOST +#define IN_CLASSA_MAX IP_CLASSA_MAX + +#define IN_CLASSB(b) IP_CLASSB(b) +#define IN_CLASSB_NET IP_CLASSB_NET +#define IN_CLASSB_NSHIFT IP_CLASSB_NSHIFT +#define IN_CLASSB_HOST IP_CLASSB_HOST +#define IN_CLASSB_MAX IP_CLASSB_MAX + +#define IN_CLASSC(c) IP_CLASSC(c) +#define IN_CLASSC_NET IP_CLASSC_NET +#define IN_CLASSC_NSHIFT IP_CLASSC_NSHIFT +#define IN_CLASSC_HOST IP_CLASSC_HOST +#define IN_CLASSC_MAX IP_CLASSC_MAX + +#define IN_CLASSD(d) IP_CLASSD(d) +#define IN_CLASSD_NET IP_CLASSD_NET /* These ones aren't really */ +#define IN_CLASSD_NSHIFT IP_CLASSD_NSHIFT /* net and host fields, but */ +#define IN_CLASSD_HOST IP_CLASSD_HOST /* routing needn't know. */ +#define IN_CLASSD_MAX IP_CLASSD_MAX + +#define IN_MULTICAST(a) IP_MULTICAST(a) + +#define IN_EXPERIMENTAL(a) IP_EXPERIMENTAL(a) +#define IN_BADCLASS(a) IP_BADCLASS(a) + +#define IN_LOOPBACKNET IP_LOOPBACKNET + +#define inet_addr_from_ipaddr(target_inaddr, source_ipaddr) ((target_inaddr)->s_addr = ip4_addr_get_u32(source_ipaddr)) +#define inet_addr_to_ipaddr(target_ipaddr, source_inaddr) (ip4_addr_set_u32(target_ipaddr, (source_inaddr)->s_addr)) +/* ATTENTION: the next define only works because both s_addr and ip_addr_t are an u32_t effectively! */ +#define inet_addr_to_ipaddr_p(target_ipaddr_p, source_inaddr) ((target_ipaddr_p) = (ip_addr_t*)&((source_inaddr)->s_addr)) + +/* directly map this to the lwip internal functions */ +#define inet_addr(cp) ipaddr_addr(cp) +#define inet_aton(cp, addr) ipaddr_aton(cp, (ip_addr_t*)addr) +#define inet_ntoa(addr) ipaddr_ntoa((ip_addr_t*)&(addr)) +#define inet_ntoa_r(addr, buf, buflen) ipaddr_ntoa_r((ip_addr_t*)&(addr), buf, buflen) + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_INET_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/ipv4/lwip/inet_chksum.h b/Project/externalModules/lwip_v141/src/include/ipv4/lwip/inet_chksum.h new file mode 100644 index 0000000..9737420 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/ipv4/lwip/inet_chksum.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_INET_CHKSUM_H__ +#define __LWIP_INET_CHKSUM_H__ + +#include "lwip/opt.h" + +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" + +/** Swap the bytes in an u16_t: much like htons() for little-endian */ +#ifndef SWAP_BYTES_IN_WORD +#if LWIP_PLATFORM_BYTESWAP && (BYTE_ORDER == LITTLE_ENDIAN) +/* little endian and PLATFORM_BYTESWAP defined */ +#define SWAP_BYTES_IN_WORD(w) LWIP_PLATFORM_HTONS(w) +#else /* LWIP_PLATFORM_BYTESWAP && (BYTE_ORDER == LITTLE_ENDIAN) */ +/* can't use htons on big endian (or PLATFORM_BYTESWAP not defined)... */ +#define SWAP_BYTES_IN_WORD(w) (((w) & 0xff) << 8) | (((w) & 0xff00) >> 8) +#endif /* LWIP_PLATFORM_BYTESWAP && (BYTE_ORDER == LITTLE_ENDIAN)*/ +#endif /* SWAP_BYTES_IN_WORD */ + +/** Split an u32_t in two u16_ts and add them up */ +#ifndef FOLD_U32T +#define FOLD_U32T(u) (((u) >> 16) + ((u) & 0x0000ffffUL)) +#endif + +#if LWIP_CHECKSUM_ON_COPY +/** Function-like macro: same as MEMCPY but returns the checksum of copied data + as u16_t */ +#ifndef LWIP_CHKSUM_COPY +#define LWIP_CHKSUM_COPY(dst, src, len) lwip_chksum_copy(dst, src, len) +#ifndef LWIP_CHKSUM_COPY_ALGORITHM +#define LWIP_CHKSUM_COPY_ALGORITHM 1 +#endif /* LWIP_CHKSUM_COPY_ALGORITHM */ +#endif /* LWIP_CHKSUM_COPY */ +#else /* LWIP_CHECKSUM_ON_COPY */ +#define LWIP_CHKSUM_COPY_ALGORITHM 0 +#endif /* LWIP_CHECKSUM_ON_COPY */ + +#ifdef __cplusplus +extern "C" { +#endif + +u16_t inet_chksum(void *dataptr, u16_t len); +u16_t inet_chksum_pbuf(struct pbuf *p); +u16_t inet_chksum_pseudo(struct pbuf *p, + ip_addr_t *src, ip_addr_t *dest, + u8_t proto, u16_t proto_len); +u16_t inet_chksum_pseudo_partial(struct pbuf *p, + ip_addr_t *src, ip_addr_t *dest, + u8_t proto, u16_t proto_len, u16_t chksum_len); +#if LWIP_CHKSUM_COPY_ALGORITHM +u16_t lwip_chksum_copy(void *dst, const void *src, u16_t len); +#endif /* LWIP_CHKSUM_COPY_ALGORITHM */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_INET_H__ */ + diff --git a/Project/externalModules/lwip_v141/src/include/ipv4/lwip/ip.h b/Project/externalModules/lwip_v141/src/include/ipv4/lwip/ip.h new file mode 100644 index 0000000..b7087af --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/ipv4/lwip/ip.h @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_IP_H__ +#define __LWIP_IP_H__ + +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" +#include "lwip/err.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** Currently, the function ip_output_if_opt() is only used with IGMP */ +#define IP_OPTIONS_SEND LWIP_IGMP + +#define IP_HLEN 20 + +#define IP_PROTO_ICMP 1 +#define IP_PROTO_IGMP 2 +#define IP_PROTO_UDP 17 +#define IP_PROTO_UDPLITE 136 +#define IP_PROTO_TCP 6 + +/* This is passed as the destination address to ip_output_if (not + to ip_output), meaning that an IP header already is constructed + in the pbuf. This is used when TCP retransmits. */ +#ifdef IP_HDRINCL +#undef IP_HDRINCL +#endif /* IP_HDRINCL */ +#define IP_HDRINCL NULL + +#if LWIP_NETIF_HWADDRHINT +#define IP_PCB_ADDRHINT ;u8_t addr_hint +#else +#define IP_PCB_ADDRHINT +#endif /* LWIP_NETIF_HWADDRHINT */ + +/* This is the common part of all PCB types. It needs to be at the + beginning of a PCB type definition. It is located here so that + changes to this common part are made in one location instead of + having to change all PCB structs. */ +#define IP_PCB \ + /* ip addresses in network byte order */ \ + ip_addr_t local_ip; \ + ip_addr_t remote_ip; \ + /* Socket options */ \ + u8_t so_options; \ + /* Type Of Service */ \ + u8_t tos; \ + /* Time To Live */ \ + u8_t ttl \ + /* link layer address resolution hint */ \ + IP_PCB_ADDRHINT + +struct ip_pcb { +/* Common members of all PCB types */ + IP_PCB; +}; + +/* + * Option flags per-socket. These are the same like SO_XXX. + */ +/*#define SOF_DEBUG 0x01U Unimplemented: turn on debugging info recording */ +#define SOF_ACCEPTCONN 0x02U /* socket has had listen() */ +#define SOF_REUSEADDR 0x04U /* allow local address reuse */ +#define SOF_KEEPALIVE 0x08U /* keep connections alive */ +/*#define SOF_DONTROUTE 0x10U Unimplemented: just use interface addresses */ +#define SOF_BROADCAST 0x20U /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */ +/*#define SOF_USELOOPBACK 0x40U Unimplemented: bypass hardware when possible */ +#define SOF_LINGER 0x80U /* linger on close if data present */ +/*#define SOF_OOBINLINE 0x0100U Unimplemented: leave received OOB data in line */ +/*#define SOF_REUSEPORT 0x0200U Unimplemented: allow local address & port reuse */ + +/* These flags are inherited (e.g. from a listen-pcb to a connection-pcb): */ +#define SOF_INHERITED (SOF_REUSEADDR|SOF_KEEPALIVE|SOF_LINGER/*|SOF_DEBUG|SOF_DONTROUTE|SOF_OOBINLINE*/) + + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_hdr { + /* version / header length */ + PACK_STRUCT_FIELD(u8_t _v_hl); + /* type of service */ + PACK_STRUCT_FIELD(u8_t _tos); + /* total length */ + PACK_STRUCT_FIELD(u16_t _len); + /* identification */ + PACK_STRUCT_FIELD(u16_t _id); + /* fragment offset field */ + PACK_STRUCT_FIELD(u16_t _offset); +#define IP_RF 0x8000U /* reserved fragment flag */ +#define IP_DF 0x4000U /* dont fragment flag */ +#define IP_MF 0x2000U /* more fragments flag */ +#define IP_OFFMASK 0x1fffU /* mask for fragmenting bits */ + /* time to live */ + PACK_STRUCT_FIELD(u8_t _ttl); + /* protocol*/ + PACK_STRUCT_FIELD(u8_t _proto); + /* checksum */ + PACK_STRUCT_FIELD(u16_t _chksum); + /* source and destination IP addresses */ + PACK_STRUCT_FIELD(ip_addr_p_t src); + PACK_STRUCT_FIELD(ip_addr_p_t dest); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define IPH_V(hdr) ((hdr)->_v_hl >> 4) +#define IPH_HL(hdr) ((hdr)->_v_hl & 0x0f) +#define IPH_TOS(hdr) ((hdr)->_tos) +#define IPH_LEN(hdr) ((hdr)->_len) +#define IPH_ID(hdr) ((hdr)->_id) +#define IPH_OFFSET(hdr) ((hdr)->_offset) +#define IPH_TTL(hdr) ((hdr)->_ttl) +#define IPH_PROTO(hdr) ((hdr)->_proto) +#define IPH_CHKSUM(hdr) ((hdr)->_chksum) + +#define IPH_VHL_SET(hdr, v, hl) (hdr)->_v_hl = (((v) << 4) | (hl)) +#define IPH_TOS_SET(hdr, tos) (hdr)->_tos = (tos) +#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len) +#define IPH_ID_SET(hdr, id) (hdr)->_id = (id) +#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off) +#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl = (u8_t)(ttl) +#define IPH_PROTO_SET(hdr, proto) (hdr)->_proto = (u8_t)(proto) +#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum) + +/** The interface that provided the packet for the current callback invocation. */ +extern struct netif *current_netif; +/** Header of the input packet currently being processed. */ +extern const struct ip_hdr *current_header; +/** Source IP address of current_header */ +extern ip_addr_t current_iphdr_src; +/** Destination IP address of current_header */ +extern ip_addr_t current_iphdr_dest; + +#define ip_init() /* Compatibility define, not init needed. */ +struct netif *ip_route(ip_addr_t *dest); +err_t ip_input(struct pbuf *p, struct netif *inp); +err_t ip_output(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto); +err_t ip_output_if(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto, + struct netif *netif); +#if LWIP_NETIF_HWADDRHINT +err_t ip_output_hinted(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto, u8_t *addr_hint); +#endif /* LWIP_NETIF_HWADDRHINT */ +#if IP_OPTIONS_SEND +err_t ip_output_if_opt(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options, + u16_t optlen); +#endif /* IP_OPTIONS_SEND */ +/** Get the interface that received the current packet. + * This function must only be called from a receive callback (udp_recv, + * raw_recv, tcp_accept). It will return NULL otherwise. */ +#define ip_current_netif() (current_netif) +/** Get the IP header of the current packet. + * This function must only be called from a receive callback (udp_recv, + * raw_recv, tcp_accept). It will return NULL otherwise. */ +#define ip_current_header() (current_header) +/** Source IP address of current_header */ +#define ip_current_src_addr() (¤t_iphdr_src) +/** Destination IP address of current_header */ +#define ip_current_dest_addr() (¤t_iphdr_dest) + +/** Gets an IP pcb option (SOF_* flags) */ +#define ip_get_option(pcb, opt) ((pcb)->so_options & (opt)) +/** Sets an IP pcb option (SOF_* flags) */ +#define ip_set_option(pcb, opt) ((pcb)->so_options |= (opt)) +/** Resets an IP pcb option (SOF_* flags) */ +#define ip_reset_option(pcb, opt) ((pcb)->so_options &= ~(opt)) + +#if IP_DEBUG +void ip_debug_print(struct pbuf *p); +#else +#define ip_debug_print(p) +#endif /* IP_DEBUG */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_IP_H__ */ + + diff --git a/Project/externalModules/lwip_v141/src/include/ipv4/lwip/ip_addr.h b/Project/externalModules/lwip_v141/src/include/ipv4/lwip/ip_addr.h new file mode 100644 index 0000000..ef69304 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/ipv4/lwip/ip_addr.h @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_IP_ADDR_H__ +#define __LWIP_IP_ADDR_H__ + +#include "lwip/opt.h" +#include "lwip/def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* This is the aligned version of ip_addr_t, + used as local variable, on the stack, etc. */ +struct ip_addr { + u32_t addr; +}; + +/* This is the packed version of ip_addr_t, + used in network headers that are itself packed */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_addr_packed { + PACK_STRUCT_FIELD(u32_t addr); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/** ip_addr_t uses a struct for convenience only, so that the same defines can + * operate both on ip_addr_t as well as on ip_addr_p_t. */ +typedef struct ip_addr ip_addr_t; +typedef struct ip_addr_packed ip_addr_p_t; + +/* + * struct ipaddr2 is used in the definition of the ARP packet format in + * order to support compilers that don't have structure packing. + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_addr2 { + PACK_STRUCT_FIELD(u16_t addrw[2]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/* Forward declaration to not include netif.h */ +struct netif; + +extern const ip_addr_t ip_addr_any; +extern const ip_addr_t ip_addr_broadcast; + +/** IP_ADDR_ can be used as a fixed IP address + * for the wildcard and the broadcast address + */ +#define IP_ADDR_ANY ((ip_addr_t *)&ip_addr_any) +#define IP_ADDR_BROADCAST ((ip_addr_t *)&ip_addr_broadcast) + +/** 255.255.255.255 */ +#define IPADDR_NONE ((u32_t)0xffffffffUL) +/** 127.0.0.1 */ +#define IPADDR_LOOPBACK ((u32_t)0x7f000001UL) +/** 0.0.0.0 */ +#define IPADDR_ANY ((u32_t)0x00000000UL) +/** 255.255.255.255 */ +#define IPADDR_BROADCAST ((u32_t)0xffffffffUL) + +/* Definitions of the bits in an Internet address integer. + + On subnets, host and network parts are found according to + the subnet mask, not these masks. */ +#define IP_CLASSA(a) ((((u32_t)(a)) & 0x80000000UL) == 0) +#define IP_CLASSA_NET 0xff000000 +#define IP_CLASSA_NSHIFT 24 +#define IP_CLASSA_HOST (0xffffffff & ~IP_CLASSA_NET) +#define IP_CLASSA_MAX 128 + +#define IP_CLASSB(a) ((((u32_t)(a)) & 0xc0000000UL) == 0x80000000UL) +#define IP_CLASSB_NET 0xffff0000 +#define IP_CLASSB_NSHIFT 16 +#define IP_CLASSB_HOST (0xffffffff & ~IP_CLASSB_NET) +#define IP_CLASSB_MAX 65536 + +#define IP_CLASSC(a) ((((u32_t)(a)) & 0xe0000000UL) == 0xc0000000UL) +#define IP_CLASSC_NET 0xffffff00 +#define IP_CLASSC_NSHIFT 8 +#define IP_CLASSC_HOST (0xffffffff & ~IP_CLASSC_NET) + +#define IP_CLASSD(a) (((u32_t)(a) & 0xf0000000UL) == 0xe0000000UL) +#define IP_CLASSD_NET 0xf0000000 /* These ones aren't really */ +#define IP_CLASSD_NSHIFT 28 /* net and host fields, but */ +#define IP_CLASSD_HOST 0x0fffffff /* routing needn't know. */ +#define IP_MULTICAST(a) IP_CLASSD(a) + +#define IP_EXPERIMENTAL(a) (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL) +#define IP_BADCLASS(a) (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL) + +#define IP_LOOPBACKNET 127 /* official! */ + + +#if BYTE_ORDER == BIG_ENDIAN +/** Set an IP address given by the four byte-parts */ +#define IP4_ADDR(ipaddr, a,b,c,d) \ + (ipaddr)->addr = ((u32_t)((a) & 0xff) << 24) | \ + ((u32_t)((b) & 0xff) << 16) | \ + ((u32_t)((c) & 0xff) << 8) | \ + (u32_t)((d) & 0xff) +#else +/** Set an IP address given by the four byte-parts. + Little-endian version that prevents the use of htonl. */ +#define IP4_ADDR(ipaddr, a,b,c,d) \ + (ipaddr)->addr = ((u32_t)((d) & 0xff) << 24) | \ + ((u32_t)((c) & 0xff) << 16) | \ + ((u32_t)((b) & 0xff) << 8) | \ + (u32_t)((a) & 0xff) +#endif + +/** MEMCPY-like copying of IP addresses where addresses are known to be + * 16-bit-aligned if the port is correctly configured (so a port could define + * this to copying 2 u16_t's) - no NULL-pointer-checking needed. */ +#ifndef IPADDR2_COPY +#define IPADDR2_COPY(dest, src) SMEMCPY(dest, src, sizeof(ip_addr_t)) +#endif + +/** Copy IP address - faster than ip_addr_set: no NULL check */ +#define ip_addr_copy(dest, src) ((dest).addr = (src).addr) +/** Safely copy one IP address to another (src may be NULL) */ +#define ip_addr_set(dest, src) ((dest)->addr = \ + ((src) == NULL ? 0 : \ + (src)->addr)) +/** Set complete address to zero */ +#define ip_addr_set_zero(ipaddr) ((ipaddr)->addr = 0) +/** Set address to IPADDR_ANY (no need for htonl()) */ +#define ip_addr_set_any(ipaddr) ((ipaddr)->addr = IPADDR_ANY) +/** Set address to loopback address */ +#define ip_addr_set_loopback(ipaddr) ((ipaddr)->addr = PP_HTONL(IPADDR_LOOPBACK)) +/** Safely copy one IP address to another and change byte order + * from host- to network-order. */ +#define ip_addr_set_hton(dest, src) ((dest)->addr = \ + ((src) == NULL ? 0:\ + htonl((src)->addr))) +/** IPv4 only: set the IP address given as an u32_t */ +#define ip4_addr_set_u32(dest_ipaddr, src_u32) ((dest_ipaddr)->addr = (src_u32)) +/** IPv4 only: get the IP address as an u32_t */ +#define ip4_addr_get_u32(src_ipaddr) ((src_ipaddr)->addr) + +/** Get the network address by combining host address with netmask */ +#define ip_addr_get_network(target, host, netmask) ((target)->addr = ((host)->addr) & ((netmask)->addr)) + +/** + * Determine if two address are on the same network. + * + * @arg addr1 IP address 1 + * @arg addr2 IP address 2 + * @arg mask network identifier mask + * @return !0 if the network identifiers of both address match + */ +#define ip_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \ + (mask)->addr) == \ + ((addr2)->addr & \ + (mask)->addr)) +#define ip_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr) + +#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == IPADDR_ANY) + +#define ip_addr_isbroadcast(ipaddr, netif) ip4_addr_isbroadcast((ipaddr)->addr, (netif)) +u8_t ip4_addr_isbroadcast(u32_t addr, const struct netif *netif); + +#define ip_addr_netmask_valid(netmask) ip4_addr_netmask_valid((netmask)->addr) +u8_t ip4_addr_netmask_valid(u32_t netmask); + +#define ip_addr_ismulticast(addr1) (((addr1)->addr & PP_HTONL(0xf0000000UL)) == PP_HTONL(0xe0000000UL)) + +#define ip_addr_islinklocal(addr1) (((addr1)->addr & PP_HTONL(0xffff0000UL)) == PP_HTONL(0xa9fe0000UL)) + +#define ip_addr_debug_print(debug, ipaddr) \ + LWIP_DEBUGF(debug, ("%"U16_F".%"U16_F".%"U16_F".%"U16_F, \ + ipaddr != NULL ? ip4_addr1_16(ipaddr) : 0, \ + ipaddr != NULL ? ip4_addr2_16(ipaddr) : 0, \ + ipaddr != NULL ? ip4_addr3_16(ipaddr) : 0, \ + ipaddr != NULL ? ip4_addr4_16(ipaddr) : 0)) + +/* Get one byte from the 4-byte address */ +#define ip4_addr1(ipaddr) (((u8_t*)(ipaddr))[0]) +#define ip4_addr2(ipaddr) (((u8_t*)(ipaddr))[1]) +#define ip4_addr3(ipaddr) (((u8_t*)(ipaddr))[2]) +#define ip4_addr4(ipaddr) (((u8_t*)(ipaddr))[3]) +/* These are cast to u16_t, with the intent that they are often arguments + * to printf using the U16_F format from cc.h. */ +#define ip4_addr1_16(ipaddr) ((u16_t)ip4_addr1(ipaddr)) +#define ip4_addr2_16(ipaddr) ((u16_t)ip4_addr2(ipaddr)) +#define ip4_addr3_16(ipaddr) ((u16_t)ip4_addr3(ipaddr)) +#define ip4_addr4_16(ipaddr) ((u16_t)ip4_addr4(ipaddr)) + +/** For backwards compatibility */ +#define ip_ntoa(ipaddr) ipaddr_ntoa(ipaddr) + +u32_t ipaddr_addr(const char *cp); +int ipaddr_aton(const char *cp, ip_addr_t *addr); +/** returns ptr to static buffer; not reentrant! */ +char *ipaddr_ntoa(const ip_addr_t *addr); +char *ipaddr_htoa(const ip_addr_t *addr); +char *ipaddr_ntoa_r(const ip_addr_t *addr, char *buf, int buflen); + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_IP_ADDR_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/ipv4/lwip/ip_frag.h b/Project/externalModules/lwip_v141/src/include/ipv4/lwip/ip_frag.h new file mode 100644 index 0000000..86350cd --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/ipv4/lwip/ip_frag.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Jani Monoses + * + */ + +#ifndef __LWIP_IP_FRAG_H__ +#define __LWIP_IP_FRAG_H__ + +#include "lwip/opt.h" +#include "lwip/err.h" +#include "lwip/pbuf.h" +#include "lwip/netif.h" +#include "lwip/ip_addr.h" +#include "lwip/ip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if IP_REASSEMBLY +/* The IP reassembly timer interval in milliseconds. */ +#define IP_TMR_INTERVAL 1000 + +/* IP reassembly helper struct. + * This is exported because memp needs to know the size. + */ +struct ip_reassdata { + struct ip_reassdata *next; + struct pbuf *p; + struct ip_hdr iphdr; + u16_t datagram_len; + u8_t flags; + u8_t timer; +}; + +void ip_reass_init(void); +void ip_reass_tmr(void); +struct pbuf * ip_reass(struct pbuf *p); +#endif /* IP_REASSEMBLY */ + +#if IP_FRAG +#if !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF +/** A custom pbuf that holds a reference to another pbuf, which is freed + * when this custom pbuf is freed. This is used to create a custom PBUF_REF + * that points into the original pbuf. */ +struct pbuf_custom_ref { + /** 'base class' */ + struct pbuf_custom pc; + /** pointer to the original pbuf that is referenced */ + struct pbuf *original; +}; +#endif /* !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF */ + +err_t ip_frag(struct pbuf *p, struct netif *netif, ip_addr_t *dest); +#endif /* IP_FRAG */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_IP_FRAG_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/ipv6/lwip/icmp.h b/Project/externalModules/lwip_v141/src/include/ipv6/lwip/icmp.h new file mode 100644 index 0000000..cbdf07a --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/ipv6/lwip/icmp.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_ICMP_H__ +#define __LWIP_ICMP_H__ + +#include "lwip/opt.h" + +#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ICMP6_DUR 1 +#define ICMP6_TE 3 +#define ICMP6_ECHO 128 /* echo */ +#define ICMP6_ER 129 /* echo reply */ + + +enum icmp_dur_type { + ICMP_DUR_NET = 0, /* net unreachable */ + ICMP_DUR_HOST = 1, /* host unreachable */ + ICMP_DUR_PROTO = 2, /* protocol unreachable */ + ICMP_DUR_PORT = 3, /* port unreachable */ + ICMP_DUR_FRAG = 4, /* fragmentation needed and DF set */ + ICMP_DUR_SR = 5 /* source route failed */ +}; + +enum icmp_te_type { + ICMP_TE_TTL = 0, /* time to live exceeded in transit */ + ICMP_TE_FRAG = 1 /* fragment reassembly time exceeded */ +}; + +void icmp_input(struct pbuf *p, struct netif *inp); + +void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t); +void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t); + +struct icmp_echo_hdr { + u8_t type; + u8_t icode; + u16_t chksum; + u16_t id; + u16_t seqno; +}; + +struct icmp_dur_hdr { + u8_t type; + u8_t icode; + u16_t chksum; + u32_t unused; +}; + +struct icmp_te_hdr { + u8_t type; + u8_t icode; + u16_t chksum; + u32_t unused; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_ICMP */ + +#endif /* __LWIP_ICMP_H__ */ + diff --git a/Project/externalModules/lwip_v141/src/include/ipv6/lwip/inet.h b/Project/externalModules/lwip_v141/src/include/ipv6/lwip/inet.h new file mode 100644 index 0000000..216ebd7 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/ipv6/lwip/inet.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_INET_H__ +#define __LWIP_INET_H__ + +#include "lwip/opt.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +u16_t inet_chksum(void *data, u16_t len); +u16_t inet_chksum_pbuf(struct pbuf *p); +u16_t inet_chksum_pseudo(struct pbuf *p, + struct ip_addr *src, struct ip_addr *dest, + u8_t proto, u32_t proto_len); + +u32_t inet_addr(const char *cp); +s8_t inet_aton(const char *cp, struct in_addr *addr); + +#ifndef _MACHINE_ENDIAN_H_ +#ifndef _NETINET_IN_H +#ifndef _LINUX_BYTEORDER_GENERIC_H +u16_t htons(u16_t n); +u16_t ntohs(u16_t n); +u32_t htonl(u32_t n); +u32_t ntohl(u32_t n); +#endif /* _LINUX_BYTEORDER_GENERIC_H */ +#endif /* _NETINET_IN_H */ +#endif /* _MACHINE_ENDIAN_H_ */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_INET_H__ */ + diff --git a/Project/externalModules/lwip_v141/src/include/ipv6/lwip/ip.h b/Project/externalModules/lwip_v141/src/include/ipv6/lwip/ip.h new file mode 100644 index 0000000..3bf37ab --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/ipv6/lwip/ip.h @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_IP_H__ +#define __LWIP_IP_H__ + +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" + +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define IP_HLEN 40 + +#define IP_PROTO_ICMP 58 +#define IP_PROTO_UDP 17 +#define IP_PROTO_UDPLITE 136 +#define IP_PROTO_TCP 6 + +/* This is passed as the destination address to ip_output_if (not + to ip_output), meaning that an IP header already is constructed + in the pbuf. This is used when TCP retransmits. */ +#ifdef IP_HDRINCL +#undef IP_HDRINCL +#endif /* IP_HDRINCL */ +#define IP_HDRINCL NULL + +#if LWIP_NETIF_HWADDRHINT +#define IP_PCB_ADDRHINT ;u8_t addr_hint +#else +#define IP_PCB_ADDRHINT +#endif /* LWIP_NETIF_HWADDRHINT */ + +/* This is the common part of all PCB types. It needs to be at the + beginning of a PCB type definition. It is located here so that + changes to this common part are made in one location instead of + having to change all PCB structs. */ +#define IP_PCB struct ip_addr local_ip; \ + struct ip_addr remote_ip; \ + /* Socket options */ \ + u16_t so_options; \ + /* Type Of Service */ \ + u8_t tos; \ + /* Time To Live */ \ + u8_t ttl; \ + /* link layer address resolution hint */ \ + IP_PCB_ADDRHINT + + +/* The IPv6 header. */ +struct ip_hdr { +#if BYTE_ORDER == LITTLE_ENDIAN + u8_t tclass1:4, v:4; + u8_t flow1:4, tclass2:4; +#else + u8_t v:4, tclass1:4; + u8_t tclass2:8, flow1:4; +#endif + u16_t flow2; + u16_t len; /* payload length */ + u8_t nexthdr; /* next header */ + u8_t hoplim; /* hop limit (TTL) */ + struct ip_addr src, dest; /* source and destination IP addresses */ +}; + +#define IPH_PROTO(hdr) (iphdr->nexthdr) + +void ip_init(void); + +#include "lwip/netif.h" + +struct netif *ip_route(struct ip_addr *dest); + +void ip_input(struct pbuf *p, struct netif *inp); + +/* source and destination addresses in network byte order, please */ +err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t proto); + +err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t proto, + struct netif *netif); + +#define ip_current_netif() NULL +#define ip_current_header() NULL + +#if IP_DEBUG +void ip_debug_print(struct pbuf *p); +#endif /* IP_DEBUG */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_IP_H__ */ + + diff --git a/Project/externalModules/lwip_v141/src/include/ipv6/lwip/ip_addr.h b/Project/externalModules/lwip_v141/src/include/ipv6/lwip/ip_addr.h new file mode 100644 index 0000000..85971c9 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/ipv6/lwip/ip_addr.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_IP_ADDR_H__ +#define __LWIP_IP_ADDR_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define IP_ADDR_ANY 0 + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN + struct ip_addr { + PACK_STRUCT_FIELD(u32_t addr[4]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/* + * struct ipaddr2 is used in the definition of the ARP packet format in + * order to support compilers that don't have structure packing. + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_addr2 { + PACK_STRUCT_FIELD(u16_t addrw[2]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define IP6_ADDR(ipaddr, a,b,c,d,e,f,g,h) do { (ipaddr)->addr[0] = htonl((u32_t)((a & 0xffff) << 16) | (b & 0xffff)); \ + (ipaddr)->addr[1] = htonl(((c & 0xffff) << 16) | (d & 0xffff)); \ + (ipaddr)->addr[2] = htonl(((e & 0xffff) << 16) | (f & 0xffff)); \ + (ipaddr)->addr[3] = htonl(((g & 0xffff) << 16) | (h & 0xffff)); } while(0) + +u8_t ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2, + struct ip_addr *mask); +u8_t ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2); +void ip_addr_set(struct ip_addr *dest, struct ip_addr *src); +u8_t ip_addr_isany(struct ip_addr *addr); + +#define ip_addr_debug_print(debug, ipaddr) \ + LWIP_DEBUGF(debug, ("%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F"\n", \ + (ntohl(ipaddr->addr[0]) >> 16) & 0xffff, \ + ntohl(ipaddr->addr[0]) & 0xffff, \ + (ntohl(ipaddr->addr[1]) >> 16) & 0xffff, \ + ntohl(ipaddr->addr[1]) & 0xffff, \ + (ntohl(ipaddr->addr[2]) >> 16) & 0xffff, \ + ntohl(ipaddr->addr[2]) & 0xffff, \ + (ntohl(ipaddr->addr[3]) >> 16) & 0xffff, \ + ntohl(ipaddr->addr[3]) & 0xffff)); + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_IP_ADDR_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/api.h b/Project/externalModules/lwip_v141/src/include/lwip/api.h new file mode 100644 index 0000000..f7cc52a --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/api.h @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_API_H__ +#define __LWIP_API_H__ + +#include "lwip/opt.h" + +#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ + +#include /* for size_t */ + +#include "lwip/netbuf.h" +#include "lwip/sys.h" +#include "lwip/ip_addr.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Throughout this file, IP addresses and port numbers are expected to be in + * the same byte order as in the corresponding pcb. + */ + +/* Flags for netconn_write (u8_t) */ +#define NETCONN_NOFLAG 0x00 +#define NETCONN_NOCOPY 0x00 /* Only for source code compatibility */ +#define NETCONN_COPY 0x01 +#define NETCONN_MORE 0x02 +#define NETCONN_DONTBLOCK 0x04 + +/* Flags for struct netconn.flags (u8_t) */ +/** TCP: when data passed to netconn_write doesn't fit into the send buffer, + this temporarily stores whether to wake up the original application task + if data couldn't be sent in the first try. */ +#define NETCONN_FLAG_WRITE_DELAYED 0x01 +/** Should this netconn avoid blocking? */ +#define NETCONN_FLAG_NON_BLOCKING 0x02 +/** Was the last connect action a non-blocking one? */ +#define NETCONN_FLAG_IN_NONBLOCKING_CONNECT 0x04 +/** If this is set, a TCP netconn must call netconn_recved() to update + the TCP receive window (done automatically if not set). */ +#define NETCONN_FLAG_NO_AUTO_RECVED 0x08 +/** If a nonblocking write has been rejected before, poll_tcp needs to + check if the netconn is writable again */ +#define NETCONN_FLAG_CHECK_WRITESPACE 0x10 + + +/* Helpers to process several netconn_types by the same code */ +#define NETCONNTYPE_GROUP(t) (t&0xF0) +#define NETCONNTYPE_DATAGRAM(t) (t&0xE0) + +/** Protocol family and type of the netconn */ +enum netconn_type { + NETCONN_INVALID = 0, + /* NETCONN_TCP Group */ + NETCONN_TCP = 0x10, + /* NETCONN_UDP Group */ + NETCONN_UDP = 0x20, + NETCONN_UDPLITE = 0x21, + NETCONN_UDPNOCHKSUM= 0x22, + /* NETCONN_RAW Group */ + NETCONN_RAW = 0x40 +}; + +/** Current state of the netconn. Non-TCP netconns are always + * in state NETCONN_NONE! */ +enum netconn_state { + NETCONN_NONE, + NETCONN_WRITE, + NETCONN_LISTEN, + NETCONN_CONNECT, + NETCONN_CLOSE +}; + +/** Use to inform the callback function about changes */ +enum netconn_evt { + NETCONN_EVT_RCVPLUS, + NETCONN_EVT_RCVMINUS, + NETCONN_EVT_SENDPLUS, + NETCONN_EVT_SENDMINUS, + NETCONN_EVT_ERROR +}; + +#if LWIP_IGMP +/** Used for netconn_join_leave_group() */ +enum netconn_igmp { + NETCONN_JOIN, + NETCONN_LEAVE +}; +#endif /* LWIP_IGMP */ + +/* forward-declare some structs to avoid to include their headers */ +struct ip_pcb; +struct tcp_pcb; +struct udp_pcb; +struct raw_pcb; +struct netconn; +struct api_msg_msg; + +/** A callback prototype to inform about events for a netconn */ +typedef void (* netconn_callback)(struct netconn *, enum netconn_evt, u16_t len); + +/** A netconn descriptor */ +struct netconn { + /** type of the netconn (TCP, UDP or RAW) */ + enum netconn_type type; + /** current state of the netconn */ + enum netconn_state state; + /** the lwIP internal protocol control block */ + union { + struct ip_pcb *ip; + struct tcp_pcb *tcp; + struct udp_pcb *udp; + struct raw_pcb *raw; + } pcb; + /** the last error this netconn had */ + err_t last_err; + /** sem that is used to synchroneously execute functions in the core context */ + sys_sem_t op_completed; + /** mbox where received packets are stored until they are fetched + by the netconn application thread (can grow quite big) */ + sys_mbox_t recvmbox; +#if LWIP_TCP + /** mbox where new connections are stored until processed + by the application thread */ + sys_mbox_t acceptmbox; +#endif /* LWIP_TCP */ + /** only used for socket layer */ +#if LWIP_SOCKET + int socket; +#endif /* LWIP_SOCKET */ +#if LWIP_SO_SNDTIMEO + /** timeout to wait for sending data (which means enqueueing data for sending + in internal buffers) */ + s32_t send_timeout; +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVTIMEO + /** timeout to wait for new data to be received + (or connections to arrive for listening netconns) */ + int recv_timeout; +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF + /** maximum amount of bytes queued in recvmbox + not used for TCP: adjust TCP_WND instead! */ + int recv_bufsize; + /** number of bytes currently in recvmbox to be received, + tested against recv_bufsize to limit bytes on recvmbox + for UDP and RAW, used for FIONREAD */ + s16_t recv_avail; +#endif /* LWIP_SO_RCVBUF */ + /** flags holding more netconn-internal state, see NETCONN_FLAG_* defines */ + u8_t flags; +#if LWIP_TCP + /** TCP: when data passed to netconn_write doesn't fit into the send buffer, + this temporarily stores how much is already sent. */ + size_t write_offset; + /** TCP: when data passed to netconn_write doesn't fit into the send buffer, + this temporarily stores the message. + Also used during connect and close. */ + struct api_msg_msg *current_msg; +#endif /* LWIP_TCP */ + /** A callback function that is informed about events for this netconn */ + netconn_callback callback; +}; + +/** Register an Network connection event */ +#define API_EVENT(c,e,l) if (c->callback) { \ + (*c->callback)(c, e, l); \ + } + +/** Set conn->last_err to err but don't overwrite fatal errors */ +#define NETCONN_SET_SAFE_ERR(conn, err) do { \ + SYS_ARCH_DECL_PROTECT(lev); \ + SYS_ARCH_PROTECT(lev); \ + if (!ERR_IS_FATAL((conn)->last_err)) { \ + (conn)->last_err = err; \ + } \ + SYS_ARCH_UNPROTECT(lev); \ +} while(0); + +/* Network connection functions: */ +#define netconn_new(t) netconn_new_with_proto_and_callback(t, 0, NULL) +#define netconn_new_with_callback(t, c) netconn_new_with_proto_and_callback(t, 0, c) +struct +netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto, + netconn_callback callback); +err_t netconn_delete(struct netconn *conn); +/** Get the type of a netconn (as enum netconn_type). */ +#define netconn_type(conn) (conn->type) + +err_t netconn_getaddr(struct netconn *conn, ip_addr_t *addr, + u16_t *port, u8_t local); +#define netconn_peer(c,i,p) netconn_getaddr(c,i,p,0) +#define netconn_addr(c,i,p) netconn_getaddr(c,i,p,1) + +err_t netconn_bind(struct netconn *conn, ip_addr_t *addr, u16_t port); +err_t netconn_connect(struct netconn *conn, ip_addr_t *addr, u16_t port); +err_t netconn_disconnect (struct netconn *conn); +err_t netconn_listen_with_backlog(struct netconn *conn, u8_t backlog); +#define netconn_listen(conn) netconn_listen_with_backlog(conn, TCP_DEFAULT_LISTEN_BACKLOG) +err_t netconn_accept(struct netconn *conn, struct netconn **new_conn); +err_t netconn_recv(struct netconn *conn, struct netbuf **new_buf); +err_t netconn_recv_tcp_pbuf(struct netconn *conn, struct pbuf **new_buf); +void netconn_recved(struct netconn *conn, u32_t length); +err_t netconn_sendto(struct netconn *conn, struct netbuf *buf, + ip_addr_t *addr, u16_t port); +err_t netconn_send(struct netconn *conn, struct netbuf *buf); +err_t netconn_write_partly(struct netconn *conn, const void *dataptr, size_t size, + u8_t apiflags, size_t *bytes_written); +#define netconn_write(conn, dataptr, size, apiflags) \ + netconn_write_partly(conn, dataptr, size, apiflags, NULL) +err_t netconn_close(struct netconn *conn); +err_t netconn_shutdown(struct netconn *conn, u8_t shut_rx, u8_t shut_tx); + +#if LWIP_IGMP +err_t netconn_join_leave_group(struct netconn *conn, ip_addr_t *multiaddr, + ip_addr_t *netif_addr, enum netconn_igmp join_or_leave); +#endif /* LWIP_IGMP */ +#if LWIP_DNS +err_t netconn_gethostbyname(const char *name, ip_addr_t *addr); +#endif /* LWIP_DNS */ + +#define netconn_err(conn) ((conn)->last_err) +#define netconn_recv_bufsize(conn) ((conn)->recv_bufsize) + +/** Set the blocking status of netconn calls (@todo: write/send is missing) */ +#define netconn_set_nonblocking(conn, val) do { if(val) { \ + (conn)->flags |= NETCONN_FLAG_NON_BLOCKING; \ +} else { \ + (conn)->flags &= ~ NETCONN_FLAG_NON_BLOCKING; }} while(0) +/** Get the blocking status of netconn calls (@todo: write/send is missing) */ +#define netconn_is_nonblocking(conn) (((conn)->flags & NETCONN_FLAG_NON_BLOCKING) != 0) + +/** TCP: Set the no-auto-recved status of netconn calls (see NETCONN_FLAG_NO_AUTO_RECVED) */ +#define netconn_set_noautorecved(conn, val) do { if(val) { \ + (conn)->flags |= NETCONN_FLAG_NO_AUTO_RECVED; \ +} else { \ + (conn)->flags &= ~ NETCONN_FLAG_NO_AUTO_RECVED; }} while(0) +/** TCP: Get the no-auto-recved status of netconn calls (see NETCONN_FLAG_NO_AUTO_RECVED) */ +#define netconn_get_noautorecved(conn) (((conn)->flags & NETCONN_FLAG_NO_AUTO_RECVED) != 0) + +#if LWIP_SO_SNDTIMEO +/** Set the send timeout in milliseconds */ +#define netconn_set_sendtimeout(conn, timeout) ((conn)->send_timeout = (timeout)) +/** Get the send timeout in milliseconds */ +#define netconn_get_sendtimeout(conn) ((conn)->send_timeout) +#endif /* LWIP_SO_SNDTIMEO */ +#if LWIP_SO_RCVTIMEO +/** Set the receive timeout in milliseconds */ +#define netconn_set_recvtimeout(conn, timeout) ((conn)->recv_timeout = (timeout)) +/** Get the receive timeout in milliseconds */ +#define netconn_get_recvtimeout(conn) ((conn)->recv_timeout) +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF +/** Set the receive buffer in bytes */ +#define netconn_set_recvbufsize(conn, recvbufsize) ((conn)->recv_bufsize = (recvbufsize)) +/** Get the receive buffer in bytes */ +#define netconn_get_recvbufsize(conn) ((conn)->recv_bufsize) +#endif /* LWIP_SO_RCVBUF*/ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_NETCONN */ + +#endif /* __LWIP_API_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/api_msg.h b/Project/externalModules/lwip_v141/src/include/lwip/api_msg.h new file mode 100644 index 0000000..318477f --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/api_msg.h @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_API_MSG_H__ +#define __LWIP_API_MSG_H__ + +#include "lwip/opt.h" + +#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ + +#include /* for size_t */ + +#include "lwip/ip_addr.h" +#include "lwip/err.h" +#include "lwip/sys.h" +#include "lwip/igmp.h" +#include "lwip/api.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* For the netconn API, these values are use as a bitmask! */ +#define NETCONN_SHUT_RD 1 +#define NETCONN_SHUT_WR 2 +#define NETCONN_SHUT_RDWR (NETCONN_SHUT_RD | NETCONN_SHUT_WR) + +/* IP addresses and port numbers are expected to be in + * the same byte order as in the corresponding pcb. + */ +/** This struct includes everything that is necessary to execute a function + for a netconn in another thread context (mainly used to process netconns + in the tcpip_thread context to be thread safe). */ +struct api_msg_msg { + /** The netconn which to process - always needed: it includes the semaphore + which is used to block the application thread until the function finished. */ + struct netconn *conn; + /** The return value of the function executed in tcpip_thread. */ + err_t err; + /** Depending on the executed function, one of these union members is used */ + union { + /** used for do_send */ + struct netbuf *b; + /** used for do_newconn */ + struct { + u8_t proto; + } n; + /** used for do_bind and do_connect */ + struct { + ip_addr_t *ipaddr; + u16_t port; + } bc; + /** used for do_getaddr */ + struct { + ip_addr_t *ipaddr; + u16_t *port; + u8_t local; + } ad; + /** used for do_write */ + struct { + const void *dataptr; + size_t len; + u8_t apiflags; +#if LWIP_SO_SNDTIMEO + u32_t time_started; +#endif /* LWIP_SO_SNDTIMEO */ + } w; + /** used for do_recv */ + struct { + u32_t len; + } r; + /** used for do_close (/shutdown) */ + struct { + u8_t shut; + } sd; +#if LWIP_IGMP + /** used for do_join_leave_group */ + struct { + ip_addr_t *multiaddr; + ip_addr_t *netif_addr; + enum netconn_igmp join_or_leave; + } jl; +#endif /* LWIP_IGMP */ +#if TCP_LISTEN_BACKLOG + struct { + u8_t backlog; + } lb; +#endif /* TCP_LISTEN_BACKLOG */ + } msg; +}; + +/** This struct contains a function to execute in another thread context and + a struct api_msg_msg that serves as an argument for this function. + This is passed to tcpip_apimsg to execute functions in tcpip_thread context. */ +struct api_msg { + /** function to execute in tcpip_thread context */ + void (* function)(struct api_msg_msg *msg); + /** arguments for this function */ + struct api_msg_msg msg; +}; + +#if LWIP_DNS +/** As do_gethostbyname requires more arguments but doesn't require a netconn, + it has its own struct (to avoid struct api_msg getting bigger than necessary). + do_gethostbyname must be called using tcpip_callback instead of tcpip_apimsg + (see netconn_gethostbyname). */ +struct dns_api_msg { + /** Hostname to query or dotted IP address string */ + const char *name; + /** Rhe resolved address is stored here */ + ip_addr_t *addr; + /** This semaphore is posted when the name is resolved, the application thread + should wait on it. */ + sys_sem_t *sem; + /** Errors are given back here */ + err_t *err; +}; +#endif /* LWIP_DNS */ + +void do_newconn ( struct api_msg_msg *msg); +void do_delconn ( struct api_msg_msg *msg); +void do_bind ( struct api_msg_msg *msg); +void do_connect ( struct api_msg_msg *msg); +void do_disconnect ( struct api_msg_msg *msg); +void do_listen ( struct api_msg_msg *msg); +void do_send ( struct api_msg_msg *msg); +void do_recv ( struct api_msg_msg *msg); +void do_write ( struct api_msg_msg *msg); +void do_getaddr ( struct api_msg_msg *msg); +void do_close ( struct api_msg_msg *msg); +void do_shutdown ( struct api_msg_msg *msg); +#if LWIP_IGMP +void do_join_leave_group( struct api_msg_msg *msg); +#endif /* LWIP_IGMP */ + +#if LWIP_DNS +void do_gethostbyname(void *arg); +#endif /* LWIP_DNS */ + +struct netconn* netconn_alloc(enum netconn_type t, netconn_callback callback); +void netconn_free(struct netconn *conn); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_NETCONN */ + +#endif /* __LWIP_API_MSG_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/arch.h b/Project/externalModules/lwip_v141/src/include/lwip/arch.h new file mode 100644 index 0000000..919a6cf --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/arch.h @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_ARCH_H__ +#define __LWIP_ARCH_H__ + +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 1234 +#endif + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 4321 +#endif + +#include "arch/cc.h" + +/** Temporary: define format string for size_t if not defined in cc.h */ +#ifndef SZT_F +#define SZT_F U32_F +#endif /* SZT_F */ +/** Temporary upgrade helper: define format string for u8_t as hex if not + defined in cc.h */ +#ifndef X8_F +#define X8_F "02x" +#endif /* X8_F */ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef PACK_STRUCT_BEGIN +#define PACK_STRUCT_BEGIN +#endif /* PACK_STRUCT_BEGIN */ + +#ifndef PACK_STRUCT_END +#define PACK_STRUCT_END +#endif /* PACK_STRUCT_END */ + +#ifndef PACK_STRUCT_FIELD +#define PACK_STRUCT_FIELD(x) x +#endif /* PACK_STRUCT_FIELD */ + + +#ifndef LWIP_UNUSED_ARG +#define LWIP_UNUSED_ARG(x) (void)x +#endif /* LWIP_UNUSED_ARG */ + + +#ifdef LWIP_PROVIDE_ERRNO + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Arg list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + +#ifndef errno +extern int errno; +#endif + +#endif /* LWIP_PROVIDE_ERRNO */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_ARCH_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/debug.h b/Project/externalModules/lwip_v141/src/include/lwip/debug.h new file mode 100644 index 0000000..7c4143a --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/debug.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_DEBUG_H__ +#define __LWIP_DEBUG_H__ + +#include "lwip/arch.h" +#include "lwip/opt.h" + +/** lower two bits indicate debug level + * - 0 all + * - 1 warning + * - 2 serious + * - 3 severe + */ +#define LWIP_DBG_LEVEL_ALL 0x00 +#define LWIP_DBG_LEVEL_OFF LWIP_DBG_LEVEL_ALL /* compatibility define only */ +#define LWIP_DBG_LEVEL_WARNING 0x01 /* bad checksums, dropped packets, ... */ +#define LWIP_DBG_LEVEL_SERIOUS 0x02 /* memory allocation failures, ... */ +#define LWIP_DBG_LEVEL_SEVERE 0x03 +#define LWIP_DBG_MASK_LEVEL 0x03 + +/** flag for LWIP_DEBUGF to enable that debug message */ +#define LWIP_DBG_ON 0x80U +/** flag for LWIP_DEBUGF to disable that debug message */ +#define LWIP_DBG_OFF 0x00U + +/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */ +#define LWIP_DBG_TRACE 0x40U +/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */ +#define LWIP_DBG_STATE 0x20U +/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */ +#define LWIP_DBG_FRESH 0x10U +/** flag for LWIP_DEBUGF to halt after printing this debug message */ +#define LWIP_DBG_HALT 0x08U + +#ifndef LWIP_NOASSERT +#define LWIP_ASSERT(message, assertion) do { if(!(assertion)) \ + LWIP_PLATFORM_ASSERT(message); } while(0) +#else /* LWIP_NOASSERT */ +#define LWIP_ASSERT(message, assertion) +#endif /* LWIP_NOASSERT */ + +/** if "expression" isn't true, then print "message" and execute "handler" expression */ +#ifndef LWIP_ERROR +#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \ + LWIP_PLATFORM_ASSERT(message); handler;}} while(0) +#endif /* LWIP_ERROR */ + +#ifdef LWIP_DEBUG +/** print debug message only if debug message type is enabled... + * AND is of correct type AND is at least LWIP_DBG_LEVEL + */ +#define LWIP_DEBUGF(debug, message) do { \ + if ( \ + ((debug) & LWIP_DBG_ON) && \ + ((debug) & LWIP_DBG_TYPES_ON) && \ + ((s16_t)((debug) & LWIP_DBG_MASK_LEVEL) >= LWIP_DBG_MIN_LEVEL)) { \ + LWIP_PLATFORM_DIAG(message); \ + if ((debug) & LWIP_DBG_HALT) { \ + while(1); \ + } \ + } \ + } while(0) + +#else /* LWIP_DEBUG */ +#define LWIP_DEBUGF(debug, message) +#endif /* LWIP_DEBUG */ + +#endif /* __LWIP_DEBUG_H__ */ + diff --git a/Project/externalModules/lwip_v141/src/include/lwip/def.h b/Project/externalModules/lwip_v141/src/include/lwip/def.h new file mode 100644 index 0000000..93b7ca9 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/def.h @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_DEF_H__ +#define __LWIP_DEF_H__ + +/* arch.h might define NULL already */ +#include "lwip/arch.h" +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define LWIP_MAX(x , y) (((x) > (y)) ? (x) : (y)) +#define LWIP_MIN(x , y) (((x) < (y)) ? (x) : (y)) + +#ifndef NULL +#define NULL ((void *)0) +#endif + +/* Endianess-optimized shifting of two u8_t to create one u16_t */ +#if BYTE_ORDER == LITTLE_ENDIAN +#define LWIP_MAKE_U16(a, b) ((a << 8) | b) +#else +#define LWIP_MAKE_U16(a, b) ((b << 8) | a) +#endif + +#ifndef LWIP_PLATFORM_BYTESWAP +#define LWIP_PLATFORM_BYTESWAP 0 +#endif + +#ifndef LWIP_PREFIX_BYTEORDER_FUNCS +/* workaround for naming collisions on some platforms */ + +#ifdef htons +#undef htons +#endif /* htons */ +#ifdef htonl +#undef htonl +#endif /* htonl */ +#ifdef ntohs +#undef ntohs +#endif /* ntohs */ +#ifdef ntohl +#undef ntohl +#endif /* ntohl */ + +#define htons(x) lwip_htons(x) +#define ntohs(x) lwip_ntohs(x) +#define htonl(x) lwip_htonl(x) +#define ntohl(x) lwip_ntohl(x) +#endif /* LWIP_PREFIX_BYTEORDER_FUNCS */ + +#if BYTE_ORDER == BIG_ENDIAN +#define lwip_htons(x) (x) +#define lwip_ntohs(x) (x) +#define lwip_htonl(x) (x) +#define lwip_ntohl(x) (x) +#define PP_HTONS(x) (x) +#define PP_NTOHS(x) (x) +#define PP_HTONL(x) (x) +#define PP_NTOHL(x) (x) +#else /* BYTE_ORDER != BIG_ENDIAN */ +#if LWIP_PLATFORM_BYTESWAP +#define lwip_htons(x) LWIP_PLATFORM_HTONS(x) +#define lwip_ntohs(x) LWIP_PLATFORM_HTONS(x) +#define lwip_htonl(x) LWIP_PLATFORM_HTONL(x) +#define lwip_ntohl(x) LWIP_PLATFORM_HTONL(x) +#else /* LWIP_PLATFORM_BYTESWAP */ +u16_t lwip_htons(u16_t x); +u16_t lwip_ntohs(u16_t x); +u32_t lwip_htonl(u32_t x); +u32_t lwip_ntohl(u32_t x); +#endif /* LWIP_PLATFORM_BYTESWAP */ + +/* These macros should be calculated by the preprocessor and are used + with compile-time constants only (so that there is no little-endian + overhead at runtime). */ +#define PP_HTONS(x) ((((x) & 0xff) << 8) | (((x) & 0xff00) >> 8)) +#define PP_NTOHS(x) PP_HTONS(x) +#define PP_HTONL(x) ((((x) & 0xff) << 24) | \ + (((x) & 0xff00) << 8) | \ + (((x) & 0xff0000UL) >> 8) | \ + (((x) & 0xff000000UL) >> 24)) +#define PP_NTOHL(x) PP_HTONL(x) + +#endif /* BYTE_ORDER == BIG_ENDIAN */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_DEF_H__ */ + diff --git a/Project/externalModules/lwip_v141/src/include/lwip/dhcp.h b/Project/externalModules/lwip_v141/src/include/lwip/dhcp.h new file mode 100644 index 0000000..eca7567 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/dhcp.h @@ -0,0 +1,243 @@ +/** @file + */ + +#ifndef __LWIP_DHCP_H__ +#define __LWIP_DHCP_H__ + +#include "lwip/opt.h" + +#if LWIP_DHCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/netif.h" +#include "lwip/udp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** period (in seconds) of the application calling dhcp_coarse_tmr() */ +#define DHCP_COARSE_TIMER_SECS 60 +/** period (in milliseconds) of the application calling dhcp_coarse_tmr() */ +#define DHCP_COARSE_TIMER_MSECS (DHCP_COARSE_TIMER_SECS * 1000UL) +/** period (in milliseconds) of the application calling dhcp_fine_tmr() */ +#define DHCP_FINE_TIMER_MSECS 500 + +#define DHCP_CHADDR_LEN 16U +#define DHCP_SNAME_LEN 64U +#define DHCP_FILE_LEN 128U + +struct dhcp +{ + /** transaction identifier of last sent request */ + u32_t xid; + /** our connection to the DHCP server */ + struct udp_pcb *pcb; + /** incoming msg */ + struct dhcp_msg *msg_in; + /** current DHCP state machine state */ + u8_t state; + /** retries of current request */ + u8_t tries; +#if LWIP_DHCP_AUTOIP_COOP + u8_t autoip_coop_state; +#endif + u8_t subnet_mask_given; + + struct pbuf *p_out; /* pbuf of outcoming msg */ + struct dhcp_msg *msg_out; /* outgoing msg */ + u16_t options_out_len; /* outgoing msg options length */ + u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */ + u16_t t1_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */ + u16_t t2_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */ + ip_addr_t server_ip_addr; /* dhcp server address that offered this lease */ + ip_addr_t offered_ip_addr; + ip_addr_t offered_sn_mask; + ip_addr_t offered_gw_addr; + + u32_t offered_t0_lease; /* lease period (in seconds) */ + u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */ + u32_t offered_t2_rebind; /* recommended rebind time (usually 66% of lease period) */ + /* @todo: LWIP_DHCP_BOOTP_FILE configuration option? + integrate with possible TFTP-client for booting? */ +#if LWIP_DHCP_BOOTP_FILE + ip_addr_t offered_si_addr; + char boot_file_name[DHCP_FILE_LEN]; +#endif /* LWIP_DHCP_BOOTPFILE */ +}; + +/* MUST be compiled with "pack structs" or equivalent! */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** minimum set of fields of any DHCP message */ +struct dhcp_msg +{ + PACK_STRUCT_FIELD(u8_t op); + PACK_STRUCT_FIELD(u8_t htype); + PACK_STRUCT_FIELD(u8_t hlen); + PACK_STRUCT_FIELD(u8_t hops); + PACK_STRUCT_FIELD(u32_t xid); + PACK_STRUCT_FIELD(u16_t secs); + PACK_STRUCT_FIELD(u16_t flags); + PACK_STRUCT_FIELD(ip_addr_p_t ciaddr); + PACK_STRUCT_FIELD(ip_addr_p_t yiaddr); + PACK_STRUCT_FIELD(ip_addr_p_t siaddr); + PACK_STRUCT_FIELD(ip_addr_p_t giaddr); + PACK_STRUCT_FIELD(u8_t chaddr[DHCP_CHADDR_LEN]); + PACK_STRUCT_FIELD(u8_t sname[DHCP_SNAME_LEN]); + PACK_STRUCT_FIELD(u8_t file[DHCP_FILE_LEN]); + PACK_STRUCT_FIELD(u32_t cookie); +#define DHCP_MIN_OPTIONS_LEN 68U +/** make sure user does not configure this too small */ +#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN)) +# undef DHCP_OPTIONS_LEN +#endif +/** allow this to be configured in lwipopts.h, but not too small */ +#if (!defined(DHCP_OPTIONS_LEN)) +/** set this to be sufficient for your options in outgoing DHCP msgs */ +# define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN +#endif + PACK_STRUCT_FIELD(u8_t options[DHCP_OPTIONS_LEN]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +void dhcp_set_struct(struct netif *netif, struct dhcp *dhcp); +/** Remove a struct dhcp previously set to the netif using dhcp_set_struct() */ +#define dhcp_remove_struct(netif) do { (netif)->dhcp = NULL; } while(0) +void dhcp_cleanup(struct netif *netif); +/** start DHCP configuration */ +err_t dhcp_start(struct netif *netif); +/** enforce early lease renewal (not needed normally)*/ +err_t dhcp_renew(struct netif *netif); +/** release the DHCP lease, usually called before dhcp_stop()*/ +err_t dhcp_release(struct netif *netif); +/** stop DHCP configuration */ +void dhcp_stop(struct netif *netif); +/** inform server of our manual IP address */ +void dhcp_inform(struct netif *netif); +/** Handle a possible change in the network configuration */ +void dhcp_network_changed(struct netif *netif); +err_t dhcp_discover(struct netif *netif); + +/** if enabled, check whether the offered IP address is not in use, using ARP */ +#if DHCP_DOES_ARP_CHECK +void dhcp_arp_reply(struct netif *netif, ip_addr_t *addr); +#endif + +/** to be called every minute */ +void dhcp_coarse_tmr(void); +/** to be called every half second */ +void dhcp_fine_tmr(void); + +/** DHCP message item offsets and length */ +#define DHCP_OP_OFS 0 +#define DHCP_HTYPE_OFS 1 +#define DHCP_HLEN_OFS 2 +#define DHCP_HOPS_OFS 3 +#define DHCP_XID_OFS 4 +#define DHCP_SECS_OFS 8 +#define DHCP_FLAGS_OFS 10 +#define DHCP_CIADDR_OFS 12 +#define DHCP_YIADDR_OFS 16 +#define DHCP_SIADDR_OFS 20 +#define DHCP_GIADDR_OFS 24 +#define DHCP_CHADDR_OFS 28 +#define DHCP_SNAME_OFS 44 +#define DHCP_FILE_OFS 108 +#define DHCP_MSG_LEN 236 + +#define DHCP_COOKIE_OFS DHCP_MSG_LEN +#define DHCP_OPTIONS_OFS (DHCP_MSG_LEN + 4) + +#define DHCP_CLIENT_PORT 68 +#define DHCP_SERVER_PORT 67 + +/** DHCP client states */ +#define DHCP_OFF 0 +#define DHCP_REQUESTING 1 +#define DHCP_INIT 2 +#define DHCP_REBOOTING 3 +#define DHCP_REBINDING 4 +#define DHCP_RENEWING 5 +#define DHCP_SELECTING 6 +#define DHCP_INFORMING 7 +#define DHCP_CHECKING 8 +#define DHCP_PERMANENT 9 +#define DHCP_BOUND 10 +/** not yet implemented #define DHCP_RELEASING 11 */ +#define DHCP_BACKING_OFF 12 + +/** AUTOIP cooperatation flags */ +#define DHCP_AUTOIP_COOP_STATE_OFF 0 +#define DHCP_AUTOIP_COOP_STATE_ON 1 + +#define DHCP_BOOTREQUEST 1 +#define DHCP_BOOTREPLY 2 + +/** DHCP message types */ +#define DHCP_DISCOVER 1 +#define DHCP_OFFER 2 +#define DHCP_REQUEST 3 +#define DHCP_DECLINE 4 +#define DHCP_ACK 5 +#define DHCP_NAK 6 +#define DHCP_RELEASE 7 +#define DHCP_INFORM 8 + +/** DHCP hardware type, currently only ethernet is supported */ +#define DHCP_HTYPE_ETH 1 + +#define DHCP_MAGIC_COOKIE 0x63825363UL + +/* This is a list of options for BOOTP and DHCP, see RFC 2132 for descriptions */ + +/** BootP options */ +#define DHCP_OPTION_PAD 0 +#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */ +#define DHCP_OPTION_ROUTER 3 +#define DHCP_OPTION_DNS_SERVER 6 +#define DHCP_OPTION_HOSTNAME 12 +#define DHCP_OPTION_IP_TTL 23 +#define DHCP_OPTION_MTU 26 +#define DHCP_OPTION_BROADCAST 28 +#define DHCP_OPTION_TCP_TTL 37 +#define DHCP_OPTION_END 255 + +/** DHCP options */ +#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */ +#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */ +#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */ + +#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */ +#define DHCP_OPTION_MESSAGE_TYPE_LEN 1 + +#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */ +#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */ + +#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */ +#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2 + +#define DHCP_OPTION_T1 58 /* T1 renewal time */ +#define DHCP_OPTION_T2 59 /* T2 rebinding time */ +#define DHCP_OPTION_US 60 +#define DHCP_OPTION_CLIENT_ID 61 +#define DHCP_OPTION_TFTP_SERVERNAME 66 +#define DHCP_OPTION_BOOTFILE 67 + +/** possible combinations of overloading the file and sname fields with options */ +#define DHCP_OVERLOAD_NONE 0 +#define DHCP_OVERLOAD_FILE 1 +#define DHCP_OVERLOAD_SNAME 2 +#define DHCP_OVERLOAD_SNAME_FILE 3 + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_DHCP */ + +#endif /*__LWIP_DHCP_H__*/ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/dns.h b/Project/externalModules/lwip_v141/src/include/lwip/dns.h new file mode 100644 index 0000000..b41d23d --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/dns.h @@ -0,0 +1,124 @@ +/** + * lwip DNS resolver header file. + + * Author: Jim Pettinato + * April 2007 + + * ported from uIP resolv.c Copyright (c) 2002-2003, Adam Dunkels. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __LWIP_DNS_H__ +#define __LWIP_DNS_H__ + +#include "lwip/opt.h" + +#if LWIP_DNS /* don't build if not configured for use in lwipopts.h */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** DNS timer period */ +#define DNS_TMR_INTERVAL 1000 + +/** DNS field TYPE used for "Resource Records" */ +#define DNS_RRTYPE_A 1 /* a host address */ +#define DNS_RRTYPE_NS 2 /* an authoritative name server */ +#define DNS_RRTYPE_MD 3 /* a mail destination (Obsolete - use MX) */ +#define DNS_RRTYPE_MF 4 /* a mail forwarder (Obsolete - use MX) */ +#define DNS_RRTYPE_CNAME 5 /* the canonical name for an alias */ +#define DNS_RRTYPE_SOA 6 /* marks the start of a zone of authority */ +#define DNS_RRTYPE_MB 7 /* a mailbox domain name (EXPERIMENTAL) */ +#define DNS_RRTYPE_MG 8 /* a mail group member (EXPERIMENTAL) */ +#define DNS_RRTYPE_MR 9 /* a mail rename domain name (EXPERIMENTAL) */ +#define DNS_RRTYPE_NULL 10 /* a null RR (EXPERIMENTAL) */ +#define DNS_RRTYPE_WKS 11 /* a well known service description */ +#define DNS_RRTYPE_PTR 12 /* a domain name pointer */ +#define DNS_RRTYPE_HINFO 13 /* host information */ +#define DNS_RRTYPE_MINFO 14 /* mailbox or mail list information */ +#define DNS_RRTYPE_MX 15 /* mail exchange */ +#define DNS_RRTYPE_TXT 16 /* text strings */ + +/** DNS field CLASS used for "Resource Records" */ +#define DNS_RRCLASS_IN 1 /* the Internet */ +#define DNS_RRCLASS_CS 2 /* the CSNET class (Obsolete - used only for examples in some obsolete RFCs) */ +#define DNS_RRCLASS_CH 3 /* the CHAOS class */ +#define DNS_RRCLASS_HS 4 /* Hesiod [Dyer 87] */ +#define DNS_RRCLASS_FLUSH 0x800 /* Flush bit */ + +/* The size used for the next line is rather a hack, but it prevents including socket.h in all files + that include memp.h, and that would possibly break portability (since socket.h defines some types + and constants possibly already define by the OS). + Calculation rule: + sizeof(struct addrinfo) + sizeof(struct sockaddr_in) + DNS_MAX_NAME_LENGTH + 1 byte zero-termination */ +#define NETDB_ELEM_SIZE (32 + 16 + DNS_MAX_NAME_LENGTH + 1) + +#if DNS_LOCAL_HOSTLIST +/** struct used for local host-list */ +struct local_hostlist_entry { + /** static hostname */ + const char *name; + /** static host address in network byteorder */ + ip_addr_t addr; + struct local_hostlist_entry *next; +}; +#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC +#ifndef DNS_LOCAL_HOSTLIST_MAX_NAMELEN +#define DNS_LOCAL_HOSTLIST_MAX_NAMELEN DNS_MAX_NAME_LENGTH +#endif +#define LOCALHOSTLIST_ELEM_SIZE ((sizeof(struct local_hostlist_entry) + DNS_LOCAL_HOSTLIST_MAX_NAMELEN + 1)) +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ +#endif /* DNS_LOCAL_HOSTLIST */ + +/** Callback which is invoked when a hostname is found. + * A function of this type must be implemented by the application using the DNS resolver. + * @param name pointer to the name that was looked up. + * @param ipaddr pointer to an ip_addr_t containing the IP address of the hostname, + * or NULL if the name could not be found (or on any other error). + * @param callback_arg a user-specified callback argument passed to dns_gethostbyname +*/ +typedef void (*dns_found_callback)(const char *name, ip_addr_t *ipaddr, void *callback_arg); + +void dns_init(void); +void dns_tmr(void); +void dns_setserver(u8_t numdns, ip_addr_t *dnsserver); +ip_addr_t dns_getserver(u8_t numdns); +err_t dns_gethostbyname(const char *hostname, ip_addr_t *addr, + dns_found_callback found, void *callback_arg); + +#if DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC +int dns_local_removehost(const char *hostname, const ip_addr_t *addr); +err_t dns_local_addhost(const char *hostname, const ip_addr_t *addr); +#endif /* DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_DNS */ + +#endif /* __LWIP_DNS_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/err.h b/Project/externalModules/lwip_v141/src/include/lwip/err.h new file mode 100644 index 0000000..837203d --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/err.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_ERR_H__ +#define __LWIP_ERR_H__ + +#include "lwip/opt.h" +#include "lwip/arch.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** Define LWIP_ERR_T in cc.h if you want to use + * a different type for your platform (must be signed). */ +#ifdef LWIP_ERR_T +typedef LWIP_ERR_T err_t; +#else /* LWIP_ERR_T */ +typedef s8_t err_t; +#endif /* LWIP_ERR_T*/ + +/* Definitions for error constants. */ + +#define ERR_OK 0 /* No error, everything OK. */ +#define ERR_MEM -1 /* Out of memory error. */ +#define ERR_BUF -2 /* Buffer error. */ +#define ERR_TIMEOUT -3 /* Timeout. */ +#define ERR_RTE -4 /* Routing problem. */ +#define ERR_INPROGRESS -5 /* Operation in progress */ +#define ERR_VAL -6 /* Illegal value. */ +#define ERR_WOULDBLOCK -7 /* Operation would block. */ +#define ERR_USE -8 /* Address in use. */ +#define ERR_ISCONN -9 /* Already connected. */ + +#define ERR_IS_FATAL(e) ((e) < ERR_ISCONN) + +#define ERR_ABRT -10 /* Connection aborted. */ +#define ERR_RST -11 /* Connection reset. */ +#define ERR_CLSD -12 /* Connection closed. */ +#define ERR_CONN -13 /* Not connected. */ + +#define ERR_ARG -14 /* Illegal argument. */ + +#define ERR_IF -15 /* Low-level netif error */ + + +#ifdef LWIP_DEBUG +extern const char *lwip_strerr(err_t err); +#else +#define lwip_strerr(x) "" +#endif /* LWIP_DEBUG */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_ERR_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/init.h b/Project/externalModules/lwip_v141/src/include/lwip/init.h new file mode 100644 index 0000000..c9d8300 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/init.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_INIT_H__ +#define __LWIP_INIT_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** X.x.x: Major version of the stack */ +#define LWIP_VERSION_MAJOR 1U +/** x.X.x: Minor version of the stack */ +#define LWIP_VERSION_MINOR 4U +/** x.x.X: Revision of the stack */ +#define LWIP_VERSION_REVISION 1U +/** For release candidates, this is set to 1..254 + * For official releases, this is set to 255 (LWIP_RC_RELEASE) + * For development versions (CVS), this is set to 0 (LWIP_RC_DEVELOPMENT) */ +#define LWIP_VERSION_RC 0U + +/** LWIP_VERSION_RC is set to LWIP_RC_RELEASE for official releases */ +#define LWIP_RC_RELEASE 255U +/** LWIP_VERSION_RC is set to LWIP_RC_DEVELOPMENT for CVS versions */ +#define LWIP_RC_DEVELOPMENT 0U + +#define LWIP_VERSION_IS_RELEASE (LWIP_VERSION_RC == LWIP_RC_RELEASE) +#define LWIP_VERSION_IS_DEVELOPMENT (LWIP_VERSION_RC == LWIP_RC_DEVELOPMENT) +#define LWIP_VERSION_IS_RC ((LWIP_VERSION_RC != LWIP_RC_RELEASE) && (LWIP_VERSION_RC != LWIP_RC_DEVELOPMENT)) + +/** Provides the version of the stack */ +#define LWIP_VERSION (LWIP_VERSION_MAJOR << 24 | LWIP_VERSION_MINOR << 16 | \ + LWIP_VERSION_REVISION << 8 | LWIP_VERSION_RC) + +/* Modules initialization */ +void lwip_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_INIT_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/mem.h b/Project/externalModules/lwip_v141/src/include/lwip/mem.h new file mode 100644 index 0000000..b44313a --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/mem.h @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_MEM_H__ +#define __LWIP_MEM_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if MEM_LIBC_MALLOC + +#include /* for size_t */ + +typedef size_t mem_size_t; +#define MEM_SIZE_F SZT_F + +/* aliases for C library malloc() */ +#define mem_init() +/* in case C library malloc() needs extra protection, + * allow these defines to be overridden. + */ +#ifndef mem_free +#define mem_free chHeapFree +#endif +#ifndef mem_malloc +#define mem_malloc(size) chHeapAlloc(NULL,size) +#endif +#ifndef mem_calloc +#define mem_calloc calloc +#endif +/* Since there is no C library allocation function to shrink memory without + moving it, define this to nothing. */ +#ifndef mem_trim +#define mem_trim(mem, size) (mem) +#endif +#else /* MEM_LIBC_MALLOC */ + +/* MEM_SIZE would have to be aligned, but using 64000 here instead of + * 65535 leaves some room for alignment... + */ +#if MEM_SIZE > 64000L +typedef u32_t mem_size_t; +#define MEM_SIZE_F U32_F +#else +typedef u16_t mem_size_t; +#define MEM_SIZE_F U16_F +#endif /* MEM_SIZE > 64000 */ + +#if MEM_USE_POOLS +/** mem_init is not used when using pools instead of a heap */ +#define mem_init() +/** mem_trim is not used when using pools instead of a heap: + we can't free part of a pool element and don't want to copy the rest */ +#define mem_trim(mem, size) (mem) +#else /* MEM_USE_POOLS */ +/* lwIP alternative malloc */ +void mem_init(void); +void *mem_trim(void *mem, mem_size_t size); +#endif /* MEM_USE_POOLS */ +void *mem_malloc(mem_size_t size); +void *mem_calloc(mem_size_t count, mem_size_t size); +void mem_free(void *mem); +#endif /* MEM_LIBC_MALLOC */ + +/** Calculate memory size for an aligned buffer - returns the next highest + * multiple of MEM_ALIGNMENT (e.g. LWIP_MEM_ALIGN_SIZE(3) and + * LWIP_MEM_ALIGN_SIZE(4) will both yield 4 for MEM_ALIGNMENT == 4). + */ +#ifndef LWIP_MEM_ALIGN_SIZE +#define LWIP_MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1) & ~(MEM_ALIGNMENT-1)) +#endif + +/** Calculate safe memory size for an aligned buffer when using an unaligned + * type as storage. This includes a safety-margin on (MEM_ALIGNMENT - 1) at the + * start (e.g. if buffer is u8_t[] and actual data will be u32_t*) + */ +#ifndef LWIP_MEM_ALIGN_BUFFER +#define LWIP_MEM_ALIGN_BUFFER(size) (((size) + MEM_ALIGNMENT - 1)) +#endif + +/** Align a memory pointer to the alignment defined by MEM_ALIGNMENT + * so that ADDR % MEM_ALIGNMENT == 0 + */ +#ifndef LWIP_MEM_ALIGN +#define LWIP_MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1))) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_MEM_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/memp.h b/Project/externalModules/lwip_v141/src/include/lwip/memp.h new file mode 100644 index 0000000..f375f3e --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/memp.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __LWIP_MEMP_H__ +#define __LWIP_MEMP_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Create the list of all memory pools managed by memp. MEMP_MAX represents a NULL pool at the end */ +typedef enum { +#define LWIP_MEMPOOL(name,num,size,desc) MEMP_##name, +#include "lwip/memp_std.h" + MEMP_MAX +} memp_t; + +#if MEM_USE_POOLS +/* Use a helper type to get the start and end of the user "memory pools" for mem_malloc */ +typedef enum { + /* Get the first (via: + MEMP_POOL_HELPER_START = ((u8_t) 1*MEMP_POOL_A + 0*MEMP_POOL_B + 0*MEMP_POOL_C + 0)*/ + MEMP_POOL_HELPER_FIRST = ((u8_t) +#define LWIP_MEMPOOL(name,num,size,desc) +#define LWIP_MALLOC_MEMPOOL_START 1 +#define LWIP_MALLOC_MEMPOOL(num, size) * MEMP_POOL_##size + 0 +#define LWIP_MALLOC_MEMPOOL_END +#include "lwip/memp_std.h" + ) , + /* Get the last (via: + MEMP_POOL_HELPER_END = ((u8_t) 0 + MEMP_POOL_A*0 + MEMP_POOL_B*0 + MEMP_POOL_C*1) */ + MEMP_POOL_HELPER_LAST = ((u8_t) +#define LWIP_MEMPOOL(name,num,size,desc) +#define LWIP_MALLOC_MEMPOOL_START +#define LWIP_MALLOC_MEMPOOL(num, size) 0 + MEMP_POOL_##size * +#define LWIP_MALLOC_MEMPOOL_END 1 +#include "lwip/memp_std.h" + ) +} memp_pool_helper_t; + +/* The actual start and stop values are here (cast them over) + We use this helper type and these defines so we can avoid using const memp_t values */ +#define MEMP_POOL_FIRST ((memp_t) MEMP_POOL_HELPER_FIRST) +#define MEMP_POOL_LAST ((memp_t) MEMP_POOL_HELPER_LAST) +#endif /* MEM_USE_POOLS */ + +#if MEMP_MEM_MALLOC || MEM_USE_POOLS +extern const u16_t memp_sizes[MEMP_MAX]; +#endif /* MEMP_MEM_MALLOC || MEM_USE_POOLS */ + +#if MEMP_MEM_MALLOC + +#include "mem.h" + +#define memp_init() +#define memp_malloc(type) mem_malloc(memp_sizes[type]) +#define memp_free(type, mem) mem_free(mem) + +#else /* MEMP_MEM_MALLOC */ + +#if MEM_USE_POOLS +/** This structure is used to save the pool one element came from. */ +struct memp_malloc_helper +{ + memp_t poolnr; +}; +#endif /* MEM_USE_POOLS */ + +void memp_init(void); + +#if MEMP_OVERFLOW_CHECK +void *memp_malloc_fn(memp_t type, const char* file, const int line); +#define memp_malloc(t) memp_malloc_fn((t), __FILE__, __LINE__) +#else +void *memp_malloc(memp_t type); +#endif +void memp_free(memp_t type, void *mem); + +void memp_status(void); +#endif /* MEMP_MEM_MALLOC */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_MEMP_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/memp_std.h b/Project/externalModules/lwip_v141/src/include/lwip/memp_std.h new file mode 100644 index 0000000..7c3b6d4 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/memp_std.h @@ -0,0 +1,122 @@ +/* + * SETUP: Make sure we define everything we will need. + * + * We have create three types of pools: + * 1) MEMPOOL - standard pools + * 2) MALLOC_MEMPOOL - to be used by mem_malloc in mem.c + * 3) PBUF_MEMPOOL - a mempool of pbuf's, so include space for the pbuf struct + * + * If the include'r doesn't require any special treatment of each of the types + * above, then will declare #2 & #3 to be just standard mempools. + */ +#ifndef LWIP_MALLOC_MEMPOOL +/* This treats "malloc pools" just like any other pool. + The pools are a little bigger to provide 'size' as the amount of user data. */ +#define LWIP_MALLOC_MEMPOOL(num, size) LWIP_MEMPOOL(POOL_##size, num, (size + sizeof(struct memp_malloc_helper)), "MALLOC_"#size) +#define LWIP_MALLOC_MEMPOOL_START +#define LWIP_MALLOC_MEMPOOL_END +#endif /* LWIP_MALLOC_MEMPOOL */ + +#ifndef LWIP_PBUF_MEMPOOL +/* This treats "pbuf pools" just like any other pool. + * Allocates buffers for a pbuf struct AND a payload size */ +#define LWIP_PBUF_MEMPOOL(name, num, payload, desc) LWIP_MEMPOOL(name, num, (MEMP_ALIGN_SIZE(sizeof(struct pbuf)) + MEMP_ALIGN_SIZE(payload)), desc) +#endif /* LWIP_PBUF_MEMPOOL */ + + +/* + * A list of internal pools used by LWIP. + * + * LWIP_MEMPOOL(pool_name, number_elements, element_size, pool_description) + * creates a pool name MEMP_pool_name. description is used in stats.c + */ +#if LWIP_RAW +LWIP_MEMPOOL(RAW_PCB, MEMP_NUM_RAW_PCB, sizeof(struct raw_pcb), "RAW_PCB") +#endif /* LWIP_RAW */ + +#if LWIP_UDP +LWIP_MEMPOOL(UDP_PCB, MEMP_NUM_UDP_PCB, sizeof(struct udp_pcb), "UDP_PCB") +#endif /* LWIP_UDP */ + +#if LWIP_TCP +LWIP_MEMPOOL(TCP_PCB, MEMP_NUM_TCP_PCB, sizeof(struct tcp_pcb), "TCP_PCB") +LWIP_MEMPOOL(TCP_PCB_LISTEN, MEMP_NUM_TCP_PCB_LISTEN, sizeof(struct tcp_pcb_listen), "TCP_PCB_LISTEN") +LWIP_MEMPOOL(TCP_SEG, MEMP_NUM_TCP_SEG, sizeof(struct tcp_seg), "TCP_SEG") +#endif /* LWIP_TCP */ + +#if IP_REASSEMBLY +LWIP_MEMPOOL(REASSDATA, MEMP_NUM_REASSDATA, sizeof(struct ip_reassdata), "REASSDATA") +#endif /* IP_REASSEMBLY */ +#if IP_FRAG && !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF +LWIP_MEMPOOL(FRAG_PBUF, MEMP_NUM_FRAG_PBUF, sizeof(struct pbuf_custom_ref),"FRAG_PBUF") +#endif /* IP_FRAG && !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF */ + +#if LWIP_NETCONN +LWIP_MEMPOOL(NETBUF, MEMP_NUM_NETBUF, sizeof(struct netbuf), "NETBUF") +LWIP_MEMPOOL(NETCONN, MEMP_NUM_NETCONN, sizeof(struct netconn), "NETCONN") +#endif /* LWIP_NETCONN */ + +#if NO_SYS==0 +LWIP_MEMPOOL(TCPIP_MSG_API, MEMP_NUM_TCPIP_MSG_API, sizeof(struct tcpip_msg), "TCPIP_MSG_API") +#if !LWIP_TCPIP_CORE_LOCKING_INPUT +LWIP_MEMPOOL(TCPIP_MSG_INPKT,MEMP_NUM_TCPIP_MSG_INPKT, sizeof(struct tcpip_msg), "TCPIP_MSG_INPKT") +#endif /* !LWIP_TCPIP_CORE_LOCKING_INPUT */ +#endif /* NO_SYS==0 */ + +#if LWIP_ARP && ARP_QUEUEING +LWIP_MEMPOOL(ARP_QUEUE, MEMP_NUM_ARP_QUEUE, sizeof(struct etharp_q_entry), "ARP_QUEUE") +#endif /* LWIP_ARP && ARP_QUEUEING */ + +#if LWIP_IGMP +LWIP_MEMPOOL(IGMP_GROUP, MEMP_NUM_IGMP_GROUP, sizeof(struct igmp_group), "IGMP_GROUP") +#endif /* LWIP_IGMP */ + +#if (!NO_SYS || (NO_SYS && !NO_SYS_NO_TIMERS)) /* LWIP_TIMERS */ +LWIP_MEMPOOL(SYS_TIMEOUT, MEMP_NUM_SYS_TIMEOUT, sizeof(struct sys_timeo), "SYS_TIMEOUT") +#endif /* LWIP_TIMERS */ + +#if LWIP_SNMP +LWIP_MEMPOOL(SNMP_ROOTNODE, MEMP_NUM_SNMP_ROOTNODE, sizeof(struct mib_list_rootnode), "SNMP_ROOTNODE") +LWIP_MEMPOOL(SNMP_NODE, MEMP_NUM_SNMP_NODE, sizeof(struct mib_list_node), "SNMP_NODE") +LWIP_MEMPOOL(SNMP_VARBIND, MEMP_NUM_SNMP_VARBIND, sizeof(struct snmp_varbind), "SNMP_VARBIND") +LWIP_MEMPOOL(SNMP_VALUE, MEMP_NUM_SNMP_VALUE, SNMP_MAX_VALUE_SIZE, "SNMP_VALUE") +#endif /* LWIP_SNMP */ +#if LWIP_DNS && LWIP_SOCKET +LWIP_MEMPOOL(NETDB, MEMP_NUM_NETDB, NETDB_ELEM_SIZE, "NETDB") +#endif /* LWIP_DNS && LWIP_SOCKET */ +#if LWIP_DNS && DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC +LWIP_MEMPOOL(LOCALHOSTLIST, MEMP_NUM_LOCALHOSTLIST, LOCALHOSTLIST_ELEM_SIZE, "LOCALHOSTLIST") +#endif /* LWIP_DNS && DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ +#if PPP_SUPPORT && PPPOE_SUPPORT +LWIP_MEMPOOL(PPPOE_IF, MEMP_NUM_PPPOE_INTERFACES, sizeof(struct pppoe_softc), "PPPOE_IF") +#endif /* PPP_SUPPORT && PPPOE_SUPPORT */ + +/* + * A list of pools of pbuf's used by LWIP. + * + * LWIP_PBUF_MEMPOOL(pool_name, number_elements, pbuf_payload_size, pool_description) + * creates a pool name MEMP_pool_name. description is used in stats.c + * This allocates enough space for the pbuf struct and a payload. + * (Example: pbuf_payload_size=0 allocates only size for the struct) + */ +LWIP_PBUF_MEMPOOL(PBUF, MEMP_NUM_PBUF, 0, "PBUF_REF/ROM") +LWIP_PBUF_MEMPOOL(PBUF_POOL, PBUF_POOL_SIZE, PBUF_POOL_BUFSIZE, "PBUF_POOL") + + +/* + * Allow for user-defined pools; this must be explicitly set in lwipopts.h + * since the default is to NOT look for lwippools.h + */ +#if MEMP_USE_CUSTOM_POOLS +#include "lwippools.h" +#endif /* MEMP_USE_CUSTOM_POOLS */ + +/* + * REQUIRED CLEANUP: Clear up so we don't get "multiply defined" error later + * (#undef is ignored for something that is not defined) + */ +#undef LWIP_MEMPOOL +#undef LWIP_MALLOC_MEMPOOL +#undef LWIP_MALLOC_MEMPOOL_START +#undef LWIP_MALLOC_MEMPOOL_END +#undef LWIP_PBUF_MEMPOOL diff --git a/Project/externalModules/lwip_v141/src/include/lwip/netbuf.h b/Project/externalModules/lwip_v141/src/include/lwip/netbuf.h new file mode 100644 index 0000000..1f254bd --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/netbuf.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_NETBUF_H__ +#define __LWIP_NETBUF_H__ + +#include "lwip/opt.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** This netbuf has dest-addr/port set */ +#define NETBUF_FLAG_DESTADDR 0x01 +/** This netbuf includes a checksum */ +#define NETBUF_FLAG_CHKSUM 0x02 + +struct netbuf { + struct pbuf *p, *ptr; + ip_addr_t addr; + u16_t port; +#if LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY +#if LWIP_CHECKSUM_ON_COPY + u8_t flags; +#endif /* LWIP_CHECKSUM_ON_COPY */ + u16_t toport_chksum; +#if LWIP_NETBUF_RECVINFO + ip_addr_t toaddr; +#endif /* LWIP_NETBUF_RECVINFO */ +#endif /* LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY */ +}; + +/* Network buffer functions: */ +struct netbuf * netbuf_new (void); +void netbuf_delete (struct netbuf *buf); +void * netbuf_alloc (struct netbuf *buf, u16_t size); +void netbuf_free (struct netbuf *buf); +err_t netbuf_ref (struct netbuf *buf, + const void *dataptr, u16_t size); +void netbuf_chain (struct netbuf *head, + struct netbuf *tail); + +err_t netbuf_data (struct netbuf *buf, + void **dataptr, u16_t *len); +s8_t netbuf_next (struct netbuf *buf); +void netbuf_first (struct netbuf *buf); + + +#define netbuf_copy_partial(buf, dataptr, len, offset) \ + pbuf_copy_partial((buf)->p, (dataptr), (len), (offset)) +#define netbuf_copy(buf,dataptr,len) netbuf_copy_partial(buf, dataptr, len, 0) +#define netbuf_take(buf, dataptr, len) pbuf_take((buf)->p, dataptr, len) +#define netbuf_len(buf) ((buf)->p->tot_len) +#define netbuf_fromaddr(buf) (&((buf)->addr)) +#define netbuf_set_fromaddr(buf, fromaddr) ip_addr_set((&(buf)->addr), fromaddr) +#define netbuf_fromport(buf) ((buf)->port) +#if LWIP_NETBUF_RECVINFO +#define netbuf_destaddr(buf) (&((buf)->toaddr)) +#define netbuf_set_destaddr(buf, destaddr) ip_addr_set((&(buf)->addr), destaddr) +#define netbuf_destport(buf) (((buf)->flags & NETBUF_FLAG_DESTADDR) ? (buf)->toport_chksum : 0) +#endif /* LWIP_NETBUF_RECVINFO */ +#if LWIP_CHECKSUM_ON_COPY +#define netbuf_set_chksum(buf, chksum) do { (buf)->flags = NETBUF_FLAG_CHKSUM; \ + (buf)->toport_chksum = chksum; } while(0) +#endif /* LWIP_CHECKSUM_ON_COPY */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_NETBUF_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/netdb.h b/Project/externalModules/lwip_v141/src/include/lwip/netdb.h new file mode 100644 index 0000000..4b7c07a --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/netdb.h @@ -0,0 +1,124 @@ +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ +#ifndef __LWIP_NETDB_H__ +#define __LWIP_NETDB_H__ + +#include "lwip/opt.h" + +#if LWIP_DNS && LWIP_SOCKET + +#include /* for size_t */ + +#include "lwip/inet.h" +#include "lwip/sockets.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* some rarely used options */ +#ifndef LWIP_DNS_API_DECLARE_H_ERRNO +#define LWIP_DNS_API_DECLARE_H_ERRNO 1 +#endif + +#ifndef LWIP_DNS_API_DEFINE_ERRORS +#define LWIP_DNS_API_DEFINE_ERRORS 1 +#endif + +#ifndef LWIP_DNS_API_DECLARE_STRUCTS +#define LWIP_DNS_API_DECLARE_STRUCTS 1 +#endif + +#if LWIP_DNS_API_DEFINE_ERRORS +/** Errors used by the DNS API functions, h_errno can be one of them */ +#define EAI_NONAME 200 +#define EAI_SERVICE 201 +#define EAI_FAIL 202 +#define EAI_MEMORY 203 + +#define HOST_NOT_FOUND 210 +#define NO_DATA 211 +#define NO_RECOVERY 212 +#define TRY_AGAIN 213 +#endif /* LWIP_DNS_API_DEFINE_ERRORS */ + +#if LWIP_DNS_API_DECLARE_STRUCTS +struct hostent { + char *h_name; /* Official name of the host. */ + char **h_aliases; /* A pointer to an array of pointers to alternative host names, + terminated by a null pointer. */ + int h_addrtype; /* Address type. */ + int h_length; /* The length, in bytes, of the address. */ + char **h_addr_list; /* A pointer to an array of pointers to network addresses (in + network byte order) for the host, terminated by a null pointer. */ +#define h_addr h_addr_list[0] /* for backward compatibility */ +}; + +struct addrinfo { + int ai_flags; /* Input flags. */ + int ai_family; /* Address family of socket. */ + int ai_socktype; /* Socket type. */ + int ai_protocol; /* Protocol of socket. */ + socklen_t ai_addrlen; /* Length of socket address. */ + struct sockaddr *ai_addr; /* Socket address of socket. */ + char *ai_canonname; /* Canonical name of service location. */ + struct addrinfo *ai_next; /* Pointer to next in list. */ +}; +#endif /* LWIP_DNS_API_DECLARE_STRUCTS */ + +#if LWIP_DNS_API_DECLARE_H_ERRNO +/* application accessable error code set by the DNS API functions */ +extern int h_errno; +#endif /* LWIP_DNS_API_DECLARE_H_ERRNO*/ + +struct hostent *lwip_gethostbyname(const char *name); +int lwip_gethostbyname_r(const char *name, struct hostent *ret, char *buf, + size_t buflen, struct hostent **result, int *h_errnop); +void lwip_freeaddrinfo(struct addrinfo *ai); +int lwip_getaddrinfo(const char *nodename, + const char *servname, + const struct addrinfo *hints, + struct addrinfo **res); + +#if LWIP_COMPAT_SOCKETS +#define gethostbyname(name) lwip_gethostbyname(name) +#define gethostbyname_r(name, ret, buf, buflen, result, h_errnop) \ + lwip_gethostbyname_r(name, ret, buf, buflen, result, h_errnop) +#define freeaddrinfo(addrinfo) lwip_freeaddrinfo(addrinfo) +#define getaddrinfo(nodname, servname, hints, res) \ + lwip_getaddrinfo(nodname, servname, hints, res) +#endif /* LWIP_COMPAT_SOCKETS */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_DNS && LWIP_SOCKET */ + +#endif /* __LWIP_NETDB_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/netif.h b/Project/externalModules/lwip_v141/src/include/lwip/netif.h new file mode 100644 index 0000000..d34887c --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/netif.h @@ -0,0 +1,328 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_NETIF_H__ +#define __LWIP_NETIF_H__ + +#include "lwip/opt.h" + +#define ENABLE_LOOPBACK (LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF) + +#include "lwip/err.h" + +#include "lwip/ip_addr.h" + +#include "lwip/def.h" +#include "lwip/pbuf.h" +#if LWIP_DHCP +struct dhcp; +#endif +#if LWIP_AUTOIP +struct autoip; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* Throughout this file, IP addresses are expected to be in + * the same byte order as in IP_PCB. */ + +/** must be the maximum of all used hardware address lengths + across all types of interfaces in use */ +#define NETIF_MAX_HWADDR_LEN 6U + +/** Whether the network interface is 'up'. This is + * a software flag used to control whether this network + * interface is enabled and processes traffic. + * It is set by the startup code (for static IP configuration) or + * by dhcp/autoip when an address has been assigned. + */ +#define NETIF_FLAG_UP 0x01U +/** If set, the netif has broadcast capability. + * Set by the netif driver in its init function. */ +#define NETIF_FLAG_BROADCAST 0x02U +/** If set, the netif is one end of a point-to-point connection. + * Set by the netif driver in its init function. */ +#define NETIF_FLAG_POINTTOPOINT 0x04U +/** If set, the interface is configured using DHCP. + * Set by the DHCP code when starting or stopping DHCP. */ +#define NETIF_FLAG_DHCP 0x08U +/** If set, the interface has an active link + * (set by the network interface driver). + * Either set by the netif driver in its init function (if the link + * is up at that time) or at a later point once the link comes up + * (if link detection is supported by the hardware). */ +#define NETIF_FLAG_LINK_UP 0x10U +/** If set, the netif is an ethernet device using ARP. + * Set by the netif driver in its init function. + * Used to check input packet types and use of DHCP. */ +#define NETIF_FLAG_ETHARP 0x20U +/** If set, the netif is an ethernet device. It might not use + * ARP or TCP/IP if it is used for PPPoE only. + */ +#define NETIF_FLAG_ETHERNET 0x40U +/** If set, the netif has IGMP capability. + * Set by the netif driver in its init function. */ +#define NETIF_FLAG_IGMP 0x80U + +/** Function prototype for netif init functions. Set up flags and output/linkoutput + * callback functions in this function. + * + * @param netif The netif to initialize + */ +typedef err_t (*netif_init_fn)(struct netif *netif); +/** Function prototype for netif->input functions. This function is saved as 'input' + * callback function in the netif struct. Call it when a packet has been received. + * + * @param p The received packet, copied into a pbuf + * @param inp The netif which received the packet + */ +typedef err_t (*netif_input_fn)(struct pbuf *p, struct netif *inp); +/** Function prototype for netif->output functions. Called by lwIP when a packet + * shall be sent. For ethernet netif, set this to 'etharp_output' and set + * 'linkoutput'. + * + * @param netif The netif which shall send a packet + * @param p The packet to send (p->payload points to IP header) + * @param ipaddr The IP address to which the packet shall be sent + */ +typedef err_t (*netif_output_fn)(struct netif *netif, struct pbuf *p, + ip_addr_t *ipaddr); +/** Function prototype for netif->linkoutput functions. Only used for ethernet + * netifs. This function is called by ARP when a packet shall be sent. + * + * @param netif The netif which shall send a packet + * @param p The packet to send (raw ethernet packet) + */ +typedef err_t (*netif_linkoutput_fn)(struct netif *netif, struct pbuf *p); +/** Function prototype for netif status- or link-callback functions. */ +typedef void (*netif_status_callback_fn)(struct netif *netif); +/** Function prototype for netif igmp_mac_filter functions */ +typedef err_t (*netif_igmp_mac_filter_fn)(struct netif *netif, + ip_addr_t *group, u8_t action); + +/** Generic data structure used for all lwIP network interfaces. + * The following fields should be filled in by the initialization + * function for the device driver: hwaddr_len, hwaddr[], mtu, flags */ +struct netif { + /** pointer to next in linked list */ + struct netif *next; + + /** IP address configuration in network byte order */ + ip_addr_t ip_addr; + ip_addr_t netmask; + ip_addr_t gw; + + /** This function is called by the network device driver + * to pass a packet up the TCP/IP stack. */ + netif_input_fn input; + /** This function is called by the IP module when it wants + * to send a packet on the interface. This function typically + * first resolves the hardware address, then sends the packet. */ + netif_output_fn output; + /** This function is called by the ARP module when it wants + * to send a packet on the interface. This function outputs + * the pbuf as-is on the link medium. */ + netif_linkoutput_fn linkoutput; +#if LWIP_NETIF_STATUS_CALLBACK + /** This function is called when the netif state is set to up or down + */ + netif_status_callback_fn status_callback; +#endif /* LWIP_NETIF_STATUS_CALLBACK */ +#if LWIP_NETIF_LINK_CALLBACK + /** This function is called when the netif link is set to up or down + */ + netif_status_callback_fn link_callback; +#endif /* LWIP_NETIF_LINK_CALLBACK */ +#if LWIP_NETIF_REMOVE_CALLBACK + /** This function is called when the netif has been removed */ + netif_status_callback_fn remove_callback; +#endif /* LWIP_NETIF_REMOVE_CALLBACK */ + /** This field can be set by the device driver and could point + * to state information for the device. */ + void *state; +#if LWIP_DHCP + /** the DHCP client state information for this netif */ + struct dhcp *dhcp; +#endif /* LWIP_DHCP */ +#if LWIP_AUTOIP + /** the AutoIP client state information for this netif */ + struct autoip *autoip; +#endif +#if LWIP_NETIF_HOSTNAME + /* the hostname for this netif, NULL is a valid value */ + char* hostname; +#endif /* LWIP_NETIF_HOSTNAME */ + /** maximum transfer unit (in bytes) */ + u16_t mtu; + /** number of bytes used in hwaddr */ + u8_t hwaddr_len; + /** link level hardware address of this interface */ + u8_t hwaddr[NETIF_MAX_HWADDR_LEN]; + /** flags (see NETIF_FLAG_ above) */ + u8_t flags; + /** descriptive abbreviation */ + char name[2]; + /** number of this interface */ + u8_t num; +#if LWIP_SNMP + /** link type (from "snmp_ifType" enum from snmp.h) */ + u8_t link_type; + /** (estimate) link speed */ + u32_t link_speed; + /** timestamp at last change made (up/down) */ + u32_t ts; + /** counters */ + u32_t ifinoctets; + u32_t ifinucastpkts; + u32_t ifinnucastpkts; + u32_t ifindiscards; + u32_t ifoutoctets; + u32_t ifoutucastpkts; + u32_t ifoutnucastpkts; + u32_t ifoutdiscards; +#endif /* LWIP_SNMP */ +#if LWIP_IGMP + /** This function could be called to add or delete a entry in the multicast + filter table of the ethernet MAC.*/ + netif_igmp_mac_filter_fn igmp_mac_filter; +#endif /* LWIP_IGMP */ +#if LWIP_NETIF_HWADDRHINT + u8_t *addr_hint; +#endif /* LWIP_NETIF_HWADDRHINT */ +#if ENABLE_LOOPBACK + /* List of packets to be queued for ourselves. */ + struct pbuf *loop_first; + struct pbuf *loop_last; +#if LWIP_LOOPBACK_MAX_PBUFS + u16_t loop_cnt_current; +#endif /* LWIP_LOOPBACK_MAX_PBUFS */ +#endif /* ENABLE_LOOPBACK */ +}; + +#if LWIP_SNMP +#define NETIF_INIT_SNMP(netif, type, speed) \ + /* use "snmp_ifType" enum from snmp.h for "type", snmp_ifType_ethernet_csmacd by example */ \ + (netif)->link_type = (type); \ + /* your link speed here (units: bits per second) */ \ + (netif)->link_speed = (speed); \ + (netif)->ts = 0; \ + (netif)->ifinoctets = 0; \ + (netif)->ifinucastpkts = 0; \ + (netif)->ifinnucastpkts = 0; \ + (netif)->ifindiscards = 0; \ + (netif)->ifoutoctets = 0; \ + (netif)->ifoutucastpkts = 0; \ + (netif)->ifoutnucastpkts = 0; \ + (netif)->ifoutdiscards = 0 +#else /* LWIP_SNMP */ +#define NETIF_INIT_SNMP(netif, type, speed) +#endif /* LWIP_SNMP */ + + +/** The list of network interfaces. */ +extern struct netif *netif_list; +/** The default network interface. */ +extern struct netif *netif_default; + +void netif_init(void); + +struct netif *netif_add(struct netif *netif, ip_addr_t *ipaddr, ip_addr_t *netmask, + ip_addr_t *gw, void *state, netif_init_fn init, netif_input_fn input); + +void +netif_set_addr(struct netif *netif, ip_addr_t *ipaddr, ip_addr_t *netmask, + ip_addr_t *gw); +void netif_remove(struct netif * netif); + +/* Returns a network interface given its name. The name is of the form + "et0", where the first two letters are the "name" field in the + netif structure, and the digit is in the num field in the same + structure. */ +struct netif *netif_find(char *name); + +void netif_set_default(struct netif *netif); + +void netif_set_ipaddr(struct netif *netif, ip_addr_t *ipaddr); +void netif_set_netmask(struct netif *netif, ip_addr_t *netmask); +void netif_set_gw(struct netif *netif, ip_addr_t *gw); + +void netif_set_up(struct netif *netif); +void netif_set_down(struct netif *netif); +/** Ask if an interface is up */ +#define netif_is_up(netif) (((netif)->flags & NETIF_FLAG_UP) ? (u8_t)1 : (u8_t)0) + +#if LWIP_NETIF_STATUS_CALLBACK +void netif_set_status_callback(struct netif *netif, netif_status_callback_fn status_callback); +#endif /* LWIP_NETIF_STATUS_CALLBACK */ +#if LWIP_NETIF_REMOVE_CALLBACK +void netif_set_remove_callback(struct netif *netif, netif_status_callback_fn remove_callback); +#endif /* LWIP_NETIF_REMOVE_CALLBACK */ + +void netif_set_link_up(struct netif *netif , uint8_t dhcp_renew); +void netif_set_link_down(struct netif *netif); +/** Ask if a link is up */ +#define netif_is_link_up(netif) (((netif)->flags & NETIF_FLAG_LINK_UP) ? (u8_t)1 : (u8_t)0) + +#if LWIP_NETIF_LINK_CALLBACK +void netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback); +#endif /* LWIP_NETIF_LINK_CALLBACK */ + +#if LWIP_NETIF_HOSTNAME +#define netif_set_hostname(netif, name) do { if((netif) != NULL) { (netif)->hostname = name; }}while(0) +#define netif_get_hostname(netif) (((netif) != NULL) ? ((netif)->hostname) : NULL) +#endif /* LWIP_NETIF_HOSTNAME */ + +#if LWIP_IGMP +#define netif_set_igmp_mac_filter(netif, function) do { if((netif) != NULL) { (netif)->igmp_mac_filter = function; }}while(0) +#define netif_get_igmp_mac_filter(netif) (((netif) != NULL) ? ((netif)->igmp_mac_filter) : NULL) +#endif /* LWIP_IGMP */ + +#if ENABLE_LOOPBACK +err_t netif_loop_output(struct netif *netif, struct pbuf *p, ip_addr_t *dest_ip); +void netif_poll(struct netif *netif); +#if !LWIP_NETIF_LOOPBACK_MULTITHREADING +void netif_poll_all(void); +#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */ +#endif /* ENABLE_LOOPBACK */ + +#if LWIP_NETIF_HWADDRHINT +#define NETIF_SET_HWADDRHINT(netif, hint) ((netif)->addr_hint = (hint)) +#else /* LWIP_NETIF_HWADDRHINT */ +#define NETIF_SET_HWADDRHINT(netif, hint) +#endif /* LWIP_NETIF_HWADDRHINT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_NETIF_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/netifapi.h b/Project/externalModules/lwip_v141/src/include/lwip/netifapi.h new file mode 100644 index 0000000..141ac14 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/netifapi.h @@ -0,0 +1,108 @@ +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#ifndef __LWIP_NETIFAPI_H__ +#define __LWIP_NETIFAPI_H__ + +#include "lwip/opt.h" + +#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/sys.h" +#include "lwip/netif.h" +#include "lwip/dhcp.h" +#include "lwip/autoip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (*netifapi_void_fn)(struct netif *netif); +typedef err_t (*netifapi_errt_fn)(struct netif *netif); + +struct netifapi_msg_msg { +#if !LWIP_TCPIP_CORE_LOCKING + sys_sem_t sem; +#endif /* !LWIP_TCPIP_CORE_LOCKING */ + err_t err; + struct netif *netif; + union { + struct { + ip_addr_t *ipaddr; + ip_addr_t *netmask; + ip_addr_t *gw; + void *state; + netif_init_fn init; + netif_input_fn input; + } add; + struct { + netifapi_void_fn voidfunc; + netifapi_errt_fn errtfunc; + } common; + } msg; +}; + +struct netifapi_msg { + void (* function)(struct netifapi_msg_msg *msg); + struct netifapi_msg_msg msg; +}; + + +/* API for application */ +err_t netifapi_netif_add ( struct netif *netif, + ip_addr_t *ipaddr, + ip_addr_t *netmask, + ip_addr_t *gw, + void *state, + netif_init_fn init, + netif_input_fn input); + +err_t netifapi_netif_set_addr ( struct netif *netif, + ip_addr_t *ipaddr, + ip_addr_t *netmask, + ip_addr_t *gw ); + +err_t netifapi_netif_common ( struct netif *netif, + netifapi_void_fn voidfunc, + netifapi_errt_fn errtfunc); + +#define netifapi_netif_remove(n) netifapi_netif_common(n, netif_remove, NULL) +#define netifapi_netif_set_up(n) netifapi_netif_common(n, netif_set_up, NULL) +#define netifapi_netif_set_down(n) netifapi_netif_common(n, netif_set_down, NULL) +#define netifapi_netif_set_default(n) netifapi_netif_common(n, netif_set_default, NULL) +#define netifapi_dhcp_start(n) netifapi_netif_common(n, NULL, dhcp_start) +#define netifapi_dhcp_stop(n) netifapi_netif_common(n, dhcp_stop, NULL) +#define netifapi_autoip_start(n) netifapi_netif_common(n, NULL, autoip_start) +#define netifapi_autoip_stop(n) netifapi_netif_common(n, NULL, autoip_stop) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_NETIF_API */ + +#endif /* __LWIP_NETIFAPI_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/opt.h b/Project/externalModules/lwip_v141/src/include/lwip/opt.h new file mode 100644 index 0000000..0b86b09 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/opt.h @@ -0,0 +1,2133 @@ +/** + * @file + * + * lwIP Options Configuration + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_OPT_H__ +#define __LWIP_OPT_H__ + +/* + * Include user defined options first. Anything not defined in these files + * will be set to standard values. Override anything you dont like! + */ +#include "lwipopts.h" +#include "lwip/debug.h" + +/* + ----------------------------------------------- + ---------- Platform specific locking ---------- + ----------------------------------------------- +*/ + +/** + * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain + * critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#ifndef SYS_LIGHTWEIGHT_PROT +#define SYS_LIGHTWEIGHT_PROT 0 +#endif + +/** + * NO_SYS==1: Provides VERY minimal functionality. Otherwise, + * use lwIP facilities. + */ +#ifndef NO_SYS +#define NO_SYS 0 +#endif + +/** + * NO_SYS_NO_TIMERS==1: Drop support for sys_timeout when NO_SYS==1 + * Mainly for compatibility to old versions. + */ +#ifndef NO_SYS_NO_TIMERS +#define NO_SYS_NO_TIMERS 0 +#endif + +/** + * MEMCPY: override this if you have a faster implementation at hand than the + * one included in your C library + */ +#ifndef MEMCPY +#define MEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/** + * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a + * call to memcpy() if the length is known at compile time and is small. + */ +#ifndef SMEMCPY +#define SMEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/* + ------------------------------------ + ---------- Memory options ---------- + ------------------------------------ +*/ +/** + * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library + * instead of the lwip internal allocator. Can save code size if you + * already use it. + */ +#ifndef MEM_LIBC_MALLOC +#define MEM_LIBC_MALLOC 0 +#endif + +/** +* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator. +* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution +* speed and usage from interrupts! +*/ +#ifndef MEMP_MEM_MALLOC +#define MEMP_MEM_MALLOC 0 +#endif + +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> #define MEM_ALIGNMENT 4 + * 2 byte alignment -> #define MEM_ALIGNMENT 2 + */ +#ifndef MEM_ALIGNMENT +#define MEM_ALIGNMENT 1 +#endif + +/** + * MEM_SIZE: the size of the heap memory. If the application will send + * a lot of data that needs to be copied, this should be set high. + */ +#ifndef MEM_SIZE +#define MEM_SIZE 1600 +#endif + +/** + * MEMP_SEPARATE_POOLS: if defined to 1, each pool is placed in its own array. + * This can be used to individually change the location of each pool. + * Default is one big array for all pools + */ +#ifndef MEMP_SEPARATE_POOLS +#define MEMP_SEPARATE_POOLS 0 +#endif + +/** + * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable + * amount of bytes before and after each memp element in every pool and fills + * it with a prominent default value. + * MEMP_OVERFLOW_CHECK == 0 no checking + * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed + * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time + * memp_malloc() or memp_free() is called (useful but slow!) + */ +#ifndef MEMP_OVERFLOW_CHECK +#define MEMP_OVERFLOW_CHECK 0 +#endif + +/** + * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make + * sure that there are no cycles in the linked lists. + */ +#ifndef MEMP_SANITY_CHECK +#define MEMP_SANITY_CHECK 0 +#endif + +/** + * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set + * of memory pools of various sizes. When mem_malloc is called, an element of + * the smallest pool that can provide the length needed is returned. + * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled. + */ +#ifndef MEM_USE_POOLS +#define MEM_USE_POOLS 0 +#endif + +/** + * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next + * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more + * reliable. */ +#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL +#define MEM_USE_POOLS_TRY_BIGGER_POOL 0 +#endif + +/** + * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h + * that defines additional pools beyond the "standard" ones required + * by lwIP. If you set this to 1, you must have lwippools.h in your + * inlude path somewhere. + */ +#ifndef MEMP_USE_CUSTOM_POOLS +#define MEMP_USE_CUSTOM_POOLS 0 +#endif + +/** + * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from + * interrupt context (or another context that doesn't allow waiting for a + * semaphore). + * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT, + * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs + * with each loop so that mem_free can run. + * + * ATTENTION: As you can see from the above description, this leads to dis-/ + * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc + * can need longer. + * + * If you don't want that, at least for NO_SYS=0, you can still use the following + * functions to enqueue a deallocation call which then runs in the tcpip_thread + * context: + * - pbuf_free_callback(p); + * - mem_free_callback(m); + */ +#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT +#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0 +#endif + +/* + ------------------------------------------------ + ---------- Internal Memory Pool Sizes ---------- + ------------------------------------------------ +*/ +/** + * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). + * If the application sends a lot of data out of ROM (or other static memory), + * this should be set high. + */ +#ifndef MEMP_NUM_PBUF +#define MEMP_NUM_PBUF 16 +#endif + +/** + * MEMP_NUM_RAW_PCB: Number of raw connection PCBs + * (requires the LWIP_RAW option) + */ +#ifndef MEMP_NUM_RAW_PCB +#define MEMP_NUM_RAW_PCB 4 +#endif + +/** + * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + * per active UDP "connection". + * (requires the LWIP_UDP option) + */ +#ifndef MEMP_NUM_UDP_PCB +#define MEMP_NUM_UDP_PCB 4 +#endif + +/** + * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB +#define MEMP_NUM_TCP_PCB 5 +#endif + +/** + * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB_LISTEN +#define MEMP_NUM_TCP_PCB_LISTEN 8 +#endif + +/** + * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_SEG +#define MEMP_NUM_TCP_SEG 16 +#endif + +/** + * MEMP_NUM_REASSDATA: the number of IP packets simultaneously queued for + * reassembly (whole packets, not fragments!) + */ +#ifndef MEMP_NUM_REASSDATA +#define MEMP_NUM_REASSDATA 5 +#endif + +/** + * MEMP_NUM_FRAG_PBUF: the number of IP fragments simultaneously sent + * (fragments, not whole packets!). + * This is only used with IP_FRAG_USES_STATIC_BUF==0 and + * LWIP_NETIF_TX_SINGLE_PBUF==0 and only has to be > 1 with DMA-enabled MACs + * where the packet is not yet sent when netif->output returns. + */ +#ifndef MEMP_NUM_FRAG_PBUF +#define MEMP_NUM_FRAG_PBUF 15 +#endif + +/** + * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing + * packets (pbufs) that are waiting for an ARP request (to resolve + * their destination address) to finish. + * (requires the ARP_QUEUEING option) + */ +#ifndef MEMP_NUM_ARP_QUEUE +#define MEMP_NUM_ARP_QUEUE 30 +#endif + +/** + * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces + * can be members et the same time (one per netif - allsystems group -, plus one + * per netif membership). + * (requires the LWIP_IGMP option) + */ +#ifndef MEMP_NUM_IGMP_GROUP +#define MEMP_NUM_IGMP_GROUP 8 +#endif + +/** + * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts. + * (requires NO_SYS==0) + * The default number of timeouts is calculated here for all enabled modules. + * The formula expects settings to be either '0' or '1'. + */ +#ifndef MEMP_NUM_SYS_TIMEOUT +#define MEMP_NUM_SYS_TIMEOUT (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_SUPPORT) +#endif + +/** + * MEMP_NUM_NETBUF: the number of struct netbufs. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETBUF +#define MEMP_NUM_NETBUF 2 +#endif + +/** + * MEMP_NUM_NETCONN: the number of struct netconns. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETCONN +#define MEMP_NUM_NETCONN 8 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used + * for callback/timeout API communication. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_API +#define MEMP_NUM_TCPIP_MSG_API 8 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used + * for incoming packets. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_INPKT +#define MEMP_NUM_TCPIP_MSG_INPKT 8 +#endif + +/** + * MEMP_NUM_SNMP_NODE: the number of leafs in the SNMP tree. + */ +#ifndef MEMP_NUM_SNMP_NODE +#define MEMP_NUM_SNMP_NODE 50 +#endif + +/** + * MEMP_NUM_SNMP_ROOTNODE: the number of branches in the SNMP tree. + * Every branch has one leaf (MEMP_NUM_SNMP_NODE) at least! + */ +#ifndef MEMP_NUM_SNMP_ROOTNODE +#define MEMP_NUM_SNMP_ROOTNODE 30 +#endif + +/** + * MEMP_NUM_SNMP_VARBIND: the number of concurrent requests (does not have to + * be changed normally) - 2 of these are used per request (1 for input, + * 1 for output) + */ +#ifndef MEMP_NUM_SNMP_VARBIND +#define MEMP_NUM_SNMP_VARBIND 2 +#endif + +/** + * MEMP_NUM_SNMP_VALUE: the number of OID or values concurrently used + * (does not have to be changed normally) - 3 of these are used per request + * (1 for the value read and 2 for OIDs - input and output) + */ +#ifndef MEMP_NUM_SNMP_VALUE +#define MEMP_NUM_SNMP_VALUE 3 +#endif + +/** + * MEMP_NUM_NETDB: the number of concurrently running lwip_addrinfo() calls + * (before freeing the corresponding memory using lwip_freeaddrinfo()). + */ +#ifndef MEMP_NUM_NETDB +#define MEMP_NUM_NETDB 1 +#endif + +/** + * MEMP_NUM_LOCALHOSTLIST: the number of host entries in the local host list + * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1. + */ +#ifndef MEMP_NUM_LOCALHOSTLIST +#define MEMP_NUM_LOCALHOSTLIST 1 +#endif + +/** + * MEMP_NUM_PPPOE_INTERFACES: the number of concurrently active PPPoE + * interfaces (only used with PPPOE_SUPPORT==1) + */ +#ifndef MEMP_NUM_PPPOE_INTERFACES +#define MEMP_NUM_PPPOE_INTERFACES 1 +#endif + +/** + * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + */ +#ifndef PBUF_POOL_SIZE +#define PBUF_POOL_SIZE 16 +#endif + +/* + --------------------------------- + ---------- ARP options ---------- + --------------------------------- +*/ +/** + * LWIP_ARP==1: Enable ARP functionality. + */ +#ifndef LWIP_ARP +#define LWIP_ARP 1 +#endif + +/** + * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached. + */ +#ifndef ARP_TABLE_SIZE +#define ARP_TABLE_SIZE 10 +#endif + +/** + * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address + * resolution. By default, only the most recent packet is queued per IP address. + * This is sufficient for most protocols and mainly reduces TCP connection + * startup time. Set this to 1 if you know your application sends more than one + * packet in a row to an IP address that is not in the ARP cache. + */ +#ifndef ARP_QUEUEING +#define ARP_QUEUEING 0 +#endif + +/** + * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be + * updated with the source MAC and IP addresses supplied in the packet. + * You may want to disable this if you do not trust LAN peers to have the + * correct addresses, or as a limited approach to attempt to handle + * spoofing. If disabled, lwIP will need to make a new ARP request if + * the peer is not already in the ARP table, adding a little latency. + * The peer *is* in the ARP table if it requested our address before. + * Also notice that this slows down input processing of every IP packet! + */ +#ifndef ETHARP_TRUST_IP_MAC +#define ETHARP_TRUST_IP_MAC 0 +#endif + +/** + * ETHARP_SUPPORT_VLAN==1: support receiving ethernet packets with VLAN header. + * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check. + * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted. + * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted. + * Alternatively, define a function/define ETHARP_VLAN_CHECK_FN(eth_hdr, vlan) + * that returns 1 to accept a packet or 0 to drop a packet. + */ +#ifndef ETHARP_SUPPORT_VLAN +#define ETHARP_SUPPORT_VLAN 0 +#endif + +/** LWIP_ETHERNET==1: enable ethernet support for PPPoE even though ARP + * might be disabled + */ +#ifndef LWIP_ETHERNET +#define LWIP_ETHERNET (LWIP_ARP || PPPOE_SUPPORT) +#endif + +/** ETH_PAD_SIZE: number of bytes added before the ethernet header to ensure + * alignment of payload after that header. Since the header is 14 bytes long, + * without this padding e.g. addresses in the IP header will not be aligned + * on a 32-bit boundary, so setting this to 2 can speed up 32-bit-platforms. + */ +#ifndef ETH_PAD_SIZE +#define ETH_PAD_SIZE 0 +#endif + +/** ETHARP_SUPPORT_STATIC_ENTRIES==1: enable code to support static ARP table + * entries (using etharp_add_static_entry/etharp_remove_static_entry). + */ +#ifndef ETHARP_SUPPORT_STATIC_ENTRIES +#define ETHARP_SUPPORT_STATIC_ENTRIES 0 +#endif + + +/* + -------------------------------- + ---------- IP options ---------- + -------------------------------- +*/ +/** + * IP_FORWARD==1: Enables the ability to forward IP packets across network + * interfaces. If you are going to run lwIP on a device with only one network + * interface, define this to 0. + */ +#ifndef IP_FORWARD +#define IP_FORWARD 0 +#endif + +/** + * IP_OPTIONS_ALLOWED: Defines the behavior for IP options. + * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped. + * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed). + */ +#ifndef IP_OPTIONS_ALLOWED +#define IP_OPTIONS_ALLOWED 1 +#endif + +/** + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via IP_FRAG. + */ +#ifndef IP_REASSEMBLY +#define IP_REASSEMBLY 1 +#endif + +/** + * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#ifndef IP_FRAG +#define IP_FRAG 1 +#endif + +/** + * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) + * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived + * in this time, the whole packet is discarded. + */ +#ifndef IP_REASS_MAXAGE +#define IP_REASS_MAXAGE 3 +#endif + +/** + * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. + * Since the received pbufs are enqueued, be sure to configure + * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive + * packets even if the maximum amount of fragments is enqueued for reassembly! + */ +#ifndef IP_REASS_MAX_PBUFS +#define IP_REASS_MAX_PBUFS 10 +#endif + +/** + * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP + * fragmentation. Otherwise pbufs are allocated and reference the original + * packet data to be fragmented (or with LWIP_NETIF_TX_SINGLE_PBUF==1, + * new PBUF_RAM pbufs are used for fragments). + * ATTENTION: IP_FRAG_USES_STATIC_BUF==1 may not be used for DMA-enabled MACs! + */ +#ifndef IP_FRAG_USES_STATIC_BUF +#define IP_FRAG_USES_STATIC_BUF 0 +#endif + +/** + * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer + * (requires IP_FRAG_USES_STATIC_BUF==1) + */ +#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU) +#define IP_FRAG_MAX_MTU 1500 +#endif + +/** + * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers. + */ +#ifndef IP_DEFAULT_TTL +#define IP_DEFAULT_TTL 255 +#endif + +/** + * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast + * filter per pcb on udp and raw send operations. To enable broadcast filter + * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1. + */ +#ifndef IP_SOF_BROADCAST +#define IP_SOF_BROADCAST 0 +#endif + +/** + * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast + * filter on recv operations. + */ +#ifndef IP_SOF_BROADCAST_RECV +#define IP_SOF_BROADCAST_RECV 0 +#endif + +/** + * IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1: allow ip_forward() to send packets back + * out on the netif where it was received. This should only be used for + * wireless networks. + * ATTENTION: When this is 1, make sure your netif driver correctly marks incoming + * link-layer-broadcast/multicast packets as such using the corresponding pbuf flags! + */ +#ifndef IP_FORWARD_ALLOW_TX_ON_RX_NETIF +#define IP_FORWARD_ALLOW_TX_ON_RX_NETIF 0 +#endif + +/** + * LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS==1: randomize the local port for the first + * local TCP/UDP pcb (default==0). This can prevent creating predictable port + * numbers after booting a device. + */ +#ifndef LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS +#define LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS 0 +#endif + +/* + ---------------------------------- + ---------- ICMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_ICMP==1: Enable ICMP module inside the IP stack. + * Be careful, disable that make your product non-compliant to RFC1122 + */ +#ifndef LWIP_ICMP +#define LWIP_ICMP 1 +#endif + +/** + * ICMP_TTL: Default value for Time-To-Live used by ICMP packets. + */ +#ifndef ICMP_TTL +#define ICMP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only) + */ +#ifndef LWIP_BROADCAST_PING +#define LWIP_BROADCAST_PING 0 +#endif + +/** + * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only) + */ +#ifndef LWIP_MULTICAST_PING +#define LWIP_MULTICAST_PING 0 +#endif + +/* + --------------------------------- + ---------- RAW options ---------- + --------------------------------- +*/ +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef LWIP_RAW +#define LWIP_RAW 1 +#endif + +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef RAW_TTL +#define RAW_TTL (IP_DEFAULT_TTL) +#endif + +/* + ---------------------------------- + ---------- DHCP options ---------- + ---------------------------------- +*/ +/** + * LWIP_DHCP==1: Enable DHCP module. + */ +#ifndef LWIP_DHCP +#define LWIP_DHCP 0 +#endif + +/** + * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address. + */ +#ifndef DHCP_DOES_ARP_CHECK +#define DHCP_DOES_ARP_CHECK ((LWIP_DHCP) && (LWIP_ARP)) +#endif + +/* + ------------------------------------ + ---------- AUTOIP options ---------- + ------------------------------------ +*/ +/** + * LWIP_AUTOIP==1: Enable AUTOIP module. + */ +#ifndef LWIP_AUTOIP +#define LWIP_AUTOIP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on + * the same interface at the same time. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP +#define LWIP_DHCP_AUTOIP_COOP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes + * that should be sent before falling back on AUTOIP. This can be set + * as low as 1 to get an AutoIP address very quickly, but you should + * be prepared to handle a changing IP address when DHCP overrides + * AutoIP. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES +#define LWIP_DHCP_AUTOIP_COOP_TRIES 9 +#endif + +/* + ---------------------------------- + ---------- SNMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP + * transport. + */ +#ifndef LWIP_SNMP +#define LWIP_SNMP 0 +#endif + +/** + * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will + * allow. At least one request buffer is required. + * Does not have to be changed unless external MIBs answer request asynchronously + */ +#ifndef SNMP_CONCURRENT_REQUESTS +#define SNMP_CONCURRENT_REQUESTS 1 +#endif + +/** + * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap + * destination is required + */ +#ifndef SNMP_TRAP_DESTINATIONS +#define SNMP_TRAP_DESTINATIONS 1 +#endif + +/** + * SNMP_PRIVATE_MIB: + * When using a private MIB, you have to create a file 'private_mib.h' that contains + * a 'struct mib_array_node mib_private' which contains your MIB. + */ +#ifndef SNMP_PRIVATE_MIB +#define SNMP_PRIVATE_MIB 0 +#endif + +/** + * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not + * a safe action and disabled when SNMP_SAFE_REQUESTS = 1). + * Unsafe requests are disabled by default! + */ +#ifndef SNMP_SAFE_REQUESTS +#define SNMP_SAFE_REQUESTS 1 +#endif + +/** + * The maximum length of strings used. This affects the size of + * MEMP_SNMP_VALUE elements. + */ +#ifndef SNMP_MAX_OCTET_STRING_LEN +#define SNMP_MAX_OCTET_STRING_LEN 127 +#endif + +/** + * The maximum depth of the SNMP tree. + * With private MIBs enabled, this depends on your MIB! + * This affects the size of MEMP_SNMP_VALUE elements. + */ +#ifndef SNMP_MAX_TREE_DEPTH +#define SNMP_MAX_TREE_DEPTH 15 +#endif + +/** + * The size of the MEMP_SNMP_VALUE elements, normally calculated from + * SNMP_MAX_OCTET_STRING_LEN and SNMP_MAX_TREE_DEPTH. + */ +#ifndef SNMP_MAX_VALUE_SIZE +#define SNMP_MAX_VALUE_SIZE LWIP_MAX((SNMP_MAX_OCTET_STRING_LEN)+1, sizeof(s32_t)*(SNMP_MAX_TREE_DEPTH)) +#endif + +/* + ---------------------------------- + ---------- IGMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_IGMP==1: Turn on IGMP module. + */ +#ifndef LWIP_IGMP +#define LWIP_IGMP 0 +#endif + +/* + ---------------------------------- + ---------- DNS options ----------- + ---------------------------------- +*/ +/** + * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS + * transport. + */ +#ifndef LWIP_DNS +#define LWIP_DNS 0 +#endif + +/** DNS maximum number of entries to maintain locally. */ +#ifndef DNS_TABLE_SIZE +#define DNS_TABLE_SIZE 4 +#endif + +/** DNS maximum host name length supported in the name table. */ +#ifndef DNS_MAX_NAME_LENGTH +#define DNS_MAX_NAME_LENGTH 256 +#endif + +/** The maximum of DNS servers */ +#ifndef DNS_MAX_SERVERS +#define DNS_MAX_SERVERS 2 +#endif + +/** DNS do a name checking between the query and the response. */ +#ifndef DNS_DOES_NAME_CHECK +#define DNS_DOES_NAME_CHECK 1 +#endif + +/** DNS message max. size. Default value is RFC compliant. */ +#ifndef DNS_MSG_SIZE +#define DNS_MSG_SIZE 512 +#endif + +/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, + * you have to define + * #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}} + * (an array of structs name/address, where address is an u32_t in network + * byte order). + * + * Instead, you can also use an external function: + * #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name) + * that returns the IP address or INADDR_NONE if not found. + */ +#ifndef DNS_LOCAL_HOSTLIST +#define DNS_LOCAL_HOSTLIST 0 +#endif /* DNS_LOCAL_HOSTLIST */ + +/** If this is turned on, the local host-list can be dynamically changed + * at runtime. */ +#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC +#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0 +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +/* + --------------------------------- + ---------- UDP options ---------- + --------------------------------- +*/ +/** + * LWIP_UDP==1: Turn on UDP. + */ +#ifndef LWIP_UDP +#define LWIP_UDP 1 +#endif + +/** + * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP) + */ +#ifndef LWIP_UDPLITE +#define LWIP_UDPLITE 0 +#endif + +/** + * UDP_TTL: Default Time-To-Live value. + */ +#ifndef UDP_TTL +#define UDP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf. + */ +#ifndef LWIP_NETBUF_RECVINFO +#define LWIP_NETBUF_RECVINFO 0 +#endif + +/* + --------------------------------- + ---------- TCP options ---------- + --------------------------------- +*/ +/** + * LWIP_TCP==1: Turn on TCP. + */ +#ifndef LWIP_TCP +#define LWIP_TCP 1 +#endif + +/** + * TCP_TTL: Default Time-To-Live value. + */ +#ifndef TCP_TTL +#define TCP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * TCP_WND: The size of a TCP window. This must be at least + * (2 * TCP_MSS) for things to work well + */ +#ifndef TCP_WND +#define TCP_WND (4 * TCP_MSS) +#endif + +/** + * TCP_MAXRTX: Maximum number of retransmissions of data segments. + */ +#ifndef TCP_MAXRTX +#define TCP_MAXRTX 12 +#endif + +/** + * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. + */ +#ifndef TCP_SYNMAXRTX +#define TCP_SYNMAXRTX 6 +#endif + +/** + * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order. + * Define to 0 if your device is low on memory. + */ +#ifndef TCP_QUEUE_OOSEQ +#define TCP_QUEUE_OOSEQ (LWIP_TCP) +#endif + +/** + * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default, + * you might want to increase this.) + * For the receive side, this MSS is advertised to the remote side + * when opening a connection. For the transmit size, this MSS sets + * an upper limit on the MSS advertised by the remote host. + */ +#ifndef TCP_MSS +#define TCP_MSS 536 +#endif + +/** + * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really + * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which + * reflects the available reassembly buffer size at the remote host) and the + * largest size permitted by the IP layer" (RFC 1122) + * Setting this to 1 enables code that checks TCP_MSS against the MTU of the + * netif used for a connection and limits the MSS if it would be too big otherwise. + */ +#ifndef TCP_CALCULATE_EFF_SEND_MSS +#define TCP_CALCULATE_EFF_SEND_MSS 1 +#endif + + +/** + * TCP_SND_BUF: TCP sender buffer space (bytes). + * To achieve good performance, this should be at least 2 * TCP_MSS. + */ +#ifndef TCP_SND_BUF +#define TCP_SND_BUF (2 * TCP_MSS) +#endif + +/** + * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least + * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. + */ +#ifndef TCP_SND_QUEUELEN +#define TCP_SND_QUEUELEN ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS)) +#endif + +/** + * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than + * TCP_SND_BUF. It is the amount of space which must be available in the + * TCP snd_buf for select to return writable (combined with TCP_SNDQUEUELOWAT). + */ +#ifndef TCP_SNDLOWAT +#define TCP_SNDLOWAT LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1) +#endif + +/** + * TCP_SNDQUEUELOWAT: TCP writable bufs (pbuf count). This must be less + * than TCP_SND_QUEUELEN. If the number of pbufs queued on a pcb drops below + * this number, select returns writable (combined with TCP_SNDLOWAT). + */ +#ifndef TCP_SNDQUEUELOWAT +#define TCP_SNDQUEUELOWAT LWIP_MAX(((TCP_SND_QUEUELEN)/2), 5) +#endif + +/** + * TCP_OOSEQ_MAX_BYTES: The maximum number of bytes queued on ooseq per pcb. + * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0. + */ +#ifndef TCP_OOSEQ_MAX_BYTES +#define TCP_OOSEQ_MAX_BYTES 0 +#endif + +/** + * TCP_OOSEQ_MAX_PBUFS: The maximum number of pbufs queued on ooseq per pcb. + * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0. + */ +#ifndef TCP_OOSEQ_MAX_PBUFS +#define TCP_OOSEQ_MAX_PBUFS 0 +#endif + +/** + * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb. + */ +#ifndef TCP_LISTEN_BACKLOG +#define TCP_LISTEN_BACKLOG 0 +#endif + +/** + * The maximum allowed backlog for TCP listen netconns. + * This backlog is used unless another is explicitly specified. + * 0xff is the maximum (u8_t). + */ +#ifndef TCP_DEFAULT_LISTEN_BACKLOG +#define TCP_DEFAULT_LISTEN_BACKLOG 0xff +#endif + +/** + * TCP_OVERSIZE: The maximum number of bytes that tcp_write may + * allocate ahead of time in an attempt to create shorter pbuf chains + * for transmission. The meaningful range is 0 to TCP_MSS. Some + * suggested values are: + * + * 0: Disable oversized allocation. Each tcp_write() allocates a new + pbuf (old behaviour). + * 1: Allocate size-aligned pbufs with minimal excess. Use this if your + * scatter-gather DMA requires aligned fragments. + * 128: Limit the pbuf/memory overhead to 20%. + * TCP_MSS: Try to create unfragmented TCP packets. + * TCP_MSS/4: Try to create 4 fragments or less per TCP packet. + */ +#ifndef TCP_OVERSIZE +#define TCP_OVERSIZE TCP_MSS +#endif + +/** + * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option. + */ +#ifndef LWIP_TCP_TIMESTAMPS +#define LWIP_TCP_TIMESTAMPS 0 +#endif + +/** + * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an + * explicit window update + */ +#ifndef TCP_WND_UPDATE_THRESHOLD +#define TCP_WND_UPDATE_THRESHOLD (TCP_WND / 4) +#endif + +/** + * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1. + * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all + * events (accept, sent, etc) that happen in the system. + * LWIP_CALLBACK_API==1: The PCB callback function is called directly + * for the event. This is the default. + */ +#if !defined(LWIP_EVENT_API) && !defined(LWIP_CALLBACK_API) +#define LWIP_EVENT_API 0 +#define LWIP_CALLBACK_API 1 +#endif + + +/* + ---------------------------------- + ---------- Pbuf options ---------- + ---------------------------------- +*/ +/** + * PBUF_LINK_HLEN: the number of bytes that should be allocated for a + * link level header. The default is 14, the standard value for + * Ethernet. + */ +#ifndef PBUF_LINK_HLEN +#define PBUF_LINK_HLEN (14 + ETH_PAD_SIZE) +#endif + +/** + * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is + * designed to accomodate single full size TCP frame in one pbuf, including + * TCP_MSS, IP header, and link header. + */ +#ifndef PBUF_POOL_BUFSIZE +#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN) +#endif + +/* + ------------------------------------------------ + ---------- Network Interfaces options ---------- + ------------------------------------------------ +*/ +/** + * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname + * field. + */ +#ifndef LWIP_NETIF_HOSTNAME +#define LWIP_NETIF_HOSTNAME 0 +#endif + +/** + * LWIP_NETIF_API==1: Support netif api (in netifapi.c) + */ +#ifndef LWIP_NETIF_API +#define LWIP_NETIF_API 0 +#endif + +/** + * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface + * changes its up/down status (i.e., due to DHCP IP acquistion) + */ +#ifndef LWIP_NETIF_STATUS_CALLBACK +#define LWIP_NETIF_STATUS_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface + * whenever the link changes (i.e., link down) + */ +#ifndef LWIP_NETIF_LINK_CALLBACK +#define LWIP_NETIF_LINK_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_REMOVE_CALLBACK==1: Support a callback function that is called + * when a netif has been removed + */ +#ifndef LWIP_NETIF_REMOVE_CALLBACK +#define LWIP_NETIF_REMOVE_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table + * indices) in struct netif. TCP and UDP can make use of this to prevent + * scanning the ARP table for every sent packet. While this is faster for big + * ARP tables or many concurrent connections, it might be counterproductive + * if you have a tiny ARP table or if there never are concurrent connections. + */ +#ifndef LWIP_NETIF_HWADDRHINT +#define LWIP_NETIF_HWADDRHINT 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP + * address equal to the netif IP address, looping them back up the stack. + */ +#ifndef LWIP_NETIF_LOOPBACK +#define LWIP_NETIF_LOOPBACK 0 +#endif + +/** + * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback + * sending for each netif (0 = disabled) + */ +#ifndef LWIP_LOOPBACK_MAX_PBUFS +#define LWIP_LOOPBACK_MAX_PBUFS 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in + * the system, as netifs must change how they behave depending on this setting + * for the LWIP_NETIF_LOOPBACK option to work. + * Setting this is needed to avoid reentering non-reentrant functions like + * tcp_input(). + * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a + * multithreaded environment like tcpip.c. In this case, netif->input() + * is called directly. + * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup. + * The packets are put on a list and netif_poll() must be called in + * the main application loop. + */ +#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING +#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS) +#endif + +/** + * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data + * to be sent into one single pbuf. This is for compatibility with DMA-enabled + * MACs that do not support scatter-gather. + * Beware that this might involve CPU-memcpy before transmitting that would not + * be needed without this flag! Use this only if you need to! + * + * @todo: TCP and IP-frag do not work with this, yet: + */ +#ifndef LWIP_NETIF_TX_SINGLE_PBUF +#define LWIP_NETIF_TX_SINGLE_PBUF 0 +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + +/* + ------------------------------------ + ---------- LOOPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c + */ +#ifndef LWIP_HAVE_LOOPIF +#define LWIP_HAVE_LOOPIF 0 +#endif + +/* + ------------------------------------ + ---------- SLIPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c + */ +#ifndef LWIP_HAVE_SLIPIF +#define LWIP_HAVE_SLIPIF 0 +#endif + +/* + ------------------------------------ + ---------- Thread options ---------- + ------------------------------------ +*/ +/** + * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread. + */ +#ifndef TCPIP_THREAD_NAME +#define TCPIP_THREAD_NAME "tcpip_thread" +#endif + +/** + * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_STACKSIZE +#define TCPIP_THREAD_STACKSIZE 0 +#endif + +/** + * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_PRIO +#define TCPIP_THREAD_PRIO 1 +#endif + +/** + * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when tcpip_init is called. + */ +#ifndef TCPIP_MBOX_SIZE +#define TCPIP_MBOX_SIZE 0 +#endif + +/** + * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread. + */ +#ifndef SLIPIF_THREAD_NAME +#define SLIPIF_THREAD_NAME "slipif_loop" +#endif + +/** + * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_STACKSIZE +#define SLIPIF_THREAD_STACKSIZE 0 +#endif + +/** + * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_PRIO +#define SLIPIF_THREAD_PRIO 1 +#endif + +/** + * PPP_THREAD_NAME: The name assigned to the pppInputThread. + */ +#ifndef PPP_THREAD_NAME +#define PPP_THREAD_NAME "pppInputThread" +#endif + +/** + * PPP_THREAD_STACKSIZE: The stack size used by the pppInputThread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_STACKSIZE +#define PPP_THREAD_STACKSIZE 0 +#endif + +/** + * PPP_THREAD_PRIO: The priority assigned to the pppInputThread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_PRIO +#define PPP_THREAD_PRIO 1 +#endif + +/** + * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread. + */ +#ifndef DEFAULT_THREAD_NAME +#define DEFAULT_THREAD_NAME "lwIP" +#endif + +/** + * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_STACKSIZE +#define DEFAULT_THREAD_STACKSIZE 0 +#endif + +/** + * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_PRIO +#define DEFAULT_THREAD_PRIO 1 +#endif + +/** + * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_RAW_RECVMBOX_SIZE +#define DEFAULT_RAW_RECVMBOX_SIZE 0 +#endif + +/** + * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_UDP_RECVMBOX_SIZE +#define DEFAULT_UDP_RECVMBOX_SIZE 0 +#endif + +/** + * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_TCP_RECVMBOX_SIZE +#define DEFAULT_TCP_RECVMBOX_SIZE 0 +#endif + +/** + * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when the acceptmbox is created. + */ +#ifndef DEFAULT_ACCEPTMBOX_SIZE +#define DEFAULT_ACCEPTMBOX_SIZE 0 +#endif + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +/** + * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING +#define LWIP_TCPIP_CORE_LOCKING 0 +#endif + +/** + * LWIP_TCPIP_CORE_LOCKING_INPUT: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING_INPUT +#define LWIP_TCPIP_CORE_LOCKING_INPUT 0 +#endif + +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#ifndef LWIP_NETCONN +#define LWIP_NETCONN 1 +#endif + +/** LWIP_TCPIP_TIMEOUT==1: Enable tcpip_timeout/tcpip_untimeout tod create + * timers running in tcpip_thread from another thread. + */ +#ifndef LWIP_TCPIP_TIMEOUT +#define LWIP_TCPIP_TIMEOUT 1 +#endif + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#ifndef LWIP_SOCKET +#define LWIP_SOCKET 1 +#endif + +/** + * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names. + * (only used if you use sockets.c) + */ +#ifndef LWIP_COMPAT_SOCKETS +#define LWIP_COMPAT_SOCKETS 1 +#endif + +/** + * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names. + * Disable this option if you use a POSIX operating system that uses the same + * names (read, write & close). (only used if you use sockets.c) + */ +#ifndef LWIP_POSIX_SOCKETS_IO_NAMES +#define LWIP_POSIX_SOCKETS_IO_NAMES 1 +#endif + +/** + * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT + * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set + * in seconds. (does not require sockets.c, and will affect tcp.c) + */ +#ifndef LWIP_TCP_KEEPALIVE +#define LWIP_TCP_KEEPALIVE 0 +#endif + +/** + * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and + * SO_SNDTIMEO processing. + */ +#ifndef LWIP_SO_SNDTIMEO +#define LWIP_SO_SNDTIMEO 0 +#endif + +/** + * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and + * SO_RCVTIMEO processing. + */ +#ifndef LWIP_SO_RCVTIMEO +#define LWIP_SO_RCVTIMEO 0 +#endif + +/** + * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing. + */ +#ifndef LWIP_SO_RCVBUF +#define LWIP_SO_RCVBUF 0 +#endif + +/** + * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize. + */ +#ifndef RECV_BUFSIZE_DEFAULT +#define RECV_BUFSIZE_DEFAULT INT_MAX +#endif + +/** + * SO_REUSE==1: Enable SO_REUSEADDR option. + */ +#ifndef SO_REUSE +#define SO_REUSE 0 +#endif + +/** + * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets + * to all local matches if SO_REUSEADDR is turned on. + * WARNING: Adds a memcpy for every packet if passing to more than one pcb! + */ +#ifndef SO_REUSE_RXTOALL +#define SO_REUSE_RXTOALL 0 +#endif + +/* + ---------------------------------------- + ---------- Statistics options ---------- + ---------------------------------------- +*/ +/** + * LWIP_STATS==1: Enable statistics collection in lwip_stats. + */ +#ifndef LWIP_STATS +#define LWIP_STATS 1 +#endif + +#if LWIP_STATS + +/** + * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. + */ +#ifndef LWIP_STATS_DISPLAY +#define LWIP_STATS_DISPLAY 1 +#endif + +/** + * LINK_STATS==1: Enable link stats. + */ +#ifndef LINK_STATS +#define LINK_STATS 1 +#endif + +/** + * ETHARP_STATS==1: Enable etharp stats. + */ +#ifndef ETHARP_STATS +#define ETHARP_STATS (LWIP_ARP) +#endif + +/** + * IP_STATS==1: Enable IP stats. + */ +#ifndef IP_STATS +#define IP_STATS 1 +#endif + +/** + * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is + * on if using either frag or reass. + */ +#ifndef IPFRAG_STATS +#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG) +#endif + +/** + * ICMP_STATS==1: Enable ICMP stats. + */ +#ifndef ICMP_STATS +#define ICMP_STATS 1 +#endif + +/** + * IGMP_STATS==1: Enable IGMP stats. + */ +#ifndef IGMP_STATS +#define IGMP_STATS (LWIP_IGMP) +#endif + +/** + * UDP_STATS==1: Enable UDP stats. Default is on if + * UDP enabled, otherwise off. + */ +#ifndef UDP_STATS +#define UDP_STATS (LWIP_UDP) +#endif + +/** + * TCP_STATS==1: Enable TCP stats. Default is on if TCP + * enabled, otherwise off. + */ +#ifndef TCP_STATS +#define TCP_STATS (LWIP_TCP) +#endif + +/** + * MEM_STATS==1: Enable mem.c stats. + */ +#ifndef MEM_STATS +#define MEM_STATS ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0)) +#endif + +/** + * MEMP_STATS==1: Enable memp.c pool stats. + */ +#ifndef MEMP_STATS +#define MEMP_STATS (MEMP_MEM_MALLOC == 0) +#endif + +/** + * SYS_STATS==1: Enable system stats (sem and mbox counts, etc). + */ +#ifndef SYS_STATS +#define SYS_STATS (NO_SYS == 0) +#endif + +#else + +#define LINK_STATS 0 +#define IP_STATS 0 +#define IPFRAG_STATS 0 +#define ICMP_STATS 0 +#define IGMP_STATS 0 +#define UDP_STATS 0 +#define TCP_STATS 0 +#define MEM_STATS 0 +#define MEMP_STATS 0 +#define SYS_STATS 0 +#define LWIP_STATS_DISPLAY 1 + +#endif /* LWIP_STATS */ + +/* + --------------------------------- + ---------- PPP options ---------- + --------------------------------- +*/ +/** + * PPP_SUPPORT==1: Enable PPP. + */ +#ifndef PPP_SUPPORT +#define PPP_SUPPORT 0 +#endif + +/** + * PPPOE_SUPPORT==1: Enable PPP Over Ethernet + */ +#ifndef PPPOE_SUPPORT +#define PPPOE_SUPPORT 0 +#endif + +/** + * PPPOS_SUPPORT==1: Enable PPP Over Serial + */ +#ifndef PPPOS_SUPPORT +#define PPPOS_SUPPORT PPP_SUPPORT +#endif + +#if PPP_SUPPORT + +/** + * NUM_PPP: Max PPP sessions. + */ +#ifndef NUM_PPP +#define NUM_PPP 1 +#endif + +/** + * PAP_SUPPORT==1: Support PAP. + */ +#ifndef PAP_SUPPORT +#define PAP_SUPPORT 0 +#endif + +/** + * CHAP_SUPPORT==1: Support CHAP. + */ +#ifndef CHAP_SUPPORT +#define CHAP_SUPPORT 0 +#endif + +/** + * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef MSCHAP_SUPPORT +#define MSCHAP_SUPPORT 0 +#endif + +/** + * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CBCP_SUPPORT +#define CBCP_SUPPORT 0 +#endif + +/** + * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CCP_SUPPORT +#define CCP_SUPPORT 0 +#endif + +/** + * VJ_SUPPORT==1: Support VJ header compression. + */ +#ifndef VJ_SUPPORT +#define VJ_SUPPORT 0 +#endif + +/** + * MD5_SUPPORT==1: Support MD5 (see also CHAP). + */ +#ifndef MD5_SUPPORT +#define MD5_SUPPORT 0 +#endif + +/* + * Timeouts + */ +#ifndef FSM_DEFTIMEOUT +#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef FSM_DEFMAXTERMREQS +#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXCONFREQS +#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXNAKLOOPS +#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */ +#endif + +#ifndef UPAP_DEFTIMEOUT +#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */ +#endif + +#ifndef UPAP_DEFREQTIME +#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */ +#endif + +#ifndef CHAP_DEFTIMEOUT +#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef CHAP_DEFTRANSMITS +#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */ +#endif + +/* Interval in seconds between keepalive echo requests, 0 to disable. */ +#ifndef LCP_ECHOINTERVAL +#define LCP_ECHOINTERVAL 0 +#endif + +/* Number of unanswered echo requests before failure. */ +#ifndef LCP_MAXECHOFAILS +#define LCP_MAXECHOFAILS 3 +#endif + +/* Max Xmit idle time (in jiffies) before resend flag char. */ +#ifndef PPP_MAXIDLEFLAG +#define PPP_MAXIDLEFLAG 100 +#endif + +/* + * Packet sizes + * + * Note - lcp shouldn't be allowed to negotiate stuff outside these + * limits. See lcp.h in the pppd directory. + * (XXX - these constants should simply be shared by lcp.c instead + * of living in lcp.h) + */ +#define PPP_MTU 1500 /* Default MTU (size of Info field) */ +#ifndef PPP_MAXMTU +/* #define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) */ +#define PPP_MAXMTU 1500 /* Largest MTU we allow */ +#endif +#define PPP_MINMTU 64 +#define PPP_MRU 1500 /* default MRU = max length of info field */ +#define PPP_MAXMRU 1500 /* Largest MRU we allow */ +#ifndef PPP_DEFMRU +#define PPP_DEFMRU 296 /* Try for this */ +#endif +#define PPP_MINMRU 128 /* No MRUs below this */ + +#ifndef MAXNAMELEN +#define MAXNAMELEN 256 /* max length of hostname or name for auth */ +#endif +#ifndef MAXSECRETLEN +#define MAXSECRETLEN 256 /* max length of password or secret */ +#endif + +#endif /* PPP_SUPPORT */ + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ +/** + * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets. + */ +#ifndef CHECKSUM_GEN_IP +#define CHECKSUM_GEN_IP 1 +#endif + +/** + * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets. + */ +#ifndef CHECKSUM_GEN_UDP +#define CHECKSUM_GEN_UDP 1 +#endif + +/** + * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets. + */ +#ifndef CHECKSUM_GEN_TCP +#define CHECKSUM_GEN_TCP 1 +#endif + +/** + * CHECKSUM_GEN_ICMP==1: Generate checksums in software for outgoing ICMP packets. + */ +#ifndef CHECKSUM_GEN_ICMP +#define CHECKSUM_GEN_ICMP 1 +#endif + +/** + * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets. + */ +#ifndef CHECKSUM_CHECK_IP +#define CHECKSUM_CHECK_IP 1 +#endif + +/** + * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets. + */ +#ifndef CHECKSUM_CHECK_UDP +#define CHECKSUM_CHECK_UDP 1 +#endif + +/** + * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets. + */ +#ifndef CHECKSUM_CHECK_TCP +#define CHECKSUM_CHECK_TCP 1 +#endif + +/** + * LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from + * application buffers to pbufs. + */ +#ifndef LWIP_CHECKSUM_ON_COPY +#define LWIP_CHECKSUM_ON_COPY 0 +#endif + +/* + --------------------------------------- + ---------- Hook options --------------- + --------------------------------------- +*/ + +/* Hooks are undefined by default, define them to a function if you need them. */ + +/** + * LWIP_HOOK_IP4_INPUT(pbuf, input_netif): + * - called from ip_input() (IPv4) + * - pbuf: received struct pbuf passed to ip_input() + * - input_netif: struct netif on which the packet has been received + * Return values: + * - 0: Hook has not consumed the packet, packet is processed as normal + * - != 0: Hook has consumed the packet. + * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook + * (i.e. free it when done). + */ + +/** + * LWIP_HOOK_IP4_ROUTE(dest): + * - called from ip_route() (IPv4) + * - dest: destination IPv4 address + * Returns the destination netif or NULL if no destination netif is found. In + * that case, ip_route() continues as normal. + */ + +/* + --------------------------------------- + ---------- Debugging options ---------- + --------------------------------------- +*/ +/** + * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is + * compared against this value. If it is smaller, then debugging + * messages are written. + */ +#ifndef LWIP_DBG_MIN_LEVEL +#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL +#endif + +/** + * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable + * debug messages of certain types. + */ +#ifndef LWIP_DBG_TYPES_ON +#define LWIP_DBG_TYPES_ON LWIP_DBG_ON +#endif + +/** + * ETHARP_DEBUG: Enable debugging in etharp.c. + */ +#ifndef ETHARP_DEBUG +#define ETHARP_DEBUG LWIP_DBG_OFF +#endif + +/** + * NETIF_DEBUG: Enable debugging in netif.c. + */ +#ifndef NETIF_DEBUG +#define NETIF_DEBUG LWIP_DBG_OFF +#endif + +/** + * PBUF_DEBUG: Enable debugging in pbuf.c. + */ +#ifndef PBUF_DEBUG +#define PBUF_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_LIB_DEBUG: Enable debugging in api_lib.c. + */ +#ifndef API_LIB_DEBUG +#define API_LIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_MSG_DEBUG: Enable debugging in api_msg.c. + */ +#ifndef API_MSG_DEBUG +#define API_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SOCKETS_DEBUG: Enable debugging in sockets.c. + */ +#ifndef SOCKETS_DEBUG +#define SOCKETS_DEBUG LWIP_DBG_OFF +#endif + +/** + * ICMP_DEBUG: Enable debugging in icmp.c. + */ +#ifndef ICMP_DEBUG +#define ICMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IGMP_DEBUG: Enable debugging in igmp.c. + */ +#ifndef IGMP_DEBUG +#define IGMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * INET_DEBUG: Enable debugging in inet.c. + */ +#ifndef INET_DEBUG +#define INET_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_DEBUG: Enable debugging for IP. + */ +#ifndef IP_DEBUG +#define IP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass. + */ +#ifndef IP_REASS_DEBUG +#define IP_REASS_DEBUG LWIP_DBG_OFF +#endif + +/** + * RAW_DEBUG: Enable debugging in raw.c. + */ +#ifndef RAW_DEBUG +#define RAW_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEM_DEBUG: Enable debugging in mem.c. + */ +#ifndef MEM_DEBUG +#define MEM_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEMP_DEBUG: Enable debugging in memp.c. + */ +#ifndef MEMP_DEBUG +#define MEMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SYS_DEBUG: Enable debugging in sys.c. + */ +#ifndef SYS_DEBUG +#define SYS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TIMERS_DEBUG: Enable debugging in timers.c. + */ +#ifndef TIMERS_DEBUG +#define TIMERS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_DEBUG: Enable debugging for TCP. + */ +#ifndef TCP_DEBUG +#define TCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug. + */ +#ifndef TCP_INPUT_DEBUG +#define TCP_INPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit. + */ +#ifndef TCP_FR_DEBUG +#define TCP_FR_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit + * timeout. + */ +#ifndef TCP_RTO_DEBUG +#define TCP_RTO_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_CWND_DEBUG: Enable debugging for TCP congestion window. + */ +#ifndef TCP_CWND_DEBUG +#define TCP_CWND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating. + */ +#ifndef TCP_WND_DEBUG +#define TCP_WND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions. + */ +#ifndef TCP_OUTPUT_DEBUG +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RST_DEBUG: Enable debugging for TCP with the RST message. + */ +#ifndef TCP_RST_DEBUG +#define TCP_RST_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths. + */ +#ifndef TCP_QLEN_DEBUG +#define TCP_QLEN_DEBUG LWIP_DBG_OFF +#endif + +/** + * UDP_DEBUG: Enable debugging in UDP. + */ +#ifndef UDP_DEBUG +#define UDP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCPIP_DEBUG: Enable debugging in tcpip.c. + */ +#ifndef TCPIP_DEBUG +#define TCPIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * PPP_DEBUG: Enable debugging for PPP. + */ +#ifndef PPP_DEBUG +#define PPP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SLIP_DEBUG: Enable debugging in slipif.c. + */ +#ifndef SLIP_DEBUG +#define SLIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * DHCP_DEBUG: Enable debugging in dhcp.c. + */ +#ifndef DHCP_DEBUG +#define DHCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * AUTOIP_DEBUG: Enable debugging in autoip.c. + */ +#ifndef AUTOIP_DEBUG +#define AUTOIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MSG_DEBUG: Enable debugging for SNMP messages. + */ +#ifndef SNMP_MSG_DEBUG +#define SNMP_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs. + */ +#ifndef SNMP_MIB_DEBUG +#define SNMP_MIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * DNS_DEBUG: Enable debugging for DNS. + */ +#ifndef DNS_DEBUG +#define DNS_DEBUG LWIP_DBG_OFF +#endif + +#endif /* __LWIP_OPT_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/pbuf.h b/Project/externalModules/lwip_v141/src/include/lwip/pbuf.h new file mode 100644 index 0000000..6dbdf9b --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/pbuf.h @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __LWIP_PBUF_H__ +#define __LWIP_PBUF_H__ + +#include "lwip/opt.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** Currently, the pbuf_custom code is only needed for one specific configuration + * of IP_FRAG */ +#define LWIP_SUPPORT_CUSTOM_PBUF (IP_FRAG && !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF) + +#define PBUF_WIFI_TRANSPORT_HLEN 16 +#define PBUF_TRANSPORT_HLEN 20 +#define PBUF_IP_HLEN 20 + +typedef enum { + PBUF_TRANSPORT, + PBUF_IP, + PBUF_LINK, + PBUF_RAW +} pbuf_layer; + +typedef enum { + PBUF_RAM, /* pbuf data is stored in RAM */ + PBUF_ROM, /* pbuf data is stored in ROM */ + PBUF_REF, /* pbuf comes from the pbuf pool */ + PBUF_POOL /* pbuf payload refers to RAM */ +} pbuf_type; + + +/** indicates this packet's data should be immediately passed to the application */ +#define PBUF_FLAG_PUSH 0x01U +/** indicates this is a custom pbuf: pbuf_free and pbuf_header handle such a + a pbuf differently */ +#define PBUF_FLAG_IS_CUSTOM 0x02U +/** indicates this pbuf is UDP multicast to be looped back */ +#define PBUF_FLAG_MCASTLOOP 0x04U +/** indicates this pbuf was received as link-level broadcast */ +#define PBUF_FLAG_LLBCAST 0x08U +/** indicates this pbuf was received as link-level multicast */ +#define PBUF_FLAG_LLMCAST 0x10U +/** indicates this pbuf includes a TCP FIN flag */ +#define PBUF_FLAG_TCP_FIN 0x20U + +struct pbuf { + /** next pbuf in singly linked pbuf chain */ + struct pbuf *next; + + /** pointer to the actual data in the buffer */ + void *payload; + + /** + * total length of this buffer and all next buffers in chain + * belonging to the same packet. + * + * For non-queue packet chains this is the invariant: + * p->tot_len == p->len + (p->next? p->next->tot_len: 0) + */ + u16_t tot_len; + + /** length of this buffer */ + u16_t len; + + /** pbuf_type as u8_t instead of enum to save space */ + u8_t /*pbuf_type*/ type; + + /** misc flags */ + u8_t flags; + + /** + * the reference count always equals the number of pointers + * that refer to this pbuf. This can be pointers from an application, + * the stack itself, or pbuf->next pointers from a chain. + */ + u16_t ref; +}; + +#if LWIP_SUPPORT_CUSTOM_PBUF +/** Prototype for a function to free a custom pbuf */ +typedef void (*pbuf_free_custom_fn)(struct pbuf *p); + +/** A custom pbuf: like a pbuf, but following a function pointer to free it. */ +struct pbuf_custom { + /** The actual pbuf */ + struct pbuf pbuf; + /** This function is called when pbuf_free deallocates this pbuf(_custom) */ + pbuf_free_custom_fn custom_free_function; +}; +#endif /* LWIP_SUPPORT_CUSTOM_PBUF */ + +#if LWIP_TCP && TCP_QUEUE_OOSEQ +/** Define this to 0 to prevent freeing ooseq pbufs when the PBUF_POOL is empty */ +#ifndef PBUF_POOL_FREE_OOSEQ +#define PBUF_POOL_FREE_OOSEQ 1 +#endif /* PBUF_POOL_FREE_OOSEQ */ +#if NO_SYS && PBUF_POOL_FREE_OOSEQ +extern volatile u8_t pbuf_free_ooseq_pending; +void pbuf_free_ooseq(); +/** When not using sys_check_timeouts(), call PBUF_CHECK_FREE_OOSEQ() + at regular intervals from main level to check if ooseq pbufs need to be + freed! */ +#define PBUF_CHECK_FREE_OOSEQ() do { if(pbuf_free_ooseq_pending) { \ + /* pbuf_alloc() reported PBUF_POOL to be empty -> try to free some \ + ooseq queued pbufs now */ \ + pbuf_free_ooseq(); }}while(0) +#endif /* NO_SYS && PBUF_POOL_FREE_OOSEQ*/ +#endif /* LWIP_TCP && TCP_QUEUE_OOSEQ */ + +/* Initializes the pbuf module. This call is empty for now, but may not be in future. */ +#define pbuf_init() + +struct pbuf *pbuf_alloc(pbuf_layer l, u16_t length, pbuf_type type); +#if LWIP_SUPPORT_CUSTOM_PBUF +struct pbuf *pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type, + struct pbuf_custom *p, void *payload_mem, + u16_t payload_mem_len); +#endif /* LWIP_SUPPORT_CUSTOM_PBUF */ +void pbuf_realloc(struct pbuf *p, u16_t size); +u8_t pbuf_header(struct pbuf *p, s16_t header_size); +void pbuf_ref(struct pbuf *p); +u8_t pbuf_free(struct pbuf *p); +u8_t pbuf_clen(struct pbuf *p); +void pbuf_cat(struct pbuf *head, struct pbuf *tail); +void pbuf_chain(struct pbuf *head, struct pbuf *tail); +struct pbuf *pbuf_dechain(struct pbuf *p); +err_t pbuf_copy(struct pbuf *p_to, struct pbuf *p_from); +u16_t pbuf_copy_partial(struct pbuf *p, void *dataptr, u16_t len, u16_t offset); +err_t pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len); +struct pbuf *pbuf_coalesce(struct pbuf *p, pbuf_layer layer); +#if LWIP_CHECKSUM_ON_COPY +err_t pbuf_fill_chksum(struct pbuf *p, u16_t start_offset, const void *dataptr, + u16_t len, u16_t *chksum); +#endif /* LWIP_CHECKSUM_ON_COPY */ + +u8_t pbuf_get_at(struct pbuf* p, u16_t offset); +u16_t pbuf_memcmp(struct pbuf* p, u16_t offset, const void* s2, u16_t n); +u16_t pbuf_memfind(struct pbuf* p, const void* mem, u16_t mem_len, u16_t start_offset); +u16_t pbuf_strstr(struct pbuf* p, const char* substr); + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_PBUF_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/raw.h b/Project/externalModules/lwip_v141/src/include/lwip/raw.h new file mode 100644 index 0000000..1a56700 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/raw.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_RAW_H__ +#define __LWIP_RAW_H__ + +#include "lwip/opt.h" + +#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/def.h" +#include "lwip/ip.h" +#include "lwip/ip_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct raw_pcb; + +/** Function prototype for raw pcb receive callback functions. + * @param arg user supplied argument (raw_pcb.recv_arg) + * @param pcb the raw_pcb which received data + * @param p the packet buffer that was received + * @param addr the remote IP address from which the packet was received + * @return 1 if the packet was 'eaten' (aka. deleted), + * 0 if the packet lives on + * If returning 1, the callback is responsible for freeing the pbuf + * if it's not used any more. + */ +typedef u8_t (*raw_recv_fn)(void *arg, struct raw_pcb *pcb, struct pbuf *p, + ip_addr_t *addr); + +struct raw_pcb { + /* Common members of all PCB types */ + IP_PCB; + + struct raw_pcb *next; + + u8_t protocol; + + /** receive callback function */ + raw_recv_fn recv; + /* user-supplied argument for the recv callback */ + void *recv_arg; +}; + +/* The following functions is the application layer interface to the + RAW code. */ +struct raw_pcb * raw_new (u8_t proto); +void raw_remove (struct raw_pcb *pcb); +err_t raw_bind (struct raw_pcb *pcb, ip_addr_t *ipaddr); +err_t raw_connect (struct raw_pcb *pcb, ip_addr_t *ipaddr); + +void raw_recv (struct raw_pcb *pcb, raw_recv_fn recv, void *recv_arg); +err_t raw_sendto (struct raw_pcb *pcb, struct pbuf *p, ip_addr_t *ipaddr); +err_t raw_send (struct raw_pcb *pcb, struct pbuf *p); + +/* The following functions are the lower layer interface to RAW. */ +u8_t raw_input (struct pbuf *p, struct netif *inp); +#define raw_init() /* Compatibility define, not init needed. */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_RAW */ + +#endif /* __LWIP_RAW_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/sio.h b/Project/externalModules/lwip_v141/src/include/lwip/sio.h new file mode 100644 index 0000000..39d778b --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/sio.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + */ + +/* + * This is the interface to the platform specific serial IO module + * It needs to be implemented by those platforms which need SLIP or PPP + */ + +#ifndef __SIO_H__ +#define __SIO_H__ + +#include "lwip/arch.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* If you want to define sio_fd_t elsewhere or differently, + define this in your cc.h file. */ +#ifndef __sio_fd_t_defined +typedef void * sio_fd_t; +#endif + +/* The following functions can be defined to something else in your cc.h file + or be implemented in your custom sio.c file. */ + +#ifndef sio_open +/** + * Opens a serial device for communication. + * + * @param devnum device number + * @return handle to serial device if successful, NULL otherwise + */ +sio_fd_t sio_open(u8_t devnum); +#endif + +#ifndef sio_send +/** + * Sends a single character to the serial device. + * + * @param c character to send + * @param fd serial device handle + * + * @note This function will block until the character can be sent. + */ +void sio_send(u8_t c, sio_fd_t fd); +#endif + +#ifndef sio_recv +/** + * Receives a single character from the serial device. + * + * @param fd serial device handle + * + * @note This function will block until a character is received. + */ +u8_t sio_recv(sio_fd_t fd); +#endif + +#ifndef sio_read +/** + * Reads from the serial device. + * + * @param fd serial device handle + * @param data pointer to data buffer for receiving + * @param len maximum length (in bytes) of data to receive + * @return number of bytes actually received - may be 0 if aborted by sio_read_abort + * + * @note This function will block until data can be received. The blocking + * can be cancelled by calling sio_read_abort(). + */ +u32_t sio_read(sio_fd_t fd, u8_t *data, u32_t len); +#endif + +#ifndef sio_tryread +/** + * Tries to read from the serial device. Same as sio_read but returns + * immediately if no data is available and never blocks. + * + * @param fd serial device handle + * @param data pointer to data buffer for receiving + * @param len maximum length (in bytes) of data to receive + * @return number of bytes actually received + */ +u32_t sio_tryread(sio_fd_t fd, u8_t *data, u32_t len); +#endif + +#ifndef sio_write +/** + * Writes to the serial device. + * + * @param fd serial device handle + * @param data pointer to data to send + * @param len length (in bytes) of data to send + * @return number of bytes actually sent + * + * @note This function will block until all data can be sent. + */ +u32_t sio_write(sio_fd_t fd, u8_t *data, u32_t len); +#endif + +#ifndef sio_read_abort +/** + * Aborts a blocking sio_read() call. + * + * @param fd serial device handle + */ +void sio_read_abort(sio_fd_t fd); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __SIO_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/snmp.h b/Project/externalModules/lwip_v141/src/include/lwip/snmp.h new file mode 100644 index 0000000..3548ba2 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/snmp.h @@ -0,0 +1,367 @@ +/* + * Copyright (c) 2001, 2002 Leon Woestenberg + * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Leon Woestenberg + * + */ +#ifndef __LWIP_SNMP_H__ +#define __LWIP_SNMP_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include "lwip/ip_addr.h" + +struct udp_pcb; +struct netif; + +/** + * @see RFC1213, "MIB-II, 6. Definitions" + */ +enum snmp_ifType { + snmp_ifType_other=1, /* none of the following */ + snmp_ifType_regular1822, + snmp_ifType_hdh1822, + snmp_ifType_ddn_x25, + snmp_ifType_rfc877_x25, + snmp_ifType_ethernet_csmacd, + snmp_ifType_iso88023_csmacd, + snmp_ifType_iso88024_tokenBus, + snmp_ifType_iso88025_tokenRing, + snmp_ifType_iso88026_man, + snmp_ifType_starLan, + snmp_ifType_proteon_10Mbit, + snmp_ifType_proteon_80Mbit, + snmp_ifType_hyperchannel, + snmp_ifType_fddi, + snmp_ifType_lapb, + snmp_ifType_sdlc, + snmp_ifType_ds1, /* T-1 */ + snmp_ifType_e1, /* european equiv. of T-1 */ + snmp_ifType_basicISDN, + snmp_ifType_primaryISDN, /* proprietary serial */ + snmp_ifType_propPointToPointSerial, + snmp_ifType_ppp, + snmp_ifType_softwareLoopback, + snmp_ifType_eon, /* CLNP over IP [11] */ + snmp_ifType_ethernet_3Mbit, + snmp_ifType_nsip, /* XNS over IP */ + snmp_ifType_slip, /* generic SLIP */ + snmp_ifType_ultra, /* ULTRA technologies */ + snmp_ifType_ds3, /* T-3 */ + snmp_ifType_sip, /* SMDS */ + snmp_ifType_frame_relay +}; + +#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ + +/** SNMP "sysuptime" Interval */ +#define SNMP_SYSUPTIME_INTERVAL 10 + +/** fixed maximum length for object identifier type */ +#define LWIP_SNMP_OBJ_ID_LEN 32 + +/** internal object identifier representation */ +struct snmp_obj_id +{ + u8_t len; + s32_t id[LWIP_SNMP_OBJ_ID_LEN]; +}; + +/* system */ +void snmp_set_sysdesr(u8_t* str, u8_t* len); +void snmp_set_sysobjid(struct snmp_obj_id *oid); +void snmp_get_sysobjid_ptr(struct snmp_obj_id **oid); +void snmp_inc_sysuptime(void); +void snmp_add_sysuptime(u32_t value); +void snmp_get_sysuptime(u32_t *value); +void snmp_set_syscontact(u8_t *ocstr, u8_t *ocstrlen); +void snmp_set_sysname(u8_t *ocstr, u8_t *ocstrlen); +void snmp_set_syslocation(u8_t *ocstr, u8_t *ocstrlen); + +/* network interface */ +void snmp_add_ifinoctets(struct netif *ni, u32_t value); +void snmp_inc_ifinucastpkts(struct netif *ni); +void snmp_inc_ifinnucastpkts(struct netif *ni); +void snmp_inc_ifindiscards(struct netif *ni); +void snmp_add_ifoutoctets(struct netif *ni, u32_t value); +void snmp_inc_ifoutucastpkts(struct netif *ni); +void snmp_inc_ifoutnucastpkts(struct netif *ni); +void snmp_inc_ifoutdiscards(struct netif *ni); +void snmp_inc_iflist(void); +void snmp_dec_iflist(void); + +/* ARP (for atTable and ipNetToMediaTable) */ +void snmp_insert_arpidx_tree(struct netif *ni, ip_addr_t *ip); +void snmp_delete_arpidx_tree(struct netif *ni, ip_addr_t *ip); + +/* IP */ +void snmp_inc_ipinreceives(void); +void snmp_inc_ipinhdrerrors(void); +void snmp_inc_ipinaddrerrors(void); +void snmp_inc_ipforwdatagrams(void); +void snmp_inc_ipinunknownprotos(void); +void snmp_inc_ipindiscards(void); +void snmp_inc_ipindelivers(void); +void snmp_inc_ipoutrequests(void); +void snmp_inc_ipoutdiscards(void); +void snmp_inc_ipoutnoroutes(void); +void snmp_inc_ipreasmreqds(void); +void snmp_inc_ipreasmoks(void); +void snmp_inc_ipreasmfails(void); +void snmp_inc_ipfragoks(void); +void snmp_inc_ipfragfails(void); +void snmp_inc_ipfragcreates(void); +void snmp_inc_iproutingdiscards(void); +void snmp_insert_ipaddridx_tree(struct netif *ni); +void snmp_delete_ipaddridx_tree(struct netif *ni); +void snmp_insert_iprteidx_tree(u8_t dflt, struct netif *ni); +void snmp_delete_iprteidx_tree(u8_t dflt, struct netif *ni); + +/* ICMP */ +void snmp_inc_icmpinmsgs(void); +void snmp_inc_icmpinerrors(void); +void snmp_inc_icmpindestunreachs(void); +void snmp_inc_icmpintimeexcds(void); +void snmp_inc_icmpinparmprobs(void); +void snmp_inc_icmpinsrcquenchs(void); +void snmp_inc_icmpinredirects(void); +void snmp_inc_icmpinechos(void); +void snmp_inc_icmpinechoreps(void); +void snmp_inc_icmpintimestamps(void); +void snmp_inc_icmpintimestampreps(void); +void snmp_inc_icmpinaddrmasks(void); +void snmp_inc_icmpinaddrmaskreps(void); +void snmp_inc_icmpoutmsgs(void); +void snmp_inc_icmpouterrors(void); +void snmp_inc_icmpoutdestunreachs(void); +void snmp_inc_icmpouttimeexcds(void); +void snmp_inc_icmpoutparmprobs(void); +void snmp_inc_icmpoutsrcquenchs(void); +void snmp_inc_icmpoutredirects(void); +void snmp_inc_icmpoutechos(void); +void snmp_inc_icmpoutechoreps(void); +void snmp_inc_icmpouttimestamps(void); +void snmp_inc_icmpouttimestampreps(void); +void snmp_inc_icmpoutaddrmasks(void); +void snmp_inc_icmpoutaddrmaskreps(void); + +/* TCP */ +void snmp_inc_tcpactiveopens(void); +void snmp_inc_tcppassiveopens(void); +void snmp_inc_tcpattemptfails(void); +void snmp_inc_tcpestabresets(void); +void snmp_inc_tcpinsegs(void); +void snmp_inc_tcpoutsegs(void); +void snmp_inc_tcpretranssegs(void); +void snmp_inc_tcpinerrs(void); +void snmp_inc_tcpoutrsts(void); + +/* UDP */ +void snmp_inc_udpindatagrams(void); +void snmp_inc_udpnoports(void); +void snmp_inc_udpinerrors(void); +void snmp_inc_udpoutdatagrams(void); +void snmp_insert_udpidx_tree(struct udp_pcb *pcb); +void snmp_delete_udpidx_tree(struct udp_pcb *pcb); + +/* SNMP */ +void snmp_inc_snmpinpkts(void); +void snmp_inc_snmpoutpkts(void); +void snmp_inc_snmpinbadversions(void); +void snmp_inc_snmpinbadcommunitynames(void); +void snmp_inc_snmpinbadcommunityuses(void); +void snmp_inc_snmpinasnparseerrs(void); +void snmp_inc_snmpintoobigs(void); +void snmp_inc_snmpinnosuchnames(void); +void snmp_inc_snmpinbadvalues(void); +void snmp_inc_snmpinreadonlys(void); +void snmp_inc_snmpingenerrs(void); +void snmp_add_snmpintotalreqvars(u8_t value); +void snmp_add_snmpintotalsetvars(u8_t value); +void snmp_inc_snmpingetrequests(void); +void snmp_inc_snmpingetnexts(void); +void snmp_inc_snmpinsetrequests(void); +void snmp_inc_snmpingetresponses(void); +void snmp_inc_snmpintraps(void); +void snmp_inc_snmpouttoobigs(void); +void snmp_inc_snmpoutnosuchnames(void); +void snmp_inc_snmpoutbadvalues(void); +void snmp_inc_snmpoutgenerrs(void); +void snmp_inc_snmpoutgetrequests(void); +void snmp_inc_snmpoutgetnexts(void); +void snmp_inc_snmpoutsetrequests(void); +void snmp_inc_snmpoutgetresponses(void); +void snmp_inc_snmpouttraps(void); +void snmp_get_snmpgrpid_ptr(struct snmp_obj_id **oid); +void snmp_set_snmpenableauthentraps(u8_t *value); +void snmp_get_snmpenableauthentraps(u8_t *value); + +/* LWIP_SNMP support not available */ +/* define everything to be empty */ +#else + +/* system */ +#define snmp_set_sysdesr(str, len) +#define snmp_set_sysobjid(oid); +#define snmp_get_sysobjid_ptr(oid) +#define snmp_inc_sysuptime() +#define snmp_add_sysuptime(value) +#define snmp_get_sysuptime(value) +#define snmp_set_syscontact(ocstr, ocstrlen); +#define snmp_set_sysname(ocstr, ocstrlen); +#define snmp_set_syslocation(ocstr, ocstrlen); + +/* network interface */ +#define snmp_add_ifinoctets(ni,value) +#define snmp_inc_ifinucastpkts(ni) +#define snmp_inc_ifinnucastpkts(ni) +#define snmp_inc_ifindiscards(ni) +#define snmp_add_ifoutoctets(ni,value) +#define snmp_inc_ifoutucastpkts(ni) +#define snmp_inc_ifoutnucastpkts(ni) +#define snmp_inc_ifoutdiscards(ni) +#define snmp_inc_iflist() +#define snmp_dec_iflist() + +/* ARP */ +#define snmp_insert_arpidx_tree(ni,ip) +#define snmp_delete_arpidx_tree(ni,ip) + +/* IP */ +#define snmp_inc_ipinreceives() +#define snmp_inc_ipinhdrerrors() +#define snmp_inc_ipinaddrerrors() +#define snmp_inc_ipforwdatagrams() +#define snmp_inc_ipinunknownprotos() +#define snmp_inc_ipindiscards() +#define snmp_inc_ipindelivers() +#define snmp_inc_ipoutrequests() +#define snmp_inc_ipoutdiscards() +#define snmp_inc_ipoutnoroutes() +#define snmp_inc_ipreasmreqds() +#define snmp_inc_ipreasmoks() +#define snmp_inc_ipreasmfails() +#define snmp_inc_ipfragoks() +#define snmp_inc_ipfragfails() +#define snmp_inc_ipfragcreates() +#define snmp_inc_iproutingdiscards() +#define snmp_insert_ipaddridx_tree(ni) +#define snmp_delete_ipaddridx_tree(ni) +#define snmp_insert_iprteidx_tree(dflt, ni) +#define snmp_delete_iprteidx_tree(dflt, ni) + +/* ICMP */ +#define snmp_inc_icmpinmsgs() +#define snmp_inc_icmpinerrors() +#define snmp_inc_icmpindestunreachs() +#define snmp_inc_icmpintimeexcds() +#define snmp_inc_icmpinparmprobs() +#define snmp_inc_icmpinsrcquenchs() +#define snmp_inc_icmpinredirects() +#define snmp_inc_icmpinechos() +#define snmp_inc_icmpinechoreps() +#define snmp_inc_icmpintimestamps() +#define snmp_inc_icmpintimestampreps() +#define snmp_inc_icmpinaddrmasks() +#define snmp_inc_icmpinaddrmaskreps() +#define snmp_inc_icmpoutmsgs() +#define snmp_inc_icmpouterrors() +#define snmp_inc_icmpoutdestunreachs() +#define snmp_inc_icmpouttimeexcds() +#define snmp_inc_icmpoutparmprobs() +#define snmp_inc_icmpoutsrcquenchs() +#define snmp_inc_icmpoutredirects() +#define snmp_inc_icmpoutechos() +#define snmp_inc_icmpoutechoreps() +#define snmp_inc_icmpouttimestamps() +#define snmp_inc_icmpouttimestampreps() +#define snmp_inc_icmpoutaddrmasks() +#define snmp_inc_icmpoutaddrmaskreps() +/* TCP */ +#define snmp_inc_tcpactiveopens() +#define snmp_inc_tcppassiveopens() +#define snmp_inc_tcpattemptfails() +#define snmp_inc_tcpestabresets() +#define snmp_inc_tcpinsegs() +#define snmp_inc_tcpoutsegs() +#define snmp_inc_tcpretranssegs() +#define snmp_inc_tcpinerrs() +#define snmp_inc_tcpoutrsts() + +/* UDP */ +#define snmp_inc_udpindatagrams() +#define snmp_inc_udpnoports() +#define snmp_inc_udpinerrors() +#define snmp_inc_udpoutdatagrams() +#define snmp_insert_udpidx_tree(pcb) +#define snmp_delete_udpidx_tree(pcb) + +/* SNMP */ +#define snmp_inc_snmpinpkts() +#define snmp_inc_snmpoutpkts() +#define snmp_inc_snmpinbadversions() +#define snmp_inc_snmpinbadcommunitynames() +#define snmp_inc_snmpinbadcommunityuses() +#define snmp_inc_snmpinasnparseerrs() +#define snmp_inc_snmpintoobigs() +#define snmp_inc_snmpinnosuchnames() +#define snmp_inc_snmpinbadvalues() +#define snmp_inc_snmpinreadonlys() +#define snmp_inc_snmpingenerrs() +#define snmp_add_snmpintotalreqvars(value) +#define snmp_add_snmpintotalsetvars(value) +#define snmp_inc_snmpingetrequests() +#define snmp_inc_snmpingetnexts() +#define snmp_inc_snmpinsetrequests() +#define snmp_inc_snmpingetresponses() +#define snmp_inc_snmpintraps() +#define snmp_inc_snmpouttoobigs() +#define snmp_inc_snmpoutnosuchnames() +#define snmp_inc_snmpoutbadvalues() +#define snmp_inc_snmpoutgenerrs() +#define snmp_inc_snmpoutgetrequests() +#define snmp_inc_snmpoutgetnexts() +#define snmp_inc_snmpoutsetrequests() +#define snmp_inc_snmpoutgetresponses() +#define snmp_inc_snmpouttraps() +#define snmp_get_snmpgrpid_ptr(oid) +#define snmp_set_snmpenableauthentraps(value) +#define snmp_get_snmpenableauthentraps(value) + +#endif /* LWIP_SNMP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_SNMP_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/snmp_asn1.h b/Project/externalModules/lwip_v141/src/include/lwip/snmp_asn1.h new file mode 100644 index 0000000..fbfb68b --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/snmp_asn1.h @@ -0,0 +1,101 @@ +/** + * @file + * Abstract Syntax Notation One (ISO 8824, 8825) codec. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#ifndef __LWIP_SNMP_ASN1_H__ +#define __LWIP_SNMP_ASN1_H__ + +#include "lwip/opt.h" +#include "lwip/err.h" +#include "lwip/pbuf.h" +#include "lwip/snmp.h" + +#if LWIP_SNMP + +#ifdef __cplusplus +extern "C" { +#endif + +#define SNMP_ASN1_UNIV (0) /* (!0x80 | !0x40) */ +#define SNMP_ASN1_APPLIC (0x40) /* (!0x80 | 0x40) */ +#define SNMP_ASN1_CONTXT (0x80) /* ( 0x80 | !0x40) */ + +#define SNMP_ASN1_CONSTR (0x20) /* ( 0x20) */ +#define SNMP_ASN1_PRIMIT (0) /* (!0x20) */ + +/* universal tags */ +#define SNMP_ASN1_INTEG 2 +#define SNMP_ASN1_OC_STR 4 +#define SNMP_ASN1_NUL 5 +#define SNMP_ASN1_OBJ_ID 6 +#define SNMP_ASN1_SEQ 16 + +/* application specific (SNMP) tags */ +#define SNMP_ASN1_IPADDR 0 /* octet string size(4) */ +#define SNMP_ASN1_COUNTER 1 /* u32_t */ +#define SNMP_ASN1_GAUGE 2 /* u32_t */ +#define SNMP_ASN1_TIMETICKS 3 /* u32_t */ +#define SNMP_ASN1_OPAQUE 4 /* octet string */ + +/* context specific (SNMP) tags */ +#define SNMP_ASN1_PDU_GET_REQ 0 +#define SNMP_ASN1_PDU_GET_NEXT_REQ 1 +#define SNMP_ASN1_PDU_GET_RESP 2 +#define SNMP_ASN1_PDU_SET_REQ 3 +#define SNMP_ASN1_PDU_TRAP 4 + +err_t snmp_asn1_dec_type(struct pbuf *p, u16_t ofs, u8_t *type); +err_t snmp_asn1_dec_length(struct pbuf *p, u16_t ofs, u8_t *octets_used, u16_t *length); +err_t snmp_asn1_dec_u32t(struct pbuf *p, u16_t ofs, u16_t len, u32_t *value); +err_t snmp_asn1_dec_s32t(struct pbuf *p, u16_t ofs, u16_t len, s32_t *value); +err_t snmp_asn1_dec_oid(struct pbuf *p, u16_t ofs, u16_t len, struct snmp_obj_id *oid); +err_t snmp_asn1_dec_raw(struct pbuf *p, u16_t ofs, u16_t len, u16_t raw_len, u8_t *raw); + +void snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed); +void snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed); +void snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed); +void snmp_asn1_enc_oid_cnt(u8_t ident_len, s32_t *ident, u16_t *octets_needed); +err_t snmp_asn1_enc_type(struct pbuf *p, u16_t ofs, u8_t type); +err_t snmp_asn1_enc_length(struct pbuf *p, u16_t ofs, u16_t length); +err_t snmp_asn1_enc_u32t(struct pbuf *p, u16_t ofs, u16_t octets_needed, u32_t value); +err_t snmp_asn1_enc_s32t(struct pbuf *p, u16_t ofs, u16_t octets_needed, s32_t value); +err_t snmp_asn1_enc_oid(struct pbuf *p, u16_t ofs, u8_t ident_len, s32_t *ident); +err_t snmp_asn1_enc_raw(struct pbuf *p, u16_t ofs, u16_t raw_len, u8_t *raw); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_SNMP */ + +#endif /* __LWIP_SNMP_ASN1_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/snmp_msg.h b/Project/externalModules/lwip_v141/src/include/lwip/snmp_msg.h new file mode 100644 index 0000000..656924e --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/snmp_msg.h @@ -0,0 +1,315 @@ +/** + * @file + * SNMP Agent message handling structures. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#ifndef __LWIP_SNMP_MSG_H__ +#define __LWIP_SNMP_MSG_H__ + +#include "lwip/opt.h" +#include "lwip/snmp.h" +#include "lwip/snmp_structs.h" +#include "lwip/ip_addr.h" +#include "lwip/err.h" + +#if LWIP_SNMP + +#if SNMP_PRIVATE_MIB +/* When using a private MIB, you have to create a file 'private_mib.h' that contains + * a 'struct mib_array_node mib_private' which contains your MIB. */ +#include "private_mib.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* The listen port of the SNMP agent. Clients have to make their requests to + this port. Most standard clients won't work if you change this! */ +#ifndef SNMP_IN_PORT +#define SNMP_IN_PORT 161 +#endif +/* The remote port the SNMP agent sends traps to. Most standard trap sinks won't + work if you change this! */ +#ifndef SNMP_TRAP_PORT +#define SNMP_TRAP_PORT 162 +#endif + +#define SNMP_ES_NOERROR 0 +#define SNMP_ES_TOOBIG 1 +#define SNMP_ES_NOSUCHNAME 2 +#define SNMP_ES_BADVALUE 3 +#define SNMP_ES_READONLY 4 +#define SNMP_ES_GENERROR 5 + +#define SNMP_GENTRAP_COLDSTART 0 +#define SNMP_GENTRAP_WARMSTART 1 +#define SNMP_GENTRAP_AUTHFAIL 4 +#define SNMP_GENTRAP_ENTERPRISESPC 6 + +struct snmp_varbind +{ + /* next pointer, NULL for last in list */ + struct snmp_varbind *next; + /* previous pointer, NULL for first in list */ + struct snmp_varbind *prev; + + /* object identifier length (in s32_t) */ + u8_t ident_len; + /* object identifier array */ + s32_t *ident; + + /* object value ASN1 type */ + u8_t value_type; + /* object value length (in u8_t) */ + u8_t value_len; + /* object value */ + void *value; + + /* encoding varbind seq length length */ + u8_t seqlenlen; + /* encoding object identifier length length */ + u8_t olenlen; + /* encoding object value length length */ + u8_t vlenlen; + /* encoding varbind seq length */ + u16_t seqlen; + /* encoding object identifier length */ + u16_t olen; + /* encoding object value length */ + u16_t vlen; +}; + +struct snmp_varbind_root +{ + struct snmp_varbind *head; + struct snmp_varbind *tail; + /* number of variable bindings in list */ + u8_t count; + /* encoding varbind-list seq length length */ + u8_t seqlenlen; + /* encoding varbind-list seq length */ + u16_t seqlen; +}; + +/** output response message header length fields */ +struct snmp_resp_header_lengths +{ + /* encoding error-index length length */ + u8_t erridxlenlen; + /* encoding error-status length length */ + u8_t errstatlenlen; + /* encoding request id length length */ + u8_t ridlenlen; + /* encoding pdu length length */ + u8_t pdulenlen; + /* encoding community length length */ + u8_t comlenlen; + /* encoding version length length */ + u8_t verlenlen; + /* encoding sequence length length */ + u8_t seqlenlen; + + /* encoding error-index length */ + u16_t erridxlen; + /* encoding error-status length */ + u16_t errstatlen; + /* encoding request id length */ + u16_t ridlen; + /* encoding pdu length */ + u16_t pdulen; + /* encoding community length */ + u16_t comlen; + /* encoding version length */ + u16_t verlen; + /* encoding sequence length */ + u16_t seqlen; +}; + +/** output response message header length fields */ +struct snmp_trap_header_lengths +{ + /* encoding timestamp length length */ + u8_t tslenlen; + /* encoding specific-trap length length */ + u8_t strplenlen; + /* encoding generic-trap length length */ + u8_t gtrplenlen; + /* encoding agent-addr length length */ + u8_t aaddrlenlen; + /* encoding enterprise-id length length */ + u8_t eidlenlen; + /* encoding pdu length length */ + u8_t pdulenlen; + /* encoding community length length */ + u8_t comlenlen; + /* encoding version length length */ + u8_t verlenlen; + /* encoding sequence length length */ + u8_t seqlenlen; + + /* encoding timestamp length */ + u16_t tslen; + /* encoding specific-trap length */ + u16_t strplen; + /* encoding generic-trap length */ + u16_t gtrplen; + /* encoding agent-addr length */ + u16_t aaddrlen; + /* encoding enterprise-id length */ + u16_t eidlen; + /* encoding pdu length */ + u16_t pdulen; + /* encoding community length */ + u16_t comlen; + /* encoding version length */ + u16_t verlen; + /* encoding sequence length */ + u16_t seqlen; +}; + +/* Accepting new SNMP messages. */ +#define SNMP_MSG_EMPTY 0 +/* Search for matching object for variable binding. */ +#define SNMP_MSG_SEARCH_OBJ 1 +/* Perform SNMP operation on in-memory object. + Pass-through states, for symmetry only. */ +#define SNMP_MSG_INTERNAL_GET_OBJDEF 2 +#define SNMP_MSG_INTERNAL_GET_VALUE 3 +#define SNMP_MSG_INTERNAL_SET_TEST 4 +#define SNMP_MSG_INTERNAL_GET_OBJDEF_S 5 +#define SNMP_MSG_INTERNAL_SET_VALUE 6 +/* Perform SNMP operation on object located externally. + In theory this could be used for building a proxy agent. + Practical use is for an enterprise spc. app. gateway. */ +#define SNMP_MSG_EXTERNAL_GET_OBJDEF 7 +#define SNMP_MSG_EXTERNAL_GET_VALUE 8 +#define SNMP_MSG_EXTERNAL_SET_TEST 9 +#define SNMP_MSG_EXTERNAL_GET_OBJDEF_S 10 +#define SNMP_MSG_EXTERNAL_SET_VALUE 11 + +#define SNMP_COMMUNITY_STR_LEN 64 +struct snmp_msg_pstat +{ + /* lwIP local port (161) binding */ + struct udp_pcb *pcb; + /* source IP address */ + ip_addr_t sip; + /* source UDP port */ + u16_t sp; + /* request type */ + u8_t rt; + /* request ID */ + s32_t rid; + /* error status */ + s32_t error_status; + /* error index */ + s32_t error_index; + /* community name (zero terminated) */ + u8_t community[SNMP_COMMUNITY_STR_LEN + 1]; + /* community string length (exclusive zero term) */ + u8_t com_strlen; + /* one out of MSG_EMPTY, MSG_DEMUX, MSG_INTERNAL, MSG_EXTERNAL_x */ + u8_t state; + /* saved arguments for MSG_EXTERNAL_x */ + struct mib_external_node *ext_mib_node; + struct snmp_name_ptr ext_name_ptr; + struct obj_def ext_object_def; + struct snmp_obj_id ext_oid; + /* index into input variable binding list */ + u8_t vb_idx; + /* ptr into input variable binding list */ + struct snmp_varbind *vb_ptr; + /* list of variable bindings from input */ + struct snmp_varbind_root invb; + /* list of variable bindings to output */ + struct snmp_varbind_root outvb; + /* output response lengths used in ASN encoding */ + struct snmp_resp_header_lengths rhl; +}; + +struct snmp_msg_trap +{ + /* lwIP local port (161) binding */ + struct udp_pcb *pcb; + /* destination IP address in network order */ + ip_addr_t dip; + + /* source enterprise ID (sysObjectID) */ + struct snmp_obj_id *enterprise; + /* source IP address, raw network order format */ + u8_t sip_raw[4]; + /* generic trap code */ + u32_t gen_trap; + /* specific trap code */ + u32_t spc_trap; + /* timestamp */ + u32_t ts; + /* list of variable bindings to output */ + struct snmp_varbind_root outvb; + /* output trap lengths used in ASN encoding */ + struct snmp_trap_header_lengths thl; +}; + +/** Agent Version constant, 0 = v1 oddity */ +extern const s32_t snmp_version; +/** Agent default "public" community string */ +extern const char snmp_publiccommunity[7]; + +extern struct snmp_msg_trap trap_msg; + +/** Agent setup, start listening to port 161. */ +void snmp_init(void); +void snmp_trap_dst_enable(u8_t dst_idx, u8_t enable); +void snmp_trap_dst_ip_set(u8_t dst_idx, ip_addr_t *dst); + +/** Varbind-list functions. */ +struct snmp_varbind* snmp_varbind_alloc(struct snmp_obj_id *oid, u8_t type, u8_t len); +void snmp_varbind_free(struct snmp_varbind *vb); +void snmp_varbind_list_free(struct snmp_varbind_root *root); +void snmp_varbind_tail_add(struct snmp_varbind_root *root, struct snmp_varbind *vb); +struct snmp_varbind* snmp_varbind_tail_remove(struct snmp_varbind_root *root); + +/** Handle an internal (recv) or external (private response) event. */ +void snmp_msg_event(u8_t request_id); +err_t snmp_send_response(struct snmp_msg_pstat *m_stat); +err_t snmp_send_trap(s8_t generic_trap, struct snmp_obj_id *eoid, s32_t specific_trap); +void snmp_coldstart_trap(void); +void snmp_authfail_trap(void); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_SNMP */ + +#endif /* __LWIP_SNMP_MSG_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/snmp_structs.h b/Project/externalModules/lwip_v141/src/include/lwip/snmp_structs.h new file mode 100644 index 0000000..f7193b9 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/snmp_structs.h @@ -0,0 +1,268 @@ +/** + * @file + * Generic MIB tree structures. + * + * @todo namespace prefixes + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#ifndef __LWIP_SNMP_STRUCTS_H__ +#define __LWIP_SNMP_STRUCTS_H__ + +#include "lwip/opt.h" + +#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/snmp.h" + +#if SNMP_PRIVATE_MIB +/* When using a private MIB, you have to create a file 'private_mib.h' that contains + * a 'struct mib_array_node mib_private' which contains your MIB. */ +#include "private_mib.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* MIB object instance */ +#define MIB_OBJECT_NONE 0 +#define MIB_OBJECT_SCALAR 1 +#define MIB_OBJECT_TAB 2 + +/* MIB access types */ +#define MIB_ACCESS_READ 1 +#define MIB_ACCESS_WRITE 2 + +/* MIB object access */ +#define MIB_OBJECT_READ_ONLY MIB_ACCESS_READ +#define MIB_OBJECT_READ_WRITE (MIB_ACCESS_READ | MIB_ACCESS_WRITE) +#define MIB_OBJECT_WRITE_ONLY MIB_ACCESS_WRITE +#define MIB_OBJECT_NOT_ACCESSIBLE 0 + +/** object definition returned by (get_object_def)() */ +struct obj_def +{ + /* MIB_OBJECT_NONE (0), MIB_OBJECT_SCALAR (1), MIB_OBJECT_TAB (2) */ + u8_t instance; + /* 0 read-only, 1 read-write, 2 write-only, 3 not-accessible */ + u8_t access; + /* ASN type for this object */ + u8_t asn_type; + /* value length (host length) */ + u16_t v_len; + /* length of instance part of supplied object identifier */ + u8_t id_inst_len; + /* instance part of supplied object identifier */ + s32_t *id_inst_ptr; +}; + +struct snmp_name_ptr +{ + u8_t ident_len; + s32_t *ident; +}; + +/** MIB const scalar (.0) node */ +#define MIB_NODE_SC 0x01 +/** MIB const array node */ +#define MIB_NODE_AR 0x02 +/** MIB array node (mem_malloced from RAM) */ +#define MIB_NODE_RA 0x03 +/** MIB list root node (mem_malloced from RAM) */ +#define MIB_NODE_LR 0x04 +/** MIB node for external objects */ +#define MIB_NODE_EX 0x05 + +/** node "base class" layout, the mandatory fields for a node */ +struct mib_node +{ + /** returns struct obj_def for the given object identifier */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + /** returns object value for the given object identifier, + @note the caller must allocate at least len bytes for the value */ + void (*get_value)(struct obj_def *od, u16_t len, void *value); + /** tests length and/or range BEFORE setting */ + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + /** sets object value, only to be called when set_test() */ + void (*set_value)(struct obj_def *od, u16_t len, void *value); + /** One out of MIB_NODE_AR, MIB_NODE_LR or MIB_NODE_EX */ + u8_t node_type; + /* array or max list length */ + u16_t maxlength; +}; + +/** derived node for scalars .0 index */ +typedef struct mib_node mib_scalar_node; + +/** derived node, points to a fixed size const array + of sub-identifiers plus a 'child' pointer */ +struct mib_array_node +{ + /* inherited "base class" members */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + u8_t node_type; + u16_t maxlength; + + /* additional struct members */ + const s32_t *objid; + struct mib_node* const *nptr; +}; + +/** derived node, points to a fixed size mem_malloced array + of sub-identifiers plus a 'child' pointer */ +struct mib_ram_array_node +{ + /* inherited "base class" members */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + u8_t node_type; + u16_t maxlength; + + /* aditional struct members */ + s32_t *objid; + struct mib_node **nptr; +}; + +struct mib_list_node +{ + struct mib_list_node *prev; + struct mib_list_node *next; + s32_t objid; + struct mib_node *nptr; +}; + +/** derived node, points to a doubly linked list + of sub-identifiers plus a 'child' pointer */ +struct mib_list_rootnode +{ + /* inherited "base class" members */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + u8_t node_type; + u16_t maxlength; + + /* additional struct members */ + struct mib_list_node *head; + struct mib_list_node *tail; + /* counts list nodes in list */ + u16_t count; +}; + +/** derived node, has access functions for mib object in external memory or device + using 'tree_level' and 'idx', with a range 0 .. (level_length() - 1) */ +struct mib_external_node +{ + /* inherited "base class" members */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + u8_t node_type; + u16_t maxlength; + + /* additional struct members */ + /** points to an external (in memory) record of some sort of addressing + information, passed to and interpreted by the funtions below */ + void* addr_inf; + /** tree levels under this node */ + u8_t tree_levels; + /** number of objects at this level */ + u16_t (*level_length)(void* addr_inf, u8_t level); + /** compares object sub identifier with external id + return zero when equal, nonzero when unequal */ + s32_t (*ident_cmp)(void* addr_inf, u8_t level, u16_t idx, s32_t sub_id); + void (*get_objid)(void* addr_inf, u8_t level, u16_t idx, s32_t *sub_id); + + /** async Questions */ + void (*get_object_def_q)(void* addr_inf, u8_t rid, u8_t ident_len, s32_t *ident); + void (*get_value_q)(u8_t rid, struct obj_def *od); + void (*set_test_q)(u8_t rid, struct obj_def *od); + void (*set_value_q)(u8_t rid, struct obj_def *od, u16_t len, void *value); + /** async Answers */ + void (*get_object_def_a)(u8_t rid, u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); + u8_t (*set_test_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); + void (*set_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); + /** async Panic Close (agent returns error reply, + e.g. used for external transaction cleanup) */ + void (*get_object_def_pc)(u8_t rid, u8_t ident_len, s32_t *ident); + void (*get_value_pc)(u8_t rid, struct obj_def *od); + void (*set_test_pc)(u8_t rid, struct obj_def *od); + void (*set_value_pc)(u8_t rid, struct obj_def *od); +}; + +/** export MIB tree from mib2.c */ +extern const struct mib_array_node internet; + +/** dummy function pointers for non-leaf MIB nodes from mib2.c */ +void noleafs_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +void noleafs_get_value(struct obj_def *od, u16_t len, void *value); +u8_t noleafs_set_test(struct obj_def *od, u16_t len, void *value); +void noleafs_set_value(struct obj_def *od, u16_t len, void *value); + +void snmp_oidtoip(s32_t *ident, ip_addr_t *ip); +void snmp_iptooid(ip_addr_t *ip, s32_t *ident); +void snmp_ifindextonetif(s32_t ifindex, struct netif **netif); +void snmp_netiftoifindex(struct netif *netif, s32_t *ifidx); + +struct mib_list_node* snmp_mib_ln_alloc(s32_t id); +void snmp_mib_ln_free(struct mib_list_node *ln); +struct mib_list_rootnode* snmp_mib_lrn_alloc(void); +void snmp_mib_lrn_free(struct mib_list_rootnode *lrn); + +s8_t snmp_mib_node_insert(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **insn); +s8_t snmp_mib_node_find(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **fn); +struct mib_list_rootnode *snmp_mib_node_delete(struct mib_list_rootnode *rn, struct mib_list_node *n); + +struct mib_node* snmp_search_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_name_ptr *np); +struct mib_node* snmp_expand_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret); +u8_t snmp_iso_prefix_tst(u8_t ident_len, s32_t *ident); +u8_t snmp_iso_prefix_expand(u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_SNMP */ + +#endif /* __LWIP_SNMP_STRUCTS_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/sockets.h b/Project/externalModules/lwip_v141/src/include/lwip/sockets.h new file mode 100644 index 0000000..d1fbc63 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/sockets.h @@ -0,0 +1,379 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + + +#ifndef __LWIP_SOCKETS_H__ +#define __LWIP_SOCKETS_H__ + +#include "lwip/opt.h" + +#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ + +#include /* for size_t */ + +#include "lwip/ip_addr.h" +#include "lwip/inet.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* members are in network byte order */ +struct sockaddr_in { + u8_t sin_len; + u8_t sin_family; + u16_t sin_port; + struct in_addr sin_addr; + char sin_zero[8]; +}; + +struct sockaddr { + u8_t sa_len; + u8_t sa_family; + char sa_data[14]; +}; + +/* If your port already typedef's socklen_t, define SOCKLEN_T_DEFINED + to prevent this code from redefining it. */ +#if !defined(socklen_t) && !defined(SOCKLEN_T_DEFINED) +typedef u32_t socklen_t; +#endif + +/* Socket protocol types (TCP/UDP/RAW) */ +#define SOCK_STREAM 1 +#define SOCK_DGRAM 2 +#define SOCK_RAW 3 + +/* + * Option flags per-socket. These must match the SOF_ flags in ip.h (checked in init.c) + */ +#define SO_DEBUG 0x0001 /* Unimplemented: turn on debugging info recording */ +#define SO_ACCEPTCONN 0x0002 /* socket has had listen() */ +#define SO_REUSEADDR 0x0004 /* Allow local address reuse */ +#define SO_KEEPALIVE 0x0008 /* keep connections alive */ +#define SO_DONTROUTE 0x0010 /* Unimplemented: just use interface addresses */ +#define SO_BROADCAST 0x0020 /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */ +#define SO_USELOOPBACK 0x0040 /* Unimplemented: bypass hardware when possible */ +#define SO_LINGER 0x0080 /* linger on close if data present */ +#define SO_OOBINLINE 0x0100 /* Unimplemented: leave received OOB data in line */ +#define SO_REUSEPORT 0x0200 /* Unimplemented: allow local address & port reuse */ + +#define SO_DONTLINGER ((int)(~SO_LINGER)) + +/* + * Additional options, not kept in so_options. + */ +#define SO_SNDBUF 0x1001 /* Unimplemented: send buffer size */ +#define SO_RCVBUF 0x1002 /* receive buffer size */ +#define SO_SNDLOWAT 0x1003 /* Unimplemented: send low-water mark */ +#define SO_RCVLOWAT 0x1004 /* Unimplemented: receive low-water mark */ +#define SO_SNDTIMEO 0x1005 /* Unimplemented: send timeout */ +#define SO_RCVTIMEO 0x1006 /* receive timeout */ +#define SO_ERROR 0x1007 /* get error status and clear */ +#define SO_TYPE 0x1008 /* get socket type */ +#define SO_CONTIMEO 0x1009 /* Unimplemented: connect timeout */ +#define SO_NO_CHECK 0x100a /* don't create UDP checksum */ + + +/* + * Structure used for manipulating linger option. + */ +struct linger { + int l_onoff; /* option on/off */ + int l_linger; /* linger time */ +}; + +/* + * Level number for (get/set)sockopt() to apply to socket itself. + */ +#define SOL_SOCKET 0xfff /* options for socket level */ + + +#define AF_UNSPEC 0 +#define AF_INET 2 +#define PF_INET AF_INET +#define PF_UNSPEC AF_UNSPEC + +#define IPPROTO_IP 0 +#define IPPROTO_TCP 6 +#define IPPROTO_UDP 17 +#define IPPROTO_UDPLITE 136 + +/* Flags we can use with send and recv. */ +#define MSG_PEEK 0x01 /* Peeks at an incoming message */ +#define MSG_WAITALL 0x02 /* Unimplemented: Requests that the function block until the full amount of data requested can be returned */ +#define MSG_OOB 0x04 /* Unimplemented: Requests out-of-band data. The significance and semantics of out-of-band data are protocol-specific */ +#define MSG_DONTWAIT 0x08 /* Nonblocking i/o for this operation only */ +#define MSG_MORE 0x10 /* Sender will send more */ + + +/* + * Options for level IPPROTO_IP + */ +#define IP_TOS 1 +#define IP_TTL 2 + +#if LWIP_TCP +/* + * Options for level IPPROTO_TCP + */ +#define TCP_NODELAY 0x01 /* don't delay send to coalesce packets */ +#define TCP_KEEPALIVE 0x02 /* send KEEPALIVE probes when idle for pcb->keep_idle milliseconds */ +#define TCP_KEEPIDLE 0x03 /* set pcb->keep_idle - Same as TCP_KEEPALIVE, but use seconds for get/setsockopt */ +#define TCP_KEEPINTVL 0x04 /* set pcb->keep_intvl - Use seconds for get/setsockopt */ +#define TCP_KEEPCNT 0x05 /* set pcb->keep_cnt - Use number of probes sent for get/setsockopt */ +#endif /* LWIP_TCP */ + +#if LWIP_UDP && LWIP_UDPLITE +/* + * Options for level IPPROTO_UDPLITE + */ +#define UDPLITE_SEND_CSCOV 0x01 /* sender checksum coverage */ +#define UDPLITE_RECV_CSCOV 0x02 /* minimal receiver checksum coverage */ +#endif /* LWIP_UDP && LWIP_UDPLITE*/ + + +#if LWIP_IGMP +/* + * Options and types for UDP multicast traffic handling + */ +#define IP_ADD_MEMBERSHIP 3 +#define IP_DROP_MEMBERSHIP 4 +#define IP_MULTICAST_TTL 5 +#define IP_MULTICAST_IF 6 +#define IP_MULTICAST_LOOP 7 + +typedef struct ip_mreq { + struct in_addr imr_multiaddr; /* IP multicast address of group */ + struct in_addr imr_interface; /* local IP address of interface */ +} ip_mreq; +#endif /* LWIP_IGMP */ + +/* + * The Type of Service provides an indication of the abstract + * parameters of the quality of service desired. These parameters are + * to be used to guide the selection of the actual service parameters + * when transmitting a datagram through a particular network. Several + * networks offer service precedence, which somehow treats high + * precedence traffic as more important than other traffic (generally + * by accepting only traffic above a certain precedence at time of high + * load). The major choice is a three way tradeoff between low-delay, + * high-reliability, and high-throughput. + * The use of the Delay, Throughput, and Reliability indications may + * increase the cost (in some sense) of the service. In many networks + * better performance for one of these parameters is coupled with worse + * performance on another. Except for very unusual cases at most two + * of these three indications should be set. + */ +#define IPTOS_TOS_MASK 0x1E +#define IPTOS_TOS(tos) ((tos) & IPTOS_TOS_MASK) +#define IPTOS_LOWDELAY 0x10 +#define IPTOS_THROUGHPUT 0x08 +#define IPTOS_RELIABILITY 0x04 +#define IPTOS_LOWCOST 0x02 +#define IPTOS_MINCOST IPTOS_LOWCOST + +/* + * The Network Control precedence designation is intended to be used + * within a network only. The actual use and control of that + * designation is up to each network. The Internetwork Control + * designation is intended for use by gateway control originators only. + * If the actual use of these precedence designations is of concern to + * a particular network, it is the responsibility of that network to + * control the access to, and use of, those precedence designations. + */ +#define IPTOS_PREC_MASK 0xe0 +#define IPTOS_PREC(tos) ((tos) & IPTOS_PREC_MASK) +#define IPTOS_PREC_NETCONTROL 0xe0 +#define IPTOS_PREC_INTERNETCONTROL 0xc0 +#define IPTOS_PREC_CRITIC_ECP 0xa0 +#define IPTOS_PREC_FLASHOVERRIDE 0x80 +#define IPTOS_PREC_FLASH 0x60 +#define IPTOS_PREC_IMMEDIATE 0x40 +#define IPTOS_PREC_PRIORITY 0x20 +#define IPTOS_PREC_ROUTINE 0x00 + + +/* + * Commands for ioctlsocket(), taken from the BSD file fcntl.h. + * lwip_ioctl only supports FIONREAD and FIONBIO, for now + * + * Ioctl's have the command encoded in the lower word, + * and the size of any in or out parameters in the upper + * word. The high 2 bits of the upper word are used + * to encode the in/out status of the parameter; for now + * we restrict parameters to at most 128 bytes. + */ +#if !defined(FIONREAD) || !defined(FIONBIO) +#define IOCPARM_MASK 0x7fU /* parameters must be < 128 bytes */ +#define IOC_VOID 0x20000000UL /* no parameters */ +#define IOC_OUT 0x40000000UL /* copy out parameters */ +#define IOC_IN 0x80000000UL /* copy in parameters */ +#define IOC_INOUT (IOC_IN|IOC_OUT) + /* 0x20000000 distinguishes new & + old ioctl's */ +#define _IO(x,y) (IOC_VOID|((x)<<8)|(y)) + +#define _IOR(x,y,t) (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) + +#define _IOW(x,y,t) (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) +#endif /* !defined(FIONREAD) || !defined(FIONBIO) */ + +#ifndef FIONREAD +#define FIONREAD _IOR('f', 127, unsigned long) /* get # bytes to read */ +#endif +#ifndef FIONBIO +#define FIONBIO _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */ +#endif + +/* Socket I/O Controls: unimplemented */ +#ifndef SIOCSHIWAT +#define SIOCSHIWAT _IOW('s', 0, unsigned long) /* set high watermark */ +#define SIOCGHIWAT _IOR('s', 1, unsigned long) /* get high watermark */ +#define SIOCSLOWAT _IOW('s', 2, unsigned long) /* set low watermark */ +#define SIOCGLOWAT _IOR('s', 3, unsigned long) /* get low watermark */ +#define SIOCATMARK _IOR('s', 7, unsigned long) /* at oob mark? */ +#endif + +/* commands for fnctl */ +#ifndef F_GETFL +#define F_GETFL 3 +#endif +#ifndef F_SETFL +#define F_SETFL 4 +#endif + +/* File status flags and file access modes for fnctl, + these are bits in an int. */ +#ifndef O_NONBLOCK +#define O_NONBLOCK 1 /* nonblocking I/O */ +#endif +#ifndef O_NDELAY +#define O_NDELAY 1 /* same as O_NONBLOCK, for compatibility */ +#endif + +#ifndef SHUT_RD + #define SHUT_RD 0 + #define SHUT_WR 1 + #define SHUT_RDWR 2 +#endif + +/* FD_SET used for lwip_select */ +#ifndef FD_SET + #undef FD_SETSIZE + /* Make FD_SETSIZE match NUM_SOCKETS in socket.c */ + #define FD_SETSIZE MEMP_NUM_NETCONN + #define FD_SET(n, p) ((p)->fd_bits[(n)/8] |= (1 << ((n) & 7))) + #define FD_CLR(n, p) ((p)->fd_bits[(n)/8] &= ~(1 << ((n) & 7))) + #define FD_ISSET(n,p) ((p)->fd_bits[(n)/8] & (1 << ((n) & 7))) + #define FD_ZERO(p) memset((void*)(p),0,sizeof(*(p))) + + typedef struct fd_set { + unsigned char fd_bits [(FD_SETSIZE+7)/8]; + } fd_set; + +#endif /* FD_SET */ + +/** LWIP_TIMEVAL_PRIVATE: if you want to use the struct timeval provided + * by your system, set this to 0 and include in cc.h */ +#ifndef LWIP_TIMEVAL_PRIVATE +#define LWIP_TIMEVAL_PRIVATE 1 +#endif + +#if LWIP_TIMEVAL_PRIVATE +struct timeval { + long tv_sec; /* seconds */ + long tv_usec; /* and microseconds */ +}; +#endif /* LWIP_TIMEVAL_PRIVATE */ + +void lwip_socket_init(void); + +int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen); +int lwip_bind(int s, const struct sockaddr *name, socklen_t namelen); +int lwip_shutdown(int s, int how); +int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen); +int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen); +int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen); +int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen); +int lwip_close(int s); +int lwip_connect(int s, const struct sockaddr *name, socklen_t namelen); +int lwip_listen(int s, int backlog); +int lwip_recv(int s, void *mem, size_t len, int flags); +int lwip_read(int s, void *mem, size_t len); +int lwip_recvfrom(int s, void *mem, size_t len, int flags, + struct sockaddr *from, socklen_t *fromlen); +int lwip_send(int s, const void *dataptr, size_t size, int flags); +int lwip_sendto(int s, const void *dataptr, size_t size, int flags, + const struct sockaddr *to, socklen_t tolen); +int lwip_socket(int domain, int type, int protocol); +int lwip_write(int s, const void *dataptr, size_t size); +int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, + struct timeval *timeout); +int lwip_ioctl(int s, long cmd, void *argp); +int lwip_fcntl(int s, int cmd, int val); + +#if LWIP_COMPAT_SOCKETS +#define accept(a,b,c) lwip_accept(a,b,c) +#define bind(a,b,c) lwip_bind(a,b,c) +#define shutdown(a,b) lwip_shutdown(a,b) +#define closesocket(s) lwip_close(s) +#define connect(a,b,c) lwip_connect(a,b,c) +#define getsockname(a,b,c) lwip_getsockname(a,b,c) +#define getpeername(a,b,c) lwip_getpeername(a,b,c) +#define setsockopt(a,b,c,d,e) lwip_setsockopt(a,b,c,d,e) +#define getsockopt(a,b,c,d,e) lwip_getsockopt(a,b,c,d,e) +#define listen(a,b) lwip_listen(a,b) +#define recv(a,b,c,d) lwip_recv(a,b,c,d) +#define recvfrom(a,b,c,d,e,f) lwip_recvfrom(a,b,c,d,e,f) +#define send(a,b,c,d) lwip_send(a,b,c,d) +#define sendto(a,b,c,d,e,f) lwip_sendto(a,b,c,d,e,f) +#define socket(a,b,c) lwip_socket(a,b,c) +#define select(a,b,c,d,e) lwip_select(a,b,c,d,e) +#define ioctlsocket(a,b,c) lwip_ioctl(a,b,c) + +#if LWIP_POSIX_SOCKETS_IO_NAMES +#define read(a,b,c) lwip_read(a,b,c) +#define write(a,b,c) lwip_write(a,b,c) +#define close(s) lwip_close(s) +#define fcntl(a,b,c) lwip_fcntl(a,b,c) +#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */ + +#endif /* LWIP_COMPAT_SOCKETS */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_SOCKET */ + +#endif /* __LWIP_SOCKETS_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/stats.h b/Project/externalModules/lwip_v141/src/include/lwip/stats.h new file mode 100644 index 0000000..7e0764d --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/stats.h @@ -0,0 +1,292 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_STATS_H__ +#define __LWIP_STATS_H__ + +#include "lwip/opt.h" + +#include "lwip/mem.h" +#include "lwip/memp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_STATS + +#ifndef LWIP_STATS_LARGE +#define LWIP_STATS_LARGE 0 +#endif + +#if LWIP_STATS_LARGE +#define STAT_COUNTER u32_t +#define STAT_COUNTER_F U32_F +#else +#define STAT_COUNTER u16_t +#define STAT_COUNTER_F U16_F +#endif + +struct stats_proto { + STAT_COUNTER xmit; /* Transmitted packets. */ + STAT_COUNTER recv; /* Received packets. */ + STAT_COUNTER fw; /* Forwarded packets. */ + STAT_COUNTER drop; /* Dropped packets. */ + STAT_COUNTER chkerr; /* Checksum error. */ + STAT_COUNTER lenerr; /* Invalid length error. */ + STAT_COUNTER memerr; /* Out of memory error. */ + STAT_COUNTER rterr; /* Routing error. */ + STAT_COUNTER proterr; /* Protocol error. */ + STAT_COUNTER opterr; /* Error in options. */ + STAT_COUNTER err; /* Misc error. */ + STAT_COUNTER cachehit; +}; + +struct stats_igmp { + STAT_COUNTER xmit; /* Transmitted packets. */ + STAT_COUNTER recv; /* Received packets. */ + STAT_COUNTER drop; /* Dropped packets. */ + STAT_COUNTER chkerr; /* Checksum error. */ + STAT_COUNTER lenerr; /* Invalid length error. */ + STAT_COUNTER memerr; /* Out of memory error. */ + STAT_COUNTER proterr; /* Protocol error. */ + STAT_COUNTER rx_v1; /* Received v1 frames. */ + STAT_COUNTER rx_group; /* Received group-specific queries. */ + STAT_COUNTER rx_general; /* Received general queries. */ + STAT_COUNTER rx_report; /* Received reports. */ + STAT_COUNTER tx_join; /* Sent joins. */ + STAT_COUNTER tx_leave; /* Sent leaves. */ + STAT_COUNTER tx_report; /* Sent reports. */ +}; + +struct stats_mem { +#ifdef LWIP_DEBUG + const char *name; +#endif /* LWIP_DEBUG */ + mem_size_t avail; + mem_size_t used; + mem_size_t max; + STAT_COUNTER err; + STAT_COUNTER illegal; +}; + +struct stats_syselem { + STAT_COUNTER used; + STAT_COUNTER max; + STAT_COUNTER err; +}; + +struct stats_sys { + struct stats_syselem sem; + struct stats_syselem mutex; + struct stats_syselem mbox; +}; + +struct stats_ { +#if LINK_STATS + struct stats_proto link; +#endif +#if ETHARP_STATS + struct stats_proto etharp; +#endif +#if IPFRAG_STATS + struct stats_proto ip_frag; +#endif +#if IP_STATS + struct stats_proto ip; +#endif +#if ICMP_STATS + struct stats_proto icmp; +#endif +#if IGMP_STATS + struct stats_igmp igmp; +#endif +#if UDP_STATS + struct stats_proto udp; +#endif +#if TCP_STATS + struct stats_proto tcp; +#endif +#if MEM_STATS + struct stats_mem mem; +#endif +#if MEMP_STATS + struct stats_mem memp[MEMP_MAX]; +#endif +#if SYS_STATS + struct stats_sys sys; +#endif +}; + +extern struct stats_ lwip_stats; + +void stats_init(void); + +#define STATS_INC(x) ++lwip_stats.x +#define STATS_DEC(x) --lwip_stats.x +#define STATS_INC_USED(x, y) do { lwip_stats.x.used += y; \ + if (lwip_stats.x.max < lwip_stats.x.used) { \ + lwip_stats.x.max = lwip_stats.x.used; \ + } \ + } while(0) +#else /* LWIP_STATS */ +#define stats_init() +#define STATS_INC(x) +#define STATS_DEC(x) +#define STATS_INC_USED(x) +#endif /* LWIP_STATS */ + +#if TCP_STATS +#define TCP_STATS_INC(x) STATS_INC(x) +#define TCP_STATS_DISPLAY() stats_display_proto(&lwip_stats.tcp, "TCP") +#else +#define TCP_STATS_INC(x) +#define TCP_STATS_DISPLAY() +#endif + +#if UDP_STATS +#define UDP_STATS_INC(x) STATS_INC(x) +#define UDP_STATS_DISPLAY() stats_display_proto(&lwip_stats.udp, "UDP") +#else +#define UDP_STATS_INC(x) +#define UDP_STATS_DISPLAY() +#endif + +#if ICMP_STATS +#define ICMP_STATS_INC(x) STATS_INC(x) +#define ICMP_STATS_DISPLAY() stats_display_proto(&lwip_stats.icmp, "ICMP") +#else +#define ICMP_STATS_INC(x) +#define ICMP_STATS_DISPLAY() +#endif + +#if IGMP_STATS +#define IGMP_STATS_INC(x) STATS_INC(x) +#define IGMP_STATS_DISPLAY() stats_display_igmp(&lwip_stats.igmp) +#else +#define IGMP_STATS_INC(x) +#define IGMP_STATS_DISPLAY() +#endif + +#if IP_STATS +#define IP_STATS_INC(x) STATS_INC(x) +#define IP_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip, "IP") +#else +#define IP_STATS_INC(x) +#define IP_STATS_DISPLAY() +#endif + +#if IPFRAG_STATS +#define IPFRAG_STATS_INC(x) STATS_INC(x) +#define IPFRAG_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG") +#else +#define IPFRAG_STATS_INC(x) +#define IPFRAG_STATS_DISPLAY() +#endif + +#if ETHARP_STATS +#define ETHARP_STATS_INC(x) STATS_INC(x) +#define ETHARP_STATS_DISPLAY() stats_display_proto(&lwip_stats.etharp, "ETHARP") +#else +#define ETHARP_STATS_INC(x) +#define ETHARP_STATS_DISPLAY() +#endif + +#if LINK_STATS +#define LINK_STATS_INC(x) STATS_INC(x) +#define LINK_STATS_DISPLAY() stats_display_proto(&lwip_stats.link, "LINK") +#else +#define LINK_STATS_INC(x) +#define LINK_STATS_DISPLAY() +#endif + +#if MEM_STATS +#define MEM_STATS_AVAIL(x, y) lwip_stats.mem.x = y +#define MEM_STATS_INC(x) STATS_INC(mem.x) +#define MEM_STATS_INC_USED(x, y) STATS_INC_USED(mem, y) +#define MEM_STATS_DEC_USED(x, y) lwip_stats.mem.x -= y +#define MEM_STATS_DISPLAY() stats_display_mem(&lwip_stats.mem, "HEAP") +#else +#define MEM_STATS_AVAIL(x, y) +#define MEM_STATS_INC(x) +#define MEM_STATS_INC_USED(x, y) +#define MEM_STATS_DEC_USED(x, y) +#define MEM_STATS_DISPLAY() +#endif + +#if MEMP_STATS +#define MEMP_STATS_AVAIL(x, i, y) lwip_stats.memp[i].x = y +#define MEMP_STATS_INC(x, i) STATS_INC(memp[i].x) +#define MEMP_STATS_DEC(x, i) STATS_DEC(memp[i].x) +#define MEMP_STATS_INC_USED(x, i) STATS_INC_USED(memp[i], 1) +#define MEMP_STATS_DISPLAY(i) stats_display_memp(&lwip_stats.memp[i], i) +#else +#define MEMP_STATS_AVAIL(x, i, y) +#define MEMP_STATS_INC(x, i) +#define MEMP_STATS_DEC(x, i) +#define MEMP_STATS_INC_USED(x, i) +#define MEMP_STATS_DISPLAY(i) +#endif + +#if SYS_STATS +#define SYS_STATS_INC(x) STATS_INC(sys.x) +#define SYS_STATS_DEC(x) STATS_DEC(sys.x) +#define SYS_STATS_INC_USED(x) STATS_INC_USED(sys.x, 1) +#define SYS_STATS_DISPLAY() stats_display_sys(&lwip_stats.sys) +#else +#define SYS_STATS_INC(x) +#define SYS_STATS_DEC(x) +#define SYS_STATS_INC_USED(x) +#define SYS_STATS_DISPLAY() +#endif + +/* Display of statistics */ +#if LWIP_STATS_DISPLAY +void stats_display(void); +void stats_display_proto(struct stats_proto *proto, const char *name); +void stats_display_igmp(struct stats_igmp *igmp); +void stats_display_mem(struct stats_mem *mem, const char *name); +void stats_display_memp(struct stats_mem *mem, int index); +void stats_display_sys(struct stats_sys *sys); +#else /* LWIP_STATS_DISPLAY */ +#define stats_display() +#define stats_display_proto(proto, name) +#define stats_display_igmp(igmp) +#define stats_display_mem(mem, name) +#define stats_display_memp(mem, index) +#define stats_display_sys(sys) +#endif /* LWIP_STATS_DISPLAY */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_STATS_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/sys.h b/Project/externalModules/lwip_v141/src/include/lwip/sys.h new file mode 100644 index 0000000..8d9e9be --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/sys.h @@ -0,0 +1,340 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_SYS_H__ +#define __LWIP_SYS_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if NO_SYS + +/* For a totally minimal and standalone system, we provide null + definitions of the sys_ functions. */ +typedef u8_t sys_sem_t; +typedef u8_t sys_mutex_t; +typedef u8_t sys_mbox_t; + +#define sys_sem_new(s, c) ERR_OK +#define sys_sem_signal(s) +#define sys_sem_wait(s) +#define sys_arch_sem_wait(s,t) +#define sys_sem_free(s) +#define sys_sem_valid(s) 0 +#define sys_sem_set_invalid(s) +#define sys_mutex_new(mu) ERR_OK +#define sys_mutex_lock(mu) +#define sys_mutex_unlock(mu) +#define sys_mutex_free(mu) +#define sys_mutex_valid(mu) 0 +#define sys_mutex_set_invalid(mu) +#define sys_mbox_new(m, s) ERR_OK +#define sys_mbox_fetch(m,d) +#define sys_mbox_tryfetch(m,d) +#define sys_mbox_post(m,d) +#define sys_mbox_trypost(m,d) +#define sys_mbox_free(m) +#define sys_mbox_valid(m) +#define sys_mbox_set_invalid(m) + +#define sys_thread_new(n,t,a,s,p) + +#define sys_msleep(t) + +#else /* NO_SYS */ + +/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */ +#define SYS_ARCH_TIMEOUT 0xffffffffUL + +/** sys_mbox_tryfetch() returns SYS_MBOX_EMPTY if appropriate. + * For now we use the same magic value, but we allow this to change in future. + */ +#define SYS_MBOX_EMPTY SYS_ARCH_TIMEOUT + +#include "lwip/err.h" +#include "arch/sys_arch.h" + +/** Function prototype for thread functions */ +typedef void (*lwip_thread_fn)(void *arg); + +/* Function prototypes for functions to be implemented by platform ports + (in sys_arch.c) */ + +/* Mutex functions: */ + +/** Define LWIP_COMPAT_MUTEX if the port has no mutexes and binary semaphores + should be used instead */ +#if LWIP_COMPAT_MUTEX +/* for old ports that don't have mutexes: define them to binary semaphores */ +#define sys_mutex_t sys_sem_t +#define sys_mutex_new(mutex) sys_sem_new(mutex, 1) +#define sys_mutex_lock(mutex) sys_sem_wait(mutex) +#define sys_mutex_unlock(mutex) sys_sem_signal(mutex) +#define sys_mutex_free(mutex) sys_sem_free(mutex) +#define sys_mutex_valid(mutex) sys_sem_valid(mutex) +#define sys_mutex_set_invalid(mutex) sys_sem_set_invalid(mutex) + +#else /* LWIP_COMPAT_MUTEX */ + +/** Create a new mutex + * @param mutex pointer to the mutex to create + * @return a new mutex */ +err_t sys_mutex_new(sys_mutex_t *mutex); +/** Lock a mutex + * @param mutex the mutex to lock */ +void sys_mutex_lock(sys_mutex_t *mutex); +/** Unlock a mutex + * @param mutex the mutex to unlock */ +void sys_mutex_unlock(sys_mutex_t *mutex); +/** Delete a semaphore + * @param mutex the mutex to delete */ +void sys_mutex_free(sys_mutex_t *mutex); +#ifndef sys_mutex_valid +/** Check if a mutex is valid/allocated: return 1 for valid, 0 for invalid */ +int sys_mutex_valid(sys_mutex_t *mutex); +#endif +#ifndef sys_mutex_set_invalid +/** Set a mutex invalid so that sys_mutex_valid returns 0 */ +void sys_mutex_set_invalid(sys_mutex_t *mutex); +#endif +#endif /* LWIP_COMPAT_MUTEX */ + +/* Semaphore functions: */ + +/** Create a new semaphore + * @param sem pointer to the semaphore to create + * @param count initial count of the semaphore + * @return ERR_OK if successful, another err_t otherwise */ +err_t sys_sem_new(sys_sem_t *sem, u8_t count); +/** Signals a semaphore + * @param sem the semaphore to signal */ +void sys_sem_signal(sys_sem_t *sem); +#ifdef LWIP_SOCKET_SELECT_ENABLED +void sys_sem_signalI(sys_sem_t *sem); +#endif +/** Wait for a semaphore for the specified timeout + * @param sem the semaphore to wait for + * @param timeout timeout in milliseconds to wait (0 = wait forever) + * @return time (in milliseconds) waited for the semaphore + * or SYS_ARCH_TIMEOUT on timeout */ +u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout); +/** Delete a semaphore + * @param sem semaphore to delete */ +void sys_sem_free(sys_sem_t *sem); +/** Wait for a semaphore - forever/no timeout */ +#define sys_sem_wait(sem) sys_arch_sem_wait(sem, 0) +#ifndef sys_sem_valid +/** Check if a sempahore is valid/allocated: return 1 for valid, 0 for invalid */ +int sys_sem_valid(sys_sem_t *sem); +#endif +#ifndef sys_sem_set_invalid +/** Set a semaphore invalid so that sys_sem_valid returns 0 */ +void sys_sem_set_invalid(sys_sem_t *sem); +#endif + +/* Time functions. */ +#ifndef sys_msleep +void sys_msleep(u32_t ms); /* only has a (close to) 1 jiffy resolution. */ +#endif + +/* Mailbox functions. */ + +/** Create a new mbox of specified size + * @param mbox pointer to the mbox to create + * @param size (miminum) number of messages in this mbox + * @return ERR_OK if successful, another err_t otherwise */ +err_t sys_mbox_new(sys_mbox_t *mbox, int size); +/** Post a message to an mbox - may not fail + * -> blocks if full, only used from tasks not from ISR + * @param mbox mbox to posts the message + * @param msg message to post (ATTENTION: can be NULL) */ +void sys_mbox_post(sys_mbox_t *mbox, void *msg); +/** Try to post a message to an mbox - may fail if full or ISR + * @param mbox mbox to posts the message + * @param msg message to post (ATTENTION: can be NULL) */ +err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg); +/** Wait for a new message to arrive in the mbox + * @param mbox mbox to get a message from + * @param msg pointer where the message is stored + * @param timeout maximum time (in milliseconds) to wait for a message + * @return time (in milliseconds) waited for a message, may be 0 if not waited + or SYS_ARCH_TIMEOUT on timeout + * The returned time has to be accurate to prevent timer jitter! */ +u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout); +/* Allow port to override with a macro, e.g. special timout for sys_arch_mbox_fetch() */ +#ifndef sys_arch_mbox_tryfetch +/** Wait for a new message to arrive in the mbox + * @param mbox mbox to get a message from + * @param msg pointer where the message is stored + * @param timeout maximum time (in milliseconds) to wait for a message + * @return 0 (milliseconds) if a message has been received + * or SYS_MBOX_EMPTY if the mailbox is empty */ +u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg); +#endif +/** For now, we map straight to sys_arch implementation. */ +#define sys_mbox_tryfetch(mbox, msg) sys_arch_mbox_tryfetch(mbox, msg) +/** Delete an mbox + * @param mbox mbox to delete */ +void sys_mbox_free(sys_mbox_t *mbox); +#define sys_mbox_fetch(mbox, msg) sys_arch_mbox_fetch(mbox, msg, 0) +#ifndef sys_mbox_valid +/** Check if an mbox is valid/allocated: return 1 for valid, 0 for invalid */ +int sys_mbox_valid(sys_mbox_t *mbox); +#endif +#ifndef sys_mbox_set_invalid +/** Set an mbox invalid so that sys_mbox_valid returns 0 */ +void sys_mbox_set_invalid(sys_mbox_t *mbox); +#endif + +/** The only thread function: + * Creates a new thread + * @param name human-readable name for the thread (used for debugging purposes) + * @param thread thread-function + * @param arg parameter passed to 'thread' + * @param stacksize stack size in bytes for the new thread (may be ignored by ports) + * @param prio priority of the new thread (may be ignored by ports) */ +sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread, void *arg, int stacksize, int prio); + +#endif /* NO_SYS */ + +/* sys_init() must be called before anthing else. */ +void sys_init(void); + +#ifndef sys_jiffies +/** Ticks/jiffies since power up. */ +u32_t sys_jiffies(void); +#endif + +/** Returns the current time in milliseconds, + * may be the same as sys_jiffies or at least based on it. */ +u32_t sys_now(void); + +/* Critical Region Protection */ +/* These functions must be implemented in the sys_arch.c file. + In some implementations they can provide a more light-weight protection + mechanism than using semaphores. Otherwise semaphores can be used for + implementation */ +#ifndef SYS_ARCH_PROTECT +/** SYS_LIGHTWEIGHT_PROT + * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection + * for certain critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#if SYS_LIGHTWEIGHT_PROT + +/** SYS_ARCH_DECL_PROTECT + * declare a protection variable. This macro will default to defining a variable of + * type sys_prot_t. If a particular port needs a different implementation, then + * this macro may be defined in sys_arch.h. + */ +#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev +/** SYS_ARCH_PROTECT + * Perform a "fast" protect. This could be implemented by + * disabling interrupts for an embedded system or by using a semaphore or + * mutex. The implementation should allow calling SYS_ARCH_PROTECT when + * already protected. The old protection level is returned in the variable + * "lev". This macro will default to calling the sys_arch_protect() function + * which should be implemented in sys_arch.c. If a particular port needs a + * different implementation, then this macro may be defined in sys_arch.h + */ +#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect() +/** SYS_ARCH_UNPROTECT + * Perform a "fast" set of the protection level to "lev". This could be + * implemented by setting the interrupt level to "lev" within the MACRO or by + * using a semaphore or mutex. This macro will default to calling the + * sys_arch_unprotect() function which should be implemented in + * sys_arch.c. If a particular port needs a different implementation, then + * this macro may be defined in sys_arch.h + */ +#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev) +sys_prot_t sys_arch_protect(void); +void sys_arch_unprotect(sys_prot_t pval); + +#else + +#define SYS_ARCH_DECL_PROTECT(lev) +#define SYS_ARCH_PROTECT(lev) +#define SYS_ARCH_UNPROTECT(lev) + +#endif /* SYS_LIGHTWEIGHT_PROT */ + +#endif /* SYS_ARCH_PROTECT */ + +/* + * Macros to set/get and increase/decrease variables in a thread-safe way. + * Use these for accessing variable that are used from more than one thread. + */ + +#ifndef SYS_ARCH_INC +#define SYS_ARCH_INC(var, val) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + var += val; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_INC */ + +#ifndef SYS_ARCH_DEC +#define SYS_ARCH_DEC(var, val) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + var -= val; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_DEC */ + +#ifndef SYS_ARCH_GET +#define SYS_ARCH_GET(var, ret) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + ret = var; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_GET */ + +#ifndef SYS_ARCH_SET +#define SYS_ARCH_SET(var, val) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + var = val; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_SET */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_SYS_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/tcp.h b/Project/externalModules/lwip_v141/src/include/lwip/tcp.h new file mode 100644 index 0000000..1401c56 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/tcp.h @@ -0,0 +1,379 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_TCP_H__ +#define __LWIP_TCP_H__ + +#include "lwip/opt.h" + +#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/ip.h" +#include "lwip/icmp.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct tcp_pcb; + +/** Function prototype for tcp accept callback functions. Called when a new + * connection can be accepted on a listening pcb. + * + * @param arg Additional argument to pass to the callback function (@see tcp_arg()) + * @param newpcb The new connection pcb + * @param err An error code if there has been an error accepting. + * Only return ERR_ABRT if you have called tcp_abort from within the + * callback function! + */ +typedef err_t (*tcp_accept_fn)(void *arg, struct tcp_pcb *newpcb, err_t err); + +/** Function prototype for tcp receive callback functions. Called when data has + * been received. + * + * @param arg Additional argument to pass to the callback function (@see tcp_arg()) + * @param tpcb The connection pcb which received data + * @param p The received data (or NULL when the connection has been closed!) + * @param err An error code if there has been an error receiving + * Only return ERR_ABRT if you have called tcp_abort from within the + * callback function! + */ +typedef err_t (*tcp_recv_fn)(void *arg, struct tcp_pcb *tpcb, + struct pbuf *p, err_t err); + +/** Function prototype for tcp sent callback functions. Called when sent data has + * been acknowledged by the remote side. Use it to free corresponding resources. + * This also means that the pcb has now space available to send new data. + * + * @param arg Additional argument to pass to the callback function (@see tcp_arg()) + * @param tpcb The connection pcb for which data has been acknowledged + * @param len The amount of bytes acknowledged + * @return ERR_OK: try to send some data by calling tcp_output + * Only return ERR_ABRT if you have called tcp_abort from within the + * callback function! + */ +typedef err_t (*tcp_sent_fn)(void *arg, struct tcp_pcb *tpcb, + u16_t len); + +/** Function prototype for tcp poll callback functions. Called periodically as + * specified by @see tcp_poll. + * + * @param arg Additional argument to pass to the callback function (@see tcp_arg()) + * @param tpcb tcp pcb + * @return ERR_OK: try to send some data by calling tcp_output + * Only return ERR_ABRT if you have called tcp_abort from within the + * callback function! + */ +typedef err_t (*tcp_poll_fn)(void *arg, struct tcp_pcb *tpcb); + +/** Function prototype for tcp error callback functions. Called when the pcb + * receives a RST or is unexpectedly closed for any other reason. + * + * @note The corresponding pcb is already freed when this callback is called! + * + * @param arg Additional argument to pass to the callback function (@see tcp_arg()) + * @param err Error code to indicate why the pcb has been closed + * ERR_ABRT: aborted through tcp_abort or by a TCP timer + * ERR_RST: the connection was reset by the remote host + */ +typedef void (*tcp_err_fn)(void *arg, err_t err); + +/** Function prototype for tcp connected callback functions. Called when a pcb + * is connected to the remote side after initiating a connection attempt by + * calling tcp_connect(). + * + * @param arg Additional argument to pass to the callback function (@see tcp_arg()) + * @param tpcb The connection pcb which is connected + * @param err An unused error code, always ERR_OK currently ;-) TODO! + * Only return ERR_ABRT if you have called tcp_abort from within the + * callback function! + * + * @note When a connection attempt fails, the error callback is currently called! + */ +typedef err_t (*tcp_connected_fn)(void *arg, struct tcp_pcb *tpcb, err_t err); + +enum tcp_state { + CLOSED = 0, + LISTEN = 1, + SYN_SENT = 2, + SYN_RCVD = 3, + ESTABLISHED = 4, + FIN_WAIT_1 = 5, + FIN_WAIT_2 = 6, + CLOSE_WAIT = 7, + CLOSING = 8, + LAST_ACK = 9, + TIME_WAIT = 10 +}; + +#if LWIP_CALLBACK_API + /* Function to call when a listener has been connected. + * @param arg user-supplied argument (tcp_pcb.callback_arg) + * @param pcb a new tcp_pcb that now is connected + * @param err an error argument (TODO: that is current always ERR_OK?) + * @return ERR_OK: accept the new connection, + * any other err_t abortsthe new connection + */ +#define DEF_ACCEPT_CALLBACK tcp_accept_fn accept; +#else /* LWIP_CALLBACK_API */ +#define DEF_ACCEPT_CALLBACK +#endif /* LWIP_CALLBACK_API */ + +/** + * members common to struct tcp_pcb and struct tcp_listen_pcb + */ +#define TCP_PCB_COMMON(type) \ + type *next; /* for the linked list */ \ + void *callback_arg; \ + /* the accept callback for listen- and normal pcbs, if LWIP_CALLBACK_API */ \ + DEF_ACCEPT_CALLBACK \ + enum tcp_state state; /* TCP state */ \ + u8_t prio; \ + /* ports are in host byte order */ \ + u16_t local_port + + +/* the TCP protocol control block */ +struct tcp_pcb { +/** common PCB members */ + IP_PCB; +/** protocol specific PCB members */ + TCP_PCB_COMMON(struct tcp_pcb); + + /* ports are in host byte order */ + u16_t remote_port; + + u8_t flags; +#define TF_ACK_DELAY ((u8_t)0x01U) /* Delayed ACK. */ +#define TF_ACK_NOW ((u8_t)0x02U) /* Immediate ACK. */ +#define TF_INFR ((u8_t)0x04U) /* In fast recovery. */ +#define TF_TIMESTAMP ((u8_t)0x08U) /* Timestamp option enabled */ +#define TF_RXCLOSED ((u8_t)0x10U) /* rx closed by tcp_shutdown */ +#define TF_FIN ((u8_t)0x20U) /* Connection was closed locally (FIN segment enqueued). */ +#define TF_NODELAY ((u8_t)0x40U) /* Disable Nagle algorithm */ +#define TF_NAGLEMEMERR ((u8_t)0x80U) /* nagle enabled, memerr, try to output to prevent delayed ACK to happen */ + + /* the rest of the fields are in host byte order + as we have to do some math with them */ + + /* Timers */ + u8_t polltmr, pollinterval; + u8_t last_timer; + u32_t tmr; + + /* receiver variables */ + u32_t rcv_nxt; /* next seqno expected */ + u16_t rcv_wnd; /* receiver window available */ + u16_t rcv_ann_wnd; /* receiver window to announce */ + u32_t rcv_ann_right_edge; /* announced right edge of window */ + + /* Retransmission timer. */ + s16_t rtime; + + u16_t mss; /* maximum segment size */ + + /* RTT (round trip time) estimation variables */ + u32_t rttest; /* RTT estimate in 500ms ticks */ + u32_t rtseq; /* sequence number being timed */ + s16_t sa, sv; /* @todo document this */ + + s16_t rto; /* retransmission time-out */ + u8_t nrtx; /* number of retransmissions */ + + /* fast retransmit/recovery */ + u8_t dupacks; + u32_t lastack; /* Highest acknowledged seqno. */ + + /* congestion avoidance/control variables */ + u16_t cwnd; + u16_t ssthresh; + + /* sender variables */ + u32_t snd_nxt; /* next new seqno to be sent */ + u32_t snd_wl1, snd_wl2; /* Sequence and acknowledgement numbers of last + window update. */ + u32_t snd_lbb; /* Sequence number of next byte to be buffered. */ + u16_t snd_wnd; /* sender window */ + u16_t snd_wnd_max; /* the maximum sender window announced by the remote host */ + + u16_t acked; + + u16_t snd_buf; /* Available buffer space for sending (in bytes). */ +#define TCP_SNDQUEUELEN_OVERFLOW (0xffffU-3) + u16_t snd_queuelen; /* Available buffer space for sending (in tcp_segs). */ + +#if TCP_OVERSIZE + /* Extra bytes available at the end of the last pbuf in unsent. */ + u16_t unsent_oversize; +#endif /* TCP_OVERSIZE */ + + /* These are ordered by sequence number: */ + struct tcp_seg *unsent; /* Unsent (queued) segments. */ + struct tcp_seg *unacked; /* Sent but unacknowledged segments. */ +#if TCP_QUEUE_OOSEQ + struct tcp_seg *ooseq; /* Received out of sequence segments. */ +#endif /* TCP_QUEUE_OOSEQ */ + + struct pbuf *refused_data; /* Data previously received but not yet taken by upper layer */ + +#if LWIP_CALLBACK_API + /* Function to be called when more send buffer space is available. */ + tcp_sent_fn sent; + /* Function to be called when (in-sequence) data has arrived. */ + tcp_recv_fn recv; + /* Function to be called when a connection has been set up. */ + tcp_connected_fn connected; + /* Function which is called periodically. */ + tcp_poll_fn poll; + /* Function to be called whenever a fatal error occurs. */ + tcp_err_fn errf; +#endif /* LWIP_CALLBACK_API */ + +#if LWIP_TCP_TIMESTAMPS + u32_t ts_lastacksent; + u32_t ts_recent; +#endif /* LWIP_TCP_TIMESTAMPS */ + + /* idle time before KEEPALIVE is sent */ + u32_t keep_idle; +#if LWIP_TCP_KEEPALIVE + u32_t keep_intvl; + u32_t keep_cnt; +#endif /* LWIP_TCP_KEEPALIVE */ + + /* Persist timer counter */ + u8_t persist_cnt; + /* Persist timer back-off */ + u8_t persist_backoff; + + /* KEEPALIVE counter */ + u8_t keep_cnt_sent; +}; + +struct tcp_pcb_listen { +/* Common members of all PCB types */ + IP_PCB; +/* Protocol specific PCB members */ + TCP_PCB_COMMON(struct tcp_pcb_listen); + +#if TCP_LISTEN_BACKLOG + u8_t backlog; + u8_t accepts_pending; +#endif /* TCP_LISTEN_BACKLOG */ +}; + +#if LWIP_EVENT_API + +enum lwip_event { + LWIP_EVENT_ACCEPT, + LWIP_EVENT_SENT, + LWIP_EVENT_RECV, + LWIP_EVENT_CONNECTED, + LWIP_EVENT_POLL, + LWIP_EVENT_ERR +}; + +err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb, + enum lwip_event, + struct pbuf *p, + u16_t size, + err_t err); + +#endif /* LWIP_EVENT_API */ + +/* Application program's interface: */ +struct tcp_pcb * tcp_new (void); + +void tcp_arg (struct tcp_pcb *pcb, void *arg); +void tcp_accept (struct tcp_pcb *pcb, tcp_accept_fn accept); +void tcp_recv (struct tcp_pcb *pcb, tcp_recv_fn recv); +void tcp_sent (struct tcp_pcb *pcb, tcp_sent_fn sent); +void tcp_poll (struct tcp_pcb *pcb, tcp_poll_fn poll, u8_t interval); +void tcp_err (struct tcp_pcb *pcb, tcp_err_fn err); + +#define tcp_mss(pcb) (((pcb)->flags & TF_TIMESTAMP) ? ((pcb)->mss - 12) : (pcb)->mss) +#define tcp_sndbuf(pcb) ((pcb)->snd_buf) +#define tcp_sndqueuelen(pcb) ((pcb)->snd_queuelen) +#define tcp_nagle_disable(pcb) ((pcb)->flags |= TF_NODELAY) +#define tcp_nagle_enable(pcb) ((pcb)->flags &= ~TF_NODELAY) +#define tcp_nagle_disabled(pcb) (((pcb)->flags & TF_NODELAY) != 0) + +#if TCP_LISTEN_BACKLOG +#define tcp_accepted(pcb) do { \ + LWIP_ASSERT("pcb->state == LISTEN (called for wrong pcb?)", pcb->state == LISTEN); \ + (((struct tcp_pcb_listen *)(pcb))->accepts_pending--); } while(0) +#else /* TCP_LISTEN_BACKLOG */ +#define tcp_accepted(pcb) LWIP_ASSERT("pcb->state == LISTEN (called for wrong pcb?)", \ + (pcb)->state == LISTEN) +#endif /* TCP_LISTEN_BACKLOG */ + +void tcp_recved (struct tcp_pcb *pcb, u16_t len); +err_t tcp_bind (struct tcp_pcb *pcb, ip_addr_t *ipaddr, + u16_t port); +err_t tcp_connect (struct tcp_pcb *pcb, ip_addr_t *ipaddr, + u16_t port, tcp_connected_fn connected); + +struct tcp_pcb * tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog); +#define tcp_listen(pcb) tcp_listen_with_backlog(pcb, TCP_DEFAULT_LISTEN_BACKLOG) + +void tcp_abort (struct tcp_pcb *pcb); +err_t tcp_close (struct tcp_pcb *pcb); +err_t tcp_shutdown(struct tcp_pcb *pcb, int shut_rx, int shut_tx); + +/* Flags for "apiflags" parameter in tcp_write */ +#define TCP_WRITE_FLAG_COPY 0x01 +#define TCP_WRITE_FLAG_MORE 0x02 + +err_t tcp_write (struct tcp_pcb *pcb, const void *dataptr, u16_t len, + u8_t apiflags); + +void tcp_setprio (struct tcp_pcb *pcb, u8_t prio); + +#define TCP_PRIO_MIN 1 +#define TCP_PRIO_NORMAL 64 +#define TCP_PRIO_MAX 127 + +err_t tcp_output (struct tcp_pcb *pcb); + + +const char* tcp_debug_state_str(enum tcp_state s); + + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_TCP */ + +#endif /* __LWIP_TCP_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/tcp_impl.h b/Project/externalModules/lwip_v141/src/include/lwip/tcp_impl.h new file mode 100644 index 0000000..03f5d4c --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/tcp_impl.h @@ -0,0 +1,486 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_TCP_IMPL_H__ +#define __LWIP_TCP_IMPL_H__ + +#include "lwip/opt.h" + +#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/tcp.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/ip.h" +#include "lwip/icmp.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Functions for interfacing with TCP: */ + +/* Lower layer interface to TCP: */ +void tcp_init (void); /* Initialize this module. */ +void tcp_tmr (void); /* Must be called every + TCP_TMR_INTERVAL + ms. (Typically 250 ms). */ +/* It is also possible to call these two functions at the right + intervals (instead of calling tcp_tmr()). */ +void tcp_slowtmr (void); +void tcp_fasttmr (void); + + +/* Only used by IP to pass a TCP segment to TCP: */ +void tcp_input (struct pbuf *p, struct netif *inp); +/* Used within the TCP code only: */ +struct tcp_pcb * tcp_alloc (u8_t prio); +void tcp_abandon (struct tcp_pcb *pcb, int reset); +err_t tcp_send_empty_ack(struct tcp_pcb *pcb); +void tcp_rexmit (struct tcp_pcb *pcb); +void tcp_rexmit_rto (struct tcp_pcb *pcb); +void tcp_rexmit_fast (struct tcp_pcb *pcb); +u32_t tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb); +err_t tcp_process_refused_data(struct tcp_pcb *pcb); + +/** + * This is the Nagle algorithm: try to combine user data to send as few TCP + * segments as possible. Only send if + * - no previously transmitted data on the connection remains unacknowledged or + * - the TF_NODELAY flag is set (nagle algorithm turned off for this pcb) or + * - the only unsent segment is at least pcb->mss bytes long (or there is more + * than one unsent segment - with lwIP, this can happen although unsent->len < mss) + * - or if we are in fast-retransmit (TF_INFR) + */ +#define tcp_do_output_nagle(tpcb) ((((tpcb)->unacked == NULL) || \ + ((tpcb)->flags & (TF_NODELAY | TF_INFR)) || \ + (((tpcb)->unsent != NULL) && (((tpcb)->unsent->next != NULL) || \ + ((tpcb)->unsent->len >= (tpcb)->mss))) || \ + ((tcp_sndbuf(tpcb) == 0) || (tcp_sndqueuelen(tpcb) >= TCP_SND_QUEUELEN)) \ + ) ? 1 : 0) +#define tcp_output_nagle(tpcb) (tcp_do_output_nagle(tpcb) ? tcp_output(tpcb) : ERR_OK) + + +#define TCP_SEQ_LT(a,b) ((s32_t)((u32_t)(a) - (u32_t)(b)) < 0) +#define TCP_SEQ_LEQ(a,b) ((s32_t)((u32_t)(a) - (u32_t)(b)) <= 0) +#define TCP_SEQ_GT(a,b) ((s32_t)((u32_t)(a) - (u32_t)(b)) > 0) +#define TCP_SEQ_GEQ(a,b) ((s32_t)((u32_t)(a) - (u32_t)(b)) >= 0) +/* is b<=a<=c? */ +#if 0 /* see bug #10548 */ +#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b)) +#endif +#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c)) +#define TCP_FIN 0x01U +#define TCP_SYN 0x02U +#define TCP_RST 0x04U +#define TCP_PSH 0x08U +#define TCP_ACK 0x10U +#define TCP_URG 0x20U +#define TCP_ECE 0x40U +#define TCP_CWR 0x80U + +#define TCP_FLAGS 0x3fU + +/* Length of the TCP header, excluding options. */ +#define TCP_HLEN 20 + +#ifndef TCP_TMR_INTERVAL +#define TCP_TMR_INTERVAL 200 /* ECONAIS: default timer was 250msecs. The TCP timer interval in milliseconds. */ +#endif /* TCP_TMR_INTERVAL */ + +#ifndef TCP_FAST_INTERVAL +#define TCP_FAST_INTERVAL TCP_TMR_INTERVAL /* the fine grained timeout in milliseconds */ +#endif /* TCP_FAST_INTERVAL */ + +#ifndef TCP_SLOW_INTERVAL +#define TCP_SLOW_INTERVAL (2*TCP_TMR_INTERVAL) /* the coarse grained timeout in milliseconds */ +#endif /* TCP_SLOW_INTERVAL */ + +#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */ +#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */ + +#define TCP_OOSEQ_TIMEOUT 6U /* x RTO */ + +#ifndef TCP_MSL +#define TCP_MSL 60000UL /* The maximum segment lifetime in milliseconds */ +#endif + +/* Keepalive values, compliant with RFC 1122. Don't change this unless you know what you're doing */ +#ifndef TCP_KEEPIDLE_DEFAULT +#define TCP_KEEPIDLE_DEFAULT 7200000UL /* Default KEEPALIVE timer in milliseconds */ +#endif + +#ifndef TCP_KEEPINTVL_DEFAULT +#define TCP_KEEPINTVL_DEFAULT 75000UL /* Default Time between KEEPALIVE probes in milliseconds */ +#endif + +#ifndef TCP_KEEPCNT_DEFAULT +#define TCP_KEEPCNT_DEFAULT 9U /* Default Counter for KEEPALIVE probes */ +#endif + +#define TCP_MAXIDLE TCP_KEEPCNT_DEFAULT * TCP_KEEPINTVL_DEFAULT /* Maximum KEEPALIVE probe time */ + +/* Fields are (of course) in network byte order. + * Some fields are converted to host byte order in tcp_input(). + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct tcp_hdr { + PACK_STRUCT_FIELD(u16_t src); + PACK_STRUCT_FIELD(u16_t dest); + PACK_STRUCT_FIELD(u32_t seqno); + PACK_STRUCT_FIELD(u32_t ackno); + PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags); + PACK_STRUCT_FIELD(u16_t wnd); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u16_t urgp); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12) +#define TCPH_FLAGS(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS) + +#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr)) +#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = (((phdr)->_hdrlen_rsvd_flags & PP_HTONS((u16_t)(~(u16_t)(TCP_FLAGS)))) | htons(flags)) +#define TCPH_HDRLEN_FLAGS_SET(phdr, len, flags) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | (flags)) + +#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = ((phdr)->_hdrlen_rsvd_flags | htons(flags)) +#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) ) + +#define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & (TCP_FIN | TCP_SYN)) != 0)) + +/** Flags used on input processing, not on pcb->flags +*/ +#define TF_RESET (u8_t)0x08U /* Connection was reset. */ +#define TF_CLOSED (u8_t)0x10U /* Connection was sucessfully closed. */ +#define TF_GOT_FIN (u8_t)0x20U /* Connection was closed by the remote end. */ + + +#if LWIP_EVENT_API + +#define TCP_EVENT_ACCEPT(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_ACCEPT, NULL, 0, err) +#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_SENT, NULL, space, ERR_OK) +#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_RECV, (p), 0, (err)) +#define TCP_EVENT_CLOSED(pcb,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_RECV, NULL, 0, ERR_OK) +#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_CONNECTED, NULL, 0, (err)) +#define TCP_EVENT_POLL(pcb,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_POLL, NULL, 0, ERR_OK) +#define TCP_EVENT_ERR(errf,arg,err) lwip_tcp_event((arg), NULL, \ + LWIP_EVENT_ERR, NULL, 0, (err)) + +#else /* LWIP_EVENT_API */ + +#define TCP_EVENT_ACCEPT(pcb,err,ret) \ + do { \ + if((pcb)->accept != NULL) \ + (ret) = (pcb)->accept((pcb)->callback_arg,(pcb),(err)); \ + else (ret) = ERR_ARG; \ + } while (0) + +#define TCP_EVENT_SENT(pcb,space,ret) \ + do { \ + if((pcb)->sent != NULL) \ + (ret) = (pcb)->sent((pcb)->callback_arg,(pcb),(space)); \ + else (ret) = ERR_OK; \ + } while (0) + +#define TCP_EVENT_RECV(pcb,p,err,ret) \ + do { \ + if((pcb)->recv != NULL) { \ + (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err));\ + } else { \ + (ret) = tcp_recv_null(NULL, (pcb), (p), (err)); \ + } \ + } while (0) + +#define TCP_EVENT_CLOSED(pcb,ret) \ + do { \ + if(((pcb)->recv != NULL)) { \ + (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),NULL,ERR_OK);\ + } else { \ + (ret) = ERR_OK; \ + } \ + } while (0) + +#define TCP_EVENT_CONNECTED(pcb,err,ret) \ + do { \ + if((pcb)->connected != NULL) \ + (ret) = (pcb)->connected((pcb)->callback_arg,(pcb),(err)); \ + else (ret) = ERR_OK; \ + } while (0) + +#define TCP_EVENT_POLL(pcb,ret) \ + do { \ + if((pcb)->poll != NULL) \ + (ret) = (pcb)->poll((pcb)->callback_arg,(pcb)); \ + else (ret) = ERR_OK; \ + } while (0) + +#define TCP_EVENT_ERR(errf,arg,err) \ + do { \ + if((errf) != NULL) \ + (errf)((arg),(err)); \ + } while (0) + +#endif /* LWIP_EVENT_API */ + +/** Enabled extra-check for TCP_OVERSIZE if LWIP_DEBUG is enabled */ +#if TCP_OVERSIZE && defined(LWIP_DEBUG) +#define TCP_OVERSIZE_DBGCHECK 1 +#else +#define TCP_OVERSIZE_DBGCHECK 0 +#endif + +/** Don't generate checksum on copy if CHECKSUM_GEN_TCP is disabled */ +#define TCP_CHECKSUM_ON_COPY (LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_TCP) + +/* This structure represents a TCP segment on the unsent, unacked and ooseq queues */ +struct tcp_seg { + struct tcp_seg *next; /* used when putting segements on a queue */ + struct pbuf *p; /* buffer containing data + TCP header */ + u16_t len; /* the TCP length of this segment */ +#if TCP_OVERSIZE_DBGCHECK + u16_t oversize_left; /* Extra bytes available at the end of the last + pbuf in unsent (used for asserting vs. + tcp_pcb.unsent_oversized only) */ +#endif /* TCP_OVERSIZE_DBGCHECK */ +#if TCP_CHECKSUM_ON_COPY + u16_t chksum; + u8_t chksum_swapped; +#endif /* TCP_CHECKSUM_ON_COPY */ + u8_t flags; +#define TF_SEG_OPTS_MSS (u8_t)0x01U /* Include MSS option. */ +#define TF_SEG_OPTS_TS (u8_t)0x02U /* Include timestamp option. */ +#define TF_SEG_DATA_CHECKSUMMED (u8_t)0x04U /* ALL data (not the header) is + checksummed into 'chksum' */ + struct tcp_hdr *tcphdr; /* the TCP header */ +}; + +#define LWIP_TCP_OPT_LENGTH(flags) \ + (flags & TF_SEG_OPTS_MSS ? 4 : 0) + \ + (flags & TF_SEG_OPTS_TS ? 12 : 0) + +/** This returns a TCP header option for MSS in an u32_t */ +#define TCP_BUILD_MSS_OPTION(mss) htonl(0x02040000 | ((mss) & 0xFFFF)) + +/* Global variables: */ +extern struct tcp_pcb *tcp_input_pcb; +extern u32_t tcp_ticks; +extern u8_t tcp_active_pcbs_changed; + +/* The TCP PCB lists. */ +union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */ + struct tcp_pcb_listen *listen_pcbs; + struct tcp_pcb *pcbs; +}; +extern struct tcp_pcb *tcp_bound_pcbs; +extern union tcp_listen_pcbs_t tcp_listen_pcbs; +extern struct tcp_pcb *tcp_active_pcbs; /* List of all TCP PCBs that are in a + state in which they accept or send + data. */ +extern struct tcp_pcb *tcp_tw_pcbs; /* List of all TCP PCBs in TIME-WAIT. */ + +extern struct tcp_pcb *tcp_tmp_pcb; /* Only used for temporary storage. */ + +/* Axioms about the above lists: + 1) Every TCP PCB that is not CLOSED is in one of the lists. + 2) A PCB is only in one of the lists. + 3) All PCBs in the tcp_listen_pcbs list is in LISTEN state. + 4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state. +*/ +/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB + with a PCB list or removes a PCB from a list, respectively. */ +#ifndef TCP_DEBUG_PCB_LISTS +#define TCP_DEBUG_PCB_LISTS 0 +#endif +#if TCP_DEBUG_PCB_LISTS +#define TCP_REG(pcbs, npcb) do {\ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", (npcb), (npcb)->local_port)); \ + for(tcp_tmp_pcb = *(pcbs); \ + tcp_tmp_pcb != NULL; \ + tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != (npcb)); \ + } \ + LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", ((pcbs) == &tcp_bound_pcbs) || ((npcb)->state != CLOSED)); \ + (npcb)->next = *(pcbs); \ + LWIP_ASSERT("TCP_REG: npcb->next != npcb", (npcb)->next != (npcb)); \ + *(pcbs) = (npcb); \ + LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ + tcp_timer_needed(); \ + } while(0) +#define TCP_RMV(pcbs, npcb) do { \ + LWIP_ASSERT("TCP_RMV: pcbs != NULL", *(pcbs) != NULL); \ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", (npcb), *(pcbs))); \ + if(*(pcbs) == (npcb)) { \ + *(pcbs) = (*pcbs)->next; \ + } else for(tcp_tmp_pcb = *(pcbs); tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + if(tcp_tmp_pcb->next == (npcb)) { \ + tcp_tmp_pcb->next = (npcb)->next; \ + break; \ + } \ + } \ + (npcb)->next = NULL; \ + LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", (npcb), *(pcbs))); \ + } while(0) + +#else /* LWIP_DEBUG */ + +#define TCP_REG(pcbs, npcb) \ + do { \ + (npcb)->next = *pcbs; \ + *(pcbs) = (npcb); \ + tcp_timer_needed(); \ + } while (0) + +#define TCP_RMV(pcbs, npcb) \ + do { \ + if(*(pcbs) == (npcb)) { \ + (*(pcbs)) = (*pcbs)->next; \ + } \ + else { \ + for(tcp_tmp_pcb = *pcbs; \ + tcp_tmp_pcb != NULL; \ + tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + if(tcp_tmp_pcb->next == (npcb)) { \ + tcp_tmp_pcb->next = (npcb)->next; \ + break; \ + } \ + } \ + } \ + (npcb)->next = NULL; \ + } while(0) + +#endif /* LWIP_DEBUG */ + +#define TCP_REG_ACTIVE(npcb) \ + do { \ + TCP_REG(&tcp_active_pcbs, npcb); \ + tcp_active_pcbs_changed = 1; \ + } while (0) + +#define TCP_RMV_ACTIVE(npcb) \ + do { \ + TCP_RMV(&tcp_active_pcbs, npcb); \ + tcp_active_pcbs_changed = 1; \ + } while (0) + +#define TCP_PCB_REMOVE_ACTIVE(pcb) \ + do { \ + tcp_pcb_remove(&tcp_active_pcbs, pcb); \ + tcp_active_pcbs_changed = 1; \ + } while (0) + + +/* Internal functions: */ +struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb); +void tcp_pcb_purge(struct tcp_pcb *pcb); +void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb); + +void tcp_segs_free(struct tcp_seg *seg); +void tcp_seg_free(struct tcp_seg *seg); +struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg); + +#define tcp_ack(pcb) \ + do { \ + if((pcb)->flags & TF_ACK_DELAY) { \ + (pcb)->flags &= ~TF_ACK_DELAY; \ + (pcb)->flags |= TF_ACK_NOW; \ + } \ + else { \ + (pcb)->flags |= TF_ACK_DELAY; \ + } \ + } while (0) + +#define tcp_ack_now(pcb) \ + do { \ + (pcb)->flags |= TF_ACK_NOW; \ + } while (0) + +err_t tcp_send_fin(struct tcp_pcb *pcb); +err_t tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags); + +void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg); + +void tcp_rst(u32_t seqno, u32_t ackno, + ip_addr_t *local_ip, ip_addr_t *remote_ip, + u16_t local_port, u16_t remote_port); + +u32_t tcp_next_iss(void); + +void tcp_keepalive(struct tcp_pcb *pcb); +void tcp_zero_window_probe(struct tcp_pcb *pcb); + +#if TCP_CALCULATE_EFF_SEND_MSS +u16_t tcp_eff_send_mss(u16_t sendmss, ip_addr_t *addr); +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + +#if LWIP_CALLBACK_API +err_t tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err); +#endif /* LWIP_CALLBACK_API */ + +#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG +void tcp_debug_print(struct tcp_hdr *tcphdr); +void tcp_debug_print_flags(u8_t flags); +void tcp_debug_print_state(enum tcp_state s); +void tcp_debug_print_pcbs(void); +s16_t tcp_pcbs_sane(void); +#else +# define tcp_debug_print(tcphdr) +# define tcp_debug_print_flags(flags) +# define tcp_debug_print_state(s) +# define tcp_debug_print_pcbs() +# define tcp_pcbs_sane() 1 +#endif /* TCP_DEBUG */ + +/** External function (implemented in timers.c), called when TCP detects + * that a timer is needed (i.e. active- or time-wait-pcb found). */ +void tcp_timer_needed(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_TCP */ + +#endif /* __LWIP_TCP_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/tcpip.h b/Project/externalModules/lwip_v141/src/include/lwip/tcpip.h new file mode 100644 index 0000000..a2c9a5b --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/tcpip.h @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_TCPIP_H__ +#define __LWIP_TCPIP_H__ + +#include "lwip/opt.h" + +#if !NO_SYS /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/api_msg.h" +#include "lwip/netifapi.h" +#include "lwip/pbuf.h" +#include "lwip/api.h" +#include "lwip/sys.h" +#include "lwip/timers.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** Define this to something that triggers a watchdog. This is called from + * tcpip_thread after processing a message. */ +#ifndef LWIP_TCPIP_THREAD_ALIVE +#define LWIP_TCPIP_THREAD_ALIVE() +#endif + +#if LWIP_TCPIP_CORE_LOCKING +/** The global semaphore to lock the stack. */ +extern sys_mutex_t lock_tcpip_core; +#define LOCK_TCPIP_CORE() sys_mutex_lock(&lock_tcpip_core) +#define UNLOCK_TCPIP_CORE() sys_mutex_unlock(&lock_tcpip_core) +#define TCPIP_APIMSG(m) tcpip_apimsg_lock(m) +#define TCPIP_APIMSG_ACK(m) +#define TCPIP_NETIFAPI(m) tcpip_netifapi_lock(m) +#define TCPIP_NETIFAPI_ACK(m) +#else /* LWIP_TCPIP_CORE_LOCKING */ +#define LOCK_TCPIP_CORE() +#define UNLOCK_TCPIP_CORE() +#define TCPIP_APIMSG(m) tcpip_apimsg(m) +#define TCPIP_APIMSG_ACK(m) sys_sem_signal(&m->conn->op_completed) +#define TCPIP_NETIFAPI(m) tcpip_netifapi(m) +#define TCPIP_NETIFAPI_ACK(m) sys_sem_signal(&m->sem) +#endif /* LWIP_TCPIP_CORE_LOCKING */ + +/** Function prototype for the init_done function passed to tcpip_init */ +typedef void (*tcpip_init_done_fn)(void *arg); +/** Function prototype for functions passed to tcpip_callback() */ +typedef void (*tcpip_callback_fn)(void *ctx); + +/* Forward declarations */ +struct tcpip_callback_msg; + +void tcpip_init(tcpip_init_done_fn tcpip_init_done, void *arg); + +#if LWIP_NETCONN +err_t tcpip_apimsg(struct api_msg *apimsg); +#if LWIP_TCPIP_CORE_LOCKING +err_t tcpip_apimsg_lock(struct api_msg *apimsg); +#endif /* LWIP_TCPIP_CORE_LOCKING */ +#endif /* LWIP_NETCONN */ + +err_t tcpip_input(struct pbuf *p, struct netif *inp); + +#if LWIP_NETIF_API +err_t tcpip_netifapi(struct netifapi_msg *netifapimsg); +#if LWIP_TCPIP_CORE_LOCKING +err_t tcpip_netifapi_lock(struct netifapi_msg *netifapimsg); +#endif /* LWIP_TCPIP_CORE_LOCKING */ +#endif /* LWIP_NETIF_API */ + +err_t tcpip_callback_with_block(tcpip_callback_fn function, void *ctx, u8_t block); +#define tcpip_callback(f, ctx) tcpip_callback_with_block(f, ctx, 1) + +struct tcpip_callback_msg* tcpip_callbackmsg_new(tcpip_callback_fn function, void *ctx); +void tcpip_callbackmsg_delete(struct tcpip_callback_msg* msg); +err_t tcpip_trycallback(struct tcpip_callback_msg* msg); + +/* free pbufs or heap memory from another context without blocking */ +err_t pbuf_free_callback(struct pbuf *p); +err_t mem_free_callback(void *m); + +#if LWIP_TCPIP_TIMEOUT +err_t tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg); +err_t tcpip_untimeout(sys_timeout_handler h, void *arg); +#endif /* LWIP_TCPIP_TIMEOUT */ + +enum tcpip_msg_type { +#if LWIP_NETCONN + TCPIP_MSG_API, +#endif /* LWIP_NETCONN */ + TCPIP_MSG_INPKT, +#if LWIP_NETIF_API + TCPIP_MSG_NETIFAPI, +#endif /* LWIP_NETIF_API */ +#if LWIP_TCPIP_TIMEOUT + TCPIP_MSG_TIMEOUT, + TCPIP_MSG_UNTIMEOUT, +#endif /* LWIP_TCPIP_TIMEOUT */ + TCPIP_MSG_CALLBACK, + TCPIP_MSG_CALLBACK_STATIC +}; + +struct tcpip_msg { + enum tcpip_msg_type type; + sys_sem_t *sem; + union { +#if LWIP_NETCONN + struct api_msg *apimsg; +#endif /* LWIP_NETCONN */ +#if LWIP_NETIF_API + struct netifapi_msg *netifapimsg; +#endif /* LWIP_NETIF_API */ + struct { + struct pbuf *p; + struct netif *netif; + } inp; + struct { + tcpip_callback_fn function; + void *ctx; + } cb; +#if LWIP_TCPIP_TIMEOUT + struct { + u32_t msecs; + sys_timeout_handler h; + void *arg; + } tmo; +#endif /* LWIP_TCPIP_TIMEOUT */ + } msg; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* !NO_SYS */ + +#endif /* __LWIP_TCPIP_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/timers.h b/Project/externalModules/lwip_v141/src/include/lwip/timers.h new file mode 100644 index 0000000..03612f9 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/timers.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * Simon Goldschmidt + * + */ +#ifndef __LWIP_TIMERS_H__ +#define __LWIP_TIMERS_H__ + +#include "lwip/opt.h" + +/* Timers are not supported when NO_SYS==1 and NO_SYS_NO_TIMERS==1 */ +#define LWIP_TIMERS (!NO_SYS || (NO_SYS && !NO_SYS_NO_TIMERS)) + +#if LWIP_TIMERS + +#include "lwip/err.h" +#if !NO_SYS +#include "lwip/sys.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef LWIP_DEBUG_TIMERNAMES +#ifdef LWIP_DEBUG +#define LWIP_DEBUG_TIMERNAMES SYS_DEBUG +#else /* LWIP_DEBUG */ +#define LWIP_DEBUG_TIMERNAMES 0 +#endif /* LWIP_DEBUG*/ +#endif + +/** Function prototype for a timeout callback function. Register such a function + * using sys_timeout(). + * + * @param arg Additional argument to pass to the function - set up by sys_timeout() + */ +typedef void (* sys_timeout_handler)(void *arg); + +struct sys_timeo { + struct sys_timeo *next; + u32_t time; + sys_timeout_handler h; + void *arg; +#if LWIP_DEBUG_TIMERNAMES + const char* handler_name; +#endif /* LWIP_DEBUG_TIMERNAMES */ +}; + +void sys_timeouts_init(void); + +#if LWIP_DEBUG_TIMERNAMES +void sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char* handler_name); +#define sys_timeout(msecs, handler, arg) sys_timeout_debug(msecs, handler, arg, #handler) +#else /* LWIP_DEBUG_TIMERNAMES */ +void sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg); +#endif /* LWIP_DEBUG_TIMERNAMES */ + +void sys_untimeout(sys_timeout_handler handler, void *arg); +#if NO_SYS +void sys_check_timeouts(void); +void sys_restart_timeouts(void); +#else /* NO_SYS */ +void sys_timeouts_mbox_fetch(sys_mbox_t *mbox, void **msg); +#endif /* NO_SYS */ + + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_TIMERS */ +#endif /* __LWIP_TIMERS_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/lwip/udp.h b/Project/externalModules/lwip_v141/src/include/lwip/udp.h new file mode 100644 index 0000000..1ddb734 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/lwip/udp.h @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_UDP_H__ +#define __LWIP_UDP_H__ + +#include "lwip/opt.h" + +#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/netif.h" +#include "lwip/ip_addr.h" +#include "lwip/ip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define UDP_HLEN 8 + +/* Fields are (of course) in network byte order. */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct udp_hdr { + PACK_STRUCT_FIELD(u16_t src); + PACK_STRUCT_FIELD(u16_t dest); /* src/dest UDP ports */ + PACK_STRUCT_FIELD(u16_t len); + PACK_STRUCT_FIELD(u16_t chksum); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define UDP_FLAGS_NOCHKSUM 0x01U +#define UDP_FLAGS_UDPLITE 0x02U +#define UDP_FLAGS_CONNECTED 0x04U +#define UDP_FLAGS_MULTICAST_LOOP 0x08U + +struct udp_pcb; + +/** Function prototype for udp pcb receive callback functions + * addr and port are in same byte order as in the pcb + * The callback is responsible for freeing the pbuf + * if it's not used any more. + * + * ATTENTION: Be aware that 'addr' points into the pbuf 'p' so freeing this pbuf + * makes 'addr' invalid, too. + * + * @param arg user supplied argument (udp_pcb.recv_arg) + * @param pcb the udp_pcb which received data + * @param p the packet buffer that was received + * @param addr the remote IP address from which the packet was received + * @param port the remote port from which the packet was received + */ +typedef void (*udp_recv_fn)(void *arg, struct udp_pcb *pcb, struct pbuf *p, + ip_addr_t *addr, u16_t port); + + +struct udp_pcb { +/* Common members of all PCB types */ + IP_PCB; + +/* Protocol specific PCB members */ + + struct udp_pcb *next; + + u8_t flags; + /** ports are in host byte order */ + u16_t local_port, remote_port; + +#if LWIP_IGMP + /** outgoing network interface for multicast packets */ + ip_addr_t multicast_ip; +#endif /* LWIP_IGMP */ + +#if LWIP_UDPLITE + /** used for UDP_LITE only */ + u16_t chksum_len_rx, chksum_len_tx; +#endif /* LWIP_UDPLITE */ + + /** receive callback function */ + udp_recv_fn recv; + /** user-supplied argument for the recv callback */ + void *recv_arg; +}; +/* udp_pcbs export for exernal reference (e.g. SNMP agent) */ +extern struct udp_pcb *udp_pcbs; + +/* The following functions is the application layer interface to the + UDP code. */ +struct udp_pcb * udp_new (void); +void udp_remove (struct udp_pcb *pcb); +err_t udp_bind (struct udp_pcb *pcb, ip_addr_t *ipaddr, + u16_t port); +err_t udp_connect (struct udp_pcb *pcb, ip_addr_t *ipaddr, + u16_t port); +void udp_disconnect (struct udp_pcb *pcb); +void udp_recv (struct udp_pcb *pcb, udp_recv_fn recv, + void *recv_arg); +err_t udp_sendto_if (struct udp_pcb *pcb, struct pbuf *p, + ip_addr_t *dst_ip, u16_t dst_port, + struct netif *netif); +err_t udp_sendto (struct udp_pcb *pcb, struct pbuf *p, + ip_addr_t *dst_ip, u16_t dst_port); +err_t udp_send (struct udp_pcb *pcb, struct pbuf *p); + +#if LWIP_CHECKSUM_ON_COPY +err_t udp_sendto_if_chksum(struct udp_pcb *pcb, struct pbuf *p, + ip_addr_t *dst_ip, u16_t dst_port, + struct netif *netif, u8_t have_chksum, + u16_t chksum); +err_t udp_sendto_chksum(struct udp_pcb *pcb, struct pbuf *p, + ip_addr_t *dst_ip, u16_t dst_port, + u8_t have_chksum, u16_t chksum); +err_t udp_send_chksum(struct udp_pcb *pcb, struct pbuf *p, + u8_t have_chksum, u16_t chksum); +#endif /* LWIP_CHECKSUM_ON_COPY */ + +#define udp_flags(pcb) ((pcb)->flags) +#define udp_setflags(pcb, f) ((pcb)->flags = (f)) + +/* The following functions are the lower layer interface to UDP. */ +void udp_input (struct pbuf *p, struct netif *inp); + +void udp_init (void); + +#if UDP_DEBUG +void udp_debug_print(struct udp_hdr *udphdr); +#else +#define udp_debug_print(udphdr) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_UDP */ + +#endif /* __LWIP_UDP_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/netif/etharp.h b/Project/externalModules/lwip_v141/src/include/netif/etharp.h new file mode 100644 index 0000000..4734d95 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/netif/etharp.h @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * Copyright (c) 2003-2004 Leon Woestenberg + * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __NETIF_ETHARP_H__ +#define __NETIF_ETHARP_H__ + +#include "lwip/opt.h" + +#if LWIP_ARP || LWIP_ETHERNET /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/ip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ETHARP_HWADDR_LEN +#define ETHARP_HWADDR_LEN 6 +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct eth_addr { + PACK_STRUCT_FIELD(u8_t addr[ETHARP_HWADDR_LEN]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** Ethernet header */ +struct eth_hdr { +#if ETH_PAD_SIZE + PACK_STRUCT_FIELD(u8_t padding[ETH_PAD_SIZE]); +#endif + PACK_STRUCT_FIELD(struct eth_addr dest); + PACK_STRUCT_FIELD(struct eth_addr src); + PACK_STRUCT_FIELD(u16_t type); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define SIZEOF_ETH_HDR (14 + ETH_PAD_SIZE) + +#if ETHARP_SUPPORT_VLAN + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** VLAN header inserted between ethernet header and payload + * if 'type' in ethernet header is ETHTYPE_VLAN. + * See IEEE802.Q */ +struct eth_vlan_hdr { + PACK_STRUCT_FIELD(u16_t prio_vid); + PACK_STRUCT_FIELD(u16_t tpid); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define SIZEOF_VLAN_HDR 4 +#define VLAN_ID(vlan_hdr) (htons((vlan_hdr)->prio_vid) & 0xFFF) + +#endif /* ETHARP_SUPPORT_VLAN */ + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** the ARP message, see RFC 826 ("Packet format") */ +struct etharp_hdr { + PACK_STRUCT_FIELD(u16_t hwtype); + PACK_STRUCT_FIELD(u16_t proto); + PACK_STRUCT_FIELD(u8_t hwlen); + PACK_STRUCT_FIELD(u8_t protolen); + PACK_STRUCT_FIELD(u16_t opcode); + PACK_STRUCT_FIELD(struct eth_addr shwaddr); + PACK_STRUCT_FIELD(struct ip_addr2 sipaddr); + PACK_STRUCT_FIELD(struct eth_addr dhwaddr); + PACK_STRUCT_FIELD(struct ip_addr2 dipaddr); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define SIZEOF_ETHARP_HDR 28 +#define SIZEOF_ETHARP_PACKET (SIZEOF_ETH_HDR + SIZEOF_ETHARP_HDR) + +/** 5 seconds period */ +#define ARP_TMR_INTERVAL 5000 + +#define ETHTYPE_ARP 0x0806U +#define ETHTYPE_IP 0x0800U +#define ETHTYPE_VLAN 0x8100U +#define ETHTYPE_PPPOEDISC 0x8863U /* PPP Over Ethernet Discovery Stage */ +#define ETHTYPE_PPPOE 0x8864U /* PPP Over Ethernet Session Stage */ + +/** MEMCPY-like macro to copy to/from struct eth_addr's that are local variables + * or known to be 32-bit aligned within the protocol header. */ +#ifndef ETHADDR32_COPY +#define ETHADDR32_COPY(src, dst) SMEMCPY(src, dst, ETHARP_HWADDR_LEN) +#endif + +/** MEMCPY-like macro to copy to/from struct eth_addr's that are no local + * variables and known to be 16-bit aligned within the protocol header. */ +#ifndef ETHADDR16_COPY +#define ETHADDR16_COPY(src, dst) SMEMCPY(src, dst, ETHARP_HWADDR_LEN) +#endif + +#if LWIP_ARP /* don't build if not configured for use in lwipopts.h */ + +/** ARP message types (opcodes) */ +#define ARP_REQUEST 1 +#define ARP_REPLY 2 + +/** Define this to 1 and define LWIP_ARP_FILTER_NETIF_FN(pbuf, netif, type) + * to a filter function that returns the correct netif when using multiple + * netifs on one hardware interface where the netif's low-level receive + * routine cannot decide for the correct netif (e.g. when mapping multiple + * IP addresses to one hardware interface). + */ +#ifndef LWIP_ARP_FILTER_NETIF +#define LWIP_ARP_FILTER_NETIF 0 +#endif + +#if ARP_QUEUEING +/** struct for queueing outgoing packets for unknown address + * defined here to be accessed by memp.h + */ +struct etharp_q_entry { + struct etharp_q_entry *next; + struct pbuf *p; +}; +#endif /* ARP_QUEUEING */ + +#define etharp_init() /* Compatibility define, not init needed. */ +void etharp_tmr(void); +s8_t etharp_find_addr(struct netif *netif, ip_addr_t *ipaddr, + struct eth_addr **eth_ret, ip_addr_t **ip_ret); +err_t etharp_output(struct netif *netif, struct pbuf *q, ip_addr_t *ipaddr); +err_t etharp_query(struct netif *netif, ip_addr_t *ipaddr, struct pbuf *q); +err_t etharp_request(struct netif *netif, ip_addr_t *ipaddr); +err_t etharp_update_arp_entry(struct netif *netif, ip_addr_t *ipaddr, struct eth_addr *ethaddr, u8_t flags); + +/** For Ethernet network interfaces, we might want to send "gratuitous ARP"; + * this is an ARP packet sent by a node in order to spontaneously cause other + * nodes to update an entry in their ARP cache. + * From RFC 3220 "IP Mobility Support for IPv4" section 4.6. */ +#define etharp_gratuitous(netif) etharp_request((netif), &(netif)->ip_addr) +void etharp_cleanup_netif(struct netif *netif); + +#if ETHARP_SUPPORT_STATIC_ENTRIES +err_t etharp_add_static_entry(ip_addr_t *ipaddr, struct eth_addr *ethaddr); +err_t etharp_remove_static_entry(ip_addr_t *ipaddr); +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ + +#if LWIP_AUTOIP +err_t etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr, + const struct eth_addr *ethdst_addr, + const struct eth_addr *hwsrc_addr, const ip_addr_t *ipsrc_addr, + const struct eth_addr *hwdst_addr, const ip_addr_t *ipdst_addr, + const u16_t opcode); +#endif /* LWIP_AUTOIP */ + +#endif /* LWIP_ARP */ + +err_t ethernet_input(struct pbuf *p, struct netif *netif); + +#define eth_addr_cmp(addr1, addr2) (memcmp((addr1)->addr, (addr2)->addr, ETHARP_HWADDR_LEN) == 0) + +extern const struct eth_addr ethbroadcast, ethzero; + +#endif /* LWIP_ARP || LWIP_ETHERNET */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NETIF_ARP_H__ */ diff --git a/Project/externalModules/lwip_v141/src/include/netif/ppp_oe.h b/Project/externalModules/lwip_v141/src/include/netif/ppp_oe.h new file mode 100644 index 0000000..67d8fe0 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/netif/ppp_oe.h @@ -0,0 +1,190 @@ +/***************************************************************************** +* ppp_oe.h - PPP Over Ethernet implementation for lwIP. +* +* Copyright (c) 2006 by Marc Boucher, Services Informatiques (MBSI) inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 06-01-01 Marc Boucher +* Ported to lwIP. +*****************************************************************************/ + + + +/* based on NetBSD: if_pppoe.c,v 1.64 2006/01/31 23:50:15 martin Exp */ + +/*- + * Copyright (c) 2002 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Martin Husemann . + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef PPP_OE_H +#define PPP_OE_H + +#include "lwip/opt.h" + +#if PPPOE_SUPPORT > 0 + +#include "netif/etharp.h" + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct pppoehdr { + PACK_STRUCT_FIELD(u8_t vertype); + PACK_STRUCT_FIELD(u8_t code); + PACK_STRUCT_FIELD(u16_t session); + PACK_STRUCT_FIELD(u16_t plen); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct pppoetag { + PACK_STRUCT_FIELD(u16_t tag); + PACK_STRUCT_FIELD(u16_t len); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + + +#define PPPOE_STATE_INITIAL 0 +#define PPPOE_STATE_PADI_SENT 1 +#define PPPOE_STATE_PADR_SENT 2 +#define PPPOE_STATE_SESSION 3 +#define PPPOE_STATE_CLOSING 4 +/* passive */ +#define PPPOE_STATE_PADO_SENT 1 + +#define PPPOE_HEADERLEN sizeof(struct pppoehdr) +#define PPPOE_VERTYPE 0x11 /* VER=1, TYPE = 1 */ + +#define PPPOE_TAG_EOL 0x0000 /* end of list */ +#define PPPOE_TAG_SNAME 0x0101 /* service name */ +#define PPPOE_TAG_ACNAME 0x0102 /* access concentrator name */ +#define PPPOE_TAG_HUNIQUE 0x0103 /* host unique */ +#define PPPOE_TAG_ACCOOKIE 0x0104 /* AC cookie */ +#define PPPOE_TAG_VENDOR 0x0105 /* vendor specific */ +#define PPPOE_TAG_RELAYSID 0x0110 /* relay session id */ +#define PPPOE_TAG_SNAME_ERR 0x0201 /* service name error */ +#define PPPOE_TAG_ACSYS_ERR 0x0202 /* AC system error */ +#define PPPOE_TAG_GENERIC_ERR 0x0203 /* gerneric error */ + +#define PPPOE_CODE_PADI 0x09 /* Active Discovery Initiation */ +#define PPPOE_CODE_PADO 0x07 /* Active Discovery Offer */ +#define PPPOE_CODE_PADR 0x19 /* Active Discovery Request */ +#define PPPOE_CODE_PADS 0x65 /* Active Discovery Session confirmation */ +#define PPPOE_CODE_PADT 0xA7 /* Active Discovery Terminate */ + +#ifndef ETHERMTU +#define ETHERMTU 1500 +#endif + +/* two byte PPP protocol discriminator, then IP data */ +#define PPPOE_MAXMTU (ETHERMTU-PPPOE_HEADERLEN-2) + +#ifndef PPPOE_MAX_AC_COOKIE_LEN +#define PPPOE_MAX_AC_COOKIE_LEN 64 +#endif + +struct pppoe_softc { + struct pppoe_softc *next; + struct netif *sc_ethif; /* ethernet interface we are using */ + int sc_pd; /* ppp unit number */ + void (*sc_linkStatusCB)(int pd, int up); + + int sc_state; /* discovery phase or session connected */ + struct eth_addr sc_dest; /* hardware address of concentrator */ + u16_t sc_session; /* PPPoE session id */ + +#ifdef PPPOE_TODO + char *sc_service_name; /* if != NULL: requested name of service */ + char *sc_concentrator_name; /* if != NULL: requested concentrator id */ +#endif /* PPPOE_TODO */ + u8_t sc_ac_cookie[PPPOE_MAX_AC_COOKIE_LEN]; /* content of AC cookie we must echo back */ + size_t sc_ac_cookie_len; /* length of cookie data */ +#ifdef PPPOE_SERVER + u8_t *sc_hunique; /* content of host unique we must echo back */ + size_t sc_hunique_len; /* length of host unique */ +#endif + int sc_padi_retried; /* number of PADI retries already done */ + int sc_padr_retried; /* number of PADR retries already done */ +}; + + +#define pppoe_init() /* compatibility define, no initialization needed */ + +err_t pppoe_create(struct netif *ethif, int pd, void (*linkStatusCB)(int pd, int up), struct pppoe_softc **scptr); +err_t pppoe_destroy(struct netif *ifp); + +int pppoe_connect(struct pppoe_softc *sc); +void pppoe_disconnect(struct pppoe_softc *sc); + +void pppoe_disc_input(struct netif *netif, struct pbuf *p); +void pppoe_data_input(struct netif *netif, struct pbuf *p); + +err_t pppoe_xmit(struct pppoe_softc *sc, struct pbuf *pb); + +/** used in ppp.c */ +#define PPPOE_HDRLEN (sizeof(struct eth_hdr) + PPPOE_HEADERLEN) + +#endif /* PPPOE_SUPPORT */ + +#endif /* PPP_OE_H */ diff --git a/Project/externalModules/lwip_v141/src/include/netif/slipif.h b/Project/externalModules/lwip_v141/src/include/netif/slipif.h new file mode 100644 index 0000000..9689c3f --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/netif/slipif.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __NETIF_SLIPIF_H__ +#define __NETIF_SLIPIF_H__ + +#include "lwip/opt.h" +#include "lwip/netif.h" + +/** Set this to 1 to start a thread that blocks reading on the serial line + * (using sio_read()). + */ +#ifndef SLIP_USE_RX_THREAD +#define SLIP_USE_RX_THREAD !NO_SYS +#endif + +/** Set this to 1 to enable functions to pass in RX bytes from ISR context. + * If enabled, slipif_received_byte[s]() process incoming bytes and put assembled + * packets on a queue, which is fed into lwIP from slipif_poll(). + * If disabled, slipif_poll() polls the serila line (using sio_tryread()). + */ +#ifndef SLIP_RX_FROM_ISR +#define SLIP_RX_FROM_ISR 0 +#endif + +/** Set this to 1 (default for SLIP_RX_FROM_ISR) to queue incoming packets + * received by slipif_received_byte[s]() as long as PBUF_POOL pbufs are available. + * If disabled, packets will be dropped if more than one packet is received. + */ +#ifndef SLIP_RX_QUEUE +#define SLIP_RX_QUEUE SLIP_RX_FROM_ISR +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +err_t slipif_init(struct netif * netif); +void slipif_poll(struct netif *netif); +#if SLIP_RX_FROM_ISR +void slipif_process_rxqueue(struct netif *netif); +void slipif_received_byte(struct netif *netif, u8_t data); +void slipif_received_bytes(struct netif *netif, u8_t *data, u8_t len); +#endif /* SLIP_RX_FROM_ISR */ + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Project/externalModules/lwip_v141/src/include/posix/netdb.h b/Project/externalModules/lwip_v141/src/include/posix/netdb.h new file mode 100644 index 0000000..8fc2596 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/posix/netdb.h @@ -0,0 +1,33 @@ +/** + * @file + * This file is a posix wrapper for lwip/netdb.h. + */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#include "lwip/netdb.h" diff --git a/Project/externalModules/lwip_v141/src/include/posix/sys/socket.h b/Project/externalModules/lwip_v141/src/include/posix/sys/socket.h new file mode 100644 index 0000000..5d2ab84 --- /dev/null +++ b/Project/externalModules/lwip_v141/src/include/posix/sys/socket.h @@ -0,0 +1,33 @@ +/** + * @file + * This file is a posix wrapper for lwip/sockets.h. + */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#include "lwip/sockets.h" diff --git a/Project/os/hal/dox/adc.dox b/Project/os/hal/dox/adc.dox new file mode 100644 index 0000000..d5fe363 --- /dev/null +++ b/Project/os/hal/dox/adc.dox @@ -0,0 +1,153 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup ADC ADC Driver + * @brief Generic ADC Driver. + * @details This module implements a generic ADC (Analog to Digital Converter) + * driver supporting a variety of buffer and conversion modes. + * @pre In order to use the ADC driver the @p HAL_USE_ADC option + * must be enabled in @p halconf.h. + * + * @section adc_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @if LATEX_PDF + * @dot + digraph example { + rankdir="LR"; + size="5, 7"; + + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="ADC_STOP\nLow Power"]; + uninit [label="ADC_UNINIT", style="bold"]; + ready [label="ADC_READY\nClock Enabled"]; + active [label="ADC_ACTIVE\nConverting"]; + error [label="ADC_ERROR\nError"]; + complete [label="ADC_COMPLETE\nComplete"]; + + uninit -> stop [label="\n adcInit()", constraint=false]; + stop -> ready [label="\nadcStart()"]; + ready -> ready [label="\nadcStart()\nadcStopConversion()"]; + ready -> stop [label="\nadcStop()"]; + stop -> stop [label="\nadcStop()"]; + ready -> active [label="\nadcStartConversion() (async)\nadcConvert() (sync)"]; + active -> ready [label="\nadcStopConversion()\nsync return"]; + active -> active [label="\nasync callback (half buffer)\nasync callback (full buffer circular)\n>acg_endcb<"]; + active -> complete [label="\n\nasync callback (full buffer)\n>end_cb<"]; + active -> error [label="\n\nasync callback (error)\n>error_cb<"]; + complete -> active [label="\nadcStartConversionI()\nthen\ncallback return"]; + complete -> ready [label="\ncallback return"]; + error -> active [label="\nadcStartConversionI()\nthen\ncallback return"]; + error -> ready [label="\ncallback return"]; + } + * @enddot + * @else + * @dot + digraph example { + rankdir="LR"; + + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="ADC_STOP\nLow Power"]; + uninit [label="ADC_UNINIT", style="bold"]; + ready [label="ADC_READY\nClock Enabled"]; + active [label="ADC_ACTIVE\nConverting"]; + error [label="ADC_ERROR\nError"]; + complete [label="ADC_COMPLETE\nComplete"]; + + uninit -> stop [label="\n adcInit()", constraint=false]; + stop -> ready [label="\nadcStart()"]; + ready -> ready [label="\nadcStart()\nadcStopConversion()"]; + ready -> stop [label="\nadcStop()"]; + stop -> stop [label="\nadcStop()"]; + ready -> active [label="\nadcStartConversion() (async)\nadcConvert() (sync)"]; + active -> ready [label="\nadcStopConversion()\nsync return"]; + active -> active [label="\nasync callback (half buffer)\nasync callback (full buffer circular)\n>acg_endcb<"]; + active -> complete [label="\n\nasync callback (full buffer)\n>end_cb<"]; + active -> error [label="\n\nasync callback (error)\n>error_cb<"]; + complete -> active [label="\nadcStartConversionI()\nthen\ncallback return"]; + complete -> ready [label="\ncallback return"]; + error -> active [label="\nadcStartConversionI()\nthen\ncallback return"]; + error -> ready [label="\ncallback return"]; + } + * @enddot + * @endif + * + * @section adc_2 ADC Operations + * The ADC driver is quite complex, an explanation of the terminology and of + * the operational details follows. + * + * @subsection adc_2_1 ADC Conversion Groups + * The @p ADCConversionGroup is the objects that specifies a physical + * conversion operation. This structure contains some standard fields and + * several implementation-dependent fields.
+ * The standard fields define the CG mode, the number of channels belonging + * to the CG and the optional callbacks.
+ * The implementation-dependent fields specify the physical ADC operation + * mode, the analog channels belonging to the group and any other + * implementation-specific setting. Usually the extra fields just mirror + * the physical ADC registers, please refer to the vendor's MCU Reference + * Manual for details about the available settings. Details are also available + * into the documentation of the ADC low level drivers and in the various + * sample applications. + * + * @subsection adc_2_2 ADC Conversion Modes + * The driver supports several conversion modes: + * - One Shot, the driver performs a single group conversion then stops. + * - Linear Buffer, the driver performs a series of group conversions + * then stops. This mode is like a one shot conversion repeated N times, + * the buffer pointer increases after each conversion. The buffer is + * organized as an S(CG)*N samples matrix, when S(CG) is the conversion + * group size (number of channels) and N is the buffer depth (number of + * repeated conversions). + * - Circular Buffer, much like the linear mode but the operation does + * not stop when the buffer is filled, it is automatically restarted + * with the buffer pointer wrapping back to the buffer base. + * . + * @subsection adc_2_3 ADC Callbacks + * The driver is able to invoke callbacks during the conversion process. A + * callback is invoked when the operation has been completed or, in circular + * mode, when the buffer has been filled and the operation is restarted. In + * linear and circular modes a callback is also invoked when the buffer is + * half filled.
+ * The "half filled" and "filled" callbacks in circular mode allow to + * implement "streaming processing" of the sampled data, while the driver is + * busy filling one half of the buffer the application can process the + * other half, this allows for continuous interleaved operations. + * + * The driver is not thread safe for performance reasons, if you need to access + * the ADC bus from multiple threads then use the @p adcAcquireBus() and + * @p adcReleaseBus() APIs in order to gain exclusive access. + * + * @ingroup IO + */ diff --git a/Project/os/hal/dox/can.dox b/Project/os/hal/dox/can.dox new file mode 100644 index 0000000..8da6a2c --- /dev/null +++ b/Project/os/hal/dox/can.dox @@ -0,0 +1,99 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup CAN CAN Driver + * @brief Generic CAN Driver. + * @details This module implements a generic CAN (Controller Area Network) + * driver allowing the exchange of information at frame level. + * @pre In order to use the CAN driver the @p HAL_USE_CAN option + * must be enabled in @p halconf.h. + * + * @section can_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @if LATEX_PDF + * @dot + digraph example { + size="5, 7"; + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="CAN_STOP\nLow Power"]; + uninit [label="CAN_UNINIT", style="bold"]; + starting [label="CAN_STARTING\nInitializing"]; + ready [label="CAN_READY\nClock Enabled"]; + sleep [label="CAN_SLEEP\nLow Power"]; + + uninit -> stop [label=" canInit()", constraint=false]; + stop -> stop [label="\ncanStop()"]; + stop -> ready [label="\ncanStart()\n(fast implementation)"]; + stop -> starting [label="\ncanStart()\n(slow implementation)"]; + starting -> starting [label="\ncanStart()\n(other thread)"]; + starting -> ready [label="\ninitialization complete\n(all threads)"]; + ready -> stop [label="\ncanStop()"]; + ready -> ready [label="\ncanStart()\ncanReceive()\ncanTransmit()"]; + ready -> sleep [label="\ncanSleep()"]; + sleep -> sleep [label="\ncanSleep()"]; + sleep -> ready [label="\ncanWakeup()"]; + sleep -> ready [label="\nhardware\nwakeup event"]; + } + * @enddot + * @else + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="CAN_STOP\nLow Power"]; + uninit [label="CAN_UNINIT", style="bold"]; + starting [label="CAN_STARTING\nInitializing"]; + ready [label="CAN_READY\nClock Enabled"]; + sleep [label="CAN_SLEEP\nLow Power"]; + + uninit -> stop [label=" canInit()", constraint=false]; + stop -> stop [label="\ncanStop()"]; + stop -> ready [label="\ncanStart()\n(fast implementation)"]; + stop -> starting [label="\ncanStart()\n(slow implementation)"]; + starting -> starting [label="\ncanStart()\n(other thread)"]; + starting -> ready [label="\ninitialization complete\n(all threads)"]; + ready -> stop [label="\ncanStop()"]; + ready -> ready [label="\ncanStart()\ncanReceive()\ncanTransmit()"]; + ready -> sleep [label="\ncanSleep()"]; + sleep -> sleep [label="\ncanSleep()"]; + sleep -> ready [label="\ncanWakeup()"]; + sleep -> ready [label="\nhardware\nwakeup event"]; + } + * @enddot + * @endif + * + * @ingroup IO + */ diff --git a/Project/os/hal/dox/ext.dox b/Project/os/hal/dox/ext.dox new file mode 100644 index 0000000..86e8b35 --- /dev/null +++ b/Project/os/hal/dox/ext.dox @@ -0,0 +1,91 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup EXT EXT Driver + * @brief Generic EXT Driver. + * @details This module implements a generic EXT (EXTernal) driver. + * @pre In order to use the EXT driver the @p HAL_USE_EXT option + * must be enabled in @p halconf.h. + * + * @section ext_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @if LATEX_PDF + * @dot + digraph example { + size="5, 7"; + rankdir="LR"; + + node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Sans, fontsize=8]; + + uninit [label="EXT_UNINIT", style="bold"]; + stop [label="EXT_STOP\nLow Power"]; + active [label="EXT_ACTIVE"]; + + uninit -> stop [label="extInit()"]; + stop -> stop [label="\nextStop()"]; + stop -> active [label="\nextStart()"]; + active -> stop [label="\nextStop()"]; + active -> active [label="\nextStart()"]; + } + * @enddot + * @else + * @dot + digraph example { + rankdir="LR"; + + node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Sans, fontsize=8]; + + uninit [label="EXT_UNINIT", style="bold"]; + stop [label="EXT_STOP\nLow Power"]; + active [label="EXT_ACTIVE"]; + + uninit -> stop [label="extInit()"]; + stop -> stop [label="\nextStop()"]; + stop -> active [label="\nextStart()"]; + active -> stop [label="\nextStop()"]; + active -> active [label="\nextStart()"]; + } + * @enddot + * @endif + * + * @section ext_2 EXT Operations. + * This driver abstracts generic external interrupt sources, a callback + * is invoked when a programmable transition is detected on one of the + * configured channels. Several channel modes are possible. + * - EXT_CH_MODE_DISABLED, channel not used. + * - EXT_CH_MODE_RISING_EDGE, callback on a rising edge. + * - EXT_CH_MODE_FALLING_EDGE, callback on a falling edge. + * - EXT_CH_MODE_BOTH_EDGES, callback on a both edges. + * . + * @ingroup IO + */ diff --git a/Project/os/hal/dox/gpt.dox b/Project/os/hal/dox/gpt.dox new file mode 100644 index 0000000..8c19d80 --- /dev/null +++ b/Project/os/hal/dox/gpt.dox @@ -0,0 +1,85 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup GPT GPT Driver + * @brief Generic GPT Driver. + * @details This module implements a generic GPT (General Purpose Timer) + * driver. The timer can be programmed in order to trigger callbacks + * after a specified time period or continuously with a specified + * interval. + * @pre In order to use the GPT driver the @p HAL_USE_GPT option + * must be enabled in @p halconf.h. + * + * @section gpt_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="GPT_STOP\nLow Power"]; + uninit [label="GPT_UNINIT", style="bold"]; + ready [label="GPT_READY\nClock Enabled"]; + continuous [label="GPT_CONT..S\nContinuous\nMode"]; + oneshot [label="GPT_ONESHOT\nOne Shot\nMode"]; + + uninit -> stop [label=" gptInit()", constraint=false]; + stop -> stop [label="\ngptStop()"]; + stop -> ready [label="\ngptStart()"]; + ready -> stop [label="\ngptStop()"]; + ready -> ready [label="\ngptStart()"]; + ready -> continuous [label="\ngptStartContinuous()"]; + continuous -> ready [label="\ngptStopTimer()"]; + continuous -> continuous [label=">callback<"]; + ready -> oneshot [label="\ngptStartOneShot()\ngptPolledDelay()"]; + oneshot -> ready [label="\n>callback<\nor\nDelay Over"]; + } + * @enddot + * + * @section gpt_2 GPT Operations. + * This driver abstracts a generic timer composed of: + * - A clock prescaler. + * - A main up counter. + * - A comparator register that resets the main counter to zero when the limit + * is reached. A callback is invoked when this happens. + * . + * The timer can operate in three different modes: + * - Continuous Mode, a periodic callback is invoked until the driver + * is explicitly stopped. + * - One Shot Mode, a callback is invoked after the programmed period + * and then the timer automatically stops. + * - Delay Mode, the timer is used for inserting a brief delay into + * the execution flow, no callback is invoked in this mode. + * . + * @ingroup IO + */ diff --git a/Project/os/hal/dox/hal.dox b/Project/os/hal/dox/hal.dox new file mode 100644 index 0000000..c943a9a --- /dev/null +++ b/Project/os/hal/dox/hal.dox @@ -0,0 +1,43 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup HAL HAL Driver + * @brief Hardware Abstraction Layer. + * @details The HAL (Hardware Abstraction Layer) driver performs the system + * initialization and includes the platform support code shared by + * the other drivers. This driver does contain any API function + * except for a general initialization function @p halInit() that + * must be invoked before any HAL service can be used, usually the + * HAL initialization should be performed immediately before the + * kernel initialization.
+ * Some HAL driver implementations also offer a custom early clock + * setup function that can be invoked before the C runtime + * initialization in order to accelerate the startup time. + * + * @ingroup IO + */ diff --git a/Project/os/hal/dox/i2c.dox b/Project/os/hal/dox/i2c.dox new file mode 100644 index 0000000..b5d5e10 --- /dev/null +++ b/Project/os/hal/dox/i2c.dox @@ -0,0 +1,109 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup I2C I2C Driver + * @brief Generic I2C Driver. + * @details This module implements a generic I2C (Inter-Integrated Circuit) + * driver. + * @pre In order to use the I2C driver the @p HAL_USE_I2C option + * must be enabled in @p halconf.h. + * + * @section i2c_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @if LATEX_PDF + * @dot + digraph example { + size="5, 7"; + rankdir="LR"; + + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="I2C_STOP\nLow Power"]; + uninit [label="I2C_UNINIT", style="bold"]; + ready [label="I2C_READY\nClock Enabled"]; + active_tx [label="I2C_ACTIVE_TX\nBus TX Active"]; + active_rx [label="I2C_ACTIVE_RX\nBus RX Active"]; + locked [label="I2C_LOCKED\nBus Locked"]; + + uninit -> stop [label="i2cInit()", constraint=false]; + stop -> stop [label="i2cStop()"]; + stop -> ready [label="i2cStart()"]; + ready -> ready [label="i2cStart()"]; + ready -> stop [label="i2cStop()"]; + ready -> active_tx [label="i2cMasterTransmit()"]; + ready -> active_rx [label="i2cMasterReceive()"]; + active_tx -> ready [label="completed"]; + active_rx -> ready [label="completed"]; + active_tx -> locked [label="RDY_TIMEOUT"]; + active_rx -> locked [label="RDY_TIMEOUT"]; + locked -> stop [label="i2cStop()"]; + locked -> ready [label="i2cStart()"]; + } + * @else + * @dot + digraph example { + rankdir="LR"; + + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="I2C_STOP\nLow Power"]; + uninit [label="I2C_UNINIT", style="bold"]; + ready [label="I2C_READY\nClock Enabled"]; + active_tx [label="I2C_ACTIVE_TX\nBus TX Active"]; + active_rx [label="I2C_ACTIVE_RX\nBus RX Active"]; + locked [label="I2C_LOCKED\nBus Locked"]; + + uninit -> stop [label="i2cInit()", constraint=false]; + stop -> stop [label="i2cStop()"]; + stop -> ready [label="i2cStart()"]; + ready -> ready [label="i2cStart()"]; + ready -> stop [label="i2cStop()"]; + ready -> active_tx [label="i2cMasterTransmit()"]; + ready -> active_rx [label="i2cMasterReceive()"]; + active_tx -> ready [label="completed"]; + active_rx -> ready [label="completed"]; + active_tx -> locked [label="RDY_TIMEOUT"]; + active_rx -> locked [label="RDY_TIMEOUT"]; + locked -> stop [label="i2cStop()"]; + locked -> ready [label="i2cStart()"]; + } + * @enddot + * @endif + * The driver is not thread safe for performance reasons, if you need to access + * the I2C bus from multiple threads then use the @p i2cAcquireBus() and + * @p i2cReleaseBus() APIs in order to gain exclusive access. + * + * @ingroup IO + */ diff --git a/Project/os/hal/dox/icu.dox b/Project/os/hal/dox/icu.dox new file mode 100644 index 0000000..6c39082 --- /dev/null +++ b/Project/os/hal/dox/icu.dox @@ -0,0 +1,122 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup ICU ICU Driver + * @brief Generic ICU Driver. + * @details This module implements a generic ICU (Input Capture Unit) driver. + * @pre In order to use the ICU driver the @p HAL_USE_ICU option + * must be enabled in @p halconf.h. + * + * @section icu_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @if LATEX_PDF + * @dot + digraph example { + size="5, 7"; + rankdir="LR"; + + node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Sans, fontsize=8]; + + stop [label="ICU_STOP\nLow Power"]; + uninit [label="ICU_UNINIT", style="bold"]; + ready [label="ICU_READY\nClock Enabled"]; + waiting [label="ICU_WAITING"]; + active [label="ICU_ACTIVE"]; + idle [label="ICU_IDLE"]; + + uninit -> stop [label=" icuInit()", constraint=false]; + stop -> stop [label="\nicuStop()"]; + stop -> ready [label="\nicuStart()"]; + ready -> stop [label="\nicuStop()"]; + ready -> ready [label="\nicuStart()\nicuDisable()"]; + ready -> waiting [label="\nicuEnable()"]; + waiting -> active [label="\nStart Front"]; + waiting -> ready [label="\nicuDisable()"]; + active -> idle [label="\nStop Front\n>width_cb<"]; + active -> ready [label="\nicuDisable()\nicuDisableI()"]; + idle -> active [label="\nStart Front\n>period_cb<"]; + idle -> ready [label="\nicuDisable()\nicuDisableI()"]; + } + * @enddot + * @else + * @dot + digraph example { + rankdir="LR"; + + node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Sans, fontsize=8]; + + stop [label="ICU_STOP\nLow Power"]; + uninit [label="ICU_UNINIT", style="bold"]; + ready [label="ICU_READY\nClock Enabled"]; + waiting [label="ICU_WAITING"]; + active [label="ICU_ACTIVE"]; + idle [label="ICU_IDLE"]; + + uninit -> stop [label=" icuInit()", constraint=false]; + stop -> stop [label="\nicuStop()"]; + stop -> ready [label="\nicuStart()"]; + ready -> stop [label="\nicuStop()"]; + ready -> ready [label="\nicuStart()\nicuDisable()"]; + ready -> waiting [label="\nicuEnable()"]; + waiting -> active [label="\nStart Front"]; + waiting -> ready [label="\nicuDisable()"]; + active -> idle [label="\nStop Front\n>width_cb<"]; + active -> ready [label="\nicuDisable()\nicuDisableI()"]; + idle -> active [label="\nStart Front\n>period_cb<"]; + idle -> ready [label="\nicuDisable()\nicuDisableI()"]; + } + * @enddot + * @endif + * + * @section icu_2 ICU Operations. + * This driver abstracts a generic Input Capture Unit composed of: + * - A clock prescaler. + * - A main up counter. + * - Two capture registers triggered by the rising and falling edges on + * the sampled input. + * . + * The ICU unit can be programmed to synchronize on the rising or falling + * edge of the sample input: + * - ICU_INPUT_ACTIVE_HIGH, a rising edge is the start signal. + * - ICU_INPUT_ACTIVE_LOW, a falling edge is the start signal. + * . + * After the activation the ICU unit can be in one of the following + * states at any time: + * - ICU_WAITING, waiting the first start signal. + * - ICU_ACTIVE, after a start signal. + * - ICU_IDLE, after a stop signal. + * . + * Callbacks are invoked when start or stop signals occur. + * + * @ingroup IO + */ diff --git a/Project/os/hal/dox/mac.dox b/Project/os/hal/dox/mac.dox new file mode 100644 index 0000000..bdb1e41 --- /dev/null +++ b/Project/os/hal/dox/mac.dox @@ -0,0 +1,37 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup MAC MAC Driver + * @brief Generic MAC driver. + * @details This module implements a generic MAC (Media Access Control) + * driver for Ethernet controllers. + * @pre In order to use the MAC driver the @p HAL_USE_MAC option + * must be enabled in @p halconf.h. + * + * @ingroup IO + */ diff --git a/Project/os/hal/dox/mmc_spi.dox b/Project/os/hal/dox/mmc_spi.dox new file mode 100644 index 0000000..bbe8d73 --- /dev/null +++ b/Project/os/hal/dox/mmc_spi.dox @@ -0,0 +1,126 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup MMC_SPI MMC over SPI Driver + * @brief Generic MMC driver. + * @details This module implements a portable MMC/SD driver that uses a SPI + * driver as physical layer. Hot plugging and removal are supported + * through kernel events. + * @pre In order to use the MMC_SPI driver the @p HAL_USE_MMC_SPI and + * @p HAL_USE_SPI options must be enabled in @p halconf.h. + * + * @section mmc_spi_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @if LATEX_PDF + * @dot + digraph example { + size="5, 7"; + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + any [label="Any State"]; + stop2 [label="MMC_STOP\nLow Power"]; + uninit [label="MMC_UNINIT", style="bold"]; + stop [label="MMC_STOP\nLow Power"]; + wait [label="MMC_WAIT\nWaiting Card"]; + inserted [label="MMC_INSERTED\nCard Inserted"]; + ready [label="MMC_READY\nCard Ready"]; + reading [label="MMC_READING\nReading"]; + writing [label="MMC_WRITING\nWriting"]; + + uninit -> stop [label="mmcInit()"]; + stop -> wait [label="mmcStart()", constraint=false]; + wait -> inserted [label="insertion (inserted event)"]; + inserted -> inserted [label="mmcDisconnect()"]; + inserted -> ready [label="mmcConnect()"]; + ready -> ready [label="mmcConnect()"]; + ready -> inserted [label="mmcDisconnect()"]; + ready -> reading [label="mmcStartSequentialRead()"]; + reading -> reading [label="mmcSequentialRead()"]; + reading -> ready [label="mmcStopSequentialRead()"]; + reading -> ready [label="read error"]; + ready -> writing [label="mmcStartSequentialWrite()"]; + writing -> writing [label="mmcSequentialWrite()"]; + writing -> ready [label="mmcStopSequentialWrite()"]; + writing -> ready [label="write error"]; + inserted -> wait [label="removal (removed event)"]; + ready -> wait [label="removal (removed event)"]; + reading -> wait [label="removal (removed event)"]; + writing -> wait [label="removal (removed event)"]; + + any -> stop2 [label="mmcStop()"]; + } + * @enddot + * @else + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + any [label="Any State"]; + stop2 [label="MMC_STOP\nLow Power"]; + uninit [label="MMC_UNINIT", style="bold"]; + stop [label="MMC_STOP\nLow Power"]; + wait [label="MMC_WAIT\nWaiting Card"]; + inserted [label="MMC_INSERTED\nCard Inserted"]; + ready [label="MMC_READY\nCard Ready"]; + reading [label="MMC_READING\nReading"]; + writing [label="MMC_WRITING\nWriting"]; + + uninit -> stop [label="mmcInit()"]; + stop -> wait [label="mmcStart()", constraint=false]; + wait -> inserted [label="insertion (inserted event)"]; + inserted -> inserted [label="mmcDisconnect()"]; + inserted -> ready [label="mmcConnect()"]; + ready -> ready [label="mmcConnect()"]; + ready -> inserted [label="mmcDisconnect()"]; + ready -> reading [label="mmcStartSequentialRead()"]; + reading -> reading [label="mmcSequentialRead()"]; + reading -> ready [label="mmcStopSequentialRead()"]; + reading -> ready [label="read error"]; + ready -> writing [label="mmcStartSequentialWrite()"]; + writing -> writing [label="mmcSequentialWrite()"]; + writing -> ready [label="mmcStopSequentialWrite()"]; + writing -> ready [label="write error"]; + inserted -> wait [label="removal (removed event)"]; + ready -> wait [label="removal (removed event)"]; + reading -> wait [label="removal (removed event)"]; + writing -> wait [label="removal (removed event)"]; + + any -> stop2 [label="mmcStop()"]; + } + * @enddot + * @endif + * + * @ingroup IO + */ diff --git a/Project/os/hal/dox/pal.dox b/Project/os/hal/dox/pal.dox new file mode 100644 index 0000000..f736bec --- /dev/null +++ b/Project/os/hal/dox/pal.dox @@ -0,0 +1,81 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup PAL PAL Driver + * @brief I/O Ports Abstraction Layer + * @details This module defines an abstract interface for digital I/O ports. + * Note that most I/O ports functions are just macros. The macros + * have default software implementations that can be redefined in a + * PAL Low Level Driver if the target hardware supports special + * features like, for example, atomic bit set/reset/masking. Please + * refer to the ports specific documentation for details.
+ * The @ref PAL has the advantage to make the access to the I/O + * ports platform independent and still be optimized for the specific + * architectures.
+ * Note that the PAL Low Level Driver may also offer non standard + * macro and functions in order to support specific features but, + * of course, the use of such interfaces would not be portable. + * Such interfaces shall be marked with the architecture name inside + * the function names. + * @pre In order to use the PAL driver the @p HAL_USE_PAL option + * must be enabled in @p halconf.h. + * + * @section pal_1 Implementation Rules + * In implementing a PAL Low Level Driver there are some rules/behaviors that + * should be respected. + * + * @subsection pal_1_1 Writing on input pads + * The behavior is not specified but there are implementations better than + * others, this is the list of possible implementations, preferred options + * are on top: + * -# The written value is not actually output but latched, should the pads + * be reprogrammed as outputs the value would be in effect. + * -# The write operation is ignored. + * -# The write operation has side effects, as example disabling/enabling + * pull up/down resistors or changing the pad direction. This scenario is + * discouraged, please try to avoid this scenario. + * . + * @subsection pal_1_2 Reading from output pads + * The behavior is not specified but there are implementations better than + * others, this is the list of possible implementations, preferred options + * are on top: + * -# The actual pads states are read (not the output latch). + * -# The output latch value is read (regardless of the actual pads states). + * -# Unspecified, please try to avoid this scenario. + * . + * @subsection pal_1_3 Writing unused or unimplemented port bits + * The behavior is not specified. + * + * @subsection pal_1_4 Reading from unused or unimplemented port bits + * The behavior is not specified. + * + * @subsection pal_1_5 Reading or writing on pins associated to other functionalities + * The behavior is not specified. + * + * @ingroup IO + */ diff --git a/Project/os/hal/dox/pwm.dox b/Project/os/hal/dox/pwm.dox new file mode 100644 index 0000000..506ae2e --- /dev/null +++ b/Project/os/hal/dox/pwm.dox @@ -0,0 +1,76 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup PWM PWM Driver + * @brief Generic PWM Driver. + * @details This module implements a generic PWM (Pulse Width Modulation) + * driver. + * @pre In order to use the PWM driver the @p HAL_USE_PWM option + * must be enabled in @p halconf.h. + * + * @section pwm_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + uninit [label="PWM_UNINIT", style="bold"]; + stop [label="PWM_STOP\nLow Power"]; + ready [label="PWM_READY\nClock Enabled"]; + uninit -> stop [label="pwmInit()"]; + stop -> stop [label="pwmStop()"]; + stop -> ready [label="pwmStart()"]; + ready -> stop [label="pwmStop()"]; + ready -> ready [label="pwmEnableChannel()\npwmDisableChannel()"]; + } + * @enddot + * + * @section pwm_2 PWM Operations. + * This driver abstracts a generic PWM timer composed of: + * - A clock prescaler. + * - A main up counter. + * - A comparator register that resets the main counter to zero when the limit + * is reached. An optional callback can be generated when this happens. + * - An array of @p PWM_CHANNELS PWM channels, each channel has an output, + * a comparator and is able to invoke an optional callback when a comparator + * match with the main counter happens. + * . + * A PWM channel output can be in two different states: + * - IDLE, when the channel is disabled or after a match occurred. + * - ACTIVE, when the channel is enabled and a match didn't occur yet + * in the current PWM cycle. + * . + * Note that the two states can be associated to both logical zero or one in + * the @p PWMChannelConfig structure. + * + * @ingroup IO + */ diff --git a/Project/os/hal/dox/rtc.dox b/Project/os/hal/dox/rtc.dox new file mode 100644 index 0000000..211e015 --- /dev/null +++ b/Project/os/hal/dox/rtc.dox @@ -0,0 +1,37 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup RTC RTC Driver + * @brief Real Time Clock Abstraction Layer + * @details This module defines an abstract interface for a Real Time Clock + * Peripheral. + * @pre In order to use the RTC driver the @p HAL_USE_RTC option + * must be enabled in @p halconf.h. + * + * @ingroup IO + */ diff --git a/Project/os/hal/dox/sdc.dox b/Project/os/hal/dox/sdc.dox new file mode 100644 index 0000000..bffd281 --- /dev/null +++ b/Project/os/hal/dox/sdc.dox @@ -0,0 +1,116 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup SDC SDC Driver + * @brief Generic SD Card Driver. + * @details This module implements a generic SDC (Secure Digital Card) driver. + * @pre In order to use the SDC driver the @p HAL_USE_SDC option + * must be enabled in @p halconf.h. + * + * @section sdc_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @if LATEX_PDF + * @dot + digraph example { + size="5, 7"; + rankdir="LR"; + + node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Sans, fontsize=8]; + + stop [label="SDC_STOP\nLow Power"]; + uninit [label="SDC_UNINIT", style="bold"]; + ready [label="SDC_READY\nClock Enabled"]; + connecting [label="SDC_CONN.ING\nConnecting"]; + disconnecting [label="SDC_DISC.ING\nDisconnecting"]; + active [label="SDC_ACTIVE\nCard Ready"]; + reading [label="SDC_READING\nReading"]; + writing [label="SDC_WRITING\nWriting"]; + + uninit -> stop [label=" sdcInit()", constraint=false]; + stop -> stop [label="\nsdcStop()"]; + stop -> ready [label="\nsdcStart()"]; + ready -> stop [label="\nsdcStop()"]; + ready -> ready [label="\nsdcStart()\nsdcDisconnect()"]; + ready -> connecting [label="\nsdcConnect()"]; + connecting -> active [label="\nconnection\nsuccessful"]; + connecting -> active [label="\nsdcConnect()", dir="back"]; + connecting -> ready [label="\nconnection\nfailed"]; + disconnecting -> active [label="\nsdcDisconnect()", dir="back"]; + ready -> disconnecting [label="\ndisconnection\nfinished", dir="back"]; + active -> reading [label="\nsdcRead()"]; + reading -> active [label="\nread finished\nread error"]; + active -> writing [label="\nsdcWrite()"]; + writing -> active [label="\nwrite finished\nwrite error"]; + } + * @enddot + * @else + * @dot + digraph example { + rankdir="LR"; + + node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Sans, fontsize=8]; + + stop [label="SDC_STOP\nLow Power"]; + uninit [label="SDC_UNINIT", style="bold"]; + ready [label="SDC_READY\nClock Enabled"]; + connecting [label="SDC_CONN.ING\nConnecting"]; + disconnecting [label="SDC_DISC.ING\nDisconnecting"]; + active [label="SDC_ACTIVE\nCard Ready"]; + reading [label="SDC_READING\nReading"]; + writing [label="SDC_WRITING\nWriting"]; + + uninit -> stop [label=" sdcInit()", constraint=false]; + stop -> stop [label="\nsdcStop()"]; + stop -> ready [label="\nsdcStart()"]; + ready -> stop [label="\nsdcStop()"]; + ready -> ready [label="\nsdcStart()\nsdcDisconnect()"]; + ready -> connecting [label="\nsdcConnect()"]; + connecting -> active [label="\nconnection\nsuccessful"]; + connecting -> active [label="\nsdcConnect()", dir="back"]; + connecting -> ready [label="\nconnection\nfailed"]; + disconnecting -> active [label="\nsdcDisconnect()", dir="back"]; + ready -> disconnecting [label="\ndisconnection\nfinished", dir="back"]; + active -> reading [label="\nsdcRead()"]; + reading -> active [label="\nread finished\nread error"]; + active -> writing [label="\nsdcWrite()"]; + writing -> active [label="\nwrite finished\nwrite error"]; + } + * @enddot + * @endif + * + * @section sdc_2 SDC Operations. + * This driver allows to read or write single or multiple 512 bytes blocks + * on a SD Card. + * + * @ingroup IO + */ diff --git a/Project/os/hal/dox/serial.dox b/Project/os/hal/dox/serial.dox new file mode 100644 index 0000000..67fcea7 --- /dev/null +++ b/Project/os/hal/dox/serial.dox @@ -0,0 +1,68 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup SERIAL Serial Driver + * @brief Generic Serial Driver. + * @details This module implements a generic full duplex serial driver. The + * driver implements a @p SerialDriver interface and uses I/O Queues + * for communication between the upper and the lower driver. Event + * flags are used to notify the application about incoming data, + * outgoing data and other I/O events.
+ * The module also contains functions that make the implementation + * of the interrupt service routines much easier. + * @pre In order to use the SERIAL driver the @p HAL_USE_SERIAL option + * must be enabled in @p halconf.h. + * + * + * @section serial_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + uninit [label="SD_UNINIT", style="bold"]; + stop [label="SD_STOP\nLow Power"]; + ready [label="SD_READY\nClock Enabled"]; + + uninit -> stop [label=" sdInit()"]; + stop -> stop [label="\nsdStop()"]; + stop -> ready [label="\nsdStart()"]; + ready -> stop [label="\nsdStop()"]; + ready -> ready [label="\nsdStart()"]; + ready -> ready [label="\nAny I/O operation"]; + } + * @enddot + * + * @ingroup IO + */ diff --git a/Project/os/hal/dox/serial_usb.dox b/Project/os/hal/dox/serial_usb.dox new file mode 100644 index 0000000..6579166 --- /dev/null +++ b/Project/os/hal/dox/serial_usb.dox @@ -0,0 +1,63 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup SERIAL_USB Serial over USB Driver + * @brief Serial over USB Driver. + * @details This module implements an USB Communication Device Class + * (CDC) as a normal serial communication port accessible from + * the device application. + * @pre In order to use the USB over Serial driver the + * @p HAL_USE_SERIAL_USB option must be enabled in @p halconf.h. + * + * @section usb_serial_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + uninit [label="SDU_UNINIT", style="bold"]; + stop [label="SDU_STOP\nLow Power"]; + ready [label="SDU_READY\nClock Enabled"]; + + uninit -> stop [label=" sduInit()"]; + stop -> stop [label="\nsduStop()"]; + stop -> ready [label="\nsduStart()"]; + ready -> stop [label="\nsduStop()"]; + ready -> ready [label="\nsduStart()"]; + ready -> ready [label="\nAny I/O operation"]; + } + * @enddot + * + * @ingroup IO + */ diff --git a/Project/os/hal/dox/spi.dox b/Project/os/hal/dox/spi.dox new file mode 100644 index 0000000..b0a5ba2 --- /dev/null +++ b/Project/os/hal/dox/spi.dox @@ -0,0 +1,101 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup SPI SPI Driver + * @brief Generic SPI Driver. + * @details This module implements a generic SPI (Serial Peripheral Interface) + * driver allowing bidirectional and monodirectional transfers, + * complex atomic transactions are supported as well. + * @pre In order to use the SPI driver the @p HAL_USE_SPI option + * must be enabled in @p halconf.h. + * + * @section spi_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @if LATEX_PDF + * @dot + digraph example { + size="5, 7"; + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="SPI_STOP\nLow Power"]; + uninit [label="SPI_UNINIT", style="bold"]; + ready [label="SPI_READY\nClock Enabled"]; + active [label="SPI_ACTIVE\nBus Active"]; + complete [label="SPI_COMPLETE\nComplete"]; + + uninit -> stop [label="\n spiInit()", constraint=false]; + stop -> ready [label="\nspiStart()"]; + ready -> ready [label="\nspiSelect()\nspiUnselect()\nspiStart()"]; + ready -> stop [label="\nspiStop()"]; + stop -> stop [label="\nspiStop()"]; + ready -> active [label="\nspiStartXXXI() (async)\nspiXXX() (sync)"]; + active -> ready [label="\nsync return"]; + active -> complete [label="\nasync callback\n>spc_endcb<"]; + complete -> active [label="\nspiStartXXXI() (async)\nthen\ncallback return"]; + complete -> ready [label="\ncallback return"]; + } + * @enddot + * @else + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="SPI_STOP\nLow Power"]; + uninit [label="SPI_UNINIT", style="bold"]; + ready [label="SPI_READY\nClock Enabled"]; + active [label="SPI_ACTIVE\nBus Active"]; + complete [label="SPI_COMPLETE\nComplete"]; + + uninit -> stop [label="\n spiInit()", constraint=false]; + stop -> ready [label="\nspiStart()"]; + ready -> ready [label="\nspiSelect()\nspiUnselect()\nspiStart()"]; + ready -> stop [label="\nspiStop()"]; + stop -> stop [label="\nspiStop()"]; + ready -> active [label="\nspiStartXXX() (async)\nspiXXX() (sync)"]; + active -> ready [label="\nsync return"]; + active -> complete [label="\nasync callback\n>spc_endcb<"]; + complete -> active [label="\nspiStartXXXI() (async)\nthen\ncallback return"]; + complete -> ready [label="\ncallback return"]; + } + * @enddot + * @endif + * + * The driver is not thread safe for performance reasons, if you need to access + * the SPI bus from multiple threads then use the @p spiAcquireBus() and + * @p spiReleaseBus() APIs in order to gain exclusive access. + * + * @ingroup IO + */ diff --git a/Project/os/hal/dox/tm.dox b/Project/os/hal/dox/tm.dox new file mode 100644 index 0000000..8acdf0a --- /dev/null +++ b/Project/os/hal/dox/tm.dox @@ -0,0 +1,38 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup TM Time Measurement Driver. + * + * @brief Time Measurement unit. + * @details This module implements a time measurement mechanism able to + * monitor a portion of code and store the best/worst/last + * measurement. The measurement is performed using the realtime + * counter mechanism abstracted in the HAL driver. + * + * @ingroup IO + */ diff --git a/Project/os/hal/dox/uart.dox b/Project/os/hal/dox/uart.dox new file mode 100644 index 0000000..f4e9f9f --- /dev/null +++ b/Project/os/hal/dox/uart.dox @@ -0,0 +1,132 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup UART UART Driver + * @brief Generic UART Driver. + * @details This driver abstracts a generic UART (Universal Asynchronous + * Receiver Transmitter) peripheral, the API is designed to be: + * - Unbuffered and copy-less, transfers are always directly performed + * from/to the application-level buffers without extra copy + * operations. + * - Asynchronous, the API is always non blocking. + * - Callbacks capable, operations completion and other events are + * notified using callbacks. + * . + * Special hardware features like deep hardware buffers, DMA transfers + * are hidden to the user but fully supportable by the low level + * implementations.
+ * This driver model is best used where communication events are + * meant to drive an higher level state machine, as example: + * - RS485 drivers. + * - Multipoint network drivers. + * - Serial protocol decoders. + * . + * If your application requires a synchronous buffered driver then + * the @ref SERIAL should be used instead. + * @pre In order to use the UART driver the @p HAL_USE_UART option + * must be enabled in @p halconf.h. + * + * @section uart_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + uninit [label="UART_UNINIT", style="bold"]; + stop [label="UART_STOP\nLow Power"]; + ready [label="UART_READY\nClock Enabled"]; + + uninit -> stop [label="\nuartInit()"]; + stop -> ready [label="\nuartStart()"]; + ready -> ready [label="\nuartStart()"]; + ready -> stop [label="\nuartStop()"]; + stop -> stop [label="\nuartStop()"]; + } + * @enddot + * + * @subsection uart_1_1 Transmitter sub State Machine + * The follow diagram describes the transmitter state machine, this diagram + * is valid while the driver is in the @p UART_READY state. This state + * machine is automatically reset to the @p TX_IDLE state each time the + * driver enters the @p UART_READY state. + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + tx_idle [label="TX_IDLE", style="bold"]; + tx_active [label="TX_ACTIVE"]; + tx_complete [label="TX_COMPLETE"]; + tx_fatal [label="Fatal Error", style="bold"]; + + tx_idle -> tx_active [label="\nuartStartSend()"]; + tx_idle -> tx_idle [label="\nuartStopSend()\n>uc_txend2<"]; + tx_active -> tx_complete [label="\nbuffer transmitted\n>uc_txend1<"]; + tx_active -> tx_idle [label="\nuartStopSend()"]; + tx_active -> tx_fatal [label="\nuartStartSend()"]; + tx_complete -> tx_active [label="\nuartStartSendI()\nthen\ncallback return"]; + tx_complete -> tx_idle [label="\ncallback return"]; + } + * @enddot + * + * @subsection uart_1_2 Receiver sub State Machine + * The follow diagram describes the receiver state machine, this diagram + * is valid while the driver is in the @p UART_READY state. This state + * machine is automatically reset to the @p RX_IDLE state each time the + * driver enters the @p UART_READY state. + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + rx_idle [label="RX_IDLE", style="bold"]; + rx_active [label="RX_ACTIVE"]; + rx_complete [label="RX_COMPLETE"]; + rx_fatal [label="Fatal Error", style="bold"]; + + rx_idle -> rx_idle [label="\nuartStopReceive()\n>uc_rxchar<\n>uc_rxerr<"]; + rx_idle -> rx_active [label="\nuartStartReceive()"]; + + rx_active -> rx_complete [label="\nbuffer filled\n>uc_rxend<"]; + rx_active -> rx_idle [label="\nuartStopReceive()"]; + rx_active -> rx_active [label="\nreceive error\n>uc_rxerr<"]; + rx_active -> rx_fatal [label="\nuartStartReceive()"]; + rx_complete -> rx_active [label="\nuartStartReceiveI()\nthen\ncallback return"]; + rx_complete -> rx_idle [label="\ncallback return"]; + } + * @enddot + * + * @ingroup IO + */ diff --git a/Project/os/hal/dox/usb.dox b/Project/os/hal/dox/usb.dox new file mode 100644 index 0000000..6c3806f --- /dev/null +++ b/Project/os/hal/dox/usb.dox @@ -0,0 +1,246 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup USB USB Driver + * @brief Generic USB Driver. + * @details This module implements a generic USB (Universal Serial Bus) driver + * supporting device-mode operations. + * @pre In order to use the USB driver the @p HAL_USE_USB option + * must be enabled in @p halconf.h. + * + * @section usb_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @if LATEX_PDF + * @dot + digraph example { + size="5, 7"; + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="USB_STOP\nLow Power"]; + uninit [label="USB_UNINIT", style="bold"]; + ready [label="USB_READY\nClock Enabled"]; + selected [label="\nUSB_SELECTED\naddress\nassigned"]; + configured [label="\nUSB_ACTIVE\nconfiguration\nselected"]; + + uninit -> stop [label=" usbInit()", constraint=false]; + stop -> stop [label="\nusbStop()"]; + stop -> ready [label="\nusbStart()"]; + ready -> stop [label="\nusbStop()"]; + ready -> ready [label="\n\nusbStart()"]; + ready -> ready [label="\nSUSPEND/WAKEUP\n>event_cb<"]; + ready -> selected [label="\nSET_ADDRESS\n>event_cb<"]; + selected -> ready [label="\nUSB RESET\n>event_cb<"]; + selected -> selected [label="\nSUSPEND/WAKEUP\n>event_cb<\n\nValid EP0 Message\n>requests_hook_cb<\n\nGET DESCRIPTOR\n>get_descriptor_cb<"]; + selected -> configured [label="\nSET_CONF(n)\n>event_cb<"]; + configured -> selected [label="\nSET_CONF(0)\n>event_cb<"]; + configured -> configured [label="\nSUSPEND/WAKEUP\n>event_cb<\n\nValid EP0 Message\n>requests_hook_cb<\n\nGET DESCRIPTOR\n>get_descriptor_cb<\n\nEndpoints Activity\n >in_cb< or >out_cb<"]; + configured -> ready [label="\nUSB RESET\n>event_cb<"]; + } + * @enddot + * @else + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + stop [label="USB_STOP\nLow Power"]; + uninit [label="USB_UNINIT", style="bold"]; + ready [label="USB_READY\nClock Enabled"]; + selected [label="\nUSB_SELECTED\naddress\nassigned"]; + configured [label="\nUSB_ACTIVE\nconfiguration\nselected"]; + + uninit -> stop [label=" usbInit()", constraint=false]; + stop -> stop [label="\nusbStop()"]; + stop -> ready [label="\nusbStart()"]; + ready -> stop [label="\nusbStop()"]; + ready -> ready [label="\n\nusbStart()"]; + ready -> ready [label="\nSUSPEND/WAKEUP\n>event_cb<"]; + ready -> selected [label="\nSET_ADDRESS\n>event_cb<"]; + selected -> ready [label="\nUSB RESET\n>event_cb<"]; + selected -> selected [label="\nSUSPEND/WAKEUP\n>event_cb<\n\nValid EP0 Message\n>requests_hook_cb<\n\nGET DESCRIPTOR\n>get_descriptor_cb<"]; + selected -> configured [label="\nSET_CONF(n)\n>event_cb<"]; + configured -> selected [label="\nSET_CONF(0)\n>event_cb<"]; + configured -> configured [label="\nSUSPEND/WAKEUP\n>event_cb<\n\nValid EP0 Message\n>requests_hook_cb<\n\nGET DESCRIPTOR\n>get_descriptor_cb<\n\nEndpoints Activity\n >in_cb< or >out_cb<"]; + configured -> ready [label="\nUSB RESET\n>event_cb<"]; + } + * @enddot + * @endif + * + * @section usb_2 USB Operations + * The USB driver is quite complex and USB is complex in itself, it is + * recommended to study the USB specification before trying to use the + * driver. + * + * @subsection usb_2_1 USB Implementation + * The USB driver abstracts the inner details of the underlying USB hardware. + * The driver works asynchronously and communicates with the application + * using callbacks. The application is responsible of the descriptors and + * strings required by the USB device class to be implemented and of the + * handling of the specific messages sent over the endpoint zero. Standard + * messages are handled internally to the driver. The application can use + * hooks in order to handle custom messages or override the handling of the + * default handling of standard messages. + * + * @subsection usb_2_2 USB Endpoints + * USB endpoints are the objects that the application uses to exchange + * data with the host. There are two kind of endpoints: + * - IN endpoints are used by the application to transmit data to + * the host.
+ * - OUT endpoints are used by the application to receive data from + * the host. + * . + * In ChibiOS/RT the endpoints can be configured in two distinct ways: + * - Packet Mode. In this mode the driver invokes a callback each + * time a packet has been received or transmitted. This mode is especially + * suited for those applications handling continuous streams of data. + *

+ * States diagram for OUT endpoints in packet mode: + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + disabled [label="EP_DISABLED\nDisabled", style="bold"]; + receiving [label="EP_BUSY\nReceiving Packet"]; + idle [label="EP_IDLE\nPacket in Buffer"]; + + disabled -> receiving [label="\nusbInitEndpointI()"]; + receiving -> idle [label="\npacket received\n>out_cb<"]; + idle -> receiving [label="\nusbReadPacketBuffer()\nusbStartReceiveI()"]; + receiving -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"]; + idle -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"]; + } + * @enddot + *

+ * States diagram for IN endpoints in packet mode: + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + disabled [label="EP_DISABLED\nDisabled", style="bold"]; + transmitting [label="EP_BUSY\nSending Packet"]; + idle [label="EP_IDLE\nBuffer Empty"]; + + disabled -> idle [label="\nusbInitEndpointI()"]; + idle -> transmitting [label="\nusbWritePacketBuffer()\nusbStartTransmitI()"]; + transmitting -> idle [label="\npacket sent\n>in_cb<"]; + transmitting -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"]; + idle -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"]; + } + * @enddot + *

+ * - Transaction Mode. In this mode the driver invokes a callback + * only after a large, potentially multi-packet, transfer has been + * completed, a callback is invoked only at the end of the transfer. + *

+ * States diagram for OUT endpoints in transaction mode: + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + disabled [label="EP_DISABLED\nDisabled", style="bold"]; + receiving [label="EP_BUSY\nReceiving"]; + idle [label="EP_IDLE\nReady"]; + + disabled -> idle [label="\nusbInitEndpointI()"]; + idle -> receiving [label="\nusbPrepareReceive()\nusbStartReceiveI()"]; + receiving -> receiving [label="\nmore packets"]; + receiving -> idle [label="\nreception end\n>out_cb<"]; + receiving -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"]; + idle -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"]; + } + * @enddot + *

+ * States diagram for IN endpoints in transaction mode: + * @dot + digraph example { + rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", + width="0.9", height="0.9"]; + edge [fontname=Helvetica, fontsize=8]; + + disabled [label="EP_DISABLED\nDisabled", style="bold"]; + transmitting [label="EP_BUSY\nTransmitting"]; + idle [label="EP_IDLE\nReady"]; + + disabled -> idle [label="\usbInitEndpointI()"]; + idle -> transmitting [label="\nusbPrepareTransmit()\nusbStartTransmitI()"]; + transmitting -> transmitting [label="\nmore packets"]; + transmitting -> idle [label="\ntransmission end\n>in_cb<"]; + transmitting -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"]; + idle -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"]; + } + * @enddot + *

+ * . + * @subsection usb_2_3 USB Packet Buffers + * An important difference between packet and transaction modes is that there + * is a dedicated endpoint buffer in packet mode while in transaction mode + * the application has to specify its own buffer for duration of the whole + * transfer.
+ * Packet buffers cannot be accessed directly by the application because those + * could not be necessarily memory mapped, a buffer could be a FIFO or some + * other kind of memory accessible in a special way depending on the + * underlying hardware architecture, the functions @p usbReadPacketI() and + * @p usbWritePacketI() allow to access packet buffers in an abstract way. + * + * @subsection usb_2_4 USB Callbacks + * The USB driver uses callbacks in order to interact with the application. + * There are several kinds of callbacks to be handled: + * - Driver events callback. As example errors, suspend event, reset event + * etc. + * - Messages Hook callback. This hook allows the application to implement + * handling of custom messages or to override the default handling of + * standard messages on endpoint zero. + * - Descriptor Requested callback. When the driver endpoint zero handler + * receives a GET DESCRIPTOR message and needs to send a descriptor to + * the host it queries the application using this callback. + * - Start of Frame callback. This callback is invoked each time a SOF + * packet is received. + * - Endpoint callbacks. Each endpoint informs the application about I/O + * conditions using those callbacks. + * . + * + * @ingroup IO + */ diff --git a/Project/os/hal/hal.dox b/Project/os/hal/hal.dox new file mode 100644 index 0000000..e9da57a --- /dev/null +++ b/Project/os/hal/hal.dox @@ -0,0 +1,90 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup IO HAL + * @brief Hardware Abstraction Layer. + * @details Under ChibiOS/RT the set of the various device driver interfaces + * is called the HAL subsystem: Hardware Abstraction Layer. The HAL is the + * abstract interface between ChibiOS/RT application and hardware. + * + * @section hal_device_driver_arch HAL Device Drivers Architecture + * A device driver is usually split in two layers: + * - High Level Device Driver (HLD). This layer contains the definitions + * of the driver's APIs and the platform independent part of the driver.
+ * An HLD is composed by two files: + * - @p @.c, the HLD implementation file. This file must be + * included in the Makefile in order to use the driver. + * - @p @.h, the HLD header file. This file is implicitly + * included by the HAL header file @p hal.h. + * . + * - Low Level Device Driver (LLD). This layer contains the platform + * dependent part of the driver.
+ * A LLD is composed by two files: + * - @p @_lld.c, the LLD implementation file. This file must be + * included in the Makefile in order to use the driver. + * - @p @_lld.h, the LLD header file. This file is implicitly + * included by the HLD header file. + * . + * The LLD may be not present in those drivers that do not access the + * hardware directly but through other device drivers, as example the + * MMC_SPI driver uses the SPI and PAL drivers in order to implement + * its functionalities. + * . + * @subsection hal_device_driver_diagram Diagram + * @dot + digraph example { + graph [size="5, 7", pad="1.5, 0"]; + node [shape=rectangle, fontname=Helvetica, fontsize=8, + fixedsize="true", width="2.0", height="0.4"]; + edge [fontname=Helvetica, fontsize=8]; + + app [label="Application"]; + hld [label="High Level Driver"]; + lld [label="Low Level Driver"]; + hw [label="Microcontroller Hardware"]; + hal_lld [label="HAL shared low level code"]; + + app->hld; + hld->lld; + lld-> hw; + lld->hal_lld; + hal_lld->hw; + } + * @enddot + */ + +/** + * @defgroup HAL_CONF Configuration + * @brief @ref HAL Configuration. + * @details The file @p halconf.h contains the high level settings for all + * the drivers supported by the HAL. The low level, platform dependent, + * settings are contained in the @p mcuconf.h file instead and are describe + * in the various platforms reference manuals. + * + * @ingroup IO + */ diff --git a/Project/os/hal/hal.mk b/Project/os/hal/hal.mk new file mode 100644 index 0000000..83cf1bd --- /dev/null +++ b/Project/os/hal/hal.mk @@ -0,0 +1,24 @@ +# List of all the ChibiOS/RT HAL files, there is no need to remove the files +# from this list, you can disable parts of the kernel by editing halconf.h. +HALSRC = ${CHIBIOS}/os/hal/src/hal.c \ + ${CHIBIOS}/os/hal/src/adc.c \ + ${CHIBIOS}/os/hal/src/can.c \ + ${CHIBIOS}/os/hal/src/ext.c \ + ${CHIBIOS}/os/hal/src/gpt.c \ + ${CHIBIOS}/os/hal/src/i2c.c \ + ${CHIBIOS}/os/hal/src/icu.c \ + ${CHIBIOS}/os/hal/src/mac.c \ + ${CHIBIOS}/os/hal/src/pal.c \ + ${CHIBIOS}/os/hal/src/pwm.c \ + ${CHIBIOS}/os/hal/src/sdc.c \ + ${CHIBIOS}/os/hal/src/serial.c \ + ${CHIBIOS}/os/hal/src/spi.c \ + ${CHIBIOS}/os/hal/src/uart.c \ + ${CHIBIOS}/os/hal/src/usb.c \ + ${CHIBIOS}/os/hal/src/tm.c \ + ${CHIBIOS}/os/hal/src/mmc_spi.c \ + ${CHIBIOS}/os/hal/src/serial_usb.c \ + ${CHIBIOS}/os/hal/src/rtc.c + +# Required include directories +HALINC = ${CHIBIOS}/os/hal/include diff --git a/Project/os/hal/include/adc.h b/Project/os/hal/include/adc.h new file mode 100644 index 0000000..8bd51c0 --- /dev/null +++ b/Project/os/hal/include/adc.h @@ -0,0 +1,321 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file adc.h + * @brief ADC Driver macros and structures. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_H_ +#define _ADC_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name ADC configuration options + * @{ + */ +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if ADC_USE_WAIT && !CH_USE_SEMAPHORES +#error "ADC driver requires CH_USE_SEMAPHORES when ADC_USE_WAIT is enabled" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + ADC_UNINIT = 0, /**< Not initialized. */ + ADC_STOP = 1, /**< Stopped. */ + ADC_READY = 2, /**< Ready. */ + ADC_ACTIVE = 3, /**< Converting. */ + ADC_COMPLETE = 4, /**< Conversion complete. */ + ADC_ERROR = 5 /**< Conversion complete. */ +} adcstate_t; + +#include "adc_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Low Level driver helper macros + * @{ + */ +#if ADC_USE_WAIT || defined(__DOXYGEN__) +/** + * @brief Resumes a thread waiting for a conversion completion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +#define _adc_reset_i(adcp) { \ + if ((adcp)->thread != NULL) { \ + Thread *tp = (adcp)->thread; \ + (adcp)->thread = NULL; \ + tp->p_u.rdymsg = RDY_RESET; \ + chSchReadyI(tp); \ + } \ +} + +/** + * @brief Resumes a thread waiting for a conversion completion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +#define _adc_reset_s(adcp) { \ + if ((adcp)->thread != NULL) { \ + Thread *tp = (adcp)->thread; \ + (adcp)->thread = NULL; \ + chSchWakeupS(tp, RDY_RESET); \ + } \ +} + +/** + * @brief Wakes up the waiting thread. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +#define _adc_wakeup_isr(adcp) { \ + chSysLockFromIsr(); \ + if ((adcp)->thread != NULL) { \ + Thread *tp; \ + tp = (adcp)->thread; \ + (adcp)->thread = NULL; \ + tp->p_u.rdymsg = RDY_OK; \ + chSchReadyI(tp); \ + } \ + chSysUnlockFromIsr(); \ +} + +/** + * @brief Wakes up the waiting thread with a timeout message. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +#define _adc_timeout_isr(adcp) { \ + chSysLockFromIsr(); \ + if ((adcp)->thread != NULL) { \ + Thread *tp; \ + tp = (adcp)->thread; \ + (adcp)->thread = NULL; \ + tp->p_u.rdymsg = RDY_TIMEOUT; \ + chSchReadyI(tp); \ + } \ + chSysUnlockFromIsr(); \ +} + +#else /* !ADC_USE_WAIT */ +#define _adc_reset_i(adcp) +#define _adc_reset_s(adcp) +#define _adc_wakeup_isr(adcp) +#define _adc_timeout_isr(adcp) +#endif /* !ADC_USE_WAIT */ + +/** + * @brief Common ISR code, half buffer event. + * @details This code handles the portable part of the ISR code: + * - Callback invocation. + * . + * @note This macro is meant to be used in the low level drivers + * implementation only. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +#define _adc_isr_half_code(adcp) { \ + if ((adcp)->grpp->end_cb != NULL) { \ + (adcp)->grpp->end_cb(adcp, (adcp)->samples, (adcp)->depth / 2); \ + } \ +} + +/** + * @brief Common ISR code, full buffer event. + * @details This code handles the portable part of the ISR code: + * - Callback invocation. + * - Waiting thread wakeup, if any. + * - Driver state transitions. + * . + * @note This macro is meant to be used in the low level drivers + * implementation only. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +#define _adc_isr_full_code(adcp) { \ + if ((adcp)->grpp->circular) { \ + /* Callback handling.*/ \ + if ((adcp)->grpp->end_cb != NULL) { \ + if ((adcp)->depth > 1) { \ + /* Invokes the callback passing the 2nd half of the buffer.*/ \ + size_t half = (adcp)->depth / 2; \ + size_t half_index = half * (adcp)->grpp->num_channels; \ + (adcp)->grpp->end_cb(adcp, (adcp)->samples + half_index, half); \ + } \ + else { \ + /* Invokes the callback passing the whole buffer.*/ \ + (adcp)->grpp->end_cb(adcp, (adcp)->samples, (adcp)->depth); \ + } \ + } \ + } \ + else { \ + /* End conversion.*/ \ + adc_lld_stop_conversion(adcp); \ + if ((adcp)->grpp->end_cb != NULL) { \ + (adcp)->state = ADC_COMPLETE; \ + if ((adcp)->depth > 1) { \ + /* Invokes the callback passing the 2nd half of the buffer.*/ \ + size_t half = (adcp)->depth / 2; \ + size_t half_index = half * (adcp)->grpp->num_channels; \ + (adcp)->grpp->end_cb(adcp, (adcp)->samples + half_index, half); \ + } \ + else { \ + /* Invokes the callback passing the whole buffer.*/ \ + (adcp)->grpp->end_cb(adcp, (adcp)->samples, (adcp)->depth); \ + } \ + if ((adcp)->state == ADC_COMPLETE) \ + (adcp)->state = ADC_READY; \ + } \ + else \ + (adcp)->state = ADC_READY; \ + (adcp)->grpp = NULL; \ + _adc_wakeup_isr(adcp); \ + } \ +} + +/** + * @brief Common ISR code, error event. + * @details This code handles the portable part of the ISR code: + * - Callback invocation. + * - Waiting thread timeout signaling, if any. + * - Driver state transitions. + * . + * @note This macro is meant to be used in the low level drivers + * implementation only. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] err platform dependent error code + * + * @notapi + */ +#define _adc_isr_error_code(adcp, err) { \ + adc_lld_stop_conversion(adcp); \ + if ((adcp)->grpp->error_cb != NULL) { \ + (adcp)->state = ADC_ERROR; \ + (adcp)->grpp->error_cb(adcp, err); \ + if ((adcp)->state == ADC_ERROR) \ + (adcp)->state = ADC_READY; \ + } \ + (adcp)->grpp = NULL; \ + _adc_timeout_isr(adcp); \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void adcInit(void); + void adcObjectInit(ADCDriver *adcp); + void adcStart(ADCDriver *adcp, const ADCConfig *config); + void adcStop(ADCDriver *adcp); + void adcStartConversion(ADCDriver *adcp, + const ADCConversionGroup *grpp, + adcsample_t *samples, + size_t depth); + void adcStartConversionI(ADCDriver *adcp, + const ADCConversionGroup *grpp, + adcsample_t *samples, + size_t depth); + void adcStopConversion(ADCDriver *adcp); + void adcStopConversionI(ADCDriver *adcp); +#if ADC_USE_WAIT + msg_t adcConvert(ADCDriver *adcp, + const ADCConversionGroup *grpp, + adcsample_t *samples, + size_t depth); +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) + void adcAcquireBus(ADCDriver *adcp); + void adcReleaseBus(ADCDriver *adcp); +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_H_ */ + +/** @} */ diff --git a/Project/os/hal/include/can.h b/Project/os/hal/include/can.h new file mode 100644 index 0000000..b9756e4 --- /dev/null +++ b/Project/os/hal/include/can.h @@ -0,0 +1,160 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file can.h + * @brief CAN Driver macros and structures. + * + * @addtogroup CAN + * @{ + */ + +#ifndef _CAN_H_ +#define _CAN_H_ + +#if HAL_USE_CAN || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name CAN status flags + * @{ + */ +/** + * @brief Errors rate warning. + */ +#define CAN_LIMIT_WARNING 1 +/** + * @brief Errors rate error. + */ +#define CAN_LIMIT_ERROR 2 +/** + * @brief Bus off condition reached. + */ +#define CAN_BUS_OFF_ERROR 4 +/** + * @brief Framing error of some kind on the CAN bus. + */ +#define CAN_FRAMING_ERROR 8 +/** + * @brief Overflow in receive queue. + */ +#define CAN_OVERFLOW_ERROR 16 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name CAN configuration options + * @{ + */ +/** + * @brief Sleep mode related APIs inclusion switch. + * @details This option can only be enabled if the CAN implementation supports + * the sleep mode, see the macro @p CAN_SUPPORTS_SLEEP exported by + * the underlying implementation. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !CH_USE_SEMAPHORES || !CH_USE_EVENTS +#error "CAN driver requires CH_USE_SEMAPHORES and CH_USE_EVENTS" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + CAN_UNINIT = 0, /**< Not initialized. */ + CAN_STOP = 1, /**< Stopped. */ + CAN_STARTING = 2, /**< Starting. */ + CAN_READY = 3, /**< Ready. */ + CAN_SLEEP = 4 /**< Sleep state. */ +} canstate_t; + +#include "can_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Adds some flags to the CAN status mask. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] mask flags to be added to the status mask + * + * @iclass + */ +#define canAddFlagsI(canp, mask) ((canp)->status |= (mask)) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void canInit(void); + void canObjectInit(CANDriver *canp); + void canStart(CANDriver *canp, const CANConfig *config); + void canStop(CANDriver *canp); + msg_t canTransmit(CANDriver *canp, const CANTxFrame *ctfp, systime_t timeout); + msg_t canReceive(CANDriver *canp, CANRxFrame *crfp, systime_t timeout); + canstatus_t canGetAndClearFlags(CANDriver *canp); +#if CAN_USE_SLEEP_MODE + void canSleep(CANDriver *canp); + void canWakeup(CANDriver *canp); +#endif /* CAN_USE_SLEEP_MODE */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_CAN */ + +#endif /* _CAN_H_ */ + +/** @} */ diff --git a/Project/os/hal/include/ext.h b/Project/os/hal/include/ext.h new file mode 100644 index 0000000..49c6ddf --- /dev/null +++ b/Project/os/hal/include/ext.h @@ -0,0 +1,137 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file ext.h + * @brief EXT Driver macros and structures. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_H_ +#define _EXT_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name EXT channels modes + * @{ + */ +#define EXT_CH_MODE_EDGES_MASK 3 /**< @brief Mask of edges field. */ +#define EXT_CH_MODE_DISABLED 0 /**< @brief Channel disabled. */ +#define EXT_CH_MODE_RISING_EDGE 1 /**< @brief Rising edge callback. */ +#define EXT_CH_MODE_FALLING_EDGE 2 /**< @brief Falling edge callback. */ +#define EXT_CH_MODE_BOTH_EDGES 3 /**< @brief Both edges callback. */ + +#define EXT_CH_MODE_AUTOSTART 4 /**< @brief Channel started + automatically on driver start. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + EXT_UNINIT = 0, /**< Not initialized. */ + EXT_STOP = 1, /**< Stopped. */ + EXT_ACTIVE = 2, /**< Active. */ +} extstate_t; + +/** + * @brief Type of a structure representing a EXT driver. + */ +typedef struct EXTDriver EXTDriver; + +#include "ext_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @iclass + */ +#define extChannelEnableI(extp, channel) ext_lld_channel_enable(extp, channel) + +/** + * @brief Disables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be disabled + * + * @iclass + */ +#define extChannelDisableI(extp, channel) ext_lld_channel_disable(extp, channel) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void extInit(void); + void extObjectInit(EXTDriver *extp); + void extStart(EXTDriver *extp, const EXTConfig *config); + void extStop(EXTDriver *extp); + void extChannelEnable(EXTDriver *extp, expchannel_t channel); + void extChannelDisable(EXTDriver *extp, expchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_H_ */ + +/** @} */ diff --git a/Project/os/hal/include/gpt.h b/Project/os/hal/include/gpt.h new file mode 100644 index 0000000..3e6c918 --- /dev/null +++ b/Project/os/hal/include/gpt.h @@ -0,0 +1,112 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file gpt.h + * @brief GPT Driver macros and structures. + * + * @addtogroup GPT + * @{ + */ + +#ifndef _GPT_H_ +#define _GPT_H_ + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + GPT_UNINIT = 0, /**< Not initialized. */ + GPT_STOP = 1, /**< Stopped. */ + GPT_READY = 2, /**< Ready. */ + GPT_CONTINUOUS = 3, /**< Active in continuous mode. */ + GPT_ONESHOT = 4 /**< Active in one shot mode. */ +} gptstate_t; + +/** + * @brief Type of a structure representing a GPT driver. + */ +typedef struct GPTDriver GPTDriver; + +/** + * @brief GPT notification callback type. + * + * @param[in] gptp pointer to a @p GPTDriver object + */ +typedef void (*gptcallback_t)(GPTDriver *gptp); + +#include "gpt_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void gptInit(void); + void gptObjectInit(GPTDriver *gptp); + void gptStart(GPTDriver *gptp, const GPTConfig *config); + void gptStop(GPTDriver *gptp); + void gptStartContinuous(GPTDriver *gptp, gptcnt_t interval); + void gptStartContinuousI(GPTDriver *gptp, gptcnt_t interval); + void gptStartOneShot(GPTDriver *gptp, gptcnt_t interval); + void gptStartOneShotI(GPTDriver *gptp, gptcnt_t interval); + void gptStopTimer(GPTDriver *gptp); + void gptStopTimerI(GPTDriver *gptp); + void gptPolledDelay(GPTDriver *gptp, gptcnt_t interval); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT */ + +#endif /* _GPT_H_ */ + +/** @} */ diff --git a/Project/os/hal/include/hal.h b/Project/os/hal/include/hal.h new file mode 100644 index 0000000..734dca5 --- /dev/null +++ b/Project/os/hal/include/hal.h @@ -0,0 +1,175 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file hal.h + * @brief HAL subsystem header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_H_ +#define _HAL_H_ + +#include "board.h" +#include "halconf.h" + +#include "hal_lld.h" + +#include "tm.h" +#include "pal.h" +#include "adc.h" +#include "can.h" +#include "ext.h" +#include "gpt.h" +#include "i2c.h" +#include "icu.h" +#include "mac.h" +#include "pwm.h" +#include "rtc.h" +#include "serial.h" +#include "sdc.h" +#include "spi.h" +#include "uart.h" +#include "usb.h" +#include "mmc_spi.h" +#include "serial_usb.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +#if HAL_IMPLEMENTS_COUNTERS || defined(__DOXYGEN__) +/** + * @name Time conversion utilities for the realtime counter + * @{ + */ +/** + * @brief Seconds to realtime ticks. + * @details Converts from seconds to realtime ticks number. + * @note The result is rounded upward to the next tick boundary. + * + * @param[in] sec number of seconds + * @return The number of ticks. + * + * @api + */ +#define S2RTT(sec) (halGetCounterFrequency() * (sec)) + +/** + * @brief Milliseconds to realtime ticks. + * @details Converts from milliseconds to realtime ticks number. + * @note The result is rounded upward to the next tick boundary. + * + * @param[in] msec number of milliseconds + * @return The number of ticks. + * + * @api + */ +#define MS2RTT(msec) (((halGetCounterFrequency() + 999UL) / 1000UL) * (msec)) + +/** + * @brief Microseconds to realtime ticks. + * @details Converts from microseconds to realtime ticks number. + * @note The result is rounded upward to the next tick boundary. + * + * @param[in] usec number of microseconds + * @return The number of ticks. + * + * @api + */ +#define US2RTT(usec) (((halGetCounterFrequency() + 999999UL) / 1000000UL) * \ + (usec)) +/** @} */ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns the current value of the system free running counter. + * @note This is an optional service that could not be implemented in + * all HAL implementations. + * @note This function can be called from any context. + * + * @return The value of the system free running counter of + * type halrtcnt_t. + * + * @special + */ +#define halGetCounterValue() hal_lld_get_counter_value() + +/** + * @brief Realtime counter frequency. + * @note This is an optional service that could not be implemented in + * all HAL implementations. + * @note This function can be called from any context. + * + * @return The realtime counter frequency of type halclock_t. + * + * @special + */ +#define halGetCounterFrequency() hal_lld_get_counter_frequency() +/** @} */ +#endif /* HAL_IMPLEMENTS_COUNTERS */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void halInit(void); +#if HAL_IMPLEMENTS_COUNTERS + bool_t halIsCounterWithin(halrtcnt_t start, halrtcnt_t end); + void halPolledDelay(halrtcnt_t ticks); +#endif /* HAL_IMPLEMENTS_COUNTERS */ +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_H_ */ + +/** @} */ diff --git a/Project/os/hal/include/i2c.h b/Project/os/hal/include/i2c.h new file mode 100644 index 0000000..00b412e --- /dev/null +++ b/Project/os/hal/include/i2c.h @@ -0,0 +1,155 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file i2c.h + * @brief I2C Driver macros and structures. + * + * @addtogroup I2C + * @{ + */ + +#ifndef _I2C_H_ +#define _I2C_H_ + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name I2C bus error conditions + * @{ + */ +#define I2CD_NO_ERROR 0x00 /**< @brief No error. */ +#define I2CD_BUS_ERROR 0x01 /**< @brief Bus Error. */ +#define I2CD_ARBITRATION_LOST 0x02 /**< @brief Arbitration Lost + (master mode). */ +#define I2CD_ACK_FAILURE 0x04 /**< @brief Acknowledge Failure. */ +#define I2CD_OVERRUN 0x08 /**< @brief Overrun/Underrun. */ +#define I2CD_PEC_ERROR 0x10 /**< @brief PEC Error in + reception. */ +#define I2CD_TIMEOUT 0x20 /**< @brief Hardware timeout. */ +#define I2CD_SMB_ALERT 0x40 /**< @brief SMBus Alert. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if I2C_USE_MUTUAL_EXCLUSION && !CH_USE_MUTEXES && !CH_USE_SEMAPHORES +#error "I2C_USE_MUTUAL_EXCLUSION requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + I2C_UNINIT = 0, /**< Not initialized. */ + I2C_STOP = 1, /**< Stopped. */ + I2C_READY = 2, /**< Ready. */ + I2C_ACTIVE_TX = 3, /**< Transmitting. */ + I2C_ACTIVE_RX = 4, /**< Receiving. */ + I2C_LOCKED = 5 /**> Bus or driver locked. */ +} i2cstate_t; + +#include "i2c_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Wrap i2cMasterTransmitTimeout function with TIME_INFINITE timeout. + * @api + */ +#define i2cMasterTransmit(i2cp, addr, txbuf, txbytes, rxbuf, rxbytes) \ + (i2cMasterTransmitTimeout(i2cp, addr, txbuf, txbytes, rxbuf, rxbytes, \ + TIME_INFINITE)) + +/** + * @brief Wrap i2cMasterReceiveTimeout function with TIME_INFINITE timeout. + * @api + */ +#define i2cMasterReceive(i2cp, addr, rxbuf, rxbytes) \ + (i2cMasterReceiveTimeout(i2cp, addr, rxbuf, rxbytes, TIME_INFINITE)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void i2cInit(void); + void i2cObjectInit(I2CDriver *i2cp); + void i2cStart(I2CDriver *i2cp, const I2CConfig *config); + void i2cStop(I2CDriver *i2cp); + i2cflags_t i2cGetErrors(I2CDriver *i2cp); + msg_t i2cMasterTransmitTimeout(I2CDriver *i2cp, + i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); + msg_t i2cMasterReceiveTimeout(I2CDriver *i2cp, + i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); +#if I2C_USE_MUTUAL_EXCLUSION + void i2cAcquireBus(I2CDriver *i2cp); + void i2cReleaseBus(I2CDriver *i2cp); +#endif /* I2C_USE_MUTUAL_EXCLUSION */ + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_I2C */ + +#endif /* _I2C_H_ */ + +/** @} */ diff --git a/Project/os/hal/include/icu.h b/Project/os/hal/include/icu.h new file mode 100644 index 0000000..4818c15 --- /dev/null +++ b/Project/os/hal/include/icu.h @@ -0,0 +1,186 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file icu.h + * @brief ICU Driver macros and structures. + * + * @addtogroup ICU + * @{ + */ + +#ifndef _ICU_H_ +#define _ICU_H_ + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + ICU_UNINIT = 0, /**< Not initialized. */ + ICU_STOP = 1, /**< Stopped. */ + ICU_READY = 2, /**< Ready. */ + ICU_WAITING = 3, /**< Waiting first edge. */ + ICU_ACTIVE = 4, /**< Active cycle phase. */ + ICU_IDLE = 5, /**< Idle cycle phase. */ +} icustate_t; + +/** + * @brief Type of a structure representing an ICU driver. + */ +typedef struct ICUDriver ICUDriver; + +/** + * @brief ICU notification callback type. + * + * @param[in] icup pointer to a @p ICUDriver object + */ +typedef void (*icucallback_t)(ICUDriver *icup); + +#include "icu_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Enables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @iclass + */ +#define icuEnableI(icup) icu_lld_enable(icup) + +/** + * @brief Disables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @iclass + */ +#define icuDisableI(icup) icu_lld_disable(icup) + +/** + * @brief Returns the width of the latest pulse. + * @details The pulse width is defined as number of ticks between the start + * edge and the stop edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @iclass + */ +#define icuGetWidthI(icup) icu_lld_get_width(icup) + +/** + * @brief Returns the width of the latest cycle. + * @details The cycle width is defined as number of ticks between a start + * edge and the next start edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @iclass + */ +#define icuGetPeriodI(icup) icu_lld_get_period(icup) +/** @} */ + +/** + * @name Low Level driver helper macros + * @{ + */ +/** + * @brief Common ISR code, ICU width event. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +#define _icu_isr_invoke_width_cb(icup) { \ + (icup)->state = ICU_IDLE; \ + (icup)->config->width_cb(icup); \ +} + +/** + * @brief Common ISR code, ICU period event. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +#define _icu_isr_invoke_period_cb(icup) { \ + icustate_t previous_state = (icup)->state; \ + (icup)->state = ICU_ACTIVE; \ + if (previous_state != ICU_WAITING) \ + (icup)->config->period_cb(icup); \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void icuInit(void); + void icuObjectInit(ICUDriver *icup); + void icuStart(ICUDriver *icup, const ICUConfig *config); + void icuStop(ICUDriver *icup); + void icuEnable(ICUDriver *icup); + void icuDisable(ICUDriver *icup); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ICU */ + +#endif /* _ICU_H_ */ + +/** @} */ diff --git a/Project/os/hal/include/mac.h b/Project/os/hal/include/mac.h new file mode 100644 index 0000000..c5fd846 --- /dev/null +++ b/Project/os/hal/include/mac.h @@ -0,0 +1,173 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file mac.h + * @brief MAC Driver macros and structures. + * @addtogroup MAC + * @{ + */ + +#ifndef _MAC_H_ +#define _MAC_H_ + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name MAC configuration options + * @{ + */ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !CH_USE_SEMAPHORES || !CH_USE_EVENTS +#error "the MAC driver requires CH_USE_SEMAPHORES" +#endif + +#if MAC_USE_EVENTS && !CH_USE_EVENTS +#error "the MAC driver requires CH_USE_EVENTS" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + MAC_UNINIT = 0, /**< Not initialized. */ + MAC_STOP = 1, /**< Stopped. */ + MAC_ACTIVE = 2, /**< Active. */ +} macstate_t; + +/** + * @brief Type of a structure representing a MAC driver. + */ +typedef struct MACDriver MACDriver; + +#include "mac_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns the received frames event source. + * + * @param[in] macp pointer to the @p MACDriver object + * @return The pointer to the @p EventSource structure. + * + * @api + */ +#if MAC_USE_EVENTS || defined(__DOXYGEN__) +#define macGetReceiveEventSource(macp) (&(macp)->rdevent) +#endif + +/** + * @brief Writes to a transmit descriptor's stream. + * + * @param[in] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] buf pointer to the buffer containing the data to be written + * @param[in] size number of bytes to be written + * @return The number of bytes written into the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if the maximum frame + * size is reached. + * + * @api + */ +#define macWriteTransmitDescriptor(tdp, buf, size) \ + mac_lld_write_transmit_descriptor(tdp, buf, size) + +/** + * @brief Reads from a receive descriptor's stream. + * + * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[in] buf pointer to the buffer that will receive the read data + * @param[in] size number of bytes to be read + * @return The number of bytes read from the descriptor's stream, this + * value can be less than the amount specified in the + * parameter @p size if there are no more bytes to read. + * + * @api + */ +#define macReadReceiveDescriptor(rdp, buf, size) \ + mac_lld_read_receive_descriptor(rdp, buf, size) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void macInit(void); + void macObjectInit(MACDriver *macp); + void macStart(MACDriver *macp, const MACConfig *config); + void macStop(MACDriver *macp); + void macSetAddress(MACDriver *macp, const uint8_t *p); + msg_t macWaitTransmitDescriptor(MACDriver *macp, + MACTransmitDescriptor *tdp, + systime_t time); + void macReleaseTransmitDescriptor(MACTransmitDescriptor *tdp); + msg_t macWaitReceiveDescriptor(MACDriver *macp, + MACReceiveDescriptor *rdp, + systime_t time); + void macReleaseReceiveDescriptor(MACReceiveDescriptor *rdp); + bool_t macPollLinkStatus(MACDriver *macp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_MAC */ + +#endif /* _MAC_H_ */ + +/** @} */ diff --git a/Project/os/hal/include/mii.h b/Project/os/hal/include/mii.h new file mode 100644 index 0000000..f98bd9d --- /dev/null +++ b/Project/os/hal/include/mii.h @@ -0,0 +1,192 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/*-* + * @file mii.h + * @brief MII Driver macros and structures. + * + * @addtogroup MII + * @{ + */ + +#ifndef _MII_H_ +#define _MII_H_ + +/* + * Generic MII registers. Note, not all registers are present on all PHY + * devices and some extra registers may be present. + */ +#define MII_BMCR 0x00 /**< Basic mode control register. */ +#define MII_BMSR 0x01 /**< Basic mode status register. */ +#define MII_PHYSID1 0x02 /**< PHYS ID 1. */ +#define MII_PHYSID2 0x03 /**< PHYS ID 2. */ +#define MII_ADVERTISE 0x04 /**< Advertisement control reg. */ +#define MII_LPA 0x05 /**< Link partner ability reg. */ +#define MII_EXPANSION 0x06 /**< Expansion register. */ +#define MII_CTRL1000 0x09 /**< 1000BASE-T control. */ +#define MII_STAT1000 0x0a /**< 1000BASE-T status. */ +#define MII_ESTATUS 0x0f /**< Extended Status. */ +#define MII_DCOUNTER 0x12 /**< Disconnect counter. */ +#define MII_FCSCOUNTER 0x13 /**< False carrier counter. */ +#define MII_NWAYTEST 0x14 /**< N-way auto-neg test reg. */ +#define MII_RERRCOUNTER 0x15 /**< Receive error counter. */ +#define MII_SREVISION 0x16 /**< Silicon revision. */ +#define MII_RESV1 0x17 /**< Reserved. */ +#define MII_LBRERROR 0x18 /**< Lpback, rx, bypass error. */ +#define MII_PHYADDR 0x19 /**< PHY address. */ +#define MII_RESV2 0x1a /**< Reserved. */ +#define MII_TPISTATUS 0x1b /**< TPI status for 10mbps. */ +#define MII_NCONFIG 0x1c /**< Network interface config. */ + +/* + * Basic mode control register. + */ +#define BMCR_RESV 0x003f /**< Unused. */ +#define BMCR_SPEED1000 0x0040 /**< MSB of Speed (1000). */ +#define BMCR_CTST 0x0080 /**< Collision test. */ +#define BMCR_FULLDPLX 0x0100 /**< Full duplex. */ +#define BMCR_ANRESTART 0x0200 /**< Auto negotiation restart. */ +#define BMCR_ISOLATE 0x0400 /**< Disconnect DP83840 from MII. */ +#define BMCR_PDOWN 0x0800 /**< Powerdown. */ +#define BMCR_ANENABLE 0x1000 /**< Enable auto negotiation. */ +#define BMCR_SPEED100 0x2000 /**< Select 100Mbps. */ +#define BMCR_LOOPBACK 0x4000 /**< TXD loopback bits. */ +#define BMCR_RESET 0x8000 /**< Reset. */ + +/* + * Basic mode status register. + */ +#define BMSR_ERCAP 0x0001 /**< Ext-reg capability. */ +#define BMSR_JCD 0x0002 /**< Jabber detected. */ +#define BMSR_LSTATUS 0x0004 /**< Link status. */ +#define BMSR_ANEGCAPABLE 0x0008 /**< Able to do auto-negotiation. */ +#define BMSR_RFAULT 0x0010 /**< Remote fault detected. */ +#define BMSR_ANEGCOMPLETE 0x0020 /**< Auto-negotiation complete. */ +#define BMSR_RESV 0x00c0 /**< Unused. */ +#define BMSR_ESTATEN 0x0100 /**< Extended Status in R15. */ +#define BMSR_100HALF2 0x0200 /**< Can do 100BASE-T2 HDX. */ +#define BMSR_100FULL2 0x0400 /**< Can do 100BASE-T2 FDX. */ +#define BMSR_10HALF 0x0800 /**< Can do 10mbps, half-duplex. */ +#define BMSR_10FULL 0x1000 /**< Can do 10mbps, full-duplex. */ +#define BMSR_100HALF 0x2000 /**< Can do 100mbps, half-duplex. */ +#define BMSR_100FULL 0x4000 /**< Can do 100mbps, full-duplex. */ +#define BMSR_100BASE4 0x8000 /**< Can do 100mbps, 4k packets. */ + +/* + * Advertisement control register. + */ +#define ADVERTISE_SLCT 0x001f /**< Selector bits. */ +#define ADVERTISE_CSMA 0x0001 /**< Only selector supported. */ +#define ADVERTISE_10HALF 0x0020 /**< Try for 10mbps half-duplex. */ +#define ADVERTISE_1000XFULL 0x0020 /**< Try for 1000BASE-X full-duplex.*/ +#define ADVERTISE_10FULL 0x0040 /**< Try for 10mbps full-duplex. */ +#define ADVERTISE_1000XHALF 0x0040 /**< Try for 1000BASE-X half-duplex.*/ +#define ADVERTISE_100HALF 0x0080 /**< Try for 100mbps half-duplex. */ +#define ADVERTISE_1000XPAUSE 0x0080 /**< Try for 1000BASE-X pause. */ +#define ADVERTISE_100FULL 0x0100 /**< Try for 100mbps full-duplex. */ +#define ADVERTISE_1000XPSE_ASYM 0x0100 /**< Try for 1000BASE-X asym pause. */ +#define ADVERTISE_100BASE4 0x0200 /**< Try for 100mbps 4k packets. */ +#define ADVERTISE_PAUSE_CAP 0x0400 /**< Try for pause. */ +#define ADVERTISE_PAUSE_ASYM 0x0800 /**< Try for asymetric pause. */ +#define ADVERTISE_RESV 0x1000 /**< Unused. */ +#define ADVERTISE_RFAULT 0x2000 /**< Say we can detect faults. */ +#define ADVERTISE_LPACK 0x4000 /**< Ack link partners response. */ +#define ADVERTISE_NPAGE 0x8000 /**< Next page bit. */ + +#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ + ADVERTISE_CSMA) +#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ + ADVERTISE_100HALF | ADVERTISE_100FULL) + +/* + * Link partner ability register. + */ +#define LPA_SLCT 0x001f /**< Same as advertise selector. */ +#define LPA_10HALF 0x0020 /**< Can do 10mbps half-duplex. */ +#define LPA_1000XFULL 0x0020 /**< Can do 1000BASE-X full-duplex. */ +#define LPA_10FULL 0x0040 /**< Can do 10mbps full-duplex. */ +#define LPA_1000XHALF 0x0040 /**< Can do 1000BASE-X half-duplex. */ +#define LPA_100HALF 0x0080 /**< Can do 100mbps half-duplex. */ +#define LPA_1000XPAUSE 0x0080 /**< Can do 1000BASE-X pause. */ +#define LPA_100FULL 0x0100 /**< Can do 100mbps full-duplex. */ +#define LPA_1000XPAUSE_ASYM 0x0100 /**< Can do 1000BASE-X pause asym. */ +#define LPA_100BASE4 0x0200 /**< Can do 100mbps 4k packets. */ +#define LPA_PAUSE_CAP 0x0400 /**< Can pause. */ +#define LPA_PAUSE_ASYM 0x0800 /**< Can pause asymetrically. */ +#define LPA_RESV 0x1000 /**< Unused. */ +#define LPA_RFAULT 0x2000 /**< Link partner faulted. */ +#define LPA_LPACK 0x4000 /**< Link partner acked us. */ +#define LPA_NPAGE 0x8000 /**< Next page bit. */ + +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) + +/* + * Expansion register for auto-negotiation. + */ +#define EXPANSION_NWAY 0x0001 /**< Can do N-way auto-nego. */ +#define EXPANSION_LCWP 0x0002 /**< Got new RX page code word. */ +#define EXPANSION_ENABLENPAGE 0x0004 /**< This enables npage words. */ +#define EXPANSION_NPCAPABLE 0x0008 /**< Link partner supports npage. */ +#define EXPANSION_MFAULTS 0x0010 /**< Multiple faults detected. */ +#define EXPANSION_RESV 0xffe0 /**< Unused. */ + +#define ESTATUS_1000_TFULL 0x2000 /**< Can do 1000BT Full. */ +#define ESTATUS_1000_THALF 0x1000 /**< Can do 1000BT Half. */ + +/* + * N-way test register. + */ +#define NWAYTEST_RESV1 0x00ff /**< Unused. */ +#define NWAYTEST_LOOPBACK 0x0100 /**< Enable loopback for N-way. */ +#define NWAYTEST_RESV2 0xfe00 /**< Unused. */ + +/* + * 1000BASE-T Control register. + */ +#define ADVERTISE_1000FULL 0x0200 /**< Advertise 1000BASE-T full duplex.*/ +#define ADVERTISE_1000HALF 0x0100 /**< Advertise 1000BASE-T half duplex.*/ + +/* + * 1000BASE-T Status register. + */ +#define LPA_1000LOCALRXOK 0x2000 /**< Link partner local receiver status.*/ +#define LPA_1000REMRXOK 0x1000 /**< Link partner remote receiver status.*/ +#define LPA_1000FULL 0x0800 /**< Link partner 1000BASE-T full duplex.*/ +#define LPA_1000HALF 0x0400 /**< Link partner 1000BASE-T half duplex.*/ + +/* + * PHY identifiers. + */ +#define MII_DM9161_ID 0x0181b8a0 +#define MII_AM79C875_ID 0x00225540 +#define MII_KS8721_ID 0x00221610 +#define MII_STE101P_ID 0x00061C50 + +#endif /* _MII_H_ */ + +/** @} */ diff --git a/Project/os/hal/include/mmc_spi.h b/Project/os/hal/include/mmc_spi.h new file mode 100644 index 0000000..5dc4b6c --- /dev/null +++ b/Project/os/hal/include/mmc_spi.h @@ -0,0 +1,261 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file mmc_spi.h + * @brief MMC over SPI driver header. + * + * @addtogroup MMC_SPI + * @{ + */ + +#ifndef _MMC_SPI_H_ +#define _MMC_SPI_H_ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define MMC_CMD0_RETRY 10 +#define MMC_CMD1_RETRY 100 +#define MMC_ACMD41_RETRY 100 +#define MMC_WAIT_DATA 10000 + +#define MMC_CMDGOIDLE 0 +#define MMC_CMDINIT 1 +#define MMC_CMDINTERFACE_CONDITION 8 +#define MMC_CMDREADCSD 9 +#define MMC_CMDSTOP 12 +#define MMC_CMDSETBLOCKLEN 16 +#define MMC_CMDREAD 17 +#define MMC_CMDREADMULTIPLE 18 +#define MMC_CMDWRITE 24 +#define MMC_CMDWRITEMULTIPLE 25 +#define MMC_CMDAPP 55 +#define MMC_CMDREADOCR 58 +#define MMC_ACMDOPCONDITION 41 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name MMC_SPI configuration options + * @{ + */ +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !HAL_USE_SPI || !CH_USE_EVENTS +#error "MMC_SPI driver requires HAL_USE_SPI and CH_USE_EVENTS" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + MMC_UNINIT = 0, /**< Not initialized. */ + MMC_STOP = 1, /**< Stopped. */ + MMC_WAIT = 2, /**< Waiting card. */ + MMC_INSERTED = 3, /**< Card inserted. */ + MMC_READY = 4, /**< Card ready. */ + MMC_READING = 5, /**< Reading. */ + MMC_WRITING = 6 /**< Writing. */ +} mmcstate_t; + +/** + * @brief Function used to query some hardware status bits. + * + * @return The status. + */ +typedef bool_t (*mmcquery_t)(void); + +/** + * @brief Driver configuration structure. + * @note Not required in the current implementation. + */ +typedef struct { + uint8_t dummy; +} MMCConfig; + +/** + * @brief Structure representing a MMC driver. + */ +typedef struct { + /** + * @brief Driver state. + */ + mmcstate_t state; + /** + * @brief Current configuration data. + */ + const MMCConfig *config; + /** + * @brief SPI driver associated to this MMC driver. + */ + SPIDriver *spip; + /** + * @brief SPI low speed configuration used during initialization. + */ + const SPIConfig *lscfg; + /** + * @brief SPI high speed configuration used during transfers. + */ + const SPIConfig *hscfg; + /** + * @brief Write protect status query function. + */ + mmcquery_t is_protected; + /** + * @brief Insertion status query function. + */ + mmcquery_t is_inserted; + /** + * @brief Card insertion event source. + */ + EventSource inserted_event; + /** + * @brief Card removal event source. + */ + EventSource removed_event; + /** + * @brief MMC insertion polling timer. + */ + VirtualTimer vt; + /** + * @brief Insertion counter. + */ + uint_fast8_t cnt; + /*** + * @brief Addresses use blocks instead of bytes. + */ + bool_t block_addresses; +} MMCDriver; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns the driver state. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @return The driver state. + * + * @api + */ +#define mmcGetDriverState(mmcp) ((mmcp)->state) + +/** + * @brief Returns the write protect status. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @return The card state. + * @retval FALSE card not inserted. + * @retval TRUE card inserted. + * + * @api + */ +#define mmcIsWriteProtected(mmcp) ((mmcp)->is_protected()) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void mmcInit(void); + void mmcObjectInit(MMCDriver *mmcp, SPIDriver *spip, + const SPIConfig *lscfg, const SPIConfig *hscfg, + mmcquery_t is_protected, mmcquery_t is_inserted); + void mmcStart(MMCDriver *mmcp, const MMCConfig *config); + void mmcStop(MMCDriver *mmcp); + bool_t mmcConnect(MMCDriver *mmcp); + bool_t mmcDisconnect(MMCDriver *mmcp); + bool_t mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk); + bool_t mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer); + bool_t mmcStopSequentialRead(MMCDriver *mmcp); + bool_t mmcStartSequentialWrite(MMCDriver *mmcp, uint32_t startblk); + bool_t mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer); + bool_t mmcStopSequentialWrite(MMCDriver *mmcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_MMC_SPI */ + +#endif /* _MMC_SPI_H_ */ + +/** @} */ diff --git a/Project/os/hal/include/pal.h b/Project/os/hal/include/pal.h new file mode 100644 index 0000000..7ffa5fc --- /dev/null +++ b/Project/os/hal/include/pal.h @@ -0,0 +1,544 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file pal.h + * @brief I/O Ports Abstraction Layer macros, types and structures. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_H_ +#define _PAL_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Pads mode constants + * @{ + */ +/** + * @brief After reset state. + * @details The state itself is not specified and is architecture dependent, + * it is guaranteed to be equal to the after-reset state. It is + * usually an input state. + */ +#define PAL_MODE_RESET 0 + +/** + * @brief Safe state for unconnected pads. + * @details The state itself is not specified and is architecture dependent, + * it may be mapped on @p PAL_MODE_INPUT_PULLUP, + * @p PAL_MODE_INPUT_PULLDOWN or @p PAL_MODE_OUTPUT_PUSHPULL as + * example. + */ +#define PAL_MODE_UNCONNECTED 1 + +/** + * @brief Regular input high-Z pad. + */ +#define PAL_MODE_INPUT 2 + +/** + * @brief Input pad with weak pull up resistor. + */ +#define PAL_MODE_INPUT_PULLUP 3 + +/** + * @brief Input pad with weak pull down resistor. + */ +#define PAL_MODE_INPUT_PULLDOWN 4 + +/** + * @brief Analog input mode. + */ +#define PAL_MODE_INPUT_ANALOG 5 + +/** + * @brief Push-pull output pad. + */ +#define PAL_MODE_OUTPUT_PUSHPULL 6 + +/** + * @brief Open-drain output pad. + */ +#define PAL_MODE_OUTPUT_OPENDRAIN 7 +/** @} */ + +/** + * @name Logic level constants + * @{ + */ +/** + * @brief Logical low state. + */ +#define PAL_LOW 0 + +/** + * @brief Logical high state. + */ +#define PAL_HIGH 1 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +#include "pal_lld.h" + +/** + * @brief I/O bus descriptor. + * @details This structure describes a group of contiguous digital I/O lines + * that have to be handled as bus. + * @note I/O operations on a bus do not affect I/O lines on the same port but + * not belonging to the bus. + */ +typedef struct { + /** + * @brief Port identifier. + */ + ioportid_t portid; + /** + * @brief Bus mask aligned to port bit 0. + * @note The bus mask implicitly define the bus width. A logical AND is + * performed on the bus data. + */ + ioportmask_t mask; + /** + * @brief Offset, within the port, of the least significant bit of the bus. + */ + uint_fast8_t offset; +} IOBus; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Port bit helper macro. + * @details This macro calculates the mask of a bit within a port. + * + * @param[in] n bit position within the port + * @return The bit mask. + */ +#define PAL_PORT_BIT(n) ((ioportmask_t)(1 << (n))) + +/** + * @brief Bits group mask helper. + * @details This macro calculates the mask of a bits group. + * + * @param[in] width group width + * @return The group mask. + */ +#define PAL_GROUP_MASK(width) ((ioportmask_t)(1 << (width)) - 1) + +/** + * @brief Data part of a static I/O bus initializer. + * @details This macro should be used when statically initializing an I/O bus + * that is part of a bigger structure. + * + * @param[in] name name of the IOBus variable + * @param[in] port I/O port descriptor + * @param[in] width bus width in bits + * @param[in] offset bus bit offset within the port + */ +#define _IOBUS_DATA(name, port, width, offset) \ + {port, PAL_GROUP_MASK(width), offset} + +/** + * @brief Static I/O bus initializer. + * + * @param[in] name name of the IOBus variable + * @param[in] port I/O port descriptor + * @param[in] width bus width in bits + * @param[in] offset bus bit offset within the port + */ +#define IOBUS_DECL(name, port, width, offset) \ + IOBus name = _IOBUS_DATA(name, port, width, offset) + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief PAL subsystem initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @param[in] config pointer to an architecture specific configuration + * structure. This structure is defined in the low level driver + * header. + * + * @init + */ +#define palInit(config) pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * @note The default implementation always return zero and computes the + * parameter eventual side effects. + * + * @param[in] port port identifier + * @return The port logical states. + * + * @api + */ +#if !defined(pal_lld_readport) || defined(__DOXYGEN__) +#define palReadPort(port) ((void)(port), 0) +#else +#define palReadPort(port) pal_lld_readport(port) +#endif + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * @note The default implementation always return zero and computes the + * parameter eventual side effects. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @api + */ +#if !defined(pal_lld_readlatch) || defined(__DOXYGEN__) +#define palReadLatch(port) ((void)(port), 0) +#else +#define palReadLatch(port) pal_lld_readlatch(port) +#endif + +/** + * @brief Writes a bits mask on a I/O port. + * @note The default implementation does nothing except computing the + * parameters eventual side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @api + */ +#if !defined(pal_lld_writeport) || defined(__DOXYGEN__) +#define palWritePort(port, bits) ((void)(port), (void)(bits)) +#else +#define palWritePort(port, bits) pal_lld_writeport(port, bits) +#endif + +/** + * @brief Sets a bits mask on a I/O port. + * @note The operation is not guaranteed to be atomic on all the + * architectures, for atomicity and/or portability reasons you may + * need to enclose port I/O operations between @p chSysLock() and + * @p chSysUnlock(). + * @note The default implementation is non atomic and not necessarily + * optimal. Low level drivers may optimize the function by using + * specific hardware or coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @api + */ +#if !defined(pal_lld_setport) || defined(__DOXYGEN__) +#define palSetPort(port, bits) \ + palWritePort(port, palReadLatch(port) | (bits)) +#else +#define palSetPort(port, bits) pal_lld_setport(port, bits) +#endif + +/** + * @brief Clears a bits mask on a I/O port. + * @note The operation is not guaranteed to be atomic on all the + * architectures, for atomicity and/or portability reasons you may + * need to enclose port I/O operations between @p chSysLock() and + * @p chSysUnlock(). + * @note The default implementation is non atomic and not necessarily + * optimal. Low level drivers may optimize the function by using + * specific hardware or coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @api + */ +#if !defined(pal_lld_clearport) || defined(__DOXYGEN__) +#define palClearPort(port, bits) \ + palWritePort(port, palReadLatch(port) & ~(bits)) +#else +#define palClearPort(port, bits) pal_lld_clearport(port, bits) +#endif + +/** + * @brief Toggles a bits mask on a I/O port. + * @note The operation is not guaranteed to be atomic on all the + * architectures, for atomicity and/or portability reasons you may + * need to enclose port I/O operations between @p chSysLock() and + * @p chSysUnlock(). + * @note The default implementation is non atomic and not necessarily + * optimal. Low level drivers may optimize the function by using + * specific hardware or coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be XORed on the specified port + * + * @api + */ +#if !defined(pal_lld_toggleport) || defined(__DOXYGEN__) +#define palTogglePort(port, bits) \ + palWritePort(port, palReadLatch(port) ^ (bits)) +#else +#define palTogglePort(port, bits) pal_lld_toggleport(port, bits) +#endif + +/** + * @brief Reads a group of bits. + * + * @param[in] port port identifier + * @param[in] mask group mask, a logical AND is performed on the input + * data + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @api + */ +#if !defined(pal_lld_readgroup) || defined(__DOXYGEN__) +#define palReadGroup(port, mask, offset) \ + ((palReadPort(port) >> (offset)) & (mask)) +#else +#define palReadGroup(port, mask, offset) pal_lld_readgroup(port, mask, offset) +#endif + +/** + * @brief Writes a group of bits. + * + * @param[in] port port identifier + * @param[in] mask group mask, a logical AND is performed on the + * output data + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group + * width are masked. + * + * @api + */ +#if !defined(pal_lld_writegroup) || defined(__DOXYGEN__) +#define palWriteGroup(port, mask, offset, bits) \ + palWritePort(port, (palReadLatch(port) & ~((mask) << (offset))) | \ + (((bits) & (mask)) << (offset))) +#else +#define palWriteGroup(port, mask, offset, bits) \ + pal_lld_writegroup(port, mask, offset, bits) +#endif + + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @api + */ +#if !defined(pal_lld_setgroupmode) || defined(__DOXYGEN__) +#define palSetGroupMode(port, mask, offset, mode) +#else +#define palSetGroupMode(port, mask, offset, mode) \ + pal_lld_setgroupmode(port, mask, offset, mode) +#endif + +/** + * @brief Reads an input pad logical state. + * @note The default implementation not necessarily optimal. Low level + * drivers may optimize the function by using specific hardware + * or coding. + * @note The default implementation internally uses the @p palReadPort(). + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @return The logical state. + * @retval PAL_LOW low logical state. + * @retval PAL_HIGH high logical state. + * + * @api + */ +#if !defined(pal_lld_readpad) || defined(__DOXYGEN__) +#define palReadPad(port, pad) ((palReadPort(port) >> (pad)) & 1) +#else +#define palReadPad(port, pad) pal_lld_readpad(port, pad) +#endif + +/** + * @brief Writes a logical state on an output pad. + * @note The operation is not guaranteed to be atomic on all the + * architectures, for atomicity and/or portability reasons you may + * need to enclose port I/O operations between @p chSysLock() and + * @p chSysUnlock(). + * @note The default implementation is non atomic and not necessarily + * optimal. Low level drivers may optimize the function by using + * specific hardware or coding. + * @note The default implementation internally uses the @p palReadLatch() + * and @p palWritePort(). + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @api + */ +#if !defined(pal_lld_writepad) || defined(__DOXYGEN__) +#define palWritePad(port, pad, bit) \ + palWritePort(port, (palReadLatch(port) & ~PAL_PORT_BIT(pad)) | \ + (((bit) & 1) << pad)) +#else +#define palWritePad(port, pad, bit) pal_lld_writepad(port, pad, bit) +#endif + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * @note The operation is not guaranteed to be atomic on all the + * architectures, for atomicity and/or portability reasons you may + * need to enclose port I/O operations between @p chSysLock() and + * @p chSysUnlock(). + * @note The default implementation is non atomic and not necessarily + * optimal. Low level drivers may optimize the function by using + * specific hardware or coding. + * @note The default implementation internally uses the @p palSetPort(). + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @api + */ +#if !defined(pal_lld_setpad) || defined(__DOXYGEN__) +#define palSetPad(port, pad) palSetPort(port, PAL_PORT_BIT(pad)) +#else +#define palSetPad(port, pad) pal_lld_setpad(port, pad) +#endif + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * @note The operation is not guaranteed to be atomic on all the + * architectures, for atomicity and/or portability reasons you may + * need to enclose port I/O operations between @p chSysLock() and + * @p chSysUnlock(). + * @note The default implementation is non atomic and not necessarily + * optimal. Low level drivers may optimize the function by using + * specific hardware or coding. + * @note The default implementation internally uses the @p palClearPort(). + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @api + */ +#if !defined(pal_lld_clearpad) || defined(__DOXYGEN__) +#define palClearPad(port, pad) palClearPort(port, PAL_PORT_BIT(pad)) +#else +#define palClearPad(port, pad) pal_lld_clearpad(port, pad) +#endif + +/** + * @brief Toggles a pad logical state. + * @note The operation is not guaranteed to be atomic on all the + * architectures, for atomicity and/or portability reasons you may + * need to enclose port I/O operations between @p chSysLock() and + * @p chSysUnlock(). + * @note The default implementation is non atomic and not necessarily + * optimal. Low level drivers may optimize the function by using + * specific hardware or coding. + * @note The default implementation internally uses the @p palTogglePort(). + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @api + */ +#if !defined(pal_lld_togglepad) || defined(__DOXYGEN__) +#define palTogglePad(port, pad) palTogglePort(port, PAL_PORT_BIT(pad)) +#else +#define palTogglePad(port, pad) pal_lld_togglepad(port, pad) +#endif + + +/** + * @brief Pad mode setup. + * @details This function programs a pad with the specified mode. + * @note The default implementation not necessarily optimal. Low level + * drivers may optimize the function by using specific hardware + * or coding. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad mode + * + * @api + */ +#if !defined(pal_lld_setpadmode) || defined(__DOXYGEN__) +#define palSetPadMode(port, pad, mode) \ + palSetGroupMode(port, PAL_PORT_BIT(pad), 0, mode) +#else +#define palSetPadMode(port, pad, mode) pal_lld_setpadmode(port, pad, mode) +#endif +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + ioportmask_t palReadBus(IOBus *bus); + void palWriteBus(IOBus *bus, ioportmask_t bits); + void palSetBusMode(IOBus *bus, iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* _PAL_H_ */ + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/Project/os/hal/include/pwm.h b/Project/os/hal/include/pwm.h new file mode 100644 index 0000000..4d848f8 --- /dev/null +++ b/Project/os/hal/include/pwm.h @@ -0,0 +1,247 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file pwm.h + * @brief PWM Driver macros and structures. + * + * @addtogroup PWM + * @{ + */ + +#ifndef _PWM_H_ +#define _PWM_H_ + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name PWM output mode macros + * @{ + */ +/** + * @brief Standard output modes mask. + */ +#define PWM_OUTPUT_MASK 0x0F + +/** + * @brief Output not driven, callback only. + */ +#define PWM_OUTPUT_DISABLED 0x00 + +/** + * @brief Positive PWM logic, active is logic level one. + */ +#define PWM_OUTPUT_ACTIVE_HIGH 0x01 + +/** + * @brief Inverse PWM logic, active is logic level zero. + */ +#define PWM_OUTPUT_ACTIVE_LOW 0x02 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + PWM_UNINIT = 0, /**< Not initialized. */ + PWM_STOP = 1, /**< Stopped. */ + PWM_READY = 2, /**< Ready. */ +} pwmstate_t; + +/** + * @brief Type of a structure representing a PWM driver. + */ +typedef struct PWMDriver PWMDriver; + +/** + * @brief PWM notification callback type. + * + * @param[in] pwmp pointer to a @p PWMDriver object + */ +typedef void (*pwmcallback_t)(PWMDriver *pwmp); + +#include "pwm_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name PWM duty cycle conversion + * @{ + */ +/** + * @brief Converts from fraction to pulse width. + * @note Be careful with rounding errors, this is integer math not magic. + * You can specify tenths of thousandth but make sure you have the + * proper hardware resolution by carefully choosing the clock source + * and prescaler settings, see @p PWM_COMPUTE_PSC. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] denominator denominator of the fraction + * @param[in] numerator numerator of the fraction + * @return The pulse width to be passed to @p pwmEnableChannel(). + * + * @api + */ +#define PWM_FRACTION_TO_WIDTH(pwmp, denominator, numerator) \ + ((uint16_t)((((uint32_t)(pwmp)->period) * \ + (uint32_t)(numerator)) / (uint32_t)(denominator))) + +/** + * @brief Converts from degrees to pulse width. + * @note Be careful with rounding errors, this is integer math not magic. + * You can specify hundredths of degrees but make sure you have the + * proper hardware resolution by carefully choosing the clock source + * and prescaler settings, see @p PWM_COMPUTE_PSC. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] degrees degrees as an integer between 0 and 36000 + * @return The pulse width to be passed to @p pwmEnableChannel(). + * + * @api + */ +#define PWM_DEGREES_TO_WIDTH(pwmp, degrees) \ + PWM_FRACTION_TO_WIDTH(pwmp, 36000, degrees) + +/** + * @brief Converts from percentage to pulse width. + * @note Be careful with rounding errors, this is integer math not magic. + * You can specify tenths of thousandth but make sure you have the + * proper hardware resolution by carefully choosing the clock source + * and prescaler settings, see @p PWM_COMPUTE_PSC. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] percentage percentage as an integer between 0 and 10000 + * @return The pulse width to be passed to @p pwmEnableChannel(). + * + * @api + */ +#define PWM_PERCENTAGE_TO_WIDTH(pwmp, percentage) \ + PWM_FRACTION_TO_WIDTH(pwmp, 10000, percentage) +/** @} */ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @iclass + */ +#define pwmChangePeriodI(pwmp, period) { \ + (pwmp)->period = (period); \ + pwm_lld_change_period(pwmp, period); \ +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note Depending on the hardware implementation this function has + * effect starting on the next cycle (recommended implementation) + * or immediately (fallback implementation). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @iclass + */ +#define pwmEnableChannelI(pwmp, channel, width) \ + pwm_lld_enable_channel(pwmp, channel, width) + +/** + * @brief Disables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note Depending on the hardware implementation this function has + * effect starting on the next cycle (recommended implementation) + * or immediately (fallback implementation). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * + * @iclass + */ +#define pwmDisableChannelI(pwmp, channel) \ + pwm_lld_disable_channel(pwmp, channel) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void pwmInit(void); + void pwmObjectInit(PWMDriver *pwmp); + void pwmStart(PWMDriver *pwmp, const PWMConfig *config); + void pwmStop(PWMDriver *pwmp); + void pwmChangePeriod(PWMDriver *pwmp, pwmcnt_t period); + void pwmEnableChannel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width); + void pwmDisableChannel(PWMDriver *pwmp, pwmchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PWM */ + +#endif /* _PWM_H_ */ + +/** @} */ diff --git a/Project/os/hal/include/rtc.h b/Project/os/hal/include/rtc.h new file mode 100644 index 0000000..91a0982 --- /dev/null +++ b/Project/os/hal/include/rtc.h @@ -0,0 +1,165 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file rtc.h + * @brief RTC Driver macros and structures. + * + * @addtogroup RTC + * @{ + */ + +#ifndef _RTC_H_ +#define _RTC_H_ + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an RTC driver. + */ +typedef struct RTCDriver RTCDriver; + +/** + * @brief Type of a structure representing an RTC time stamp. + */ +typedef struct RTCTime RTCTime; + +#include "rtc_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Set current time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] timespec pointer to a @p RTCTime structure + * + * @iclass + */ +#define rtcSetTimeI(rtcp, timespec) rtc_lld_set_time(rtcp, timespec) + +/** + * @brief Get current time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[out] timespec pointer to a @p RTCTime structure + * + * @iclass + */ +#define rtcGetTimeI(rtcp, timespec) rtc_lld_get_time(rtcp, timespec) + +#if (RTC_ALARMS > 0) || defined(__DOXYGEN__) +/** + * @brief Set alarm time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[in] alarmspec pointer to a @p RTCAlarm structure or @p NULL + * + * @iclass + */ +#define rtcSetAlarmI(rtcp, alarm, alarmspec) \ + rtc_lld_set_alarm(rtcp, alarm, alarmspec) + +/** + * @brief Get current alarm. + * @note If an alarm has not been set then the returned alarm specification + * is not meaningful. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[out] alarmspec pointer to a @p RTCAlarm structure + * + * @iclass + */ +#define rtcGetAlarmI(rtcp, alarm, alarmspec) \ + rtc_lld_get_alarm(rtcp, alarm, alarmspec) +#endif /* RTC_ALARMS > 0 */ + +#if RTC_SUPPORTS_CALLBACKS || defined(__DOXYGEN__) +/** + * @brief Enables or disables RTC callbacks. + * @details This function enables or disables the callback, use a @p NULL + * pointer in order to disable it. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] callback callback function pointer or @p NULL + * + * @iclass + */ +#define rtcSetCallbackI(rtcp, callback) rtc_lld_set_callback(rtcp, callback) +#endif /* RTC_SUPPORTS_CALLBACKS */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void rtcInit(void); + void rtcSetTime(RTCDriver *rtcp, const RTCTime *timespec); + void rtcGetTime(RTCDriver *rtcp, RTCTime *timespec); +#if RTC_ALARMS > 0 + void rtcSetAlarm(RTCDriver *rtcp, + rtcalarm_t alarm, + const RTCAlarm *alarmspec); + void rtcGetAlarm(RTCDriver *rtcp, rtcalarm_t alarm, RTCAlarm *alarmspec); +#endif +#if RTC_SUPPORTS_CALLBACKS + void rtcSetCallback(RTCDriver *rtcp, rtccb_t callback); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_RTC */ +#endif /* _RTC_H_ */ + +/** @} */ diff --git a/Project/os/hal/include/sdc.h b/Project/os/hal/include/sdc.h new file mode 100644 index 0000000..3960e82 --- /dev/null +++ b/Project/os/hal/include/sdc.h @@ -0,0 +1,261 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file sdc.h + * @brief SDC Driver macros and structures. + * + * @addtogroup SDC + * @{ + */ + +#ifndef _SDC_H_ +#define _SDC_H_ + +#if HAL_USE_SDC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define SDC_BLOCK_SIZE 512 /**< Fixed block size. */ + +/** + * @brief Fixed pattern for CMD8. + */ +#define SDC_CMD8_PATTERN 0x000001AA + +/** + * @name SD cart types + * @{ + */ +#define SDC_MODE_CARDTYPE_MASK 0xF /**< @brief Card type mask. */ +#define SDC_MODE_CARDTYPE_SDV11 0 /**< @brief Card is SD V1.1.*/ +#define SDC_MODE_CARDTYPE_SDV20 1 /**< @brief Card is SD V2.0.*/ +#define SDC_MODE_CARDTYPE_MMC 2 /**< @brief Card is MMC. */ +#define SDC_MODE_HIGH_CAPACITY 0x10 /**< @brief High cap.card. */ +/** @} */ + +/** + * @brief Mask of error bits in R1 responses. + */ +#define SDC_R1_ERROR_MASK 0xFDFFE008 + +#define SDC_STS_IDLE 0 +#define SDC_STS_READY 1 +#define SDC_STS_IDENT 2 +#define SDC_STS_STBY 3 +#define SDC_STS_TRAN 4 +#define SDC_STS_DATA 5 +#define SDC_STS_RCV 6 +#define SDC_STS_PRG 7 +#define SDC_STS_DIS 8 + +#define SDC_CMD_GO_IDLE_STATE 0 +#define SDC_CMD_INIT 1 +#define SDC_CMD_ALL_SEND_CID 2 +#define SDC_CMD_SEND_RELATIVE_ADDR 3 +#define SDC_CMD_SET_BUS_WIDTH 6 +#define SDC_CMD_SEL_DESEL_CARD 7 +#define SDC_CMD_SEND_IF_COND 8 +#define SDC_CMD_SEND_CSD 9 +#define SDC_CMD_STOP_TRANSMISSION 12 +#define SDC_CMD_SEND_STATUS 13 +#define SDC_CMD_SET_BLOCKLEN 16 +#define SDC_CMD_READ_SINGLE_BLOCK 17 +#define SDC_CMD_READ_MULTIPLE_BLOCK 18 +#define SDC_CMD_SET_BLOCK_COUNT 23 +#define SDC_CMD_WRITE_BLOCK 24 +#define SDC_CMD_WRITE_MULTIPLE_BLOCK 25 +#define SDC_CMD_APP_OP_COND 41 +#define SDC_CMD_LOCK_UNLOCK 42 +#define SDC_CMD_APP_CMD 55 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name SDC configuration options + * @{ + */ +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + SDC_UNINIT = 0, /**< Not initialized. */ + SDC_STOP = 1, /**< Stopped. */ + SDC_READY = 2, /**< Ready. */ + SDC_CONNECTING = 3, /**< Card connection in progress. */ + SDC_DISCONNECTING = 4, /**< Card disconnection in progress. */ + SDC_ACTIVE = 5, /**< Cart initialized. */ + SDC_READING = 6, /**< Read operation in progress. */ + SDC_WRITING = 7, /**< Write operation in progress. */ +} sdcstate_t; + +#include "sdc_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name R1 response utilities + * @{ + */ +/** + * @brief Evaluates to @p TRUE if the R1 response contains error flags. + * + * @param[in] r1 the r1 response + */ +#define SDC_R1_ERROR(r1) (((r1) & SDC_R1_ERROR_MASK) != 0) + +/** + * @brief Returns the status field of an R1 response. + * + * @param[in] r1 the r1 response + */ +#define SDC_R1_STS(r1) (((r1) >> 9) & 15) + +/** + * @brief Evaluates to @p TRUE if the R1 response indicates a locked card. + * + * @param[in] r1 the r1 response + */ +#define SDC_R1_IS_CARD_LOCKED(r1) (((r1) >> 21) & 1) +/** @} */ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns the driver state. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @return The driver state. + * + * @api + */ +#define sdcGetDriverState(sdcp) ((sdcp)->state) + +/** + * @brief Returns the card insertion status. + * @note This macro wraps a low level function named + * @p sdc_lld_is_card_inserted(), this function must be + * provided by the application because it is not part of the + * SDC driver. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @return The card state. + * @retval FALSE card not inserted. + * @retval TRUE card inserted. + * + * @api + */ +#define sdcIsCardInserted(sdcp) (sdc_lld_is_card_inserted(sdcp)) + +/** + * @brief Returns the write protect status. + * @note This macro wraps a low level function named + * @p sdc_lld_is_write_protected(), this function must be + * provided by the application because it is not part of the + * SDC driver. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @return The card state. + * @retval FALSE card not inserted. + * @retval TRUE card inserted. + * + * @api + */ +#define sdcIsWriteProtected(sdcp) (sdc_lld_is_write_protected(sdcp)) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void sdcInit(void); + void sdcObjectInit(SDCDriver *sdcp); + void sdcStart(SDCDriver *sdcp, const SDCConfig *config); + void sdcStop(SDCDriver *sdcp); + bool_t sdcConnect(SDCDriver *sdcp); + bool_t sdcDisconnect(SDCDriver *sdcp); + bool_t sdcRead(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buffer, uint32_t n); + bool_t sdcWrite(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buffer, uint32_t n); + bool_t _sdc_wait_for_transfer_state(SDCDriver *sdcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SDC */ + +#endif /* _SDC_H_ */ + +/** @} */ diff --git a/Project/os/hal/include/serial.h b/Project/os/hal/include/serial.h new file mode 100644 index 0000000..972b0b2 --- /dev/null +++ b/Project/os/hal/include/serial.h @@ -0,0 +1,325 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file serial.h + * @brief Serial Driver macros and structures. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_H_ +#define _SERIAL_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Serial status flags + * @{ + */ +#define SD_PARITY_ERROR 32 /**< @brief Parity error happened. */ +#define SD_FRAMING_ERROR 64 /**< @brief Framing error happened. */ +#define SD_OVERRUN_ERROR 128 /**< @brief Overflow happened. */ +#define SD_NOISE_ERROR 256 /**< @brief Noise on the line. */ +#define SD_BREAK_DETECTED 512 /**< @brief Break detected. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Serial configuration options + * @{ + */ +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !CH_USE_QUEUES && !CH_USE_EVENTS +#error "Serial Driver requires CH_USE_QUEUES and CH_USE_EVENTS" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + SD_UNINIT = 0, /**< Not initialized. */ + SD_STOP = 1, /**< Stopped. */ + SD_READY = 2 /**< Ready. */ +} sdstate_t; + +/** + * @brief Structure representing a serial driver. + */ +typedef struct SerialDriver SerialDriver; + +#include "serial_lld.h" + +/** + * @brief @p SerialDriver specific methods. + */ +#define _serial_driver_methods \ + _base_asynchronous_channel_methods + +/** + * @extends BaseAsynchronousChannelVMT + * + * @brief @p SerialDriver virtual methods table. + */ +struct SerialDriverVMT { + _serial_driver_methods +}; + +/** + * @extends BaseAsynchronousChannel + * + * @brief Full duplex serial driver class. + * @details This class extends @p BaseAsynchronousChannel by adding physical + * I/O queues. + */ +struct SerialDriver { + /** @brief Virtual Methods Table.*/ + const struct SerialDriverVMT *vmt; + _serial_driver_data +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Direct output check on a @p SerialDriver. + * @note This function bypasses the indirect access to the channel and + * checks directly the output queue. This is faster but cannot + * be used to check different channels implementations. + * + * @see chIOPutWouldBlock() + * @deprecated + * + * @api + */ +#define sdPutWouldBlock(sdp) chOQIsFullI(&(sdp)->oqueue) + +/** + * @brief Direct input check on a @p SerialDriver. + * @note This function bypasses the indirect access to the channel and + * checks directly the input queue. This is faster but cannot + * be used to check different channels implementations. + * + * @see chIOGetWouldBlock() + * @deprecated + * + * @api + */ +#define sdGetWouldBlock(sdp) chIQIsEmptyI(&(sdp)->iqueue) + +/** + * @brief Direct write to a @p SerialDriver. + * @note This function bypasses the indirect access to the channel and + * writes directly on the output queue. This is faster but cannot + * be used to write to different channels implementations. + * + * @see chIOPut() + * + * @api + */ +#define sdPut(sdp, b) chOQPut(&(sdp)->oqueue, b) + +/** + * @brief Direct write to a @p SerialDriver with timeout specification. + * @note This function bypasses the indirect access to the channel and + * writes directly on the output queue. This is faster but cannot + * be used to write to different channels implementations. + * + * @see chIOPutTimeout() + * + * @api + */ +#define sdPutTimeout(sdp, b, t) chOQPutTimeout(&(sdp)->oqueue, b, t) + +/** + * @brief Direct read from a @p SerialDriver. + * @note This function bypasses the indirect access to the channel and + * reads directly from the input queue. This is faster but cannot + * be used to read from different channels implementations. + * + * @see chIOGet() + * + * @api + */ +#define sdGet(sdp) chIQGet(&(sdp)->iqueue) + +/** + * @brief Direct read from a @p SerialDriver with timeout specification. + * @note This function bypasses the indirect access to the channel and + * reads directly from the input queue. This is faster but cannot + * be used to read from different channels implementations. + * + * @see chIOGetTimeout() + * + * @api + */ +#define sdGetTimeout(sdp, t) chIQGetTimeout(&(sdp)->iqueue, t) + +/** + * @brief Direct blocking write to a @p SerialDriver. + * @note This function bypasses the indirect access to the channel and + * writes directly to the output queue. This is faster but cannot + * be used to write from different channels implementations. + * + * @see chIOWriteTimeout() + * + * @api + */ +#define sdWrite(sdp, b, n) \ + chOQWriteTimeout(&(sdp)->oqueue, b, n, TIME_INFINITE) + +/** + * @brief Direct blocking write to a @p SerialDriver with timeout + * specification. + * @note This function bypasses the indirect access to the channel and + * writes directly to the output queue. This is faster but cannot + * be used to write to different channels implementations. + * + * @see chIOWriteTimeout() + * + * @api + */ +#define sdWriteTimeout(sdp, b, n, t) \ + chOQWriteTimeout(&(sdp)->oqueue, b, n, t) + +/** + * @brief Direct non-blocking write to a @p SerialDriver. + * @note This function bypasses the indirect access to the channel and + * writes directly to the output queue. This is faster but cannot + * be used to write to different channels implementations. + * + * @see chIOWriteTimeout() + * + * @api + */ +#define sdAsynchronousWrite(sdp, b, n) \ + chOQWriteTimeout(&(sdp)->oqueue, b, n, TIME_IMMEDIATE) + +/** + * @brief Direct blocking read from a @p SerialDriver. + * @note This function bypasses the indirect access to the channel and + * reads directly from the input queue. This is faster but cannot + * be used to read from different channels implementations. + * + * @see chIOReadTimeout() + * + * @api + */ +#define sdRead(sdp, b, n) \ + chIQReadTimeout(&(sdp)->iqueue, b, n, TIME_INFINITE) + +/** + * @brief Direct blocking read from a @p SerialDriver with timeout + * specification. + * @note This function bypasses the indirect access to the channel and + * reads directly from the input queue. This is faster but cannot + * be used to read from different channels implementations. + * + * @see chIOReadTimeout() + * + * @api + */ +#define sdReadTimeout(sdp, b, n, t) \ + chIQReadTimeout(&(sdp)->iqueue, b, n, t) + +/** + * @brief Direct non-blocking read from a @p SerialDriver. + * @note This function bypasses the indirect access to the channel and + * reads directly from the input queue. This is faster but cannot + * be used to read from different channels implementations. + * + * @see chIOReadTimeout() + * + * @api + */ +#define sdAsynchronousRead(sdp, b, n) \ + chIQReadTimeout(&(sdp)->iqueue, b, n, TIME_IMMEDIATE) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void sdInit(void); + void sdObjectInit(SerialDriver *sdp, qnotify_t inotify, qnotify_t onotify); + void sdStart(SerialDriver *sdp, const SerialConfig *config); + void sdStop(SerialDriver *sdp); + void sdIncomingDataI(SerialDriver *sdp, uint8_t b); + msg_t sdRequestDataI(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_H_ */ + +/** @} */ diff --git a/Project/os/hal/include/serial_usb.h b/Project/os/hal/include/serial_usb.h new file mode 100644 index 0000000..ad355f4 --- /dev/null +++ b/Project/os/hal/include/serial_usb.h @@ -0,0 +1,182 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file serial_usb.h + * @brief Serial over USB Driver macros and structures. + * + * @addtogroup SERIAL_USB + * @{ + */ + +#ifndef _SERIAL_USB_H_ +#define _SERIAL_USB_H_ + +#if HAL_USE_SERIAL_USB || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name SERIAL_USB configuration options + * @{ + */ +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !HAL_USE_USB && !CH_USE_QUEUES && !CH_USE_EVENTS +#error "Serial over USB Driver requires HAL_USE_USB, CH_USE_QUEUES, " + "CH_USE_EVENTS" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + SDU_UNINIT = 0, /**< Not initialized. */ + SDU_STOP = 1, /**< Stopped. */ + SDU_READY = 2 /**< Ready. */ +} sdustate_t; + +/** + * @brief Structure representing a serial over USB driver. + */ +typedef struct SerialUSBDriver SerialUSBDriver; + +/** + * @brief Serial over USB Driver configuration structure. + * @details An instance of this structure must be passed to @p sduStart() + * in order to configure and start the driver operations. + */ +typedef struct { + /** + * @brief USB driver to use. + */ + USBDriver *usbp; + /** + * @brief USB driver configuration structure. + */ + USBConfig usb_config; +} SerialUSBConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_usb_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdustate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input buffer.*/ \ + uint8_t ib[SERIAL_USB_BUFFERS_SIZE]; \ + /* Output buffer.*/ \ + uint8_t ob[SERIAL_USB_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Current configuration data.*/ \ + const SerialUSBConfig *config; + +/** + * @brief @p SerialUSBDriver specific methods. + */ +#define _serial_usb_driver_methods \ + _base_asynchronous_channel_methods + +/** + * @extends BaseAsynchronousChannelVMT + * + * @brief @p SerialDriver virtual methods table. + */ +struct SerialUSBDriverVMT { + _serial_usb_driver_methods +}; + +/** + * @extends BaseAsynchronousChannel + * + * @brief Full duplex serial driver class. + * @details This class extends @p BaseAsynchronousChannel by adding physical + * I/O queues. + */ +struct SerialUSBDriver { + /** @brief Virtual Methods Table.*/ + const struct SerialUSBDriverVMT *vmt; + _serial_usb_driver_data +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void sduInit(void); + void sduObjectInit(SerialUSBDriver *sdp); + void sduStart(SerialUSBDriver *sdup, const SerialUSBConfig *config); + void sduStop(SerialUSBDriver *sdup); + bool_t sduRequestsHook(USBDriver *usbp); + void sduDataTransmitted(USBDriver *usbp, usbep_t ep); + void sduDataReceived(USBDriver *usbp, usbep_t ep); + void sduInterruptTransmitted(USBDriver *usbp, usbep_t ep); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL_USB */ + +#endif /* _SERIAL_USB_H_ */ + +/** @} */ diff --git a/Project/os/hal/include/spi.h b/Project/os/hal/include/spi.h new file mode 100644 index 0000000..a160d25 --- /dev/null +++ b/Project/os/hal/include/spi.h @@ -0,0 +1,330 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file spi.h + * @brief SPI Driver macros and structures. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_H_ +#define _SPI_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name SPI configuration options + * @{ + */ +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if SPI_USE_MUTUAL_EXCLUSION && !CH_USE_MUTEXES && !CH_USE_SEMAPHORES +#error "SPI_USE_MUTUAL_EXCLUSION requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + SPI_UNINIT = 0, /**< Not initialized. */ + SPI_STOP = 1, /**< Stopped. */ + SPI_READY = 2, /**< Ready. */ + SPI_ACTIVE = 3, /**< Exchanging data. */ + SPI_COMPLETE = 4 /**< Asynchronous operation complete. */ +} spistate_t; + +#include "spi_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @iclass + */ +#define spiSelectI(spip) { \ + spi_lld_select(spip); \ +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @iclass + */ +#define spiUnselectI(spip) { \ + spi_lld_unselect(spip); \ +} + +/** + * @brief Ignores data on the SPI bus. + * @details This asynchronous function starts the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @pre A slave must have been selected using @p spiSelect() or + * @p spiSelectI(). + * @post At the end of the operation the configured callback is invoked. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @iclass + */ +#define spiStartIgnoreI(spip, n) { \ + (spip)->state = SPI_ACTIVE; \ + spi_lld_ignore(spip, n); \ +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @pre A slave must have been selected using @p spiSelect() or + * @p spiSelectI(). + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @iclass + */ +#define spiStartExchangeI(spip, n, txbuf, rxbuf) { \ + (spip)->state = SPI_ACTIVE; \ + spi_lld_exchange(spip, n, txbuf, rxbuf); \ +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @pre A slave must have been selected using @p spiSelect() or + * @p spiSelectI(). + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @iclass + */ +#define spiStartSendI(spip, n, txbuf) { \ + (spip)->state = SPI_ACTIVE; \ + spi_lld_send(spip, n, txbuf); \ +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @pre A slave must have been selected using @p spiSelect() or + * @p spiSelectI(). + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @iclass + */ +#define spiStartReceiveI(spip, n, rxbuf) { \ + (spip)->state = SPI_ACTIVE; \ + spi_lld_receive(spip, n, rxbuf); \ +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * @note This API is implemented as a macro in order to minimize latency. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +#define spiPolledExchange(spip, frame) spi_lld_polled_exchange(spip, frame) +/** @} */ + +/** + * @name Low Level driver helper macros + * @{ + */ +#if SPI_USE_WAIT || defined(__DOXYGEN__) +/** + * @brief Waits for operation completion. + * @details This function waits for the driver to complete the current + * operation. + * @pre An operation must be running while the function is invoked. + * @note No more than one thread can wait on a SPI driver using + * this function. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +#define _spi_wait_s(spip) { \ + chDbgAssert((spip)->thread == NULL, \ + "_spi_wait(), #1", "already waiting"); \ + (spip)->thread = chThdSelf(); \ + chSchGoSleepS(THD_STATE_SUSPENDED); \ +} + +/** + * @brief Wakes up the waiting thread. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +#define _spi_wakeup_isr(spip) { \ + if ((spip)->thread != NULL) { \ + Thread *tp = (spip)->thread; \ + (spip)->thread = NULL; \ + chSysLockFromIsr(); \ + chSchReadyI(tp); \ + chSysUnlockFromIsr(); \ + } \ +} +#else /* !SPI_USE_WAIT */ +#define _spi_wait_s(spip) +#define _spi_wakeup_isr(spip) +#endif /* !SPI_USE_WAIT */ + +/** + * @brief Common ISR code. + * @details This code handles the portable part of the ISR code: + * - Callback invocation. + * - Waiting thread wakeup, if any. + * - Driver state transitions. + * . + * @note This macro is meant to be used in the low level drivers + * implementation only. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +#define _spi_isr_code(spip) { \ + if ((spip)->config->end_cb) { \ + (spip)->state = SPI_COMPLETE; \ + (spip)->config->end_cb(spip); \ + if ((spip)->state == SPI_COMPLETE) \ + (spip)->state = SPI_READY; \ + } \ + else \ + (spip)->state = SPI_READY; \ + _spi_wakeup_isr(spip); \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void spiInit(void); + void spiObjectInit(SPIDriver *spip); + void spiStart(SPIDriver *spip, const SPIConfig *config); + void spiStop(SPIDriver *spip); + void spiSelect(SPIDriver *spip); + void spiUnselect(SPIDriver *spip); + void spiStartIgnore(SPIDriver *spip, size_t n); + void spiStartExchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spiStartSend(SPIDriver *spip, size_t n, const void *txbuf); + void spiStartReceive(SPIDriver *spip, size_t n, void *rxbuf); +#if SPI_USE_WAIT + void spiIgnore(SPIDriver *spip, size_t n); + void spiExchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf); + void spiSend(SPIDriver *spip, size_t n, const void *txbuf); + void spiReceive(SPIDriver *spip, size_t n, void *rxbuf); +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION + void spiAcquireBus(SPIDriver *spip); + void spiReleaseBus(SPIDriver *spip); +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_H_ */ + +/** @} */ diff --git a/Project/os/hal/include/tm.h b/Project/os/hal/include/tm.h new file mode 100644 index 0000000..7583be2 --- /dev/null +++ b/Project/os/hal/include/tm.h @@ -0,0 +1,125 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file tm.h + * @brief Time Measurement driver header. + * + * @addtogroup TM + * @{ + */ + +#ifndef _TM_H_ +#define _TM_H_ + +#if HAL_USE_TM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a Time Measurement object. + * @note Start/stop of measurements is performed through the function + * pointers in order to avoid inlining of those functions which + * could compromise measurement accuracy. + * @note The maximum measurable time period depends on the implementation + * of the realtime counter in the HAL driver. + * @note The measurement is not 100% cycle-accurate, it can be in excess + * of few cycles depending on the compiler and target architecture. + * @note Interrupts can affect measurement if the measurement is performed + * with interrupts enabled. + */ +typedef struct TimeMeasurement TimeMeasurement; + +/** + * @brief Time Measurement structure. + */ +struct TimeMeasurement { + void (*start)(TimeMeasurement *tmp); /**< @brief Starts a measurement. */ + void (*stop)(TimeMeasurement *tmp); /**< @brief Stops a measurement. */ + halrtcnt_t last; /**< @brief Last measurement. */ + halrtcnt_t worst; /**< @brief Worst measurement. */ + halrtcnt_t best; /**< @brief Best measurement. */ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Starts a measurement. + * @pre The @p TimeMeasurement must be initialized. + * @note This function can be invoked in any context. + * + * @param[in,out] tmp pointer to a @p TimeMeasurement structure + * + * @special + */ +#define tmStartMeasurement(tmp) (tmp)->start(tmp) + +/** + * @brief Stops a measurement. + * @pre The @p TimeMeasurement must be initialized. + * @note This function can be invoked in any context. + * + * @param[in,out] tmp pointer to a @p TimeMeasurement structure + * + * @special + */ +#define tmStopMeasurement(tmp) (tmp)->stop(tmp) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void tmInit(void); + void tmObjectInit(TimeMeasurement *tmp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_TM */ + +#endif /* _TM_H_ */ + +/** @} */ diff --git a/Project/os/hal/include/uart.h b/Project/os/hal/include/uart.h new file mode 100644 index 0000000..2cd51a9 --- /dev/null +++ b/Project/os/hal/include/uart.h @@ -0,0 +1,129 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file uart.h + * @brief UART Driver macros and structures. + * + * @addtogroup UART + * @{ + */ + +#ifndef _UART_H_ +#define _UART_H_ + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name UART status flags + * @{ + */ +#define UART_NO_ERROR 0 /**< @brief No pending conditions. */ +#define UART_PARITY_ERROR 4 /**< @brief Parity error happened. */ +#define UART_FRAMING_ERROR 8 /**< @brief Framing error happened. */ +#define UART_OVERRUN_ERROR 16 /**< @brief Overflow happened. */ +#define UART_NOISE_ERROR 32 /**< @brief Noise on the line. */ +#define UART_BREAK_DETECTED 64 /**< @brief Break detected. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + UART_UNINIT = 0, /**< Not initialized. */ + UART_STOP = 1, /**< Stopped. */ + UART_READY = 2 /**< Ready. */ +} uartstate_t; + +/** + * @brief Transmitter state machine states. + */ +typedef enum { + UART_TX_IDLE = 0, /**< Not transmitting. */ + UART_TX_ACTIVE = 1, /**< Transmitting. */ + UART_TX_COMPLETE = 2 /**< Buffer complete. */ +} uarttxstate_t; + +/** + * @brief Receiver state machine states. + */ +typedef enum { + UART_RX_IDLE = 0, /**< Not receiving. */ + UART_RX_ACTIVE = 1, /**< Receiving. */ + UART_RX_COMPLETE = 2 /**< Buffer complete. */ +} uartrxstate_t; + +#include "uart_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void uartInit(void); + void uartObjectInit(UARTDriver *uartp); + void uartStart(UARTDriver *uartp, const UARTConfig *config); + void uartStop(UARTDriver *uartp); + void uartStartSend(UARTDriver *uartp, size_t n, const void *txbuf); + void uartStartSendI(UARTDriver *uartp, size_t n, const void *txbuf); + size_t uartStopSend(UARTDriver *uartp); + size_t uartStopSendI(UARTDriver *uartp); + void uartStartReceive(UARTDriver *uartp, size_t n, void *rxbuf); + void uartStartReceiveI(UARTDriver *uartp, size_t n, void *rxbuf); + size_t uartStopReceive(UARTDriver *uartp); + size_t uartStopReceiveI(UARTDriver *uartp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_UART */ + +#endif /* _UART_H_ */ + +/** @} */ diff --git a/Project/os/hal/include/usb.h b/Project/os/hal/include/usb.h new file mode 100644 index 0000000..21d705c --- /dev/null +++ b/Project/os/hal/include/usb.h @@ -0,0 +1,611 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file usb.h + * @brief USB Driver macros and structures. + * + * @addtogroup USB + * @{ + */ + +#ifndef _USB_H_ +#define _USB_H_ + +#if HAL_USE_USB || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define USB_RTYPE_DIR_MASK 0x80 +#define USB_RTYPE_DIR_HOST2DEV 0x00 +#define USB_RTYPE_DIR_DEV2HOST 0x80 +#define USB_RTYPE_TYPE_MASK 0x60 +#define USB_RTYPE_TYPE_STD 0x00 +#define USB_RTYPE_TYPE_CLASS 0x20 +#define USB_RTYPE_TYPE_VENDOR 0x40 +#define USB_RTYPE_TYPE_RESERVED 0x60 +#define USB_RTYPE_RECIPIENT_MASK 0x1F +#define USB_RTYPE_RECIPIENT_DEVICE 0x00 +#define USB_RTYPE_RECIPIENT_INTERFACE 0x01 +#define USB_RTYPE_RECIPIENT_ENDPOINT 0x02 +#define USB_RTYPE_RECIPIENT_OTHER 0x03 + +#define USB_REQ_GET_STATUS 0 +#define USB_REQ_CLEAR_FEATURE 1 +#define USB_REQ_SET_FEATURE 3 +#define USB_REQ_SET_ADDRESS 5 +#define USB_REQ_GET_DESCRIPTOR 6 +#define USB_REQ_SET_DESCRIPTOR 7 +#define USB_REQ_GET_CONFIGURATION 8 +#define USB_REQ_SET_CONFIGURATION 9 +#define USB_REQ_GET_INTERFACE 10 +#define USB_REQ_SET_INTERFACE 11 +#define USB_REQ_SYNCH_FRAME 12 + +#define USB_DESCRIPTOR_DEVICE 1 +#define USB_DESCRIPTOR_CONFIGURATION 2 +#define USB_DESCRIPTOR_STRING 3 +#define USB_DESCRIPTOR_INTERFACE 4 +#define USB_DESCRIPTOR_ENDPOINT 5 +#define USB_DESCRIPTOR_DEVICE_QUALIFIER 6 +#define USB_DESCRIPTOR_OTHER_SPEED_CFG 7 +#define USB_DESCRIPTOR_INTERFACE_POWER 8 + +#define USB_FEATURE_ENDPOINT_HALT 0 +#define USB_FEATURE_DEVICE_REMOTE_WAKEUP 1 +#define USB_FEATURE_TEST_MODE 2 + +#define USB_EARLY_SET_ADDRESS 0 +#define USB_LATE_SET_ADDRESS 1 + +/** + * @name Helper macros for USB descriptors + * @{ + */ +/** + * @brief Helper macro for index values into descriptor strings. + */ +#define USB_DESC_INDEX(i) ((uint8_t)(i)) + +/** + * @brief Helper macro for byte values into descriptor strings. + */ +#define USB_DESC_BYTE(b) ((uint8_t)(b)) + +/** + * @brief Helper macro for word values into descriptor strings. + */ +#define USB_DESC_WORD(w) \ + (uint8_t)((w) & 255), \ + (uint8_t)(((w) >> 8) & 255) + +/** + * @brief Helper macro for BCD values into descriptor strings. + */ +#define USB_DESC_BCD(bcd) \ + (uint8_t)((bcd) & 255), \ + (uint8_t)(((bcd) >> 8) & 255) + +/** + * @brief Device Descriptor helper macro. + */ +#define USB_DESC_DEVICE(bcdUSB, bDeviceClass, bDeviceSubClass, \ + bDeviceProtocol, bMaxPacketSize, idVendor, \ + idProduct, bcdDevice, iManufacturer, \ + iProduct, iSerialNumber, bNumConfigurations) \ + USB_DESC_BYTE(18), \ + USB_DESC_BYTE(USB_DESCRIPTOR_DEVICE), \ + USB_DESC_BCD(bcdUSB), \ + USB_DESC_BYTE(bDeviceClass), \ + USB_DESC_BYTE(bDeviceSubClass), \ + USB_DESC_BYTE(bDeviceProtocol), \ + USB_DESC_BYTE(bMaxPacketSize), \ + USB_DESC_WORD(idVendor), \ + USB_DESC_WORD(idProduct), \ + USB_DESC_BCD(bcdDevice), \ + USB_DESC_INDEX(iManufacturer), \ + USB_DESC_INDEX(iProduct), \ + USB_DESC_INDEX(iSerialNumber), \ + USB_DESC_BYTE(bNumConfigurations) + +/** + * @brief Configuration Descriptor helper macro. + */ +#define USB_DESC_CONFIGURATION(wTotalLength, bNumInterfaces, \ + bConfigurationValue, iConfiguration, \ + bmAttributes, bMaxPower) \ + USB_DESC_BYTE(9), \ + USB_DESC_BYTE(USB_DESCRIPTOR_CONFIGURATION), \ + USB_DESC_WORD(wTotalLength), \ + USB_DESC_BYTE(bNumInterfaces), \ + USB_DESC_BYTE(bConfigurationValue), \ + USB_DESC_INDEX(iConfiguration), \ + USB_DESC_BYTE(bmAttributes), \ + USB_DESC_BYTE(bMaxPower) + +/** + * @brief Interface Descriptor helper macro. + */ +#define USB_DESC_INTERFACE(bInterfaceNumber, bAlternateSetting, \ + bNumEndpoints, bInterfaceClass, \ + bInterfaceSubClass, bInterfaceProtocol, \ + iInterface) \ + USB_DESC_BYTE(9), \ + USB_DESC_BYTE(USB_DESCRIPTOR_INTERFACE), \ + USB_DESC_BYTE(bInterfaceNumber), \ + USB_DESC_BYTE(bAlternateSetting), \ + USB_DESC_BYTE(bNumEndpoints), \ + USB_DESC_BYTE(bInterfaceClass), \ + USB_DESC_BYTE(bInterfaceSubClass), \ + USB_DESC_BYTE(bInterfaceProtocol), \ + USB_DESC_INDEX(iInterface) + +/** + * @brief Endpoint Descriptor helper macro. + */ +#define USB_DESC_ENDPOINT(bEndpointAddress, bmAttributes, wMaxPacketSize, \ + bInterval) \ + USB_DESC_BYTE(7), \ + USB_DESC_BYTE(USB_DESCRIPTOR_ENDPOINT), \ + USB_DESC_BYTE(bEndpointAddress), \ + USB_DESC_BYTE(bmAttributes), \ + USB_DESC_WORD(wMaxPacketSize), \ + USB_DESC_BYTE(bInterval) +/** @} */ + +/** + * @name Endpoint types and settings + * @{ + */ +#define USB_EP_MODE_TYPE 0x0003 /**< Endpoint type mask. */ +#define USB_EP_MODE_TYPE_CTRL 0x0000 /**< Control endpoint. */ +#define USB_EP_MODE_TYPE_ISOC 0x0001 /**< Isochronous endpoint. */ +#define USB_EP_MODE_TYPE_BULK 0x0002 /**< Bulk endpoint. */ +#define USB_EP_MODE_TYPE_INTR 0x0003 /**< Interrupt endpoint. */ +#define USB_EP_MODE_TRANSACTION 0x0000 /**< Transaction mode. */ +#define USB_EP_MODE_PACKET 0x0010 /**< Packet mode enabled. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an USB driver. + */ +typedef struct USBDriver USBDriver; + +/** + * @brief Type of an endpoint identifier. + */ +typedef uint8_t usbep_t; + +/** + * @brief Type of a driver state machine possible states. + */ +typedef enum { + USB_UNINIT = 0, /**< Not initialized. */ + USB_STOP = 1, /**< Stopped. */ + USB_READY = 2, /**< Ready, after bus reset. */ + USB_SELECTED = 3, /**< Address assigned. */ + USB_ACTIVE = 4, /**< Active, configuration selected.*/ +} usbstate_t; + +/** + * @brief Type of an endpoint status. + */ +typedef enum { + EP_STATUS_DISABLED = 0, /**< Endpoint not active. */ + EP_STATUS_STALLED = 1, /**< Endpoint opened but stalled. */ + EP_STATUS_ACTIVE = 2 /**< Active endpoint. */ +} usbepstatus_t; + +/** + * @brief Type of an endpoint zero state machine states. + */ +typedef enum { + USB_EP0_WAITING_SETUP, /**< Waiting for SETUP data. */ + USB_EP0_TX, /**< Trasmitting. */ + USB_EP0_WAITING_STS, /**< Waiting status. */ + USB_EP0_RX, /**< Receiving. */ + USB_EP0_SENDING_STS, /**< Sending status. */ + USB_EP0_ERROR /**< Error, EP0 stalled. */ +} usbep0state_t; + +/** + * @brief Type of an enumeration of the possible USB events. + */ +typedef enum { + USB_EVENT_RESET = 0, /**< Driver has been reset by host. */ + USB_EVENT_ADDRESS = 1, /**< Address assigned. */ + USB_EVENT_CONFIGURED = 2, /**< Configuration selected. */ + USB_EVENT_SUSPEND = 3, /**< Entering suspend mode. */ + USB_EVENT_WAKEUP = 4, /**< Leaving suspend mode. */ + USB_EVENT_STALLED = 5, /**< Endpoint 0 error, stalled. */ +} usbevent_t; + +/** + * @brief Type of an USB descriptor. + */ +typedef struct { + /** + * @brief Descriptor size in unicode characters. + */ + size_t ud_size; + /** + * @brief Pointer to the descriptor. + */ + const uint8_t *ud_string; +} USBDescriptor; + +/** + * @brief Type of an USB generic notification callback. + * + * @param[in] usbp pointer to the @p USBDriver object triggering the + * callback + */ +typedef void (*usbcallback_t)(USBDriver *usbp); + +/** + * @brief Type of an USB endpoint callback. + * + * @param[in] usbp pointer to the @p USBDriver object triggering the + * callback + * @param[in] ep endpoint number + */ +typedef void (*usbepcallback_t)(USBDriver *usbp, usbep_t ep); + +/** + * @brief Type of an USB event notification callback. + * + * @param[in] usbp pointer to the @p USBDriver object triggering the + * callback + * @param[in] event event type + */ +typedef void (*usbeventcb_t)(USBDriver *usbp, usbevent_t event); + +/** + * @brief Type of a requests handler callback. + * @details The request is encoded in the @p usb_setup buffer. + * + * @param[in] usbp pointer to the @p USBDriver object triggering the + * callback + * @return The request handling exit code. + * @retval FALSE Request not recognized by the handler. + * @retval TRUE Request handled. + */ +typedef bool_t (*usbreqhandler_t)(USBDriver *usbp); + +/** + * @brief Type of an USB descriptor-retrieving callback. + */ +typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang); + +#include "usb_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Connects the USB device. + */ +#define usbConnectBus(usbp) usb_lld_connect_bus(usbp) + +/** + * @brief Disconnect the USB device. + */ +#define usbDisconnectBus(usbp) usb_lld_disconnect_bus(usbp) + +/** + * @brief Returns the current frame number. + * + * @param[in] usbp pointer to the @p USBDriver object + * @return The current frame number. + * + * @api + */ +#define usbGetFrameNumber(usbp) usb_lld_get_frame_number(usbp) + +/** + * @brief Returns the status of an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The operation status. + * @retval FALSE Endpoint ready. + * @retval TRUE Endpoint transmitting. + * + * @iclass + */ +#define usbGetTransmitStatusI(usbp, ep) ((usbp)->transmitting & (1 << (ep))) + +/** + * @brief Returns the status of an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The operation status. + * @retval FALSE Endpoint ready. + * @retval TRUE Endpoint receiving. + * + * @iclass + */ +#define usbGetReceiveStatusI(usbp, ep) ((usbp)->receiving & (1 << (ep))) + +/** + * @brief Reads from a dedicated packet buffer. + * @pre In order to use this function the endpoint must have been + * initialized in packet mode. + * @note This function can be invoked both in thread and IRQ context. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the packet data + * @param[in] n maximum number of bytes to copy. This value must + * not exceed the maximum packet size for this endpoint. + * @return The received packet size regardless the specified + * @p n parameter. + * @retval 0 Zero size packet received. + * + * @special + */ +#define usbReadPacketBuffer(usbp, ep, buf, n) \ + usb_lld_read_packet_buffer(usbp, ep, buf, n) + +/** + * @brief Writes to a dedicated packet buffer. + * @pre In order to use this function the endpoint must have been + * initialized in packet mode. + * @note This function can be invoked both in thread and IRQ context. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[in] buf buffer where to fetch the packet data + * @param[in] n maximum number of bytes to copy. This value must + * not exceed the maximum packet size for this endpoint. + * + * @special + */ +#define usbWritePacketBuffer(usbp, ep, buf, n) \ + usb_lld_write_packet_buffer(usbp, ep, buf, n) + +/** + * @brief Prepares for a receive transaction on an OUT endpoint. + * @pre In order to use this function the endpoint must have been + * initialized in transaction mode. + * @post The endpoint is ready for @p usbStartReceiveI(). + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the received data + * @param[in] n maximum number of bytes to copy + * + * @special + */ +#define usbPrepareReceive(usbp, ep, buf, n) \ + usb_lld_prepare_receive(usbp, ep, buf, n) + +/** + * @brief Prepares for a transmit transaction on an IN endpoint. + * @pre In order to use this function the endpoint must have been + * initialized in transaction mode. + * @post The endpoint is ready for @p usbStartTransmitI(). + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[in] buf buffer where to fetch the data to be transmitted + * @param[in] n maximum number of bytes to copy + * + * @special + */ +#define usbPrepareTransmit(usbp, ep, buf, n) \ + usb_lld_prepare_transmit(usbp, ep, buf, n) + +/** + * @brief Returns the exact size of a receive transaction. + * @details The received size can be different from the size specified in + * @p usbStartReceiveI() because the last packet could have a size + * different from the expected one. + * @pre The OUT endpoint must have been configured in transaction mode + * in order to use this function. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return Received data size. + * + * @iclass + */ +#define usbGetReceiveTransactionSizeI(usbp, ep) \ + usb_lld_get_transaction_size(usbp, ep) + +/** + * @brief Returns the exact size of a received packet. + * @pre The OUT endpoint must have been configured in packet mode + * in order to use this function. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return Received data size. + * + * @iclass + */ +#define usbGetReceivePacketSizeI(usbp, ep) \ + usb_lld_get_packet_size(usbp, ep) + +/** + * @brief Request transfer setup. + * @details This macro is used by the request handling callbacks in order to + * prepare a transaction over the endpoint zero. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] buf pointer to a buffer for the transaction data + * @param[in] n number of bytes to be transferred + * @param[in] endcb callback to be invoked after the transfer or @p NULL + * + * @api + */ +#define usbSetupTransfer(usbp, buf, n, endcb) { \ + (usbp)->ep0next = (buf); \ + (usbp)->ep0n = (n); \ + (usbp)->ep0endcb = (endcb); \ +} + +/** + * @brief Reads a setup packet from the dedicated packet buffer. + * @details This function must be invoked in the context of the @p setup_cb + * callback in order to read the received setup packet. + * @pre In order to use this function the endpoint must have been + * initialized as a control endpoint. + * @note This function can be invoked both in thread and IRQ context. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the packet data + * + * @special + */ +#define usbReadSetup(usbp, ep, buf) usb_lld_read_setup(usbp, ep, buf) +/** @} */ + +/** + * @name Low Level driver helper macros + * @{ + */ +/** + * @brief Common ISR code, usb event callback. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] evt USB event code + * + * @notapi + */ +#define _usb_isr_invoke_event_cb(usbp, evt) { \ + if (((usbp)->config->event_cb) != NULL) \ + (usbp)->config->event_cb(usbp, evt); \ +} + +/** + * @brief Common ISR code, SOF callback. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +#define _usb_isr_invoke_sof_cb(usbp) { \ + if (((usbp)->config->sof_cb) != NULL) \ + (usbp)->config->sof_cb(usbp); \ +} + +/** + * @brief Common ISR code, setup packet callback. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +#define _usb_isr_invoke_setup_cb(usbp, ep) { \ + (usbp)->epc[ep]->setup_cb(usbp, ep); \ +} + +/** + * @brief Common ISR code, IN endpoint callback. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +#define _usb_isr_invoke_in_cb(usbp, ep) { \ + (usbp)->transmitting &= ~(1 << (ep)); \ + (usbp)->epc[ep]->in_cb(usbp, ep); \ +} + +/** + * @brief Common ISR code, OUT endpoint event. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +#define _usb_isr_invoke_out_cb(usbp, ep) { \ + (usbp)->receiving &= ~(1 << (ep)); \ + (usbp)->epc[ep]->out_cb(usbp, ep); \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void usbInit(void); + void usbObjectInit(USBDriver *usbp); + void usbStart(USBDriver *usbp, const USBConfig *config); + void usbStop(USBDriver *usbp); + void usbInitEndpointI(USBDriver *usbp, usbep_t ep, + const USBEndpointConfig *epcp); + void usbDisableEndpointsI(USBDriver *usbp); + void usbReadSetupI(USBDriver *usbp, usbep_t ep, uint8_t *buf); + bool_t usbStartReceiveI(USBDriver *usbp, usbep_t ep); + bool_t usbStartTransmitI(USBDriver *usbp, usbep_t ep); + bool_t usbStallReceiveI(USBDriver *usbp, usbep_t ep); + bool_t usbStallTransmitI(USBDriver *usbp, usbep_t ep); + void _usb_reset(USBDriver *usbp); + void _usb_ep0setup(USBDriver *usbp, usbep_t ep); + void _usb_ep0in(USBDriver *usbp, usbep_t ep); + void _usb_ep0out(USBDriver *usbp, usbep_t ep); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_USB */ + +#endif /* _USB_H_ */ + +/** @} */ diff --git a/Project/os/hal/include/usb_cdc.h b/Project/os/hal/include/usb_cdc.h new file mode 100644 index 0000000..f768c38 --- /dev/null +++ b/Project/os/hal/include/usb_cdc.h @@ -0,0 +1,141 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/*-* + * @file usb_cdc.h + * @brief USB Communication Device Class support header. + * + * @addtogroup USB_CDC + * @{ + */ + +#ifndef _USB_CDC_H_ +#define _USB_CDC_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name CDC specific messages. + * @{ + */ +#define CDC_SEND_ENCAPSULATED_COMMAND 0x00 +#define CDC_GET_ENCAPSULATED_RESPONSE 0x01 +#define CDC_SET_COMM_FEATURE 0x02 +#define CDC_GET_COMM_FEATURE 0x03 +#define CDC_CLEAR_COMM_FEATURE 0x04 +#define CDC_SET_AUX_LINE_STATE 0x10 +#define CDC_SET_HOOK_STATE 0x11 +#define CDC_PULSE_SETUP 0x12 +#define CDC_SEND_PULSE 0x13 +#define CDC_SET_PULSE_TIME 0x14 +#define CDC_RING_AUX_JACK 0x15 +#define CDC_SET_LINE_CODING 0x20 +#define CDC_GET_LINE_CODING 0x21 +#define CDC_SET_CONTROL_LINE_STATE 0x22 +#define CDC_SEND_BREAK 0x23 +#define CDC_SET_RINGER_PARMS 0x30 +#define CDC_GET_RINGER_PARMS 0x31 +#define CDC_SET_OPERATION_PARMS 0x32 +#define CDC_GET_OPERATION_PARMS 0x33 +/** @} */ + +/** + * @name Line Control bit definitions. + * @{ + */ +#define LC_STOP_1 0 +#define LC_STOP_1P5 1 +#define LC_STOP_2 2 + +#define LC_PARITY_NONE 0 +#define LC_PARITY_ODD 1 +#define LC_PARITY_EVEN 2 +#define LC_PARITY_MARK 3 +#define LC_PARITY_SPACE 4 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name USB_CDC configuration options + * @{ + */ +/** + * @brief Endpoint number for bulk IN. + */ +#if !defined(USB_CDC_DATA_REQUEST_EP) || defined(__DOXYGEN__) +#define USB_CDC_DATA_REQUEST_EP 1 +#endif + +/** + * @brief Endpoint number for interrupt IN. + */ +#if !defined(USB_CDC_INTERRUPT_REQUEST_EP) || defined(__DOXYGEN__) +#define USB_CDC_INTERRUPT_REQUEST_EP 2 +#endif + +/** + * @brief Endpoint number for bulk OUT. + */ +#if !defined(USB_CDC_DATA_AVAILABLE_EP) || defined(__DOXYGEN__) +#define USB_CDC_DATA_AVAILABLE_EP 3 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of Line Coding structure. + */ +typedef struct { + uint8_t dwDTERate[4]; + uint8_t bCharFormat; + uint8_t bParityType; + uint8_t bDataBits; +} cdc_linecoding_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#endif /* _USB_CDC_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S128.h b/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S128.h new file mode 100644 index 0000000..8fc3a98 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S128.h @@ -0,0 +1,2229 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7S128.h +// Object : AT91SAM7S128 definitions +// Generated : AT91 SW Application Group 07/07/2008 (16:12:49) +// +// CVS Reference : /AT91SAM7S128.pl/1.12/Wed Aug 30 14:08:34 2006// +// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005// +// CVS Reference : /MC_SAM7S.pl/1.4/Thu Feb 16 16:45:50 2006// +// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005// +// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005// +// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006// +// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7S128_H +#define AT91SAM7S128_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[469]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved13[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved14[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved15[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved16[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved17[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved18[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved19[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved20[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; +#else + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved4[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; +#else +#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register + +#endif +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; +#else +#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register +#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register +#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register +#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register +#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register +#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register + +#endif +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved2[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +#else +#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register +#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register +#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register +#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register +#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register +#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved + +#endif +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; +#else +#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register +#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register +#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register +#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register +#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register +#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register +#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register +#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register +#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register + +#endif +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register + AT91_REG Reserved3[4]; // + AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register + AT91_REG Reserved4[5]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7S128 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register +#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register +#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7S128 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 +#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 +#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data +#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 +#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave +#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave +#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock +#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync +#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock +#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data +#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data +#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock +#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync +#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data +#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data +#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock +#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send +#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send +#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect +#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready +#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready +#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator +#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data +#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 +#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 +#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock +#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data +#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data +#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send +#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send +#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data +#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S128 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller +#define AT91C_ID_3_Reserved ( 3) // Reserved +#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter +#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_15_Reserved (15) // Reserved +#define AT91C_ID_16_Reserved (16) // Reserved +#define AT91C_ID_17_Reserved (17) // Reserved +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7S128 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S128 +// ***************************************************************************** +// ISRAM +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00100000) // Internal FLASH base address +#define AT91C_IFLASH_SIZE (0x00020000) // Internal FLASH size in byte (128 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (512) // Internal FLASH Number of Pages: 512 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (8) // Internal FLASH Number of Lock Bits: 8 bytes + +#endif diff --git a/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S256.h b/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S256.h new file mode 100644 index 0000000..a4f1af1 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S256.h @@ -0,0 +1,2229 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7S256.h +// Object : AT91SAM7S256 definitions +// Generated : AT91 SW Application Group 07/07/2008 (16:12:57) +// +// CVS Reference : /AT91SAM7S256.pl/1.12/Wed Aug 30 14:08:39 2006// +// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005// +// CVS Reference : /MC_SAM7S.pl/1.4/Thu Feb 16 16:45:50 2006// +// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005// +// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005// +// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006// +// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7S256_H +#define AT91SAM7S256_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[469]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved13[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved14[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved15[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved16[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved17[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved18[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved19[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved20[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; +#else + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved4[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; +#else +#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register + +#endif +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; +#else +#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register +#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register +#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register +#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register +#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register +#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register + +#endif +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved2[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +#else +#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register +#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register +#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register +#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register +#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register +#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved + +#endif +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; +#else +#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register +#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register +#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register +#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register +#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register +#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register +#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register +#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register +#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register + +#endif +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register + AT91_REG Reserved3[4]; // + AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register + AT91_REG Reserved4[5]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7S256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register +#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register +#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7S256 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 +#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 +#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data +#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 +#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave +#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave +#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock +#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync +#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock +#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data +#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data +#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock +#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync +#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data +#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data +#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock +#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send +#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send +#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect +#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready +#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready +#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator +#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data +#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 +#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 +#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock +#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data +#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data +#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send +#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send +#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data +#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S256 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller +#define AT91C_ID_3_Reserved ( 3) // Reserved +#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter +#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_15_Reserved (15) // Reserved +#define AT91C_ID_16_Reserved (16) // Reserved +#define AT91C_ID_17_Reserved (17) // Reserved +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7S256 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S256 +// ***************************************************************************** +// ISRAM +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00100000) // Internal FLASH base address +#define AT91C_IFLASH_SIZE (0x00040000) // Internal FLASH size in byte (256 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH Number of Pages: 1024 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes + +#endif diff --git a/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S512.h b/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S512.h new file mode 100644 index 0000000..aa45c39 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S512.h @@ -0,0 +1,2303 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7S512.h +// Object : AT91SAM7S512 definitions +// Generated : AT91 SW Application Group 07/07/2008 (16:13:20) +// +// CVS Reference : /AT91SAM7S512.pl/1.6/Wed Aug 30 14:08:44 2006// +// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005// +// CVS Reference : /MC_SAM7SE.pl/1.10/Thu Feb 16 16:35:28 2006// +// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005// +// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005// +// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006// +// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// +// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// CVS Reference : /EBI_SAM7SE512.pl/1.22/Fri Nov 18 17:47:47 2005// +// CVS Reference : /SMC_1783A.pl/1.4/Thu Feb 3 10:30:06 2005// +// CVS Reference : /SDRC_SAM7SE512.pl/1.7/Fri Jul 8 07:50:18 2005// +// CVS Reference : /HECC_SAM7SE512.pl/1.8/Tue Jul 12 06:31:42 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7S512_H +#define AT91SAM7S512_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[469]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved13[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved14[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved15[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved16[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved17[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved18[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved19[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved20[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; +#else + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved4[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; +#else +#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register + +#endif +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Embedded Flash Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EFC { + AT91_REG EFC_FMR; // MC Flash Mode Register + AT91_REG EFC_FCR; // MC Flash Command Register + AT91_REG EFC_FSR; // MC Flash Status Register + AT91_REG EFC_VR; // MC Flash Version Register +} AT91S_EFC, *AT91PS_EFC; +#else +#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_FMR) MC Flash Mode Register +#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_FCR) MC Flash Command Register +#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_FSR) MC Flash Status Register +#define MC_VR (AT91_CAST(AT91_REG *) 0x0000000C) // (MC_VR) MC Flash Version Register + +#endif +// -------- MC_FMR : (EFC Offset: 0x0) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (EFC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (EFC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (EFC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (EFC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (EFC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (EFC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (EFC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (EFC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (EFC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (EFC) Flash Microsecond Cycle Number +// -------- MC_FCR : (EFC Offset: 0x4) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (EFC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (EFC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (EFC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (EFC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (EFC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (EFC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (EFC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (EFC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (EFC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (EFC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (EFC) Writing Protect Key +// -------- MC_FSR : (EFC Offset: 0x8) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (EFC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (EFC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (EFC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (EFC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (EFC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (EFC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (EFC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (EFC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (EFC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (EFC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (EFC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (EFC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (EFC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (EFC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (EFC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (EFC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (EFC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (EFC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (EFC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (EFC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (EFC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (EFC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (EFC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (EFC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (EFC) Sector 15 Lock Status +// -------- EFC_VR : (EFC Offset: 0xc) EFC version register -------- +#define AT91C_EFC_VERSION (0xFFF << 0) // (EFC) EFC version number +#define AT91C_EFC_MFN (0x7 << 16) // (EFC) EFC MFN + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[1]; // + AT91_REG MC_PUIA[16]; // MC Protection Unit Area + AT91_REG MC_PUP; // MC Protection Unit Peripherals + AT91_REG MC_PUER; // MC Protection Unit Enable Register + AT91_REG Reserved1[2]; // + AT91_REG MC0_FMR; // MC Flash Mode Register + AT91_REG MC0_FCR; // MC Flash Command Register + AT91_REG MC0_FSR; // MC Flash Status Register + AT91_REG MC0_VR; // MC Flash Version Register + AT91_REG MC1_FMR; // MC Flash Mode Register + AT91_REG MC1_FCR; // MC Flash Command Register + AT91_REG MC1_FSR; // MC Flash Status Register + AT91_REG MC1_VR; // MC Flash Version Register +} AT91S_MC, *AT91PS_MC; +#else +#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register +#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register +#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register +#define MC_PUIA (AT91_CAST(AT91_REG *) 0x00000010) // (MC_PUIA) MC Protection Unit Area +#define MC_PUP (AT91_CAST(AT91_REG *) 0x00000050) // (MC_PUP) MC Protection Unit Peripherals +#define MC_PUER (AT91_CAST(AT91_REG *) 0x00000054) // (MC_PUER) MC Protection Unit Enable Register + +#endif +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- +#define AT91C_MC_PROT (0x3 << 0) // (MC) Protection +#define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access +#define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access +#define AT91C_MC_PROT_PRWURO (0x2) // (MC) Privilege: Read/Write, User: Read Only +#define AT91C_MC_PROT_PRWURW (0x3) // (MC) Privilege: Read/Write, User: Read/Write +#define AT91C_MC_SIZE (0xF << 4) // (MC) Internal Area Size +#define AT91C_MC_SIZE_1KB (0x0 << 4) // (MC) Area size 1KByte +#define AT91C_MC_SIZE_2KB (0x1 << 4) // (MC) Area size 2KByte +#define AT91C_MC_SIZE_4KB (0x2 << 4) // (MC) Area size 4KByte +#define AT91C_MC_SIZE_8KB (0x3 << 4) // (MC) Area size 8KByte +#define AT91C_MC_SIZE_16KB (0x4 << 4) // (MC) Area size 16KByte +#define AT91C_MC_SIZE_32KB (0x5 << 4) // (MC) Area size 32KByte +#define AT91C_MC_SIZE_64KB (0x6 << 4) // (MC) Area size 64KByte +#define AT91C_MC_SIZE_128KB (0x7 << 4) // (MC) Area size 128KByte +#define AT91C_MC_SIZE_256KB (0x8 << 4) // (MC) Area size 256KByte +#define AT91C_MC_SIZE_512KB (0x9 << 4) // (MC) Area size 512KByte +#define AT91C_MC_SIZE_1MB (0xA << 4) // (MC) Area size 1MByte +#define AT91C_MC_SIZE_2MB (0xB << 4) // (MC) Area size 2MByte +#define AT91C_MC_SIZE_4MB (0xC << 4) // (MC) Area size 4MByte +#define AT91C_MC_SIZE_8MB (0xD << 4) // (MC) Area size 8MByte +#define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte +#define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte +#define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address +// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- +// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- +#define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved2[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +#else +#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register +#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register +#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register +#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register +#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register +#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved + +#endif +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; +#else +#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register +#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register +#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register +#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register +#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register +#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register +#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register +#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register +#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register + +#endif +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register + AT91_REG Reserved3[4]; // + AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register + AT91_REG Reserved4[5]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7S512 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for EFC0 peripheral ========== +#define AT91C_EFC0_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (EFC0) MC Flash Command Register +#define AT91C_EFC0_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (EFC0) MC Flash Status Register +#define AT91C_EFC0_VR (AT91_CAST(AT91_REG *) 0xFFFFFF6C) // (EFC0) MC Flash Version Register +#define AT91C_EFC0_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (EFC0) MC Flash Mode Register +// ========== Register definition for EFC1 peripheral ========== +#define AT91C_EFC1_VR (AT91_CAST(AT91_REG *) 0xFFFFFF7C) // (EFC1) MC Flash Version Register +#define AT91C_EFC1_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF74) // (EFC1) MC Flash Command Register +#define AT91C_EFC1_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF78) // (EFC1) MC Flash Status Register +#define AT91C_EFC1_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF70) // (EFC1) MC Flash Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_PUP (AT91_CAST(AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals +#define AT91C_MC_PUIA (AT91_CAST(AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area +#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_PUER (AT91_CAST(AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register +#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register +#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7S512 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 +#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 +#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data +#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 +#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave +#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave +#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock +#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync +#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock +#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data +#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data +#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock +#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync +#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data +#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data +#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock +#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send +#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send +#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect +#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready +#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready +#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator +#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data +#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 +#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 +#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock +#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data +#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data +#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send +#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send +#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data +#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S512 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller +#define AT91C_ID_3_Reserved ( 3) // Reserved +#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter +#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_15_Reserved (15) // Reserved +#define AT91C_ID_16_Reserved (16) // Reserved +#define AT91C_ID_17_Reserved (17) // Reserved +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7S512 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_EFC0 (AT91_CAST(AT91PS_EFC) 0xFFFFFF60) // (EFC0) Base Address +#define AT91C_BASE_EFC1 (AT91_CAST(AT91PS_EFC) 0xFFFFFF70) // (EFC1) Base Address +#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S512 +// ***************************************************************************** +// ISRAM +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00100000) // Internal FLASH base address +#define AT91C_IFLASH_SIZE (0x00080000) // Internal FLASH size in byte (512 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (2048) // Internal FLASH Number of Pages: 2048 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (32) // Internal FLASH Number of Lock Bits: 32 bytes + +#endif diff --git a/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S64.h b/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S64.h new file mode 100644 index 0000000..d124ce2 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S64.h @@ -0,0 +1,2229 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7S64.h +// Object : AT91SAM7S64 definitions +// Generated : AT91 SW Application Group 07/07/2008 (16:13:29) +// +// CVS Reference : /AT91SAM7S64.pl/1.23/Wed Aug 30 14:08:51 2006// +// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005// +// CVS Reference : /MC_SAM7S.pl/1.4/Thu Feb 16 16:45:50 2006// +// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005// +// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005// +// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006// +// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7S64_H +#define AT91SAM7S64_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[469]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved13[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved14[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved15[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved16[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved17[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved18[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved19[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved20[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; +#else + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved4[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; +#else +#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register + +#endif +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; +#else +#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register +#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register +#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register +#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register +#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register +#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register + +#endif +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved2[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +#else +#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register +#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register +#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register +#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register +#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register +#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved + +#endif +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; +#else +#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register +#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register +#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register +#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register +#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register +#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register +#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register +#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register +#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register + +#endif +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register + AT91_REG Reserved3[4]; // + AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register + AT91_REG Reserved4[5]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register +#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register +#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 +#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 +#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data +#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 +#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave +#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave +#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock +#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync +#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock +#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data +#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data +#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock +#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync +#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data +#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data +#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock +#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send +#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send +#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect +#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready +#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready +#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator +#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data +#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 +#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 +#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock +#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data +#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data +#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send +#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send +#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data +#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller +#define AT91C_ID_3_Reserved ( 3) // Reserved +#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter +#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_15_Reserved (15) // Reserved +#define AT91C_ID_16_Reserved (16) // Reserved +#define AT91C_ID_17_Reserved (17) // Reserved +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +// ISRAM +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00004000) // Internal SRAM size in byte (16 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00100000) // Internal FLASH base address +#define AT91C_IFLASH_SIZE (0x00010000) // Internal FLASH size in byte (64 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (128) // Internal FLASH Page Size: 128 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (4096) // Internal FLASH Lock Region Size: 4 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (512) // Internal FLASH Number of Pages: 512 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes + +#endif diff --git a/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X128.h b/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X128.h new file mode 100644 index 0000000..7fab07f --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X128.h @@ -0,0 +1,2914 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X128.h +// Object : AT91SAM7X128 definitions +// Generated : AT91 SW Application Group 07/07/2008 (16:15:23) +// +// CVS Reference : /AT91SAM7X128.pl/1.19/Wed Aug 30 14:09:08 2006// +// CVS Reference : /SYS_SAM7X.pl/1.3/Wed Feb 2 15:48:15 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:22:29 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 14:00:19 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005// +// CVS Reference : /UDP_6ept.pl/1.1/Wed Aug 30 10:56:49 2006// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SSC_6078B.pl/1.2/Wed Apr 16 08:28:18 2008// +// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005// +// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X128_H +#define AT91SAM7X128_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; +#else + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; +#else +#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register + +#endif +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; +#else +#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register +#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register +#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register +#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register +#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register +#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register + +#endif +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection +#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock +#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low +#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 +#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved2[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +#else +#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register +#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register +#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register +#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register +#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register +#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved + +#endif +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; +#else +#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register +#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register +#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register +#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register +#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register +#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register +#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register +#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register +#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register + +#endif +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; +#else +#define CAN_MMR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MMR) MailBox Mode Register +#define CAN_MAM (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register +#define CAN_MID (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_MID) MailBox ID Register +#define CAN_MFID (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_MFID) MailBox Family ID Register +#define CAN_MSR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_MSR) MailBox Status Register +#define CAN_MDL (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_MDL) MailBox Data Low Register +#define CAN_MDH (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_MDH) MailBox Data High Register +#define CAN_MCR (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_MCR) MailBox Control Register + +#endif +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; +#else +#define CAN_MR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MR) Mode Register +#define CAN_IER (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_IER) Interrupt Enable Register +#define CAN_IDR (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_IDR) Interrupt Disable Register +#define CAN_IMR (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_IMR) Interrupt Mask Register +#define CAN_SR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_SR) Status Register +#define CAN_BR (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_BR) Baudrate Register +#define CAN_TIM (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_TIM) Timer Register +#define CAN_TIMESTP (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_TIMESTP) Time Stamp Register +#define CAN_ECR (AT91_CAST(AT91_REG *) 0x00000020) // (CAN_ECR) Error Counter Register +#define CAN_TCR (AT91_CAST(AT91_REG *) 0x00000024) // (CAN_TCR) Transfer Command Register +#define CAN_ACR (AT91_CAST(AT91_REG *) 0x00000028) // (CAN_ACR) Abort Command Register +#define CAN_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (CAN_VR) Version Register + +#endif +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; +#else +#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register +#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register +#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register +#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register +#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer +#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer +#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register +#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register +#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register +#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register +#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register +#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register +#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register +#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register +#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register +#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register +#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register +#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register +#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register +#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register +#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register +#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register +#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register +#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register +#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register +#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register +#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register +#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register +#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register +#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register +#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register +#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register +#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register +#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register +#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0] +#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32] +#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes +#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes +#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes +#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes +#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes +#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes +#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes +#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes +#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register +#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register +#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register +#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register +#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register + +#endif +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII +#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID (AT91_CAST(AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID (AT91_CAST(AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID (AT91_CAST(AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID (AT91_CAST(AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID (AT91_CAST(AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID (AT91_CAST(AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID (AT91_CAST(AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID (AT91_CAST(AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER (AT91_CAST(AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP (AT91_CAST(AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR (AT91_CAST(AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM (AT91_CAST(AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR (AT91_CAST(AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR (AT91_CAST(AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H (AT91_CAST(AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L (AT91_CAST(AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE (AT91_CAST(AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE (AT91_CAST(AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF (AT91_CAST(AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND (AT91_CAST(AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L (AT91_CAST(AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR (AT91_CAST(AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE (AT91_CAST(AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL (AT91_CAST(AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID (AT91_CAST(AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB (AT91_CAST(AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR (AT91_CAST(AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV (AT91_CAST(AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE (AT91_CAST(AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA (AT91_CAST(AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP (AT91_CAST(AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF (AT91_CAST(AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT (AT91_CAST(AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF (AT91_CAST(AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE (AT91_CAST(AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ (AT91_CAST(AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN (AT91_CAST(AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO (AT91_CAST(AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV (AT91_CAST(AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR (AT91_CAST(AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF (AT91_CAST(AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR (AT91_CAST(AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF (AT91_CAST(AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR (AT91_CAST(AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO (AT91_CAST(AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER (AT91_CAST(AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE (AT91_CAST(AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE (AT91_CAST(AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_SPI0_NPCS0 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_SPI0_NPCS1 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPI0_NPCS2 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_SPI0_NPCS3 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_SPI0_MISO (AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_SPI0_MOSI (AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPI0_SPCK (AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_SPI1_NPCS1 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_SPI1_NPCS0 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPI1_SPCK (AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_SPI1_MOSI (AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_SPI1_MISO (AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_SPI1_NPCS1 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_SPI1_NPCS2 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_SPI1_NPCS3 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_SPI1_NPCS2 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_SPI1_NPCS3 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_SPI0_NPCS1 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_SPI0_NPCS2 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_SPI0_NPCS3 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_SPI1_NPCS1 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_SPI1_NPCS2 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_SPI0_NPCS1 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_SPI0_NPCS2 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV_ECRSDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_SPI1_NPCS3 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_SPI0_NPCS3 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_CAN (15) // Control Area Network Controller +#define AT91C_ID_EMAC (16) // Ethernet MAC +#define AT91C_ID_ADC (17) // Analog-to-Digital Converter +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ALL_INT (0xC003FFFF) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN (AT91_CAST(AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC (AT91_CAST(AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +// ISRAM +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00100000) // Internal FLASH base address +#define AT91C_IFLASH_SIZE (0x00020000) // Internal FLASH size in byte (128 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (512) // Internal FLASH Number of Pages: 512 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (8) // Internal FLASH Number of Lock Bits: 8 bytes + +#endif diff --git a/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X256.h b/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X256.h new file mode 100644 index 0000000..20b0e74 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X256.h @@ -0,0 +1,2918 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// - Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the disclaimer below in the documentation and/or +// other materials provided with the distribution. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X256.h +// Object : AT91SAM7X256 definitions +// Generated : AT91 SW Application Group 06/19/2007 (15:41:06) +// +// CVS Reference : /AT91SAM7X256.pl/1.16/Wed Aug 30 14:16:22 2006// +// CVS Reference : /SYS_SAM7X.pl/1.3/Wed Feb 2 15:48:15 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:22:29 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 14:00:19 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005// +// CVS Reference : /UDP_6ept.pl/1.1/Wed Aug 30 14:20:52 2006// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:25:46 2005// +// CVS Reference : /TWI_6061A.pl/1.2/Wed Oct 25 15:03:34 2006// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005// +// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X256_H +#define AT91SAM7X256_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; +#else + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; +#else +#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register + +#endif +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; +#else +#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register +#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register +#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register +#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register +#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register +#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register + +#endif +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection +#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock +#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low +#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 +#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved2[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +#else +#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register +#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register +#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register +#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register +#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register +#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved + +#endif +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; +#else +#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register +#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register +#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register +#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register +#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register +#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register +#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register +#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register +#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register + +#endif +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; +#else +#define CAN_MMR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MMR) MailBox Mode Register +#define CAN_MAM (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register +#define CAN_MID (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_MID) MailBox ID Register +#define CAN_MFID (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_MFID) MailBox Family ID Register +#define CAN_MSR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_MSR) MailBox Status Register +#define CAN_MDL (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_MDL) MailBox Data Low Register +#define CAN_MDH (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_MDH) MailBox Data High Register +#define CAN_MCR (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_MCR) MailBox Control Register + +#endif +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; +#else +#define CAN_MR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MR) Mode Register +#define CAN_IER (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_IER) Interrupt Enable Register +#define CAN_IDR (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_IDR) Interrupt Disable Register +#define CAN_IMR (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_IMR) Interrupt Mask Register +#define CAN_SR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_SR) Status Register +#define CAN_BR (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_BR) Baudrate Register +#define CAN_TIM (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_TIM) Timer Register +#define CAN_TIMESTP (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_TIMESTP) Time Stamp Register +#define CAN_ECR (AT91_CAST(AT91_REG *) 0x00000020) // (CAN_ECR) Error Counter Register +#define CAN_TCR (AT91_CAST(AT91_REG *) 0x00000024) // (CAN_TCR) Transfer Command Register +#define CAN_ACR (AT91_CAST(AT91_REG *) 0x00000028) // (CAN_ACR) Abort Command Register +#define CAN_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (CAN_VR) Version Register + +#endif +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; +#else +#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register +#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register +#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register +#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register +#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer +#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer +#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register +#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register +#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register +#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register +#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register +#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register +#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register +#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register +#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register +#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register +#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register +#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register +#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register +#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register +#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register +#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register +#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register +#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register +#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register +#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register +#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register +#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register +#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register +#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register +#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register +#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register +#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register +#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register +#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0] +#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32] +#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes +#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes +#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes +#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes +#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes +#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes +#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes +#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes +#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register +#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register +#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register +#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register +#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register + +#endif +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII +#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID (AT91_CAST(AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID (AT91_CAST(AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID (AT91_CAST(AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID (AT91_CAST(AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID (AT91_CAST(AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID (AT91_CAST(AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID (AT91_CAST(AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID (AT91_CAST(AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER (AT91_CAST(AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP (AT91_CAST(AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR (AT91_CAST(AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM (AT91_CAST(AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR (AT91_CAST(AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR (AT91_CAST(AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H (AT91_CAST(AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L (AT91_CAST(AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE (AT91_CAST(AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE (AT91_CAST(AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF (AT91_CAST(AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND (AT91_CAST(AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L (AT91_CAST(AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR (AT91_CAST(AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE (AT91_CAST(AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL (AT91_CAST(AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID (AT91_CAST(AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB (AT91_CAST(AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR (AT91_CAST(AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV (AT91_CAST(AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE (AT91_CAST(AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA (AT91_CAST(AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP (AT91_CAST(AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF (AT91_CAST(AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT (AT91_CAST(AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF (AT91_CAST(AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE (AT91_CAST(AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ (AT91_CAST(AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN (AT91_CAST(AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO (AT91_CAST(AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV (AT91_CAST(AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR (AT91_CAST(AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF (AT91_CAST(AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR (AT91_CAST(AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF (AT91_CAST(AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR (AT91_CAST(AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO (AT91_CAST(AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER (AT91_CAST(AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE (AT91_CAST(AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE (AT91_CAST(AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_SPI0_NPCS0 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_SPI0_NPCS1 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPI0_NPCS2 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_SPI0_NPCS3 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_SPI0_MISO (AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_SPI0_MOSI (AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPI0_SPCK (AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_SPI1_NPCS1 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_SPI1_NPCS0 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPI1_SPCK (AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_SPI1_MOSI (AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_SPI1_MISO (AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_SPI1_NPCS1 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_SPI1_NPCS2 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_SPI1_NPCS3 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_SPI1_NPCS2 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_SPI1_NPCS3 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_SPI0_NPCS1 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_SPI0_NPCS2 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_SPI0_NPCS3 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_SPI1_NPCS1 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_SPI1_NPCS2 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_SPI0_NPCS1 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_SPI0_NPCS2 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV_ECRSDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_SPI1_NPCS3 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_SPI0_NPCS3 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_CAN (15) // Control Area Network Controller +#define AT91C_ID_EMAC (16) // Ethernet MAC +#define AT91C_ID_ADC (17) // Analog-to-Digital Converter +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ALL_INT (0xC003FFFF) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN (AT91_CAST(AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC (AT91_CAST(AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +// ISRAM +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00100000) // Internal FLASH base address +#define AT91C_IFLASH_SIZE (0x00040000) // Internal FLASH size in byte (256 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH Number of Pages: 1024 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes + +#endif diff --git a/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X512.h b/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X512.h new file mode 100644 index 0000000..7c03a0d --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X512.h @@ -0,0 +1,2984 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X512.h +// Object : AT91SAM7X512 definitions +// Generated : AT91 SW Application Group 07/07/2008 (16:15:41) +// +// CVS Reference : /AT91SAM7X512.pl/1.7/Wed Aug 30 14:09:17 2006// +// CVS Reference : /SYS_SAM7X.pl/1.3/Wed Feb 2 15:48:15 2005// +// CVS Reference : /MC_SAM7SE.pl/1.10/Thu Feb 16 16:35:28 2006// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 14:00:19 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005// +// CVS Reference : /UDP_6ept.pl/1.1/Wed Aug 30 10:56:49 2006// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SSC_6078B.pl/1.2/Wed Apr 16 08:28:18 2008// +// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005// +// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X512_H +#define AT91SAM7X512_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; +#else + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; +#else +#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register + +#endif +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Embedded Flash Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EFC { + AT91_REG EFC_FMR; // MC Flash Mode Register + AT91_REG EFC_FCR; // MC Flash Command Register + AT91_REG EFC_FSR; // MC Flash Status Register + AT91_REG EFC_VR; // MC Flash Version Register +} AT91S_EFC, *AT91PS_EFC; +#else +#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_FMR) MC Flash Mode Register +#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_FCR) MC Flash Command Register +#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_FSR) MC Flash Status Register +#define MC_VR (AT91_CAST(AT91_REG *) 0x0000000C) // (MC_VR) MC Flash Version Register + +#endif +// -------- MC_FMR : (EFC Offset: 0x0) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (EFC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (EFC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (EFC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (EFC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (EFC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (EFC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (EFC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (EFC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (EFC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (EFC) Flash Microsecond Cycle Number +// -------- MC_FCR : (EFC Offset: 0x4) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (EFC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (EFC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (EFC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (EFC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (EFC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (EFC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (EFC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (EFC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (EFC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (EFC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (EFC) Writing Protect Key +// -------- MC_FSR : (EFC Offset: 0x8) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (EFC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (EFC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (EFC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (EFC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (EFC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (EFC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (EFC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (EFC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (EFC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (EFC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (EFC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (EFC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (EFC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (EFC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (EFC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (EFC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (EFC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (EFC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (EFC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (EFC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (EFC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (EFC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (EFC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (EFC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (EFC) Sector 15 Lock Status +// -------- EFC_VR : (EFC Offset: 0xc) EFC version register -------- +#define AT91C_EFC_VERSION (0xFFF << 0) // (EFC) EFC version number +#define AT91C_EFC_MFN (0x7 << 16) // (EFC) EFC MFN + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[1]; // + AT91_REG MC_PUIA[16]; // MC Protection Unit Area + AT91_REG MC_PUP; // MC Protection Unit Peripherals + AT91_REG MC_PUER; // MC Protection Unit Enable Register + AT91_REG Reserved1[2]; // + AT91_REG MC0_FMR; // MC Flash Mode Register + AT91_REG MC0_FCR; // MC Flash Command Register + AT91_REG MC0_FSR; // MC Flash Status Register + AT91_REG MC0_VR; // MC Flash Version Register + AT91_REG MC1_FMR; // MC Flash Mode Register + AT91_REG MC1_FCR; // MC Flash Command Register + AT91_REG MC1_FSR; // MC Flash Status Register + AT91_REG MC1_VR; // MC Flash Version Register +} AT91S_MC, *AT91PS_MC; +#else +#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register +#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register +#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register +#define MC_PUIA (AT91_CAST(AT91_REG *) 0x00000010) // (MC_PUIA) MC Protection Unit Area +#define MC_PUP (AT91_CAST(AT91_REG *) 0x00000050) // (MC_PUP) MC Protection Unit Peripherals +#define MC_PUER (AT91_CAST(AT91_REG *) 0x00000054) // (MC_PUER) MC Protection Unit Enable Register + +#endif +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- +#define AT91C_MC_PROT (0x3 << 0) // (MC) Protection +#define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access +#define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access +#define AT91C_MC_PROT_PRWURO (0x2) // (MC) Privilege: Read/Write, User: Read Only +#define AT91C_MC_PROT_PRWURW (0x3) // (MC) Privilege: Read/Write, User: Read/Write +#define AT91C_MC_SIZE (0xF << 4) // (MC) Internal Area Size +#define AT91C_MC_SIZE_1KB (0x0 << 4) // (MC) Area size 1KByte +#define AT91C_MC_SIZE_2KB (0x1 << 4) // (MC) Area size 2KByte +#define AT91C_MC_SIZE_4KB (0x2 << 4) // (MC) Area size 4KByte +#define AT91C_MC_SIZE_8KB (0x3 << 4) // (MC) Area size 8KByte +#define AT91C_MC_SIZE_16KB (0x4 << 4) // (MC) Area size 16KByte +#define AT91C_MC_SIZE_32KB (0x5 << 4) // (MC) Area size 32KByte +#define AT91C_MC_SIZE_64KB (0x6 << 4) // (MC) Area size 64KByte +#define AT91C_MC_SIZE_128KB (0x7 << 4) // (MC) Area size 128KByte +#define AT91C_MC_SIZE_256KB (0x8 << 4) // (MC) Area size 256KByte +#define AT91C_MC_SIZE_512KB (0x9 << 4) // (MC) Area size 512KByte +#define AT91C_MC_SIZE_1MB (0xA << 4) // (MC) Area size 1MByte +#define AT91C_MC_SIZE_2MB (0xB << 4) // (MC) Area size 2MByte +#define AT91C_MC_SIZE_4MB (0xC << 4) // (MC) Area size 4MByte +#define AT91C_MC_SIZE_8MB (0xD << 4) // (MC) Area size 8MByte +#define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte +#define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte +#define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address +// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- +// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- +#define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection +#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock +#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low +#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 +#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved2[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +#else +#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register +#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register +#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register +#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register +#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register +#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved + +#endif +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; +#else +#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register +#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register +#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register +#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register +#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register +#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register +#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register +#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register +#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register + +#endif +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; +#else +#define CAN_MMR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MMR) MailBox Mode Register +#define CAN_MAM (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register +#define CAN_MID (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_MID) MailBox ID Register +#define CAN_MFID (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_MFID) MailBox Family ID Register +#define CAN_MSR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_MSR) MailBox Status Register +#define CAN_MDL (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_MDL) MailBox Data Low Register +#define CAN_MDH (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_MDH) MailBox Data High Register +#define CAN_MCR (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_MCR) MailBox Control Register + +#endif +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; +#else +#define CAN_MR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MR) Mode Register +#define CAN_IER (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_IER) Interrupt Enable Register +#define CAN_IDR (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_IDR) Interrupt Disable Register +#define CAN_IMR (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_IMR) Interrupt Mask Register +#define CAN_SR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_SR) Status Register +#define CAN_BR (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_BR) Baudrate Register +#define CAN_TIM (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_TIM) Timer Register +#define CAN_TIMESTP (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_TIMESTP) Time Stamp Register +#define CAN_ECR (AT91_CAST(AT91_REG *) 0x00000020) // (CAN_ECR) Error Counter Register +#define CAN_TCR (AT91_CAST(AT91_REG *) 0x00000024) // (CAN_TCR) Transfer Command Register +#define CAN_ACR (AT91_CAST(AT91_REG *) 0x00000028) // (CAN_ACR) Abort Command Register +#define CAN_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (CAN_VR) Version Register + +#endif +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; +#else +#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register +#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register +#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register +#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register +#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer +#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer +#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register +#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register +#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register +#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register +#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register +#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register +#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register +#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register +#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register +#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register +#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register +#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register +#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register +#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register +#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register +#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register +#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register +#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register +#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register +#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register +#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register +#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register +#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register +#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register +#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register +#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register +#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register +#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register +#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0] +#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32] +#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes +#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes +#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes +#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes +#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes +#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes +#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes +#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes +#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register +#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register +#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register +#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register +#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register + +#endif +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII +#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X512 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for EFC0 peripheral ========== +#define AT91C_EFC0_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (EFC0) MC Flash Command Register +#define AT91C_EFC0_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (EFC0) MC Flash Status Register +#define AT91C_EFC0_VR (AT91_CAST(AT91_REG *) 0xFFFFFF6C) // (EFC0) MC Flash Version Register +#define AT91C_EFC0_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (EFC0) MC Flash Mode Register +// ========== Register definition for EFC1 peripheral ========== +#define AT91C_EFC1_VR (AT91_CAST(AT91_REG *) 0xFFFFFF7C) // (EFC1) MC Flash Version Register +#define AT91C_EFC1_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF74) // (EFC1) MC Flash Command Register +#define AT91C_EFC1_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF78) // (EFC1) MC Flash Status Register +#define AT91C_EFC1_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF70) // (EFC1) MC Flash Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_PUP (AT91_CAST(AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals +#define AT91C_MC_PUIA (AT91_CAST(AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area +#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_PUER (AT91_CAST(AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID (AT91_CAST(AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID (AT91_CAST(AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID (AT91_CAST(AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID (AT91_CAST(AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID (AT91_CAST(AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID (AT91_CAST(AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID (AT91_CAST(AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID (AT91_CAST(AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER (AT91_CAST(AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP (AT91_CAST(AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR (AT91_CAST(AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM (AT91_CAST(AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR (AT91_CAST(AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR (AT91_CAST(AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H (AT91_CAST(AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L (AT91_CAST(AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE (AT91_CAST(AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE (AT91_CAST(AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF (AT91_CAST(AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND (AT91_CAST(AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L (AT91_CAST(AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR (AT91_CAST(AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE (AT91_CAST(AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL (AT91_CAST(AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID (AT91_CAST(AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB (AT91_CAST(AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR (AT91_CAST(AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV (AT91_CAST(AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE (AT91_CAST(AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA (AT91_CAST(AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP (AT91_CAST(AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF (AT91_CAST(AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT (AT91_CAST(AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF (AT91_CAST(AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE (AT91_CAST(AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ (AT91_CAST(AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN (AT91_CAST(AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO (AT91_CAST(AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV (AT91_CAST(AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR (AT91_CAST(AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF (AT91_CAST(AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR (AT91_CAST(AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF (AT91_CAST(AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR (AT91_CAST(AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO (AT91_CAST(AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER (AT91_CAST(AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE (AT91_CAST(AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE (AT91_CAST(AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X512 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_SPI0_NPCS0 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_SPI0_NPCS1 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPI0_NPCS2 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_SPI0_NPCS3 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_SPI0_MISO (AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_SPI0_MOSI (AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPI0_SPCK (AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_SPI1_NPCS1 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_SPI1_NPCS0 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPI1_SPCK (AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_SPI1_MOSI (AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_SPI1_MISO (AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_SPI1_NPCS1 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_SPI1_NPCS2 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_SPI1_NPCS3 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_SPI1_NPCS2 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_SPI1_NPCS3 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_SPI0_NPCS1 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_SPI0_NPCS2 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_SPI0_NPCS3 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_SPI1_NPCS1 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_SPI1_NPCS2 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_SPI0_NPCS1 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_SPI0_NPCS2 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV_ECRSDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_SPI1_NPCS3 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_SPI0_NPCS3 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X512 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_CAN (15) // Control Area Network Controller +#define AT91C_ID_EMAC (16) // Ethernet MAC +#define AT91C_ID_ADC (17) // Analog-to-Digital Converter +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ALL_INT (0xC003FFFF) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X512 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_EFC0 (AT91_CAST(AT91PS_EFC) 0xFFFFFF60) // (EFC0) Base Address +#define AT91C_BASE_EFC1 (AT91_CAST(AT91PS_EFC) 0xFFFFFF70) // (EFC1) Base Address +#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN (AT91_CAST(AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC (AT91_CAST(AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X512 +// ***************************************************************************** +// ISRAM +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00020000) // Internal SRAM size in byte (128 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00100000) // Internal FLASH base address +#define AT91C_IFLASH_SIZE (0x00080000) // Internal FLASH size in byte (512 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (2048) // Internal FLASH Number of Pages: 2048 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (32) // Internal FLASH Number of Lock Bits: 32 bytes + +#endif diff --git a/Project/os/hal/platforms/AT91SAM7/at91lib/aic.c b/Project/os/hal/platforms/AT91SAM7/at91lib/aic.c new file mode 100644 index 0000000..66eebf9 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/at91lib/aic.c @@ -0,0 +1,84 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + * ---------------------------------------------------------------------------- + * Copyright (c) 2006, Atmel Corporation + + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaiimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "aic.h" +#include + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Configures the interrupt associated with the given source, using the +/// specified mode and interrupt handler. +/// \param source Interrupt source to configure. +/// \param mode Triggering mode of the interrupt. +/// \param handler Interrupt handler function. +//------------------------------------------------------------------------------ +void AIC_ConfigureIT(unsigned int source, + unsigned int mode, + void (*handler)( void )) +{ + // Disable the interrupt first + AT91C_BASE_AIC->AIC_IDCR = 1 << source; + + // Configure mode and handler + AT91C_BASE_AIC->AIC_SMR[source] = mode; + AT91C_BASE_AIC->AIC_SVR[source] = (unsigned int) handler; + + // Clear interrupt + AT91C_BASE_AIC->AIC_ICCR = 1 << source; +} + +//------------------------------------------------------------------------------ +/// Enables interrupts coming from the given (unique) source. +/// \param source Interrupt source to enable. +//------------------------------------------------------------------------------ +void AIC_EnableIT(unsigned int source) +{ + AT91C_BASE_AIC->AIC_IECR = 1 << source; +} + +//------------------------------------------------------------------------------ +/// Disables interrupts coming from the given (unique) source. +/// \param source Interrupt source to enable. +//------------------------------------------------------------------------------ +void AIC_DisableIT(unsigned int source) +{ + AT91C_BASE_AIC->AIC_IDCR = 1 << source; +} + diff --git a/Project/os/hal/platforms/AT91SAM7/at91lib/aic.h b/Project/os/hal/platforms/AT91SAM7/at91lib/aic.h new file mode 100644 index 0000000..e8e52c7 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/at91lib/aic.h @@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + * ---------------------------------------------------------------------------- + * Copyright (c) 2006, Atmel Corporation + + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaiimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \dir +/// !Purpose +/// +/// Methods and definitions for configuring interrupts using the Advanced +/// Interrupt Controller (AIC). +/// +/// !Usage +/// -# Configure an interrupt source using AIC_ConfigureIT +/// -# Enable or disable interrupt generation of a particular source with +/// AIC_EnableIT and AIC_DisableIT. +//------------------------------------------------------------------------------ + +#ifndef AIC_H +#define AIC_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +#ifndef AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL + /// Redefinition of missing constant. + #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE +#endif + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void AIC_ConfigureIT(unsigned int source, + unsigned int mode, + void (*handler)( void )); + +extern void AIC_EnableIT(unsigned int source); + +extern void AIC_DisableIT(unsigned int source); + +#endif //#ifndef AIC_H + diff --git a/Project/os/hal/platforms/AT91SAM7/at91sam7.h b/Project/os/hal/platforms/AT91SAM7/at91sam7.h new file mode 100644 index 0000000..a72d0f7 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/at91sam7.h @@ -0,0 +1,64 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +#ifndef _AT91SAM7_H_ +#define _AT91SAM7_H_ + +/* + * Supported platforms. + */ +#define SAM7S64 0 +#define SAM7S128 1 +#define SAM7S256 2 +#define SAM7S512 3 +#define SAM7X128 4 +#define SAM7X256 5 +#define SAM7X512 6 + +#ifndef SAM7_PLATFORM +#error "SAM7 platform not defined" +#endif + +#if SAM7_PLATFORM == SAM7S64 +#include "at91lib/AT91SAM7S64.h" +#elif SAM7_PLATFORM == SAM7S128 +#include "at91lib/AT91SAM7S128.h" +#elif SAM7_PLATFORM == SAM7S256 +#include "at91lib/AT91SAM7S256.h" +#elif SAM7_PLATFORM == SAM7S512 +#include "at91lib/AT91SAM7S512.h" +#elif SAM7_PLATFORM == SAM7X128 +#include "at91lib/AT91SAM7X128.h" +#elif SAM7_PLATFORM == SAM7X256 +#include "at91lib/AT91SAM7X256.h" +#elif SAM7_PLATFORM == SAM7X512 +#include "at91lib/AT91SAM7X512.h" +#else +#error "SAM7 platform not supported" +#endif + +#endif /* _AT91SAM7_H_ */ diff --git a/Project/os/hal/platforms/AT91SAM7/at91sam7_mii.c b/Project/os/hal/platforms/AT91SAM7/at91sam7_mii.c new file mode 100644 index 0000000..863220b --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/at91sam7_mii.c @@ -0,0 +1,155 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AT91SAM7/at91sam7_mii.c + * @brief AT91SAM7 low level MII driver code. + * + * @addtogroup AT91SAM7_MII + * @{ + */ + +#include "ch.h" +#include "hal.h" +#include "at91sam7_mii.h" + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level MII driver initialization. + * + * @notapi + */ +void miiInit(void) { + +} + +/** + * @brief Resets a PHY device. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void miiReset(MACDriver *macp) { + + (void)macp; + + /* + * Disables the pullups on all the pins that are latched on reset by the PHY. + */ + AT91C_BASE_PIOB->PIO_PPUDR = PHY_LATCHED_PINS; + +#ifdef PIOB_PHY_PD_MASK + /* + * PHY power control. + */ + AT91C_BASE_PIOB->PIO_OER = PIOB_PHY_PD_MASK; /* Becomes an output. */ + AT91C_BASE_PIOB->PIO_PPUDR = PIOB_PHY_PD_MASK;/* Default pullup disabled. */ +#if (PHY_HARDWARE == PHY_DAVICOM_9161) + AT91C_BASE_PIOB->PIO_CODR = PIOB_PHY_PD_MASK; /* Output to low level. */ +#else + AT91C_BASE_PIOB->PIO_SODR = PIOB_PHY_PD_MASK; /* Output to high level. */ +#endif +#endif + + /* + * PHY reset by pulsing the NRST pin. + */ + AT91C_BASE_RSTC->RSTC_RMR = 0xA5000100; + AT91C_BASE_RSTC->RSTC_RCR = 0xA5000000 | AT91C_RSTC_EXTRST; + while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL)) + ; +} + +/** + * @brief Reads a PHY register through the MII interface. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[in] addr the register address + * @return The register value. + * + * @notapi + */ +phyreg_t miiGet(MACDriver *macp, phyaddr_t addr) { + + (void)macp; + AT91C_BASE_EMAC->EMAC_MAN = (0b01 << 30) | /* SOF */ + (0b10 << 28) | /* RW */ + (PHY_ADDRESS << 23) | /* PHYA */ + (addr << 18) | /* REGA */ + (0b10 << 16); /* CODE */ + while (!( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE)) + ; + return (phyreg_t)(AT91C_BASE_EMAC->EMAC_MAN & 0xFFFF); +} + +/** + * @brief Writes a PHY register through the MII interface. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[in] addr the register address + * @param[in] value the new register value + * + * @notapi + */ +void miiPut(MACDriver *macp, phyaddr_t addr, phyreg_t value) { + + (void)macp; + AT91C_BASE_EMAC->EMAC_MAN = (0b01 << 30) | /* SOF */ + (0b01 << 28) | /* RW */ + (PHY_ADDRESS << 23) | /* PHYA */ + (addr << 18) | /* REGA */ + (0b10 << 16) | /* CODE */ + value; + while (!( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE)) + ; +} + +#endif /* HAL_USE_MAC */ + +/** @} */ diff --git a/Project/os/hal/platforms/AT91SAM7/at91sam7_mii.h b/Project/os/hal/platforms/AT91SAM7/at91sam7_mii.h new file mode 100644 index 0000000..d943e7e --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/at91sam7_mii.h @@ -0,0 +1,122 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AT91SAM7/at91sam7_mii.h + * @brief AT91SAM7 low level MII driver header. + * + * @addtogroup AT91SAM7_MII + * @{ + */ + +#ifndef _AT91SAM7_MII_H_ +#define _AT91SAM7_MII_H_ + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define PHY_MICREL_KS8721 0 +#define PHY_DAVICOM_9161 1 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief PHY manufacturer and model. + */ +#if !defined(PHY_HARDWARE) || defined(__DOXYGEN__) +#define PHY_HARDWARE PHY_MICREL_KS8721 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** + * @brief Pins latched by the PHY at reset. + */ +#if PHY_HARDWARE == PHY_MICREL_KS8721 +#define PHY_ADDRESS 1 +#define PHY_ID MII_KS8721_ID +#define PHY_LATCHED_PINS (AT91C_PB4_ECRS | AT91C_PB5_ERX0 | \ + AT91C_PB6_ERX1 | AT91C_PB7_ERXER | \ + AT91C_PB13_ERX2 | AT91C_PB14_ERX3 | \ + AT91C_PB15_ERXDV_ECRSDV | AT91C_PB16_ECOL | \ + AT91C_PIO_PB26) + +#elif PHY_HARDWARE == PHY_DAVICOM_9161 +#define PHY_ADDRESS 0 +#define PHY_ID MII_DM9161_ID +#define PHY_LATCHED_PINS (AT91C_PB0_ETXCK_EREFCK | AT91C_PB4_ECRS | \ + AT91C_PB5_ERX0 | AT91C_PB6_ERX1 | \ + AT91C_PB7_ERXER | AT91C_PB13_ERX2 | \ + AT91C_PB14_ERX3 | AT91C_PB15_ERXDV_ECRSDV | \ + AT91C_PB16_ECOL | AT91C_PB17_ERXCK) +#endif /* PHY_HARDWARE */ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a PHY register value. + */ +typedef uint16_t phyreg_t; + +/** + * @brief Type of a PHY register address. + */ +typedef uint8_t phyaddr_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void miiInit(void); + void miiReset(MACDriver *macp); + phyreg_t miiGet(MACDriver *macp, phyaddr_t addr); + void miiPut(MACDriver *macp, phyaddr_t addr, phyreg_t value); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_MAC */ + +#endif /* _AT91SAM7_MII_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/AT91SAM7/ext_lld.c b/Project/os/hal/platforms/AT91SAM7/ext_lld.c new file mode 100644 index 0000000..26dbb13 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/ext_lld.c @@ -0,0 +1,243 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AT91SAM7/ext_lld.c + * @brief AT91SAM7 EXT subsystem low level driver source. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EXTDA driver identifier. + */ +EXTDriver EXTDA; + +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) +/** + * @brief EXTDB driver identifier. + */ +EXTDriver EXTDB; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Handles external interrupts. + * + * @param[in] extp pointer to the driver that received the interrupt + */ +static void ext_lld_serveInterrupt(EXTDriver *extp) { + uint32_t irqFlags; + uint32_t ch; + + chSysLockFromIsr(); + + /* Read flags of pending PIO interrupts.*/ + irqFlags = extp->pio->PIO_ISR; + + /* Call callback function for any pending interrupt.*/ + for(ch = 0; ch < 32; ch++) { + + /* Check if the channel is activated and if its IRQ flag is set.*/ + if((extp->config->channels[ch].mode & + EXT_CH_MODE_ENABLED & EXT_CH_MODE_EDGES_MASK) + && ((1 << ch) & irqFlags)) { + (extp->config->channels[ch].cb)(extp, ch); + } + } + + chSysUnlockFromIsr(); + + AT91C_BASE_AIC->AIC_EOICR = 0; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief EXTI[0] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTIA_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + ext_lld_serveInterrupt(&EXTDA); + + CH_IRQ_EPILOGUE(); +} + +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) +/** + * @brief EXTI[1] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTIB_IRQHandler) { + CH_IRQ_PROLOGUE(); + + ext_lld_serveInterrupt(&EXTDB); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level EXT driver initialization. + * + * @notapi + */ +void ext_lld_init(void) { + + /* Driver initialization.*/ + extObjectInit(&EXTDA); + + /* Set PIO base addresses.*/ + EXTDA.pio = AT91C_BASE_PIOA; + + /* Set peripheral IDs.*/ + EXTDA.pid = AT91C_ID_PIOA; + +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) + /* Same for PIOB.*/ + extObjectInit(&EXTDB); + EXTDB.pio = AT91C_BASE_PIOB; + EXTDB.pid = AT91C_ID_PIOB; +#endif +} + +/** + * @brief Configures and activates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_start(EXTDriver *extp) { + uint16_t ch; + uint32_t ier = 0; + const EXTConfig *config = extp->config; + + switch(extp->pid) { + case AT91C_ID_PIOA: + AIC_ConfigureIT(AT91C_ID_PIOA, SAM7_computeSMR(config->mode, + config->priority), + EXTIA_IRQHandler); + break; +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) + case AT91C_ID_PIOB: + AIC_ConfigureIT(AT91C_ID_PIOB, SAM7_computeSMR(config->mode, + config->priority), + EXTIB_IRQHandler); + break; +#endif + } + + /* Enable and Disable channels with respect to config.*/ + for(ch = 0; ch < EXT_MAX_CHANNELS; ch++) { + ier |= (config->channels[ch].mode & EXT_CH_MODE_EDGES_MASK & EXT_CH_MODE_ENABLED ? 1 : 0) << ch; + } + extp->pio->PIO_IER = ier; + extp->pio->PIO_IDR = ~ier; + + /* Enable interrupt on corresponding PIO port in AIC.*/ + AIC_EnableIT(extp->pid); +} + +/** + * @brief Deactivates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_stop(EXTDriver *extp) { + + /* Disable interrupt on corresponding PIO port in AIC.*/ + AIC_DisableIT(extp->pid); +} + +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @notapi + */ +void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { + + extp->pio->PIO_IER = (1 << channel); +} + +/** + * @brief Disables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be disabled + * + * @notapi + */ +void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) { + + extp->pio->PIO_IDR = (1 << channel); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/Project/os/hal/platforms/AT91SAM7/ext_lld.h b/Project/os/hal/platforms/AT91SAM7/ext_lld.h new file mode 100644 index 0000000..a24c5a2 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/ext_lld.h @@ -0,0 +1,254 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AT91SAM7/ext_lld.h + * @brief AT91SAM7 EXT subsystem low level driver header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_H_ +#define _EXT_LLD_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Pointer to the SAM7 AIC register block. + */ +#define SAM7_EXT_AIC ((AT91PS_AIC *)AT91C_BASE_AIC) + +/** + * @brief Number of channels within one ext driver. + */ +#define EXT_MAX_CHANNELS 32 + +/** + * @brief Mask of priority bits in interrupt mode register. + */ +#define SAM7_EXT_PRIORITY_MASK 0x00000007 + +/** + * @brief Shifter for priority bits in interrupt mode register. + */ +#define SAM7_EXT_PRIORITY_SHIFTER 0 + +/** + * @brief Shifter for mode bits in interrupt mode register. + */ +#define SAM7_EXT_MODE_SHIFTER 5 + +/* + * On the SAM7 architecture, a single channel can only be enables or disabled + * Hence, undefine the other channel mode constants + */ +#ifdef EXT_CH_MODE_RISING_EDGE +#undef EXT_CH_MODE_RISING_EDGE +#endif + +#ifdef EXT_CH_MODE_FALLING_EDGE +#undef EXT_CH_MODE_FALLING_EDGE +#endif + +#ifdef EXT_CH_MODE_BOTH_EDGES +#undef EXT_CH_MODE_BOTH_EDGES +#endif + +/** + * @name EXT channels mode + * @{ + */ +#define EXT_CH_MODE_ENABLED 1 /**< @brief Channel is enabled. */ +/** @} */ + +/** + * @name EXT drivers mode + * @{ + */ +/** + * @brief Mask for modes. + */ +#define SAM7_EXT_MODE_MASK AT91C_AIC_SRCTYPE +/** + * @brief Falling edge callback. + */ +#define SAM7_EXT_MODE_FALLING_EDGE AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE +/** + * @brief Rising edge callback. + */ +#define SAM7_EXT_MODE_RISING_EDGE AT91C_AIC_SRCTYPE_POSITIVE_EDGE +/** + * @brief High-level callback. + */ +#define SAM7_EXT_MODE_HIGH_LEVEL AT91C_AIC_SRCTYPE_HIGH_LEVEL +/** + * @brief Low-level callback. + */ +#define SAM7_EXT_MODE_LOW_LEVEL AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL +/** @} */ + +/** + * @name EXT drivers priorities + * @{ + */ +#define SAM7_EXT_PRIOR_HIGHEST AT91C_AIC_PRIOR_HIGHEST +#define SAM7_EXT_PRIOR_LOWEST AT91C_AIC_PRIOR_LOWEST +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief EXT channel identifier. + */ +typedef uint32_t expchannel_t; + +/** + * @brief Type of an EXT generic notification callback. + * + * @param[in] extp pointer to the @p EXPDriver object triggering the + * callback + */ +typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); + +/** + * @brief Channel configuration structure. + */ +typedef struct { + /** + * @brief Channel mode. + */ + uint32_t mode; + /** + * @brief Channel callback. + * @details In the STM32 implementation a @p NULL callback pointer is + * valid and configures the channel as an event sources instead + * of an interrupt source. + */ + extcallback_t cb; +} EXTChannelConfig; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Channel configurations. + */ + EXTChannelConfig channels[EXT_MAX_CHANNELS]; + /* End of the mandatory fields.*/ + + /** + * @brief interrupt mode. + */ + uint32_t mode; + + /** + * @brief interrupt priority. + */ + uint32_t priority; +} EXTConfig; + +/** + * @brief Structure representing an EXT driver. + */ +struct EXTDriver { + /** + * @brief Driver state. + */ + extstate_t state; + /** + * @brief Current configuration data. + */ + const EXTConfig *config; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the corresponding PIO registers block. + */ + AT91PS_PIO pio; + /** + * @brief peripheral ID of the corresponding PIO block. + */ + uint32_t pid; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Computes the content for the interrupt source mode register. + */ +#define SAM7_computeSMR(mode, prio) ( \ + ((mode & SAM7_EXT_MODE_MASK) << SAM7_EXT_MODE_SHIFTER) | \ + ((prio & SAM7_EXT_PRIORITY_MASK) << SAM7_EXT_PRIORITY_SHIFTER) \ +) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern EXTDriver EXTDA; +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) +extern EXTDriver EXTDB; +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_init(void); + void ext_lld_start(EXTDriver *extp); + void ext_lld_stop(EXTDriver *extp); + void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); + void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/AT91SAM7/hal_lld.c b/Project/os/hal/platforms/AT91SAM7/hal_lld.c new file mode 100644 index 0000000..346af35 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/hal_lld.c @@ -0,0 +1,140 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AT91SAM7/hal_lld.c + * @brief AT91SAM7 HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +static CH_IRQ_HANDLER(spurious_handler) { + + CH_IRQ_PROLOGUE(); + + AT91SAM7_SPURIOUS_HANDLER_HOOK(); + + AT91C_BASE_AIC->AIC_EOICR = 0; + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + unsigned i; + + /* FIQ Handler weak symbol defined in vectors.s.*/ + void FiqHandler(void); + + /* Default AIC setup, the device drivers will modify it as needed.*/ + AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF; + AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF; + AT91C_BASE_AIC->AIC_SVR[0] = (AT91_REG)FiqHandler; + for (i = 1; i < 31; i++) { + AT91C_BASE_AIC->AIC_SVR[i] = (AT91_REG)NULL; + AT91C_BASE_AIC->AIC_EOICR = (AT91_REG)i; + } + AT91C_BASE_AIC->AIC_SPU = (AT91_REG)spurious_handler; + +} + +/** + * @brief AT91SAM7 clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function must be invoked only after the system reset. + * + * @special + */ +void at91sam7_clock_init(void) { + + /* wait for reset */ + while((AT91C_BASE_RSTC->RSTC_RSR & (AT91C_RSTC_SRCMP | AT91C_RSTC_NRSTL)) != AT91C_RSTC_NRSTL) + ; + /* enable reset */ + AT91C_BASE_RSTC->RSTC_RMR = ((0xA5 << 24) | AT91C_RSTC_URSTEN); + + /* Flash Memory: 1 wait state, about 50 cycles in a microsecond.*/ +#if SAM7_PLATFORM == SAM7X512 + AT91C_BASE_MC->MC0_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS; + AT91C_BASE_MC->MC1_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS; +#else + AT91C_BASE_MC->MC_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS; +#endif + + /* Enables the main oscillator and waits 56 slow cycles as startup time.*/ + AT91C_BASE_PMC->PMC_MOR = (AT91C_CKGR_OSCOUNT & (7 << 8)) | AT91C_CKGR_MOSCEN; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)) + ; + + /* PLL setup: DIV = 14, MUL = 72, PLLCOUNT = 10 + PLLfreq = 96109714 Hz (rounded).*/ + AT91C_BASE_PMC->PMC_PLLR = (AT91C_CKGR_DIV & 14) | + (AT91C_CKGR_PLLCOUNT & (10 << 8)) | + (AT91SAM7_USBDIV) | + (AT91C_CKGR_MUL & (72 << 16)); + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK)) + ; + + /* Master clock = PLLfreq / 2 = 48054858 Hz (rounded).*/ + AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) + ; + + AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) + ; +} + +/** @} */ diff --git a/Project/os/hal/platforms/AT91SAM7/hal_lld.h b/Project/os/hal/platforms/AT91SAM7/hal_lld.h new file mode 100644 index 0000000..49a4e25 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/hal_lld.h @@ -0,0 +1,101 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AT91SAM7/hal_lld.h + * @brief AT91SAM7 HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "at91sam7.h" +#include "at91lib/aic.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "AT91SAM7x" + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Default action for the spurious handler, nothing. + */ +#if !defined(AT91SAM7_SPURIOUS_HANDLER_HOOK) || defined(__DOXYGEN__) +#define AT91SAM7_SPURIOUS_HANDLER_HOOK() +#endif + +/** + * @brief Default divider for the USB clock - half the PLL clock. + */ +#if !defined(AT91SAM7_USBDIV) || defined(__DOXYGEN__) +#define AT91SAM7_USBDIV AT91C_CKGR_USBDIV_1 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void at91sam7_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/AT91SAM7/mac_lld.c b/Project/os/hal/platforms/AT91SAM7/mac_lld.c new file mode 100644 index 0000000..a0907a6 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/mac_lld.c @@ -0,0 +1,562 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AT91SAM7/mac_lld.c + * @brief AT91SAM7 low level MAC driver code. + * + * @addtogroup MAC + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" +#include "mii.h" +#include "at91sam7_mii.h" + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +#define EMAC_PIN_MASK (AT91C_PB0_ETXCK_EREFCK | AT91C_PB1_ETXEN | \ + AT91C_PB2_ETX0 | AT91C_PB3_ETX1 | \ + AT91C_PB4_ECRS | AT91C_PB5_ERX0 | \ + AT91C_PB6_ERX1 | AT91C_PB7_ERXER | \ + AT91C_PB8_EMDC | AT91C_PB9_EMDIO | \ + AT91C_PB10_ETX2 | AT91C_PB11_ETX3 | \ + AT91C_PB12_ETXER | AT91C_PB13_ERX2 | \ + AT91C_PB14_ERX3 | AT91C_PB15_ERXDV_ECRSDV | \ + AT91C_PB16_ECOL | AT91C_PB17_ERXCK) + +#define RSR_BITS (AT91C_EMAC_BNA | AT91C_EMAC_REC | AT91C_EMAC_OVR) + +#define TSR_BITS (AT91C_EMAC_UBR | AT91C_EMAC_COL | AT91C_EMAC_RLES | \ + AT91C_EMAC_BEX | AT91C_EMAC_COMP | AT91C_EMAC_UND) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief Ethernet driver 1. + */ +MACDriver ETHD1; + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +#ifndef __DOXYGEN__ + +static uint8_t default_mac[] = {0xAA, 0x55, 0x13, 0x37, 0x01, 0x10}; + +static EMACDescriptor *rxptr; +static EMACDescriptor *txptr; +static EMACDescriptor rd[EMAC_RECEIVE_DESCRIPTORS] + __attribute__((aligned(8))); +static EMACDescriptor td[EMAC_TRANSMIT_DESCRIPTORS] + __attribute__((aligned(8))); +static uint8_t rb[EMAC_RECEIVE_DESCRIPTORS * EMAC_RECEIVE_BUFFERS_SIZE] + __attribute__((aligned(8))); +static uint8_t tb[EMAC_TRANSMIT_DESCRIPTORS * EMAC_TRANSMIT_BUFFERS_SIZE] + __attribute__((aligned(8))); +#endif + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief IRQ handler. + */ +/** @cond never*/ +__attribute__((noinline)) +/** @endcond*/ +static void serve_interrupt(void) { + uint32_t isr, rsr, tsr; + + /* Fix for the EMAC errata */ + isr = AT91C_BASE_EMAC->EMAC_ISR; + rsr = AT91C_BASE_EMAC->EMAC_RSR; + tsr = AT91C_BASE_EMAC->EMAC_TSR; + + if ((isr & AT91C_EMAC_RCOMP) || (rsr & RSR_BITS)) { + if (rsr & AT91C_EMAC_REC) { + chSysLockFromIsr(); + chSemResetI(ÐD1.rdsem, 0); +#if MAC_USE_EVENTS + chEvtBroadcastI(ÐD1.rdevent); +#endif + chSysUnlockFromIsr(); + } + AT91C_BASE_EMAC->EMAC_RSR = RSR_BITS; + } + + if ((isr & AT91C_EMAC_TCOMP) || (tsr & TSR_BITS)) { + if (tsr & AT91C_EMAC_COMP) { + chSysLockFromIsr(); + chSemResetI(ÐD1.tdsem, 0); + chSysUnlockFromIsr(); + } + AT91C_BASE_EMAC->EMAC_TSR = TSR_BITS; + } + AT91C_BASE_AIC->AIC_EOICR = 0; +} + +/** + * @brief Cleans an incomplete frame. + * + * @param[in] from the start position of the incomplete frame + */ +static void cleanup(EMACDescriptor *from) { + + while (from != rxptr) { + from->w1 &= ~W1_R_OWNERSHIP; + if (++from >= &rd[EMAC_RECEIVE_DESCRIPTORS]) + from = rd; + } +} + +/** + * @brief MAC address setup. + * + * @param[in] p pointer to a six bytes buffer containing the MAC + * address + */ +static void set_address(const uint8_t *p) { + + AT91C_BASE_EMAC->EMAC_SA1L = (AT91_REG)((p[3] << 24) | (p[2] << 16) | + (p[1] << 8) | p[0]); + AT91C_BASE_EMAC->EMAC_SA1H = (AT91_REG)((p[5] << 8) | p[4]); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief EMAC IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(irq_handler) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(); + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level MAC initialization. + * + * @notapi + */ +void mac_lld_init(void) { + + miiInit(); + macObjectInit(ÐD1); + + /* + * Associated PHY initialization. + */ + miiReset(ÐD1); + + /* + * EMAC pins setup. Note, PB18 is not included because it is + * used as #PD control and not as EF100. + */ + AT91C_BASE_PIOB->PIO_ASR = EMAC_PIN_MASK; + AT91C_BASE_PIOB->PIO_PDR = EMAC_PIN_MASK; + AT91C_BASE_PIOB->PIO_PPUDR = EMAC_PIN_MASK; +} + +/** + * @brief Configures and activates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_start(MACDriver *macp) { + unsigned i; + + /* + * Buffers initialization. + */ + for (i = 0; i < EMAC_RECEIVE_DESCRIPTORS; i++) { + rd[i].w1 = (uint32_t)&rb[i * EMAC_RECEIVE_BUFFERS_SIZE]; + rd[i].w2 = 0; + } + rd[EMAC_RECEIVE_DESCRIPTORS - 1].w1 |= W1_R_WRAP; + rxptr = rd; + for (i = 0; i < EMAC_TRANSMIT_DESCRIPTORS; i++) { + td[i].w1 = (uint32_t)&tb[i * EMAC_TRANSMIT_BUFFERS_SIZE]; + td[i].w2 = EMAC_TRANSMIT_BUFFERS_SIZE | W2_T_LAST_BUFFER | W2_T_USED; + } + td[EMAC_TRANSMIT_DESCRIPTORS - 1].w2 |= W2_T_WRAP; + txptr = td; + + /* + * EMAC clock enable. + */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC; + + /* + * EMAC Initial setup. + */ + AT91C_BASE_EMAC->EMAC_NCR = 0; /* Stopped but MCE active.*/ + AT91C_BASE_EMAC->EMAC_NCFGR = 2 << 10; /* MDC-CLK = MCK / 32 */ + AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN;/* Enable EMAC in MII mode.*/ + AT91C_BASE_EMAC->EMAC_RBQP = (AT91_REG)rd; /* RX descriptors list.*/ + AT91C_BASE_EMAC->EMAC_TBQP = (AT91_REG)td; /* TX descriptors list.*/ + AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_OVR | + AT91C_EMAC_REC | + AT91C_EMAC_BNA; /* Clears RSR.*/ + AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_DRFCS;/* Initial NCFGR settings.*/ + AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TE | + AT91C_EMAC_RE | + AT91C_EMAC_CLRSTAT;/* Initial NCR settings.*/ + if (macp->config->mac_address == NULL) + set_address(default_mac); + else + set_address(macp->config->mac_address); + + /* + * PHY device identification. + */ + AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE; + if ((miiGet(ÐD1, MII_PHYSID1) != (PHY_ID >> 16)) || + ((miiGet(ÐD1, MII_PHYSID2) & 0xFFF0) != (PHY_ID & 0xFFF0))) + chSysHalt(); + AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE; + + /* + * Interrupt configuration. + */ + AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP | AT91C_EMAC_TCOMP; + AIC_ConfigureIT(AT91C_ID_EMAC, + AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | EMAC_INTERRUPT_PRIORITY, + irq_handler); + AIC_EnableIT(AT91C_ID_EMAC); +} + +/** + * @brief Deactivates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_stop(MACDriver *macp) { + + (void)macp; +} + +/** + * @brief Returns a transmission descriptor. + * @details One of the available transmission descriptors is locked and + * returned. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] tdp pointer to a @p MACTransmitDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp) { + EMACDescriptor *edp; + + (void)macp; + + if (!macp->link_up) + return RDY_TIMEOUT; + + chSysLock(); + edp = txptr; + if (!(edp->w2 & W2_T_USED) || (edp->w2 & W2_T_LOCKED)) { + chSysUnlock(); + return RDY_TIMEOUT; + } + /* + * Set the buffer size and configuration, the buffer is also marked + * as locked. + */ + if (++txptr >= &td[EMAC_TRANSMIT_DESCRIPTORS]) { + edp->w2 = W2_T_LOCKED | W2_T_USED | W2_T_LAST_BUFFER | W2_T_WRAP; + txptr = td; + } + else + edp->w2 = W2_T_LOCKED | W2_T_USED | W2_T_LAST_BUFFER; + chSysUnlock(); + tdp->offset = 0; + tdp->size = EMAC_TRANSMIT_BUFFERS_SIZE; + tdp->physdesc = edp; + return RDY_OK; +} + +/** + * @brief Writes to a transmit descriptor's stream. + * + * @param[in] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] buf pointer to the buffer containing the data to be + * written + * @param[in] size number of bytes to be written + * @return The number of bytes written into the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if the maximum + * frame size is reached. + * + * @notapi + */ +size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size) { + + if (size > tdp->size - tdp->offset) + size = tdp->size - tdp->offset; + if (size > 0) { + memcpy((uint8_t *)(tdp->physdesc->w1 & W1_T_ADDRESS_MASK) + + tdp->offset, + buf, size); + tdp->offset += size; + } + return size; +} + +/** + * @brief Releases a transmit descriptor and starts the transmission of the + * enqueued data as a single frame. + * + * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure + * + * @notapi + */ +void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) { + + chSysLock(); + tdp->physdesc->w2 = (tdp->physdesc->w2 & + ~(W2_T_LOCKED | W2_T_USED | W2_T_LENGTH_MASK)) | + tdp->offset; + AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART; + chSysUnlock(); +} + +/** + * @brief Returns a receive descriptor. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] rdp pointer to a @p MACReceiveDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t mac_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp) { + unsigned n; + EMACDescriptor *edp; + + (void)macp; + n = EMAC_RECEIVE_DESCRIPTORS; + + /* + * Skips unused buffers, if any. + */ +skip: + while ((n > 0) && !(rxptr->w1 & W1_R_OWNERSHIP)) { + if (++rxptr >= &rd[EMAC_RECEIVE_DESCRIPTORS]) + rxptr = rd; + n--; + } + + /* + * Skips fragments, if any, cleaning them up. + */ + while ((n > 0) && (rxptr->w1 & W1_R_OWNERSHIP) && + !(rxptr->w2 & W2_R_FRAME_START)) { + rxptr->w1 &= ~W1_R_OWNERSHIP; + if (++rxptr >= &rd[EMAC_RECEIVE_DESCRIPTORS]) + rxptr = rd; + n--; + } + + /* + * Now compute the total frame size skipping eventual incomplete frames + * or holes... + */ +restart: + edp = rxptr; + while (n > 0) { + if (!(rxptr->w1 & W1_R_OWNERSHIP)) { + /* Empty buffer for some reason... cleaning up the incomplete frame.*/ + cleanup(edp); + goto skip; + } + /* + * End Of Frame found. + */ + if (rxptr->w2 & W2_R_FRAME_END) { + rdp->offset = 0; + rdp->size = rxptr->w2 & W2_T_LENGTH_MASK; + rdp->physdesc = edp; + return RDY_OK; + } + + if ((edp != rxptr) && (rxptr->w2 & W2_R_FRAME_START)) { + /* Found another start... cleaning up the incomplete frame.*/ + cleanup(edp); + goto restart; /* Another start buffer for some reason... */ + } + + if (++rxptr >= &rd[EMAC_RECEIVE_DESCRIPTORS]) + rxptr = rd; + n--; + } + return RDY_TIMEOUT; +} + +/** + * @brief Reads from a receive descriptor's stream. + * + * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[in] buf pointer to the buffer that will receive the read data + * @param[in] size number of bytes to be read + * @return The number of bytes read from the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if there are + * no more bytes to read. + * + * @notapi + */ +size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size) { + if (size > rdp->size - rdp->offset) + size = rdp->size - rdp->offset; + if (size > 0) { + uint8_t *src = (uint8_t *)(rdp->physdesc->w1 & W1_R_ADDRESS_MASK) + + rdp->offset; + uint8_t *limit = &rb[EMAC_RECEIVE_DESCRIPTORS * EMAC_RECEIVE_BUFFERS_SIZE]; + if (src >= limit) + src -= EMAC_RECEIVE_DESCRIPTORS * EMAC_RECEIVE_BUFFERS_SIZE; + if (src + size > limit ) { + memcpy(buf, src, (size_t)(limit - src)); + memcpy(buf + (size_t)(limit - src), rb, size - (size_t)(limit - src)); + } + else + memcpy(buf, src, size); + rdp->offset += size; + } + return size; +} + +/** + * @brief Releases a receive descriptor. + * @details The descriptor and its buffer are made available for more incoming + * frames. + * + * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure + * + * @notapi + */ +void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) { + bool_t done; + EMACDescriptor *edp = rdp->physdesc; + + unsigned n = EMAC_RECEIVE_DESCRIPTORS; + do { + done = ((edp->w2 & W2_R_FRAME_END) != 0); + chDbgAssert(edp->w1 & W1_R_OWNERSHIP, + "mac_lld_release_receive_descriptor(), #1", + "found not owned descriptor"); + edp->w1 &= ~(W1_R_OWNERSHIP | W2_R_FRAME_START | W2_R_FRAME_END); + if (++edp >= &rd[EMAC_RECEIVE_DESCRIPTORS]) + edp = rd; + n--; + } + while ((n > 0) && !done); + /* + * Make rxptr point to the descriptor where the next frame will most + * likely appear. + */ + rxptr = edp; +} + +/** + * @brief Updates and returns the link status. + * + * @param[in] macp pointer to the @p MACDriver object + * @return The link status. + * @retval TRUE if the link is active. + * @retval FALSE if the link is down. + * + * @notapi + */ +bool_t mac_lld_poll_link_status(MACDriver *macp) { + uint32_t ncfgr, bmsr, bmcr, lpa; + + AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE; + (void)miiGet(macp, MII_BMSR); + bmsr = miiGet(macp, MII_BMSR); + if (!(bmsr & BMSR_LSTATUS)) { + AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE; + return macp->link_up = FALSE; + } + + ncfgr = AT91C_BASE_EMAC->EMAC_NCFGR & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); + bmcr = miiGet(macp, MII_BMCR); + if (bmcr & BMCR_ANENABLE) { + lpa = miiGet(macp, MII_LPA); + if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4)) + ncfgr |= AT91C_EMAC_SPD; + if (lpa & (LPA_10FULL | LPA_100FULL)) + ncfgr |= AT91C_EMAC_FD; + } + else { + if (bmcr & BMCR_SPEED100) + ncfgr |= AT91C_EMAC_SPD; + if (bmcr & BMCR_FULLDPLX) + ncfgr |= AT91C_EMAC_FD; + } + AT91C_BASE_EMAC->EMAC_NCFGR = ncfgr; + AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE; + return macp->link_up = TRUE; +} + +#endif /* HAL_USE_MAC */ + +/** @} */ diff --git a/Project/os/hal/platforms/AT91SAM7/mac_lld.h b/Project/os/hal/platforms/AT91SAM7/mac_lld.h new file mode 100644 index 0000000..494eb06 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/mac_lld.h @@ -0,0 +1,258 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AT91SAM7/mac_lld.h + * @brief AT91SAM7 low level MAC driver header. + * + * @addtogroup MAC + * @{ + */ + +#ifndef _MAC_LLD_H_ +#define _MAC_LLD_H_ + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define EMAC_RECEIVE_BUFFERS_SIZE 128 /* Do not modify */ +#define EMAC_TRANSMIT_BUFFERS_SIZE MAC_BUFFERS_SIZE +#define EMAC_RECEIVE_DESCRIPTORS \ + (((((MAC_BUFFERS_SIZE - 1) | (EMAC_RECEIVE_BUFFERS_SIZE - 1)) + 1) \ + / EMAC_RECEIVE_BUFFERS_SIZE) * MAC_RECEIVE_BUFFERS) +#define EMAC_TRANSMIT_DESCRIPTORS MAC_TRANSMIT_BUFFERS + +#define W1_R_OWNERSHIP 0x00000001 +#define W1_R_WRAP 0x00000002 +#define W1_R_ADDRESS_MASK 0xFFFFFFFC + +#define W2_R_LENGTH_MASK 0x00000FFF +#define W2_R_FRAME_START 0x00004000 +#define W2_R_FRAME_END 0x00008000 +#define W2_R_CFI 0x00010000 +#define W2_R_VLAN_PRIO_MASK 0x000E0000 +#define W2_R_PRIO_TAG_DETECTED 0x00100000 +#define W2_R_VLAN_TAG_DETECTED 0x00200000 +#define W2_R_TYPE_ID_MATCH 0x00400000 +#define W2_R_ADDR4_MATCH 0x00800000 +#define W2_R_ADDR3_MATCH 0x01000000 +#define W2_R_ADDR2_MATCH 0x02000000 +#define W2_R_ADDR1_MATCH 0x04000000 +#define W2_R_RFU1 0x08000000 +#define W2_R_ADDR_EXT_MATCH 0x10000000 +#define W2_R_UNICAST_MATCH 0x20000000 +#define W2_R_MULTICAST_MATCH 0x40000000 +#define W2_R_BROADCAST_DETECTED 0x80000000 + +#define W1_T_ADDRESS_MASK 0xFFFFFFFF + +#define W2_T_LENGTH_MASK 0x000007FF +#define W2_T_LOCKED 0x00000800 /* Not an EMAC flag. */ +#define W2_T_RFU1 0x00003000 +#define W2_T_LAST_BUFFER 0x00008000 +#define W2_T_NO_CRC 0x00010000 +#define W2_T_RFU2 0x07FE0000 +#define W2_T_BUFFERS_EXHAUSTED 0x08000000 +#define W2_T_TRANSMIT_UNDERRUN 0x10000000 +#define W2_T_RETRY_LIMIT_EXC 0x20000000 +#define W2_T_WRAP 0x40000000 +#define W2_T_USED 0x80000000 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Number of available transmit buffers. + */ +#if !defined(MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__) +#define MAC_TRANSMIT_BUFFERS 2 +#endif + +/** + * @brief Number of available receive buffers. + */ +#if !defined(MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__) +#define MAC_RECEIVE_BUFFERS 2 +#endif + +/** + * @brief Maximum supported frame size. + */ +#if !defined(MAC_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define MAC_BUFFERS_SIZE 1518 +#endif + +/** + * @brief Interrupt priority level for the EMAC device. + */ +#if !defined(EMAC_INTERRUPT_PRIORITY) || defined(__DOXYGEN__) +#define EMAC_INTERRUPT_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 3) +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Structure representing a buffer physical descriptor. + * @note It represents both descriptor types. + */ +typedef struct { + uint32_t w1; + uint32_t w2; +} EMACDescriptor; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief MAC address. + */ + uint8_t *mac_address; + /* End of the mandatory fields.*/ +} MACConfig; + +/** + * @brief Structure representing a MAC driver. + */ +struct MACDriver { + /** + * @brief Driver state. + */ + macstate_t state; + /** + * @brief Current configuration data. + */ + const MACConfig *config; + /** + * @brief Transmit semaphore. + */ + Semaphore tdsem; + /** + * @brief Receive semaphore. + */ + Semaphore rdsem; +#if MAC_USE_EVENTS || defined(__DOXYGEN__) + /** + * @brief Receive event. + */ + EventSource rdevent; +#endif + /* End of the mandatory fields.*/ + /** + * @brief Link status flag. + */ + bool_t link_up; +}; + +/** + * @brief Structure representing a transmit descriptor. + */ +typedef struct { + /** + * @brief Current write offset. + */ + size_t offset; + /** + * @brief Available space size. + */ + size_t size; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the physical descriptor. + */ + EMACDescriptor *physdesc; +} MACTransmitDescriptor; + +/** + * @brief Structure representing a receive descriptor. + */ +typedef struct { + /** + * @brief Current read offset. + */ + size_t offset; + /** + * @brief Available data size. + */ + size_t size; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the first descriptor of the buffers chain. + */ + EMACDescriptor *physdesc; +} MACReceiveDescriptor; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern MACDriver ETHD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void mac_lld_init(void); + void mac_lld_start(MACDriver *macp); + void mac_lld_stop(MACDriver *macp); + msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp); + size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size); + void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp); + msg_t mac_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp); + size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size); + void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp); + bool_t mac_lld_poll_link_status(MACDriver *macp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_MAC */ + +#endif /* _MAC_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/AT91SAM7/pal_lld.c b/Project/os/hal/platforms/AT91SAM7/pal_lld.c new file mode 100644 index 0000000..24bfef0 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/pal_lld.c @@ -0,0 +1,161 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AT91SAM7/pal_lld.c + * @brief AT91SAM7 PIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief AT91SAM7 I/O ports configuration. + * @details PIO registers initialization. + * + * @param[in] config the AT91SAM7 ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + uint32_t ports = (1 << AT91C_ID_PIOA); +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) + ports |= (1 << AT91C_ID_PIOB); +#endif + AT91C_BASE_PMC->PMC_PCER = ports; + + /* + * PIOA setup. + */ + AT91C_BASE_PIOA->PIO_PPUER = config->P0Data.pusr; /* Pull-up as spec.*/ + AT91C_BASE_PIOA->PIO_PPUDR = ~config->P0Data.pusr; + AT91C_BASE_PIOA->PIO_PER = 0xFFFFFFFF; /* PIO enabled.*/ + AT91C_BASE_PIOA->PIO_ODSR = config->P0Data.odsr; /* Data as specified.*/ + AT91C_BASE_PIOA->PIO_OER = config->P0Data.osr; /* Dir. as specified.*/ + AT91C_BASE_PIOA->PIO_ODR = ~config->P0Data.osr; + AT91C_BASE_PIOA->PIO_IFDR = 0xFFFFFFFF; /* Filter disabled.*/ + AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF; /* Int. disabled.*/ + AT91C_BASE_PIOA->PIO_MDDR = 0xFFFFFFFF; /* Push Pull drive.*/ + AT91C_BASE_PIOA->PIO_ASR = 0xFFFFFFFF; /* Peripheral A.*/ + AT91C_BASE_PIOA->PIO_OWER = 0xFFFFFFFF; /* Write enabled.*/ + + /* + * PIOB setup. + */ +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) + AT91C_BASE_PIOB->PIO_PPUER = config->P1Data.pusr; /* Pull-up as spec.*/ + AT91C_BASE_PIOB->PIO_PPUDR = ~config->P1Data.pusr; + AT91C_BASE_PIOB->PIO_PER = 0xFFFFFFFF; /* PIO enabled.*/ + AT91C_BASE_PIOB->PIO_ODSR = config->P1Data.odsr; /* Data as specified.*/ + AT91C_BASE_PIOB->PIO_OER = config->P1Data.osr; /* Dir. as specified.*/ + AT91C_BASE_PIOB->PIO_ODR = ~config->P1Data.osr; + AT91C_BASE_PIOB->PIO_IFDR = 0xFFFFFFFF; /* Filter disabled.*/ + AT91C_BASE_PIOB->PIO_IDR = 0xFFFFFFFF; /* Int. disabled.*/ + AT91C_BASE_PIOB->PIO_MDDR = 0xFFFFFFFF; /* Push Pull drive.*/ + AT91C_BASE_PIOB->PIO_ASR = 0xFFFFFFFF; /* Peripheral A.*/ + AT91C_BASE_PIOB->PIO_OWER = 0xFFFFFFFF; /* Write enabled.*/ +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note This function is not meant to be invoked directly from the + * application code. + * @note @p PAL_MODE_RESET is implemented as input with pull-up. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with + * high state. + * @note @p PAL_MODE_OUTPUT_OPENDRAIN also enables the pull-up resistor. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT_PULLUP: + port->PIO_PPUER = mask; + port->PIO_ODR = mask; + break; + case PAL_MODE_INPUT: + case PAL_MODE_INPUT_ANALOG: + port->PIO_PPUDR = mask; + port->PIO_ODR = mask; + break; + case PAL_MODE_UNCONNECTED: + port->PIO_SODR = mask; + /* Falls in */ + case PAL_MODE_OUTPUT_PUSHPULL: + port->PIO_PPUDR = mask; + port->PIO_OER = mask; + port->PIO_MDDR = mask; + break; + case PAL_MODE_OUTPUT_OPENDRAIN: + port->PIO_PPUER = mask; + port->PIO_OER = mask; + port->PIO_MDER = mask; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/AT91SAM7/pal_lld.h b/Project/os/hal/platforms/AT91SAM7/pal_lld.h new file mode 100644 index 0000000..e710b87 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/pal_lld.h @@ -0,0 +1,265 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AT91SAM7/pal_lld.h + * @brief AT91SAM7 PIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLDOWN + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief PIO port setup info. + */ +typedef struct { + /** Initial value for ODSR register (data).*/ + uint32_t odsr; + /** Initial value for OSR register (direction).*/ + uint32_t osr; + /** Initial value for PUSR register (Pull-ups).*/ + uint32_t pusr; +} at91sam7_pio_setup_t; + +/** + * @brief AT91SAM7 PIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialize the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { + /** @brief Port 0 setup data.*/ + at91sam7_pio_setup_t P0Data; +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) || defined(__DOXYGEN__) + /** @brief Port 1 setup data.*/ + at91sam7_pio_setup_t P1Data; +#endif +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 32 + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef AT91PS_PIO ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief PIO port A identifier. + */ +#define IOPORT1 AT91C_BASE_PIOA + +/** + * @brief PIO port B identifier. + */ +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) || defined(__DOXYGEN__) +#define IOPORT2 AT91C_BASE_PIOB +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * @details This function is implemented by reading the PIO_PDSR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->PIO_PDSR) + +/** + * @brief Reads the output latch. + * @details This function is implemented by reading the PIO_ODSR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->PIO_ODSR) + +/** + * @brief Writes a bits mask on a I/O port. + * @details This function is implemented by writing the PIO_ODSR register, the + * implementation has no side effects. + * + * @param[in] port the port identifier + * @param[in] bits the bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->PIO_ODSR = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @details This function is implemented by writing the PIO_SODR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) ((port)->PIO_SODR = (bits)) + +/** + * @brief Clears a bits mask on a I/O port. + * @details This function is implemented by writing the PIO_CODR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) ((port)->PIO_CODR = (bits)) + +/** + * @brief Writes a group of bits. + * @details This function is implemented by writing the PIO_OWER, PIO_ODSR and + * PIO_OWDR registers, the implementation is not atomic because the + * multiple accesses. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset the group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group + * width are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + ((port)->PIO_OWER = (mask) << (offset), \ + (port)->PIO_ODSR = (bits) << (offset), \ + (port)->PIO_OWDR = (mask) << (offset)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with + * high state. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) + +extern const PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/AT91SAM7/platform.dox b/Project/os/hal/platforms/AT91SAM7/platform.dox new file mode 100644 index 0000000..b4414b4 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/platform.dox @@ -0,0 +1,147 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup AT91SAM7 AT91SAM7 Drivers + * @details This section describes all the supported drivers on the AT91SAM7 + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup AT91SAM7_HAL AT91SAM7 Initialization Support + * @details The AT91SAM7 HAL support is responsible for system initialization. + * + * @section at91sam7_hal_1 Supported HW resources + * - MC. + * - PMC. + * . + * @section at91sam7_hal_2 AT91SAM7 HAL driver implementation features + * - PLLs startup and stabilization. + * - Clock source selection. + * - Flash wait states. + * . +* @ingroup AT91SAM7 + */ + +/** + * @defgroup AT91SAM7_MAC AT91SAM7 MAC Support + * @details The AT91SAM7 MAC driver supports the EMAC peripheral. + * + * @section at91sam7_mac_1 Supported HW resources + * - EMAC. + * . + * @ingroup AT91SAM7 + */ + +/** + * @defgroup AT91SAM7_MII AT91SAM7 MII Support + * @details This driver supports the AT91SAM7 EMAC peripheral communicating + * with an external PHY transceiver. The driver currently supports + * the Micrel KS8721 PHY and the Davicom DV9161 modules. This driver + * is used internally by the MAC driver. + * + * @ingroup AT91SAM7 + */ + +/** + * @defgroup AT91SAM7_PAL AT91SAM7 PAL Support + * @details The AT91SAM7 PAL driver supports the PIO peripherals. + * + * @section at91sam7_pal_1 Supported HW resources + * - PIOA. + * - PIOB. + * . + * @section at91sam7_pal_2 AT91SAM7 PAL driver implementation features + * The PAL driver implementation fully supports the following hardware + * capabilities: + * - 32 bits wide ports. + * - Atomic set/reset functions. + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section at91sam7_pal_3 Supported PAL setup modes + * The AT91SAM7 PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_ANALOG (same as @p PAL_MODE_INPUT). + * - @p PAL_MODE_INPUT_PULLUP. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * - @p PAL_MODE_OUTPUT_OPENDRAIN. + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section at91sam7_pal_4 Suboptimal behavior + * The AT91SAM7 PIO is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Pad/port toggling operations are not atomic. + * - Pad/group mode setup is not atomic. + * . + * @ingroup AT91SAM7 + */ + +/** + * @defgroup AT91SAM7_SERIAL AT91SAM7 Serial Support + * @details The AT91SAM7 Serial driver uses the USART/UART peripherals in a + * buffered, interrupt driven, implementation. + * + * @section at91sam7_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - USART1. + * - USART2. + * - DBGU. + * . + * @section at91sam7_serial_2 AT91SAM7 Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each USART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * - Programmable priority levels for each USART. + * . + * @ingroup AT91SAM7 + */ + +/** + * @defgroup AT91SAM7_SPI AT91SAM7 SPI Support + * @details The SPI driver supports the AT91SAM7 SPI peripherals using DMA + * channels for maximum performance. + * + * @section at91sam7_spi_1 Supported HW resources + * - SPI1. + * - SPI2. + * . + * @section at91sam7_spi_2 AT91SAM7 SPI driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each SPI can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable interrupt priority levels for each SPI. + * - DMA is used for receiving and transmitting. + * . + * @ingroup AT91SAM7 + */ diff --git a/Project/os/hal/platforms/AT91SAM7/platform.mk b/Project/os/hal/platforms/AT91SAM7/platform.mk new file mode 100644 index 0000000..83b5349 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/platform.mk @@ -0,0 +1,12 @@ +# List of all the AT91SAM7 platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/AT91SAM7/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/AT91SAM7/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/AT91SAM7/ext_lld.c \ + ${CHIBIOS}/os/hal/platforms/AT91SAM7/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/AT91SAM7/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/AT91SAM7/mac_lld.c \ + ${CHIBIOS}/os/hal/platforms/AT91SAM7/at91sam7_mii.c \ + ${CHIBIOS}/os/hal/platforms/AT91SAM7/at91lib/aic.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/AT91SAM7 diff --git a/Project/os/hal/platforms/AT91SAM7/serial_lld.c b/Project/os/hal/platforms/AT91SAM7/serial_lld.c new file mode 100644 index 0000000..7458f97 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/serial_lld.c @@ -0,0 +1,388 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AT91SAM7/serial_lld.c + * @brief AT91SAM7 low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +#if (SAM7_PLATFORM == SAM7S64) || (SAM7_PLATFORM == SAM7S128) || \ + (SAM7_PLATFORM == SAM7S256) || (SAM7_PLATFORM == SAM7S512) + +#define SAM7_USART0_RX AT91C_PA5_RXD0 +#define SAM7_USART0_TX AT91C_PA6_TXD0 +#define SAM7_USART1_RX AT91C_PA21_RXD1 +#define SAM7_USART1_TX AT91C_PA22_TXD1 +#define SAM7_DBGU_RX AT91C_PA9_DRXD +#define SAM7_DBGU_TX AT91C_PA10_DTXD + +#elif (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) + +#define SAM7_USART0_RX AT91C_PA0_RXD0 +#define SAM7_USART0_TX AT91C_PA1_TXD0 +#define SAM7_USART1_RX AT91C_PA5_RXD1 +#define SAM7_USART1_TX AT91C_PA6_TXD1 +#define SAM7_DBGU_RX AT91C_PA27_DRXD +#define SAM7_DBGU_TX AT91C_PA28_DTXD + +#else +#error "serial lines not defined for this SAM7 version" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if USE_SAM7_USART0 || defined(__DOXYGEN__) +/** @brief USART0 serial driver identifier.*/ +SerialDriver SD1; +#endif + +#if USE_SAM7_USART1 || defined(__DOXYGEN__) +/** @brief USART1 serial driver identifier.*/ +SerialDriver SD2; +#endif + +#if USE_SAM7_DBGU_UART || defined(__DOXYGEN__) +/** @brief DBGU_UART serial driver identifier.*/ +SerialDriver SD3; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = { + SERIAL_DEFAULT_BITRATE, + AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK | + AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE | AT91C_US_NBSTOP_1_BIT +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief USART initialization. + * + * @param[in] sdp communication channel associated to the USART + * @param[in] config the architecture-dependent serial driver configuration + */ +static void usart_init(SerialDriver *sdp, const SerialConfig *config) { + AT91PS_USART u = sdp->usart; + + /* Disables IRQ sources and stop operations.*/ + u->US_IDR = 0xFFFFFFFF; + u->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RSTSTA; + + /* New parameters setup.*/ + if (config->sc_mr & AT91C_US_OVER) + u->US_BRGR = MCK / (config->sc_speed * 8); + else + u->US_BRGR = MCK / (config->sc_speed * 16); + u->US_MR = config->sc_mr; + u->US_RTOR = 0; + u->US_TTGR = 0; + + /* Enables operations and IRQ sources.*/ + u->US_CR = AT91C_US_RXEN | AT91C_US_TXEN | AT91C_US_DTREN | AT91C_US_RTSEN; + u->US_IER = AT91C_US_RXRDY | AT91C_US_OVRE | AT91C_US_FRAME | AT91C_US_PARE | + AT91C_US_RXBRK; +} + +/** + * @brief USART de-initialization. + * + * @param[in] u pointer to an USART I/O block + */ +static void usart_deinit(AT91PS_USART u) { + + /* Disables IRQ sources and stop operations.*/ + u->US_IDR = 0xFFFFFFFF; + u->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RSTSTA; + u->US_MR = 0; + u->US_RTOR = 0; + u->US_TTGR = 0; +} + +/** + * @brief Error handling routine. + * + * @param[in] err USART CSR register value + * @param[in] sdp communication channel associated to the USART + */ +static void set_error(SerialDriver *sdp, AT91_REG csr) { + ioflags_t sts = 0; + + if (csr & AT91C_US_OVRE) + sts |= SD_OVERRUN_ERROR; + if (csr & AT91C_US_PARE) + sts |= SD_PARITY_ERROR; + if (csr & AT91C_US_FRAME) + sts |= SD_FRAMING_ERROR; + if (csr & AT91C_US_RXBRK) + sts |= SD_BREAK_DETECTED; + chSysLockFromIsr(); + chIOAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +#if defined(__GNUC__) +__attribute__((noinline)) +#endif +#if !USE_SAM7_DBGU_UART +static +#endif +/** + * @brief Common IRQ handler. + * + * @param[in] sdp communication channel associated to the USART + */ +void sd_lld_serve_interrupt(SerialDriver *sdp) { + uint32_t csr; + AT91PS_USART u = sdp->usart; + + csr = u->US_CSR; + if (csr & AT91C_US_RXRDY) { + chSysLockFromIsr(); + sdIncomingDataI(sdp, u->US_RHR); + chSysUnlockFromIsr(); + } + if ((u->US_IMR & AT91C_US_TXRDY) && (csr & AT91C_US_TXRDY)) { + msg_t b; + + chSysLockFromIsr(); + b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) { + chIOAddFlagsI(sdp, IO_OUTPUT_EMPTY); + u->US_IDR = AT91C_US_TXRDY; + } + else + u->US_THR = b; + chSysUnlockFromIsr(); + } + csr &= (AT91C_US_OVRE | AT91C_US_FRAME | AT91C_US_PARE | AT91C_US_RXBRK); + if (csr != 0) { + set_error(sdp, csr); + u->US_CR = AT91C_US_RSTSTA; + } + AT91C_BASE_AIC->AIC_EOICR = 0; +} + +#if USE_SAM7_USART0 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + AT91C_BASE_US0->US_IER = AT91C_US_TXRDY; +} +#endif + +#if USE_SAM7_USART1 || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + AT91C_BASE_US1->US_IER = AT91C_US_TXRDY; +} +#endif + +#if USE_SAM7_DBGU_UART || defined(__DOXYGEN__) +static void notify3(GenericQueue *qp) { + + (void)qp; + AT91C_BASE_DBGU->DBGU_IER = AT91C_US_TXRDY; +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if USE_SAM7_USART0 || defined(__DOXYGEN__) +/** + * @brief USART0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART0IrqHandler) { + + CH_IRQ_PROLOGUE(); + sd_lld_serve_interrupt(&SD1); + AT91C_BASE_AIC->AIC_EOICR = 0; + CH_IRQ_EPILOGUE(); +} +#endif + +#if USE_SAM7_USART1 || defined(__DOXYGEN__) +/** + * @brief USART1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART1IrqHandler) { + + CH_IRQ_PROLOGUE(); + sd_lld_serve_interrupt(&SD2); + AT91C_BASE_AIC->AIC_EOICR = 0; + CH_IRQ_EPILOGUE(); +} +#endif + +/* note - DBGU_UART IRQ is the SysIrq in board.c + since it's not vectored separately by the AIC.*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if USE_SAM7_USART0 + sdObjectInit(&SD1, NULL, notify1); + SD1.usart = AT91C_BASE_US0; + AT91C_BASE_PIOA->PIO_PDR = SAM7_USART0_RX | SAM7_USART0_TX; + AT91C_BASE_PIOA->PIO_ASR = SAM7_USART0_RX | SAM7_USART0_TX; + AT91C_BASE_PIOA->PIO_PPUDR = SAM7_USART0_RX | SAM7_USART0_TX; + AIC_ConfigureIT(AT91C_ID_US0, + AT91C_AIC_SRCTYPE_HIGH_LEVEL | SAM7_USART0_PRIORITY, + USART0IrqHandler); +#endif + +#if USE_SAM7_USART1 + sdObjectInit(&SD2, NULL, notify2); + SD2.usart = AT91C_BASE_US1; + AT91C_BASE_PIOA->PIO_PDR = SAM7_USART1_RX | SAM7_USART1_TX; + AT91C_BASE_PIOA->PIO_ASR = SAM7_USART1_RX | SAM7_USART1_TX; + AT91C_BASE_PIOA->PIO_PPUDR = SAM7_USART1_RX | SAM7_USART1_TX; + AIC_ConfigureIT(AT91C_ID_US1, + AT91C_AIC_SRCTYPE_HIGH_LEVEL | SAM7_USART1_PRIORITY, + USART1IrqHandler); +#endif + +#if USE_SAM7_DBGU_UART + sdObjectInit(&SD3, NULL, notify3); + /* this is a little cheap, but OK for now since there's enough overlap + between dbgu and usart register maps. it means we can reuse all the + same usart interrupt handling and config that already exists.*/ + SD3.usart = (AT91PS_USART)AT91C_BASE_DBGU; + AT91C_BASE_PIOA->PIO_PDR = SAM7_DBGU_RX | SAM7_DBGU_TX; + AT91C_BASE_PIOA->PIO_ASR = SAM7_DBGU_RX | SAM7_DBGU_TX; + AT91C_BASE_PIOA->PIO_PPUDR = SAM7_DBGU_RX | SAM7_DBGU_TX; +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + + if (sdp->state == SD_STOP) { +#if USE_SAM7_USART0 + if (&SD1 == sdp) { + /* Starts the clock and clears possible sources of immediate interrupts.*/ + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_US0); + /* Enables associated interrupt vector.*/ + AIC_EnableIT(AT91C_ID_US0); + } +#endif +#if USE_SAM7_USART1 + if (&SD2 == sdp) { + /* Starts the clock and clears possible sources of immediate interrupts.*/ + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_US1); + /* Enables associated interrupt vector.*/ + AIC_EnableIT(AT91C_ID_US1); + } +#endif + /* Note - no explicit start for SD3 (DBGU_UART) since it's not included + in the AIC or PMC.*/ + } + usart_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) { + usart_deinit(sdp->usart); +#if USE_SAM7_USART0 + if (&SD1 == sdp) { + AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_US0); + AIC_DisableIT(AT91C_ID_US0); + return; + } +#endif +#if USE_SAM7_USART1 + if (&SD2 == sdp) { + AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_US1); + AIC_DisableIT(AT91C_ID_US1); + return; + } +#endif +#if USE_SAM7_DBGU_UART + if (&SD3 == sdp) { + AT91C_BASE_DBGU->DBGU_IDR = 0xFFFFFFFF; + return; + } +#endif + } +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/AT91SAM7/serial_lld.h b/Project/os/hal/platforms/AT91SAM7/serial_lld.h new file mode 100644 index 0000000..2830627 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/serial_lld.h @@ -0,0 +1,177 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AT91SAM7/serial_lld.h + * @brief AT91SAM7 low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief UART0 driver enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_SAM7_USART0) || defined(__DOXYGEN__) +#define USE_SAM7_USART0 TRUE +#endif + +/** + * @brief UART1 driver enable switch. + * @details If set to @p TRUE the support for USART2 is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_SAM7_USART1) || defined(__DOXYGEN__) +#define USE_SAM7_USART1 TRUE +#endif + +/** + * @brief DBGU UART driver enable switch. + * @details If set to @p TRUE the support for the DBGU UART is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_SAM7_DBGU_UART) || defined(__DOXYGEN__) +#define USE_SAM7_DBGU_UART TRUE +#endif + +/** + * @brief UART1 interrupt priority level setting. + */ +#if !defined(SAM7_USART0_PRIORITY) || defined(__DOXYGEN__) +#define SAM7_USART0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) +#endif + +/** + * @brief UART2 interrupt priority level setting. + */ +#if !defined(SAM7_USART1_PRIORITY) || defined(__DOXYGEN__) +#define SAM7_USART1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) +#endif + +/** + * @brief DBGU_UART interrupt priority level setting. + */ +#if !defined(SAM7_DBGU_UART_PRIORITY) || defined(__DOXYGEN__) +#define SAM7_DBGU_UART_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief AT91SAM7 Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + */ +typedef struct { + /** + * @brief Bit rate. + * @details This is written to the US_BRGR register of the appropriate AT91S_USART + */ + uint32_t sc_speed; + /** + * @brief Initialization value for the MR register. + * @details This is written to the US_MR register of the appropriate AT91S_USART + */ + uint32_t sc_mr; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the USART registers block.*/ \ + AT91PS_USART usart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if USE_SAM7_USART0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if USE_SAM7_USART1 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif +#if USE_SAM7_DBGU_UART +extern SerialDriver SD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#if USE_SAM7_DBGU_UART + void sd_lld_serve_interrupt(SerialDriver *sdp); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/AT91SAM7/spi_lld.c b/Project/os/hal/platforms/AT91SAM7/spi_lld.c new file mode 100644 index 0000000..dad9697 --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/spi_lld.c @@ -0,0 +1,408 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AT91SAM7/spi_lld.c + * @brief AT91SAM7 low level SPI driver code. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if AT91SAM7_SPI_USE_SPI0 || defined(__DOXYGEN__) +/** @brief SPI1 driver identifier.*/ +SPIDriver SPID1; +#endif + +#if AT91SAM7_SPI_USE_SPI1 || defined(__DOXYGEN__) +/** @brief SPI2 driver identifier.*/ +SPIDriver SPID2; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** + * @brief Idle line value. + * @details This thing's DMA apparently does not allow to *not* increment + * the memory pointer so a buffer filled with ones is required + * somewhere. + * @note This buffer size also limits the maximum transfer size, 512B, + * for @p spiReceive() and @p spiIgnore(). @p spiSend() and + * @p spiExchange are not affected. + */ +static const uint16_t idle_buf[] = { + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes a SPI device. + */ +static void spi_init(AT91PS_SPI spi) { + + /* Software reset must be written twice (errata for revision B parts).*/ + spi->SPI_CR = AT91C_SPI_SWRST; + spi->SPI_CR = AT91C_SPI_SWRST; + spi->SPI_RCR = 0; + spi->SPI_RNCR = 0; + spi->SPI_TCR = 0; + spi->SPI_TNCR = 0; + spi->SPI_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS; + spi->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS; +} + +#if defined(__GNUC__) +__attribute__((noinline)) +#endif +/** + * @brief Shared interrupt handling code. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void spi_lld_serve_interrupt(SPIDriver *spip) { + uint32_t sr = spip->spi->SPI_SR; + + if ((sr & AT91C_SPI_ENDRX) != 0) { + (void)spip->spi->SPI_RDR; /* Clears eventual overflow.*/ + spip->spi->SPI_PTCR = AT91C_PDC_RXTDIS | + AT91C_PDC_TXTDIS; /* PDC disabled. */ + spip->spi->SPI_IDR = AT91C_SPI_ENDRX; /* Interrupt disabled. */ + spip->spi->SPI_CR = AT91C_SPI_SPIDIS; /* SPI disabled. */ + /* Portable SPI ISR code defined in the high level driver, note, it is + a macro.*/ + _spi_isr_code(spip); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if AT91SAM7_SPI_USE_SPI0 || defined(__DOXYGEN__) +/** + * @brief SPI0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPI0IrqHandler) { + + CH_IRQ_PROLOGUE(); + spi_lld_serve_interrupt(&SPID1); + AT91C_BASE_AIC->AIC_EOICR = 0; + CH_IRQ_EPILOGUE(); +} +#endif + +#if AT91SAM7_SPI_USE_SPI1 || defined(__DOXYGEN__) +/** + * @brief SPI1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPI1IrqHandler) { + + CH_IRQ_PROLOGUE(); + spi_lld_serve_interrupt(&SPID2); + AT91C_BASE_AIC->AIC_EOICR = 0; + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +#if AT91SAM7_SPI_USE_SPI0 + spiObjectInit(&SPID1); + SPID1.spi = AT91C_BASE_SPI0; + spi_init(AT91C_BASE_SPI0); + AT91C_BASE_PIOA->PIO_PDR = SPI0_MISO | SPI0_MOSI | SPI0_SCK; + AT91C_BASE_PIOA->PIO_ASR = SPI0_MISO | SPI0_MOSI | SPI0_SCK; + AT91C_BASE_PIOA->PIO_PPUDR = SPI0_MISO | SPI0_MOSI | SPI0_SCK; + AIC_ConfigureIT(AT91C_ID_SPI0, + AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91SAM7_SPI0_PRIORITY, + SPI0IrqHandler); +#endif + +#if AT91SAM7_SPI_USE_SPI1 + spiObjectInit(&SPID2); + SPID2.spi = AT91C_BASE_SPI1; + spi_init(AT91C_BASE_SPI1); + AT91C_BASE_PIOA->PIO_PDR = SPI1_MISO | SPI1_MOSI | SPI1_SCK; + AT91C_BASE_PIOA->PIO_BSR = SPI1_MISO | SPI1_MOSI | SPI1_SCK; + AT91C_BASE_PIOA->PIO_PPUDR = SPI1_MISO | SPI1_MOSI | SPI1_SCK; + AIC_ConfigureIT(AT91C_ID_SPI1, + AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91SAM7_SPI1_PRIORITY, + SPI1IrqHandler); +#endif +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + if (spip->state == SPI_STOP) { +#if AT91SAM7_SPI_USE_SPI0 + if (&SPID1 == spip) { + /* Clock activation.*/ + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SPI0); + /* Enables associated interrupt vector.*/ + AIC_EnableIT(AT91C_ID_SPI0); + } +#endif +#if AT91SAM7_SPI_USE_SPI1 + if (&SPID2 == spip) { + /* Clock activation.*/ + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SPI1); + /* Enables associated interrupt vector.*/ + AIC_EnableIT(AT91C_ID_SPI1); + } +#endif + } + /* Configuration.*/ + spip->spi->SPI_CSR[0] = spip->config->csr; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + if (spip->state != SPI_STOP) { +#if AT91SAM7_SPI_USE_SPI0 + if (&SPID1 == spip) { + AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_SPI0); + AIC_DisableIT(AT91C_ID_SPI0); + } +#endif +#if AT91SAM7_SPI_USE_SPI1 + if (&SPID1 == spip) { + AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_SPI1); + AIC_DisableIT(AT91C_ID_SPI0); + } +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This function transmits a series of idle words on the SPI bus and + * ignores the received data. This function can be invoked even + * when a slave select signal has not been yet asserted. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + spip->spi->SPI_TCR = n; + spip->spi->SPI_RCR = n; + spip->spi->SPI_TPR = (AT91_REG)idle_buf; + spip->spi->SPI_RPR = (AT91_REG)idle_buf; + spip->spi->SPI_IER = AT91C_SPI_ENDRX; + spip->spi->SPI_CR = AT91C_SPI_SPIEN; + spip->spi->SPI_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN; +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This function performs a simultaneous transmit/receive operation. + * @note The buffers are organized as uint8_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + spip->spi->SPI_TCR = n; + spip->spi->SPI_RCR = n; + spip->spi->SPI_TPR = (AT91_REG)txbuf; + spip->spi->SPI_RPR = (AT91_REG)rxbuf; + spip->spi->SPI_IER = AT91C_SPI_ENDRX; + spip->spi->SPI_CR = AT91C_SPI_SPIEN; + spip->spi->SPI_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN; +} + +/** + * @brief Sends data over the SPI bus. + * @note The buffers are organized as uint8_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + spip->spi->SPI_TCR = n; + spip->spi->SPI_RCR = n; + spip->spi->SPI_TPR = (AT91_REG)txbuf; + spip->spi->SPI_RPR = (AT91_REG)idle_buf; + spip->spi->SPI_IER = AT91C_SPI_ENDRX; + spip->spi->SPI_CR = AT91C_SPI_SPIEN; + spip->spi->SPI_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN; +} + +/** + * @brief Receives data from the SPI bus. + * @note The buffers are organized as uint8_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + spip->spi->SPI_TCR = n; + spip->spi->SPI_RCR = n; + spip->spi->SPI_TPR = (AT91_REG)idle_buf; + spip->spi->SPI_RPR = (AT91_REG)rxbuf; + spip->spi->SPI_IER = AT91C_SPI_ENDRX; + spip->spi->SPI_CR = AT91C_SPI_SPIEN; + spip->spi->SPI_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN; +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + spip->spi->SPI_CR = AT91C_SPI_SPIEN; + spip->spi->SPI_TDR = frame; + while ((spip->spi->SPI_SR & AT91C_SPI_RDRF) == 0) + ; + return spip->spi->SPI_RDR; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/Project/os/hal/platforms/AT91SAM7/spi_lld.h b/Project/os/hal/platforms/AT91SAM7/spi_lld.h new file mode 100644 index 0000000..94b3d8c --- /dev/null +++ b/Project/os/hal/platforms/AT91SAM7/spi_lld.h @@ -0,0 +1,230 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AT91SAM7/spi_lld.h + * @brief AT91SAM7 low level SPI driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Device compatibility.. */ +/*===========================================================================*/ + +#if defined (AT91C_BASE_SPI) +#define AT91C_BASE_SPI0 AT91C_BASE_SPI +#define AT91C_ID_SPI0 AT91C_ID_SPI + +#define SPI0_MISO (1 << 12) +#define SPI0_MOSI (1 << 13) +#define SPI0_SCK (1 << 14) +#else +#define SPI0_MISO (1 << 16) +#define SPI0_MOSI (1 << 17) +#define SPI0_SCK (1 << 18) + +#define SPI1_MISO (1 << 24) +#define SPI1_MOSI (1 << 23) +#define SPI1_SCK (1 << 22) +#endif + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SPID1 enable switch (SPI0 device). + * @details If set to @p TRUE the support for SPI0 is included. + * @note The default is @p TRUE. + */ +#if !defined(AT91SAM7_SPI_USE_SPI0) || defined(__DOXYGEN__) +#define AT91SAM7_SPI_USE_SPI0 TRUE +#endif + +/** + * @brief SPID2 enable switch (SPI1 device). + * @details If set to @p TRUE the support for SPI1 is included. + * @note The default is @p TRUE. + */ +#if !defined(AT91SAM7_SPI_USE_SPI1) || defined(__DOXYGEN__) +#define AT91SAM7_SPI_USE_SPI1 TRUE +#endif + +/** + * @brief SPI0 device interrupt priority level setting. + */ +#if !defined(AT91SAM7_SPI0_PRIORITY) || defined(__DOXYGEN__) +#define AT91SAM7_SPI0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) +#endif + +/** + * @brief SPI1 device interrupt priority level setting. + */ +#if !defined(AT91SAM7_SPI1_PRIORITY) || defined(__DOXYGEN__) +#define AT91SAM7_SPI1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if defined (AT91C_BASE_SPI) && AT91SAM7_SPI_USE_SPI1 +#error "SPI1 not present" +#endif + +#if !AT91SAM7_SPI_USE_SPI0 && !AT91SAM7_SPI_USE_SPI1 +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief SPI Chip Select Register initialization data. + */ + uint32_t csr; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SPIx registers block. + */ + AT91PS_SPI spi; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if AT91SAM7_SPI_USE_SPI0 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#if AT91SAM7_SPI_USE_SPI1 && !defined(__DOXYGEN__) +extern SPIDriver SPID2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/AVR/hal_lld.c b/Project/os/hal/platforms/AVR/hal_lld.c new file mode 100644 index 0000000..315784d --- /dev/null +++ b/Project/os/hal/platforms/AVR/hal_lld.c @@ -0,0 +1,68 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AVR/hal_lld.c + * @brief AVR HAL subsystem low level driver code. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + +} + +/** @} */ diff --git a/Project/os/hal/platforms/AVR/hal_lld.h b/Project/os/hal/platforms/AVR/hal_lld.h new file mode 100644 index 0000000..87ae6a0 --- /dev/null +++ b/Project/os/hal/platforms/AVR/hal_lld.h @@ -0,0 +1,83 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AVR/hal_lld.h + * @brief AVR HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "ATmega128" + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/AVR/pal_lld.c b/Project/os/hal/platforms/AVR/pal_lld.c new file mode 100644 index 0000000..98d3e9b --- /dev/null +++ b/Project/os/hal/platforms/AVR/pal_lld.c @@ -0,0 +1,148 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AVR/pal_lld.c + * @brief AVR GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief AVR GPIO ports configuration. + * @details GPIO registers initialization. + * + * @param[in] config the AVR ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + +#if defined(PORTA) || defined(__DOXYGEN__) + PORTA = config->porta.out; + DDRA = config->porta.dir; +#endif + +#if defined(PORTB) || defined(__DOXYGEN__) + PORTB = config->portb.out; + DDRB = config->portb.dir; +#endif + +#if defined(PORTC) || defined(__DOXYGEN__) + PORTC = config->portc.out; + DDRC = config->portc.dir; +#endif + +#if defined(PORTD) || defined(__DOXYGEN__) + PORTD = config->portd.out; + DDRD = config->portd.dir; +#endif + +#if defined(PORTE) || defined(__DOXYGEN__) + PORTE = config->porte.out; + DDRE = config->porte.dir; +#endif + +#if defined(PORTF) || defined(__DOXYGEN__) + PORTF = config->portf.out; + DDRF = config->portf.dir; +#endif + +#if defined(PORTG) || defined(__DOXYGEN__) + PORTG = config->portg.out; + DDRG = config->portg.dir; +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @note This function is not meant to be invoked directly by the application + * code. + * @note @p PAL_MODE_UNCONNECTED is implemented as output as recommended by + * the AVR Family User's Guide. Unconnected pads are set to input + * with pull-up by default. + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + case PAL_MODE_INPUT_ANALOG: + port->dir &= ~mask; + port->out &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + case PAL_MODE_INPUT_PULLUP: + port->dir &= ~mask; + port->out |= mask; + break; + case PAL_MODE_OUTPUT_PUSHPULL: + port->dir |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/AVR/pal_lld.h b/Project/os/hal/platforms/AVR/pal_lld.h new file mode 100644 index 0000000..3af6f6d --- /dev/null +++ b/Project/os/hal/platforms/AVR/pal_lld.h @@ -0,0 +1,300 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AVR/pal_lld.h + * @brief AVR GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 8 + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) + +/** + * @brief AVR setup registers. + */ +typedef struct { + uint8_t out; + uint8_t dir; +} avr_gpio_setup_t; + +/** + * @brief AVR registers block. + * @note On some devices registers do not follow this layout on some + * ports, the ports with abnormal layout cannot be used through + * PAL driver. Example: PORT F on Mega128. + */ +typedef struct { + volatile uint8_t in; + volatile uint8_t dir; + volatile uint8_t out; +} avr_gpio_registers_t; + +/** + * @brief Generic I/O ports static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { +#if defined(PORTA) || defined(__DOXYGEN__) + avr_gpio_setup_t porta; +#endif +#if defined(PORTB) || defined(__DOXYGEN__) + avr_gpio_setup_t portb; +#endif +#if defined(PORTC) || defined(__DOXYGEN__) + avr_gpio_setup_t portc; +#endif +#if defined(PORTD) || defined(__DOXYGEN__) + avr_gpio_setup_t portd; +#endif +#if defined(PORTE) || defined(__DOXYGEN__) + avr_gpio_setup_t porte; +#endif +#if defined(PORTF) || defined(__DOXYGEN__) + avr_gpio_setup_t portf; +#endif +#if defined(PORTG) || defined(__DOXYGEN__) + avr_gpio_setup_t portg; +#endif +} PALConfig; + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint8_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint8_t iomode_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef avr_gpio_registers_t *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +#if defined(PORTA) || defined(__DOXYGEN__) +/** + * @brief GPIO port A identifier. + */ +#define IOPORT1 ((volatile avr_gpio_registers_t *)&PINA) +#endif + +#if defined(PORTB) || defined(__DOXYGEN__) +/** + * @brief GPIO port B identifier. + */ +#define IOPORT2 ((volatile avr_gpio_registers_t *)&PINB) +#endif + +#if defined(PORTC) || defined(__DOXYGEN__) +/** + * @brief GPIO port C identifier. + */ +#define IOPORT3 ((volatile avr_gpio_registers_t *)&PINC) +#endif + +#if defined(PORTD) || defined(__DOXYGEN__) +/** + * @brief GPIO port D identifier. + */ +#define IOPORT4 ((volatile avr_gpio_registers_t *)&PIND) +#endif + +#if defined(PORTE) || defined(__DOXYGEN__) +/** + * @brief GPIO port E identifier. + */ +#define IOPORT5 ((volatile avr_gpio_registers_t *)&PINE) +#endif + +#if defined(PORTF) || defined(__DOXYGEN__) +/** + * @brief GPIO port F identifier. + */ +#define IOPORT6 ((volatile avr_gpio_registers_t *)&PINF) +#endif + +#if defined(PORTG) || defined(__DOXYGEN__) +/** + * @brief GPIO port G identifier. + */ +#define IOPORT7 ((volatile avr_gpio_registers_t *)&PING) +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config the architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->in) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->out) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->out = bits) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) \ +__asm__ __volatile__ \ +( \ + "sbi %0,%1\n\t" \ + : \ + : "I" (_SFR_IO_ADDR(port->out)), \ + "I" (pad) \ + \ +) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) \ +__asm__ __volatile__ \ +( \ + "cbi %0,%1\n\t" \ + : \ + : "I" (_SFR_IO_ADDR(port->out)), \ + "I" (pad) \ + \ +) + +extern ROMCONST PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/AVR/platform.dox b/Project/os/hal/platforms/AVR/platform.dox new file mode 100644 index 0000000..6e04841 --- /dev/null +++ b/Project/os/hal/platforms/AVR/platform.dox @@ -0,0 +1,109 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup AVR_DRIVERS AVR Drivers + * @details This section describes all the supported drivers on the AVR + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup AVR_HAL AVR Initialization Support + * @details On the AVR platform the HAL driver is a stub and does not perform + * any platform-specific initialization, it still performs the + * initialization of the other drivers. + * + * @ingroup AVR_DRIVERS + */ + +/** + * @defgroup AVR_PAL AVR PAL Support + * @details The AVR PAL driver uses the PORT peripherals. + * + * @section avr_pal_1 Supported HW resources + * - PORTA. + * - PORTB. + * - PORTC. + * - PORTD. + * - PORTE. + * - PORTF. + * - PORTG. + * . + * @section avr_pal_2 AVR PAL driver implementation features + * The AVR PAL driver implementation fully supports the following hardware + * capabilities: + * - 8 bits wide ports. + * - Atomic set/reset functions. + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section avr_pal_3 Supported PAL setup modes + * The AVR PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_PULLUP. + * - @p PAL_MODE_INPUT_ANALOG. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section avr_pal_4 Suboptimal behavior + * The AVR PORT is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Pad/port toggling operations are not atomic. + * - Pad/group mode setup is not atomic. + * - Group set+reset function is not atomic. + * - Writing on pads/groups/ports programmed as input with pull-up + * resistor changes the resistor setting because the output latch is + * used for resistor selection. + * - The PORT registers layout on some devices is not regular (it does + * not have contiguous PIN, DDR, PORT registers in this order), such + * ports cannot be accessed using the PAL driver. For example, PORT F + * on ATmega128. Verify the user manual of your device. + * . + * @ingroup AVR_DRIVERS + */ + +/** + * @defgroup AVR_SERIAL AVR Serial Support + * @details The AVR Serial driver uses the USART peripherals in a + * buffered, interrupt driven, implementation. + * + * @section avr_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - USART0. + * - USART1. + * . + * @section avr_serial_2 AVR Serial driver implementation features + * - Each USART can be independently enabled and programmed. + * - Fully interrupt driven. + * . + * @ingroup AVR_DRIVERS + */ diff --git a/Project/os/hal/platforms/AVR/platform.mk b/Project/os/hal/platforms/AVR/platform.mk new file mode 100644 index 0000000..e31413c --- /dev/null +++ b/Project/os/hal/platforms/AVR/platform.mk @@ -0,0 +1,7 @@ +# List of all the AVR platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/AVR/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/AVR/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/AVR/serial_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/AVR diff --git a/Project/os/hal/platforms/AVR/serial_lld.c b/Project/os/hal/platforms/AVR/serial_lld.c new file mode 100644 index 0000000..3f5957f --- /dev/null +++ b/Project/os/hal/platforms/AVR/serial_lld.c @@ -0,0 +1,318 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AVR/serial_lld.c + * @brief AVR low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief USART0 serial driver identifier. + * @note The name does not follow the convention used in the other ports + * (COMn) because a name conflict with the AVR headers. + */ +#if USE_AVR_USART0 || defined(__DOXYGEN__) +SerialDriver SD1; +#endif + +/** + * @brief USART1 serial driver identifier. + * @note The name does not follow the convention used in the other ports + * (COMn) because a name conflict with the AVR headers. + */ +#if USE_AVR_USART1 || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** + * @brief Driver default configuration. + */ +static const SerialConfig default_config = { + UBRR(SERIAL_DEFAULT_BITRATE), + (1 << UCSZ1) | (1 << UCSZ0) +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void set_error(uint8_t sra, SerialDriver *sdp) { + ioflags_t sts = 0; + + if (sra & (1 << DOR)) + sts |= SD_OVERRUN_ERROR; + if (sra & (1 << UPE)) + sts |= SD_PARITY_ERROR; + if (sra & (1 << FE)) + sts |= SD_FRAMING_ERROR; + chSysLockFromIsr(); + chIOAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +#if USE_AVR_USART0 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + UCSR0B |= (1 << UDRIE); +} + +/** + * @brief USART0 initialization. + * + * @param[in] config the architecture-dependent serial driver configuration + */ +static void usart0_init(const SerialConfig *config) { + + UBRR0L = config->sc_brr; + UBRR0H = config->sc_brr >> 8; + UCSR0A = 0; + UCSR0B = (1 << RXEN) | (1 << TXEN) | (1 << RXCIE); + UCSR0C = config->sc_csrc; +} + +/** + * @brief USART0 de-initialization. + */ +static void usart0_deinit(void) { + + UCSR0A = 0; + UCSR0B = 0; + UCSR0C = 0; +} +#endif + +#if USE_AVR_USART1 || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + UCSR1B |= (1 << UDRIE); +} + +/** + * @brief USART1 initialization. + * + * @param[in] config the architecture-dependent serial driver configuration + */ +static void usart1_init(const SerialConfig *config) { + + UBRR1L = config->sc_brr; + UBRR1H = config->sc_brr >> 8; + UCSR1A = 0; + UCSR1B = (1 << RXEN) | (1 << TXEN) | (1 << RXCIE); + UCSR1C = config->sc_csrc; +} + +/** + * @brief USART1 de-initialization. + */ +static void usart1_deinit(void) { + + UCSR1A = 0; + UCSR1B = 0; + UCSR1C = 0; +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if USE_AVR_USART0 || defined(__DOXYGEN__) +/** + * @brief USART0 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART0_RX_vect) { + uint8_t sra; + + CH_IRQ_PROLOGUE(); + + sra = UCSR0A; + if (sra & ((1 << DOR) | (1 << UPE) | (1 << FE))) + set_error(sra, &SD1); + chSysLockFromIsr(); + sdIncomingDataI(&SD1, UDR0); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief USART0 TX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART0_UDRE_vect) { + msg_t b; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + b = sdRequestDataI(&SD1); + chSysUnlockFromIsr(); + if (b < Q_OK) + UCSR0B &= ~(1 << UDRIE); + else + UDR0 = b; + + CH_IRQ_EPILOGUE(); +} +#endif /* USE_AVR_USART0 */ + +#if USE_AVR_USART1 || defined(__DOXYGEN__) +/** + * @brief USART1 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART1_RX_vect) { + uint8_t sra; + + CH_IRQ_PROLOGUE(); + + sra = UCSR1A; + if (sra & ((1 << DOR) | (1 << UPE) | (1 << FE))) + set_error(sra, &SD2); + chSysLockFromIsr(); + sdIncomingDataI(&SD2, UDR1); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief USART1 TX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART1_UDRE_vect) { + msg_t b; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + b = sdRequestDataI(&SD2); + chSysUnlockFromIsr(); + if (b < Q_OK) + UCSR1B &= ~(1 << UDRIE); + else + UDR1 = b; + + CH_IRQ_EPILOGUE(); +} +#endif /* USE_AVR_USART1 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if USE_AVR_USART0 + sdObjectInit(&SD1, NULL, notify1); +#endif +#if USE_AVR_USART1 + sdObjectInit(&SD2, NULL, notify2); +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + +#if USE_AVR_USART0 + if (&SD1 == sdp) { + usart0_init(config); + return; + } +#endif +#if USE_AVR_USART1 + if (&SD2 == sdp) { + usart1_init(config); + return; + } +#endif +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + +#if USE_AVR_USART0 + if (&SD1 == sdp) + usart0_deinit(); +#endif +#if USE_AVR_USART1 + if (&SD2 == sdp) + usart1_deinit(); +#endif +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/AVR/serial_lld.h b/Project/os/hal/platforms/AVR/serial_lld.h new file mode 100644 index 0000000..cc88204 --- /dev/null +++ b/Project/os/hal/platforms/AVR/serial_lld.h @@ -0,0 +1,163 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AVR/serial_lld.h + * @brief AVR low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief USART0 driver enable switch. + * @details If set to @p TRUE the support for USART0 is included. + * @note The default is @p FALSE. + */ +#if !defined(USE_AVR_USART0) || defined(__DOXYGEN__) +#define USE_AVR_USART0 TRUE +#endif + +/** + * @brief USART1 driver enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_AVR_USART1) || defined(__DOXYGEN__) +#define USE_AVR_USART1 TRUE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief AVR Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + */ +typedef struct { + /** + * @brief Initialization value for the BRR register. + */ + uint16_t sc_brr; + /** + * @brief Initialization value for the CSRC register. + */ + uint8_t sc_csrc; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Macro for baud rate computation. + * @note Make sure the final baud rate is within tolerance. + */ +#define UBRR(b) (((F_CPU / b) >> 4) - 1) + +/** + * @brief Macro for baud rate computation when U2Xn == 1. + * @note Make sure the final baud rate is within tolerance. + */ +#define UBRR2(b) (((F_CPU / b) >> 3) - 1) + +/** +* @brief Macro for baud rate computation. +* @note Make sure the final baud rate is within tolerance. +* @note This version uses floating point math for greater accuracy. +*/ +#define UBRR_F(b) ((((double) F_CPU / (double) b) / 16.0) - 0.5) + +/** +* @brief Macro for baud rate computation when U2Xn == 1. +* @note Make sure the final baud rate is within tolerance. +* @note This version uses floating point math for greater accuracy. +*/ +#define UBRR2_F(b) ((((double) F_CPU / (double) b) / 8.0) - 0.5) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if USE_AVR_USART0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if USE_AVR_USART1 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC11xx/LPC11xx.h b/Project/os/hal/platforms/LPC11xx/LPC11xx.h new file mode 100644 index 0000000..c07fe3b --- /dev/null +++ b/Project/os/hal/platforms/LPC11xx/LPC11xx.h @@ -0,0 +1,499 @@ +/**************************************************************************//** + * @file LPC11xx.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for + * NXP LPC11xx Device Series + * @version V1.00 + * @date 17. November 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __LPC11xx_H__ +#define __LPC11xx_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup LPC11xx_Definitions LPC11xx Definitions + This file defines all structures and symbols for LPC11xx: + - Registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + @{ +*/ + + +/******************************************************************************/ +/* Processor and Core Peripherals */ +/******************************************************************************/ +/** @addtogroup LPC11xx_CMSIS LPC11xx CMSIS Definitions + Configuration of the Cortex-M0 Processor and Core Peripherals + @{ +*/ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/****** LPC13xx Specific Interrupt Numbers *******************************************************/ + WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */ + WAKEUP1_IRQn = 1, /*!< There are 13 pins in total for LPC11xx */ + WAKEUP2_IRQn = 2, + WAKEUP3_IRQn = 3, + WAKEUP4_IRQn = 4, + WAKEUP5_IRQn = 5, + WAKEUP6_IRQn = 6, + WAKEUP7_IRQn = 7, + WAKEUP8_IRQn = 8, + WAKEUP9_IRQn = 9, + WAKEUP10_IRQn = 10, + WAKEUP11_IRQn = 11, + WAKEUP12_IRQn = 12, + SSP1_IRQn = 14, /*!< SSP1 Interrupt */ + I2C_IRQn = 15, /*!< I2C Interrupt */ + TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */ + TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */ + TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */ + TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */ + SSP0_IRQn = 20, /*!< SSP0 Interrupt */ + UART_IRQn = 21, /*!< UART Interrupt */ + ADC_IRQn = 24, /*!< A/D Converter Interrupt */ + WDT_IRQn = 25, /*!< Watchdog timer Interrupt */ + BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */ + EINT3_IRQn = 28, /*!< External Interrupt 3 Interrupt */ + EINT2_IRQn = 29, /*!< External Interrupt 2 Interrupt */ + EINT1_IRQn = 30, /*!< External Interrupt 1 Interrupt */ + EINT0_IRQn = 31, /*!< External Interrupt 0 Interrupt */ +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M3 Processor and Core Peripherals */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/*@}*/ /* end of group LPC11xx_CMSIS */ + + +#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#include "system_LPC11xx.h" /* System Header */ + + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/*------------- System Control (SYSCON) --------------------------------------*/ +/** @addtogroup LPC11xx_SYSCON LPC11xx System Control Block + @{ +*/ +typedef struct +{ + __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */ + __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */ + __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */ + __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/ ) */ + uint32_t RESERVED0[4]; + + __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */ + __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */ + __IO uint32_t IRCCTRL; /*!< Offset: 0x028 IRC control (R/W) */ + uint32_t RESERVED1[1]; + __IO uint32_t SYSRESSTAT; /*!< Offset: 0x030 System reset status Register (R/ ) */ + uint32_t RESERVED2[3]; + __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */ + __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */ + uint32_t RESERVED3[10]; + + __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */ + __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */ + __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */ + uint32_t RESERVED4[1]; + + __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */ + uint32_t RESERVED5[4]; + __IO uint32_t SSP0CLKDIV; /*!< Offset: 0x094 SSP0 clock divider (R/W) */ + __IO uint32_t UARTCLKDIV; /*!< Offset: 0x098 UART clock divider (R/W) */ + __IO uint32_t SSP1CLKDIV; /*!< Offset: 0x09C SSP1 clock divider (R/W) */ + uint32_t RESERVED6[4]; + + __IO uint32_t SYSTICKCLKDIV; /*!< Offset: 0x0B0 SYSTICK clock divider (R/W) */ + uint32_t RESERVED7[7]; + + __IO uint32_t WDTCLKSEL; /*!< Offset: 0x0D0 WDT clock source select (R/W) */ + __IO uint32_t WDTCLKUEN; /*!< Offset: 0x0D4 WDT clock source update enable (R/W) */ + __IO uint32_t WDTCLKDIV; /*!< Offset: 0x0D8 WDT clock divider (R/W) */ + uint32_t RESERVED8[1]; + __IO uint32_t CLKOUTCLKSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */ + __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */ + __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */ + uint32_t RESERVED9[5]; + + __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */ + __IO uint32_t PIOPORCAP1; /*!< Offset: 0x104 POR captured PIO status 1 (R/ ) */ + uint32_t RESERVED10[18]; + + __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */ + uint32_t RESERVED11[1]; + __IO uint32_t SYSTCKCAL; /*!< Offset: 0x158 System tick counter calibration (R/W) */ + uint32_t RESERVED12[41]; + + __IO uint32_t STARTAPRP0; /*!< Offset: 0x200 Start logic edge control Register 0 (R/W) */ + __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */ + __IO uint32_t STARTRSRP0CLR; /*!< Offset: 0x208 Start logic reset Register 0 ( /W) */ + __IO uint32_t STARTSRP0; /*!< Offset: 0x20C Start logic status Register 0 (R/W) */ + uint32_t RESERVED14[8]; + + __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */ + __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */ + __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */ + uint32_t RESERVED15[110]; + __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */ +} LPC_SYSCON_TypeDef; +/*@}*/ /* end of group LPC11xx_SYSCON */ + + +/*------------- Pin Connect Block (IOCON) --------------------------------*/ +/** @addtogroup LPC11xx_IOCON LPC11xx I/O Configuration Block + @{ +*/ +typedef struct +{ + __IO uint32_t PIO2_6; /*!< Offset: 0x000 I/O configuration for pin PIO2_6 (R/W) */ + uint32_t RESERVED0[1]; + __IO uint32_t PIO2_0; /*!< Offset: 0x008 I/O configuration for pin PIO2_0/DTR/SSEL1 (R/W) */ + __IO uint32_t RESET_PIO0_0; /*!< Offset: 0x00C I/O configuration for pin RESET/PIO0_0 (R/W) */ + __IO uint32_t PIO0_1; /*!< Offset: 0x010 I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 (R/W) */ + __IO uint32_t PIO1_8; /*!< Offset: 0x014 I/O configuration for pin PIO1_8/CT16B1_CAP0 (R/W) */ + uint32_t RESERVED1[1]; + __IO uint32_t PIO0_2; /*!< Offset: 0x01C I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 (R/W) */ + + __IO uint32_t PIO2_7; /*!< Offset: 0x020 I/O configuration for pin PIO2_7 (R/W) */ + __IO uint32_t PIO2_8; /*!< Offset: 0x024 I/O configuration for pin PIO2_8 (R/W) */ + __IO uint32_t PIO2_1; /*!< Offset: 0x028 I/O configuration for pin PIO2_1/nDSR/SCK1 (R/W) */ + __IO uint32_t PIO0_3; /*!< Offset: 0x02C I/O configuration for pin PIO0_3 (R/W) */ + __IO uint32_t PIO0_4; /*!< Offset: 0x030 I/O configuration for pin PIO0_4/SCL (R/W) */ + __IO uint32_t PIO0_5; /*!< Offset: 0x034 I/O configuration for pin PIO0_5/SDA (R/W) */ + __IO uint32_t PIO1_9; /*!< Offset: 0x038 I/O configuration for pin PIO1_9/CT16B1_MAT0 (R/W) */ + __IO uint32_t PIO3_4; /*!< Offset: 0x03C I/O configuration for pin PIO3_4 (R/W) */ + + __IO uint32_t PIO2_4; /*!< Offset: 0x040 I/O configuration for pin PIO2_4 (R/W) */ + __IO uint32_t PIO2_5; /*!< Offset: 0x044 I/O configuration for pin PIO2_5 (R/W) */ + __IO uint32_t PIO3_5; /*!< Offset: 0x048 I/O configuration for pin PIO3_5 (R/W) */ + __IO uint32_t PIO0_6; /*!< Offset: 0x04C I/O configuration for pin PIO0_6/SCK0 (R/W) */ + __IO uint32_t PIO0_7; /*!< Offset: 0x050 I/O configuration for pin PIO0_7/nCTS (R/W) */ + __IO uint32_t PIO2_9; /*!< Offset: 0x054 I/O configuration for pin PIO2_9 (R/W) */ + __IO uint32_t PIO2_10; /*!< Offset: 0x058 I/O configuration for pin PIO2_10 (R/W) */ + __IO uint32_t PIO2_2; /*!< Offset: 0x05C I/O configuration for pin PIO2_2/DCD/MISO1 (R/W) */ + + __IO uint32_t PIO0_8; /*!< Offset: 0x060 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 (R/W) */ + __IO uint32_t PIO0_9; /*!< Offset: 0x064 I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 (R/W) */ + __IO uint32_t JTAG_TCK_PIO0_10; /*!< Offset: 0x068 I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (R/W) */ + __IO uint32_t PIO1_10; /*!< Offset: 0x06C I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 (R/W) */ + __IO uint32_t PIO2_11; /*!< Offset: 0x070 I/O configuration for pin PIO2_11/SCK0 (R/W) */ + __IO uint32_t JTAG_TDI_PIO0_11; /*!< Offset: 0x074 I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 (R/W) */ + __IO uint32_t JTAG_TMS_PIO1_0; /*!< Offset: 0x078 I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 (R/W) */ + __IO uint32_t JTAG_TDO_PIO1_1; /*!< Offset: 0x07C I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 (R/W) */ + + __IO uint32_t JTAG_nTRST_PIO1_2; /*!< Offset: 0x080 I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 (R/W) */ + __IO uint32_t PIO3_0; /*!< Offset: 0x084 I/O configuration for pin PIO3_0/nDTR (R/W) */ + __IO uint32_t PIO3_1; /*!< Offset: 0x088 I/O configuration for pin PIO3_1/nDSR (R/W) */ + __IO uint32_t PIO2_3; /*!< Offset: 0x08C I/O configuration for pin PIO2_3/RI/MOSI1 (R/W) */ + __IO uint32_t ARM_SWDIO_PIO1_3; /*!< Offset: 0x090 I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 (R/W) */ + __IO uint32_t PIO1_4; /*!< Offset: 0x094 I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 (R/W) */ + __IO uint32_t PIO1_11; /*!< Offset: 0x098 I/O configuration for pin PIO1_11/AD7 (R/W) */ + __IO uint32_t PIO3_2; /*!< Offset: 0x09C I/O configuration for pin PIO3_2/nDCD (R/W) */ + + __IO uint32_t PIO1_5; /*!< Offset: 0x0A0 I/O configuration for pin PIO1_5/nRTS/CT32B0_CAP0 (R/W) */ + __IO uint32_t PIO1_6; /*!< Offset: 0x0A4 I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 (R/W) */ + __IO uint32_t PIO1_7; /*!< Offset: 0x0A8 I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 (R/W) */ + __IO uint32_t PIO3_3; /*!< Offset: 0x0AC I/O configuration for pin PIO3_3/nRI (R/W) */ + __IO uint32_t SCK_LOC; /*!< Offset: 0x0B0 SCK pin location select Register (R/W) */ + __IO uint32_t DSR_LOC; /*!< Offset: 0x0B4 DSR pin location select Register (R/W) */ + __IO uint32_t DCD_LOC; /*!< Offset: 0x0B8 DCD pin location select Register (R/W) */ + __IO uint32_t RI_LOC; /*!< Offset: 0x0BC RI pin location Register (R/W) */ +} LPC_IOCON_TypeDef; +/*@}*/ /* end of group LPC11xx_IOCON */ + + +/*------------- Power Management Unit (PMU) --------------------------*/ +/** @addtogroup LPC11xx_PMU LPC11xx Power Management Unit + @{ +*/ +typedef struct +{ + __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */ + __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */ + __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */ + __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */ + __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */ + __IO uint32_t GPREG4; /*!< Offset: 0x014 General purpose Register 4 (R/W) */ +} LPC_PMU_TypeDef; +/*@}*/ /* end of group LPC11xx_PMU */ + + +/*------------- General Purpose Input/Output (GPIO) --------------------------*/ +/** @addtogroup LPC11xx_GPIO LPC11xx General Purpose Input/Output + @{ +*/ +typedef struct +{ + union { + __IO uint32_t MASKED_ACCESS[4096]; /*!< Offset: 0x0000 to 0x3FFC Port data Register for pins PIOn_0 to PIOn_11 (R/W) */ + struct { + uint32_t RESERVED0[4095]; + __IO uint32_t DATA; /*!< Offset: 0x3FFC Port data Register (R/W) */ + }; + }; + uint32_t RESERVED1[4096]; + __IO uint32_t DIR; /*!< Offset: 0x8000 Data direction Register (R/W) */ + __IO uint32_t IS; /*!< Offset: 0x8004 Interrupt sense Register (R/W) */ + __IO uint32_t IBE; /*!< Offset: 0x8008 Interrupt both edges Register (R/W) */ + __IO uint32_t IEV; /*!< Offset: 0x800C Interrupt event Register (R/W) */ + __IO uint32_t IE; /*!< Offset: 0x8010 Interrupt mask Register (R/W) */ + __IO uint32_t RIS; /*!< Offset: 0x8014 Raw interrupt status Register (R/ ) */ + __IO uint32_t MIS; /*!< Offset: 0x8018 Masked interrupt status Register (R/ ) */ + __IO uint32_t IC; /*!< Offset: 0x801C Interrupt clear Register (R/W) */ +} LPC_GPIO_TypeDef; +/*@}*/ /* end of group LPC11xx_GPIO */ + + +/*------------- Timer (TMR) --------------------------------------------------*/ +/** @addtogroup LPC11xx_TMR LPC11xx 16/32-bit Counter/Timer + @{ +*/ +typedef struct +{ + __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */ + __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */ + __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */ + __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */ + __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */ + __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */ + __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */ + __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */ + __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */ + __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */ + __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */ + __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */ + uint32_t RESERVED1[3]; + __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */ + uint32_t RESERVED2[12]; + __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */ + __IO uint32_t PWMC; /*!< Offset: 0x074 PWM Control Register (R/W) */ +} LPC_TMR_TypeDef; +/*@}*/ /* end of group LPC11xx_TMR */ + + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +/** @addtogroup LPC11xx_UART LPC11xx Universal Asynchronous Receiver/Transmitter + @{ +*/ +typedef struct +{ + union { + __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */ + __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */ + __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */ + }; + union { + __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */ + __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */ + }; + union { + __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */ + __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */ + }; + __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */ + __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */ + __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */ + __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */ + __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */ + __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */ + uint32_t RESERVED0; + __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */ + uint32_t RESERVED1; + __IO uint32_t TER; /*!< Offset: 0x030 Transmit Enable Register (R/W) */ + uint32_t RESERVED2[6]; + __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */ + __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */ + __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */ + __I uint32_t FIFOLVL; /*!< Offset: 0x058 FIFO Level Register (R/ ) */ +} LPC_UART_TypeDef; +/*@}*/ /* end of group LPC11xx_UART */ + + +/*------------- Synchronous Serial Communication (SSP) -----------------------*/ +/** @addtogroup LPC11xx_SSP LPC11xx Synchronous Serial Port + @{ +*/ +typedef struct +{ + __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */ + __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */ + __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */ + __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */ + __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */ + __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */ + __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */ + __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */ + __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */ +} LPC_SSP_TypeDef; +/*@}*/ /* end of group LPC11xx_SSP */ + + +/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ +/** @addtogroup LPC11xx_I2C LPC11xx I2C-Bus Interface + @{ +*/ +typedef struct +{ + __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */ + __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */ + __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */ + __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */ + __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */ + __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */ + __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */ + __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */ + __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */ + __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */ + __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */ + __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */ + __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */ + __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */ + __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */ + __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */ +} LPC_I2C_TypeDef; +/*@}*/ /* end of group LPC11xx_I2C */ + + +/*------------- Watchdog Timer (WDT) -----------------------------------------*/ +/** @addtogroup LPC11xx_WDT LPC11xx WatchDog Timer + @{ +*/ +typedef struct +{ + __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */ + __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */ + __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register ( /W) */ + __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R/ ) */ +} LPC_WDT_TypeDef; +/*@}*/ /* end of group LPC11xx_WDT */ + + +/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ +/** @addtogroup LPC11xx_ADC LPC11xx Analog-to-Digital Converter + @{ +*/ +typedef struct +{ + __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */ + __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */ + uint32_t RESERVED0; + __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */ + __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */ + __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */ +} LPC_ADC_TypeDef; +/*@}*/ /* end of group LPC11xx_ADC */ + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Base addresses */ +#define LPC_FLASH_BASE (0x00000000UL) +#define LPC_RAM_BASE (0x10000000UL) +#define LPC_APB0_BASE (0x40000000UL) +#define LPC_AHB_BASE (0x50000000UL) + +/* APB0 peripherals */ +#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000) +#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000) +#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000) +#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000) +#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000) +#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000) +#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000) +#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000) +#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000) +#define LPC_SSP0_BASE (LPC_APB0_BASE + 0x40000) +#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) +#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) +#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x58000) + +/* AHB peripherals */ +#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000) +#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000) +#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) +#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) +#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE ) +#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE) +#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE) +#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE) +#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE) +#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) +#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) +#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) +#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) +#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) +#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) +#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) +#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) +#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) +#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) + +#ifdef __cplusplus +} +#endif + +#endif /* __LPC11xx_H__ */ diff --git a/Project/os/hal/platforms/LPC11xx/gpt_lld.c b/Project/os/hal/platforms/LPC11xx/gpt_lld.c new file mode 100644 index 0000000..14d000c --- /dev/null +++ b/Project/os/hal/platforms/LPC11xx/gpt_lld.c @@ -0,0 +1,349 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC11xx/gpt_lld.c + * @brief LPC11xx GPT subsystem low level driver source. + * + * @addtogroup GPT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief GPT1 driver identifier. + * @note The driver GPT1 allocates the complex timer CT16B0 when enabled. + */ +#if LPC11xx_GPT_USE_CT16B0 || defined(__DOXYGEN__) +GPTDriver GPTD1; +#endif + +/** + * @brief GPT2 driver identifier. + * @note The driver GPT2 allocates the timer CT16B1 when enabled. + */ +#if LPC11xx_GPT_USE_CT16B1 || defined(__DOXYGEN__) +GPTDriver GPTD2; +#endif + +/** + * @brief GPT3 driver identifier. + * @note The driver GPT3 allocates the timer CT32B0 when enabled. + */ +#if LPC11xx_GPT_USE_CT32B0 || defined(__DOXYGEN__) +GPTDriver GPTD3; +#endif + +/** + * @brief GPT4 driver identifier. + * @note The driver GPT4 allocates the timer CT32B1 when enabled. + */ +#if LPC11xx_GPT_USE_CT32B1 || defined(__DOXYGEN__) +GPTDriver GPTD4; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared IRQ handler. + * + * @param[in] gptp pointer to a @p GPTDriver object + */ +static void gpt_lld_serve_interrupt(GPTDriver *gptp) { + + gptp->tmr->IR = 1; /* Clear interrupt on match MR0.*/ + if (gptp->state == GPT_ONESHOT) { + gptp->state = GPT_READY; /* Back in GPT_READY state. */ + gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */ + } + gptp->config->callback(gptp); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC11xx_GPT_USE_CT16B0 +/** + * @brief CT16B0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector80) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC11xx_GPT_USE_CT16B0 */ + +#if LPC11xx_GPT_USE_CT16B1 +/** + * @brief CT16B1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector84) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC11xx_GPT_USE_CT16B0 */ + +#if LPC11xx_GPT_USE_CT32B0 +/** + * @brief CT32B0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector88) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC11xx_GPT_USE_CT32B0 */ + +#if LPC11xx_GPT_USE_CT32B1 +/** + * @brief CT32B1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector8C) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD4); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC11xx_GPT_USE_CT32B1 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level GPT driver initialization. + * + * @notapi + */ +void gpt_lld_init(void) { + +#if LPC11xx_GPT_USE_CT16B0 + /* Driver initialization.*/ + GPTD1.tmr = LPC_TMR16B0; + gptObjectInit(&GPTD1); +#endif + +#if LPC11xx_GPT_USE_CT16B1 + /* Driver initialization.*/ + GPTD2.tmr = LPC_TMR16B1; + gptObjectInit(&GPTD2); +#endif + +#if LPC11xx_GPT_USE_CT32B0 + /* Driver initialization.*/ + GPTD3.tmr = LPC_TMR32B0; + gptObjectInit(&GPTD3); +#endif + +#if LPC11xx_GPT_USE_CT32B1 + /* Driver initialization.*/ + GPTD4.tmr = LPC_TMR32B1; + gptObjectInit(&GPTD4); +#endif +} + +/** + * @brief Configures and activates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_start(GPTDriver *gptp) { + uint32_t pr; + + if (gptp->state == GPT_STOP) { + /* Clock activation.*/ +#if LPC11xx_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7); + nvicEnableVector(TIMER_16_0_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif +#if LPC11xx_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); + nvicEnableVector(TIMER_16_1_IRQn, CORTEX_PRIORITY_MASK(3)); + } +#endif +#if LPC11xx_GPT_USE_CT32B0 + if (&GPTD3 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9); + nvicEnableVector(TIMER_32_0_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif +#if LPC11xx_GPT_USE_CT32B1 + if (&GPTD4 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10); + nvicEnableVector(TIMER_32_1_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif + } + + /* Prescaler value calculation.*/ + pr = (uint16_t)((LPC11xx_SYSCLK / gptp->config->frequency) - 1); + chDbgAssert(((uint32_t)(pr + 1) * gptp->config->frequency) == LPC11xx_SYSCLK, + "gpt_lld_start(), #1", "invalid frequency"); + + /* Timer configuration.*/ + gptp->tmr->PR = pr; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; +} + +/** + * @brief Deactivates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop(GPTDriver *gptp) { + + if (gptp->state == GPT_READY) { + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; + +#if LPC11xx_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { + nvicDisableVector(TIMER_16_0_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7); + } +#endif +#if LPC11xx_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { + nvicDisableVector(TIMER_16_1_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8); + } +#endif +#if LPC11xx_GPT_USE_CT32B0 + if (&GPTD3 == gptp) { + nvicDisableVector(TIMER_32_0_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9); + } +#endif +#if LPC11xx_GPT_USE_CT32B1 + if (&GPTD4 == gptp) { + nvicDisableVector(TIMER_32_1_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10); + } +#endif + } +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @notapi + */ +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->MR0 = interval - 1; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 3; /* IRQ and clr TC on match MR0. */ + gptp->tmr->TCR = 2; /* Reset counter and prescaler. */ + gptp->tmr->TCR = 1; /* Timer enabled. */ +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop_timer(GPTDriver *gptp) { + + gptp->tmr->IR = 1; + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @notapi + */ +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->MR0 = interval - 1; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 4; /* Stop TC on match MR0. */ + gptp->tmr->TCR = 2; /* Reset counter and prescaler. */ + gptp->tmr->TCR = 1; /* Timer enabled. */ + while (gptp->tmr->TCR & 1) + ; +} + +#endif /* HAL_USE_GPT */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC11xx/gpt_lld.h b/Project/os/hal/platforms/LPC11xx/gpt_lld.h new file mode 100644 index 0000000..0c9ea8b --- /dev/null +++ b/Project/os/hal/platforms/LPC11xx/gpt_lld.h @@ -0,0 +1,215 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC11xx/gpt_lld.h + * @brief LPC11xx GPT subsystem low level driver header. + * + * @addtogroup GPT + * @{ + */ + +#ifndef _GPT_LLD_H_ +#define _GPT_LLD_H_ + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief GPT1 driver enable switch. + * @details If set to @p TRUE the support for GPT1 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC11xx_GPT_USE_CT16B0) || defined(__DOXYGEN__) +#define LPC11xx_GPT_USE_CT16B0 TRUE +#endif + +/** + * @brief GPT2 driver enable switch. + * @details If set to @p TRUE the support for GPT2 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC11xx_GPT_USE_CT16B1) || defined(__DOXYGEN__) +#define LPC11xx_GPT_USE_CT16B1 TRUE +#endif + +/** + * @brief GPT3 driver enable switch. + * @details If set to @p TRUE the support for GPT3 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC11xx_GPT_USE_CT32B0) || defined(__DOXYGEN__) +#define LPC11xx_GPT_USE_CT32B0 TRUE +#endif + +/** + * @brief GPT4 driver enable switch. + * @details If set to @p TRUE the support for GPT4 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC11xx_GPT_USE_CT32B1) || defined(__DOXYGEN__) +#define LPC11xx_GPT_USE_CT32B1 TRUE +#endif + +/** + * @brief GPT1 interrupt priority level setting. + */ +#if !defined(LPC11xx_GPT_CT16B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_GPT_CT16B0_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT2 interrupt priority level setting. + */ +#if !defined(LPC11xx_GPT_CT16B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_GPT_CT16B1_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT3 interrupt priority level setting. + */ +#if !defined(LPC11xx_GPT_CT32B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_GPT_CT32B0_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT4 interrupt priority level setting. + */ +#if !defined(LPC11xx_GPT_CT32B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_GPT_CT32B1_IRQ_PRIORITY 2 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !LPC11xx_GPT_USE_CT16B0 && !LPC11xx_GPT_USE_CT16B1 && \ + !LPC11xx_GPT_USE_CT32B0 && !LPC11xx_GPT_USE_CT32B1 +#error "GPT driver activated but no CT peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPT frequency type. + */ +typedef uint32_t gptfreq_t; + +/** + * @brief GPT counter type. + */ +typedef uint32_t gptcnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + gptfreq_t frequency; + /** + * @brief Timer callback pointer. + * @note This callback is invoked on GPT counter events. + */ + gptcallback_t callback; + /* End of the mandatory fields.*/ +} GPTConfig; + +/** + * @brief Structure representing a GPT driver. + */ +struct GPTDriver { + /** + * @brief Driver state. + */ + gptstate_t state; + /** + * @brief Current configuration data. + */ + const GPTConfig *config; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the CTxxBy registers block. + */ + LPC_TMR_TypeDef *tmr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC11xx_GPT_USE_CT16B0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD1; +#endif + +#if LPC11xx_GPT_USE_CT16B1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD2; +#endif + +#if LPC11xx_GPT_USE_CT32B0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD3; +#endif + +#if LPC11xx_GPT_USE_CT32B1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void gpt_lld_init(void); + void gpt_lld_start(GPTDriver *gptp); + void gpt_lld_stop(GPTDriver *gptp); + void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); + void gpt_lld_stop_timer(GPTDriver *gptp); + void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT */ + +#endif /* _GPT_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC11xx/hal_lld.c b/Project/os/hal/platforms/LPC11xx/hal_lld.c new file mode 100644 index 0000000..20fccdf --- /dev/null +++ b/Project/os/hal/platforms/LPC11xx/hal_lld.c @@ -0,0 +1,131 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC11xx/hal_lld.c + * @brief LPC11xx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/** + * @brief Register missing in NXP header file. + */ +#define FLASHCFG (*((volatile uint32_t *)0x4003C010)) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* SysTick initialization using the system clock.*/ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK); + SysTick->LOAD = LPC11xx_SYSCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief LPC11xx clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function must be invoked only after the system reset. + * + * @special + */ +void lpc111x_clock_init(void) { + unsigned i; + + /* Flash wait states setting, the code takes care to not touch TBD bits.*/ + FLASHCFG = (FLASHCFG & ~3) | LPC11xx_FLASHCFG_FLASHTIM; + + /* System oscillator initialization if required.*/ +#if LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT +#if LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC + LPC_SYSCON->SYSOSCCTRL = LPC11xx_SYSOSCCTRL; + LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* System oscillator ON. */ + for (i = 0; i < 200; i++) + __NOP(); /* Stabilization delay. */ +#endif /* LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC */ + + /* PLL initialization if required.*/ + LPC_SYSCON->SYSPLLCLKSEL = LPC11xx_PLLCLK_SOURCE; + LPC_SYSCON->SYSPLLCLKUEN = 1; /* Really required? */ + LPC_SYSCON->SYSPLLCLKUEN = 0; + LPC_SYSCON->SYSPLLCLKUEN = 1; + LPC_SYSCON->SYSPLLCTRL = LPC11xx_SYSPLLCTRL_MSEL | LPC11xx_SYSPLLCTRL_PSEL; + LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* System PLL ON. */ + while ((LPC_SYSCON->SYSPLLSTAT & 1) == 0) /* Wait PLL lock. */ + ; +#endif /* LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT */ + + /* Main clock source selection.*/ + LPC_SYSCON->MAINCLKSEL = LPC11xx_MAINCLK_SOURCE; + LPC_SYSCON->MAINCLKUEN = 1; /* Really required? */ + LPC_SYSCON->MAINCLKUEN = 0; + LPC_SYSCON->MAINCLKUEN = 1; + while ((LPC_SYSCON->MAINCLKUEN & 1) == 0) /* Wait switch completion. */ + ; + + /* ABH divider initialization, peripheral clocks are initially disabled, + the various device drivers will handle their own setup except GPIO and + IOCON that are left enabled.*/ + LPC_SYSCON->SYSAHBCLKDIV = LPC11xx_SYSABHCLK_DIV; + LPC_SYSCON->SYSAHBCLKCTRL = 0x0001005F; + + /* Memory remapping, vectors always in ROM.*/ + LPC_SYSCON->SYSMEMREMAP = 2; +} + +/** @} */ diff --git a/Project/os/hal/platforms/LPC11xx/hal_lld.h b/Project/os/hal/platforms/LPC11xx/hal_lld.h new file mode 100644 index 0000000..9025278 --- /dev/null +++ b/Project/os/hal/platforms/LPC11xx/hal_lld.h @@ -0,0 +1,230 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC11xx/hal_lld.h + * @brief HAL subsystem low level driver header template. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "LPC11xx.h" +#include "nvic.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "LPC11xx" + +#define IRCOSCCLK 12000000 /**< High speed internal clock. */ +#define WDGOSCCLK 1600000 /**< Watchdog internal clock. */ + +#define SYSPLLCLKSEL_IRCOSC 0 /**< Internal RC oscillator + clock source. */ +#define SYSPLLCLKSEL_SYSOSC 1 /**< System oscillator clock + source. */ + +#define SYSMAINCLKSEL_IRCOSC 0 /**< Clock source is IRC. */ +#define SYSMAINCLKSEL_PLLIN 1 /**< Clock source is PLLIN. */ +#define SYSMAINCLKSEL_WDGOSC 2 /**< Clock source is WDGOSC. */ +#define SYSMAINCLKSEL_PLLOUT 3 /**< Clock source is PLLOUT. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief System PLL clock source. + */ +#if !defined(LPC11xx_PLLCLK_SOURCE) || defined(__DOXYGEN__) +#define LPC11xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#endif + +/** + * @brief System PLL multiplier. + * @note The value must be in the 1..32 range and the final frequency + * must not exceed the CCO ratings. + */ +#if !defined(LPC11xx_SYSPLL_MUL) || defined(__DOXYGEN__) +#define LPC11xx_SYSPLL_MUL 4 +#endif + +/** + * @brief System PLL divider. + * @note The value must be chosen between (2, 4, 8, 16). + */ +#if !defined(LPC11xx_SYSPLL_DIV) || defined(__DOXYGEN__) +#define LPC11xx_SYSPLL_DIV 4 +#endif + +/** + * @brief System main clock source. + */ +#if !defined(LPC11xx_MAINCLK_SOURCE) || defined(__DOXYGEN__) +#define LPC11xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#endif + +/** + * @brief AHB clock divider. + * @note The value must be chosen between (1...255). + */ +#if !defined(LPC11xx_SYSCLK_DIV) || defined(__DOXYGEN__) +#define LPC11xx_SYSABHCLK_DIV 1 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** + * @brief Calculated SYSOSCCTRL setting. + */ +#if (SYSOSCCLK < 18000000) || defined(__DOXYGEN__) +#define LPC11xx_SYSOSCCTRL 0 +#else +#define LPC11xx_SYSOSCCTRL 1 +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__) +#define LPC11xx_SYSPLLCLKIN SYSOSCCLK +#elif LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOSC +#define LPC11xx_SYSPLLCLKIN IRCOSCCLK +#else +#error "invalid LPC11xx_PLLCLK_SOURCE clock source specified" +#endif + +/** + * @brief MSEL mask in SYSPLLCTRL register. + */ +#if (LPC11xx_SYSPLL_MUL >= 1) && (LPC11xx_SYSPLL_MUL <= 32) || \ + defined(__DOXYGEN__) +#define LPC11xx_SYSPLLCTRL_MSEL (LPC11xx_SYSPLL_MUL - 1) +#else +#error "LPC11xx_SYSPLL_MUL out of range (1...32)" +#endif + +/** + * @brief PSEL mask in SYSPLLCTRL register. + */ +#if (LPC11xx_SYSPLL_DIV == 2) || defined(__DOXYGEN__) +#define LPC11xx_SYSPLLCTRL_PSEL (0 << 5) +#elif LPC11xx_SYSPLL_DIV == 4 +#define LPC11xx_SYSPLLCTRL_PSEL (1 << 5) +#elif LPC11xx_SYSPLL_DIV == 8 +#define LPC11xx_SYSPLLCTRL_PSEL (2 << 5) +#elif LPC11xx_SYSPLL_DIV == 16 +#define LPC11xx_SYSPLLCTRL_PSEL (3 << 5) +#else +#error "invalid LPC11xx_SYSPLL_DIV value (2,4,8,16)" +#endif + +/** + * @brief CCP frequency. + */ +#define LPC11xx_SYSPLLCCO (LPC11xx_SYSPLLCLKIN * LPC11xx_SYSPLL_MUL * \ + LPC11xx_SYSPLL_DIV) + +#if (LPC11xx_SYSPLLCCO < 156000000) || (LPC11xx_SYSPLLCCO > 320000000) +#error "CCO frequency out of the acceptable range (156...320)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define LPC11xx_SYSPLLCLKOUT (LPC11xx_SYSPLLCCO / LPC11xx_SYSPLL_DIV) + +#if (LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOSC) || defined(__DOXYGEN__) +#define LPC11xx_MAINCLK IRCOSCCLK +#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN +#define LPC11xx_MAINCLK LPC11xx_SYSPLLCLKIN +#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC +#define LPC11xx_MAINCLK WDGOSCCLK +#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT +#define LPC11xx_MAINCLK LPC11xx_SYSPLLCLKOUT +#else +#error "invalid LPC11xx_MAINCLK_SOURCE clock source specified" +#endif + +/** + * @brief AHB clock. + */ +#define LPC11xx_SYSCLK (LPC11xx_MAINCLK / LPC11xx_SYSABHCLK_DIV) +#if LPC11xx_SYSCLK > 50000000 +#error "AHB clock frequency out of the acceptable range (50MHz max)" +#endif + +/** + * @brief Flash wait states. + */ +#if (LPC11xx_SYSCLK <= 20000000) || defined(__DOXYGEN__) +#define LPC11xx_FLASHCFG_FLASHTIM 0 +#elif LPC11xx_SYSCLK <= 40000000 +#define LPC11xx_FLASHCFG_FLASHTIM 1 +#else +#define LPC11xx_FLASHCFG_FLASHTIM 2 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void lpc111x_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC11xx/pal_lld.c b/Project/os/hal/platforms/LPC11xx/pal_lld.c new file mode 100644 index 0000000..bb3c7cb --- /dev/null +++ b/Project/os/hal/platforms/LPC11xx/pal_lld.c @@ -0,0 +1,114 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC11xx/pal_lld.c + * @brief LPC11xx GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ +/** + * @brief LPC11xx I/O ports configuration. + * @details GPIO unit registers initialization. + * + * @param[in] config the LPC11xx ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + LPC_GPIO0->DIR = config->P0.dir; + LPC_GPIO1->DIR = config->P1.dir; + LPC_GPIO2->DIR = config->P2.dir; + LPC_GPIO3->DIR = config->P3.dir; + LPC_GPIO0->DATA = config->P0.data; + LPC_GPIO1->DATA = config->P1.data; + LPC_GPIO2->DATA = config->P2.data; + LPC_GPIO3->DATA = config->P3.data; +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with + * high state. + * @note This function does not alter the @p PINSELx registers. Alternate + * functions setup must be handled by device-specific code. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + port->DIR &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + palSetPort(port, PAL_WHOLE_PORT); + case PAL_MODE_OUTPUT_PUSHPULL: + port->DIR |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC11xx/pal_lld.h b/Project/os/hal/platforms/LPC11xx/pal_lld.h new file mode 100644 index 0000000..4fbf6a4 --- /dev/null +++ b/Project/os/hal/platforms/LPC11xx/pal_lld.h @@ -0,0 +1,327 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC11xx/pal_lld.h + * @brief LPC11xx GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief GPIO port setup info. + */ +typedef struct { + /** Initial value for FIO_PIN register.*/ + uint32_t data; + /** Initial value for FIO_DIR register.*/ + uint32_t dir; +} lpc111x_gpio_setup_t; + +/** + * @brief GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + * @note The @p IOCON block is not configured, initially all pins have + * enabled pullups and are programmed as GPIO. It is responsibility + * of the various drivers to reprogram the pins in the proper mode. + * Pins that are not handled by any driver may be programmed in + * @p board.c. + */ +typedef struct { + /** @brief GPIO 0 setup data.*/ + lpc111x_gpio_setup_t P0; + /** @brief GPIO 1 setup data.*/ + lpc111x_gpio_setup_t P1; + /** @brief GPIO 2 setup data.*/ + lpc111x_gpio_setup_t P2; + /** @brief GPIO 3 setup data.*/ + lpc111x_gpio_setup_t P3; +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 32 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + */ +typedef LPC_GPIO_TypeDef *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief GPIO0 port identifier. + */ +#define IOPORT1 LPC_GPIO0 +#define GPIO0 LPC_GPIO0 + +/** + * @brief GPIO1 port identifier. + */ +#define IOPORT2 LPC_GPIO1 +#define GPIO1 LPC_GPIO1 + +/** + * @brief GPIO2 port identifier. + */ +#define IOPORT3 LPC_GPIO2 +#define GPIO2 LPC_GPIO2 + +/** + * @brief GPIO3 port identifier. + */ +#define IOPORT4 LPC_GPIO3 +#define GPIO3 LPC_GPIO3 + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->DATA) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->DATA) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->DATA = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) ((port)->MASKED_ACCESS[bits] = 0xFFFFFFFF) + +/** + * @brief Clears a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) ((port)->MASKED_ACCESS[bits] = 0) + +/** + * @brief Reads a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @notapi + */ +#define pal_lld_readgroup(port, mask, offset) \ + ((port)->MASKED_ACCESS[(mask) << (offset)]) + +/** + * @brief Writes a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) \ + ((port)->MASKED_ACCESS[(mask) << (pad)] = (bit) << (pad)) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) \ + ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad)) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) \ + ((port)->MASKED_ACCESS[1 << (pad)] = 0) + +#if !defined(__DOXYGEN__) +extern const PALConfig pal_default_config; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC11xx/platform.dox b/Project/os/hal/platforms/LPC11xx/platform.dox new file mode 100644 index 0000000..cd2a28f --- /dev/null +++ b/Project/os/hal/platforms/LPC11xx/platform.dox @@ -0,0 +1,147 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup LPC11xx LPC11xx Drivers + * @details This section describes all the supported drivers on the LPC11xx + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup LPC11xx_HAL LPC11xx Initialization Support + * @details The LPC11xx HAL support is responsible for system initialization. + * + * @section lpc11xx_hal_1 Supported HW resources + * - SYSCON. + * - Flash. + * . + * @section lpc11xx_hal_2 LPC11xx HAL driver implementation features + * - Clock tree initialization. + * - Clock source selection. + * - Flash controller initialization. + * - SYSTICK initialization based on current clock and kernel required rate. + * . + * @ingroup LPC11xx + */ + +/** + * @defgroup LPC11xx_GPT LPC11xx GPT Support + * @details The LPC11xx GPT driver uses the CTxxBy peripherals. + * + * @section lpc11xx_gpt_1 Supported HW resources + * - CT16B0. + * - CT16B1. + * - CT32B0. + * - CT32B1. + * . + * @section lpc11xx_gpt_2 LPC11xx GPT driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable CTxxBy interrupts priority level. + * . + * @ingroup LPC11xx + */ + +/** + * @defgroup LPC11xx_PAL LPC11xx PAL Support + * @details The LPC11xx PAL driver uses the GPIO peripherals. + * + * @section lpc11xx_pal_1 Supported HW resources + * - GPIO0. + * - GPIO1. + * - GPIO2. + * - GPIO3. + * . + * @section lpc11xx_pal_2 LPC11xx PAL driver implementation features + * - 12 bits wide ports. + * - Atomic set/reset functions. + * - Atomic set+reset function (atomic bus operations). + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section lpc11xx_pal_3 Supported PAL setup modes + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section lpc11xx_pal_4 Suboptimal behavior + * Some GPIO features are less than optimal: + * - Pad/port toggling operations are not atomic. + * - Pull-up and Pull-down resistors cannot be programmed through the PAL + * driver and must be programmed separately using the IOCON peripheral. + * - Reading of the output latch for pads programmed as input is not possible, + * the input pin value is returned instead. + * . + * @ingroup LPC11xx + */ + +/** + * @defgroup LPC11xx_SERIAL LPC11xx Serial Support + * @details The LPC11xx Serial driver uses the UART peripheral in a + * buffered, interrupt driven, implementation. The serial driver + * also takes advantage of the LPC11xx UARTs deep hardware buffers. + * + * @section lpc11xx_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - UART. + * . + * @section lpc11xx_serial_2 LPC11xx Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Fully interrupt driven. + * - Programmable priority level. + * - Takes advantage of the input and output FIFOs. + * . + * @ingroup LPC11xx + */ + +/** + * @defgroup LPC11xx_SPI LPC11xx SPI Support + * @details The SPI driver supports the LPC11xx SSP peripherals in an interrupt + * driven implementation. + * @note Being the SPI a fast peripheral, much care must be taken to + * not saturate the CPU bandwidth with an excessive IRQ rate. The + * maximum transfer bit rate is likely limited by the IRQ + * handling. + * + * @section lpc11xx_spi_1 Supported HW resources + * - SSP0. + * - SSP1 (where present). + * . + * @section lpc11xx_spi_2 LPC11xx SPI driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each SSP can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * - Programmable interrupt priority levels for each SSP. + * . + * @ingroup LPC11xx + */ diff --git a/Project/os/hal/platforms/LPC11xx/platform.mk b/Project/os/hal/platforms/LPC11xx/platform.mk new file mode 100644 index 0000000..4f0d195 --- /dev/null +++ b/Project/os/hal/platforms/LPC11xx/platform.mk @@ -0,0 +1,9 @@ +# List of all the LPC11xx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC11xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11xx/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11xx/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11xx/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11xx/spi_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC11xx diff --git a/Project/os/hal/platforms/LPC11xx/serial_lld.c b/Project/os/hal/platforms/LPC11xx/serial_lld.c new file mode 100644 index 0000000..6b4d313 --- /dev/null +++ b/Project/os/hal/platforms/LPC11xx/serial_lld.c @@ -0,0 +1,309 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC11xx/serial_lld.c + * @brief LPC11xx low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if LPC11xx_SERIAL_USE_UART0 || defined(__DOXYGEN__) +/** @brief UART0 serial driver identifier.*/ +SerialDriver SD1; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = { + SERIAL_DEFAULT_BITRATE, + LCR_WL8 | LCR_STOP1 | LCR_NOPARITY, + FCR_TRIGGER0 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief UART initialization. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] config the architecture-dependent serial driver configuration + */ +static void uart_init(SerialDriver *sdp, const SerialConfig *config) { + LPC_UART_TypeDef *u = sdp->uart; + + uint32_t div = LPC11xx_SERIAL_UART0_PCLK / (config->sc_speed << 4); + u->LCR = config->sc_lcr | LCR_DLAB; + u->DLL = div; + u->DLM = div >> 8; + u->LCR = config->sc_lcr; + u->FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | config->sc_fcr; + u->ACR = 0; + u->FDR = 0x10; + u->TER = TER_ENABLE; + u->IER = IER_RBR | IER_STATUS; +} + +/** + * @brief UART de-initialization. + * + * @param[in] u pointer to an UART I/O block + */ +static void uart_deinit(LPC_UART_TypeDef *u) { + + u->LCR = LCR_DLAB; + u->DLL = 1; + u->DLM = 0; + u->LCR = 0; + u->FDR = 0x10; + u->IER = 0; + u->FCR = FCR_RXRESET | FCR_TXRESET; + u->ACR = 0; + u->TER = TER_ENABLE; +} + +/** + * @brief Error handling routine. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] err UART LSR register value + */ +static void set_error(SerialDriver *sdp, IOREG32 err) { + ioflags_t sts = 0; + + if (err & LSR_OVERRUN) + sts |= SD_OVERRUN_ERROR; + if (err & LSR_PARITY) + sts |= SD_PARITY_ERROR; + if (err & LSR_FRAMING) + sts |= SD_FRAMING_ERROR; + if (err & LSR_BREAK) + sts |= SD_BREAK_DETECTED; + chSysLockFromIsr(); + chIOAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +/** + * @brief Common IRQ handler. + * @note Tries hard to clear all the pending interrupt sources, we don't + * want to go through the whole ISR and have another interrupt soon + * after. + * + * @param[in] u pointer to an UART I/O block + * @param[in] sdp communication channel associated to the UART + */ +static void serve_interrupt(SerialDriver *sdp) { + LPC_UART_TypeDef *u = sdp->uart; + + while (TRUE) { + switch (u->IIR & IIR_SRC_MASK) { + case IIR_SRC_NONE: + return; + case IIR_SRC_ERROR: + set_error(sdp, u->LSR); + break; + case IIR_SRC_TIMEOUT: + case IIR_SRC_RX: + chSysLockFromIsr(); + if (chIQIsEmptyI(&sdp->iqueue)) + chIOAddFlagsI(sdp, IO_INPUT_AVAILABLE); + chSysUnlockFromIsr(); + while (u->LSR & LSR_RBR_FULL) { + chSysLockFromIsr(); + if (chIQPutI(&sdp->iqueue, u->RBR) < Q_OK) + chIOAddFlagsI(sdp, SD_OVERRUN_ERROR); + chSysUnlockFromIsr(); + } + break; + case IIR_SRC_TX: + { + int i = LPC11xx_SERIAL_FIFO_PRELOAD; + do { + msg_t b; + + chSysLockFromIsr(); + b = chOQGetI(&sdp->oqueue); + chSysUnlockFromIsr(); + if (b < Q_OK) { + u->IER &= ~IER_THRE; + chSysLockFromIsr(); + chIOAddFlagsI(sdp, IO_OUTPUT_EMPTY); + chSysUnlockFromIsr(); + break; + } + u->THR = b; + } while (--i); + } + break; + default: + (void) u->THR; + (void) u->RBR; + } + } +} + +/** + * @brief Attempts a TX FIFO preload. + */ +static void preload(SerialDriver *sdp) { + LPC_UART_TypeDef *u = sdp->uart; + + if (u->LSR & LSR_THRE) { + int i = LPC11xx_SERIAL_FIFO_PRELOAD; + do { + msg_t b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) { + chIOAddFlagsI(sdp, IO_OUTPUT_EMPTY); + return; + } + u->THR = b; + } while (--i); + } + u->IER |= IER_THRE; +} + +/** + * @brief Driver SD1 output notification. + */ +#if LPC11xx_SERIAL_USE_UART0 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + preload(&SD1); +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief UART0 IRQ handler. + * + * @isr + */ +#if LPC11xx_SERIAL_USE_UART0 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(Vector94) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD1); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if LPC11xx_SERIAL_USE_UART0 + sdObjectInit(&SD1, NULL, notify1); + SD1.uart = LPC_UART; + LPC_IOCON->PIO1_6 = 0xC1; /* RDX without resistors. */ + LPC_IOCON->PIO1_7 = 0xC1; /* TDX without resistors. */ +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + + if (sdp->state == SD_STOP) { +#if LPC11xx_SERIAL_USE_UART0 + if (&SD1 == sdp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12); + LPC_SYSCON->UARTCLKDIV = LPC11xx_SERIAL_UART0CLKDIV; + nvicEnableVector(UART_IRQn, + CORTEX_PRIORITY_MASK(LPC11xx_SERIAL_UART0_IRQ_PRIORITY)); + } +#endif + } + uart_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the UART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) { + uart_deinit(sdp->uart); +#if LPC11xx_SERIAL_USE_UART0 + if (&SD1 == sdp) { + LPC_SYSCON->UARTCLKDIV = 0; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 12); + nvicDisableVector(UART_IRQn); + return; + } +#endif + } +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC11xx/serial_lld.h b/Project/os/hal/platforms/LPC11xx/serial_lld.h new file mode 100644 index 0000000..2a29879 --- /dev/null +++ b/Project/os/hal/platforms/LPC11xx/serial_lld.h @@ -0,0 +1,217 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC11xx/serial_lld.h + * @brief LPC11xx low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define IIR_SRC_MASK 0x0F +#define IIR_SRC_NONE 0x01 +#define IIR_SRC_MODEM 0x00 +#define IIR_SRC_TX 0x02 +#define IIR_SRC_RX 0x04 +#define IIR_SRC_ERROR 0x06 +#define IIR_SRC_TIMEOUT 0x0C + +#define IER_RBR 1 +#define IER_THRE 2 +#define IER_STATUS 4 + +#define LCR_WL5 0 +#define LCR_WL6 1 +#define LCR_WL7 2 +#define LCR_WL8 3 +#define LCR_STOP1 0 +#define LCR_STOP2 4 +#define LCR_NOPARITY 0 +#define LCR_PARITYODD 0x08 +#define LCR_PARITYEVEN 0x18 +#define LCR_PARITYONE 0x28 +#define LCR_PARITYZERO 0x38 +#define LCR_BREAK_ON 0x40 +#define LCR_DLAB 0x80 + +#define FCR_ENABLE 1 +#define FCR_RXRESET 2 +#define FCR_TXRESET 4 +#define FCR_TRIGGER0 0 +#define FCR_TRIGGER1 0x40 +#define FCR_TRIGGER2 0x80 +#define FCR_TRIGGER3 0xC0 + +#define LSR_RBR_FULL 1 +#define LSR_OVERRUN 2 +#define LSR_PARITY 4 +#define LSR_FRAMING 8 +#define LSR_BREAK 0x10 +#define LSR_THRE 0x20 +#define LSR_TEMT 0x40 +#define LSR_RXFE 0x80 + +#define TER_ENABLE 0x80 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief UART0 driver enable switch. + * @details If set to @p TRUE the support for UART0 is included. + * @note The default is @p TRUE . + */ +#if !defined(LPC11xx_SERIAL_USE_UART0) || defined(__DOXYGEN__) +#define LPC11xx_SERIAL_USE_UART0 TRUE +#endif + +/** + * @brief FIFO preload parameter. + * @details Configuration parameter, this values defines how many bytes are + * preloaded in the HW transmit FIFO for each interrupt, the maximum + * value is 16 the minimum is 1. + * @note An high value reduces the number of interrupts generated but can + * also increase the worst case interrupt response time because the + * preload loops. + */ +#if !defined(LPC11xx_SERIAL_FIFO_PRELOAD) || defined(__DOXYGEN__) +#define LPC11xx_SERIAL_FIFO_PRELOAD 16 +#endif + +/** + * @brief UART0 PCLK divider. + */ +#if !defined(LPC11xx_SERIAL_UART0CLKDIV) || defined(__DOXYGEN__) +#define LPC11xx_SERIAL_UART0CLKDIV 1 +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(LPC11xx_SERIAL_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_SERIAL_UART0_IRQ_PRIORITY 3 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (LPC11xx_SERIAL_UART0CLKDIV < 1) || (LPC11xx_SERIAL_UART0CLKDIV > 255) +#error "invalid LPC11xx_SERIAL_UART0CLKDIV setting" +#endif + +#if (LPC11xx_SERIAL_FIFO_PRELOAD < 1) || (LPC11xx_SERIAL_FIFO_PRELOAD > 16) +#error "invalid LPC11xx_SERIAL_FIFO_PRELOAD setting" +#endif + +/** + * @brief UART0 clock. + */ +#define LPC11xx_SERIAL_UART0_PCLK \ + (LPC11xx_MAINCLK / LPC11xx_SERIAL_UART0CLKDIV) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief LPC11xx Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t sc_speed; + /** + * @brief Initialization value for the LCR register. + */ + uint32_t sc_lcr; + /** + * @brief Initialization value for the FCR register. + */ + uint32_t sc_fcr; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the USART registers block.*/ \ + LPC_UART_TypeDef *uart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC11xx_SERIAL_USE_UART0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC11xx/spi_lld.c b/Project/os/hal/platforms/LPC11xx/spi_lld.c new file mode 100644 index 0000000..bac1825 --- /dev/null +++ b/Project/os/hal/platforms/LPC11xx/spi_lld.c @@ -0,0 +1,415 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC11xx/spi_lld.c + * @brief LPC11xx low level SPI driver code. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if LPC11xx_SPI_USE_SSP0 || defined(__DOXYGEN__) +/** @brief SPI1 driver identifier.*/ +SPIDriver SPID1; +#endif + +#if LPC11xx_SPI_USE_SSP1 || defined(__DOXYGEN__) +/** @brief SPI2 driver identifier.*/ +SPIDriver SPID2; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Preloads the transmit FIFO. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void ssp_fifo_preload(SPIDriver *spip) { + LPC_SSP_TypeDef *ssp = spip->ssp; + uint32_t n = spip->txcnt > LPC11xx_SSP_FIFO_DEPTH ? + LPC11xx_SSP_FIFO_DEPTH : spip->txcnt; + + while(((ssp->SR & SR_TNF) != 0) && (n > 0)) { + if (spip->txptr != NULL) { + if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) { + const uint16_t *p = spip->txptr; + ssp->DR = *p++; + spip->txptr = p; + } + else { + const uint8_t *p = spip->txptr; + ssp->DR = *p++; + spip->txptr = p; + } + } + else + ssp->DR = 0xFFFFFFFF; + n--; + spip->txcnt--; + } +} + +/** + * @brief Common IRQ handler. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void spi_serve_interrupt(SPIDriver *spip) { + LPC_SSP_TypeDef *ssp = spip->ssp; + + if ((ssp->MIS & MIS_ROR) != 0) { + /* The overflow condition should never happen because priority is given + to receive but a hook macro is provided anyway...*/ + LPC11xx_SPI_SSP_ERROR_HOOK(spip); + } + ssp->ICR = ICR_RT | ICR_ROR; + while ((ssp->SR & SR_RNE) != 0) { + if (spip->rxptr != NULL) { + if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) { + uint16_t *p = spip->rxptr; + *p++ = ssp->DR; + spip->rxptr = p; + } + else { + uint8_t *p = spip->rxptr; + *p++ = ssp->DR; + spip->rxptr = p; + } + } + else + (void)ssp->DR; + if (--spip->rxcnt == 0) { + chDbgAssert(spip->txcnt == 0, + "spi_serve_interrupt(), #1", "counter out of synch"); + /* Stops the IRQ sources.*/ + ssp->IMSC = 0; + /* Portable SPI ISR code defined in the high level driver, note, it is + a macro.*/ + _spi_isr_code(spip); + return; + } + } + ssp_fifo_preload(spip); + if (spip->txcnt == 0) + ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_RX; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC11xx_SPI_USE_SSP0 || defined(__DOXYGEN__) +/** + * @brief SSP0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector90) { + + CH_IRQ_PROLOGUE(); + + spi_serve_interrupt(&SPID1); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if LPC11xx_SPI_USE_SSP1 || defined(__DOXYGEN__) +/** + * @brief SSP1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector78) { + + CH_IRQ_PROLOGUE(); + + spi_serve_interrupt(&SPID2); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +#if LPC11xx_SPI_USE_SSP0 + spiObjectInit(&SPID1); + SPID1.ssp = LPC_SSP0; + LPC_IOCON->SCK_LOC = LPC11xx_SPI_SCK0_SELECTOR; +#if LPC11xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO0_10 + LPC_IOCON->JTAG_TCK_PIO0_10 = 0xC2; /* SCK0 without resistors. */ +#elif LPC11xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO2_11 + LPC_IOCON->PIO2_11 = 0xC1; /* SCK0 without resistors. */ +#else /* LPC11xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO0_6 */ + LPC_IOCON->PIO0_6 = 0xC2; /* SCK0 without resistors. */ +#endif + LPC_IOCON->PIO0_8 = 0xC1; /* MISO0 without resistors. */ + LPC_IOCON->PIO0_9 = 0xC1; /* MOSI0 without resistors. */ +#endif /* LPC11xx_SPI_USE_SSP0 */ + +#if LPC11xx_SPI_USE_SSP1 + spiObjectInit(&SPID2); + SPID2.ssp = LPC_SSP1; + LPC_IOCON->PIO2_1 = 0xC2; /* SCK1 without resistors. */ + LPC_IOCON->PIO2_2 = 0xC2; /* MISO1 without resistors. */ + LPC_IOCON->PIO2_3 = 0xC2; /* MOSI1 without resistors. */ +#endif /* LPC11xx_SPI_USE_SSP0 */ +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + if (spip->state == SPI_STOP) { + /* Clock activation.*/ +#if LPC11xx_SPI_USE_SSP0 + if (&SPID1 == spip) { + LPC_SYSCON->SSP0CLKDIV = LPC11xx_SPI_SSP0CLKDIV; + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 11); + LPC_SYSCON->PRESETCTRL |= 1; + nvicEnableVector(SSP0_IRQn, + CORTEX_PRIORITY_MASK(LPC11xx_SPI_SSP0_IRQ_PRIORITY)); + } +#endif +#if LPC11xx_SPI_USE_SSP1 + if (&SPID2 == spip) { + LPC_SYSCON->SSP1CLKDIV = LPC11xx_SPI_SSP1CLKDIV; + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 18); + LPC_SYSCON->PRESETCTRL |= 4; + nvicEnableVector(SSP1_IRQn, + CORTEX_PRIORITY_MASK(LPC11xx_SPI_SSP1_IRQ_PRIORITY)); + } +#endif + } + /* Configuration.*/ + spip->ssp->CR1 = 0; + spip->ssp->ICR = ICR_RT | ICR_ROR; + spip->ssp->CR0 = spip->config->cr0; + spip->ssp->CPSR = spip->config->cpsr; + spip->ssp->CR1 = CR1_SSE; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + if (spip->state != SPI_STOP) { + spip->ssp->CR1 = 0; + spip->ssp->CR0 = 0; + spip->ssp->CPSR = 0; +#if LPC11xx_SPI_USE_SSP0 + if (&SPID1 == spip) { + LPC_SYSCON->PRESETCTRL &= ~1; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 11); + LPC_SYSCON->SSP0CLKDIV = 0; + nvicDisableVector(SSP0_IRQn); + } +#endif +#if LPC11xx_SPI_USE_SSP1 + if (&SPID2 == spip) { + LPC_SYSCON->PRESETCTRL &= ~4; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 18); + LPC_SYSCON->SSP1CLKDIV = 0; + nvicDisableVector(SSP1_IRQn); + } +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This function transmits a series of idle words on the SPI bus and + * ignores the received data. This function can be invoked even + * when a slave select signal has not been yet asserted. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + spip->rxptr = NULL; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + spip->rxptr = NULL; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + spip->ssp->DR = (uint32_t)frame; + while ((spip->ssp->SR & SR_RNE) == 0) + ; + return (uint16_t)spip->ssp->DR; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC11xx/spi_lld.h b/Project/os/hal/platforms/LPC11xx/spi_lld.h new file mode 100644 index 0000000..da8e07c --- /dev/null +++ b/Project/os/hal/platforms/LPC11xx/spi_lld.h @@ -0,0 +1,350 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC11xx/spi_lld.h + * @brief LPC11xx low level SPI driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Hardware FIFO depth. + */ +#define LPC11xx_SSP_FIFO_DEPTH 8 + +#define CR0_DSSMASK 0x0F +#define CR0_DSS4BIT 3 +#define CR0_DSS5BIT 4 +#define CR0_DSS6BIT 5 +#define CR0_DSS7BIT 6 +#define CR0_DSS8BIT 7 +#define CR0_DSS9BIT 8 +#define CR0_DSS10BIT 9 +#define CR0_DSS11BIT 0xA +#define CR0_DSS12BIT 0xB +#define CR0_DSS13BIT 0xC +#define CR0_DSS14BIT 0xD +#define CR0_DSS15BIT 0xE +#define CR0_DSS16BIT 0xF +#define CR0_FRFSPI 0 +#define CR0_FRFSSI 0x10 +#define CR0_FRFMW 0x20 +#define CR0_CPOL 0x40 +#define CR0_CPHA 0x80 +#define CR0_CLOCKRATE(n) ((n) << 8) + +#define CR1_LBM 1 +#define CR1_SSE 2 +#define CR1_MS 4 +#define CR1_SOD 8 + +#define SR_TFE 1 +#define SR_TNF 2 +#define SR_RNE 4 +#define SR_RFF 8 +#define SR_BSY 16 + +#define IMSC_ROR 1 +#define IMSC_RT 2 +#define IMSC_RX 4 +#define IMSC_TX 8 + +#define RIS_ROR 1 +#define RIS_RT 2 +#define RIS_RX 4 +#define RIS_TX 8 + +#define MIS_ROR 1 +#define MIS_RT 2 +#define MIS_RX 4 +#define MIS_TX 8 + +#define ICR_ROR 1 +#define ICR_RT 2 + +/** + * @brief SCK0 signal assigned to pin PIO0_10. + */ +#define SCK0_IS_PIO0_10 0 + +/** + * @brief SCK0 signal assigned to pin PIO2_11. + */ +#define SCK0_IS_PIO2_11 1 + +/** + * @brief SCK0 signal assigned to pin PIO0_6. + */ +#define SCK0_IS_PIO0_6 2 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for device SSP0 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC11xx_SPI_USE_SSP0) || defined(__DOXYGEN__) +#define LPC11xx_SPI_USE_SSP0 TRUE +#endif + +/** + * @brief SPI2 driver enable switch. + * @details If set to @p TRUE the support for device SSP1 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC11xx_SPI_USE_SSP1) || defined(__DOXYGEN__) +#define LPC11xx_SPI_USE_SSP1 TRUE +#endif + +/** + * @brief SSP0 PCLK divider. + */ +#if !defined(LPC11xx_SPI_SSP0CLKDIV) || defined(__DOXYGEN__) +#define LPC11xx_SPI_SSP0CLKDIV 1 +#endif + +/** + * @brief SSP1 PCLK divider. + */ +#if !defined(LPC11xx_SPI_SSP1CLKDIV) || defined(__DOXYGEN__) +#define LPC11xx_SPI_SSP1CLKDIV 1 +#endif + +/** + * @brief SPI0 interrupt priority level setting. + */ +#if !defined(LPC11xx_SPI_SSP0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_SPI_SSP0_IRQ_PRIORITY 1 +#endif + +/** + * @brief SPI1 interrupt priority level setting. + */ +#if !defined(LPC11xx_SPI_SSP1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC11xx_SPI_SSP1_IRQ_PRIORITY 1 +#endif + +/** + * @brief Overflow error hook. + * @details The default action is to stop the system. + */ +#if !defined(LPC11xx_SPI_SSP_ERROR_HOOK) || defined(__DOXYGEN__) +#define LPC11xx_SPI_SSP_ERROR_HOOK(spip) chSysHalt() +#endif + +/** + * @brief SCK0 signal selector. + */ +#if !defined(LPC11xx_SPI_SCK0_SELECTOR) || defined(__DOXYGEN__) +#define LPC11xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (LPC11xx_SPI_SSP0CLKDIV < 1) || (LPC11xx_SPI_SSP0CLKDIV > 255) +#error "invalid LPC11xx_SPI_SSP0CLKDIV setting" +#endif + +#if (LPC11xx_SPI_SSP1CLKDIV < 1) || (LPC11xx_SPI_SSP1CLKDIV > 255) +#error "invalid LPC11xx_SPI_SSP1CLKDIV setting" +#endif + +#if !LPC11xx_SPI_USE_SSP0 && !LPC11xx_SPI_USE_SSP1 +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +#if (LPC11xx_SPI_SCK0_SELECTOR != SCK0_IS_PIO0_10) && \ + (LPC11xx_SPI_SCK0_SELECTOR != SCK0_IS_PIO2_11) && \ + (LPC11xx_SPI_SCK0_SELECTOR != SCK0_IS_PIO0_6) +#error "invalid pin assigned to SCK0 signal" +#endif + +/** + * @brief SSP0 clock. + */ +#define LPC11xx_SERIAL_SSP0_PCLK \ + (LPC11xx_MAINCLK / LPC11xx_SERIAL_SSP0CLKDIV) + +/** + * @brief SSP1 clock. + */ +#define LPC11xx_SERIAL_SSP1_PCLK \ + (LPC11xx_MAINCLK / LPC11xx_SERIAL_SSP1CLKDIV) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief SSP CR0 initialization data. + */ + uint16_t cr0; + /** + * @brief SSP CPSR initialization data. + */ + uint32_t cpsr; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SSP registers block. + */ + LPC_SSP_TypeDef *ssp; + /** + * @brief Number of bytes yet to be received. + */ + uint32_t rxcnt; + /** + * @brief Receive pointer or @p NULL. + */ + void *rxptr; + /** + * @brief Number of bytes yet to be transmitted. + */ + uint32_t txcnt; + /** + * @brief Transmit pointer or @p NULL. + */ + const void *txptr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC11xx_SPI_USE_SSP0 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#if LPC11xx_SPI_USE_SSP1 && !defined(__DOXYGEN__) +extern SPIDriver SPID2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC11xx/system_LPC11xx.h b/Project/os/hal/platforms/LPC11xx/system_LPC11xx.h new file mode 100644 index 0000000..385fe38 --- /dev/null +++ b/Project/os/hal/platforms/LPC11xx/system_LPC11xx.h @@ -0,0 +1,64 @@ +/**************************************************************************//** + * @file system_LPC11xx.h + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File + * for the NXP LPC11xx Device Series + * @version V1.00 + * @date 17. November 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __SYSTEM_LPC11xx_H +#define __SYSTEM_LPC11xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_LPC11x_H */ diff --git a/Project/os/hal/platforms/LPC13xx/LPC13xx.h b/Project/os/hal/platforms/LPC13xx/LPC13xx.h new file mode 100644 index 0000000..e428164 --- /dev/null +++ b/Project/os/hal/platforms/LPC13xx/LPC13xx.h @@ -0,0 +1,493 @@ +/**************************************************************************//** + * @file LPC13xx.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for + * NXP LPC13xx Device Series + * @version V1.01 + * @date 19. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __LPC13xx_H__ +#define __LPC13xx_H__ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** LPC13xx Specific Interrupt Numbers *******************************************************/ + WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */ + WAKEUP1_IRQn = 1, /*!< There are 40 pins in total for LPC17xx */ + WAKEUP2_IRQn = 2, + WAKEUP3_IRQn = 3, + WAKEUP4_IRQn = 4, + WAKEUP5_IRQn = 5, + WAKEUP6_IRQn = 6, + WAKEUP7_IRQn = 7, + WAKEUP8_IRQn = 8, + WAKEUP9_IRQn = 9, + WAKEUP10_IRQn = 10, + WAKEUP11_IRQn = 11, + WAKEUP12_IRQn = 12, + WAKEUP13_IRQn = 13, + WAKEUP14_IRQn = 14, + WAKEUP15_IRQn = 15, + WAKEUP16_IRQn = 16, + WAKEUP17_IRQn = 17, + WAKEUP18_IRQn = 18, + WAKEUP19_IRQn = 19, + WAKEUP20_IRQn = 20, + WAKEUP21_IRQn = 21, + WAKEUP22_IRQn = 22, + WAKEUP23_IRQn = 23, + WAKEUP24_IRQn = 24, + WAKEUP25_IRQn = 25, + WAKEUP26_IRQn = 26, + WAKEUP27_IRQn = 27, + WAKEUP28_IRQn = 28, + WAKEUP29_IRQn = 29, + WAKEUP30_IRQn = 30, + WAKEUP31_IRQn = 31, + WAKEUP32_IRQn = 32, + WAKEUP33_IRQn = 33, + WAKEUP34_IRQn = 34, + WAKEUP35_IRQn = 35, + WAKEUP36_IRQn = 36, + WAKEUP37_IRQn = 37, + WAKEUP38_IRQn = 38, + WAKEUP39_IRQn = 39, + I2C_IRQn = 40, /*!< I2C Interrupt */ + TIMER_16_0_IRQn = 41, /*!< 16-bit Timer0 Interrupt */ + TIMER_16_1_IRQn = 42, /*!< 16-bit Timer1 Interrupt */ + TIMER_32_0_IRQn = 43, /*!< 32-bit Timer0 Interrupt */ + TIMER_32_1_IRQn = 44, /*!< 32-bit Timer1 Interrupt */ + SSP_IRQn = 45, /*!< SSP Interrupt */ + UART_IRQn = 46, /*!< UART Interrupt */ + USB_IRQn = 47, /*!< USB Regular Interrupt */ + USB_FIQn = 48, /*!< USB Fast Interrupt */ + ADC_IRQn = 49, /*!< A/D Converter Interrupt */ + WDT_IRQn = 50, /*!< Watchdog timer Interrupt */ + BOD_IRQn = 51, /*!< Brown Out Detect(BOD) Interrupt */ + EINT3_IRQn = 53, /*!< External Interrupt 3 Interrupt */ + EINT2_IRQn = 54, /*!< External Interrupt 2 Interrupt */ + EINT1_IRQn = 55, /*!< External Interrupt 1 Interrupt */ + EINT0_IRQn = 56, /*!< External Interrupt 0 Interrupt */ +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M3 Processor and Core Peripherals */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + + +#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ +#include "system_LPC13xx.h" /* System Header */ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/*------------- System Control (SYSCON) --------------------------------------*/ +typedef struct +{ + __IO uint32_t SYSMEMREMAP; /* Sys mem. Remap, Offset 0x0 */ + __IO uint32_t PRESETCTRL; + __IO uint32_t SYSPLLCTRL; /* Sys PLL control */ + __IO uint32_t SYSPLLSTAT; + __IO uint32_t USBPLLCTRL; /* USB PLL control, offset 0x10 */ + __IO uint32_t USBPLLSTAT; + uint32_t RESERVED0[2]; + + __IO uint32_t SYSOSCCTRL; /* Offset 0x20 */ + __IO uint32_t WDTOSCCTRL; + __IO uint32_t IRCCTRL; + uint32_t RESERVED1[1]; + __IO uint32_t SYSRESSTAT; /* Offset 0x30 */ + uint32_t RESERVED2[3]; + __IO uint32_t SYSPLLCLKSEL; /* Offset 0x40 */ + __IO uint32_t SYSPLLCLKUEN; + __IO uint32_t USBPLLCLKSEL; + __IO uint32_t USBPLLCLKUEN; + uint32_t RESERVED3[8]; + + __IO uint32_t MAINCLKSEL; /* Offset 0x70 */ + __IO uint32_t MAINCLKUEN; + __IO uint32_t SYSAHBCLKDIV; + uint32_t RESERVED4[1]; + + __IO uint32_t SYSAHBCLKCTRL; /* Offset 0x80 */ + uint32_t RESERVED5[4]; + __IO uint32_t SSPCLKDIV; + __IO uint32_t UARTCLKDIV; + uint32_t RESERVED6[4]; + __IO uint32_t TRACECLKDIV; + + __IO uint32_t SYSTICKCLKDIV; /* Offset 0xB0 */ + uint32_t RESERVED7[3]; + + __IO uint32_t USBCLKSEL; /* Offset 0xC0 */ + __IO uint32_t USBCLKUEN; + __IO uint32_t USBCLKDIV; + uint32_t RESERVED8[1]; + __IO uint32_t WDTCLKSEL; /* Offset 0xD0 */ + __IO uint32_t WDTCLKUEN; + __IO uint32_t WDTCLKDIV; + uint32_t RESERVED9[1]; + __IO uint32_t CLKOUTCLKSEL; /* Offset 0xE0 */ + __IO uint32_t CLKOUTUEN; + __IO uint32_t CLKOUTDIV; + uint32_t RESERVED10[5]; + + __IO uint32_t PIOPORCAP0; /* Offset 0x100 */ + __IO uint32_t PIOPORCAP1; + uint32_t RESERVED11[18]; + + __IO uint32_t BODCTRL; /* Offset 0x150 */ + uint32_t RESERVED12[1]; + __IO uint32_t SYSTCKCAL; + uint32_t RESERVED13[41]; + + __IO uint32_t STARTAPRP0; /* Offset 0x200 */ + __IO uint32_t STARTERP0; + __IO uint32_t STARTRSRP0CLR; + __IO uint32_t STARTSRP0; + __IO uint32_t STARTAPRP1; + __IO uint32_t STARTERP1; + __IO uint32_t STARTRSRP1CLR; + __IO uint32_t STARTSRP1; + uint32_t RESERVED14[4]; + + __IO uint32_t PDSLEEPCFG; /* Offset 0x230 */ + __IO uint32_t PDAWAKECFG; + __IO uint32_t PDRUNCFG; + uint32_t RESERVED15[110]; + __I uint32_t DEVICE_ID; +} LPC_SYSCON_TypeDef; + + +/*------------- Pin Connect Block (IOCON) --------------------------------*/ +typedef struct +{ + __IO uint32_t PIO2_6; + uint32_t RESERVED0[1]; + __IO uint32_t PIO2_0; + __IO uint32_t RESET_PIO0_0; + __IO uint32_t PIO0_1; + __IO uint32_t PIO1_8; + uint32_t RESERVED1[1]; + __IO uint32_t PIO0_2; + + __IO uint32_t PIO2_7; + __IO uint32_t PIO2_8; + __IO uint32_t PIO2_1; + __IO uint32_t PIO0_3; + __IO uint32_t PIO0_4; + __IO uint32_t PIO0_5; + __IO uint32_t PIO1_9; + __IO uint32_t PIO3_4; + + __IO uint32_t PIO2_4; + __IO uint32_t PIO2_5; + __IO uint32_t PIO3_5; + __IO uint32_t PIO0_6; + __IO uint32_t PIO0_7; + __IO uint32_t PIO2_9; + __IO uint32_t PIO2_10; + __IO uint32_t PIO2_2; + + __IO uint32_t PIO0_8; + __IO uint32_t PIO0_9; + __IO uint32_t JTAG_TCK_PIO0_10; + __IO uint32_t PIO1_10; + __IO uint32_t PIO2_11; + __IO uint32_t JTAG_TDI_PIO0_11; + __IO uint32_t JTAG_TMS_PIO1_0; + __IO uint32_t JTAG_TDO_PIO1_1; + + __IO uint32_t JTAG_nTRST_PIO1_2; + __IO uint32_t PIO3_0; + __IO uint32_t PIO3_1; + __IO uint32_t PIO2_3; + __IO uint32_t ARM_SWDIO_PIO1_3; + __IO uint32_t PIO1_4; + __IO uint32_t PIO1_11; + __IO uint32_t PIO3_2; + + __IO uint32_t PIO1_5; + __IO uint32_t PIO1_6; + __IO uint32_t PIO1_7; + __IO uint32_t PIO3_3; + __IO uint32_t SCKLOC; /* For HB1 only, new feature */ +} LPC_IOCON_TypeDef; + + +/*------------- Power Management Unit (PMU) --------------------------*/ +typedef struct +{ + __IO uint32_t PCON; + __IO uint32_t GPREG0; + __IO uint32_t GPREG1; + __IO uint32_t GPREG2; + __IO uint32_t GPREG3; + __IO uint32_t GPREG4; +} LPC_PMU_TypeDef; + + +/*------------- General Purpose Input/Output (GPIO) --------------------------*/ +typedef struct +{ + union { + __IO uint32_t MASKED_ACCESS[4096]; + struct { + uint32_t RESERVED0[4095]; + __IO uint32_t DATA; + }; + }; + uint32_t RESERVED1[4096]; + __IO uint32_t DIR; + __IO uint32_t IS; + __IO uint32_t IBE; + __IO uint32_t IEV; + __IO uint32_t IE; + __IO uint32_t RIS; + __IO uint32_t MIS; + __IO uint32_t IC; +} LPC_GPIO_TypeDef; + + +/*------------- Timer (TMR) --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t IR; + __IO uint32_t TCR; + __IO uint32_t TC; + __IO uint32_t PR; + __IO uint32_t PC; + __IO uint32_t MCR; + __IO uint32_t MR0; + __IO uint32_t MR1; + __IO uint32_t MR2; + __IO uint32_t MR3; + __IO uint32_t CCR; + __I uint32_t CR0; + uint32_t RESERVED1[3]; + __IO uint32_t EMR; + uint32_t RESERVED2[12]; + __IO uint32_t CTCR; + __IO uint32_t PWMC; +} LPC_TMR_TypeDef; + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + union { + __I uint32_t RBR; + __O uint32_t THR; + __IO uint32_t DLL; + }; + union { + __IO uint32_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint32_t FCR; + }; + __IO uint32_t LCR; + __IO uint32_t MCR; + __I uint32_t LSR; + __I uint32_t MSR; + __IO uint32_t SCR; + __IO uint32_t ACR; + __IO uint32_t ICR; + __IO uint32_t FDR; + uint32_t RESERVED0; + __IO uint32_t TER; + uint32_t RESERVED1[6]; + __IO uint32_t RS485CTRL; + __IO uint32_t ADRMATCH; + __IO uint32_t RS485DLY; + __I uint32_t FIFOLVL; +} LPC_UART_TypeDef; + +/*------------- Synchronous Serial Communication (SSP) -----------------------*/ +typedef struct +{ + __IO uint32_t CR0; + __IO uint32_t CR1; + __IO uint32_t DR; + __I uint32_t SR; + __IO uint32_t CPSR; + __IO uint32_t IMSC; + __IO uint32_t RIS; + __IO uint32_t MIS; + __IO uint32_t ICR; +} LPC_SSP_TypeDef; + +/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ +typedef struct +{ + __IO uint32_t CONSET; + __I uint32_t STAT; + __IO uint32_t DAT; + __IO uint32_t ADR0; + __IO uint32_t SCLH; + __IO uint32_t SCLL; + __O uint32_t CONCLR; + __IO uint32_t MMCTRL; + __IO uint32_t ADR1; + __IO uint32_t ADR2; + __IO uint32_t ADR3; + __I uint32_t DATA_BUFFER; + __IO uint32_t MASK0; + __IO uint32_t MASK1; + __IO uint32_t MASK2; + __IO uint32_t MASK3; +} LPC_I2C_TypeDef; + +/*------------- Watchdog Timer (WDT) -----------------------------------------*/ +typedef struct +{ + __IO uint32_t MOD; + __IO uint32_t TC; + __O uint32_t FEED; + __I uint32_t TV; +} LPC_WDT_TypeDef; + +/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t GDR; + uint32_t RESERVED0; + __IO uint32_t INTEN; + __I uint32_t DR0; + __I uint32_t DR1; + __I uint32_t DR2; + __I uint32_t DR3; + __I uint32_t DR4; + __I uint32_t DR5; + __I uint32_t DR6; + __I uint32_t DR7; + __I uint32_t STAT; +} LPC_ADC_TypeDef; + + +/*------------- Universal Serial Bus (USB) -----------------------------------*/ +typedef struct +{ + __I uint32_t DevIntSt; /* USB Device Interrupt Registers */ + __IO uint32_t DevIntEn; + __O uint32_t DevIntClr; + __O uint32_t DevIntSet; + + __O uint32_t CmdCode; /* USB Device SIE Command Registers */ + __I uint32_t CmdData; + + __I uint32_t RxData; /* USB Device Transfer Registers */ + __O uint32_t TxData; + __I uint32_t RxPLen; + __O uint32_t TxPLen; + __IO uint32_t Ctrl; + __O uint32_t DevFIQSel; +} LPC_USB_TypeDef; + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Base addresses */ +#define LPC_FLASH_BASE (0x00000000UL) +#define LPC_RAM_BASE (0x10000000UL) +#define LPC_APB0_BASE (0x40000000UL) +#define LPC_AHB_BASE (0x50000000UL) + +/* APB0 peripherals */ +#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000) +#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000) +#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000) +#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000) +#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000) +#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000) +#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000) +#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000) +#define LPC_USB_BASE (LPC_APB0_BASE + 0x20000) +#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000) +#define LPC_SSP_BASE (LPC_APB0_BASE + 0x40000) +#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) +#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) + +/* AHB peripherals */ +#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000) +#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000) +#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) +#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) +#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE ) +#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE) +#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE) +#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE) +#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE) +#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) +#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) +#define LPC_SSP ((LPC_SSP_TypeDef *) LPC_SSP_BASE ) +#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) +#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) +#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) +#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) +#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) +#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) +#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) + +#endif // __LPC13xx_H__ diff --git a/Project/os/hal/platforms/LPC13xx/gpt_lld.c b/Project/os/hal/platforms/LPC13xx/gpt_lld.c new file mode 100644 index 0000000..2e07553 --- /dev/null +++ b/Project/os/hal/platforms/LPC13xx/gpt_lld.c @@ -0,0 +1,349 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC13xx/gpt_lld.c + * @brief LPC13xx GPT subsystem low level driver source. + * + * @addtogroup GPT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief GPT1 driver identifier. + * @note The driver GPT1 allocates the complex timer CT16B0 when enabled. + */ +#if LPC13xx_GPT_USE_CT16B0 || defined(__DOXYGEN__) +GPTDriver GPTD1; +#endif + +/** + * @brief GPT2 driver identifier. + * @note The driver GPT2 allocates the timer CT16B1 when enabled. + */ +#if LPC13xx_GPT_USE_CT16B1 || defined(__DOXYGEN__) +GPTDriver GPTD2; +#endif + +/** + * @brief GPT3 driver identifier. + * @note The driver GPT3 allocates the timer CT32B0 when enabled. + */ +#if LPC13xx_GPT_USE_CT32B0 || defined(__DOXYGEN__) +GPTDriver GPTD3; +#endif + +/** + * @brief GPT4 driver identifier. + * @note The driver GPT4 allocates the timer CT32B1 when enabled. + */ +#if LPC13xx_GPT_USE_CT32B1 || defined(__DOXYGEN__) +GPTDriver GPTD4; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared IRQ handler. + * + * @param[in] gptp pointer to a @p GPTDriver object + */ +static void gpt_lld_serve_interrupt(GPTDriver *gptp) { + + gptp->tmr->IR = 1; /* Clear interrupt on match MR0.*/ + if (gptp->state == GPT_ONESHOT) { + gptp->state = GPT_READY; /* Back in GPT_READY state. */ + gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */ + } + gptp->config->callback(gptp); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC13xx_GPT_USE_CT16B0 +/** + * @brief CT16B0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorE4) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC13xx_GPT_USE_CT16B0 */ + +#if LPC13xx_GPT_USE_CT16B1 +/** + * @brief CT16B1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorE8) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC13xx_GPT_USE_CT16B0 */ + +#if LPC13xx_GPT_USE_CT32B0 +/** + * @brief CT32B0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorEC) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC13xx_GPT_USE_CT32B0 */ + +#if LPC13xx_GPT_USE_CT32B1 +/** + * @brief CT32B1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorF0) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD4); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC13xx_GPT_USE_CT32B1 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level GPT driver initialization. + * + * @notapi + */ +void gpt_lld_init(void) { + +#if LPC13xx_GPT_USE_CT16B0 + /* Driver initialization.*/ + GPTD1.tmr = LPC_TMR16B0; + gptObjectInit(&GPTD1); +#endif + +#if LPC13xx_GPT_USE_CT16B1 + /* Driver initialization.*/ + GPTD2.tmr = LPC_TMR16B1; + gptObjectInit(&GPTD2); +#endif + +#if LPC13xx_GPT_USE_CT32B0 + /* Driver initialization.*/ + GPTD3.tmr = LPC_TMR32B0; + gptObjectInit(&GPTD3); +#endif + +#if LPC13xx_GPT_USE_CT32B1 + /* Driver initialization.*/ + GPTD4.tmr = LPC_TMR32B1; + gptObjectInit(&GPTD4); +#endif +} + +/** + * @brief Configures and activates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_start(GPTDriver *gptp) { + uint32_t pr; + + if (gptp->state == GPT_STOP) { + /* Clock activation.*/ +#if LPC13xx_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7); + nvicEnableVector(TIMER_16_0_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif +#if LPC13xx_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); + nvicEnableVector(TIMER_16_1_IRQn, CORTEX_PRIORITY_MASK(3)); + } +#endif +#if LPC13xx_GPT_USE_CT32B0 + if (&GPTD3 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9); + nvicEnableVector(TIMER_32_0_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif +#if LPC13xx_GPT_USE_CT32B1 + if (&GPTD4 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10); + nvicEnableVector(TIMER_32_1_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif + } + + /* Prescaler value calculation.*/ + pr = (uint16_t)((LPC13xx_SYSCLK / gptp->config->frequency) - 1); + chDbgAssert(((uint32_t)(pr + 1) * gptp->config->frequency) == LPC13xx_SYSCLK, + "gpt_lld_start(), #1", "invalid frequency"); + + /* Timer configuration.*/ + gptp->tmr->PR = pr; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; +} + +/** + * @brief Deactivates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop(GPTDriver *gptp) { + + if (gptp->state == GPT_READY) { + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; + +#if LPC13xx_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { + nvicDisableVector(TIMER_16_0_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7); + } +#endif +#if LPC13xx_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { + nvicDisableVector(TIMER_16_1_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8); + } +#endif +#if LPC13xx_GPT_USE_CT32B0 + if (&GPTD3 == gptp) { + nvicDisableVector(TIMER_32_0_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9); + } +#endif +#if LPC13xx_GPT_USE_CT32B1 + if (&GPTD4 == gptp) { + nvicDisableVector(TIMER_32_1_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10); + } +#endif + } +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @notapi + */ +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->MR0 = interval - 1; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 3; /* IRQ and clr TC on match MR0. */ + gptp->tmr->TCR = 2; /* Reset counter and prescaler. */ + gptp->tmr->TCR = 1; /* Timer enabled. */ +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop_timer(GPTDriver *gptp) { + + gptp->tmr->IR = 1; + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @notapi + */ +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->MR0 = interval - 1; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 4; /* Stop TC on match MR0. */ + gptp->tmr->TCR = 2; /* Reset counter and prescaler. */ + gptp->tmr->TCR = 1; /* Timer enabled. */ + while (gptp->tmr->TCR & 1) + ; +} + +#endif /* HAL_USE_GPT */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC13xx/gpt_lld.h b/Project/os/hal/platforms/LPC13xx/gpt_lld.h new file mode 100644 index 0000000..bab9b28 --- /dev/null +++ b/Project/os/hal/platforms/LPC13xx/gpt_lld.h @@ -0,0 +1,219 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC13xx/gpt_lld.h + * @brief LPC13xx GPT subsystem low level driver header. + * + * @addtogroup GPT + * @{ + */ + +#ifndef _GPT_LLD_H_ +#define _GPT_LLD_H_ + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief GPT1 driver enable switch. + * @details If set to @p TRUE the support for GPT1 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC13xx_GPT_USE_CT16B0) || defined(__DOXYGEN__) +#define LPC13xx_GPT_USE_CT16B0 TRUE +#endif + +/** + * @brief GPT2 driver enable switch. + * @details If set to @p TRUE the support for GPT2 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC13xx_GPT_USE_CT16B1) || defined(__DOXYGEN__) +#define LPC13xx_GPT_USE_CT16B1 TRUE +#endif + +/** + * @brief GPT3 driver enable switch. + * @details If set to @p TRUE the support for GPT3 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC13xx_GPT_USE_CT32B0) || defined(__DOXYGEN__) +#define LPC13xx_GPT_USE_CT32B0 TRUE +#endif + +/** + * @brief GPT4 driver enable switch. + * @details If set to @p TRUE the support for GPT4 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC13xx_GPT_USE_CT32B1) || defined(__DOXYGEN__) +#define LPC13xx_GPT_USE_CT32B1 TRUE +#endif + +/** + * @brief GPT1 interrupt priority level setting. + */ +#if !defined(LPC13xx_GPT_CT16B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC13xx_GPT_CT16B0_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT2 interrupt priority level setting. + */ +#if !defined(LPC13xx_GPT_CT16B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC13xx_GPT_CT16B1_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT3 interrupt priority level setting. + */ +#if !defined(LPC13xx_GPT_CT32B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC13xx_GPT_CT32B0_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT4 interrupt priority level setting. + */ +#if !defined(LPC13xx_GPT_CT32B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC13xx_GPT_CT32B1_IRQ_PRIORITY 2 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !LPC13xx_GPT_USE_CT16B0 && !LPC13xx_GPT_USE_CT16B1 && \ + !LPC13xx_GPT_USE_CT32B0 && !LPC13xx_GPT_USE_CT32B1 +#error "GPT driver activated but no CT peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPT frequency type. + */ +typedef uint32_t gptfreq_t; + +/** + * @brief GPT counter type. + */ +typedef uint32_t gptcnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + gptfreq_t frequency; + /** + * @brief Timer callback pointer. + * @note This callback is invoked on GPT counter events. + */ + gptcallback_t callback; + /* End of the mandatory fields.*/ +} GPTConfig; + +/** + * @brief Structure representing a GPT driver. + */ +struct GPTDriver { + /** + * @brief Driver state. + */ + gptstate_t state; + /** + * @brief Current configuration data. + */ + const GPTConfig *config; + /* End of the mandatory fields.*/ + /** + * @brief Timer base clock. + */ + uint32_t clock; + /** + * @brief Pointer to the CTxxBy registers block. + */ + LPC_TMR_TypeDef *tmr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC13xx_GPT_USE_CT16B0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD1; +#endif + +#if LPC13xx_GPT_USE_CT16B1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD2; +#endif + +#if LPC13xx_GPT_USE_CT32B0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD3; +#endif + +#if LPC13xx_GPT_USE_CT32B1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void gpt_lld_init(void); + void gpt_lld_start(GPTDriver *gptp); + void gpt_lld_stop(GPTDriver *gptp); + void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); + void gpt_lld_stop_timer(GPTDriver *gptp); + void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT */ + +#endif /* _GPT_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC13xx/hal_lld.c b/Project/os/hal/platforms/LPC13xx/hal_lld.c new file mode 100644 index 0000000..4618d82 --- /dev/null +++ b/Project/os/hal/platforms/LPC13xx/hal_lld.c @@ -0,0 +1,131 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC13xx/hal_lld.c + * @brief LPC13xx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/** + * @brief Register missing in NXP header file. + */ +#define FLASHCFG (*((volatile uint32_t *)0x4003C010)) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* SysTick initialization using the system clock.*/ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK); + SysTick->LOAD = LPC13xx_SYSCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief LPC13xx clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function must be invoked only after the system reset. + * + * @special + */ +void LPC13xx_clock_init(void) { + unsigned i; + + /* Flash wait states setting, the code takes care to not touch TBD bits.*/ + FLASHCFG = (FLASHCFG & ~3) | LPC13xx_FLASHCFG_FLASHTIM; + + /* System oscillator initialization if required.*/ +#if LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT +#if LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC + LPC_SYSCON->SYSOSCCTRL = LPC13xx_SYSOSCCTRL; + LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* System oscillator ON. */ + for (i = 0; i < 200; i++) + __NOP(); /* Stabilization delay. */ +#endif /* LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC */ + + /* PLL initialization if required.*/ + LPC_SYSCON->SYSPLLCLKSEL = LPC13xx_PLLCLK_SOURCE; + LPC_SYSCON->SYSPLLCLKUEN = 1; /* Really required? */ + LPC_SYSCON->SYSPLLCLKUEN = 0; + LPC_SYSCON->SYSPLLCLKUEN = 1; + LPC_SYSCON->SYSPLLCTRL = LPC13xx_SYSPLLCTRL_MSEL | LPC13xx_SYSPLLCTRL_PSEL; + LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* System PLL ON. */ + while ((LPC_SYSCON->SYSPLLSTAT & 1) == 0) /* Wait PLL lock. */ + ; +#endif /* LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT */ + + /* Main clock source selection.*/ + LPC_SYSCON->MAINCLKSEL = LPC13xx_MAINCLK_SOURCE; + LPC_SYSCON->MAINCLKUEN = 1; /* Really required? */ + LPC_SYSCON->MAINCLKUEN = 0; + LPC_SYSCON->MAINCLKUEN = 1; + while ((LPC_SYSCON->MAINCLKUEN & 1) == 0) /* Wait switch completion. */ + ; + + /* ABH divider initialization, peripheral clocks are initially disabled, + the various device drivers will handle their own setup except GPIO and + IOCON that are left enabled.*/ + LPC_SYSCON->SYSAHBCLKDIV = LPC13xx_SYSABHCLK_DIV; + LPC_SYSCON->SYSAHBCLKCTRL = 0x0001005F; + + /* Memory remapping, vectors always in ROM.*/ + LPC_SYSCON->SYSMEMREMAP = 2; +} + +/** @} */ diff --git a/Project/os/hal/platforms/LPC13xx/hal_lld.h b/Project/os/hal/platforms/LPC13xx/hal_lld.h new file mode 100644 index 0000000..252b302 --- /dev/null +++ b/Project/os/hal/platforms/LPC13xx/hal_lld.h @@ -0,0 +1,230 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC13xx/hal_lld.h + * @brief HAL subsystem low level driver header template. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "LPC13xx.h" +#include "nvic.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "LPC13xx" + +#define IRCOSCCLK 12000000 /**< High speed internal clock. */ +#define WDGOSCCLK 1600000 /**< Watchdog internal clock. */ + +#define SYSPLLCLKSEL_IRCOSC 0 /**< Internal RC oscillator + clock source. */ +#define SYSPLLCLKSEL_SYSOSC 1 /**< System oscillator clock + source. */ + +#define SYSMAINCLKSEL_IRCOSC 0 /**< Clock source is IRC. */ +#define SYSMAINCLKSEL_PLLIN 1 /**< Clock source is PLLIN. */ +#define SYSMAINCLKSEL_WDGOSC 2 /**< Clock source is WDGOSC. */ +#define SYSMAINCLKSEL_PLLOUT 3 /**< Clock source is PLLOUT. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief System PLL clock source. + */ +#if !defined(LPC13xx_PLLCLK_SOURCE) || defined(__DOXYGEN__) +#define LPC13xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#endif + +/** + * @brief System PLL multiplier. + * @note The value must be in the 1..32 range and the final frequency + * must not exceed the CCO ratings. + */ +#if !defined(LPC13xx_SYSPLL_MUL) || defined(__DOXYGEN__) +#define LPC13xx_SYSPLL_MUL 6 +#endif + +/** + * @brief System PLL divider. + * @note The value must be chosen between (2, 4, 8, 16). + */ +#if !defined(LPC13xx_SYSPLL_DIV) || defined(__DOXYGEN__) +#define LPC13xx_SYSPLL_DIV 4 +#endif + +/** + * @brief System main clock source. + */ +#if !defined(LPC13xx_MAINCLK_SOURCE) || defined(__DOXYGEN__) +#define LPC13xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#endif + +/** + * @brief AHB clock divider. + * @note The value must be chosen between (1...255). + */ +#if !defined(LPC13xx_SYSCLK_DIV) || defined(__DOXYGEN__) +#define LPC13xx_SYSABHCLK_DIV 1 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** + * @brief Calculated SYSOSCCTRL setting. + */ +#if (SYSOSCCLK < 18000000) || defined(__DOXYGEN__) +#define LPC13xx_SYSOSCCTRL 0 +#else +#define LPC13xx_SYSOSCCTRL 1 +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__) +#define LPC13xx_SYSPLLCLKIN SYSOSCCLK +#elif LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOSC +#define LPC13xx_SYSPLLCLKIN IRCOSCCLK +#else +#error "invalid LPC13xx_PLLCLK_SOURCE clock source specified" +#endif + +/** + * @brief MSEL mask in SYSPLLCTRL register. + */ +#if (LPC13xx_SYSPLL_MUL >= 1) && (LPC13xx_SYSPLL_MUL <= 32) || \ + defined(__DOXYGEN__) +#define LPC13xx_SYSPLLCTRL_MSEL (LPC13xx_SYSPLL_MUL - 1) +#else +#error "LPC13xx_SYSPLL_MUL out of range (1...32)" +#endif + +/** + * @brief PSEL mask in SYSPLLCTRL register. + */ +#if (LPC13xx_SYSPLL_DIV == 2) || defined(__DOXYGEN__) +#define LPC13xx_SYSPLLCTRL_PSEL (0 << 5) +#elif LPC13xx_SYSPLL_DIV == 4 +#define LPC13xx_SYSPLLCTRL_PSEL (1 << 5) +#elif LPC13xx_SYSPLL_DIV == 8 +#define LPC13xx_SYSPLLCTRL_PSEL (2 << 5) +#elif LPC13xx_SYSPLL_DIV == 16 +#define LPC13xx_SYSPLLCTRL_PSEL (3 << 5) +#else +#error "invalid LPC13xx_SYSPLL_DIV value (2,4,8,16)" +#endif + +/** + * @brief CCP frequency. + */ +#define LPC13xx_SYSPLLCCO (LPC13xx_SYSPLLCLKIN * LPC13xx_SYSPLL_MUL * \ + LPC13xx_SYSPLL_DIV) + +#if (LPC13xx_SYSPLLCCO < 156000000) || (LPC13xx_SYSPLLCCO > 320000000) +#error "CCO frequency out of the acceptable range (156...320)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define LPC13xx_SYSPLLCLKOUT (LPC13xx_SYSPLLCCO / LPC13xx_SYSPLL_DIV) + +#if (LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOSC) || defined(__DOXYGEN__) +#define LPC13xx_MAINCLK IRCOSCCLK +#elif LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN +#define LPC13xx_MAINCLK LPC13xx_SYSPLLCLKIN +#elif LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC +#define LPC13xx_MAINCLK WDGOSCCLK +#elif LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT +#define LPC13xx_MAINCLK LPC13xx_SYSPLLCLKOUT +#else +#error "invalid LPC13xx_MAINCLK_SOURCE clock source specified" +#endif + +/** + * @brief AHB clock. + */ +#define LPC13xx_SYSCLK (LPC13xx_MAINCLK / LPC13xx_SYSABHCLK_DIV) +#if LPC13xx_SYSCLK > 72000000 +#error "AHB clock frequency out of the acceptable range (72MHz max)" +#endif + +/** + * @brief Flash wait states. + */ +#if (LPC13xx_SYSCLK <= 20000000) || defined(__DOXYGEN__) +#define LPC13xx_FLASHCFG_FLASHTIM 0 +#elif LPC13xx_SYSCLK <= 40000000 +#define LPC13xx_FLASHCFG_FLASHTIM 1 +#else +#define LPC13xx_FLASHCFG_FLASHTIM 2 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void LPC13xx_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC13xx/pal_lld.c b/Project/os/hal/platforms/LPC13xx/pal_lld.c new file mode 100644 index 0000000..701ddb5 --- /dev/null +++ b/Project/os/hal/platforms/LPC13xx/pal_lld.c @@ -0,0 +1,114 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC13xx/pal_lld.c + * @brief LPC13xx GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ +/** + * @brief LPC13xx I/O ports configuration. + * @details GPIO unit registers initialization. + * + * @param[in] config the LPC13xx ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + LPC_GPIO0->DIR = config->P0.dir; + LPC_GPIO1->DIR = config->P1.dir; + LPC_GPIO2->DIR = config->P2.dir; + LPC_GPIO3->DIR = config->P3.dir; + LPC_GPIO0->DATA = config->P0.data; + LPC_GPIO1->DATA = config->P1.data; + LPC_GPIO2->DATA = config->P2.data; + LPC_GPIO3->DATA = config->P3.data; +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with + * high state. + * @note This function does not alter the @p PINSELx registers. Alternate + * functions setup must be handled by device-specific code. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + port->DIR &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + palSetPort(port, PAL_WHOLE_PORT); + case PAL_MODE_OUTPUT_PUSHPULL: + port->DIR |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC13xx/pal_lld.h b/Project/os/hal/platforms/LPC13xx/pal_lld.h new file mode 100644 index 0000000..f7519b2 --- /dev/null +++ b/Project/os/hal/platforms/LPC13xx/pal_lld.h @@ -0,0 +1,327 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC13xx/pal_lld.h + * @brief LPC13xx GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief GPIO port setup info. + */ +typedef struct { + /** Initial value for FIO_PIN register.*/ + uint32_t data; + /** Initial value for FIO_DIR register.*/ + uint32_t dir; +} lpc13xx_gpio_setup_t; + +/** + * @brief GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + * @note The @p IOCON block is not configured, initially all pins have + * enabled pullups and are programmed as GPIO. It is responsibility + * of the various drivers to reprogram the pins in the proper mode. + * Pins that are not handled by any driver may be programmed in + * @p board.c. + */ +typedef struct { + /** @brief GPIO 0 setup data.*/ + lpc13xx_gpio_setup_t P0; + /** @brief GPIO 1 setup data.*/ + lpc13xx_gpio_setup_t P1; + /** @brief GPIO 2 setup data.*/ + lpc13xx_gpio_setup_t P2; + /** @brief GPIO 3 setup data.*/ + lpc13xx_gpio_setup_t P3; +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 32 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + */ +typedef LPC_GPIO_TypeDef *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief GPIO0 port identifier. + */ +#define IOPORT1 LPC_GPIO0 +#define GPIO0 LPC_GPIO0 + +/** + * @brief GPIO1 port identifier. + */ +#define IOPORT2 LPC_GPIO1 +#define GPIO1 LPC_GPIO1 + +/** + * @brief GPIO2 port identifier. + */ +#define IOPORT3 LPC_GPIO2 +#define GPIO2 LPC_GPIO2 + +/** + * @brief GPIO3 port identifier. + */ +#define IOPORT4 LPC_GPIO3 +#define GPIO3 LPC_GPIO3 + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->DATA) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->DATA) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->DATA = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) ((port)->MASKED_ACCESS[bits] = 0xFFFFFFFF) + +/** + * @brief Clears a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) ((port)->MASKED_ACCESS[bits] = 0) + +/** + * @brief Reads a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @notapi + */ +#define pal_lld_readgroup(port, mask, offset) \ + ((port)->MASKED_ACCESS[(mask) << (offset)]) + +/** + * @brief Writes a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) \ + ((port)->MASKED_ACCESS[(mask) << (pad)] = (bit) << (pad)) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) \ + ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad)) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) \ + ((port)->MASKED_ACCESS[1 << (pad)] = 0) + +#if !defined(__DOXYGEN__) +extern const PALConfig pal_default_config; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC13xx/platform.dox b/Project/os/hal/platforms/LPC13xx/platform.dox new file mode 100644 index 0000000..5c73990 --- /dev/null +++ b/Project/os/hal/platforms/LPC13xx/platform.dox @@ -0,0 +1,147 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup LPC13xx LPC13xx Drivers + * @details This section describes all the supported drivers on the LPC13xx + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup LPC13xx_HAL LPC13xx Initialization Support + * @details The LPC13xx HAL support is responsible for system initialization. + * + * @section lpc13xx_hal_1 Supported HW resources + * - SYSCON. + * - Flash. + * . + * @section lpc13xx_hal_2 LPC13xx HAL driver implementation features + * - Clock tree initialization. + * - Clock source selection. + * - Flash controller initialization. + * - SYSTICK initialization based on current clock and kernel required rate. + * . + * @ingroup LPC13xx + */ + +/** + * @defgroup LPC13xx_GPT LPC13xx GPT Support + * @details The LPC13xx GPT driver uses the CTxxBy peripherals. + * + * @section lpc13xx_gpt_1 Supported HW resources + * - CT16B0. + * - CT16B1. + * - CT32B0. + * - CT32B1. + * . + * @section lpc13xx_gpt_2 LPC13xx GPT driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable CTxxBy interrupts priority level. + * . + * @ingroup LPC13xx + */ + +/** + * @defgroup LPC13xx_PAL LPC13xx PAL Support + * @details The LPC13xx PAL driver uses the GPIO peripherals. + * + * @section lpc13xx_pal_1 Supported HW resources + * - GPIO0. + * - GPIO1. + * - GPIO2. + * - GPIO3. + * . + * @section lpc13xx_pal_2 LPC13xx PAL driver implementation features + * - 12 bits wide ports. + * - Atomic set/reset functions. + * - Atomic set+reset function (atomic bus operations). + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section lpc13xx_pal_3 Supported PAL setup modes + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section lpc13xx_pal_4 Suboptimal behavior + * Some GPIO features are less than optimal: + * - Pad/port toggling operations are not atomic. + * - Pull-up and Pull-down resistors cannot be programmed through the PAL + * driver and must be programmed separately using the IOCON peripheral. + * - Reading of the output latch for pads programmed as input is not possible, + * the input pin value is returned instead. + * . + * @ingroup LPC13xx + */ + +/** + * @defgroup LPC13xx_SERIAL LPC13xx Serial Support + * @details The LPC13xx Serial driver uses the UART peripheral in a + * buffered, interrupt driven, implementation. The serial driver + * also takes advantage of the LPC13xx UARTs deep hardware buffers. + * + * @section lpc13xx_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - UART. + * . + * @section lpc13xx_serial_2 LPC13xx Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Fully interrupt driven. + * - Programmable priority level. + * - Takes advantage of the input and output FIFOs. + * . + * @ingroup LPC13xx + */ + +/** + * @defgroup LPC13xx_SPI LPC13xx SPI Support + * @details The SPI driver supports the LPC13xx SSP peripherals in an interrupt + * driven implementation. + * @note Being the SPI a fast peripheral, much care must be taken to + * not saturate the CPU bandwidth with an excessive IRQ rate. The + * maximum transfer bit rate is likely limited by the IRQ + * handling. + * + * @section lpc13xx_spi_1 Supported HW resources + * - SSP0. + * - SSP1 (where present). + * . + * @section lpc13xx_spi_2 LPC13xx SPI driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each SSP can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * - Programmable interrupt priority levels for each SSP. + * . + * @ingroup LPC13xx + */ diff --git a/Project/os/hal/platforms/LPC13xx/platform.mk b/Project/os/hal/platforms/LPC13xx/platform.mk new file mode 100644 index 0000000..1171af7 --- /dev/null +++ b/Project/os/hal/platforms/LPC13xx/platform.mk @@ -0,0 +1,9 @@ +# List of all the LPC13xx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC13xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC13xx/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC13xx/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC13xx/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC13xx/spi_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC13xx diff --git a/Project/os/hal/platforms/LPC13xx/serial_lld.c b/Project/os/hal/platforms/LPC13xx/serial_lld.c new file mode 100644 index 0000000..0d54166 --- /dev/null +++ b/Project/os/hal/platforms/LPC13xx/serial_lld.c @@ -0,0 +1,309 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC13xx/serial_lld.c + * @brief LPC13xx low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if LPC13xx_SERIAL_USE_UART0 || defined(__DOXYGEN__) +/** @brief UART0 serial driver identifier.*/ +SerialDriver SD1; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = { + SERIAL_DEFAULT_BITRATE, + LCR_WL8 | LCR_STOP1 | LCR_NOPARITY, + FCR_TRIGGER0 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief UART initialization. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] config the architecture-dependent serial driver configuration + */ +static void uart_init(SerialDriver *sdp, const SerialConfig *config) { + LPC_UART_TypeDef *u = sdp->uart; + + uint32_t div = LPC13xx_SERIAL_UART0_PCLK / (config->sc_speed << 4); + u->LCR = config->sc_lcr | LCR_DLAB; + u->DLL = div; + u->DLM = div >> 8; + u->LCR = config->sc_lcr; + u->FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | config->sc_fcr; + u->ACR = 0; + u->FDR = 0x10; + u->TER = TER_ENABLE; + u->IER = IER_RBR | IER_STATUS; +} + +/** + * @brief UART de-initialization. + * + * @param[in] u pointer to an UART I/O block + */ +static void uart_deinit(LPC_UART_TypeDef *u) { + + u->LCR = LCR_DLAB; + u->DLL = 1; + u->DLM = 0; + u->LCR = 0; + u->FDR = 0x10; + u->IER = 0; + u->FCR = FCR_RXRESET | FCR_TXRESET; + u->ACR = 0; + u->TER = TER_ENABLE; +} + +/** + * @brief Error handling routine. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] err UART LSR register value + */ +static void set_error(SerialDriver *sdp, IOREG32 err) { + ioflags_t sts = 0; + + if (err & LSR_OVERRUN) + sts |= SD_OVERRUN_ERROR; + if (err & LSR_PARITY) + sts |= SD_PARITY_ERROR; + if (err & LSR_FRAMING) + sts |= SD_FRAMING_ERROR; + if (err & LSR_BREAK) + sts |= SD_BREAK_DETECTED; + chSysLockFromIsr(); + chIOAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +/** + * @brief Common IRQ handler. + * @note Tries hard to clear all the pending interrupt sources, we don't + * want to go through the whole ISR and have another interrupt soon + * after. + * + * @param[in] u pointer to an UART I/O block + * @param[in] sdp communication channel associated to the UART + */ +static void serve_interrupt(SerialDriver *sdp) { + LPC_UART_TypeDef *u = sdp->uart; + + while (TRUE) { + switch (u->IIR & IIR_SRC_MASK) { + case IIR_SRC_NONE: + return; + case IIR_SRC_ERROR: + set_error(sdp, u->LSR); + break; + case IIR_SRC_TIMEOUT: + case IIR_SRC_RX: + chSysLockFromIsr(); + if (chIQIsEmptyI(&sdp->iqueue)) + chIOAddFlagsI(sdp, IO_INPUT_AVAILABLE); + chSysUnlockFromIsr(); + while (u->LSR & LSR_RBR_FULL) { + chSysLockFromIsr(); + if (chIQPutI(&sdp->iqueue, u->RBR) < Q_OK) + chIOAddFlagsI(sdp, SD_OVERRUN_ERROR); + chSysUnlockFromIsr(); + } + break; + case IIR_SRC_TX: + { + int i = LPC13xx_SERIAL_FIFO_PRELOAD; + do { + msg_t b; + + chSysLockFromIsr(); + b = chOQGetI(&sdp->oqueue); + chSysUnlockFromIsr(); + if (b < Q_OK) { + u->IER &= ~IER_THRE; + chSysLockFromIsr(); + chIOAddFlagsI(sdp, IO_OUTPUT_EMPTY); + chSysUnlockFromIsr(); + break; + } + u->THR = b; + } while (--i); + } + break; + default: + (void) u->THR; + (void) u->RBR; + } + } +} + +/** + * @brief Attempts a TX FIFO preload. + */ +static void preload(SerialDriver *sdp) { + LPC_UART_TypeDef *u = sdp->uart; + + if (u->LSR & LSR_THRE) { + int i = LPC13xx_SERIAL_FIFO_PRELOAD; + do { + msg_t b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) { + chIOAddFlagsI(sdp, IO_OUTPUT_EMPTY); + return; + } + u->THR = b; + } while (--i); + } + u->IER |= IER_THRE; +} + +/** + * @brief Driver SD1 output notification. + */ +#if LPC13xx_SERIAL_USE_UART0 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + preload(&SD1); +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief UART0 IRQ handler. + * + * @isr + */ +#if LPC13xx_SERIAL_USE_UART0 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(VectorF8) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD1); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if LPC13xx_SERIAL_USE_UART0 + sdObjectInit(&SD1, NULL, notify1); + SD1.uart = LPC_UART; + LPC_IOCON->PIO1_6 = 0xC1; /* RDX without resistors. */ + LPC_IOCON->PIO1_7 = 0xC1; /* TDX without resistors. */ +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + + if (sdp->state == SD_STOP) { +#if LPC13xx_SERIAL_USE_UART0 + if (&SD1 == sdp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12); + LPC_SYSCON->UARTCLKDIV = LPC13xx_SERIAL_UART0CLKDIV; + nvicEnableVector(UART_IRQn, + CORTEX_PRIORITY_MASK(LPC13xx_SERIAL_UART0_IRQ_PRIORITY)); + } +#endif + } + uart_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the UART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) { + uart_deinit(sdp->uart); +#if LPC13xx_SERIAL_USE_UART0 + if (&SD1 == sdp) { + LPC_SYSCON->UARTCLKDIV = 0; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 12); + nvicDisableVector(UART_IRQn); + return; + } +#endif + } +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC13xx/serial_lld.h b/Project/os/hal/platforms/LPC13xx/serial_lld.h new file mode 100644 index 0000000..b284b82 --- /dev/null +++ b/Project/os/hal/platforms/LPC13xx/serial_lld.h @@ -0,0 +1,217 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC13xx/serial_lld.h + * @brief LPC13xx low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define IIR_SRC_MASK 0x0F +#define IIR_SRC_NONE 0x01 +#define IIR_SRC_MODEM 0x00 +#define IIR_SRC_TX 0x02 +#define IIR_SRC_RX 0x04 +#define IIR_SRC_ERROR 0x06 +#define IIR_SRC_TIMEOUT 0x0C + +#define IER_RBR 1 +#define IER_THRE 2 +#define IER_STATUS 4 + +#define LCR_WL5 0 +#define LCR_WL6 1 +#define LCR_WL7 2 +#define LCR_WL8 3 +#define LCR_STOP1 0 +#define LCR_STOP2 4 +#define LCR_NOPARITY 0 +#define LCR_PARITYODD 0x08 +#define LCR_PARITYEVEN 0x18 +#define LCR_PARITYONE 0x28 +#define LCR_PARITYZERO 0x38 +#define LCR_BREAK_ON 0x40 +#define LCR_DLAB 0x80 + +#define FCR_ENABLE 1 +#define FCR_RXRESET 2 +#define FCR_TXRESET 4 +#define FCR_TRIGGER0 0 +#define FCR_TRIGGER1 0x40 +#define FCR_TRIGGER2 0x80 +#define FCR_TRIGGER3 0xC0 + +#define LSR_RBR_FULL 1 +#define LSR_OVERRUN 2 +#define LSR_PARITY 4 +#define LSR_FRAMING 8 +#define LSR_BREAK 0x10 +#define LSR_THRE 0x20 +#define LSR_TEMT 0x40 +#define LSR_RXFE 0x80 + +#define TER_ENABLE 0x80 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief UART0 driver enable switch. + * @details If set to @p TRUE the support for UART0 is included. + * @note The default is @p TRUE . + */ +#if !defined(LPC13xx_SERIAL_USE_UART0) || defined(__DOXYGEN__) +#define LPC13xx_SERIAL_USE_UART0 TRUE +#endif + +/** + * @brief FIFO preload parameter. + * @details Configuration parameter, this values defines how many bytes are + * preloaded in the HW transmit FIFO for each interrupt, the maximum + * value is 16 the minimum is 1. + * @note An high value reduces the number of interrupts generated but can + * also increase the worst case interrupt response time because the + * preload loops. + */ +#if !defined(LPC13xx_SERIAL_FIFO_PRELOAD) || defined(__DOXYGEN__) +#define LPC13xx_SERIAL_FIFO_PRELOAD 16 +#endif + +/** + * @brief UART0 PCLK divider. + */ +#if !defined(LPC13xx_SERIAL_UART0CLKDIV) || defined(__DOXYGEN__) +#define LPC13xx_SERIAL_UART0CLKDIV 1 +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(LPC13xx_SERIAL_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC13xx_SERIAL_UART0_IRQ_PRIORITY 3 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (LPC13xx_SERIAL_UART0CLKDIV < 1) || (LPC11xx_SERIAL_UART0CLKDIV > 255) +#error "invalid LPC13xx_SERIAL_UART0CLKDIV setting" +#endif + +#if (LPC13xx_SERIAL_FIFO_PRELOAD < 1) || (LPC13xx_SERIAL_FIFO_PRELOAD > 16) +#error "invalid LPC13xx_SERIAL_FIFO_PRELOAD setting" +#endif + +/** + * @brief UART0 clock. + */ +#define LPC13xx_SERIAL_UART0_PCLK \ + (LPC13xx_MAINCLK / LPC13xx_SERIAL_UART0CLKDIV) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief LPC13xx Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t sc_speed; + /** + * @brief Initialization value for the LCR register. + */ + uint32_t sc_lcr; + /** + * @brief Initialization value for the FCR register. + */ + uint32_t sc_fcr; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the USART registers block.*/ \ + LPC_UART_TypeDef *uart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC13xx_SERIAL_USE_UART0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC13xx/spi_lld.c b/Project/os/hal/platforms/LPC13xx/spi_lld.c new file mode 100644 index 0000000..554b3d3 --- /dev/null +++ b/Project/os/hal/platforms/LPC13xx/spi_lld.c @@ -0,0 +1,369 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC13xx/spi_lld.c + * @brief LPC13xx low level SPI driver code. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if LPC13xx_SPI_USE_SSP0 || defined(__DOXYGEN__) +/** @brief SPI1 driver identifier.*/ +SPIDriver SPID1; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Preloads the transmit FIFO. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void ssp_fifo_preload(SPIDriver *spip) { + LPC_SSP_TypeDef *ssp = spip->ssp; + uint32_t n = spip->txcnt > LPC13xx_SSP_FIFO_DEPTH ? + LPC13xx_SSP_FIFO_DEPTH : spip->txcnt; + + while(((ssp->SR & SR_TNF) != 0) && (n > 0)) { + if (spip->txptr != NULL) { + if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) { + const uint16_t *p = spip->txptr; + ssp->DR = *p++; + spip->txptr = p; + } + else { + const uint8_t *p = spip->txptr; + ssp->DR = *p++; + spip->txptr = p; + } + } + else + ssp->DR = 0xFFFFFFFF; + n--; + spip->txcnt--; + } +} + +/** + * @brief Common IRQ handler. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void spi_serve_interrupt(SPIDriver *spip) { + LPC_SSP_TypeDef *ssp = spip->ssp; + + if ((ssp->MIS & MIS_ROR) != 0) { + /* The overflow condition should never happen because priority is given + to receive but a hook macro is provided anyway...*/ + LPC13xx_SPI_SSP_ERROR_HOOK(spip); + } + ssp->ICR = ICR_RT | ICR_ROR; + while ((ssp->SR & SR_RNE) != 0) { + if (spip->rxptr != NULL) { + if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) { + uint16_t *p = spip->rxptr; + *p++ = ssp->DR; + spip->rxptr = p; + } + else { + uint8_t *p = spip->rxptr; + *p++ = ssp->DR; + spip->rxptr = p; + } + } + else + (void)ssp->DR; + if (--spip->rxcnt == 0) { + chDbgAssert(spip->txcnt == 0, + "spi_serve_interrupt(), #1", "counter out of synch"); + /* Stops the IRQ sources.*/ + ssp->IMSC = 0; + /* Portable SPI ISR code defined in the high level driver, note, it is + a macro.*/ + _spi_isr_code(spip); + return; + } + } + ssp_fifo_preload(spip); + if (spip->txcnt == 0) + ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_RX; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC13xx_SPI_USE_SSP0 || defined(__DOXYGEN__) +/** + * @brief SSP0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(VectorF4) { + + CH_IRQ_PROLOGUE(); + + spi_serve_interrupt(&SPID1); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +#if LPC13xx_SPI_USE_SSP0 + spiObjectInit(&SPID1); + SPID1.ssp = LPC_SSP; + LPC_IOCON->SCKLOC = LPC13xx_SPI_SCK0_SELECTOR; +#if LPC13xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO0_10 + LPC_IOCON->JTAG_TCK_PIO0_10 = 0xC2; /* SCK0 without resistors. */ +#elif LPC13xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO2_11 + LPC_IOCON->PIO2_11 = 0xC1; /* SCK0 without resistors. */ +#else /* LPC13xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO0_6 */ + LPC_IOCON->PIO0_6 = 0xC2; /* SCK0 without resistors. */ +#endif + LPC_IOCON->PIO0_8 = 0xC1; /* MISO0 without resistors. */ + LPC_IOCON->PIO0_9 = 0xC1; /* MOSI0 without resistors. */ +#endif /* LPC13xx_SPI_USE_SSP0 */ +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + if (spip->state == SPI_STOP) { + /* Clock activation.*/ +#if LPC13xx_SPI_USE_SSP0 + if (&SPID1 == spip) { + LPC_SYSCON->SSPCLKDIV = LPC13xx_SPI_SSP0CLKDIV; + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 11); + LPC_SYSCON->PRESETCTRL |= 1; + nvicEnableVector(SSP_IRQn, + CORTEX_PRIORITY_MASK(LPC13xx_SPI_SSP0_IRQ_PRIORITY)); + } +#endif + } + /* Configuration.*/ + spip->ssp->CR1 = 0; + spip->ssp->ICR = ICR_RT | ICR_ROR; + spip->ssp->CR0 = spip->config->cr0; + spip->ssp->CPSR = spip->config->cpsr; + spip->ssp->CR1 = CR1_SSE; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + if (spip->state != SPI_STOP) { + spip->ssp->CR1 = 0; + spip->ssp->CR0 = 0; + spip->ssp->CPSR = 0; +#if LPC13xx_SPI_USE_SSP0 + if (&SPID1 == spip) { + LPC_SYSCON->PRESETCTRL &= ~1; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 11); + LPC_SYSCON->SSPCLKDIV = 0; + nvicDisableVector(SSP_IRQn); + } +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This function transmits a series of idle words on the SPI bus and + * ignores the received data. This function can be invoked even + * when a slave select signal has not been yet asserted. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + spip->rxptr = NULL; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + spip->rxptr = NULL; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + spip->ssp->DR = (uint32_t)frame; + while ((spip->ssp->SR & SR_RNE) == 0) + ; + return (uint16_t)spip->ssp->DR; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC13xx/spi_lld.h b/Project/os/hal/platforms/LPC13xx/spi_lld.h new file mode 100644 index 0000000..f72c7ef --- /dev/null +++ b/Project/os/hal/platforms/LPC13xx/spi_lld.h @@ -0,0 +1,313 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC13xx/spi_lld.h + * @brief LPC13xx low level SPI driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Hardware FIFO depth. + */ +#define LPC13xx_SSP_FIFO_DEPTH 8 + +#define CR0_DSSMASK 0x0F +#define CR0_DSS4BIT 3 +#define CR0_DSS5BIT 4 +#define CR0_DSS6BIT 5 +#define CR0_DSS7BIT 6 +#define CR0_DSS8BIT 7 +#define CR0_DSS9BIT 8 +#define CR0_DSS10BIT 9 +#define CR0_DSS11BIT 0xA +#define CR0_DSS12BIT 0xB +#define CR0_DSS13BIT 0xC +#define CR0_DSS14BIT 0xD +#define CR0_DSS15BIT 0xE +#define CR0_DSS16BIT 0xF +#define CR0_FRFSPI 0 +#define CR0_FRFSSI 0x10 +#define CR0_FRFMW 0x20 +#define CR0_CPOL 0x40 +#define CR0_CPHA 0x80 +#define CR0_CLOCKRATE(n) ((n) << 8) + +#define CR1_LBM 1 +#define CR1_SSE 2 +#define CR1_MS 4 +#define CR1_SOD 8 + +#define SR_TFE 1 +#define SR_TNF 2 +#define SR_RNE 4 +#define SR_RFF 8 +#define SR_BSY 16 + +#define IMSC_ROR 1 +#define IMSC_RT 2 +#define IMSC_RX 4 +#define IMSC_TX 8 + +#define RIS_ROR 1 +#define RIS_RT 2 +#define RIS_RX 4 +#define RIS_TX 8 + +#define MIS_ROR 1 +#define MIS_RT 2 +#define MIS_RX 4 +#define MIS_TX 8 + +#define ICR_ROR 1 +#define ICR_RT 2 + +/** + * @brief SCK0 signal assigned to pin PIO0_10. + */ +#define SCK0_IS_PIO0_10 0 + +/** + * @brief SCK0 signal assigned to pin PIO2_11. + */ +#define SCK0_IS_PIO2_11 1 + +/** + * @brief SCK0 signal assigned to pin PIO0_6. + */ +#define SCK0_IS_PIO0_6 2 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for device SSP0 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC13xx_SPI_USE_SSP0) || defined(__DOXYGEN__) +#define LPC13xx_SPI_USE_SSP0 TRUE +#endif + +/** + * @brief SSP0 PCLK divider. + */ +#if !defined(LPC13xx_SPI_SSP0CLKDIV) || defined(__DOXYGEN__) +#define LPC13xx_SPI_SSP0CLKDIV 1 +#endif + +/** + * @brief SPI0 interrupt priority level setting. + */ +#if !defined(LPC13xx_SPI_SSP0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC13xx_SPI_SSP0_IRQ_PRIORITY 5 +#endif + +/** + * @brief Overflow error hook. + * @details The default action is to stop the system. + */ +#if !defined(LPC13xx_SPI_SSP_ERROR_HOOK) || defined(__DOXYGEN__) +#define LPC13xx_SPI_SSP_ERROR_HOOK(spip) chSysHalt() +#endif + +/** + * @brief SCK0 signal selector. + */ +#if !defined(LPC13xx_SPI_SCK0_SELECTOR) || defined(__DOXYGEN__) +#define LPC13xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (LPC13xx_SPI_SSP0CLKDIV < 1) || (LPC13xx_SPI_SSP0CLKDIV > 255) +#error "invalid LPC13xx_SPI_SSP0CLKDIV setting" +#endif + +#if !LPC13xx_SPI_USE_SSP0 +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +#if (LPC13xx_SPI_SCK0_SELECTOR != SCK0_IS_PIO0_10) && \ + (LPC13xx_SPI_SCK0_SELECTOR != SCK0_IS_PIO2_11) && \ + (LPC13xx_SPI_SCK0_SELECTOR != SCK0_IS_PIO0_6) +#error "invalid pin assigned to SCK0 signal" +#endif + +/** + * @brief SSP0 clock. + */ +#define LPC13xx_SERIAL_SSP0_PCLK \ + (LPC13xx_MAINCLK / LPC13xx_SERIAL_SSP0CLKDIV) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief SSP CR0 initialization data. + */ + uint16_t cr0; + /** + * @brief SSP CPSR initialization data. + */ + uint32_t cpsr; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SSP registers block. + */ + LPC_SSP_TypeDef *ssp; + /** + * @brief Number of bytes yet to be received. + */ + uint32_t rxcnt; + /** + * @brief Receive pointer or @p NULL. + */ + void *rxptr; + /** + * @brief Number of bytes yet to be transmitted. + */ + uint32_t txcnt; + /** + * @brief Transmit pointer or @p NULL. + */ + const void *txptr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC13xx_SPI_USE_SSP0 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC13xx/system_LPC13xx.h b/Project/os/hal/platforms/LPC13xx/system_LPC13xx.h new file mode 100644 index 0000000..5b9f2ff --- /dev/null +++ b/Project/os/hal/platforms/LPC13xx/system_LPC13xx.h @@ -0,0 +1,64 @@ +/**************************************************************************//** + * @file system_LPC13xx.h + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File + * for the NXP LPC13xx Device Series + * @version V1.01 + * @date 19. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __SYSTEM_LPC13xx_H +#define __SYSTEM_LPC13xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_LPC13x_H */ diff --git a/Project/os/hal/platforms/LPC214x/hal_lld.c b/Project/os/hal/platforms/LPC214x/hal_lld.c new file mode 100644 index 0000000..d0a76cc --- /dev/null +++ b/Project/os/hal/platforms/LPC214x/hal_lld.c @@ -0,0 +1,128 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC214x/hal_lld.c + * @brief LPC214x HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/* + * Non-vectored IRQs handler, the default action can be overridden by + * redefining the @p LPC214x_NON_VECTORED_IRQ_HOOK() hook macro. + */ +static CH_IRQ_HANDLER(irq_handler) { + + CH_IRQ_PROLOGUE(); + + LPC214x_NON_VECTORED_IRQ_HOOK(); + + VICVectAddr = 0; + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + vic_init(); + VICDefVectAddr = (IOREG32)irq_handler; + +} + +/** + * @brief LPC214x clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function must be invoked only after the system reset. + * + * @special + */ +void lpc214x_clock_init(void) { + + /* + * All peripherals clock disabled by default in order to save power. + */ + PCONP = PCRTC | PCTIM0; + + /* + * MAM setup. + */ + MAMTIM = 0x3; /* 3 cycles for flash accesses. */ + MAMCR = 0x2; /* MAM fully enabled. */ + + /* + * PLL setup for Fosc=12MHz and CCLK=48MHz. + * P=2 M=3. + */ + PLL *pll = PLL0Base; + pll->PLL_CFG = 0x23; /* P and M values. */ + pll->PLL_CON = 0x1; /* Enables the PLL 0. */ + pll->PLL_FEED = 0xAA; + pll->PLL_FEED = 0x55; + while (!(pll->PLL_STAT & 0x400)) + ; /* Wait for PLL lock. */ + + pll->PLL_CON = 0x3; /* Connects the PLL. */ + pll->PLL_FEED = 0xAA; + pll->PLL_FEED = 0x55; + + /* + * VPB setup. + * PCLK = CCLK / 4. + */ + VPBDIV = VPD_D4; +} + +/** @} */ diff --git a/Project/os/hal/platforms/LPC214x/hal_lld.h b/Project/os/hal/platforms/LPC214x/hal_lld.h new file mode 100644 index 0000000..36c2606 --- /dev/null +++ b/Project/os/hal/platforms/LPC214x/hal_lld.h @@ -0,0 +1,94 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC214x/hal_lld.h + * @brief LPC214x HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "lpc214x.h" +#include "vic.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "LPC214x" + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Default action for the non vectored IRQ handler, nothing. + */ +#if !defined(LPC214x_NON_VECTORED_IRQ_HOOK) || defined(__DOXYGEN__) +#define LPC214x_NON_VECTORED_IRQ_HOOK() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void lpc214x_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC214x/lpc214x.h b/Project/os/hal/platforms/LPC214x/lpc214x.h new file mode 100644 index 0000000..f68ce2f --- /dev/null +++ b/Project/os/hal/platforms/LPC214x/lpc214x.h @@ -0,0 +1,534 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file lpc214x.h + * @brief LPC214x register definitions. + */ + +#ifndef _LPC214X_H_ +#define _LPC214X_H_ + +typedef volatile uint8_t IOREG8; +typedef volatile uint16_t IOREG16; +typedef volatile uint32_t IOREG32; + +/* + * System. + */ +#define MEMMAP (*((IOREG32 *)0xE01FC040)) +#define PCON (*((IOREG32 *)0xE01FC0C0)) +#define PCONP (*((IOREG32 *)0xE01FC0C4)) +#define VPBDIV (*((IOREG32 *)0xE01FC100)) +#define EXTINT (*((IOREG32 *)0xE01FC140)) +#define INTWAKE (*((IOREG32 *)0xE01FC144)) +#define EXTMODE (*((IOREG32 *)0xE01FC148)) +#define EXTPOLAR (*((IOREG32 *)0xE01FC14C)) +#define RSID (*((IOREG32 *)0xE01FC180)) +#define CSPR (*((IOREG32 *)0xE01FC184)) +#define SCS (*((IOREG32 *)0xE01FC1A0)) + +#define VPD_D4 0 +#define VPD_D1 1 +#define VPD_D2 2 +#define VPD_RESERVED 3 + +#define PCTIM0 (1 << 1) +#define PCTIM1 (1 << 2) +#define PCUART0 (1 << 3) +#define PCUART1 (1 << 4) +#define PCPWM0 (1 << 5) +#define PCI2C0 (1 << 7) +#define PCSPI0 (1 << 8) +#define PCRTC (1 << 9) +#define PCSPI1 (1 << 10) +#define PCAD0 (1 << 12) +#define PCI2C1 (1 << 19) +#define PCAD1 (1 << 20) +#define PCUSB (1 << 31) +#define PCALL (PCTIM0 | PCTIM1 | PCUART0 | PCUART1 | \ + PCPWM0 | PCI2C0 | PCSPI0 | PCRTC | PCSPI1 | \ + PCAD0 | PCI2C1 | PCAD1 | PCUSB) + +#define EINT0 1 +#define EINT1 2 +#define EINT2 4 +#define EINT3 8 + +#define EXTWAKE0 1 +#define EXTWAKE1 2 +#define EXTWAKE2 4 +#define EXTWAKE3 8 +#define USBWAKE 0x20 +#define BODWAKE 0x4000 +#define RTCWAKE 0x8000 + +#define EXTMODE0 1 +#define EXTMODE1 2 +#define EXTMODE2 4 +#define EXTMODE3 8 + +#define EXTPOLAR0 1 +#define EXTPOLAR1 2 +#define EXTPOLAR2 4 +#define EXTPOLAR3 8 + +typedef struct { + IOREG32 PLL_CON; + IOREG32 PLL_CFG; + IOREG32 PLL_STAT; + IOREG32 PLL_FEED; +} PLL; + +#define PLL0Base ((PLL *)0xE01FC080) +#define PLL1Base ((PLL *)0xE01FC0A0) +#define PLL0CON (PLL0Base->PLL_CON) +#define PLL0CFG (PLL0Base->PLL_CFG) +#define PLL0STAT (PLL0Base->PLL_STAT) +#define PLL0FEED (PLL0Base->PLL_FEED) +#define PLL1CON (PLL1Base->PLL_CON) +#define PLL1CFG (PLL1Base->PLL_CFG) +#define PLL1STAT (PLL1Base->PLL_STAT) +#define PLL1FEED (PLL1Base->PLL_FEED) + +/* + * Pins. + */ +typedef struct { + IOREG32 PS_SEL0; + IOREG32 PS_SEL1; + IOREG32 _dummy[3]; + IOREG32 PS_SEL2; +} PS; + +#define PSBase ((PS *)0xE002C000) +#define PINSEL0 (PSBase->PS_SEL0) +#define PINSEL1 (PSBase->PS_SEL1) +#define PINSEL2 (PSBase->PS_SEL2) + +/* + * VIC + */ +#define SOURCE_WDT 0 +#define SOURCE_ARMCore0 2 +#define SOURCE_ARMCore1 3 +#define SOURCE_Timer0 4 +#define SOURCE_Timer1 5 +#define SOURCE_UART0 6 +#define SOURCE_UART1 7 +#define SOURCE_PWM0 8 +#define SOURCE_I2C0 9 +#define SOURCE_SPI0 10 +#define SOURCE_SPI1 11 +#define SOURCE_PLL 12 +#define SOURCE_RTC 13 +#define SOURCE_EINT0 14 +#define SOURCE_EINT1 15 +#define SOURCE_EINT2 16 +#define SOURCE_EINT3 17 +#define SOURCE_ADC0 18 +#define SOURCE_I2C1 19 +#define SOURCE_BOD 20 +#define SOURCE_ADC1 21 +#define SOURCE_USB 22 + +#define INTMASK(n) (1 << (n)) +#define ALLINTMASK (INTMASK(SOURCE_WDT) | INTMASK(SOURCE_ARMCore0) | \ + INTMASK(SOURCE_ARMCore1) | INTMASK(SOURCE_Timer0) | \ + INTMASK(SOURCE_Timer1) | INTMASK(SOURCE_UART0) | \ + INTMASK(SOURCE_UART1) | INTMASK(SOURCE_PWM0) | \ + INTMASK(SOURCE_I2C0) | INTMASK(SOURCE_SPI0) | \ + INTMASK(SOURCE_SPI1) | INTMASK(SOURCE_PLL) | \ + INTMASK(SOURCE_RTC) | INTMASK(SOURCE_EINT0) | \ + INTMASK(SOURCE_EINT1) | INTMASK(SOURCE_EINT2) | \ + INTMASK(SOURCE_EINT3) | INTMASK(SOURCE_ADC0) | \ + INTMASK(SOURCE_I2C1) | INTMASK(SOURCE_BOD) | \ + INTMASK(SOURCE_ADC1) | INTMASK(SOURCE_USB)) + +typedef struct { + IOREG32 VIC_IRQStatus; + IOREG32 VIC_FIQStatus; + IOREG32 VIC_RawIntr; + IOREG32 VIC_IntSelect; + IOREG32 VIC_IntEnable; + IOREG32 VIC_IntEnClear; + IOREG32 VIC_SoftInt; + IOREG32 VIC_SoftIntClear; + IOREG32 VIC_Protection; + IOREG32 unused1[3]; + IOREG32 VIC_VectAddr; + IOREG32 VIC_DefVectAddr; + IOREG32 unused2[50]; + IOREG32 VIC_VectAddrs[16]; + IOREG32 unused3[48]; + IOREG32 VIC_VectCntls[16]; +} VIC; + +#define VICBase ((VIC *)0xFFFFF000) +#define VICVectorsBase ((IOREG32 *)0xFFFFF100) +#define VICControlsBase ((IOREG32 *)0xFFFFF200) + +#define VICIRQStatus (VICBase->VIC_IRQStatus) +#define VICFIQStatus (VICBase->VIC_FIQStatus) +#define VICRawIntr (VICBase->VIC_RawIntr) +#define VICIntSelect (VICBase->VIC_IntSelect) +#define VICIntEnable (VICBase->VIC_IntEnable) +#define VICIntEnClear (VICBase->VIC_IntEnClear) +#define VICSoftInt (VICBase->VIC_SoftInt) +#define VICSoftIntClear (VICBase->VIC_SoftIntClear) +#define VICProtection (VICBase->VIC_Protection) +#define VICVectAddr (VICBase->VIC_VectAddr) +#define VICDefVectAddr (VICBase->VIC_DefVectAddr) + +#define VICVectAddrs(n) (VICBase->VIC_VectAddrs[n]) +#define VICVectCntls(n) (VICBase->VIC_VectCntls[n]) + +/* + * MAM. + */ +typedef struct { + IOREG32 MAM_Control; + IOREG32 MAM_Timing; +} MAM; + +#define MAMBase ((MAM *)0xE01FC000) +#define MAMCR (MAMBase->MAM_Control) +#define MAMTIM (MAMBase->MAM_Timing) + +/* + * GPIO - FIO. + */ +typedef struct { + IOREG32 IO_PIN; + IOREG32 IO_SET; + IOREG32 IO_DIR; + IOREG32 IO_CLR; +} GPIO; + +#define GPIO0Base ((GPIO *)0xE0028000) +#define IO0PIN (GPIO0Base->IO_PIN) +#define IO0SET (GPIO0Base->IO_SET) +#define IO0DIR (GPIO0Base->IO_DIR) +#define IO0CLR (GPIO0Base->IO_CLR) + +#define GPIO1Base ((GPIO *)0xE0028010) +#define IO1PIN (GPIO1Base->IO_PIN) +#define IO1SET (GPIO1Base->IO_SET) +#define IO1DIR (GPIO1Base->IO_DIR) +#define IO1CLR (GPIO1Base->IO_CLR) + +typedef struct { + IOREG32 FIO_DIR; + IOREG32 unused1; + IOREG32 unused2; + IOREG32 unused3; + IOREG32 FIO_MASK; + IOREG32 FIO_PIN; + IOREG32 FIO_SET; + IOREG32 FIO_CLR; +} FIO; + +#define FIO0Base ((FIO *)0x3FFFC000) +#define FIO0DIR (FIO0Base->FIO_DIR) +#define FIO0MASK (FIO0Base->FIO_MASK) +#define FIO0PIN (FIO0Base->FIO_PIN) +#define FIO0SET (FIO0Base->FIO_SET) +#define FIO0CLR (FIO0Base->FIO_CLR) + +#define FIO1Base ((FIO *)0x3FFFC020) +#define FIO1DIR (FIO1Base->FIO_DIR) +#define FIO1MASK (FIO1Base->FIO_MASK) +#define FIO1PIN (FIO1Base->FIO_PIN) +#define FIO1SET (FIO1Base->FIO_SET) +#define FIO1CLR (FIO1Base->FIO_CLR) + +/* + * UART. + */ +typedef struct { + union { + IOREG32 UART_RBR; + IOREG32 UART_THR; + IOREG32 UART_DLL; + }; + union { + IOREG32 UART_IER; + IOREG32 UART_DLM; + }; + union { + IOREG32 UART_IIR; + IOREG32 UART_FCR; + }; + IOREG32 UART_LCR; + IOREG32 UART_MCR; + IOREG32 UART_LSR; + IOREG32 unused18; + IOREG32 UART_SCR; + IOREG32 UART_ACR; + IOREG32 unused24; + IOREG32 UART_FDR; + IOREG32 unused2C; + IOREG32 UART_TER; +} UART; + +#define U0Base ((UART *)0xE000C000) +#define U0RBR (U0Base->UART_RBR) +#define U0THR (U0Base->UART_THR) +#define U0DLL (U0Base->UART_DLL) +#define U0IER (U0Base->UART_IER) +#define U0DLM (U0Base->UART_DLM) +#define U0IIR (U0Base->UART_IIR) +#define U0FCR (U0Base->UART_FCR) +#define U0LCR (U0Base->UART_LCR) +#define U0LSR (U0Base->UART_LSR) +#define U0SCR (U0Base->UART_SCR) +#define U0ACR (U0Base->UART_ACR) +#define U0FDR (U0Base->UART_FDR) +#define U0TER (U0Base->UART_TER) + +#define U1Base ((UART *)0xE0010000) +#define U1RBR (U1Base->UART_RBR) +#define U1THR (U1Base->UART_THR) +#define U1DLL (U1Base->UART_DLL) +#define U1IER (U1Base->UART_IER) +#define U1DLM (U1Base->UART_DLM) +#define U1IIR (U1Base->UART_IIR) +#define U1FCR (U1Base->UART_FCR) +#define U1MCR (U1Base->UART_MCR) +#define U1LCR (U1Base->UART_LCR) +#define U1LSR (U1Base->UART_LSR) +#define U1SCR (U1Base->UART_SCR) +#define U1ACR (U1Base->UART_ACR) +#define U1FDR (U1Base->UART_FDR) +#define U1TER (U1Base->UART_TER) + +#define IIR_SRC_MASK 0x0F +#define IIR_SRC_NONE 0x01 +#define IIR_SRC_TX 0x02 +#define IIR_SRC_RX 0x04 +#define IIR_SRC_ERROR 0x06 +#define IIR_SRC_TIMEOUT 0x0C + +#define IER_RBR 1 +#define IER_THRE 2 +#define IER_STATUS 4 + +#define IIR_INT_PENDING 1 + +#define LCR_WL5 0 +#define LCR_WL6 1 +#define LCR_WL7 2 +#define LCR_WL8 3 +#define LCR_STOP1 0 +#define LCR_STOP2 4 +#define LCR_NOPARITY 0 +#define LCR_PARITYODD 0x08 +#define LCR_PARITYEVEN 0x18 +#define LCR_PARITYONE 0x28 +#define LCR_PARITYZERO 0x38 +#define LCR_BREAK_ON 0x40 +#define LCR_DLAB 0x80 + +#define FCR_ENABLE 1 +#define FCR_RXRESET 2 +#define FCR_TXRESET 4 +#define FCR_TRIGGER0 0 +#define FCR_TRIGGER1 0x40 +#define FCR_TRIGGER2 0x80 +#define FCR_TRIGGER3 0xC0 + +#define LSR_RBR_FULL 1 +#define LSR_OVERRUN 2 +#define LSR_PARITY 4 +#define LSR_FRAMING 8 +#define LSR_BREAK 0x10 +#define LSR_THRE 0x20 +#define LSR_TEMT 0x40 +#define LSR_RXFE 0x80 + +#define TER_ENABLE 0x80 + +/* + * SSP. + */ +typedef struct { + IOREG32 SSP_CR0; + IOREG32 SSP_CR1; + IOREG32 SSP_DR; + IOREG32 SSP_SR; + IOREG32 SSP_CPSR; + IOREG32 SSP_IMSC; + IOREG32 SSP_RIS; + IOREG32 SSP_MIS; + IOREG32 SSP_ICR; +} SSP; + +#define SSPBase ((SSP *)0xE0068000) +#define SSPCR0 (SSPBase->SSP_CR0) +#define SSPCR1 (SSPBase->SSP_CR1) +#define SSPDR (SSPBase->SSP_DR) +#define SSPSR (SSPBase->SSP_SR) +#define SSPCPSR (SSPBase->SSP_CPSR) +#define SSPIMSC (SSPBase->SSP_IMSC) +#define SSPRIS (SSPBase->SSP_RIS) +#define SSPMIS (SSPBase->SSP_MIS) +#define SSPICR (SSPBase->SSP_ICR) + +#define CR0_DSSMASK 0x0F +#define CR0_DSS4BIT 3 +#define CR0_DSS5BIT 4 +#define CR0_DSS6BIT 5 +#define CR0_DSS7BIT 6 +#define CR0_DSS8BIT 7 +#define CR0_DSS9BIT 8 +#define CR0_DSS10BIT 9 +#define CR0_DSS11BIT 0xA +#define CR0_DSS12BIT 0xB +#define CR0_DSS13BIT 0xC +#define CR0_DSS14BIT 0xD +#define CR0_DSS15BIT 0xE +#define CR0_DSS16BIT 0xF +#define CR0_FRFSPI 0 +#define CR0_FRFSSI 0x10 +#define CR0_FRFMW 0x20 +#define CR0_CPOL 0x40 +#define CR0_CPHA 0x80 +#define CR0_CLOCKRATE(n) ((n) << 8) + +#define CR1_LBM 1 +#define CR1_SSE 2 +#define CR1_MS 4 +#define CR1_SOD 8 + +#define SR_TFE 1 +#define SR_TNF 2 +#define SR_RNE 4 +#define SR_RFF 8 +#define SR_BSY 0x10 + +#define IMSC_ROR 1 +#define IMSC_RT 2 +#define IMSC_RX 4 +#define IMSC_TX 8 + +#define RIS_ROR 1 +#define RIS_RT 2 +#define RIS_RX 4 +#define RIS_TX 8 + +#define MIS_ROR 1 +#define MIS_RT 2 +#define MIS_RX 4 +#define MIS_TX 8 + +#define ICR_ROR 1 +#define ICR_RT 2 + +/* + * Timers/Counters. + */ +typedef struct { + IOREG32 TC_IR; + IOREG32 TC_TCR; + IOREG32 TC_TC; + IOREG32 TC_PR; + IOREG32 TC_PC; + IOREG32 TC_MCR; + IOREG32 TC_MR0; + IOREG32 TC_MR1; + IOREG32 TC_MR2; + IOREG32 TC_MR3; + IOREG32 TC_CCR; + IOREG32 TC_CR0; + IOREG32 TC_CR1; + IOREG32 TC_CR2; + IOREG32 TC_CR3; + IOREG32 TC_EMR; + IOREG32 TC_CTCR; +} TC; + +#define T0Base ((TC *)0xE0004000) +#define T0IR (T0Base->TC_IR) +#define T0TCR (T0Base->TC_TCR) +#define T0TC (T0Base->TC_TC) +#define T0PR (T0Base->TC_PR) +#define T0PC (T0Base->TC_PC) +#define T0MCR (T0Base->TC_MCR) +#define T0MR0 (T0Base->TC_MR0) +#define T0MR1 (T0Base->TC_MR1) +#define T0MR2 (T0Base->TC_MR2) +#define T0MR3 (T0Base->TC_MR3) +#define T0CCR (T0Base->TC_CCR) +#define T0CR0 (T0Base->TC_CR0) +#define T0CR1 (T0Base->TC_CR1) +#define T0CR2 (T0Base->TC_CR2) +#define T0CR3 (T0Base->TC_CR3) +#define T0EMR (T0Base->TC_EMR) +#define T0CTCR (T0Base->TC_CTCR) + +#define T1Base ((TC *)0xE0008000) +#define T1IR (T1Base->TC_IR) +#define T1TCR (T1Base->TC_TCR) +#define T1TC (T1Base->TC_TC) +#define T1PR (T1Base->TC_PR) +#define T1PC (T1Base->TC_PC) +#define T1MCR (T1Base->TC_MCR) +#define T1MR0 (T1Base->TC_MR0) +#define T1MR1 (T1Base->TC_MR1) +#define T1MR2 (T1Base->TC_MR2) +#define T1MR3 (T1Base->TC_MR3) +#define T1CCR (T1Base->TC_CCR) +#define T1CR0 (T1Base->TC_CR0) +#define T1CR1 (T1Base->TC_CR1) +#define T1CR2 (T1Base->TC_CR2) +#define T1CR3 (T1Base->TC_CR3) +#define T1EMR (T1Base->TC_EMR) +#define T1CTCR (T1Base->TC_CTCR) + +/* + * Watchdog. + */ +typedef struct { + IOREG32 WD_MOD; + IOREG32 WD_TC; + IOREG32 WD_FEED; + IOREG32 WD_TV; +} WD; + +#define WDBase ((WD *)0xE0000000) +#define WDMOD (WDBase->WD_MOD) +#define WDTC (WDBase->WD_TC) +#define WDFEED (WDBase->WD_FEED) +#define WDTV (WDBase->WD_TV) + +/* + * DAC. + */ +#define DACR (*((IOREG32 *)0xE006C000)) + +#endif /* _LPC214X_H_ */ + diff --git a/Project/os/hal/platforms/LPC214x/pal_lld.c b/Project/os/hal/platforms/LPC214x/pal_lld.c new file mode 100644 index 0000000..4591134 --- /dev/null +++ b/Project/os/hal/platforms/LPC214x/pal_lld.c @@ -0,0 +1,123 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC214x/pal_lld.c + * @brief LPC214x FIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief LPC214x I/O ports configuration. + * @details FIO units and PINSEL registers initialization. + * + * @param[in] config the LPC214x ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + /* Enables the access through the fast registers.*/ + SCS = 3; + + /* I/O pads initial assignment, device drivers may change this setup at a + * later time.*/ + PINSEL0 = config->pinsel0; + PINSEL1 = config->pinsel1; + PINSEL2 = config->pinsel2; + + /* I/O pads direction initial setting.*/ + FIO0Base->FIO_MASK = 0; + FIO0Base->FIO_PIN = config->P0Data.pin; + FIO0Base->FIO_DIR = config->P0Data.dir; + FIO1Base->FIO_MASK = 0; + FIO1Base->FIO_PIN = config->P1Data.pin; + FIO1Base->FIO_DIR = config->P1Data.dir; +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with + * high state. + * @note This function does not alter the @p PINSELx registers. Alternate + * functions setup must be handled by device-specific code. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + port->FIO_DIR &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + port->FIO_PIN |= mask; + case PAL_MODE_OUTPUT_PUSHPULL: + port->FIO_DIR |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC214x/pal_lld.h b/Project/os/hal/platforms/LPC214x/pal_lld.h new file mode 100644 index 0000000..af2fc9e --- /dev/null +++ b/Project/os/hal/platforms/LPC214x/pal_lld.h @@ -0,0 +1,272 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC214x/pal_lld.h + * @brief LPC214x FIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief FIO port setup info. + */ +typedef struct { + /** Initial value for FIO_PIN register.*/ + uint32_t pin; + /** Initial value for FIO_DIR register.*/ + uint32_t dir; +} lpc214x_fio_setup_t; + +/** + * @brief LPC214x FIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialize the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { + /** @brief PINSEL0 initial value.*/ + uint32_t pinsel0; + /** @brief PINSEL1 initial value.*/ + uint32_t pinsel1; + /** @brief PINSEL2 initial value.*/ + uint32_t pinsel2; + /** @brief Port 0 setup data.*/ + lpc214x_fio_setup_t P0Data; + /** @brief Port 1 setup data.*/ + lpc214x_fio_setup_t P1Data; +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 32 + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + */ +typedef FIO * ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief FIO port 0 identifier. + */ +#define IOPORT1 FIO0Base + +/** + * @brief FIO port 1 identifier. + */ +#define IOPORT2 FIO1Base + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief FIO subsystem initialization. + * @details Enables the access through the fast registers. + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads an I/O port. + * @details This function is implemented by reading the FIO PIN register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->FIO_PIN) + +/** + * @brief Reads the output latch. + * @details This function is implemented by reading the FIO SET register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->FIO_SET) + +/** + * @brief Writes a bits mask on a I/O port. + * @details This function is implemented by writing the FIO PIN register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->FIO_PIN = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @details This function is implemented by writing the FIO SET register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) ((port)->FIO_SET = (bits)) + +/** + * @brief Clears a bits mask on a I/O port. + * @details This function is implemented by writing the FIO CLR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) ((port)->FIO_CLR = (bits)) + +/** + * @brief Writes a value on an I/O bus. + * @details This function is implemented by writing the FIO PIN and MASK + * registers, the implementation is not atomic because the multiple + * accesses. + * + * @param[in] port port identifier + * @param[in] mask group mask, a logical AND is performed on the + * output data + * @param[in] offset the group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group + * width are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + ((port)->FIO_MASK = ~((mask) << (offset)), \ + (port)->FIO_PIN = (bits) << (offset), \ + (port)->FIO_MASK = 0) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with + * high state. + * @note This function does not alter the @p PINSELx registers. Alternate + * functions setup must be handled by device-specific code. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) + +/** + * @brief FIO port setup. + * @details This function programs the pins direction within a port. + * + * @notapi + */ +#define pal_lld_lpc214x_set_direction(port, dir) ((port)->FIO_DIR = (dir)) + +extern const PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC214x/platform.dox b/Project/os/hal/platforms/LPC214x/platform.dox new file mode 100644 index 0000000..22a7b75 --- /dev/null +++ b/Project/os/hal/platforms/LPC214x/platform.dox @@ -0,0 +1,129 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup LPC214x LPC214x Drivers + * @details This section describes all the supported drivers on the LPC214x + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup LPC214x_HAL LPC214x Initialization Support + * @details The LPC214x HAL support is responsible for system initialization. + * + * @section lpc214x_hal_1 Supported HW resources + * - PLL0. + * - MAM. + * - VPBDIV. + * . + * @section lpc214x_hal_2 LPC214x HAL driver implementation features + * - Clock tree initialization. + * - Clock source selection. + * - MAM initialization. + * . + * @ingroup LPC214x + */ + +/** + * @defgroup LPC214x_PAL LPC214x PAL Support + * @details The LPC214x PAL driver uses the FIO peripherals. + * + * @section lpc214x_pal_1 Supported HW resources + * - FIO0. + * - FIO1. + * . + * @section lpc214x_pal_2 LPC214x PAL driver implementation features + * - 32 bits wide ports. + * - Atomic set/reset functions. + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section lpc214x_pal_3 Supported PAL setup modes + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_ANALOG (same as @p PAL_MODE_INPUT). + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section lpc214x_pal_4 Suboptimal behavior + * Some FIO features are less than optimal: + * - Pad/port toggling operations are not atomic. + * - Pad/group mode setup is not atomic. + * . + * @ingroup LPC214x + */ + +/** + * @defgroup LPC214x_SERIAL LPC214x Serial Support + * @details The LPC214x Serial driver uses the UART peripherals in a + * buffered, interrupt driven, implementation. The serial driver + * also takes advantage of the LPC214x UARTs deep hardware buffers. + * + * @section lpc214x_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - UART0. + * - UART1. + * . + * @section lpc214x_serial_2 LPC214x Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Fully interrupt driven. + * - Programmable interrupt priority levels for each UART. + * - Takes advantage of the input and output FIFOs. + * . + * @ingroup LPC214x + */ + +/** + * @defgroup LPC214x_SPI LPC214x SPI Support + * @details The SPI driver supports the LPC214x SSP peripheral in an interrupt + * driven implementation. + * @note Being the SPI a fast peripheral, much care must be taken to + * not saturate the CPU bandwidth with an excessive IRQ rate. The + * maximum transfer bit rate is likely limited by the IRQ + * handling. + * + * @section lpc214x_spi_1 Supported HW resources + * - SSP (SPI0). + * . + * @section lpc214x_spi_2 LPC214x SPI driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Programmable interrupt priority level. + * . + * @ingroup LPC214x + */ + +/** + * @defgroup LPC214x_VIC LPC214x VIC Support + * @details This VIC helper driver is used by the other drivers in order to + * access the shared VIC resources in a consistent way. + * + * @ingroup LPC214x + */ diff --git a/Project/os/hal/platforms/LPC214x/platform.mk b/Project/os/hal/platforms/LPC214x/platform.mk new file mode 100644 index 0000000..0253e47 --- /dev/null +++ b/Project/os/hal/platforms/LPC214x/platform.mk @@ -0,0 +1,9 @@ +# List of all the LPC214x platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC214x/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC214x/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC214x/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC214x/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC214x/vic.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC214x diff --git a/Project/os/hal/platforms/LPC214x/serial_lld.c b/Project/os/hal/platforms/LPC214x/serial_lld.c new file mode 100644 index 0000000..f735f95 --- /dev/null +++ b/Project/os/hal/platforms/LPC214x/serial_lld.c @@ -0,0 +1,358 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC214x/serial_lld.c + * @brief LPC214x low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if USE_LPC214x_UART0 || defined(__DOXYGEN__) +/** @brief UART0 serial driver identifier.*/ +SerialDriver SD1; +#endif + +#if USE_LPC214x_UART1 || defined(__DOXYGEN__) +/** @brief UART1 serial driver identifier.*/ +SerialDriver SD2; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = { + SERIAL_DEFAULT_BITRATE, + LCR_WL8 | LCR_STOP1 | LCR_NOPARITY, + FCR_TRIGGER0 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief UART initialization. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] config the architecture-dependent serial driver configuration + */ +static void uart_init(SerialDriver *sdp, const SerialConfig *config) { + UART *u = sdp->uart; + + uint32_t div = PCLK / (config->sc_speed << 4); + u->UART_LCR = config->sc_lcr | LCR_DLAB; + u->UART_DLL = div; + u->UART_DLM = div >> 8; + u->UART_LCR = config->sc_lcr; + u->UART_FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | config->sc_fcr; + u->UART_ACR = 0; + u->UART_FDR = 0x10; + u->UART_TER = TER_ENABLE; + u->UART_IER = IER_RBR | IER_STATUS; +} + +/** + * @brief UART de-initialization. + * + * @param[in] u pointer to an UART I/O block + */ +static void uart_deinit(UART *u) { + + u->UART_LCR = LCR_DLAB; + u->UART_DLL = 1; + u->UART_DLM = 0; + u->UART_LCR = 0; + u->UART_FDR = 0x10; + u->UART_IER = 0; + u->UART_FCR = FCR_RXRESET | FCR_TXRESET; + u->UART_ACR = 0; + u->UART_TER = TER_ENABLE; +} + +/** + * @brief Error handling routine. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] err UART LSR register value + */ +static void set_error(SerialDriver *sdp, IOREG32 err) { + ioflags_t sts = 0; + + if (err & LSR_OVERRUN) + sts |= SD_OVERRUN_ERROR; + if (err & LSR_PARITY) + sts |= SD_PARITY_ERROR; + if (err & LSR_FRAMING) + sts |= SD_FRAMING_ERROR; + if (err & LSR_BREAK) + sts |= SD_BREAK_DETECTED; + chSysLockFromIsr(); + chIOAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +#if defined(__GNUC__) +__attribute__((noinline)) +#endif +/** + * @brief Common IRQ handler. + * @note Tries hard to clear all the pending interrupt sources, we dont want + * to go through the whole ISR and have another interrupt soon after. + * + * @param[in] sdp communication channel associated to the UART + */ +static void serve_interrupt(SerialDriver *sdp) { + UART *u = sdp->uart; + + while (TRUE) { + switch (u->UART_IIR & IIR_SRC_MASK) { + case IIR_SRC_NONE: + return; + case IIR_SRC_ERROR: + set_error(sdp, u->UART_LSR); + break; + case IIR_SRC_TIMEOUT: + case IIR_SRC_RX: + chSysLockFromIsr(); + if (chIQIsEmptyI(&sdp->iqueue)) + chIOAddFlagsI(sdp, IO_INPUT_AVAILABLE); + chSysUnlockFromIsr(); + while (u->UART_LSR & LSR_RBR_FULL) { + chSysLockFromIsr(); + if (chIQPutI(&sdp->iqueue, u->UART_RBR) < Q_OK) + chIOAddFlagsI(sdp, SD_OVERRUN_ERROR); + chSysUnlockFromIsr(); + } + break; + case IIR_SRC_TX: + { + int i = LPC214x_UART_FIFO_PRELOAD; + do { + msg_t b; + + chSysLockFromIsr(); + b = chOQGetI(&sdp->oqueue); + chSysUnlockFromIsr(); + if (b < Q_OK) { + u->UART_IER &= ~IER_THRE; + chSysLockFromIsr(); + chIOAddFlagsI(sdp, IO_OUTPUT_EMPTY); + chSysUnlockFromIsr(); + break; + } + u->UART_THR = b; + } while (--i); + } + break; + default: + (void) u->UART_THR; + (void) u->UART_RBR; + } + } +} + +/** + * @brief Attempts a TX FIFO preload. + */ +static void preload(SerialDriver *sdp) { + UART *u = sdp->uart; + + if (u->UART_LSR & LSR_THRE) { + int i = LPC214x_UART_FIFO_PRELOAD; + do { + msg_t b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) { + chIOAddFlagsI(sdp, IO_OUTPUT_EMPTY); + return; + } + u->UART_THR = b; + } while (--i); + } + u->UART_IER |= IER_THRE; +} + +/** + * @brief Driver SD1 output notification. + */ +#if USE_LPC214x_UART0 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + preload(&SD1); +} +#endif + +/** + * @brief Driver SD2 output notification. + */ +#if USE_LPC214x_UART1 || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + preload(&SD2); +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief UART0 IRQ handler. + * + * @isr + */ +#if USE_LPC214x_UART0 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(UART0IrqHandler) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD1); + VICVectAddr = 0; + + CH_IRQ_EPILOGUE(); +} +#endif + +/** + * @brief UART1 IRQ handler. + * + * @isr + */ +#if USE_LPC214x_UART1 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(UART1IrqHandler) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD2); + VICVectAddr = 0; + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if USE_LPC214x_UART0 + sdObjectInit(&SD1, NULL, notify1); + SD1.uart = U0Base; + SetVICVector(UART0IrqHandler, LPC214x_UART0_PRIORITY, SOURCE_UART0); +#endif +#if USE_LPC214x_UART1 + sdObjectInit(&SD2, NULL, notify2); + SD2.uart = U1Base; + SetVICVector(UART1IrqHandler, LPC214x_UART1_PRIORITY, SOURCE_UART1); +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + + if (sdp->state == SD_STOP) { +#if USE_LPC214x_UART0 + if (&SD1 == sdp) { + PCONP = (PCONP & PCALL) | PCUART0; + VICIntEnable = INTMASK(SOURCE_UART0); + } +#endif +#if USE_LPC214x_UART1 + if (&SD2 == sdp) { + PCONP = (PCONP & PCALL) | PCUART1; + VICIntEnable = INTMASK(SOURCE_UART1); + } +#endif + } + uart_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the UART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) { + uart_deinit(sdp->uart); +#if USE_LPC214x_UART0 + if (&SD1 == sdp) { + PCONP = (PCONP & PCALL) & ~PCUART0; + VICIntEnClear = INTMASK(SOURCE_UART0); + return; + } +#endif +#if USE_LPC214x_UART1 + if (&SD2 == sdp) { + PCONP = (PCONP & PCALL) & ~PCUART1; + VICIntEnClear = INTMASK(SOURCE_UART1); + return; + } +#endif + } +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC214x/serial_lld.h b/Project/os/hal/platforms/LPC214x/serial_lld.h new file mode 100644 index 0000000..7f0eb51 --- /dev/null +++ b/Project/os/hal/platforms/LPC214x/serial_lld.h @@ -0,0 +1,174 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC214x/serial_lld.h + * @brief LPC214x low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief UART0 driver enable switch. + * @details If set to @p TRUE the support for UART0 is included. + * @note The default is @p TRUE . + */ +#if !defined(USE_LPC214x_UART0) || defined(__DOXYGEN__) +#define USE_LPC214x_UART0 TRUE +#endif + +/** + * @brief UART1 driver enable switch. + * @details If set to @p TRUE the support for UART1 is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_LPC214x_UART1) || defined(__DOXYGEN__) +#define USE_LPC214x_UART1 TRUE +#endif + +/** + * @brief FIFO preload parameter. + * @details Configuration parameter, this values defines how many bytes are + * preloaded in the HW transmit FIFO for each interrupt, the maximum + * value is 16 the minimum is 1. + * @note An high value reduces the number of interrupts generated but can + * also increase the worst case interrupt response time because the + * preload loops. + */ +#if !defined(LPC214x_UART_FIFO_PRELOAD) || defined(__DOXYGEN__) +#define LPC214x_UART_FIFO_PRELOAD 16 +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(LPC214x_UART0_PRIORITY) || defined(__DOXYGEN__) +#define LPC214x_UART0_PRIORITY 1 +#endif + +/** + * @brief UART1 interrupt priority level setting. + */ +#if !defined(LPC214x_UART1_PRIORITY) || defined(__DOXYGEN__) +#define LPC214x_UART1_PRIORITY 2 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (LPC214x_UART_FIFO_PRELOAD < 1) || (LPC214x_UART_FIFO_PRELOAD > 16) +#error "invalid LPC214x_UART_FIFO_PRELOAD setting" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief LPC214x Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t sc_speed; + /** + * @brief Initialization value for the LCR register. + */ + uint32_t sc_lcr; + /** + * @brief Initialization value for the FCR register. + */ + uint32_t sc_fcr; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the USART registers block.*/ \ + UART *uart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if USE_LPC214x_UART0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if USE_LPC214x_UART1 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC214x/spi_lld.c b/Project/os/hal/platforms/LPC214x/spi_lld.c new file mode 100644 index 0000000..488934e --- /dev/null +++ b/Project/os/hal/platforms/LPC214x/spi_lld.c @@ -0,0 +1,350 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC214x/spi_lld.c + * @brief LPC214x low level SPI driver code. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if LPC214x_SPI_USE_SSP || defined(__DOXYGEN__) +/** @brief SPI1 driver identifier.*/ +SPIDriver SPID1; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Preloads the transmit FIFO. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void ssp_fifo_preload(SPIDriver *spip) { + SSP *ssp = spip->ssp; + uint32_t n = spip->txcnt > LPC214x_SSP_FIFO_DEPTH ? + LPC214x_SSP_FIFO_DEPTH : spip->txcnt; + + while(((ssp->SSP_SR & SR_TNF) != 0) && (n > 0)) { + if (spip->txptr != NULL) { + if ((ssp->SSP_CR0 & CR0_DSSMASK) > CR0_DSS8BIT) + ssp->SSP_DR = *(uint16_t *)spip->txptr++; + else + ssp->SSP_DR = *(uint8_t *)spip->txptr++; + } + else + ssp->SSP_DR = 0xFFFFFFFF; + n--; + spip->txcnt--; + } +} + +#if defined(__GNUC__) +__attribute__((noinline)) +#endif +/** + * @brief Common IRQ handler. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void serve_interrupt(SPIDriver *spip) { + SSP *ssp = spip->ssp; + + if ((ssp->SSP_MIS & MIS_ROR) != 0) { + /* The overflow condition should never happen because priority is given + to receive but a hook macro is provided anyway...*/ + LPC214x_SPI_SSP_ERROR_HOOK(); + } + ssp->SSP_ICR = ICR_RT | ICR_ROR; + while ((ssp->SSP_SR & SR_RNE) != 0) { + if (spip->rxptr != NULL) { + if ((ssp->SSP_CR0 & CR0_DSSMASK) > CR0_DSS8BIT) + *(uint16_t *)spip->rxptr++ = ssp->SSP_DR; + else + *(uint8_t *)spip->rxptr++ = ssp->SSP_DR; + } + else + (void)ssp->SSP_DR; + if (--spip->rxcnt == 0) { + chDbgAssert(spip->txcnt == 0, + "spi_serve_interrupt(), #1", "counter out of synch"); + /* Stops the IRQ sources.*/ + ssp->SSP_IMSC = 0; + /* Portable SPI ISR code defined in the high level driver, note, it is + a macro.*/ + _spi_isr_code(spip); + return; + } + } + ssp_fifo_preload(spip); + if (spip->txcnt == 0) + ssp->SSP_IMSC = IMSC_ROR | IMSC_RT | IMSC_RX; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC214x_SPI_USE_SSP || defined(__DOXYGEN__) +/** + * @brief SPI1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(SPI1IrqHandler) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SPID1); + VICVectAddr = 0; + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +#if LPC214x_SPI_USE_SSP + spiObjectInit(&SPID1); + SPID1.ssp = SSPBase; + SetVICVector(SPI1IrqHandler, LPC214x_SPI_SSP_IRQ_PRIORITY, SOURCE_SPI1); +#endif +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + if (spip->state == SPI_STOP) { + /* Clock activation.*/ +#if LPC214x_SPI_USE_SSP + if (&SPID1 == spip) { + PCONP = (PCONP & PCALL) | PCSPI1; + VICIntEnable = INTMASK(SOURCE_SPI1); + } +#endif + } + /* Configuration.*/ + spip->ssp->SSP_CR1 = 0; + /* Emptying the receive FIFO, it happens to not be empty while debugging.*/ + while (spip->ssp->SSP_SR & SR_RNE) + (void) spip->ssp->SSP_DR; + spip->ssp->SSP_ICR = ICR_RT | ICR_ROR; + spip->ssp->SSP_CR0 = spip->config->cr0; + spip->ssp->SSP_CPSR = spip->config->cpsr; + spip->ssp->SSP_CR1 = CR1_SSE; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + if (spip->state != SPI_STOP) { + spip->ssp->SSP_CR1 = 0; + spip->ssp->SSP_CR0 = 0; + spip->ssp->SSP_CPSR = 0; +#if LPC214x_SPI_USE_SSP + if (&SPID1 == spip) { + PCONP = (PCONP & PCALL) & ~PCSPI1; + VICIntEnClear = INTMASK(SOURCE_SPI1); + } +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This function transmits a series of idle words on the SPI bus and + * ignores the received data. This function can be invoked even + * when a slave select signal has not been yet asserted. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + spip->rxptr = NULL; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->SSP_IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->SSP_IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + spip->rxptr = NULL; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->SSP_IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->SSP_IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + spip->ssp->SSP_DR = (uint32_t)frame; + while ((spip->ssp->SSP_SR & SR_RNE) == 0) + ; + return (uint16_t)spip->ssp->SSP_DR; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC214x/spi_lld.h b/Project/os/hal/platforms/LPC214x/spi_lld.h new file mode 100644 index 0000000..6c65c86 --- /dev/null +++ b/Project/os/hal/platforms/LPC214x/spi_lld.h @@ -0,0 +1,218 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC214x/spi_lld.h + * @brief LPC214x low level SPI driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Hardware FIFO depth. + */ +#define LPC214x_SSP_FIFO_DEPTH 8 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for SSP is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC214x_SPI_USE_SSP) || defined(__DOXYGEN__) +#define LPC214x_SPI_USE_SSP TRUE +#endif + +/** + * @brief SSP interrupt priority level setting. + */ +#if !defined(LPC214x_SPI_SSP_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC214x_SPI_SSP_IRQ_PRIORITY 4 +#endif + +/** + * @brief Overflow error hook. + * @details The default action is to stop the system. + */ +#if !defined(LPC214x_SPI_SSP_ERROR_HOOK) || defined(__DOXYGEN__) +#define LPC214x_SPI_SSP_ERROR_HOOK() chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !LPC214x_SPI_USE_SSP +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief SSP CR0 initialization data. + */ + uint16_t cr0; + /** + * @brief SSP CPSR initialization data. + */ + uint32_t cpsr; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SSP registers block. + */ + SSP *ssp; + /** + * @brief Number of bytes yet to be received. + */ + uint32_t rxcnt; + /** + * @brief Receive pointer or @p NULL. + */ + void *rxptr; + /** + * @brief Number of bytes yet to be transmitted. + */ + uint32_t txcnt; + /** + * @brief Transmit pointer or @p NULL. + */ + const void *txptr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC214x_SPI_USE_SSP && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/LPC214x/vic.c b/Project/os/hal/platforms/LPC214x/vic.c new file mode 100644 index 0000000..9f87259 --- /dev/null +++ b/Project/os/hal/platforms/LPC214x/vic.c @@ -0,0 +1,76 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC214x/vic.c + * @brief LPC214x VIC peripheral support code. + * + * @addtogroup LPC214x_VIC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/** + * @brief VIC Initialization. + * @note Better reset everything in the VIC, it is a HUGE source of trouble. + * + * @notapi + */ +void vic_init(void) { + int i; + + VIC *vic = VICBase; + vic->VIC_IntSelect = 0; /* All sources assigned to IRQ. */ + vic->VIC_SoftIntClear = ALLINTMASK; /* No interrupts enforced */ + vic->VIC_IntEnClear = ALLINTMASK; /* All sources disabled. */ + for (i = 0; i < 16; i++) { + vic->VIC_VectCntls[i] = 0; + vic->VIC_VectAddrs[i] = 0; + vic->VIC_VectAddr = 0; + } +} + +/** + * @brief Initializes a VIC vector. + * @details Set a vector for an interrupt source and enables it. + * + * @param[in] handler the pointer to the IRQ service routine + * @param[in] vector the vector number + * @param[in] source the IRQ source to be associated to the vector + * + * @api + */ +void SetVICVector(void *handler, int vector, int source) { + + VIC *vicp = VICBase; + vicp->VIC_VectAddrs[vector] = (IOREG32)handler; + vicp->VIC_VectCntls[vector] = (IOREG32)(source | 0x20); +} + +/** @} */ diff --git a/Project/os/hal/platforms/LPC214x/vic.h b/Project/os/hal/platforms/LPC214x/vic.h new file mode 100644 index 0000000..429646f --- /dev/null +++ b/Project/os/hal/platforms/LPC214x/vic.h @@ -0,0 +1,50 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file LPC214x/vic.h + * @brief LPC214x VIC peripheral support header. + * + * @addtogroup LPC214x_VIC + * @{ + */ + +#ifndef _VIC_H_ +#define _VIC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + void vic_init(void); + void SetVICVector(void *handler, int vector, int source); +#ifdef __cplusplus +} +#endif + +#endif /* _VIC_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/MSP430/hal_lld.c b/Project/os/hal/platforms/MSP430/hal_lld.c new file mode 100644 index 0000000..41d4bc2 --- /dev/null +++ b/Project/os/hal/platforms/MSP430/hal_lld.c @@ -0,0 +1,83 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file MSP430/hal_lld.c + * @brief MSP430 HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* RTC initially stopped.*/ + WDTCTL = 0x5A80; + + /* Clock sources setup.*/ + DCOCTL = VAL_DCOCTL; + BCSCTL1 = VAL_BCSCTL1; +#if MSP430_USE_CLOCK == MSP430_CLOCK_SOURCE_XT2CLK + do { + int i; + IFG1 &= ~OFIFG; + for (i = 255; i > 0; i--) + asm("nop"); + } while (IFG1 & OFIFG); +#endif + BCSCTL2 = VAL_BCSCTL2; +} + +/** @} */ diff --git a/Project/os/hal/platforms/MSP430/hal_lld.h b/Project/os/hal/platforms/MSP430/hal_lld.h new file mode 100644 index 0000000..4242fd2 --- /dev/null +++ b/Project/os/hal/platforms/MSP430/hal_lld.h @@ -0,0 +1,126 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file MSP430/hal_lld.h + * @brief MSP430 HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "msp430.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "MSP430" + +#define MSP430_CLOCK_SOURCE_XT2CLK 0 /**< @brief XT2CLK clock selector. */ +#define MSP430_CLOCK_SOURCE_DCOCLK 1 /**< @brief DCOCLK clock selector. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Clock source. + * @details The clock source can be selected from: + * - @p MSP430_CLOCK_SOURCE_XT2CLK. + * - @p MSP430_CLOCK_SOURCE_DCOCLK. + * . + */ +#if !defined(MSP430_USE_CLOCK) || defined(__DOXYGEN__) +#define MSP430_USE_CLOCK MSP430_CLOCK_SOURCE_XT2CLK +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Calculating the derived clock constants. + */ +#define ACLK LFXT1CLK +#if MSP430_USE_CLOCK == MSP430_CLOCK_SOURCE_XT2CLK +#define MCLK XT2CLK +#define SMCLK (XT2CLK / 8) +#elif MSP430_USE_CLOCK == MSP430_CLOCK_SOURCE_DCOCLK +#define MCLK DCOCLK +#define SMCLK DCOCLK +#else +#error "unknown clock source specified" +#endif + +/* + * Calculating the initialization values. + */ +#define VAL_DCOCTL (DCO0 | DCO1) +#if MSP430_USE_CLOCK == MSP430_CLOCK_SOURCE_XT2CLK +#define VAL_BCSCTL1 (RSEL2) +#define VAL_BCSCTL2 (SELM_2 | DIVM_0 | DIVS_3 | SELS) +#endif +#if MSP430_USE_CLOCK == MSP430_CLOCK_SOURCE_DCOCLK +#define VAL_BCSCTL1 (XT2OFF | RSEL2) +#define VAL_BCSCTL2 (SELM_0 | DIVM_0 | DIVS_0) +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/MSP430/pal_lld.c b/Project/os/hal/platforms/MSP430/pal_lld.c new file mode 100644 index 0000000..48b1c34 --- /dev/null +++ b/Project/os/hal/platforms/MSP430/pal_lld.c @@ -0,0 +1,148 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file MSP430/pal_lld.c + * @brief MSP430 Digital I/O low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief MSP430 I/O ports configuration. + * @note The @p PxIFG, @p PxIE and @p PxSEL registers are cleared. @p PxOUT + * and @p PxDIR are configured as specified. + * + * @param[in] config the MSP430 ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + +#if defined(__MSP430_HAS_PORT1__) || defined(__MSP430_HAS_PORT1_R__) + IOPORT1->iop_full.ie = 0; + IOPORT1->iop_full.ifg = 0; + IOPORT1->iop_full.sel = 0; + IOPORT1->iop_common.out = config->P1Data.out; + IOPORT1->iop_common.dir = config->P1Data.dir; +#endif + +#if defined(__MSP430_HAS_PORT2__) || defined(__MSP430_HAS_PORT2_R__) + IOPORT2->iop_full.ie = 0; + IOPORT2->iop_full.ifg = 0; + IOPORT2->iop_full.sel = 0; + IOPORT2->iop_common.out = config->P2Data.out; + IOPORT2->iop_common.dir = config->P2Data.dir; +#endif + +#if defined(__MSP430_HAS_PORT3__) || defined(__MSP430_HAS_PORT3_R__) + IOPORT3->iop_simple.sel = 0; + IOPORT3->iop_common.out = config->P3Data.out; + IOPORT3->iop_common.dir = config->P3Data.dir; +#endif + +#if defined(__MSP430_HAS_PORT4__) || defined(__MSP430_HAS_PORT4_R__) + IOPORT4->iop_simple.sel = 0; + IOPORT4->iop_common.out = config->P4Data.out; + IOPORT4->iop_common.dir = config->P4Data.dir; +#endif + +#if defined(__MSP430_HAS_PORT5__) || defined(__MSP430_HAS_PORT5_R__) + IOPORT5->iop_simple.sel = 0; + IOPORT5->iop_common.out = config->P5Data.out; + IOPORT5->iop_common.dir = config->P5Data.dir; +#endif + +#if defined(__MSP430_HAS_PORT6__) || defined(__MSP430_HAS_PORT6_R__) + IOPORT6->iop_simple.sel = 0; + IOPORT6->iop_common.out = config->P6Data.out; + IOPORT6->iop_common.dir = config->P6Data.dir; +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as output as recommended by + * the MSP430x1xx Family User's Guide. Unconnected pads are set to + * high logic state by default. + * @note This function does not alter the @p PxSEL registers. Alternate + * functions setup must be handled by device-specific code. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + port->iop_common.dir &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + port->iop_common.out |= mask; + case PAL_MODE_OUTPUT_PUSHPULL: + port->iop_common.dir |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/MSP430/pal_lld.h b/Project/os/hal/platforms/MSP430/pal_lld.h new file mode 100644 index 0000000..c047143 --- /dev/null +++ b/Project/os/hal/platforms/MSP430/pal_lld.h @@ -0,0 +1,334 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file MSP430/pal_lld.h + * @brief MSP430 Digital I/O low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief Simple MSP430 I/O port. + */ +struct msp430_port_simple_t { + volatile uint8_t in; + volatile uint8_t out; + volatile uint8_t dir; + volatile uint8_t sel; +}; + +/** + * @brief Full MSP430 I/O port. + */ +struct msp430_port_full_t { + volatile uint8_t in; + volatile uint8_t out; + volatile uint8_t dir; + volatile uint8_t ifg; + volatile uint8_t ies; + volatile uint8_t ie; + volatile uint8_t sel; +#if defined(__MSP430_HAS_PORT1_R__) || defined(__MSP430_HAS_PORT2_R__) + volatile uint8_t ren; +#endif +}; + +/** + * @brief Simplified MSP430 I/O port representation. + * @details This structure represents the common part of all the MSP430 I/O + * ports. + */ +struct msp430_port_common { + volatile uint8_t in; + volatile uint8_t out; + volatile uint8_t dir; +}; + +/** + * @brief Generic MSP430 I/O port. + */ +typedef union { + struct msp430_port_common iop_common; + struct msp430_port_simple_t iop_simple; + struct msp430_port_full_t iop_full; +} msp430_ioport_t; + +/** + * @brief Setup registers common to all the MSP430 ports. + */ +typedef struct { + volatile uint8_t out; + volatile uint8_t dir; +} msp430_dio_setup_t; + +/** + * @brief MSP430 I/O ports static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialize the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { +#if defined(__MSP430_HAS_PORT1__) || \ + defined(__MSP430_HAS_PORT1_R__) || \ + defined(__DOXYGEN__) + /** @brief Port 1 setup data.*/ + msp430_dio_setup_t P1Data; +#endif +#if defined(__MSP430_HAS_PORT2__) || \ + defined(__MSP430_HAS_PORT2_R__) || \ + defined(__DOXYGEN__) + /** @brief Port 2 setup data.*/ + msp430_dio_setup_t P2Data; +#endif +#if defined(__MSP430_HAS_PORT3__) || \ + defined(__MSP430_HAS_PORT3_R__) || \ + defined(__DOXYGEN__) + /** @brief Port 3 setup data.*/ + msp430_dio_setup_t P3Data; +#endif +#if defined(__MSP430_HAS_PORT4__) || \ + defined(__MSP430_HAS_PORT4_R__) || \ + defined(__DOXYGEN__) + /** @brief Port 4 setup data.*/ + msp430_dio_setup_t P4Data; +#endif +#if defined(__MSP430_HAS_PORT5__) || \ + defined(__MSP430_HAS_PORT5_R__) || \ + defined(__DOXYGEN__) + /** @brief Port 5 setup data.*/ + msp430_dio_setup_t P5Data; +#endif +#if defined(__MSP430_HAS_PORT6__) || \ + defined(__MSP430_HAS_PORT6_R__) || \ + defined(__DOXYGEN__) + /** @brief Port 6 setup data.*/ + msp430_dio_setup_t P6Data; +#endif +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 8 + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint8_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint16_t iomode_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef msp430_ioport_t *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief I/O port A identifier. + * @details This port identifier is mapped on the MSP430 port 1 (P1). + */ +#if defined(__MSP430_HAS_PORT1__) || \ + defined(__MSP430_HAS_PORT1_R__) || \ + defined(__DOXYGEN__) +#define IOPORT1 ((ioportid_t)P1IN_) +#endif + +/** + * @brief I/O port B identifier. + * @details This port identifier is mapped on the MSP430 port 2 (P2). + */ +#if defined(__MSP430_HAS_PORT2__) || \ + defined(__MSP430_HAS_PORT2_R__) || \ + defined(__DOXYGEN__) +#define IOPORT2 ((ioportid_t)P2IN_) +#endif + +/** + * @brief I/O port C identifier. + * @details This port identifier is mapped on the MSP430 port 3 (P3). + */ +#if defined(__MSP430_HAS_PORT3__) || \ + defined(__MSP430_HAS_PORT3_R__) || \ + defined(__DOXYGEN__) +#define IOPORT3 ((ioportid_t)P3IN_) +#endif + +/** + * @brief I/O port D identifier. + * @details This port identifier is mapped on the MSP430 port 4 (P4). + */ +#if defined(__MSP430_HAS_PORT4__) || \ + defined(__MSP430_HAS_PORT4_R__) || \ + defined(__DOXYGEN__) +#define IOPORT4 ((ioportid_t)P4IN_) +#endif + +/** + * @brief I/O port E identifier. + * @details This port identifier is mapped on the MSP430 port 5 (P5). + */ +#if defined(__MSP430_HAS_PORT5__) || \ + defined(__MSP430_HAS_PORT5_R__) || \ + defined(__DOXYGEN__) +#define IOPORT5 ((ioportid_t)P5IN_) +#endif + +/** + * @brief I/O port F identifier. + * @details This port identifier is mapped on the MSP430 port 6 (P6). + */ +#if defined(__MSP430_HAS_PORT6__) || \ + defined(__MSP430_HAS_PORT6_R__) || \ + defined(__DOXYGEN__) +#define IOPORT6 ((ioportid_t)P6IN_) +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * @details In MSP430 programs all the ports as input. + * + * @param[in] config the MSP430 ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * @details This function is implemented by reading the PxIN register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->iop_common.in) + +/** + * @brief Reads the output latch. + * @details This function is implemented by reading the PxOUT register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->iop_common.out) + +/** + * @brief Writes a bits mask on a I/O port. + * @details This function is implemented by writing the PxOUT register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->iop_common.out = (bits)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as output as recommended by + * the MSP430x1xx Family User's Guide. + * @note This function does not alter the @p PxSEL registers. Alternate + * functions setup must be handled by device-specific code. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +extern const PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* _PAL_LLD_H_ */ + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/MSP430/platform.dox b/Project/os/hal/platforms/MSP430/platform.dox new file mode 100644 index 0000000..c64f9f4 --- /dev/null +++ b/Project/os/hal/platforms/MSP430/platform.dox @@ -0,0 +1,104 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup MSP430_DRIVERS MSP430 Drivers + * @details This section describes all the supported drivers on the MSP430 + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup MSP430_HAL MSP430 Initialization Support + * @details The MSP430 HAL support is responsible for system initialization. + * + * @section msp430_hal_1 Supported HW resources + * - DCOCTL. + * - BCSCTL1. + * - BCSCTL2. + * . + * @section msp430_hal_2 MSP430 HAL driver implementation features + * - Clock source selection. + * . + * @ingroup MSP430_DRIVERS + */ + +/** + * @defgroup MSP430_PAL MSP430 PAL Support + * @details The MSP430 PAL driver uses the PORT peripherals. + * + * @section msp430_pal_1 Supported HW resources + * - PORT1 (where present). + * - PORT2 (where present). + * - PORT3 (where present). + * - PORT4 (where present). + * - PORT5 (where present). + * - PORT6 (where present). + * . + * @section msp430_pal_2 MSP430 PAL driver implementation features + * The PAL driver implementation fully supports the following hardware + * capabilities: + * - 8 bits wide ports. + * - Atomic set/reset/toggle functions because special MSP430 instruction set. + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section msp430_pal_3 Supported PAL setup modes + * The MSP430 PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section msp430_pal_4 Suboptimal behavior + * The MSP430 PORT is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Bus/group writes is not atomic. + * - Pad/group mode setup is not atomic. + * . + * @ingroup MSP430_DRIVERS + */ + +/** + * @defgroup MSP430_SERIAL MSP430 Serial Support + * @details The MSP430 Serial driver uses the USART peripherals in a + * buffered, interrupt driven, implementation. + * + * @section msp430_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - USART0. + * - USART1. + * . + * @section msp430_serial_2 MSP430 Serial driver implementation features + * - Each USART can be independently enabled and programmed. + * - Fully interrupt driven. + * . + * @ingroup MSP430_DRIVERS + */ diff --git a/Project/os/hal/platforms/MSP430/platform.mk b/Project/os/hal/platforms/MSP430/platform.mk new file mode 100644 index 0000000..d0175c1 --- /dev/null +++ b/Project/os/hal/platforms/MSP430/platform.mk @@ -0,0 +1,7 @@ +# List of all the MSP430 platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/MSP430/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/MSP430/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/MSP430/serial_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/MSP430 diff --git a/Project/os/hal/platforms/MSP430/serial_lld.c b/Project/os/hal/platforms/MSP430/serial_lld.c new file mode 100644 index 0000000..6b1057c --- /dev/null +++ b/Project/os/hal/platforms/MSP430/serial_lld.c @@ -0,0 +1,339 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file MSP430/serial_lld.c + * @brief MSP430 low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if USE_MSP430_USART0 || defined(__DOXYGEN__) +/** @brief USART0 serial driver identifier.*/ +SerialDriver SD1; +#endif +#if USE_MSP430_USART1 || defined(__DOXYGEN__) +/** @brief USART1 serial driver identifier.*/ +SerialDriver SD2; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = { + UBR(SERIAL_DEFAULT_BITRATE), + 0, + CHAR +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void set_error(SerialDriver *sdp, uint8_t urctl) { + ioflags_t sts = 0; + + if (urctl & OE) + sts |= SD_OVERRUN_ERROR; + if (urctl & PE) + sts |= SD_PARITY_ERROR; + if (urctl & FE) + sts |= SD_FRAMING_ERROR; + if (urctl & BRK) + sts |= SD_BREAK_DETECTED; + chSysLockFromIsr(); + chIOAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +#if USE_MSP430_USART0 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + if (!(U0IE & UTXIE0)) { + msg_t b = sdRequestDataI(&SD1); + if (b != Q_EMPTY) { + U0IE |= UTXIE0; + U0TXBUF = (uint8_t)b; + } + } +} + +/** + * @brief USART0 initialization. + * + * @param[in] config the architecture-dependent serial driver configuration + */ +static void usart0_init(const SerialConfig *config) { + + U0CTL = SWRST; /* Resets the USART. */ + /* USART init */ + U0TCTL = SSEL0 | SSEL1; /* SMCLK as clock source. */ + U0MCTL = config->sc_mod; /* Modulator. */ + U0BR1 = (uint8_t)(config->sc_div >> 8); /* Divider high. */ + U0BR0 = (uint8_t)(config->sc_div >> 0); /* Divider low. */ + /* Clear USART status.*/ + (void)U0RXBUF; + U0RCTL = 0; + /* USART enable.*/ + U0ME |= UTXE0 + URXE0; /* Enables the USART. */ + U0CTL = config->sc_ctl & ~SWRST; /* Various settings. */ + U0IE |= URXIE0; /* Enables RX interrupt. */ +} + +/** + * @brief USART0 de-initialization. + */ +static void usart0_deinit(void) { + + U0IE &= ~URXIE0; + U0CTL = SWRST; +} +#endif /* USE_MSP430_USART0 */ + +#if USE_MSP430_USART1 || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + if (!(U1IE & UTXIE1)) { + msg_t b = sdRequestDataI(&SD2); + if (b != Q_EMPTY) { + U1IE |= UTXIE1; + U1TXBUF = (uint8_t)b; + } + } +} + +/** + * @brief USART1 initialization. + * + * @param[in] config the architecture-dependent serial driver configuration + */ +static void usart1_init(const SerialConfig *config) { + + U1CTL = SWRST; /* Resets the USART. */ + /* USART init.*/ + U1TCTL = SSEL0 | SSEL1; /* SMCLK as clock source. */ + U1MCTL = config->sc_mod; /* Modulator. */ + U1BR1 = (uint8_t)(config->sc_div >> 8); /* Divider high. */ + U1BR0 = (uint8_t)(config->sc_div >> 0); /* Divider low. */ + /* Clear USART status.*/ + (void)U0RXBUF; + U1RCTL = 0; + /* USART enable.*/ + U1ME |= UTXE0 + URXE0; /* Enables the USART. */ + U1CTL = config->sc_ctl & ~SWRST; /* Various settings. */ + U1IE |= URXIE0; /* Enables RX interrupt. */ +} + +/** + * @brief USART1 de-initialization. + */ +static void usart1_deinit(void) { + + U1IE &= ~URXIE0; + U1CTL = SWRST; +} +#endif /* USE_MSP430_USART1 */ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if USE_MSP430_USART0 || defined(__DOXYGEN__) +/** + * @brief USART0 TX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART0TX) { + msg_t b; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + b = sdRequestDataI(&SD1); + chSysUnlockFromIsr(); + if (b < Q_OK) + U0IE &= ~UTXIE0; + else + U0TXBUF = b; + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief USART0 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART0RX) { + uint8_t urctl; + + CH_IRQ_PROLOGUE(); + + if ((urctl = U0RCTL) & RXERR) + set_error(&SD1, urctl); + chSysLockFromIsr(); + sdIncomingDataI(&SD1, U0RXBUF); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} +#endif /* USE_MSP430_USART0 */ + +#if USE_MSP430_USART1 || defined(__DOXYGEN__) +/** + * @brief USART1 TX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART1TX_VECTOR) { + msg_t b; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + b = sdRequestDataI(&SD2); + chSysUnlockFromIsr(); + if (b < Q_OK) + U1IE &= ~UTXIE1; + else + U1TXBUF = b; + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief USART1 RX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART1RX_VECTOR) { + uint8_t urctl; + + CH_IRQ_PROLOGUE(); + + if ((urctl = U1RCTL) & RXERR) + set_error(&SD2, urctl); + chSysLockFromIsr(); + sdIncomingDataI(&SD2, U1RXBUF); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} +#endif /* USE_MSP430_USART1 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if USE_MSP430_USART0 + sdObjectInit(&SD1, NULL, notify1); +#endif + +#if USE_MSP430_USART1 + sdObjectInit(&SD2, NULL, notify2); +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + +#if USE_MSP430_USART0 + if (&SD1 == sdp) { + usart0_init(config); + return; + } +#endif +#if USE_MSP430_USART1 + if (&SD2 == sdp) { + usart1_init(config); + return; + } +#endif +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + +#if USE_MSP430_USART0 + if (&SD1 == sdp) { + usart0_deinit(); + return; + } +#endif +#if USE_MSP430_USART1 + if (&SD2 == sdp) { + usart1_deinit(); + return; + } +#endif +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/MSP430/serial_lld.h b/Project/os/hal/platforms/MSP430/serial_lld.h new file mode 100644 index 0000000..76e2de8 --- /dev/null +++ b/Project/os/hal/platforms/MSP430/serial_lld.h @@ -0,0 +1,147 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file MSP430/serial_lld.h + * @brief MSP430 low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief USART0 driver enable switch. + * @details If set to @p TRUE the support for USART0 is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_MSP430_USART0) || defined(__DOXYGEN__) +#define USE_MSP430_USART0 TRUE +#endif + +/** + * @brief USART1 driver enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p FALSE. + */ +#if !defined(USE_MSP430_USART1) || defined(__DOXYGEN__) +#define USE_MSP430_USART1 TRUE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief MSP430 Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + */ +typedef struct { + /** + * @brief Initialization value for the UBRx registers. + */ + uint16_t sc_div; + /** + * @brief Initialization value for the MOD register. + */ + uint8_t sc_mod; + /** + * @brief Initialization value for the CTL register. + */ + uint8_t sc_ctl; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Macro for baud rate computation. + * @note Make sure the final baud rate is within tolerance. + */ +#define UBR(b) (SMCLK / (b)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if USE_MSP430_USART0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if USE_MSP430_USART1 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/Posix/console.c b/Project/os/hal/platforms/Posix/console.c new file mode 100644 index 0000000..cac93d9 --- /dev/null +++ b/Project/os/hal/platforms/Posix/console.c @@ -0,0 +1,134 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file console.c + * @brief Simulator console driver code. + * @{ + */ + +#include + +#include "ch.h" +#include "console.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief Console driver 1. + */ +BaseChannel CD1; + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + + +static size_t writes(void *ip, const uint8_t *bp, size_t n) { + size_t ret; + + (void)ip; + ret = fwrite(bp, 1, n, stdout); + fflush(stdout); + return ret; +} + +static size_t reads(void *ip, uint8_t *bp, size_t n) { + + (void)ip; + return fread(bp, 1, n, stdin); +} + +static bool_t putwouldblock(void *ip) { + + (void)ip; + return FALSE; +} + +static bool_t getwouldblock(void *ip) { + + (void)ip; + return TRUE; +} + +static msg_t putt(void *ip, uint8_t b, systime_t time) { + + (void)ip; + (void)time; + fputc(b, stdout); + fflush(stdout); + return RDY_OK; +} + +static msg_t gett(void *ip, systime_t time) { + + (void)ip; + (void)time; + return fgetc(stdin); +} + +static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t time) { + size_t ret; + + (void)ip; + (void)time; + ret = fwrite(bp, 1, n, stdout); + fflush(stdout); + return ret; +} + +static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t time) { + + (void)ip; + (void)time; + return fread(bp, 1, n, stdin); +} + +static const struct BaseChannelVMT vmt = { + writes, reads, putwouldblock, getwouldblock, putt, gett, writet, readt +}; + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +void conInit(void) { + + CD1.vmt = &vmt; +} + +/** @} */ diff --git a/Project/os/hal/platforms/Posix/console.h b/Project/os/hal/platforms/Posix/console.h new file mode 100644 index 0000000..49d2710 --- /dev/null +++ b/Project/os/hal/platforms/Posix/console.h @@ -0,0 +1,73 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file console.h + * @brief Simulator console driver header. + * @{ + */ + +#ifndef _CONSOLE_H_ +#define _CONSOLE_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern BaseChannel CD1; + +#ifdef __cplusplus +extern "C" { +#endif + void conInit(void); +#ifdef __cplusplus +} +#endif + +#endif /* _CONSOLE_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/Posix/hal_lld.c b/Project/os/hal/platforms/Posix/hal_lld.c new file mode 100644 index 0000000..1e4e563 --- /dev/null +++ b/Project/os/hal/platforms/Posix/hal_lld.c @@ -0,0 +1,115 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file Posix/hal_lld.c + * @brief Posix HAL subsystem low level driver code. + * + * @addtogroup POSIX_HAL + * @{ + */ + +#include +#include +#include + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +static struct timeval nextcnt; +static struct timeval tick = {0, 1000000 / CH_FREQUENCY}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + */ +void hal_lld_init(void) { + +#if defined(__APPLE__) + puts("ChibiOS/RT simulator (OS X)\n"); +#else + puts("ChibiOS/RT simulator (Linux)\n"); +#endif + gettimeofday(&nextcnt, NULL); + timeradd(&nextcnt, &tick, &nextcnt); +} + +/** + * @brief Interrupt simulation. + */ +void ChkIntSources(void) { + struct timeval tv; + +#if HAL_USE_SERIAL + if (sd_lld_interrupt_pending()) { + dbg_check_lock(); + if (chSchIsPreemptionRequired()) + chSchDoReschedule(); + dbg_check_unlock(); + return; + } +#endif + + gettimeofday(&tv, NULL); + if (timercmp(&tv, &nextcnt, >=)) { + timeradd(&nextcnt, &tick, &nextcnt); + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); + + dbg_check_lock(); + if (chSchIsPreemptionRequired()) + chSchDoReschedule(); + dbg_check_unlock(); + } +} + +/** @} */ diff --git a/Project/os/hal/platforms/Posix/hal_lld.h b/Project/os/hal/platforms/Posix/hal_lld.h new file mode 100644 index 0000000..5f98b80 --- /dev/null +++ b/Project/os/hal/platforms/Posix/hal_lld.h @@ -0,0 +1,91 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file Posix/hal_lld.h + * @brief Posix simulator HAL subsystem low level driver header. + * + * @addtogroup POSIX_HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include +#include +#include + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "Linux" + +#define SOCKET int +#define INVALID_SOCKET -1 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void ChkIntSources(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/Posix/pal_lld.c b/Project/os/hal/platforms/Posix/pal_lld.c new file mode 100644 index 0000000..87e8d9c --- /dev/null +++ b/Project/os/hal/platforms/Posix/pal_lld.c @@ -0,0 +1,106 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file Posix/pal_lld.c + * @brief Posix low level simulated PAL driver code. + * + * @addtogroup POSIX_PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief VIO1 simulated port. + */ +sim_vio_port_t vio_port_1; + +/** + * @brief VIO2 simulated port. + */ +sim_vio_port_t vio_port_2; + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @note This function is not meant to be invoked directly by the application + * code. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with high + * state. + * @note This function does not alter the @p PINSELx registers. Alternate + * functions setup must be handled by device-specific code. + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + port->dir &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + port->latch |= mask; + case PAL_MODE_OUTPUT_PUSHPULL: + port->dir |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/Posix/pal_lld.h b/Project/os/hal/platforms/Posix/pal_lld.h new file mode 100644 index 0000000..29f1dd6 --- /dev/null +++ b/Project/os/hal/platforms/Posix/pal_lld.h @@ -0,0 +1,217 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file Posix/pal_lld.h + * @brief Posix low level simulated PAL driver header. + * + * @addtogroup POSIX_PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_OUTPUT_OPENDRAIN +#undef PAL_MODE_INPUT_ANALOG + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief VIO port structure. + */ +typedef struct { + /** + * @brief VIO_LATCH register. + * @details This register represents the output latch of the VIO port. + */ + uint32_t latch; + /** + * @brief VIO_PIN register. + * @details This register represents the logical level at the VIO port + * pin level. + */ + uint32_t pin; + /** + * @brief VIO_DIR register. + * @details Direction of the VIO port bits, 0=input, 1=output. + */ + uint32_t dir; +} sim_vio_port_t; + +/** + * @brief Virtual I/O ports static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { + /** + * @brief Virtual port 1 setup data. + */ + sim_vio_port_t VP1Data; + /** + * @brief Virtual port 2 setup data. + */ + sim_vio_port_t VP2Data; +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 32 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + */ +typedef sim_vio_port_t *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief VIO port 1 identifier. + */ +#define IOPORT1 (&vio_port_1) + +/** + * @brief VIO port 2 identifier. + */ +#define IOPORT2 (&vio_port_2) + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) \ + (vio_port_1 = (config)->VP1Data, \ + vio_port_2 = (config)->VP2Data) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->pin) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->latch) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->latch = (bits)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +#if !defined(__DOXYGEN__) +extern sim_vio_port_t vio_port_1; +extern sim_vio_port_t vio_port_2; +extern const PALConfig pal_default_config; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/Posix/platform.mk b/Project/os/hal/platforms/Posix/platform.mk new file mode 100644 index 0000000..e2e3da8 --- /dev/null +++ b/Project/os/hal/platforms/Posix/platform.mk @@ -0,0 +1,7 @@ +# List of all the Posix platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/Posix/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/Posix/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/Posix/serial_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/Posix diff --git a/Project/os/hal/platforms/Posix/serial_lld.c b/Project/os/hal/platforms/Posix/serial_lld.c new file mode 100644 index 0000000..c5babd5 --- /dev/null +++ b/Project/os/hal/platforms/Posix/serial_lld.c @@ -0,0 +1,292 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file Posix/serial_lld.c + * @brief Posix low level simulated serial driver code. + * + * @addtogroup POSIX_SERIAL + * @{ + */ + +#include +#include +#include +#include +#include +#include + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief Serial driver 1 identifier.*/ +#if USE_SIM_SERIAL1 || defined(__DOXYGEN__) +SerialDriver SD1; +#endif +/** @brief Serial driver 2 identifier.*/ +#if USE_SIM_SERIAL2 || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = { +}; + +static u_long nb = 1; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void init(SerialDriver *sdp, uint16_t port) { + struct sockaddr_in sad; + struct protoent *prtp; + + if ((prtp = getprotobyname("tcp")) == NULL) { + printf("%s: Error mapping protocol name to protocol number\n", sdp->com_name); + goto abort; + } + + sdp->com_listen = socket(PF_INET, SOCK_STREAM, prtp->p_proto); + if (sdp->com_listen == INVALID_SOCKET) { + printf("%s: Error creating simulator socket\n", sdp->com_name); + goto abort; + } + + if (ioctl(sdp->com_listen, FIONBIO, &nb) != 0) { + printf("%s: Unable to setup non blocking mode on socket\n", sdp->com_name); + goto abort; + } + + memset(&sad, 0, sizeof(sad)); + sad.sin_family = AF_INET; + sad.sin_addr.s_addr = INADDR_ANY; + sad.sin_port = htons(port); + if (bind(sdp->com_listen, (struct sockaddr *)&sad, sizeof(sad))) { + printf("%s: Error binding socket\n", sdp->com_name); + goto abort; + } + + if (listen(sdp->com_listen, 1) != 0) { + printf("%s: Error listening socket\n", sdp->com_name); + goto abort; + } + printf("Full Duplex Channel %s listening on port %d\n", sdp->com_name, port); + return; + +abort: + if (sdp->com_listen != INVALID_SOCKET) + close(sdp->com_listen); + exit(1); +} + +static bool_t connint(SerialDriver *sdp) { + + if (sdp->com_data == INVALID_SOCKET) { + struct sockaddr addr; + socklen_t addrlen = sizeof(addr); + + if ((sdp->com_data = accept(sdp->com_listen, &addr, &addrlen)) == INVALID_SOCKET) + return FALSE; + + if (ioctl(sdp->com_data, FIONBIO, &nb) != 0) { + printf("%s: Unable to setup non blocking mode on data socket\n", sdp->com_name); + goto abort; + } + chSysLockFromIsr(); + chIOAddFlagsI(sdp, IO_CONNECTED); + chSysUnlockFromIsr(); + return TRUE; + } + return FALSE; +abort: + if (sdp->com_listen != INVALID_SOCKET) + close(sdp->com_listen); + if (sdp->com_data != INVALID_SOCKET) + close(sdp->com_data); + exit(1); +} + +static bool_t inint(SerialDriver *sdp) { + + if (sdp->com_data != INVALID_SOCKET) { + int i; + uint8_t data[32]; + + /* + * Input. + */ + int n = recv(sdp->com_data, data, sizeof(data), 0); + switch (n) { + case 0: + close(sdp->com_data); + sdp->com_data = INVALID_SOCKET; + chSysLockFromIsr(); + chIOAddFlagsI(sdp, IO_DISCONNECTED); + chSysUnlockFromIsr(); + return FALSE; + case INVALID_SOCKET: + if (errno == EWOULDBLOCK) + return FALSE; + close(sdp->com_data); + sdp->com_data = INVALID_SOCKET; + return FALSE; + } + for (i = 0; i < n; i++) { + chSysLockFromIsr(); + sdIncomingDataI(sdp, data[i]); + chSysUnlockFromIsr(); + } + return TRUE; + } + return FALSE; +} + +static bool_t outint(SerialDriver *sdp) { + + if (sdp->com_data != INVALID_SOCKET) { + int n; + uint8_t data[1]; + + /* + * Input. + */ + chSysLockFromIsr(); + n = sdRequestDataI(sdp); + chSysUnlockFromIsr(); + if (n < 0) + return FALSE; + data[0] = (uint8_t)n; + n = send(sdp->com_data, data, sizeof(data), 0); + switch (n) { + case 0: + close(sdp->com_data); + sdp->com_data = INVALID_SOCKET; + chSysLockFromIsr(); + chIOAddFlagsI(sdp, IO_DISCONNECTED); + chSysUnlockFromIsr(); + return FALSE; + case INVALID_SOCKET: + if (errno == EWOULDBLOCK) + return FALSE; + close(sdp->com_data); + sdp->com_data = INVALID_SOCKET; + return FALSE; + } + return TRUE; + } + return FALSE; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + */ +void sd_lld_init(void) { + +#if USE_SIM_SERIAL1 + sdObjectInit(&SD1, NULL, NULL); + SD1.com_listen = INVALID_SOCKET; + SD1.com_data = INVALID_SOCKET; + SD1.com_name = "SD1"; +#endif + +#if USE_SIM_SERIAL2 + sdObjectInit(&SD2, NULL, NULL); + SD2.com_listen = INVALID_SOCKET; + SD2.com_data = INVALID_SOCKET; + SD2.com_name = "SD2"; +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + +#if USE_SIM_SERIAL1 + if (sdp == &SD1) + init(&SD1, SIM_SD1_PORT); +#endif + +#if USE_SIM_SERIAL2 + if (sdp == &SD2) + init(&SD2, SIM_SD2_PORT); +#endif +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + */ +void sd_lld_stop(SerialDriver *sdp) { + + (void)sdp; +} + +bool_t sd_lld_interrupt_pending(void) { + bool_t b; + + CH_IRQ_PROLOGUE(); + + b = connint(&SD1) || connint(&SD2) || + inint(&SD1) || inint(&SD2) || + outint(&SD1) || outint(&SD2); + + CH_IRQ_EPILOGUE(); + + return b; +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/Posix/serial_lld.h b/Project/os/hal/platforms/Posix/serial_lld.h new file mode 100644 index 0000000..ed5f888 --- /dev/null +++ b/Project/os/hal/platforms/Posix/serial_lld.h @@ -0,0 +1,162 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file Posix/serial_lld.h + * @brief Posix low level simulated serial driver header. + * + * @addtogroup POSIX_SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 1024 +#endif + +/** + * @brief SD1 driver enable switch. + * @details If set to @p TRUE the support for SD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_SIM_SERIAL1) || defined(__DOXYGEN__) +#define USE_SIM_SERIAL1 TRUE +#endif + +/** + * @brief SD2 driver enable switch. + * @details If set to @p TRUE the support for SD2 is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_SIM_SERIAL2) || defined(__DOXYGEN__) +#define USE_SIM_SERIAL2 TRUE +#endif + +/** + * @brief Listen port for SD1. + */ +#if !defined(SD1_PORT) || defined(__DOXYGEN__) +#define SIM_SD1_PORT 29001 +#endif + +/** + * @brief Listen port for SD2. + */ +#if !defined(SD2_PORT) || defined(__DOXYGEN__) +#define SIM_SD2_PORT 29002 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Generic Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct { +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Listen socket for simulated serial port.*/ \ + SOCKET com_listen; \ + /* Data socket for simulated serial port.*/ \ + SOCKET com_data; \ + /* Port readable name.*/ \ + const char *com_name; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if USE_SIM_SERIAL1 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if USE_SIM_SERIAL2 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); + bool_t sd_lld_interrupt_pending(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/SPC56x/hal_lld.c b/Project/os/hal/platforms/SPC56x/hal_lld.c new file mode 100644 index 0000000..0aae266 --- /dev/null +++ b/Project/os/hal/platforms/SPC56x/hal_lld.c @@ -0,0 +1,138 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file SPC56x/hal_lld.c + * @brief SPC563 HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + extern void _vectors(void); + uint32_t n; + + /* Enables the branch prediction, clears and enables the BTB into the + BUCSR special register (1013).*/ + asm volatile ("li %%r3, 0x0201 \t\n" + "mtspr 1013, %%r3": : : "r3"); + + /* FLASH wait states and prefetching setup.*/ + CFLASH0.BIUCR.R = SPC563_FLASH_BIUCR | SPC563_FLASH_WS; + CFLASH0.BIUCR2.R = 0; + CFLASH0.PFCR3.R = 0; + + /* Optimal crossbar settings. The DMA priority is placed above the CPU + priority in order to not starve I/O activities while the CPU is + executing tight loops (FLASH and SRAM slave ports only). + The SRAM is parked on the load/store port, for some unknown reason it + is defaulted on the instructions port and this kills performance.*/ + XBAR.SGPCR3.B.PARK = 4; /* RAM slave on load/store port.*/ + XBAR.MPR0.R = 0x00030201; /* Flash slave port priorities: + eDMA (1): 0 (highest) + Core Instructions (0): 1 + Undocumented (2): 2 + Core Data (4): 3 */ + XBAR.MPR3.R = 0x00030201; /* SRAM slave port priorities: + eDMA (1): 0 (highest) + Core Instructions (0): 1 + Undocumented (2): 2 + Core Data (4): 3 */ + + /* Downcounter timer initialized for system tick use, TB enabled for debug + and measurements.*/ + n = SPC563_SYSCLK / CH_FREQUENCY; + asm volatile ("li %%r3, 0 \t\n" + "mtspr 284, %%r3 \t\n" /* Clear TBL register. */ + "mtspr 285, %%r3 \t\n" /* Clear TBU register. */ + "mtspr 22, %[n] \t\n" /* Init. DEC register. */ + "mtspr 54, %[n] \t\n" /* Init. DECAR register.*/ + "li %%r3, 0x4000 \t\n" /* TBEN bit. */ + "mtspr 1008, %%r3 \t\n" /* HID0 register. */ + "lis %%r3, 0x0440 \t\n" /* DIE ARE bits. */ + "mtspr 340, %%r3" /* TCR register. */ + : : [n] "r" (n) : "r3"); + + /* INTC initialization, software vector mode, 4 bytes vectors, starting + at priority 0.*/ + INTC.MCR.R = 0; + INTC.CPR.R = 0; + INTC.IACKR.R = (uint32_t)_vectors; +} + +/** + * @brief SPC563 clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h and + * @p hal_lld.h + * @note This function must be invoked only after the system reset. + * + * @special + */ +void spc563_clock_init(void) { + + /* PLL activation.*/ + FMPLL.ESYNCR1.B.EMODE = 1; + FMPLL.ESYNCR1.B.CLKCFG &= 1; /* Bypass mode, PLL off.*/ + FMPLL.ESYNCR1.B.CLKCFG |= 2; /* PLL on. */ + FMPLL.ESYNCR1.B.EPREDIV = SPC563_CLK_PREDIV; + FMPLL.ESYNCR1.B.EMFD = SPC563_CLK_MFD; + FMPLL.ESYNCR2.B.ERFD = SPC563_CLK_RFD; + while (!FMPLL.SYNSR.B.LOCK) + ; + FMPLL.ESYNCR1.B.CLKCFG |= 4; /* Clock from the PLL. */ +} + +/** @} */ diff --git a/Project/os/hal/platforms/SPC56x/hal_lld.h b/Project/os/hal/platforms/SPC56x/hal_lld.h new file mode 100644 index 0000000..ac327dd --- /dev/null +++ b/Project/os/hal/platforms/SPC56x/hal_lld.h @@ -0,0 +1,237 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file SPC56x/hal_lld.h + * @brief SPC563 HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "mpc563m.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "SPC563M64" + +#define RFD_DIV2 0 /**< Divide VCO frequency by 2. */ +#define RFD_DIV4 1 /**< Divide VCO frequency by 4. */ +#define RFD_DIV8 2 /**< Divide VCO frequency by 8. */ +#define RFD_DIV16 3 /**< Divide VCO frequency by 16.*/ + +/* The following settings are related to the FLASH controller, performance + and stability depends on them, be careful.*/ +#define BIUCR_BANK1_TOO 0x01000000 /**< Use settings for bank1 too.*/ +#define BIUCR_MASTER7_PREFETCH 0x00800000 /**< Enable master 7 prefetch. */ +#define BIUCR_MASTER6_PREFETCH 0x00400000 /**< Enable master 6 prefetch. */ +#define BIUCR_MASTER5_PREFETCH 0x00200000 /**< Enable master 5 prefetch. */ +#define BIUCR_MASTER4_PREFETCH 0x00100000 /**< Enable master 4 prefetch. */ +#define BIUCR_MASTER3_PREFETCH 0x00080000 /**< Enable master 3 prefetch. */ +#define BIUCR_MASTER2_PREFETCH 0x00040000 /**< Enable master 2 prefetch. */ +#define BIUCR_MASTER1_PREFETCH 0x00020000 /**< Enable master 1 prefetch. */ +#define BIUCR_MASTER0_PREFETCH 0x00010000 /**< Enable master 0 prefetch. */ +#define BIUCR_APC_MASK 0x0000E000 /**< APC field mask. */ +#define BIUCR_APC_0 (0 << 13) /**< No additional hold cycles. */ +#define BIUCR_APC_1 (1 << 13) /**< 1 additional hold cycle. */ +#define BIUCR_APC_2 (2 << 13) /**< 2 additional hold cycles. */ +#define BIUCR_APC_3 (3 << 13) /**< 3 additional hold cycles. */ +#define BIUCR_APC_4 (4 << 13) /**< 4 additional hold cycles. */ +#define BIUCR_APC_5 (5 << 13) /**< 5 additional hold cycles. */ +#define BIUCR_APC_6 (6 << 13) /**< 6 additional hold cycles. */ +#define BIUCR_WWSC_MASK 0x00001800 /**< WWSC field mask. */ +#define BIUCR_WWSC_0 (0 << 11) /**< No write wait states. */ +#define BIUCR_WWSC_1 (1 << 11) /**< 1 write wait state. */ +#define BIUCR_WWSC_2 (2 << 11) /**< 2 write wait states. */ +#define BIUCR_WWSC_3 (3 << 11) /**< 3 write wait states. */ +#define BIUCR_RWSC_MASK 0x00001800 /**< RWSC field mask. */ +#define BIUCR_RWSC_0 (0 << 8) /**< No read wait states. */ +#define BIUCR_RWSC_1 (1 << 8) /**< 1 read wait state. */ +#define BIUCR_RWSC_2 (2 << 8) /**< 2 read wait states. */ +#define BIUCR_RWSC_3 (3 << 8) /**< 3 read wait states. */ +#define BIUCR_RWSC_4 (4 << 8) /**< 4 read wait states. */ +#define BIUCR_RWSC_5 (5 << 8) /**< 5 read wait states. */ +#define BIUCR_RWSC_6 (6 << 8) /**< 6 read wait states. */ +#define BIUCR_RWSC_7 (7 << 8) /**< 7 read wait states. */ +#define BIUCR_DPFEN 0x00000040 /**< Data prefetch enable. */ +#define BIUCR_IPFEN 0x00000010 /**< Instr. prefetch enable. */ +#define BIUCR_PFLIM_MASK 0x00000060 /**< PFLIM field mask. */ +#define BIUCR_PFLIM_NO (0 << 1) /**< No prefetching. */ +#define BIUCR_PFLIM_ON_MISS (1 << 1) /**< Prefetch on miss. */ +#define BIUCR_PFLIM_ON_HITMISS (2 << 1) /**< Prefetch on hit and miss. */ +#define BIUCR_BFEN 0x00000001 /**< Flash buffering enable. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Clock bypass. + * @note If set to @p TRUE then the PLL is not started and initialized, the + * external clock is used as-is and the other clock-related settings + * are ignored. + */ +#if !defined(SPC563_CLK_BYPASS) || defined(__DOXYGEN__) +#define SPC563_CLK_BYPASS FALSE +#endif + +/** + * @brief Disables the overclock checks. + */ +#if !defined(SPC563_ALLOW_OVERCLOCK) || defined(__DOXYGEN__) +#define SPC563_ALLOW_OVERCLOCK FALSE +#endif + +/** + * @brief External clock pre-divider. + * @note Must be in range 0...14. + * @note The effective divider factor is this value plus one. + */ +#if !defined(SPC563_CLK_PREDIV) || defined(__DOXYGEN__) +#define SPC563_CLK_PREDIV 1 +#endif + +/** + * @brief Multiplication factor divider. + * @note Must be in range 32...96. + */ +#if !defined(SPC563_CLK_MFD) || defined(__DOXYGEN__) +#define SPC563_CLK_MFD 80 +#endif + +/** + * @brief Reduced frequency divider. + */ +#if !defined(SPC563_CLK_RFD) || defined(__DOXYGEN__) +#define SPC563_CLK_RFD RFD_DIV4 +#endif + +/** + * @brief Flash buffer and prefetching settings. + * @note Please refer to the SPC563M64 reference manual about the meaning + * of the following bits, if in doubt DO NOT MODIFY IT. + * @note Do not specify the APC, WWSC, RWSC bits in this value because + * those are calculated from the system clock and ORed with this + * value. + */ +#if !defined(SPC563_FLASH_BIUCR) || defined(__DOXYGEN__) +#define SPC563_FLASH_BIUCR (BIUCR_BANK1_TOO | \ + BIUCR_MASTER4_PREFETCH | \ + BIUCR_MASTER0_PREFETCH | \ + BIUCR_DPFEN | \ + BIUCR_IPFEN | \ + BIUCR_PFLIM_ON_MISS | \ + BIUCR_BFEN) +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (SPC563_CLK_PREDIV < 0) || (SPC563_CLK_PREDIV > 14) +#error "invalid SPC563_CLK_PREDIV value specified" +#endif + +#if (SPC563_CLK_MFD < 32) || (SPC563_CLK_MFD > 96) +#error "invalid SPC563_CLK_MFD value specified" +#endif + +#if (SPC563_CLK_RFD != RFD_DIV2) && (SPC563_CLK_RFD != RFD_DIV4) && \ + (SPC563_CLK_RFD != RFD_DIV8) && (SPC563_CLK_RFD != RFD_DIV16) +#error "invalid SPC563_CLK_RFD value specified" +#endif + +/** + * @brief PLL output clock. + */ +#define SPC563_PLLCLK ((EXTCLK / (SPC563_CLK_PREDIV + 1)) * SPC563_CLK_MFD) + +#if (SPC563_PLLCLK < 256000000) || (SPC563_PLLCLK > 512000000) +#error "VCO frequency out of the acceptable range (256...512)" +#endif + +/** + * @brief PLL output clock. + */ +#if !SPC563_CLK_BYPASS || defined(__DOXYGEN__) +#define SPC563_SYSCLK (SPC563_PLLCLK / (1 << (SPC563_CLK_RFD + 1))) +#else +#define SPC563_SYSCLK EXTCLK +#endif + +#if (SPC563_SYSCLK > 80000000) && !SPC563_ALLOW_OVERCLOCK +#error "System clock above maximum rated frequency (80MHz)" +#endif + +/** + * @brief Flash wait states are a function of the system clock. + */ +#if (SPC563_SYSCLK <= 30000000) || defined(__DOXYGEN__) +#define SPC563_FLASH_WS (BIUCR_APC_0 | BIUCR_RWSC_0 | BIUCR_WWSC_1) +#elif SPC563_SYSCLK <= 60000000 +#define SPC563_FLASH_WS (BIUCR_APC_1 | BIUCR_RWSC_1 | BIUCR_WWSC_1) +#else +#define SPC563_FLASH_WS (BIUCR_APC_2 | BIUCR_RWSC_2 | BIUCR_WWSC_1) +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void spc563_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/SPC56x/mpc563m.h b/Project/os/hal/platforms/SPC56x/mpc563m.h new file mode 100644 index 0000000..8ee2b57 --- /dev/null +++ b/Project/os/hal/platforms/SPC56x/mpc563m.h @@ -0,0 +1,4123 @@ +/**************************************************************************/ + +/* FILE NAME: mpc563xm.h COPYRIGHT (c) Freescale 2008,2009 */ +/* VERSION: 2.0 All Rights Reserved */ +/* */ +/* DESCRIPTION: */ +/* This file contain all of the register and bit field definitions for */ +/* MPC563xM. This version supports revision 1.0 and later. */ +/*========================================================================*/ +/* UPDATE HISTORY */ +/* REV AUTHOR DATE DESCRIPTION OF CHANGE */ +/* --- ----------- --------- --------------------- */ +/* 1.0 G. Emerson 31/OCT/07 Initial version. */ +/* 1.1 G. Emerson 20/DEC/07 Added SYSDIV HLT HLTACK */ +/* Added ESYNCR1 ESYNCR2 SYNFMMR */ +/* 1.2 G. Emerson 31/JAN/08 Change eMIOS channels so there are 24. */ +/* 8 channels in the middle of the range */ +/* do not exist */ +/* 1.3 G. Emerson 30/JUL/08 FLEXCAN - Supports FIFO and Buffer. */ +/* RXIMR added */ +/* FMPLL - Added FMPLL.SYNFMMR.B.BSY */ +/* SIU - Added SIU.ISEL0-3 */ +/* EMIOS - Added EMIOS.CH[x].ALTCADR.R */ +/* MCM - Replaced ECSM with MCM */ +/* removing SWT registers as defined at */ +/* seperate memory location. PFLASH */ +/* registers pre-fixed with P*. Added PCT,*/ +/* PLREV, PLAMC, PLASC, IOPMC, MRSR, MWCR.*/ +/* PBRIDGE - Removed as no PBRIDGE */ +/* registers. */ +/* INTC - Updated number of PSR from */ +/* 358 to 360. */ +/* mpc5500_spr.h - Added RI to MSR and NMI*/ +/* to MSCR. */ +/* 1.4 G. Emerson 30/SEP/08 Add SIU.MIDR2 */ +/* Changes to SIU.MIDR as per RM. */ +/* 1.5 May 2009 Changes to match documentation, removed*/ +/* Not released */ +/* 1.6 K. Odenthal 03/June/09 Update for 1.5M version of the MPC563xM*/ +/* & R. Dees */ +/* INTC - All Processor 0 regs matched to previous */ +/* version */ +/* INTC - BCR renamed to MCR to match previous */ +/* version */ +/* INTC - VTES_PRC1 and HVEN_PRC1 added to MCR */ +/* INTC - CPR_PRC1, IACKR_PRC1 and EOIR_PRC1 */ +/* registers added */ +/* INTC - 512 PSR registers instead of 364 */ +/* ECSM - (Internal - mcm -> ecsm in the source files*/ +/* for generating the header file */ +/* ECSM - All bits and regs got an additional "p" in */ +/* the name in the user manual for "Platform" */ +/* -> deleted to match */ +/* ECSM - SWTCR, SWTSR and SWTIR don't exist in */ +/* MPC563xM -> deleted */ +/* ECSM - PROTECTION in the URM is one bitfield, */ +/* in mop5534 this are four: PROT1-4 -> */ +/* changed to match */ +/* EMCM - removed undocumented registers */ +/* ECSM - RAM ECC Syndrome is new in MPC563xM -> added */ +/* XBAR - removed AMPR and ASGPCR registers */ +/* XBAR - removed HPE bits for nonexistant masters */ +/* EBI - added: D16_31, AD_MUX and SETA bits */ +/* EBI - Added reserved register at address 0x4. */ +/* EBI - Corrected number of chip selects in for both*/ +/* the EBI_CS and the CAL_EBI_CS */ +/* SIU - corrected number of GPDO registers and */ +/* allowed for maximum PCR registers. */ +/* SWT - add KEY bit to CR, correct WND (from WNO) */ +/* SWT - add SK register */ +/* PMC - moved bits from CFGR to Status Register (SR)*/ +/* PMC - Added SR */ +/* DECFIL - Added new bits DSEL, IBIE, OBIE, EDME, */ +/* TORE, & TRFE to MCR. Added IBIC, OBIC, */ +/* DIVRC, IBIF, OBIF, DIVR to MSR. */ +/* changed OUTTEG to OUTTAG in OB */ +/* Change COEF to TAG in TAG register */ +/* EQADC - removed REDLCCR - not supported */ +/* FLASH - Aligned register and bit names with legacy*/ +/* 1.7 K. Odenthal 10/November/09 */ +/* SIU - changed PCR[n].PA from 3 bit to 4 bit */ +/* eTPU - changed WDTR_A.WDM from 1 bit to 2 bits */ +/* DECFIL - changed COEF.R and TAP.R from 16 bit to */ +/* 32 bit */ +/* 2.0 K. Odenthal 12/February/2010 */ +/* TSENS - Temperature Sensor Module added to */ +/* header file */ +/* ANSI C Compliance - Register structures have a */ +/* Bitfield Tag ('B') tag only if there is */ +/* at least one Bitfiels defined. Empty */ +/* tags like 'vuint32_t:32;' are not */ +/* allowed. */ +/* DECFIL - removed MXCR register. This register is */ +/* not supported on this part */ +/* SIU - SWT_SEL bit added in SIU DIRER register */ +/* EDMA - removed HRSL, HRSH and GPOR registers. */ +/* Those registers are not supported in */ +/* that part. */ +/* ESCI - removed LDBG and DSF bits from LCR */ +/* registers. Those bits are not supported */ +/* in that part. */ +/* Those registers are not supported in */ +/* that part. */ +/**************************************************************************/ +/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ + +#ifndef _MPC563M_H_ +#define _MPC563M_H_ + +#include "typedefs.h" + +#ifdef __cplusplus +extern "C" { + +#endif /* + */ + +#ifdef __MWERKS__ +#pragma push +#pragma ANSI_strict off +#endif /* + */ + +/****************************************************************************/ +/* MODULE : FMPLL */ +/****************************************************************************/ + struct FMPLL_tag { + union { + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t PREDIV:3; + vuint32_t MFD:5; + vuint32_t:1; + vuint32_t RFD:3; + vuint32_t LOCEN:1; + vuint32_t LOLRE:1; + vuint32_t LOCRE:1; + vuint32_t:1; /* Reserved in MPC563xM + + Deleted for legacy header version [mpc5534.h]: + + */ + vuint32_t LOLIRQ:1; + vuint32_t LOCIRQ:1; + vuint32_t:13; /* Reserved in MPC563xM + + Deleted for legacy header version [mpc5534.h]: + + + + + + */ + } B; + } SYNCR; + union { + vuint32_t R; + struct { + vuint32_t:22; + vuint32_t LOLF:1; + vuint32_t LOC:1; + vuint32_t MODE:1; + vuint32_t PLLSEL:1; + vuint32_t PLLREF:1; + vuint32_t LOCKS:1; + vuint32_t LOCK:1; + vuint32_t LOCF:1; + vuint32_t:2; /* Reserved in MPC563xM + + Deleted for legacy header version [mpc5534.h]: + + + + */ + } B; + } SYNSR; + union { + vuint32_t R; + struct { + vuint32_t EMODE:1; + vuint32_t CLKCFG:3; + vuint32_t:8; + vuint32_t EPREDIV:4; + vuint32_t:9; + vuint32_t EMFD:7; + } B; + } ESYNCR1; /* Enhanced Synthesizer Control Register 1 (ESYNCR1) (new in MPC563xM) Offset 0x0008 */ + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t LOCEN:1; + vuint32_t LOLRE:1; + vuint32_t LOCRE:1; + vuint32_t LOLIRQ:1; + vuint32_t LOCIRQ:1; + vuint32_t:17; + vuint32_t ERFD:2; + } B; + } ESYNCR2; /* Enhanced Synthesizer Control Register 2 (ESYNCR2) (new in MPC563xM) Offset 0x000C */ + int32_t FMPLL_reserved0[2]; + union { + vuint32_t R; + struct { + vuint32_t BSY:1; + vuint32_t MODEN:1; + vuint32_t MODSEL:1; + vuint32_t MODPERIOD:13; + vuint32_t:1; + vuint32_t INCSTEP:15; + } B; + } SYNFMMR; /* Synthesizer FM Modulation Register (SYNFMMR) (new in MPC563xM) Offset 0x0018 */ + }; +/****************************************************************************/ +/* MODULE : EBI */ +/****************************************************************************/ + struct CS_tag { + union { + vuint32_t R; + struct { + vuint32_t BA:17; /* */ + vuint32_t:3; /* */ + vuint32_t PS:1; /* */ + vuint32_t:3; /* */ + vuint32_t AD_MUX:1; /* new in MPC563xM */ + vuint32_t BL:1; /* */ + vuint32_t WEBS:1; /* */ + vuint32_t TBDIP:1; /* */ + vuint32_t:1; /* */ + vuint32_t SETA:1; /* new in MPC563xM */ + vuint32_t BI:1; /* */ + vuint32_t V:1; /* */ + } B; + } BR; /* EBI_BR */ + union { + vuint32_t R; + struct { + vuint32_t AM:17; /* */ + vuint32_t:7; /* */ + vuint32_t SCY:4; /* */ + vuint32_t:1; /* */ + vuint32_t BSCY:2; /* */ + vuint32_t:1; /* */ + } B; + } OR; /* EBI_OR */ + }; + struct CAL_CS_tag { + union { + vuint32_t R; + struct { + vuint32_t BA:17; /* */ + vuint32_t:3; /* */ + vuint32_t PS:1; /* */ + vuint32_t:3; /* */ + vuint32_t AD_MUX:1; /* new in MPC563xM */ + vuint32_t BL:1; /* */ + vuint32_t WEBS:1; /* */ + vuint32_t TBDIP:1; /* */ + vuint32_t:1; /* */ + vuint32_t SETA:1; /* new in MPC563xM */ + vuint32_t BI:1; /* */ + vuint32_t V:1; /* */ + } B; + } BR; /* EBI_CAL_BR */ + + union { + vuint32_t R; + struct { + vuint32_t AM:17; /* */ + vuint32_t:7; /* */ + vuint32_t SCY:4; /* */ + vuint32_t:1; /* */ + vuint32_t BSCY:2; /* */ + vuint32_t:1; /* */ + } B; + } OR; /* EBI_CAL_OR */ + + }; + + struct EBI_tag { + union { + vuint32_t R; + struct { + vuint32_t:5; /* */ + vuint32_t SIZEEN:1; /* SIZEN */ + vuint32_t SIZE:2; /* */ + vuint32_t:8; /* */ + vuint32_t ACGE:1; /* */ + vuint32_t EXTM:1; /* */ + vuint32_t EARB:1; /* */ + vuint32_t EARP:2; /* */ + vuint32_t:4; /* */ + vuint32_t MDIS:1; /* */ + vuint32_t:3; /* */ + vuint32_t D16_31:1; /* new in MPC563xM */ + vuint32_t AD_MUX:1; /* new in MPC563xM */ + vuint32_t DBM:1; /* */ + } B; + } MCR; /* EBI Module Configuration Register (MCR) EBI_MCR @baseaddress + 0x00 */ + + uint32_t EBI_reserved1[1]; + + union { + vuint32_t R; + struct { + vuint32_t:30; /* */ + vuint32_t TEAF:1; /* */ + vuint32_t BMTF:1; /* */ + } B; + } TESR; /* EBI Transfer Error Status Register (TESR) EBI_TESR @baseaddress + 0x08 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; /* */ + vuint32_t BMT:8; /* */ + vuint32_t BME:1; /* */ + vuint32_t:7; /* */ + } B; + } BMCR; /* EBI_BMCR @baseaddress + 0x0C */ + + struct CS_tag CS[4]; + + uint32_t EBI_reserved2[4]; + + /* Calibration registers */ + struct CAL_CS_tag CAL_CS[4]; + + }; /* end of EBI_tag */ +/****************************************************************************/ +/* MODULE : FLASH */ +/****************************************************************************/ +/* 3 flash modules implemented. */ +/* HBL and HBS not used in Bank 0 / Array 0 */ +/* LML, SLL, LMS, PFCR1, PFAPR, PFCR2, and PFCR3 not used in */ +/* Bank 1 / Array 1 or Bank 1 / Array 3 */ +/****************************************************************************/ + struct FLASH_tag { + union { /* Module Configuration Register (MCR)@baseaddress + 0x00 */ + vuint32_t R; + struct { + vuint32_t EDC:1; /* ECC Data Correction (Read/Clear) */ + vuint32_t:4; /* Reserved */ + vuint32_t SIZE:3; /* Array Size (Read Only) */ + vuint32_t:1; /* Reserved */ + vuint32_t LAS:3; /* Low Address Space (Read Only) */ + vuint32_t:3; /* Reserved */ + vuint32_t MAS:1; /* Mid Address Space (Read Only) */ + vuint32_t EER:1; /* ECC Event Error (Read/Clear) *//* BBEPE and EPE */ + vuint32_t RWE:1; /* Read While Write Event Error (Read/Clear) */ + vuint32_t:2; /* Reserved */ + vuint32_t PEAS:1; /* Program/Erase Access Space (Read Only) */ + vuint32_t DONE:1; /* Status (Read Only) */ + vuint32_t PEG:1; /* Program/Erase Good (Read Only) */ + vuint32_t:4; /* Reserved *//* RSD PEG STOP RSVD */ + vuint32_t PGM:1; /* Program (Read/Write) */ + vuint32_t PSUS:1; /* Program Suspend (Read/Write) */ + vuint32_t ERS:1; /* Erase (Read/Write) */ + vuint32_t ESUS:1; /* Erase Suspend (Read/Write) */ + vuint32_t EHV:1; /* Enable High Voltage (Read/Write) */ + } B; + } MCR; + + union { /* Low/Mid-Address Space Block Locking Register (LML)@baseaddress + 0x04 */ + vuint32_t R; + struct { + vuint32_t LME:1; /* Low/Mid address space block enable (Read Only) */ + vuint32_t:10; /* Reserved */ + vuint32_t SLOCK:1; /*SLK *//* Shadow address space block lock (Read/Write) */ + vuint32_t:2; /* Reserved */ + vuint32_t MLOCK:2; /*MLK *//* Mid address space block lock (Read/Write) */ + vuint32_t:8; /* Reserved */ + vuint32_t LLOCK:8; /*LLK *//* Low address space block lock (Read/Write) */ + } B; + } LMLR; /*LML */ + + union { /* High-Address Space Block Locking Register (HBL) - @baseaddress + 0x08 */ + vuint32_t R; + struct { + vuint32_t HBE:1; /* High address space Block Enable (Read Only) */ + vuint32_t:27; /* Reserved */ + vuint32_t HBLOCK:4; /* High address space block lock (Read/Write) */ + } B; + } HLR; /*HBL */ + + union { /* Secondary Low/Mid-Address Space Block Locking Register (SLL)@baseaddress + 0x0C */ + vuint32_t R; + struct { + vuint32_t SLE:1; /* Secondary low/mid address space block enable (Read Only) */ + vuint32_t:10; /* Reserved */ + vuint32_t SSLOCK:1; /*SSLK *//* Secondary shadow address space block lock (Read/Write) */ + vuint32_t:2; /* Reserved */ + vuint32_t SMLOCK:2; /*SMK *//* Secondary mid address space block lock (Read/Write) */ + vuint32_t:8; /* Reserved */ + vuint32_t SLLOCK:8; /*SLK *//* Secondary low address space block lock (Read/Write) */ + } B; + } SLMLR; /*SLL */ + + union { /* Low/Mid-Address Space Block Select Register (LMS)@baseaddress + 0x10 */ + vuint32_t R; + struct { + vuint32_t:14; /* Reserved */ + vuint32_t MSEL:2; /*MSL *//* Mid address space block select (Read/Write) */ + vuint32_t:8; /* Reserved */ + vuint32_t LSEL:8; /*LSL *//* Low address space block select (Read/Write) */ + } B; + } LMSR; /*LMS */ + + union { /* High-Address Space Block Select Register (HBS) - not used@baseaddress + 0x14 */ + vuint32_t R; + struct { + vuint32_t:28; /* Reserved */ + vuint32_t HBSEL:4; /*HSL *//* High address space block select (Read/Write) */ + } B; + } HSR; /*HBS */ + + union { /* Address Register (ADR)@baseaddress + 0x18 */ + vuint32_t R; + struct { + vuint32_t SAD:1; /* Shadow address (Read Only) */ + vuint32_t:10; /* Reserved */ + vuint32_t ADDR:18; /*AD *//* Address 20-3 (Read Only) */ + vuint32_t:3; /* Reserved */ + } B; + } AR; /*ADR */ + + union { /* @baseaddress + 0x1C */ + vuint32_t R; + struct { + vuint32_t:7; /* Reserved */ + vuint32_t GCE:1; /* Global Configuration Enable (Read/Write) */ + vuint32_t:4; /* Reserved */ + vuint32_t M3PFE:1; /* Master 3 Prefetch Enable (Read/Write) */ + vuint32_t M2PFE:1; /* Master 2 Prefetch Enable (Read/Write) */ + vuint32_t M1PFE:1; /* Master 1 Prefetch Enable (Read/Write) */ + vuint32_t M0PFE:1; /* Master 0 Prefetch Enable (Read/Write) */ + vuint32_t APC:3; /* Address Pipelining Control (Read/Write) */ + vuint32_t WWSC:2; /* Write Wait State Control (Read/Write) */ + vuint32_t RWSC:3; /* Read Wait State Control (Read/Write) */ + vuint32_t:1; /* Reserved */ + vuint32_t DPFEN:1; /*DPFE *//* Data Prefetch Enable (Read/Write) */ + vuint32_t:1; /* Reserved */ + vuint32_t IPFEN:1; /*IPFE *//* Instruction Prefetch Enable (Read/Write) */ + vuint32_t:1; /* Reserved */ + vuint32_t PFLIM:2; /* Prefetch Limit (Read/Write) */ + vuint32_t BFEN:1; /*BFE *//* Buffer Enable (Read/Write) */ + } B; + } BIUCR; /*PFCR1 */ + + union { /* @baseaddress + 0x20 */ + vuint32_t R; + struct { + vuint32_t:24; /* Reserved */ + vuint32_t M3AP:2; /* Master 3 Access Protection (Read/Write) */ + vuint32_t M2AP:2; /* Master 2 Access Protection (Read/Write) */ + vuint32_t M1AP:2; /* Master 1 Access Protection (Read/Write) */ + vuint32_t M0AP:2; /* Master 0 Access Protection (Read/Write) */ + } B; + } BIUAPR; /*PFAPR */ + + union { /* @baseaddress + 0x24 */ + vuint32_t R; + struct { + vuint32_t LBCFG:2; /* Line Buffer Configuration (Read/Write) */ + vuint32_t:30; /* Reserved */ + } B; + } BIUCR2; + + union { /* @baseaddress + 0x28 */ + vuint32_t R; + struct { + vuint32_t:25; /* Reserved */ + vuint32_t B1_DPFE:1; /* Bank1 Data Prefetch Enable (Read/Write) */ + vuint32_t:1; /* Reserved */ + vuint32_t B1_IPFE:1; /* Bank1 Instruction Prefetch Enable (Read/Write) */ + vuint32_t:1; /* Reserved */ + vuint32_t B1_PFLIM:2; /* Bank1 Prefetch Limit (Read/Write) */ + vuint32_t B1_BFE:1; /* Bank1 Buffer Enable (Read/Write) */ + } B; + } PFCR3; + + int32_t FLASH_reserverd_89[4]; + + union { /* User Test 0 (UT0) register@baseaddress + 0x3c */ + vuint32_t R; + struct { + vuint32_t UTE:1; /* User test enable (Read/Clear) */ + vuint32_t SBCE:1; /* Single bit correction enable (Read/Clear) */ + vuint32_t:6; /* Reserved */ + vuint32_t DSI:8; /* Data syndrome input (Read/Write) */ + vuint32_t:9; /* Reserved */ + vuint32_t:1; /* Reserved (Read/Write) */ + vuint32_t MRE:1; /* Margin Read Enable (Read/Write) */ + vuint32_t MRV:1; /* Margin Read Value (Read/Write) */ + vuint32_t EIE:1; /* ECC data Input Enable (Read/Write) */ + vuint32_t AIS:1; /* Array Integrity Sequence (Read/Write) */ + vuint32_t AIE:1; /* Array Integrity Enable (Read/Write) */ + vuint32_t AID:1; /* Array Integrity Done (Read Only) */ + } B; + } UT0; + + union { /* User Test 1 (UT1) register@baseaddress + 0x40 */ + vuint32_t R; + struct { + vuint32_t DAI:32; /* Data Array Input (Read/Write) */ + } B; + } UT1; + + union { /* User Test 2 (UT2) register@baseaddress + 0x44 */ + vuint32_t R; + struct { + vuint32_t DAI:32; /* Data Array Input (Read/Write) */ + } B; + } UT2; + + union { /* User Multiple Input Signature Register 0-5 (UMISR[5])@baseaddress + 0x48 */ + vuint32_t R; + struct { + vuint32_t MS:32; /* Multiple input Signature (Read/Write) */ + } B; + } UMISR[5]; + + }; /* end of FLASH_tag */ +/****************************************************************************/ +/* MODULE : SIU */ +/****************************************************************************/ + struct SIU_tag { + union { + vuint32_t R; + struct { + vuint32_t S_F:1; /* Identifies the Manufacturer S/F */ + vuint32_t FLASH_SIZE_1:4; /* Define major Flash memory size (see Table 15-4 for details) Flash Size 1 */ + vuint32_t FLASH_SIZE_2:4; /* Define Flash memory size, small granularity (see Table 15-5 for details) Flash Size 1 */ + vuint32_t TEMP_RANGE:2; /* Define maximum operating range Temp Range */ + vuint32_t:1; /* Reserved for future enhancements */ + vuint32_t MAX_FREQ:2; /* Define maximum device speed Max Freq */ + vuint32_t:1; /* Reserved for future enhancements */ + vuint32_t SUPPLY:1; /* Defines if the part is 5V or 3V Supply */ + vuint32_t PART_NUMBER:8; /* Contain the ASCII representation of the character that indicates the product Part Number */ + vuint32_t TBD:1; /* 1-bit field defined by SoC to describe optional feature, e.g., additional SPI */ + vuint32_t:2; /* Reserved for future enhancements */ + vuint32_t EE:1; /* Indicates if Data Flash is present */ + vuint32_t:3; /* Reserved for future enhancements */ + vuint32_t FR:1; /* Indicates if Data FlexRay is present */ + } B; + } MIDR2; /* MCU ID Register 2 SIU_MIDR2 @baseaddress + 0x4 */ + + union { + vuint32_t R; + struct { + vuint32_t PARTNUM:16; /* Device part number: 0x5633 */ + vuint32_t CSP:1; /* CSP configuration (new in MPC563xM) */ + vuint32_t PKG:5; /* Indicate the package the die is mounted in. (new in MPC563xM) */ + vuint32_t:2; /* Reserved */ + vuint32_t MASKNUM:8; /* MCU major mask number; updated for each complete resynthesis. MCU minor mask number; updated for each mask revision */ + } B; + } MIDR; /* MCU ID Register (MIDR) SIU_MIDR @baseaddress + 0x8 */ + + union { + vuint32_t R; + } TST; /* SIU Test Register (SIU_TST) SIU_TST @baseaddress + 0xC */ + + union { + vuint32_t R; + struct { + vuint32_t PORS:1; /* Power-On Reset Status */ + vuint32_t ERS:1; /* External Reset Status */ + vuint32_t LLRS:1; /* Loss of Lock Reset Status */ + vuint32_t LCRS:1; /* Loss of Clock Reset Status */ + vuint32_t WDRS:1; /* Watchdog Timer/Debug Reset Status */ + vuint32_t CRS:1; /* Checkstop Reset Status */ + vuint32_t SWTRS:1; /* Software Watchdog Timer Reset Status (new in MPC563xM) */ + vuint32_t:7; /* */ + vuint32_t SSRS:1; /* Software System Reset Status */ + vuint32_t SERF:1; /* Software External Reset Flag */ + vuint32_t WKPCFG:1; /* Weak Pull Configuration Pin Status */ + vuint32_t:11; /* */ + vuint32_t ABR:1; /* Auto Baud Rate (new in MPC563xM) */ + vuint32_t BOOTCFG:2; /* Reset Configuration Pin Status */ + vuint32_t RGF:1; /* RESET Glitch Flag */ + } B; + } RSR; /* Reset Status Register (SIU_RSR) SIU_RSR @baseaddress + 0x10 */ + + union { + vuint32_t R; + struct { + vuint32_t SSR:1; /* Software System Reset */ + vuint32_t SER:1; /* Software External Reset */ + vuint32_t:14; /* */ + vuint32_t CRE:1; /* Checkstop Reset Enable */ + vuint32_t:15; /* */ + } B; + } SRCR; /* System Reset Control Register (SRCR) SIU_SRCR @baseaddress + 0x14 */ + + union { + vuint32_t R; + struct { + vuint32_t NMI:1; /* Non-Maskable Interrupt Flag (new in MPC563xM) */ + vuint32_t:7; /* */ + vuint32_t SWT:1; /* Software Watch Dog Timer Interrupt Flag, from platform (new in MPC563xM) */ + vuint32_t:7; /* */ + vuint32_t EIF15:1; /* External Interrupt Request Flag x */ + vuint32_t EIF14:1; /* External Interrupt Request Flag x */ + vuint32_t EIF13:1; /* External Interrupt Request Flag x */ + vuint32_t EIF12:1; /* External Interrupt Request Flag x */ + vuint32_t EIF11:1; /* External Interrupt Request Flag x */ + vuint32_t EIF10:1; /* External Interrupt Request Flag x */ + vuint32_t EIF9:1; /* External Interrupt Request Flag x */ + vuint32_t EIF8:1; /* External Interrupt Request Flag x */ + vuint32_t:3; /* (reserved in MPC563xM) */ + vuint32_t EIF4:1; /* External Interrupt Request Flag x */ + vuint32_t EIF3:1; /* External Interrupt Request Flag x */ + vuint32_t:2; /* (reserved in MPC563xM) */ + vuint32_t EIF0:1; /* External Interrupt Request Flag x */ + } B; + } EISR; /* SIU External Interrupt Status Register (EISR) SIU_EISR @baseaddress + 0x18 */ + + union { + vuint32_t R; + struct { + vuint32_t NMI_SEL:1; /* NMI Interrupt Platform Input Selection (new in MPC563xM) */ + vuint32_t:7; /* */ + vuint32_t SWT_SEL:1; + vuint32_t:7; + vuint32_t EIRE15:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE14:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE13:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE12:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE11:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE10:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE9:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE8:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE7:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE6:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE5:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE4:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE3:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE2:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE1:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE0:1; /* External DMA/Interrupt Request Enable x */ + } B; + } DIRER; /* DMA/Interrupt Request Enable Register (DIRER) SIU_DIRER @baseaddress + 0x1C */ + + union { + vuint32_t R; + struct { + vuint32_t:28; /* */ + vuint32_t DIRS3:1; /* DMA/Interrupt Request Select x */ + vuint32_t:2; /* reserved in MPC563xM */ + vuint32_t DIRS0:1; /* DMA/Interrupt Request Select x */ + } B; + } DIRSR; /* DMA/Interrupt Request Select Register (DIRSR) SIU_DIRSR @baseaddress + 0x20 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; /* */ + vuint32_t OVF15:1; /* Overrun Flag x */ + vuint32_t OVF14:1; /* Overrun Flag x */ + vuint32_t OVF13:1; /* Overrun Flag x */ + vuint32_t OVF12:1; /* Overrun Flag x */ + vuint32_t OVF11:1; /* Overrun Flag x */ + vuint32_t OVF10:1; /* Overrun Flag x */ + vuint32_t OVF9:1; /* Overrun Flag x */ + vuint32_t OVF8:1; /* Overrun Flag x */ + vuint32_t:3; /* reserved in MPC563xM */ + vuint32_t OVF4:1; /* Overrun Flag x */ + vuint32_t OVF3:1; /* Overrun Flag x */ + vuint32_t:2; /* reserved in MPC563xM */ + vuint32_t OVF0:1; /* Overrun Flag x */ + } B; + } OSR; /* Overrun Status Register (OSR) SIU_OSR @baseaddress + 0x24 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; /* */ + vuint32_t ORE15:1; /* Overrun Request Enable x */ + vuint32_t ORE14:1; /* Overrun Request Enable x */ + vuint32_t ORE13:1; /* Overrun Request Enable x */ + vuint32_t ORE12:1; /* Overrun Request Enable x */ + vuint32_t ORE11:1; /* Overrun Request Enable x */ + vuint32_t ORE10:1; /* Overrun Request Enable x */ + vuint32_t ORE9:1; /* Overrun Request Enable x */ + vuint32_t ORE8:1; /* Overrun Request Enable x */ + vuint32_t:3; /* reserved in MPC563xM */ + vuint32_t ORE4:1; /* Overrun Request Enable x */ + vuint32_t ORE3:1; /* Overrun Request Enable x */ + vuint32_t:2; /* reserved in MPC563xM */ + vuint32_t ORE0:1; /* Overrun Request Enable x */ + } B; + } ORER; /* Overrun Request Enable Register (ORER) SIU_ORER @baseaddress + 0x28 */ + + union { + vuint32_t R; + struct { + vuint32_t NMIRE:1; /* NMI Rising-Edge Event Enable x (new in MPC563xM) */ + vuint32_t:15; /* reserved in MPC563xM */ + vuint32_t IREE15:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE14:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE13:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE12:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE11:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE10:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE9:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE8:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t:3; /* reserved in MPC563xM */ + vuint32_t IREE4:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE3:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t:2; /* reserved in MPC563xM */ + vuint32_t IREE0:1; /* IRQ Rising-Edge Event Enable x */ + } B; + } IREER; /* External IRQ Rising-Edge Event Enable Register (IREER) SIU_IREER @baseaddress + 0x2C */ + + union { + vuint32_t R; + struct { + vuint32_t NMIFE:1; /* NMI Falling-Edge Event Enable x (new in MPC563xM) */ + vuint32_t Reserverd:15; /* */ + vuint32_t IFEE15:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE14:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE13:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE12:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE11:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE10:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE9:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE8:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t:3; /* reserved in MPC563xM */ + vuint32_t IFEE4:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE3:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t:2; /* reserved in MPC563xM */ + vuint32_t IFEE0:1; /* IRQ Falling-Edge Event Enable x */ + } B; + } IFEER; /* External IRQ Falling-Edge Event Enable Regi (IFEER) SIU_IFEER @baseaddress + 0x30 */ + + union { + vuint32_t R; + struct { + vuint32_t:28; /* */ + vuint32_t DFL:4; /* Digital Filter Length */ + } B; + } IDFR; /* External IRQ Digital Filter Register (IDFR) SIU_IDFR @baseaddress + 0x40 */ + + int32_t SIU_reserverd_153[3]; + + union { + vuint16_t R; + struct { + vuint16_t:2; /* */ + vuint16_t PA:4; /* */ + vuint16_t OBE:1; /* */ + vuint16_t IBE:1; /* */ + vuint16_t DSC:2; /* */ + vuint16_t ODE:1; /* */ + vuint16_t HYS:1; /* */ + vuint16_t SRC:2; /* */ + vuint16_t WPE:1; /* */ + vuint16_t WPS:1; /* */ + } B; + } PCR[512]; /* Pad Configuration Register (PCR) SIU_PCR @baseaddress + 0x600 */ + + int32_t SIU_reserverd_164[112]; + + union { + vuint8_t R; + struct { + vuint8_t:7; /* */ + vuint8_t PDO:1; /* */ + } B; + } GPDO[512]; /* GPIO Pin Data Output Register (GPDO) SIU_GDPO @baseaddress + 0x800 */ + + union { + vuint8_t R; + struct { + vuint8_t:7; /* */ + vuint8_t PDI:1; /* */ + } B; + } GPDI[256]; /* GPIO Pin Data Input Register (GDPI) SIU_GDPI @baseaddress + 0x900 */ + + union { + vuint32_t R; + struct { + vuint32_t TSEL5:2; /* eQADC Trigger 5 Input */ + vuint32_t TSEL4:2; /* eQADC Trigger 4 Input */ + vuint32_t TSEL3:2; /* eQADC Trigger 3 Input */ + vuint32_t TSEL2:2; /* eQADC Trigger 4 Input */ + vuint32_t TSEL1:2; /* eQADC Trigger 1 Input */ + vuint32_t TSEL0:2; /* eQADC Trigger 0 Input */ + vuint32_t:20; /* */ + } B; + } ETISR; /* eQADC Trigger Input Select Register (ETISR) SIU_ETISR @baseaddress + 0x904 */ + + union { + vuint32_t R; + struct { + vuint32_t ESEL15:2; /* External IRQ Input Select x */ + vuint32_t ESEL14:2; /* External IRQ Input Select x */ + vuint32_t ESEL13:2; /* External IRQ Input Select x */ + vuint32_t ESEL12:2; /* External IRQ Input Select x */ + vuint32_t ESEL11:2; /* External IRQ Input Select x */ + vuint32_t ESEL10:2; /* External IRQ Input Select x */ + vuint32_t ESEL9:2; /* External IRQ Input Select x */ + vuint32_t ESEL8:2; /* External IRQ Input Select x */ + vuint32_t ESEL7:2; /* External IRQ Input Select x */ + vuint32_t ESEL6:2; /* External IRQ Input Select x */ + vuint32_t ESEL5:2; /* External IRQ Input Select x */ + vuint32_t ESEL4:2; /* External IRQ Input Select x */ + vuint32_t ESEL3:2; /* External IRQ Input Select x */ + vuint32_t ESEL2:2; /* External IRQ Input Select x */ + vuint32_t ESEL1:2; /* External IRQ Input Select x */ + vuint32_t ESEL0:2; /* External IRQ Input Select x */ + } B; + } EIISR; /* External IRQ Input Select Register (EIISR) SIU_EIISR @baseaddress + 0x908 */ + + union { + vuint32_t R; + struct { + vuint32_t:8; /* reserved in MPC563xM */ + vuint32_t SINSELB:2; /* DSPI_B Data Input Select SIN-SELB */ + vuint32_t SSSELB:2; /* DSPI_B Slave Select Input Select SS-SELB */ + vuint32_t SCKSELB:2; /* DSPI_B Clock Input Select SCK-SELB */ + vuint32_t TRIGSELB:2; /* DSPI_B Trigger Input Select TRIG-SELB */ + vuint32_t SINSELC:2; /* DSPI_C Data Input Select SIN-SELC */ + vuint32_t SSSELC:2; /* DSPI_C Slave Select Input Select SSSELC */ + vuint32_t SCKSELC:2; /* DSPI_C Clock Input Select SCK-SELC */ + vuint32_t TRIGSELC:2; /* DSPI_C Trigger Input Select TRIG-SELC */ + vuint32_t:8; /* reserved in MPC563xM */ + } B; + } DISR; /* DSPI Input Select Register (DISR) SIU_DISR @baseaddress + 0x90c */ + + union { + vuint32_t R; + struct { + vuint32_t:2; /* */ + vuint32_t ETSEL5:5; /* eQADC queue X Enhanced Trigger Selection eTSEL5 */ + vuint32_t ETSEL4:5; /* eQADC queue X Enhanced Trigger Selection eTSEL4 */ + vuint32_t ETSEL3:5; /* eQADC queue X Enhanced Trigger Selection eTSEL3 */ + vuint32_t ETSEL2:5; /* eQADC queue X Enhanced Trigger Selection eTSEL2 */ + vuint32_t ETSEL1:5; /* eQADC queue X Enhanced Trigger Selection eTSEL1 */ + vuint32_t ETSEL0:5; /* eQADC queue X Enhanced Trigger Selection eTSEL0 */ + } B; + } ISEL3; /* MUX Select Register 3 (ISEL3) (new in MPC563xM) SIU_ISEL3 @baseaddress + 0x920 */ + + int32_t SIU_reserverd_214[4]; + + union { + vuint32_t R; + struct { + vuint32_t:11; /* */ + vuint32_t ESEL5:1; /* eSEL5 */ + vuint32_t:3; /* */ + vuint32_t ESEL4:1; /* eSEL4 */ + vuint32_t:3; /* */ + vuint32_t ESEL3:1; /* eSEL3 */ + vuint32_t:3; /* */ + vuint32_t ESEL2:1; /* eSEL2 */ + vuint32_t:3; /* */ + vuint32_t ESEL1:1; /* eSEL1 */ + vuint32_t:3; /* */ + vuint32_t ESEL0:1; /* eSEL0 */ + } B; + } ISEL8; /* MUX Select Register 8 (ISEL8) (new in MPC563xM) SIU_ISEL8 @baseaddress + 0x924 */ + + union { + vuint32_t R; + struct { + vuint32_t:27; /* */ + vuint32_t ETSEL0A:5; /* eTSEL0A */ + } B; + } ISEL9; /* MUX Select Register 9(ISEL9) SIU_ISEL9 @baseaddress + 0x980 */ + + int32_t SIU_reserverd_230[22]; + + union { + vuint32_t R; + struct { + vuint32_t:14; /* */ + vuint32_t MATCH:1; /* Compare Register Match */ + vuint32_t DISNEX:1; /* Disable Nexus */ + vuint32_t:14; /* */ + vuint32_t CRSE:1; /* Calibration Reflection Suppression Enable (new in MPC563xM) */ + vuint32_t:1; /* */ + } B; + } CCR; /* Chip Configuration Register (CCR) SIU_CCR @baseaddress + 0x984 */ + + union { + vuint32_t R; + struct { + vuint32_t:28; /* The ENGDIV bit is reserved in MPC563xM */ + vuint32_t EBTS:1; /* External Bus Tap Select */ + vuint32_t:1; /* */ + vuint32_t EBDF:2; /* External Bus Division Factor */ + } B; + } ECCR; /* External Clock Control Register (ECCR) SIU_ECCR @baseaddress + 0x988 */ + + union { + vuint32_t R; + } CARH; /* Compare A High Register (CARH) SIU_CMPAH @baseaddress + 0x98C */ + + union { + vuint32_t R; + } CARL; /* Compare A Low Register (CARL) SIU_CMPAL @baseaddress + 0x990 */ + + union { + vuint32_t R; + } CBRH; /* Compare B High Register (CBRH) SIU_CMPBH @baseaddress + 0x994 */ + + union { + vuint32_t R; + } CBRL; /* Compare B Low Register (CBRL) SIU_CMPBL @baseaddress + 0x9A0 */ + + int32_t SIU_reserverd_250[2]; + + union { + vuint32_t R; + struct { + vuint32_t:27; /* Reserved */ + vuint32_t BYPASS:1; /* Bypass bit BY-PASS */ + vuint32_t SYSCLKDIV:2; /* System Clock Divide SYS-CLKDIV */ + vuint32_t:2; /* Reserved */ + } B; + } SYSDIV; /* System Clock Register (SYSDIV) (new in MPC563xM) SIU_SYSDIV @baseaddress + 0x9A4 */ + + union { + vuint32_t R; + struct { + vuint32_t CPUSTP:1; /* CPU stop request. When asserted, a stop request is sent to the following modules: */ + vuint32_t:2; /* Reserved */ + vuint32_t SWTSTP:1; /* SWT stop request. When asserted, a stop request is sent to the Software Watchdog */ + vuint32_t:1; /* Reserved */ + vuint32_t TPUSTP:1; /* eTPU stop request. When asserted, a stop request is sent to the eTPU module. */ + vuint32_t NPCSTP:1; /* Nexus stop request. When asserted, a stop request is sent to the Nexus Controller. */ + vuint32_t EBISTP:1; /* EBI stop request. When asserted, a stop request is sent to the external bus */ + vuint32_t ADCSTP:1; /* eQADC stop request. When asserted, a stop request is sent to the eQADC module. */ + vuint32_t:1; /* Reserved */ + vuint32_t MIOSSTP:1; /* Stop mode request */ + vuint32_t DFILSTP:1; /* Decimation filter stop request. When asserted, a stop request is sent to the */ + vuint32_t:1; /* Reserved */ + vuint32_t PITSTP:1; /* PIT stop request. When asserted, a stop request is sent to the periodical internal */ + vuint32_t:3; /* Reserved */ + vuint32_t CNCSTP:1; /* FlexCAN C stop request. When asserted, a stop request is sent to the FlexCAN C */ + vuint32_t:1; /* Reserved */ + vuint32_t CNASTP:1; /* FlexCAN A stop request. When asserted, a stop request is sent to the FlexCAN A */ + vuint32_t:1; /* Reserved */ + vuint32_t SPICSTP:1; /* DSPI C stop request. When asserted, a stop request is sent to the DSPI C. */ + vuint32_t SPIBSTP:1; /* DSPI B stop request. When asserted, a stop request is sent to the DSPI B. */ + vuint32_t:7; /* Reserved */ + vuint32_t SCIBSTP:1; /* eSCI B stop request. When asserted, a stop request is sent to the eSCI B module. */ + vuint32_t SCIASTP:1; /* eSCI A stop request. When asserted, a stop request is sent to the eSCIA module. */ + } B; + } HLT; /* Halt Register (HLT) (new in MPC563xM) SIU_HLT @baseaddress + 0x9A8 */ + + union { + vuint32_t R; + struct { + vuint32_t CPUACK:1; /* CPU stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t:2; /* Reserved */ + vuint32_t SWTACK:1; /* SWT stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t:1; /* Reserved */ + vuint32_t TPUACK:1; /* eTPU stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t NPCACK:1; /* Nexus stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t EBIACK:1; /* EBI stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t ADCACK:1; /* eQADC stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t:1; /* Reserved */ + vuint32_t MIOSACK:1; /* eMIOS stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t DFILACK:1; /* Decimation filter stop acknowledge. When asserted, indicates that a stop */ + vuint32_t:1; /* Reserved */ + vuint32_t PITACK:1; /* PIT stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t:3; /* Reserved */ + vuint32_t CNCACK:1; /* FlexCAN C stop acknowledge. When asserted, indicates that a stop acknowledge */ + vuint32_t:1; /* Reserved */ + vuint32_t CNAACK:1; /* FlexCAN A stop acknowledge. When asserted, indicates that a stop acknowledge */ + vuint32_t:1; /* Reserved */ + vuint32_t SPICACK:1; /* DSPI C stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t SPIBACK:1; /* DSPI B stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t:7; /* Reserved */ + vuint32_t SCIBACK:1; /* eSCI B stop acknowledge */ + vuint32_t SCIAACK:1; /* eSCI A stop acknowledge. */ + } B; + } HLTACK; /* Halt Acknowledge Register (HLTACK) (new in MPC563xM) SIU_HLTACK @baseaddress + 0x9ac */ + + int32_t SIU_reserved3[21]; + + }; /* end of SIU_tag */ +/****************************************************************************/ +/* MODULE : EMIOS */ +/****************************************************************************/ + struct EMIOS_tag { + union { + vuint32_t R; + struct { + vuint32_t DOZEEN:1; /* new in MPC563xM */ + vuint32_t MDIS:1; + vuint32_t FRZ:1; + vuint32_t GTBE:1; + vuint32_t ETB:1; + vuint32_t GPREN:1; + vuint32_t:6; + vuint32_t SRV:4; + vuint32_t GPRE:8; + vuint32_t:8; + } B; + } MCR; /* Module Configuration Register EMIOSMCR */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t F23:1; + vuint32_t F22:1; + vuint32_t F21:1; + vuint32_t F20:1; + vuint32_t F19:1; + vuint32_t F18:1; + vuint32_t F17:1; + vuint32_t F16:1; + vuint32_t F15:1; + vuint32_t F14:1; + vuint32_t F13:1; + vuint32_t F12:1; + vuint32_t F11:1; + vuint32_t F10:1; + vuint32_t F9:1; + vuint32_t F8:1; + vuint32_t F7:1; + vuint32_t F6:1; + vuint32_t F5:1; + vuint32_t F4:1; + vuint32_t F3:1; + vuint32_t F2:1; + vuint32_t F1:1; + vuint32_t F0:1; + } B; + } GFR; /* Global FLAG Register EMIOSGFLAG */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t OU23:1; + vuint32_t OU22:1; + vuint32_t OU21:1; + vuint32_t OU20:1; + vuint32_t OU19:1; + vuint32_t OU18:1; + vuint32_t OU17:1; + vuint32_t OU16:1; + vuint32_t OU15:1; + vuint32_t OU14:1; + vuint32_t OU13:1; + vuint32_t OU12:1; + vuint32_t OU11:1; + vuint32_t OU10:1; + vuint32_t OU9:1; + vuint32_t OU8:1; + vuint32_t OU7:1; + vuint32_t OU6:1; + vuint32_t OU5:1; + vuint32_t OU4:1; + vuint32_t OU3:1; + vuint32_t OU2:1; + vuint32_t OU1:1; + vuint32_t OU0:1; + } B; + } OUDR; /* Output Update Disable Register EMIOSOUDIS */ + + union { + vuint32_t R; + struct { + vuint32_t:8; /* */ + vuint32_t CHDIS23:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS22:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS21:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS20:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS19:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS18:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS17:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS16:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS15:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS14:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS13:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS12:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS11:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS10:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS9:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS8:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS7:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS6:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS5:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS4:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS3:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS2:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS1:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS0:1; /* Enable Channel [n] bit */ + } B; + } UCDIS; /* Disable Channel (EMIOSUCDIS) EMIOSUCDIS (new in MPC563xM) @baseaddress + 0x0C */ + + int32_t EMIOS_reserverd_30[4]; + + struct { + union { + vuint32_t R; /* Channel A Data Register */ + } CADR; /* EMIOSA */ + + union { + vuint32_t R; /* Channel B Data Register */ + } CBDR; /* EMIOSB */ + + union { + vuint32_t R; /* Channel Counter Register */ + } CCNTR; /* EMIOSCNT */ + + union { + vuint32_t R; + struct { + vuint32_t FREN:1; + vuint32_t ODIS:1; + vuint32_t ODISSL:2; + vuint32_t UCPRE:2; + vuint32_t UCPREN:1; + vuint32_t DMA:1; + vuint32_t:1; + vuint32_t IF:4; + vuint32_t FCK:1; + vuint32_t FEN:1; + vuint32_t:3; + vuint32_t FORCMA:1; + vuint32_t FORCMB:1; + vuint32_t:1; + vuint32_t BSL:2; + vuint32_t EDSEL:1; + vuint32_t EDPOL:1; + vuint32_t MODE:7; + } B; + } CCR; /* Channel Control Register EMIOSC */ + + union { + vuint32_t R; + struct { + vuint32_t OVR:1; + vuint32_t:15; + vuint32_t OVFL:1; + vuint32_t:12; + vuint32_t UCIN:1; + vuint32_t UCOUT:1; + vuint32_t FLAG:1; + } B; + } CSR; /* Channel Status Register EMIOSS */ + + union { + vuint32_t R; /* Alternate Channel A Data Register */ + } ALTA; /* new in MPC563xM EMIOSALTA */ + + uint32_t emios_channel_reserved[2]; + + } CH[24]; + + }; /* end of EMIOS_tag */ +/****************************************************************************/ +/* MODULE : ETPU */ +/****************************************************************************/ + struct ETPU_tag { /* offset 0x0000 */ + union { /* eTPU module configuration register@baseaddress + 0x00 */ + vuint32_t R; + struct { + vuint32_t GEC:1; /* Global Exception Clear */ + vuint32_t SDMERR:1; /* */ + vuint32_t WDTOA:1; /* */ + vuint32_t WDTOB:1; /* */ + vuint32_t MGE1:1; /* MGEA */ + vuint32_t MGE2:1; /* MGEB */ + vuint32_t ILF1:1; /* Invalid instruction flag eTPU A. ILFFA */ + vuint32_t ILF2:1; /* Invalid instruction flag eTPU B. ILFFB */ + vuint32_t SCMERR:1; /* . */ + vuint32_t:2; /* */ + vuint32_t SCMSIZE:5; /* Shared Code Memory size */ + vuint32_t:4; /* */ + vuint32_t SCMMISC:1; /* SCM MISC Flag */ + vuint32_t SCMMISF:1; /* SCM MISC Flag */ + vuint32_t SCMMISEN:1; /* SCM MISC Enable */ + vuint32_t:2; /* */ + vuint32_t VIS:1; /* SCM Visability */ + vuint32_t:5; /* */ + vuint32_t GTBE:1; /* Global Time Base Enable */ + } B; + } MCR; /* ETPU_MCR */ + + /* offset 0x0004 */ + union { /* eTPU coherent dual-parameter controller register@baseaddress + 0x04 */ + vuint32_t R; + struct { + vuint32_t STS:1; /* Start Status bit */ + vuint32_t CTBASE:5; /* Channel Transfer Base */ + vuint32_t PBASE:10; /* Parameter Buffer Base Address PBBASE */ + vuint32_t PWIDTH:1; /* Parameter Width */ + vuint32_t PARAM0:7; /* Channel Parameter 0 PARM0 */ + vuint32_t WR:1; /* */ + vuint32_t PARAM1:7; /* Channel Parameter 1 PARM1 */ + } B; + } CDCR; /*ETPU_CDCR */ + + vuint32_t ETPU_reserved_0; + + /* offset 0x000C */ + union { /* eTPU MISC Compare Register@baseaddress + 0x0c */ + vuint32_t R; + struct { + vuint32_t ETPUMISCCMP:32; /* Expected multiple input signature calculator compare register value. EMISCCMP */ + } B; + } MISCCMPR /*ETPU_MISCCMPR */ ; + + /* offset 0x0010 */ + union { /* eTPU SCM Off-Range Data Register@baseaddress + 0x10 */ + vuint32_t R; + struct { + vuint32_t ETPUSCMOFFDATA:32; /* SCM Off-range read data value. */ + } B; + } SCMOFFDATAR; /*ETPU_SCMOFFDATAR */ + + /* offset 0x0014 */ + union { /* eTPU Engine Configuration Register (ETPUA_ECR)@baseaddress + 0x14 */ + vuint32_t R; + struct { + vuint32_t FEND:1; /* Force END */ + vuint32_t MDIS:1; /* Low power Stop */ + vuint32_t:1; /* */ + vuint32_t STF:1; /* Stop Flag */ + vuint32_t:4; /* */ + vuint32_t HLTF:1; /* Halt Mode Flag */ + vuint32_t:3; /* */ + vuint32_t FCSS:1; + vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */ + vuint32_t CDFC:2; /* */ + vuint32_t:1; /* */ + vuint32_t ERBA:5; /* */ + vuint32_t SPPDIS:1; /* */ + vuint32_t:2; /* */ + vuint32_t ETB:5; /* Entry Table Base */ + } B; + } ECR_A; /*ETPU_ECR */ + + vuint32_t ETPU_reserved_1[2]; + + /* offset 0x0020 */ + union { /* eTPU Time Base Configuration Register (ETPU_TBCR)@baseaddress + 0x20 */ + vuint32_t R; + struct { + vuint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ + vuint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ + vuint32_t AM:2; /* Angle Mode */ + vuint32_t:3; /* */ + vuint32_t TCR2P:6; /* TCR2 Prescaler Control */ + vuint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ + vuint32_t TCR1CS:1; /* */ + vuint32_t:5; /* */ + vuint32_t TCR1P:8; /* TCR1 Prescaler Control */ + } B; + } TBCR_A; /*ETPU_TBCR */ + + /* offset 0x0024 */ + union { /* eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R)@baseaddress + 0x24 */ + vuint32_t R; + struct { + vuint32_t:8; /* */ + vuint32_t TCR1:24; /* TCR1 value. Used on matches and captures. For more information, see the eTPU reference manual. */ + } B; + } TB1R_A; /*ETPU_TB1R */ + + /* offset 0x0028 */ + union { /* eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R)@baseaddress + 0x28 */ + vuint32_t R; + struct { + vuint32_t:8; /* */ + vuint32_t TCR2:24; /* TCR2 value. Used on matches and captures. For information on TCR2, see the eTPU reference manual. */ + } B; + } TB2R_A; /*ETPU_TB2R */ + + /* offset 0x002C */ + union { /* STAC Bus Configuration Register (ETPU_STACCR)@baseaddress + 0x2c */ + vuint32_t R; + struct { + vuint32_t REN1:1; /* Resource Enable TCR1 */ + vuint32_t RSC1:1; /* Resource Control TCR1 */ + vuint32_t:2; /* */ + vuint32_t SERVER_ID1:4; /* */ + vuint32_t:4; /* */ + vuint32_t SRV1:4; /* Resource Server Slot */ + vuint32_t REN2:1; /* Resource Enable TCR2 */ + vuint32_t RSC2:1; /* Resource Control TCR2 */ + vuint32_t:2; /* */ + vuint32_t SERVER_ID2:4; /* */ + vuint32_t:4; /* */ + vuint32_t SRV2:4; /* Resource Server Slot */ + } B; + } REDCR_A; /*ETPU_REDCR */ + + vuint32_t ETPU_reserved_2[12]; + + /* offset 0x0060 */ + union { /* ETPU1 WDTR Register */ + vuint32_t R; + struct { + vuint32_t WDM:2; + vuint32_t:14; + vuint32_t WDCNT:16; + } B; + } WDTR_A; + + vuint32_t ETPU1_reserved_3; + + /* offset 0x0068 */ + union { /* ETPU1 IDLE Register */ + vuint32_t R; + struct { + vuint32_t IDLE_CNT:31; + vuint32_t ICLR:1; + } B; + } IDLE_A; + + vuint32_t ETPU_reserved_4[101]; + + /* offset 0x0200 */ + union { /* eTPU Channel Interrupt Status Register (ETPU_CISR)@baseaddress + 0x200 */ + vuint32_t R; + struct { + vuint32_t CIS31:1; /* Channel 31 Interrut Status */ + vuint32_t CIS30:1; /* Channel 30 Interrut Status */ + vuint32_t CIS29:1; /* Channel 29 Interrut Status */ + vuint32_t CIS28:1; /* Channel 28 Interrut Status */ + vuint32_t CIS27:1; /* Channel 27 Interrut Status */ + vuint32_t CIS26:1; /* Channel 26 Interrut Status */ + vuint32_t CIS25:1; /* Channel 25 Interrut Status */ + vuint32_t CIS24:1; /* Channel 24 Interrut Status */ + vuint32_t CIS23:1; /* Channel 23 Interrut Status */ + vuint32_t CIS22:1; /* Channel 22 Interrut Status */ + vuint32_t CIS21:1; /* Channel 21 Interrut Status */ + vuint32_t CIS20:1; /* Channel 20 Interrut Status */ + vuint32_t CIS19:1; /* Channel 19 Interrut Status */ + vuint32_t CIS18:1; /* Channel 18 Interrut Status */ + vuint32_t CIS17:1; /* Channel 17 Interrut Status */ + vuint32_t CIS16:1; /* Channel 16 Interrut Status */ + vuint32_t CIS15:1; /* Channel 15 Interrut Status */ + vuint32_t CIS14:1; /* Channel 14 Interrut Status */ + vuint32_t CIS13:1; /* Channel 13 Interrut Status */ + vuint32_t CIS12:1; /* Channel 12 Interrut Status */ + vuint32_t CIS11:1; /* Channel 11 Interrut Status */ + vuint32_t CIS10:1; /* Channel 10 Interrut Status */ + vuint32_t CIS9:1; /* Channel 9 Interrut Status */ + vuint32_t CIS8:1; /* Channel 8 Interrut Status */ + vuint32_t CIS7:1; /* Channel 7 Interrut Status */ + vuint32_t CIS6:1; /* Channel 6 Interrut Status */ + vuint32_t CIS5:1; /* Channel 5 Interrut Status */ + vuint32_t CIS4:1; /* Channel 4 Interrut Status */ + vuint32_t CIS3:1; /* Channel 3 Interrut Status */ + vuint32_t CIS2:1; /* Channel 2 Interrut Status */ + vuint32_t CIS1:1; /* Channel 1 Interrut Status */ + vuint32_t CIS0:1; /* Channel 0 Interrut Status */ + } B; + } CISR_A; /* ETPU_CISR */ + + int32_t ETPU_reserved_5[3]; + + /* offset 0x0210 */ + union { /* @baseaddress + 0x210 */ + vuint32_t R; + struct { + vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ + vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ + vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ + vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ + vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ + vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ + vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ + vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ + vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ + vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ + vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ + vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ + vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ + vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ + vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ + vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ + vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ + vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ + vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ + vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ + vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ + vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ + vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ + vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ + vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ + vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ + vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ + vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ + vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ + vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ + vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ + vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ + } B; + } CDTRSR_A; /* ETPU_CDTRSR */ + + int32_t ETPU_reserved_6[3]; + + /* offset 0x0220 */ + union { /* eTPU Channel Interrupt Overflow Status Register (ETPU_CIOSR)@baseaddress + 0x220 */ + vuint32_t R; + struct { + vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ + vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ + vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ + vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ + vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ + vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ + vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ + vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ + vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ + vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ + vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ + vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ + vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ + vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ + vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ + vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ + vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ + vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ + vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ + vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ + vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ + vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ + vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ + vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ + vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ + vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ + vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ + vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ + vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ + vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ + vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ + vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ + } B; + } CIOSR_A; /* ETPU_CIOSR */ + + int32_t ETPU_reserved_7[3]; + + /* offset 0x0230 */ + union { /* eTPU Channel Data Transfer Request Overflow Status Register@baseaddress + 0x230 */ + vuint32_t R; + struct { + vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ + vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ + vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ + vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ + vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ + vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ + vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ + vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ + vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ + vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ + vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ + vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ + vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ + vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ + vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ + vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ + vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ + vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ + vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ + vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ + vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ + vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ + vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ + vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ + vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ + vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ + vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ + vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ + vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ + vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ + vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ + vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ + } B; + } CDTROSR_A; /* ETPU_CDTROSR */ + + int32_t ETPU_reserved_8[3]; + + /* offset 0x0240 */ + union { /* eTPU Channel Interrupt Enable Register (ETPU_CIER)@baseaddress + 0x240 */ + vuint32_t R; + struct { + vuint32_t CIE31:1; /* Channel 31 Interruput Enable */ + vuint32_t CIE30:1; /* Channel 30 Interruput Enable */ + vuint32_t CIE29:1; /* Channel 29 Interruput Enable */ + vuint32_t CIE28:1; /* Channel 28 Interruput Enable */ + vuint32_t CIE27:1; /* Channel 27 Interruput Enable */ + vuint32_t CIE26:1; /* Channel 26 Interruput Enable */ + vuint32_t CIE25:1; /* Channel 25 Interruput Enable */ + vuint32_t CIE24:1; /* Channel 24 Interruput Enable */ + vuint32_t CIE23:1; /* Channel 23 Interruput Enable */ + vuint32_t CIE22:1; /* Channel 22 Interruput Enable */ + vuint32_t CIE21:1; /* Channel 21 Interruput Enable */ + vuint32_t CIE20:1; /* Channel 20 Interruput Enable */ + vuint32_t CIE19:1; /* Channel 19 Interruput Enable */ + vuint32_t CIE18:1; /* Channel 18 Interruput Enable */ + vuint32_t CIE17:1; /* Channel 17 Interruput Enable */ + vuint32_t CIE16:1; /* Channel 16 Interruput Enable */ + vuint32_t CIE15:1; /* Channel 15 Interruput Enable */ + vuint32_t CIE14:1; /* Channel 14 Interruput Enable */ + vuint32_t CIE13:1; /* Channel 13 Interruput Enable */ + vuint32_t CIE12:1; /* Channel 12 Interruput Enable */ + vuint32_t CIE11:1; /* Channel 11 Interruput Enable */ + vuint32_t CIE10:1; /* Channel 10 Interruput Enable */ + vuint32_t CIE9:1; /* Channel 9 Interruput Enable */ + vuint32_t CIE8:1; /* Channel 8 Interruput Enable */ + vuint32_t CIE7:1; /* Channel 7 Interruput Enable */ + vuint32_t CIE6:1; /* Channel 6 Interruput Enable */ + vuint32_t CIE5:1; /* Channel 5 Interruput Enable */ + vuint32_t CIE4:1; /* Channel 4 Interruput Enable */ + vuint32_t CIE3:1; /* Channel 3 Interruput Enable */ + vuint32_t CIE2:1; /* Channel 2 Interruput Enable */ + vuint32_t CIE1:1; /* Channel 1 Interruput Enable */ + vuint32_t CIE0:1; /* Channel 0 Interruput Enable */ + } B; + } CIER_A; /* ETPU_CIER */ + + int32_t ETPU_reserved_9[3]; + + /* offset 0x0250 */ + union { /* eTPU Channel Data Transfer Request Enable Register (ETPU_CDTRER)@baseaddress + 0x250 */ + vuint32_t R; + struct { + vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ + vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ + vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ + vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ + vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ + vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ + vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ + vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ + vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ + vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ + vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ + vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ + vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ + vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ + vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ + vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ + vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ + vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ + vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ + vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ + vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ + vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ + vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ + vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ + vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ + vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ + vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ + vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ + vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ + vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ + vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ + vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CDTRER_A; /* ETPU_CDTRER */ + + int32_t ETPU_reserved_10[3]; + + /* offset 0x0260 */ + union { /* ETPUWDSR - eTPU Watchdog Status Register */ + vuint32_t R; + struct { + vuint32_t WDS31:1; /* Channel 31 Data Transfer Request Enable */ + vuint32_t WDS30:1; /* Channel 30 Data Transfer Request Enable */ + vuint32_t WDS29:1; /* Channel 29 Data Transfer Request Enable */ + vuint32_t WDS28:1; /* Channel 28 Data Transfer Request Enable */ + vuint32_t WDS27:1; /* Channel 27 Data Transfer Request Enable */ + vuint32_t WDS26:1; /* Channel 26 Data Transfer Request Enable */ + vuint32_t WDS25:1; /* Channel 25 Data Transfer Request Enable */ + vuint32_t WDS24:1; /* Channel 24 Data Transfer Request Enable */ + vuint32_t WDS23:1; /* Channel 23 Data Transfer Request Enable */ + vuint32_t WDS22:1; /* Channel 22 Data Transfer Request Enable */ + vuint32_t WDS21:1; /* Channel 21 Data Transfer Request Enable */ + vuint32_t WDS20:1; /* Channel 20 Data Transfer Request Enable */ + vuint32_t WDS19:1; /* Channel 19 Data Transfer Request Enable */ + vuint32_t WDS18:1; /* Channel 18 Data Transfer Request Enable */ + vuint32_t WDS17:1; /* Channel 17 Data Transfer Request Enable */ + vuint32_t WDS16:1; /* Channel 16 Data Transfer Request Enable */ + vuint32_t WDS15:1; /* Channel 15 Data Transfer Request Enable */ + vuint32_t WDS14:1; /* Channel 14 Data Transfer Request Enable */ + vuint32_t WDS13:1; /* Channel 13 Data Transfer Request Enable */ + vuint32_t WDS12:1; /* Channel 12 Data Transfer Request Enable */ + vuint32_t WDS11:1; /* Channel 11 Data Transfer Request Enable */ + vuint32_t WDS10:1; /* Channel 10 Data Transfer Request Enable */ + vuint32_t WDS9:1; /* Channel 9 Data Transfer Request Enable */ + vuint32_t WDS8:1; /* Channel 8 Data Transfer Request Enable */ + vuint32_t WDS7:1; /* Channel 7 Data Transfer Request Enable */ + vuint32_t WDS6:1; /* Channel 6 Data Transfer Request Enable */ + vuint32_t WDS5:1; /* Channel 5 Data Transfer Request Enable */ + vuint32_t WDS4:1; /* Channel 4 Data Transfer Request Enable */ + vuint32_t WDS3:1; /* Channel 3 Data Transfer Request Enable */ + vuint32_t WDS2:1; /* Channel 2 Data Transfer Request Enable */ + vuint32_t WDS1:1; /* Channel 1 Data Transfer Request Enable */ + vuint32_t WDS0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } WDSR_A; + + int32_t ETPU_reserved_11[7]; + + /* offset 0x0280 */ + union { /* ETPUCPSSR - eTPU Channel Pending Service Status Register */ + vuint32_t R; + struct { + vuint32_t SR31:1; /* Channel 31 Data Transfer Request Enable */ + vuint32_t SR30:1; /* Channel 30 Data Transfer Request Enable */ + vuint32_t SR29:1; /* Channel 29 Data Transfer Request Enable */ + vuint32_t SR28:1; /* Channel 28 Data Transfer Request Enable */ + vuint32_t SR27:1; /* Channel 27 Data Transfer Request Enable */ + vuint32_t SR26:1; /* Channel 26 Data Transfer Request Enable */ + vuint32_t SR25:1; /* Channel 25 Data Transfer Request Enable */ + vuint32_t SR24:1; /* Channel 24 Data Transfer Request Enable */ + vuint32_t SR23:1; /* Channel 23 Data Transfer Request Enable */ + vuint32_t SR22:1; /* Channel 22 Data Transfer Request Enable */ + vuint32_t SR21:1; /* Channel 21 Data Transfer Request Enable */ + vuint32_t SR20:1; /* Channel 20 Data Transfer Request Enable */ + vuint32_t SR19:1; /* Channel 19 Data Transfer Request Enable */ + vuint32_t SR18:1; /* Channel 18 Data Transfer Request Enable */ + vuint32_t SR17:1; /* Channel 17 Data Transfer Request Enable */ + vuint32_t SR16:1; /* Channel 16 Data Transfer Request Enable */ + vuint32_t SR15:1; /* Channel 15 Data Transfer Request Enable */ + vuint32_t SR14:1; /* Channel 14 Data Transfer Request Enable */ + vuint32_t SR13:1; /* Channel 13 Data Transfer Request Enable */ + vuint32_t SR12:1; /* Channel 12 Data Transfer Request Enable */ + vuint32_t SR11:1; /* Channel 11 Data Transfer Request Enable */ + vuint32_t SR10:1; /* Channel 10 Data Transfer Request Enable */ + vuint32_t SR9:1; /* Channel 9 Data Transfer Request Enable */ + vuint32_t SR8:1; /* Channel 8 Data Transfer Request Enable */ + vuint32_t SR7:1; /* Channel 7 Data Transfer Request Enable */ + vuint32_t SR6:1; /* Channel 6 Data Transfer Request Enable */ + vuint32_t SR5:1; /* Channel 5 Data Transfer Request Enable */ + vuint32_t SR4:1; /* Channel 4 Data Transfer Request Enable */ + vuint32_t SR3:1; /* Channel 3 Data Transfer Request Enable */ + vuint32_t SR2:1; /* Channel 2 Data Transfer Request Enable */ + vuint32_t SR1:1; /* Channel 1 Data Transfer Request Enable */ + vuint32_t SR0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CPSSR_A; /* ETPU_CPSSR */ + + int32_t ETPU_reserved_12[3]; + + /* offset 0x0290 */ + union { /* ETPUCSSR - eTPU Channel Service Status Register */ + vuint32_t R; + struct { + vuint32_t SS31:1; /* Channel 31 Data Transfer Request Enable */ + vuint32_t SS30:1; /* Channel 30 Data Transfer Request Enable */ + vuint32_t SS29:1; /* Channel 29 Data Transfer Request Enable */ + vuint32_t SS28:1; /* Channel 28 Data Transfer Request Enable */ + vuint32_t SS27:1; /* Channel 27 Data Transfer Request Enable */ + vuint32_t SS26:1; /* Channel 26 Data Transfer Request Enable */ + vuint32_t SS25:1; /* Channel 25 Data Transfer Request Enable */ + vuint32_t SS24:1; /* Channel 24 Data Transfer Request Enable */ + vuint32_t SS23:1; /* Channel 23 Data Transfer Request Enable */ + vuint32_t SS22:1; /* Channel 22 Data Transfer Request Enable */ + vuint32_t SS21:1; /* Channel 21 Data Transfer Request Enable */ + vuint32_t SS20:1; /* Channel 20 Data Transfer Request Enable */ + vuint32_t SS19:1; /* Channel 19 Data Transfer Request Enable */ + vuint32_t SS18:1; /* Channel 18 Data Transfer Request Enable */ + vuint32_t SS17:1; /* Channel 17 Data Transfer Request Enable */ + vuint32_t SS16:1; /* Channel 16 Data Transfer Request Enable */ + vuint32_t SS15:1; /* Channel 15 Data Transfer Request Enable */ + vuint32_t SS14:1; /* Channel 14 Data Transfer Request Enable */ + vuint32_t SS13:1; /* Channel 13 Data Transfer Request Enable */ + vuint32_t SS12:1; /* Channel 12 Data Transfer Request Enable */ + vuint32_t SS11:1; /* Channel 11 Data Transfer Request Enable */ + vuint32_t SS10:1; /* Channel 10 Data Transfer Request Enable */ + vuint32_t SS9:1; /* Channel 9 Data Transfer Request Enable */ + vuint32_t SS8:1; /* Channel 8 Data Transfer Request Enable */ + vuint32_t SS7:1; /* Channel 7 Data Transfer Request Enable */ + vuint32_t SS6:1; /* Channel 6 Data Transfer Request Enable */ + vuint32_t SS5:1; /* Channel 5 Data Transfer Request Enable */ + vuint32_t SS4:1; /* Channel 4 Data Transfer Request Enable */ + vuint32_t SS3:1; /* Channel 3 Data Transfer Request Enable */ + vuint32_t SS2:1; /* Channel 2 Data Transfer Request Enable */ + vuint32_t SS1:1; /* Channel 1 Data Transfer Request Enable */ + vuint32_t SS0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CSSR_A; /* ETPU_CSSR */ + + int32_t ETPU_reserved_13[3]; + int32_t ETPU_reserved_14[88]; + +/***************************** Channels ********************************/ +/* Note not all devices implement all channels or even 2 engines */ +/* Each eTPU engine can implement 64 channels, however most devcies */ +/* only implemnet 32 channels. The eTPU block can implement 1 or 2 */ +/* engines per instantiation */ +/***********************************************************************/ + + struct { + union { /* eTPU Channel n Configuration Register (ETPU_CnCR)@baseaddress + 0x400 */ + vuint32_t R; + struct { + vuint32_t CIE:1; /* Channel Interruput Enable */ + vuint32_t DTRE:1; /* Data Transfer Request Enable */ + vuint32_t CPR:2; /* Channel Priority */ + vuint32_t:2; /* */ + vuint32_t ETPD:1; /* This bit selects which channel signal, input or output, is used in the entry point selection */ + vuint32_t ETCS:1; /* Entry Table Condition Select */ + vuint32_t:3; /* */ + vuint32_t CFS:5; /* Channel Function Select */ + vuint32_t ODIS:1; /* Output disable */ + vuint32_t OPOL:1; /* output polarity */ + vuint32_t:3; /* */ + vuint32_t CPBA:11; /* Channel Parameter Base Address */ + } B; + } CR; /* ETPU_CnCR */ + + union { /* eTPU Channel n Status Control Register (ETPU_CnSCR)@baseaddress + 0x404 */ + vuint32_t R; + struct { + vuint32_t CIS:1; /* Channel Interruput Status */ + vuint32_t CIOS:1; /* Channel Interruput Overflow Status */ + vuint32_t:6; /* */ + vuint32_t DTRS:1; /* Data Transfer Status */ + vuint32_t DTROS:1; /* Data Transfer Overflow Status */ + vuint32_t:6; /* */ + vuint32_t IPS:1; /* Input Pin State */ + vuint32_t OPS:1; /* Output Pin State */ + vuint32_t OBE:1; /* Output Pin State */ + vuint32_t:11; /* */ + vuint32_t FM1:1; /* Function mode */ + vuint32_t FM0:1; /* Function mode */ + } B; + } SCR; /* ETPU_CnSCR */ + + union { /* eTPU channel host service request register (ETPU_CnHSRR)@baseaddress + 0x408 */ + vuint32_t R; + struct { + vuint32_t:29; /* Host Service Request */ + vuint32_t HSR:3; /* */ + } B; + } HSRR; /* ETPU_CnHSRR */ + int32_t ETPU_reserved_18; + + } CHAN[127]; + /**** Note: Not all channels implemented on all devices. Up 64 can be implemented on */ + }; /* end of ETPU_tag */ +/****************************************************************************/ +/* MODULE : XBAR */ +/****************************************************************************/ + struct XBAR_tag { + union { + vuint32_t R; + struct { + vuint32_t:4; /* Master 7 Priority - Not implemented */ + vuint32_t:4; /* Master 6 Priority - Not implemented */ + vuint32_t:4; /* Master 5 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ + vuint32_t:4; /* Master 3 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ + vuint32_t:1; /* */ + vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ + vuint32_t:1; /* */ + vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ + } B; + } MPR0; /* Master Priority Register for Slave port 0 @baseaddress + 0x00 - Flash */ + + int32_t XBAR_reserverd_35[3]; + + union { + vuint32_t R; + struct { + vuint32_t RO:1; /* Read Only */ + vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ + vuint32_t:6; /* Slave General Purpose Control Register Reserved */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:6; /* */ + vuint32_t ARB:2; /* Arbitration Mode */ + vuint32_t:2; /* */ + vuint32_t PCTL:2; /* Parking Control */ + vuint32_t:1; /* */ + vuint32_t PARK:3; /* PARK */ + } B; + } SGPCR0; /* Slave General Purpose Control Register 0 @baseaddress + 0x10 */ + + int32_t XBAR_reserverd_71[59]; + + union { + vuint32_t R; + struct { + vuint32_t:4; /* Master 7 Priority - Not implemented */ + vuint32_t:4; /* Master 6 Priority - Not implemented */ + vuint32_t:4; /* Master 5 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ + vuint32_t:4; /* Master 3 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ + vuint32_t:1; /* */ + vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ + vuint32_t:1; /* */ + vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ + } B; + } MPR1; /* Master Priority Register for Slave port 1 @baseaddress + 0x100 */ + + int32_t XBAR_reserverd_105[3]; + + union { + vuint32_t R; + struct { + vuint32_t RO:1; /* Read Only */ + vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ + vuint32_t:6; /* Slave General Purpose Control Register Reserved */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:6; /* */ + vuint32_t ARB:2; /* Arbitration Mode */ + vuint32_t:2; /* */ + vuint32_t PCTL:2; /* Parking Control */ + vuint32_t:1; /* */ + vuint32_t PARK:3; /* PARK */ + } B; + } SGPCR1; /* Slave General Purpose Control Register 1 @baseaddress + 0x110 */ + + int32_t XBAR_reserverd_141[59]; + +/* Slave General Purpose Control Register 2 @baseaddress + 0x210 - not implemented */ + + int32_t XBAR_reserverd_211[64]; + + union { + vuint32_t R; + struct { + vuint32_t:4; /* Master 7 Priority - Not implemented */ + vuint32_t:4; /* Master 6 Priority - Not implemented */ + vuint32_t:4; /* Master 5 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ + vuint32_t:4; /* Master 3 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ + vuint32_t:1; /* */ + vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ + vuint32_t:1; /* */ + vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ + } B; + } MPR3; /* Master Priority Register for Slave port 3 @baseaddress + 0x300 */ + + int32_t XBAR_reserverd_245[3]; + + union { + vuint32_t R; + struct { + vuint32_t RO:1; /* Read Only */ + vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ + vuint32_t:6; /* Slave General Purpose Control Register Reserved */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:6; /* */ + vuint32_t ARB:2; /* Arbitration Mode */ + vuint32_t:2; /* */ + vuint32_t PCTL:2; /* Parking Control */ + vuint32_t:1; /* */ + vuint32_t PARK:3; /* PARK */ + } B; + } SGPCR3; /* Slave General Purpose Control Register 3 @baseaddress + 0x310 */ + + int32_t XBAR_reserverd_281[59]; + + /* Slave General Purpose Control Register 4 @baseaddress + 0x410 - not implemented */ + + int32_t XBAR_reserverd_351[64]; + + /* Slave XBAR Port 5 Not implemented @baseaddress + 0x510 */ + + int32_t XBAR_reserverd_421[64]; + + /* Slave Port 6 not implemented @baseaddress + 0x610 */ + + int32_t XBAR_reserverd_491[64]; + + union { + vuint32_t R; + struct { + vuint32_t:4; /* Master 7 Priority - Not implemented */ + vuint32_t:4; /* Master 6 Priority - Not implemented */ + vuint32_t:4; /* Master 5 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ + vuint32_t:4; /* Master 3 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ + vuint32_t:1; /* */ + vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ + vuint32_t:1; /* */ + vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ + } B; + } MPR7; /* Master Priority Register for Slave port 7 @baseaddress + 0x700 */ + + int32_t XBAR_reserverd_525[3]; + + union { + vuint32_t R; + struct { + vuint32_t RO:1; /* Read Only */ + vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ + vuint32_t:6; /* Slave General Purpose Control Register Reserved */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:6; /* */ + vuint32_t ARB:2; /* Arbitration Mode */ + vuint32_t:2; /* */ + vuint32_t PCTL:2; /* Parking Control */ + vuint32_t:1; /* */ + vuint32_t PARK:3; /* PARK */ + } B; + } SGPCR7; /* Slave General Purpose Control Register 7 @baseaddress + 0x710 */ + + int32_t XBAR_reserverd_561[59]; + + union { + vuint32_t R; + struct { + vuint32_t:29; /* */ + vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ + } B; + } MGPCR0; /* Master General Purpose Control Register 0 @baseaddress + 0x800 */ + + int32_t XBAR_reserverd_564[63]; + + union { + vuint32_t R; + struct { + vuint32_t:29; /* */ + vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ + } B; + } MGPCR1; /* Master General Purpose Control Register 1 @baseaddress + 0x900 */ + + int32_t XBAR_reserverd_567[63]; + + union { + vuint32_t R; + struct { + vuint32_t:29; /* */ + vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ + } B; + } MGPCR2; /* Master General Purpose Control Register 2 @baseaddress + 0xA00 */ + + int32_t XBAR_reserverd_570[63]; + + /* Master General Purpose Control Register 3 not implemented @baseaddress + 0xB00 */ + + int32_t XBAR_reserverd_573[64]; + + union { + vuint32_t R; + struct { + vuint32_t:29; /* */ + vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ + } B; + } MGPCR4; /* Master General Purpose Control Register 4 @baseaddress + 0xC00 */ + + int32_t XBAR_reserverd_576[64]; + + /* Master General Purpose Control Register 5 not implemented @baseaddress + 0xD00 */ + + int32_t XBAR_reserverd_579[64]; + + /* Master General Purpose Control Register 6 not implemented @baseaddress + 0xE00 */ + + int32_t XBAR_reserverd_582[64]; + + /* Master General Purpose Control Register 7 not implemented @baseaddress + 0xF00 */ + + }; /* end of XBAR_tag */ +/****************************************************************************/ +/* MODULE : ECSM */ +/****************************************************************************/ + struct ECSM_tag { + /* SWTCR, SWTSR and SWTIR don't exist in MPC563xM */ + uint32_t ecsm_reserved1[16]; + + uint8_t ecsm_reserved3[3]; /* base + 0x40 */ + + union { + vuint8_t R; + struct { + vuint8_t:6; + vuint8_t ERNCR:1; /* EPRNCR */ + vuint8_t EFNCR:1; /* EPFNCR */ + } B; + } ECR; /* ECC Configuration Register */ + + uint8_t ecsm_reserved4[3]; /* base + 0x44 */ + + union { + vuint8_t R; + struct { + vuint8_t:6; + vuint8_t RNCE:1; /* PRNCE */ + vuint8_t FNCE:1; /* PFNCE */ + } B; + } ESR; /* ECC Status Register */ + + /* EEGR don't exist in MPC563xM */ + uint32_t ecsm_reserved4a[2]; + + union { + vuint32_t R; + struct { + vuint32_t FEAR:32; /* PFEAR */ + } B; + } FEAR; /* Flash ECC Address Register PFEAR - 0x50 */ + + uint16_t ecsm_reserved4b; + + union { + vuint8_t R; + struct { + vuint8_t:4; + vuint8_t FEMR:4; /* PFEMR */ + } B; + } FEMR; /* Flash ECC Master Register PFEMR */ + + union { + vuint8_t R; + struct { + vuint8_t WRITE:1; + vuint8_t SIZE:3; + vuint8_t PROT0:1; /* PROTECTION */ + vuint8_t PROT1:1; /* PROTECTION */ + vuint8_t PROT2:1; /* PROTECTION */ + vuint8_t PROT3:1; /* PROTECTION */ + } B; + } FEAT; /* Flash ECC Attributes Register PFEAT */ + + union { + vuint32_t R; + struct { + vuint32_t FEDH:32; /* PFEDR */ + } B; + } FEDRH; /* Flash ECC Data High Register PFEDRH */ + + union { + vuint32_t R; + struct { + vuint32_t FEDL:32; /* PFEDR */ + } B; + } FEDRL; /* Flash ECC Data Low Register PFEDRL */ + + union { + vuint32_t R; + struct { + vuint32_t REAR:32; /* PREAR */ + } B; + } REAR; /* RAM ECC Address PREAR */ + + uint8_t ecsm_reserved5; + + union { + vuint8_t R; + struct { + vuint8_t PRESR:8; + } B; + } PRESR; /* RAM ECC Syndrome (new in MPC563xM) */ + + union { + vuint8_t R; + struct { + vuint8_t:4; + vuint8_t REMR:4; /* PREMR */ + } B; + } REMR; /* RAM ECC Master PREMR */ + + union { + vuint8_t R; + struct { + vuint8_t WRITE:1; + vuint8_t SIZE:3; + vuint8_t PROT0:1; /* PROTECTION */ + vuint8_t PROT1:1; /* PROTECTION */ + vuint8_t PROT2:1; /* PROTECTION */ + vuint8_t PROT3:1; /* PROTECTION */ + } B; + } REAT; /* RAM ECC Attributes Register PREAT */ + + union { + vuint32_t R; + struct { + vuint32_t REDH:32; /* PREDR */ + } B; + } REDRH; /* RAM ECC Data High Register PREDRH */ + + union { + vuint32_t R; + struct { + vuint32_t REDL:32; /* PREDR */ + } B; + } REDRL; /* RAMECC Data Low Register PREDRL */ + + }; +/****************************************************************************/ +/* MODULE : EDMA */ +/****************************************************************************/ + struct EDMA_tag { + union { + vuint32_t R; + struct { + vuint32_t:14; /* Reserved */ + vuint32_t CX:1; /* Cancel Transfer (new in MPC563xM) */ + vuint32_t ECX:1; /* Error Cancel Transfer (new in MPC563xM) */ + vuint32_t GRP3PRI:2; /* Channel Group 3 Priority (new in MPC563xM) */ + vuint32_t GRP2PRI:2; /* Channel Group 2 Priority (new in MPC563xM) */ + vuint32_t GRP1PRI:2; /* Channel Group 1 Priority */ + vuint32_t GRP0PRI:2; /* Channel Group 0 Priority */ + vuint32_t EMLM:1; /* Enable Minor Loop Mapping (new in MPC563xM) */ + vuint32_t CLM:1; /* Continuous Link Mode (new in MPC563xM) */ + vuint32_t HALT:1; /* Halt DMA Operations (new in MPC563xM) */ + vuint32_t HOE:1; /* Halt On Error (new in MPC563xM) */ + vuint32_t ERGA:1; /* Enable Round Robin Group Arbitration */ + vuint32_t ERCA:1; /* Enable Round Robin Channel Arbitration */ + vuint32_t EDBG:1; /* Enable Debug */ + vuint32_t EBW:1; /* Enable Buffered Writes */ + } B; + } CR; /* DMA Control Register DMACR @baseaddress + 0x0 */ + + union { + vuint32_t R; + struct { + vuint32_t VLD:1; /* Logical OR of all DMAERRH */ + + vuint32_t:14; /* Reserved */ + vuint32_t ECX:1; /* (new in MPC563xM) */ + vuint32_t GPE:1; /* Group Priority Error */ + vuint32_t CPE:1; /* Channel Priority Error */ + vuint32_t ERRCHN:6; /* ERRCHN[5:0] Error Channel Number or The channel number of the last recorded error */ + vuint32_t SAE:1; /* Source Address Error 0 */ + vuint32_t SOE:1; /* Source Offset Error */ + vuint32_t DAE:1; /* Destination Address Error */ + vuint32_t DOE:1; /* Destination Offset Error */ + vuint32_t NCE:1; /* Nbytes/Citer Configuration Error */ + vuint32_t SGE:1; /* Scatter/Gather Configuration Error */ + vuint32_t SBE:1; /* Source Bus Error */ + vuint32_t DBE:1; /* Destination Bus Error */ + + } B; + } ESR; /* DMAES Error Status Register */ + + uint32_t edma_reserved_erqrh; + + union { + vuint32_t R; + struct { + vuint32_t ERQ31:1; + vuint32_t ERQ30:1; + vuint32_t ERQ29:1; + vuint32_t ERQ28:1; + vuint32_t ERQ27:1; + vuint32_t ERQ26:1; + vuint32_t ERQ25:1; + vuint32_t ERQ24:1; + vuint32_t ERQ23:1; + vuint32_t ERQ22:1; + vuint32_t ERQ21:1; + vuint32_t ERQ20:1; + vuint32_t ERQ19:1; + vuint32_t ERQ18:1; + vuint32_t ERQ17:1; + vuint32_t ERQ16:1; + vuint32_t ERQ15:1; + vuint32_t ERQ14:1; + vuint32_t ERQ13:1; + vuint32_t ERQ12:1; + vuint32_t ERQ11:1; + vuint32_t ERQ10:1; + vuint32_t ERQ09:1; + vuint32_t ERQ08:1; + vuint32_t ERQ07:1; + vuint32_t ERQ06:1; + vuint32_t ERQ05:1; + vuint32_t ERQ04:1; + vuint32_t ERQ03:1; + vuint32_t ERQ02:1; + vuint32_t ERQ01:1; + vuint32_t ERQ00:1; + } B; + } ERQRL; /* DMAERQL ,DMA Enable Request Register Low */ + + uint32_t edma_reserved_eeirh; + + union { + vuint32_t R; + struct { + vuint32_t EEI31:1; + vuint32_t EEI30:1; + vuint32_t EEI29:1; + vuint32_t EEI28:1; + vuint32_t EEI27:1; + vuint32_t EEI26:1; + vuint32_t EEI25:1; + vuint32_t EEI24:1; + vuint32_t EEI23:1; + vuint32_t EEI22:1; + vuint32_t EEI21:1; + vuint32_t EEI20:1; + vuint32_t EEI19:1; + vuint32_t EEI18:1; + vuint32_t EEI17:1; + vuint32_t EEI16:1; + vuint32_t EEI15:1; + vuint32_t EEI14:1; + vuint32_t EEI13:1; + vuint32_t EEI12:1; + vuint32_t EEI11:1; + vuint32_t EEI10:1; + vuint32_t EEI09:1; + vuint32_t EEI08:1; + vuint32_t EEI07:1; + vuint32_t EEI06:1; + vuint32_t EEI05:1; + vuint32_t EEI04:1; + vuint32_t EEI03:1; + vuint32_t EEI02:1; + vuint32_t EEI01:1; + vuint32_t EEI00:1; + } B; + } EEIRL; /* DMAEEIL , DMA Enable Error Interrupt Register Low */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 SERQ:7 */ + } SERQR; /* DMASERQ , DMA Set Enable Request Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 CERQ:7 */ + } CERQR; /* DMACERQ , DMA Clear Enable Request Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 SEEI:7 */ + } SEEIR; /* DMASEEI , DMA Set Enable Error Interrupt Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 CEEI:7 */ + } CEEIR; /* DMACEEI , DMA Clear Enable Error Interrupt Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 CINT:7 */ + } CIRQR; /* DMACINT , DMA Clear Interrupt Request Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 CERR:7 */ + } CER; /* DMACERR , DMA Clear error Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 SSRT:7 */ + } SSBR; /* DMASSRT , Set Start Bit Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 CDNE:7 */ + } CDSBR; /* DMACDNE , Clear Done Status Bit Register */ + + uint32_t edma_reserved_irqrh; + + union { + vuint32_t R; + struct { + vuint32_t INT31:1; + vuint32_t INT30:1; + vuint32_t INT29:1; + vuint32_t INT28:1; + vuint32_t INT27:1; + vuint32_t INT26:1; + vuint32_t INT25:1; + vuint32_t INT24:1; + vuint32_t INT23:1; + vuint32_t INT22:1; + vuint32_t INT21:1; + vuint32_t INT20:1; + vuint32_t INT19:1; + vuint32_t INT18:1; + vuint32_t INT17:1; + vuint32_t INT16:1; + vuint32_t INT15:1; + vuint32_t INT14:1; + vuint32_t INT13:1; + vuint32_t INT12:1; + vuint32_t INT11:1; + vuint32_t INT10:1; + vuint32_t INT09:1; + vuint32_t INT08:1; + vuint32_t INT07:1; + vuint32_t INT06:1; + vuint32_t INT05:1; + vuint32_t INT04:1; + vuint32_t INT03:1; + vuint32_t INT02:1; + vuint32_t INT01:1; + vuint32_t INT00:1; + } B; + } IRQRL; /* DMAINTL , DMA Interrupt Request Low */ + + uint32_t edma_reserved_erh; + + union { + vuint32_t R; + struct { + vuint32_t ERR31:1; + vuint32_t ERR30:1; + vuint32_t ERR29:1; + vuint32_t ERR28:1; + vuint32_t ERR27:1; + vuint32_t ERR26:1; + vuint32_t ERR25:1; + vuint32_t ERR24:1; + vuint32_t ERR23:1; + vuint32_t ERR22:1; + vuint32_t ERR21:1; + vuint32_t ERR20:1; + vuint32_t ERR19:1; + vuint32_t ERR18:1; + vuint32_t ERR17:1; + vuint32_t ERR16:1; + vuint32_t ERR15:1; + vuint32_t ERR14:1; + vuint32_t ERR13:1; + vuint32_t ERR12:1; + vuint32_t ERR11:1; + vuint32_t ERR10:1; + vuint32_t ERR09:1; + vuint32_t ERR08:1; + vuint32_t ERR07:1; + vuint32_t ERR06:1; + vuint32_t ERR05:1; + vuint32_t ERR04:1; + vuint32_t ERR03:1; + vuint32_t ERR02:1; + vuint32_t ERR01:1; + vuint32_t ERR00:1; + } B; + } ERL; /* DMAERRL , DMA Error Low */ + + int32_t edma_reserverd_hrsh[1]; + + int32_t edma_reserverd_hrsl[1]; + + int32_t edma_reserverd_gpor[1]; + + int32_t EDMA_reserverd_223[49]; + + union { + vuint8_t R; + struct { + vuint8_t ECP:1; + vuint8_t DPA:1; + vuint8_t GRPPRI:2; + vuint8_t CHPRI:4; + } B; + } CPR[64]; /* DCHPRI [32] , Channel n Priority */ + + uint32_t edma_reserved2[944]; + +/****************************************************************************/ +/* DMA2 Transfer Control Descriptor */ +/****************************************************************************/ + + struct tcd_t { /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */ + vuint32_t SADDR; /* source address */ + + vuint16_t SMOD:5; /* source address modulo */ + vuint16_t SSIZE:3; /* source transfer size */ + vuint16_t DMOD:5; /* destination address modulo */ + vuint16_t DSIZE:3; /* destination transfer size */ + vint16_t SOFF; /* signed source address offset */ + vuint32_t NBYTES; /* inner (“minor”) byte count */ + vint32_t SLAST; /* last destination address adjustment, or + + scatter/gather address (if e_sg = 1) */ + vuint32_t DADDR; /* destination address */ + vuint16_t CITERE_LINK:1; + vuint16_t CITER:15; + vint16_t DOFF; /* signed destination address offset */ + vint32_t DLAST_SGA; + vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */ + vuint16_t BITER:15; + vuint16_t BWC:2; /* bandwidth control */ + vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */ + vuint16_t DONE:1; /* channel done */ + vuint16_t ACTIVE:1; /* channel active */ + vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */ + vuint16_t E_SG:1; /* enable scatter/gather descriptor */ + vuint16_t D_REQ:1; /* disable ipd_req when done */ + vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ + vuint16_t INT_MAJ:1; /* interrupt on major loop completion */ + vuint16_t START:1; /* explicit channel start */ + } TCD[64]; /* TCD [32] , transfer_control_descriptor */ + }; + + struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */ + + struct tcd_alt1_t { + vuint32_t SADDR; /* source address */ + + vuint16_t SMOD:5; /* source address modulo */ + vuint16_t SSIZE:3; /* source transfer size */ + vuint16_t DMOD:5; /* destination address modulo */ + vuint16_t DSIZE:3; /* destination transfer size */ + vint16_t SOFF; /* signed source address offset */ + vuint32_t NBYTES; /* inner (“minor”) byte count */ + vint32_t SLAST; /* last destination address adjustment, or + + scatter/gather address (if e_sg = 1) */ + vuint32_t DADDR; /* destination address */ + vuint16_t CITERE_LINK:1; + vuint16_t CITERLINKCH:6; + vuint16_t CITER:9; + vint16_t DOFF; /* signed destination address offset */ + vint32_t DLAST_SGA; + vuint16_t BITERE_LINK:1; /* beginning (“major”) iteration count */ + vuint16_t BITERLINKCH:6; + vuint16_t BITER:9; + vuint16_t BWC:2; /* bandwidth control */ + vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */ + vuint16_t DONE:1; /* channel done */ + vuint16_t ACTIVE:1; /* channel active */ + vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */ + vuint16_t E_SG:1; /* enable scatter/gather descriptor */ + vuint16_t D_REQ:1; /* disable ipd_req when done */ + vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ + vuint16_t INT_MAJ:1; /* interrupt on major loop completion */ + vuint16_t START:1; /* explicit channel start */ + } TCD[64]; /* TCD [32] , transfer_control_descriptor */ + }; + +/****************************************************************************/ +/* MODULE : INTC */ +/****************************************************************************/ + struct INTC_tag { + union { + vuint32_t R; + struct { + vuint32_t:18; /* Reserved */ + vuint32_t VTES_PRC1:1; /* Vector Table Entry Size for PRC1 (new in MPC563xM) */ + vuint32_t:4; /* Reserved */ + vuint32_t HVEN_PRC1:1; /* Hardware Vector Enable for PRC1 (new in MPC563xM) */ + vuint32_t:2; /* Reserved */ + vuint32_t VTES:1; /* Vector Table Entry Size for PRC0 VTES_PRC0 */ + vuint32_t:4; /* Reserved */ + vuint32_t HVEN:1; /* Hardware Vector Enable for PRC0 HVEN_PRC0 */ + } B; + } MCR; /* INTC Module Configuration Register (MCR) INTC_BCR @baseaddress + 0x00 */ + int32_t INTC_reserverd_10[1]; + + union { + vuint32_t R; + struct { + vuint32_t:28; /* Reserved */ + vuint32_t PRI:4; /* Priority */ + } B; + } CPR; /* INTC Current Priority Register for Processor 0 (CPR) INTC_CPR_PRC0 @baseaddress + 0x08 */ + + int32_t INTC_reserved_1; /* CPR_PRC1 - INTC Current Priority Register for Processor 1 (CPR_PRC1) INTC_CPR_PRC1 @baseaddress + 0x0c */ + + union { + vuint32_t R; + struct { + vuint32_t VTBA:21; /* Vector Table Base Address VTBA_PRC0 */ + vuint32_t INTVEC:9; /* Interrupt Vector INTVEC_PRC0 */ + vuint32_t:2; /* Reserved */ + } B; + } IACKR; /* INTC Interrupt Acknowledge Register for Processor 0 (IACKR) INTC_IACKR_PRC0 @baseaddress + 0x10 */ + + int32_t INTC_reserverd_2; /* IACKR_PRC1 - INTC Interrupt Acknowledge Register for Processor 1 (IACKR_PRC1) INTC_IACKR_PRC1 @baseaddress + 0x14 */ + + union { + vuint32_t R; + } EOIR; /* INTC End of Interrupt Register for Processor 0 (EOIR) INTC_EOIR_PRC0 @baseaddress + 0x18 */ + + int32_t INTC_reserverd_3; /* EOIR_PRC1 - INTC End of Interrupt Register for Processor 1 (EOIR_PRC1) INTC_EOIR_PRC1 @baseaddress + 0x1C */ + + union { + vuint8_t R; + struct { + vuint8_t:6; /* Reserved */ + vuint8_t SET:1; /* Set Flag bits */ + vuint8_t CLR:1; /* Clear Flag bits */ + } B; + } SSCIR[8]; /* INTC Software Set/Clear Interrupt Registers (SSCIR) INTC_SSCIRn @baseaddress + 0x20 */ + + int32_t INTC_reserverd_32[6]; + + union { + vuint8_t R; + struct { + vuint8_t PRC_SEL:2; /* Processor Select (new in MPC563xM) */ + vuint8_t:2; /* Reserved */ + vuint8_t PRI:4; /* Priority Select */ + } B; + } PSR[512]; /* INTC Priority Select Registers (PSR) INTC_PSR @baseaddress + 0x40 */ + + }; /* end of INTC_tag */ +/****************************************************************************/ +/* MODULE : EQADC */ +/****************************************************************************/ + struct EQADC_tag { + union { + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t ICEA0:1; + vuint32_t ICEA1:1; + vuint32_t:1; + vuint32_t ESSIE:2; + vuint32_t:1; + vuint32_t DBG:2; + } B; + } MCR; /* Module Configuration Register EQADC_MCR */ + + int32_t EQADC_reserved00; + + union { + vuint32_t R; + struct { + vuint32_t:6; + vuint32_t NMF:26; + } B; + } NMSFR; /* Null Message Send Format Register EQADC_NMSFR */ + + union { + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t DFL:4; + } B; + } ETDFR; /* External Trigger Digital Filter Register EQADC_ETDFR */ + + union { + vuint32_t R; + struct { + vuint32_t CFPUSH:32; /* CF_PUSH */ + } B; + } CFPR[6]; /* CFIFO Push Registers EQADC_CFPR */ + + uint32_t eqadc_reserved1; + + uint32_t eqadc_reserved2; + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RFPOP:16; /* RF_POP */ + } B; + } RFPR[6]; /* Result FIFO Pop Registers EQADC_RFPR */ + + uint32_t eqadc_reserved3; + + uint32_t eqadc_reserved4; + + union { + vuint16_t R; + struct { + vuint16_t:3; + vuint16_t CFEE0:1; + vuint16_t STRME0:1; + vuint16_t SSE:1; + vuint16_t CFINV:1; + vuint16_t:1; + vuint16_t MODE:4; + vuint16_t AMODE0:4; /* CFIFO0 only */ + } B; + } CFCR[6]; /* CFIFO Control Registers EQADC_CFCR */ + + uint32_t eqadc_reserved5; + + union { + vuint16_t R; + struct { + vuint16_t NCIE:1; + vuint16_t TORIE:1; + vuint16_t PIE:1; + vuint16_t EOQIE:1; + vuint16_t CFUIE:1; + vuint16_t:1; + vuint16_t CFFE:1; + vuint16_t CFFS:1; + vuint16_t:4; + vuint16_t RFOIE:1; + vuint16_t:1; + vuint16_t RFDE:1; + vuint16_t RFDS:1; + } B; + } IDCR[6]; /* Interrupt and DMA Control Registers EQADC_IDCR */ + + uint32_t eqadc_reserved6; + + union { + vuint32_t R; + struct { + vuint32_t NCF:1; + vuint32_t TORF:1; + vuint32_t PF:1; + vuint32_t EOQF:1; + vuint32_t CFUF:1; + vuint32_t SSS:1; + vuint32_t CFFF:1; + vuint32_t:5; + vuint32_t RFOF:1; + vuint32_t:1; + vuint32_t RFDF:1; + vuint32_t:1; + vuint32_t CFCTR:4; + vuint32_t TNXTPTR:4; + vuint32_t RFCTR:4; + vuint32_t POPNXTPTR:4; + } B; + } FISR[6]; /* FIFO and Interrupt Status Registers EQADC_FISR */ + + uint32_t eqadc_reserved7; + + uint32_t eqadc_reserved8; + + union { + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t TCCF:11; /* TC_CF */ + } B; + } CFTCR[6]; /* CFIFO Transfer Counter Registers EQADC_CFTCR */ + + uint32_t eqadc_reserved9; + + union { + vuint32_t R; + struct { + vuint32_t CFS0:2; /* CFS0_TCB0 */ + vuint32_t CFS1:2; /* CFS1_TCB0 */ + vuint32_t CFS2:2; /* CFS2_TCB0 */ + vuint32_t CFS3:2; /* CFS3_TCB0 */ + vuint32_t CFS4:2; /* CFS4_TCB0 */ + vuint32_t CFS5:2; /* CFS5_TCB0 */ + vuint32_t:5; + vuint32_t LCFTCB0:4; + vuint32_t TC_LCFTCB0:11; + } B; + } CFSSR0; /* CFIFO Status Register 0 EQADC_CFSSR0 */ + + union { + vuint32_t R; + struct { + vuint32_t CFS0:2; /* CFS0_TCB1 */ + vuint32_t CFS1:2; /* CFS1_TCB1 */ + vuint32_t CFS2:2; /* CFS2_TCB1 */ + vuint32_t CFS3:2; /* CFS3_TCB1 */ + vuint32_t CFS4:2; /* CFS4_TCB1 */ + vuint32_t CFS5:2; /* CFS5_TCB1 */ + vuint32_t:5; + vuint32_t LCFTCB1:4; + vuint32_t TC_LCFTCB1:11; + } B; + } CFSSR1; /* CFIFO Status Register 1 EQADC_CFSSR1 */ + + union { + vuint32_t R; + struct { + vuint32_t CFS0:2; /* CFS0_TSSI */ + vuint32_t CFS1:2; /* CFS1_TSSI */ + vuint32_t CFS2:2; /* CFS2_TSSI */ + vuint32_t CFS3:2; /* CFS3_TSSI */ + vuint32_t CFS4:2; /* CFS4_TSSI */ + vuint32_t CFS5:2; /* CFS5_TSSI */ + vuint32_t:4; + vuint32_t ECBNI:1; + vuint32_t LCFTSSI:4; + vuint32_t TC_LCFTSSI:11; + } B; + } CFSSR2; /* CFIFO Status Register 2 EQADC_CFSSR2 */ + + union { + vuint32_t R; + struct { + vuint32_t CFS0:2; + vuint32_t CFS1:2; + vuint32_t CFS2:2; + vuint32_t CFS3:2; + vuint32_t CFS4:2; + vuint32_t CFS5:2; + vuint32_t:20; + } B; + } CFSR; /* EQADC_CFSR */ + + uint32_t eqadc_reserved11; + + union { + vuint32_t R; + struct { + vuint32_t:21; + vuint32_t MDT:3; + vuint32_t:4; + vuint32_t BR:4; + } B; + } SSICR; /* SSI Control Register EQADC_SSICR */ + + union { + vuint32_t R; + struct { + vuint32_t RDV:1; + vuint32_t:5; + vuint32_t RDATA:26; + } B; + } SSIRDR; /* SSI Recieve Data Register EQADC_SSIRDR @ baseaddress + 0xB8 */ + + uint32_t eqadc_reserved11b[5]; + + uint32_t eqadc_reserved15; /* EQADC Red Line Client Configuration Register @ baseaddress + 0xD0 */ + /* REDLCCR is not implemented in the MPC563xM */ + + uint32_t eqadc_reserved12[11]; + + struct { + union { + vuint32_t R; + + /*B.CFIFOx_DATAw */ + + } R[4]; /*EQADC_CFxRw */ + + union { + vuint32_t R; + /*B.CFIFOx_EDATAw */ + } EDATA[4]; /*EQADC_CFxERw (new in MPC563xM) */ + + uint32_t eqadc_reserved13[8]; + + } CF[6]; + + uint32_t eqadc_reserved14[32]; + + struct { + union { + vuint32_t R; + /*RFIFOx_DATAw */ + } R[4]; /*EQADC_RFxRw */ + + uint32_t eqadc_reserved15[12]; + + } RF[6]; + + }; + /****************************************************************************/ +/* MODULE : DSPI */ +/****************************************************************************/ + struct DSPI_tag { + union { + vuint32_t R; + struct { + vuint32_t MSTR:1; + vuint32_t CONT_SCKE:1; + vuint32_t DCONF:2; + vuint32_t FRZ:1; + vuint32_t MTFE:1; + vuint32_t PCSSE:1; + vuint32_t ROOE:1; + vuint32_t PCSIS7:1; /* new in MPC563xM */ + vuint32_t PCSIS6:1; /* new in MPC563xM */ + vuint32_t PCSIS5:1; + vuint32_t PCSIS4:1; + vuint32_t PCSIS3:1; + vuint32_t PCSIS2:1; + vuint32_t PCSIS1:1; + vuint32_t PCSIS0:1; + vuint32_t DOZE:1; + vuint32_t MDIS:1; + vuint32_t DIS_TXF:1; + vuint32_t DIS_RXF:1; + vuint32_t CLR_TXF:1; + vuint32_t CLR_RXF:1; + vuint32_t SMPL_PT:2; + vuint32_t:7; + vuint32_t HALT:1; + } B; + } MCR; /* Module Configuration Register DSPI_MCR @baseaddress + 0x00 */ + + uint32_t dspi_reserved1; + + union { + vuint32_t R; + struct { + vuint32_t TCNT:16; /* SPI_TCNT */ + vuint32_t:16; + } B; + } TCR; /* DSPI Transfer Count Register DSPI_TCR @baseaddress + 0x08 */ + + union { + vuint32_t R; + struct { + vuint32_t DBR:1; + vuint32_t FMSZ:4; + vuint32_t CPOL:1; + vuint32_t CPHA:1; + vuint32_t LSBFE:1; + vuint32_t PCSSCK:2; + vuint32_t PASC:2; + vuint32_t PDT:2; + vuint32_t PBR:2; + vuint32_t CSSCK:4; + vuint32_t ASC:4; + vuint32_t DT:4; + vuint32_t BR:4; + } B; + } CTAR[8]; /* Clock and Transfer Attributes Registers DSPI_CTARx @baseaddress + 0x0C - 0x28 */ + + union { + vuint32_t R; + struct { + vuint32_t TCF:1; + vuint32_t TXRXS:1; + vuint32_t:1; + vuint32_t EOQF:1; + vuint32_t TFUF:1; + vuint32_t:1; + vuint32_t TFFF:1; + vuint32_t:5; + vuint32_t RFOF:1; + vuint32_t:1; + vuint32_t RFDF:1; + vuint32_t:1; + vuint32_t TXCTR:4; + vuint32_t TXNXTPTR:4; + vuint32_t RXCTR:4; + vuint32_t POPNXTPTR:4; + } B; + } SR; /* Status Register DSPI_SR @baseaddress + 0x2C */ + + union { + vuint32_t R; + struct { + vuint32_t TCFRE:1; /*TCF_RE */ + vuint32_t:2; + vuint32_t EOQFRE:1; /*EQQF_RE */ + vuint32_t TFUFRE:1; /*TFUF_RE */ + vuint32_t:1; + vuint32_t TFFFRE:1; /*TFFF_RE */ + vuint32_t TFFFDIRS:1; /*TFFF_DIRS */ + vuint32_t:4; + vuint32_t RFOFRE:1; /*RFOF_RE */ + vuint32_t:1; + vuint32_t RFDFRE:1; /*RFDF_RE */ + vuint32_t RFDFDIRS:1; /*RFDF_DIRS */ + vuint32_t:16; + } B; + } RSER; /* DMA/Interrupt Request Select and Enable Register DSPI_RSER @baseaddress + 0x30 */ + + union { + vuint32_t R; + struct { + vuint32_t CONT:1; + vuint32_t CTAS:3; + vuint32_t EOQ:1; + vuint32_t CTCNT:1; + vuint32_t:2; + vuint32_t PCS7:1; /* new in MPC563xM */ + vuint32_t PCS6:1; /* new in MPC563xM */ + vuint32_t PCS5:1; + vuint32_t PCS4:1; + vuint32_t PCS3:1; + vuint32_t PCS2:1; + vuint32_t PCS1:1; + vuint32_t PCS0:1; + vuint32_t TXDATA:16; + } B; + } PUSHR; /* PUSH TX FIFO Register DSPI_PUSHR @baseaddress + 0x34 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXDATA:16; + } B; + } POPR; /* POP RX FIFO Register DSPI_POPR @baseaddress + 0x38 */ + + union { + vuint32_t R; + struct { + vuint32_t TXCMD:16; + vuint32_t TXDATA:16; + } B; + } TXFR[4]; /* Transmit FIFO Registers DSPI_TXFRx @baseaddress + 0x3c - 0x78 */ + + vuint32_t DSPI_reserved_txf[12]; + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXDATA:16; + } B; + } RXFR[4]; /* Transmit FIFO Registers DSPI_RXFRx @baseaddress + 0x7c - 0xB8 */ + + vuint32_t DSPI_reserved_rxf[12]; + + union { + vuint32_t R; + struct { + vuint32_t MTOE:1; + vuint32_t:1; + vuint32_t MTOCNT:6; + vuint32_t:3; + vuint32_t TSBC:1; + vuint32_t TXSS:1; + vuint32_t TPOL:1; + vuint32_t TRRE:1; + vuint32_t CID:1; + vuint32_t DCONT:1; + vuint32_t DSICTAS:3; + vuint32_t:4; + vuint32_t DPCS7:1; + vuint32_t DPCS6:1; + vuint32_t DPCS5:1; + vuint32_t DPCS4:1; + vuint32_t DPCS3:1; + vuint32_t DPCS2:1; + vuint32_t DPCS1:1; + vuint32_t DPCS0:1; + } B; + } DSICR; /* DSI Configuration Register DSPI_DSICR @baseaddress + 0xBC */ + + union { + vuint32_t R; + struct { + vuint32_t SER_DATA:32; /* 32bit instead of 16 in MPC563xM */ + } B; + } SDR; /* DSI Serialization Data Register DSPI_SDR @baseaddress + 0xC0 */ + + union { + vuint32_t R; + struct { + vuint32_t ASER_DATA:32; /* 32bit instead of 16 in MPC563xM */ + } B; + } ASDR; /* DSI Alternate Serialization Data Register DSPI_ASDR @baseaddress + 0xC4 */ + + union { + vuint32_t R; + struct { + vuint32_t COMP_DATA:32; /* 32bit instead of 16 in MPC563xM */ + } B; + } COMPR; /* DSI Transmit Comparison Register DSPI_COMPR @baseaddress + 0xC8 */ + + union { + vuint32_t R; + struct { + vuint32_t DESER_DATA:32; /* 32bit instead of 16 in MPC563xM */ + } B; + } DDR; /* DSI deserialization Data Register DSPI_DDR @baseaddress + 0xCC */ + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t TSBCNT:5; + vuint32_t:16; + vuint32_t DPCS1_7:1; + vuint32_t DPCS1_6:1; + vuint32_t DPCS1_5:1; + vuint32_t DPCS1_4:1; + vuint32_t DPCS1_3:1; + vuint32_t DPCS1_2:1; + vuint32_t DPCS1_1:1; + vuint32_t DPCS1_0:1; + } B; + } DSICR1; /* DSI Configuration Register 1 DSPI_DSICR1 @baseaddress + 0xD0 */ + + }; +/****************************************************************************/ +/* MODULE : eSCI */ +/****************************************************************************/ + struct ESCI_tag { + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t SBR:13; + vuint32_t LOOPS:1; + vuint32_t:1; /* Reserved in MPC563xM */ + vuint32_t RSRC:1; + vuint32_t M:1; + vuint32_t WAKE:1; + vuint32_t ILT:1; + vuint32_t PE:1; + vuint32_t PT:1; + vuint32_t TIE:1; + vuint32_t TCIE:1; + vuint32_t RIE:1; + vuint32_t ILIE:1; + vuint32_t TE:1; + vuint32_t RE:1; + vuint32_t RWU:1; + vuint32_t SBK:1; + } B; + } CR1; /* Control Register 1 SCIBDH, SCIBDL, SCICR1, SCICR2 @baseaddress + 0x00 */ + + union { + vuint16_t R; + struct { + vuint16_t MDIS:1; + vuint16_t FBR:1; + vuint16_t BSTP:1; + vuint16_t IEBERR:1; /* BERIE */ + vuint16_t RXDMA:1; + vuint16_t TXDMA:1; + vuint16_t BRK13:1; /* BRCL */ + vuint16_t TXDIR:1; + vuint16_t BESM13:1; /* BESM */ + vuint16_t SBSTP:1; /* BESTP */ + vuint16_t RXPOL:1; + vuint16_t PMSK:1; + vuint16_t ORIE:1; + vuint16_t NFIE:1; + vuint16_t FEIE:1; + vuint16_t PFIE:1; + } B; + } CR2; /* Control Register 2 SCICR3, SCICR4 @baseaddress + 0x04 */ + + union { + vuint16_t R; + struct { + vuint16_t R8:1; /* RN */ + vuint16_t T8:1; /* TN */ + vuint16_t ERR:1; + vuint16_t:1; + vuint16_t R:4; + vuint8_t D; + } B; + } DR; /* Data Register SCIDRH, SCIDRL @baseaddress + 0x06 */ + + union { + vuint32_t R; + struct { + vuint32_t TDRE:1; + vuint32_t TC:1; + vuint32_t RDRF:1; + vuint32_t IDLE:1; + vuint32_t OR:1; + vuint32_t NF:1; + vuint32_t FE:1; + vuint32_t PF:1; + vuint32_t:3; + vuint32_t BERR:1; + vuint32_t:2; + vuint32_t TACT:1; + vuint32_t RAF:1; /* RACT */ + vuint32_t RXRDY:1; + vuint32_t TXRDY:1; + vuint32_t LWAKE:1; + vuint32_t STO:1; + vuint32_t PBERR:1; + vuint32_t CERR:1; + vuint32_t CKERR:1; + vuint32_t FRC:1; + vuint32_t:6; + vuint32_t UREQ:1; + vuint32_t OVFL:1; + } B; + } SR; /* Status Register SCISR1, SCIRSR2, LINSTAT1, LINSTAT2 @baseaddress + 0x08 */ + + union { + vuint32_t R; + struct { + vuint32_t LRES:1; + vuint32_t WU:1; + vuint32_t WUD0:1; + vuint32_t WUD1:1; + vuint32_t:2; /* reserved: LDBG and DSF not longer supported */ + vuint32_t PRTY:1; + vuint32_t LIN:1; + vuint32_t RXIE:1; + vuint32_t TXIE:1; + vuint32_t WUIE:1; + vuint32_t STIE:1; + vuint32_t PBIE:1; + vuint32_t CIE:1; + vuint32_t CKIE:1; + vuint32_t FCIE:1; + vuint32_t:6; + vuint32_t UQIE:1; + vuint32_t OFIE:1; + vuint32_t:8; + } B; + } LCR; /* LIN Control Register LINCTRL1, LINCTRL2, LINCTRL3 @baseaddress + 0x0C */ + + union { + vuint32_t R; + } LTR; /* LIN Transmit Register LINTX @baseaddress + 0x10 */ + + union { + vuint32_t R; + } LRR; /* LIN Recieve Register LINRX @baseaddress + 0x14 */ + + union { + vuint32_t R; + struct { + vuint32_t P:16; + vuint32_t:3; + vuint32_t SYNM:1; + vuint32_t EROE:1; + vuint32_t ERFE:1; + vuint32_t ERPE:1; + vuint32_t M2:1; + vuint32_t:8; + } B; + } LPR; /* LIN CRC Polynom Register LINCRCP1, LINCRCP2, SCICR5 @baseaddress + 0x18 */ + + }; +/****************************************************************************/ +/* MODULE : eSCI */ +/****************************************************************************/ + struct ESCI_12_13_bit_tag { + union { + vuint16_t R; + struct { + vuint16_t R8:1; + vuint16_t T8:1; + vuint16_t ERR:1; + vuint16_t:1; + vuint16_t D:12; + } B; + } DR; /* Data Register */ + }; +/****************************************************************************/ +/* MODULE : FlexCAN */ +/****************************************************************************/ + struct FLEXCAN_BUF_t { + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t CODE:4; + vuint32_t:1; + vuint32_t SRR:1; + vuint32_t IDE:1; + vuint32_t RTR:1; + vuint32_t LENGTH:4; + vuint32_t TIMESTAMP:16; + } B; + } CS; + + union { + vuint32_t R; + struct { + vuint32_t PRIO:3; + vuint32_t STD_ID:11; + vuint32_t EXT_ID:18; + } B; + } ID; + + union { + /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */ + /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */ + vuint32_t W[2]; /* Data buffer in words (32 bits) */ + /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */ + } DATA; + + }; /* end of FLEXCAN_BUF_t */ + + struct FLEXCAN_RXFIFO_t { + union { + vuint32_t R; + struct { + vuint32_t:9; + vuint32_t SRR:1; + vuint32_t IDE:1; + vuint32_t RTR:1; + vuint32_t LENGTH:4; + vuint32_t TIMESTAMP:16; + } B; + } CS; + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t STD_ID:11; + vuint32_t EXT_ID:18; + } B; + } ID; + + union { + /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */ + /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */ + vuint32_t W[2]; /* Data buffer in words (32 bits) */ + /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */ + } DATA; + + uint32_t FLEXCAN_RXFIFO_reserved[20]; /* {0x00E0-0x0090}/0x4 = 0x14 */ + + union { + vuint32_t R; + } IDTABLE[8]; + + }; /* end of FLEXCAN_RXFIFO_t */ + + struct FLEXCAN2_tag { + union { + vuint32_t R; + struct { + vuint32_t MDIS:1; + vuint32_t FRZ:1; + vuint32_t FEN:1; /* new in MPC563xM */ + vuint32_t HALT:1; + vuint32_t NOTRDY:1; /* NOT_RDY */ + vuint32_t WAK_MSK:1; /* new in MPC563xM */ + vuint32_t SOFTRST:1; /* SOFT_RST */ + vuint32_t FRZACK:1; /* FRZ_ACK */ + vuint32_t SUPV:1; /* new in MPC563xM */ + vuint32_t SLF_WAK:1; /* new in MPC563xM */ + + vuint32_t WRNEN:1; /* WRN_EN */ + + vuint32_t MDISACK:1; /* LPM_ACK */ + vuint32_t WAK_SRC:1; /* new in MPC563xM */ + vuint32_t DOZE:1; /* new in MPC563xM */ + + vuint32_t SRXDIS:1; /* SRX_DIS */ + vuint32_t MBFEN:1; /* BCC */ + vuint32_t:2; + + vuint32_t LPRIO_EN:1; /* new in MPC563xM */ + vuint32_t AEN:1; /* new in MPC563xM */ + vuint32_t:2; + vuint32_t IDAM:2; /* new in MPC563xM */ + vuint32_t:2; + + vuint32_t MAXMB:6; + } B; + } MCR; /* Module Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t PRESDIV:8; + vuint32_t RJW:2; + vuint32_t PSEG1:3; + vuint32_t PSEG2:3; + vuint32_t BOFFMSK:1; /* BOFF_MSK */ + vuint32_t ERRMSK:1; /* ERR_MSK */ + vuint32_t CLKSRC:1; /* CLK_SRC */ + vuint32_t LPB:1; + vuint32_t TWRNMSK:1; /* TWRN_MSK */ + vuint32_t RWRNMSK:1; /* RWRN_MSK */ + vuint32_t:2; + vuint32_t SMP:1; + vuint32_t BOFFREC:1; /* BOFF_REC */ + vuint32_t TSYN:1; + vuint32_t LBUF:1; + vuint32_t LOM:1; + vuint32_t PROPSEG:3; + } B; /* Control Register */ + } CR; /* CTRL */ + + union { + vuint32_t R; + } TIMER; /* Free Running Timer */ + + int32_t FLEXCAN_reserved00; + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t MI:29; + } B; + } RXGMASK; /* RX Global Mask */ + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t MI:29; + } B; + } RX14MASK; /* RX 14 Mask */ + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t MI:29; + } B; + } RX15MASK; /* RX 15 Mask */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXECNT:8; + vuint32_t TXECNT:8; + } B; + } ECR; /* Error Counter Register */ + + union { + vuint32_t R; + struct { + vuint32_t:14; + vuint32_t TWRNINT:1; /* TWRN_INT */ + vuint32_t RWRNINT:1; /* RWRN_INT */ + vuint32_t BIT1ERR:1; /* BIT1_ERR */ + vuint32_t BIT0ERR:1; /* BIT0_ERR */ + vuint32_t ACKERR:1; /* ACK_ERR */ + vuint32_t CRCERR:1; /* CRC_ERR */ + vuint32_t FRMERR:1; /* FRM_ERR */ + vuint32_t STFERR:1; /* STF_ERR */ + vuint32_t TXWRN:1; /* TX_WRN */ + vuint32_t RXWRN:1; /* RX_WRN */ + vuint32_t IDLE:1; + vuint32_t TXRX:1; + vuint32_t FLTCONF:2; /* FLT_CONF */ + vuint32_t:1; + vuint32_t BOFFINT:1; /* BOFF_INT */ + vuint32_t ERRINT:1; /* ERR_INT */ + vuint32_t WAK_INT:1; /* new in MPC563xM */ + } B; + } ESR; /* Error and Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t BUF63M:1; + vuint32_t BUF62M:1; + vuint32_t BUF61M:1; + vuint32_t BUF60M:1; + vuint32_t BUF59M:1; + vuint32_t BUF58M:1; + vuint32_t BUF57M:1; + vuint32_t BUF56M:1; + vuint32_t BUF55M:1; + vuint32_t BUF54M:1; + vuint32_t BUF53M:1; + vuint32_t BUF52M:1; + vuint32_t BUF51M:1; + vuint32_t BUF50M:1; + vuint32_t BUF49M:1; + vuint32_t BUF48M:1; + vuint32_t BUF47M:1; + vuint32_t BUF46M:1; + vuint32_t BUF45M:1; + vuint32_t BUF44M:1; + vuint32_t BUF43M:1; + vuint32_t BUF42M:1; + vuint32_t BUF41M:1; + vuint32_t BUF40M:1; + vuint32_t BUF39M:1; + vuint32_t BUF38M:1; + vuint32_t BUF37M:1; + vuint32_t BUF36M:1; + vuint32_t BUF35M:1; + vuint32_t BUF34M:1; + vuint32_t BUF33M:1; + vuint32_t BUF32M:1; + } B; /* Interruput Masks Register */ + } IMRH; /* IMASK2 */ + + union { + vuint32_t R; + struct { + vuint32_t BUF31M:1; + vuint32_t BUF30M:1; + vuint32_t BUF29M:1; + vuint32_t BUF28M:1; + vuint32_t BUF27M:1; + vuint32_t BUF26M:1; + vuint32_t BUF25M:1; + vuint32_t BUF24M:1; + vuint32_t BUF23M:1; + vuint32_t BUF22M:1; + vuint32_t BUF21M:1; + vuint32_t BUF20M:1; + vuint32_t BUF19M:1; + vuint32_t BUF18M:1; + vuint32_t BUF17M:1; + vuint32_t BUF16M:1; + vuint32_t BUF15M:1; + vuint32_t BUF14M:1; + vuint32_t BUF13M:1; + vuint32_t BUF12M:1; + vuint32_t BUF11M:1; + vuint32_t BUF10M:1; + vuint32_t BUF09M:1; + vuint32_t BUF08M:1; + vuint32_t BUF07M:1; + vuint32_t BUF06M:1; + vuint32_t BUF05M:1; + vuint32_t BUF04M:1; + vuint32_t BUF03M:1; + vuint32_t BUF02M:1; + vuint32_t BUF01M:1; + vuint32_t BUF00M:1; + } B; /* Interruput Masks Register */ + } IMRL; /* IMASK1 */ + + union { + vuint32_t R; + struct { + vuint32_t BUF63I:1; + vuint32_t BUF62I:1; + vuint32_t BUF61I:1; + vuint32_t BUF60I:1; + vuint32_t BUF59I:1; + vuint32_t BUF58I:1; + vuint32_t BUF57I:1; + vuint32_t BUF56I:1; + vuint32_t BUF55I:1; + vuint32_t BUF54I:1; + vuint32_t BUF53I:1; + vuint32_t BUF52I:1; + vuint32_t BUF51I:1; + vuint32_t BUF50I:1; + vuint32_t BUF49I:1; + vuint32_t BUF48I:1; + vuint32_t BUF47I:1; + vuint32_t BUF46I:1; + vuint32_t BUF45I:1; + vuint32_t BUF44I:1; + vuint32_t BUF43I:1; + vuint32_t BUF42I:1; + vuint32_t BUF41I:1; + vuint32_t BUF40I:1; + vuint32_t BUF39I:1; + vuint32_t BUF38I:1; + vuint32_t BUF37I:1; + vuint32_t BUF36I:1; + vuint32_t BUF35I:1; + vuint32_t BUF34I:1; + vuint32_t BUF33I:1; + vuint32_t BUF32I:1; + } B; /* Interruput Flag Register */ + } IFRH; /* IFLAG2 */ + + union { + vuint32_t R; + struct { + vuint32_t BUF31I:1; + vuint32_t BUF30I:1; + vuint32_t BUF29I:1; + vuint32_t BUF28I:1; + vuint32_t BUF27I:1; + vuint32_t BUF26I:1; + vuint32_t BUF25I:1; + vuint32_t BUF24I:1; + vuint32_t BUF23I:1; + vuint32_t BUF22I:1; + vuint32_t BUF21I:1; + vuint32_t BUF20I:1; + vuint32_t BUF19I:1; + vuint32_t BUF18I:1; + vuint32_t BUF17I:1; + vuint32_t BUF16I:1; + vuint32_t BUF15I:1; + vuint32_t BUF14I:1; + vuint32_t BUF13I:1; + vuint32_t BUF12I:1; + vuint32_t BUF11I:1; + vuint32_t BUF10I:1; + vuint32_t BUF09I:1; + vuint32_t BUF08I:1; + vuint32_t BUF07I:1; + vuint32_t BUF06I:1; + vuint32_t BUF05I:1; + vuint32_t BUF04I:1; + vuint32_t BUF03I:1; + vuint32_t BUF02I:1; + vuint32_t BUF01I:1; + vuint32_t BUF00I:1; + } B; /* Interruput Flag Register */ + } IFRL; /* IFLAG1 */ + + uint32_t flexcan2_reserved2[19]; + +/****************************************************************************/ +/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */ +/****************************************************************************/ + /* Standard Buffer Structure */ + struct FLEXCAN_BUF_t BUF[64]; + + /* RX FIFO and Buffer Structure *//* New options in MPC563xM */ + /*struct FLEXCAN_RXFIFO_t RXFIFO; */ + /*struct FLEXCAN_BUF_t BUF[56]; */ +/****************************************************************************/ + + uint32_t FLEXCAN_reserved3[256]; /* {0x0880-0x0480}/0x4 = 0x100 *//* (New in MPC563xM) Address Base + 0x0034 */ + + union { + vuint32_t R; + struct { + vuint32_t MI:32; + } B; /* RX Individual Mask Registers */ + } RXIMR[64]; /* (New in MPC563xM) Address Base + 0x0880 */ + + }; /* end of FLEXCAN_tag */ +/****************************************************************************/ +/* MODULE : Decimation Filter (DECFIL) */ +/****************************************************************************/ + struct DECFIL_tag { + union { + vuint32_t R; + struct { + vuint32_t MDIS:1; + vuint32_t FREN:1; + vuint32_t:1; + vuint32_t FRZ:1; + vuint32_t SRES:1; + vuint32_t:2; /* CASCD not supported in MPC563xM */ + vuint32_t IDEN:1; + vuint32_t ODEN:1; + vuint32_t ERREN:1; + vuint32_t:1; + vuint32_t FTYPE:2; + vuint32_t:1; + vuint32_t SCAL:2; + vuint32_t:1; + vuint32_t SAT:1; + vuint32_t ISEL:1; + vuint32_t:1; /* MIXM does not appear to be implemented on the MPC563xM */ + vuint32_t DEC_RATE:4; + vuint32_t:1; /* SDIE not supported in MPC563xM */ + vuint32_t DSEL:1; + vuint32_t IBIE:1; + vuint32_t OBIE:1; + vuint32_t EDME:1; + vuint32_t TORE:1; + vuint32_t TMODE:2; /* the LSB of TMODE is always 0 on the MPC563xM */ + } B; + } MCR; /* Configuration Register DECFILTER_MCR @baseaddress + 0x00 */ + + union { + vuint32_t R; + struct { + vuint32_t BSY:1; + vuint32_t:1; + vuint32_t DEC_COUNTER:4; + vuint32_t IDFC:1; + vuint32_t ODFC:1; + vuint32_t SDFC:1; /* SDFC not supported in MPC563xM */ + vuint32_t IBIC:1; + vuint32_t OBIC:1; + vuint32_t SVRC:1; /* SVRC not supported in MPC563xM */ + vuint32_t DIVRC:1; + vuint32_t OVFC:1; + vuint32_t OVRC:1; + vuint32_t IVRC:1; + vuint32_t:6; + vuint32_t IDF:1; + vuint32_t ODF:1; + vuint32_t SDF:1; /* SDF not supported in MPC563xM */ + vuint32_t IBIF:1; + vuint32_t OBIF:1; + vuint32_t SVR:1; /* SVR not supported in MPC563xM */ + vuint32_t DIVR:1; + vuint32_t OVF:1; + vuint32_t OVR:1; + vuint32_t IVR:1; + } B; + } MSR; /* Status Register DECFILTER_MSR @baseaddress + 0x04 */ + + /* Module Extended Config.Register - not siupported on the MPC563xM DECFILTER_MXCR @baseaddress + 0x08 */ + + uint32_t decfil_reserved1[2]; + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t INTAG:4; + vuint32_t:6; + vuint32_t PREFILL:1; + vuint32_t FLUSH:1; + vuint32_t INPBUF:16; + } B; + } IB; /* Interface Input Buffer DECFILTER_IB @baseaddress + 0x10 */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t OUTTAG:4; + vuint32_t OUTBUF:16; + } B; + } OB; /* Interface Output Buffer DECFILTER_OB @baseaddress + 0x14 */ + + uint32_t decfil_reserved2[2]; + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t COEF:24; + } B; + } COEF[9]; /* Filter Coefficient Registers DECFILTER_COEFx @baseaddress + 0x20 - 0x40 */ + + uint32_t decfil_reserved3[13]; + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t TAP:24; + } B; + } TAP[8]; /* Filter TAP Registers DECFILTER_TAPx @baseaddress + 0x78 - 0x94 */ + + uint32_t decfil_reserved4[14]; + + /* 0x0D0 */ + union { + vuint16_t R; + struct { + vuint32_t:16; + vuint32_t SAMP_DATA:16; + } B; + } EDID; /* Filter EDID Registers DECFILTER_EDID @baseaddress + 0xD0 */ + + uint32_t decfil_reserved5[3]; + + /* 0x0E0 */ + uint32_t decfil_reserved6; + /* Filter FINTVAL Registers - Not supported on MPC563xM DECFILTER_FINTVAL @baseaddress + 0xE0 */ + + /* 0x0E4 */ + uint32_t decfil_reserved7; + /* Filter FINTCNT Registers - Not supported on MPC563xM DECFILTER_FINTCNT @baseaddress + 0xE4 */ + + /* 0x0E8 */ + uint32_t decfil_reserved8; + /* Filter CINTVAL Registers - Not supported on MPC563xM DECFILTER_CINTVAL @baseaddress + 0xE8 */ + + /* 0x0EC */ + uint32_t decfil_reserved9; + /* Filter CINTCNT Registers - Not supported on MPC563xM DECFILTER_CINTCNT @baseaddress + 0xEC */ + + }; +/****************************************************************************/ +/* MODULE : Periodic Interval Timer (PIT) */ +/****************************************************************************/ + struct PIT_tag { + + union { + vuint32_t R; + struct { + vuint32_t:29; + vuint32_t MDIS_RTI:1; + vuint32_t MDIS:1; + vuint32_t FRZ:1; + } B; + } PITMCR; /* PIT Module Control Register */ + + uint32_t pit_reserved1[59]; + + struct { + union { + vuint32_t R; /* TSVn */ + } LDVAL; /* Timer Load Value Register */ + + union { + vuint32_t R; /* TVLn */ + } CVAL; /* Current Timer Value Register */ + + union { + vuint32_t R; + struct { + vuint32_t:30; + vuint32_t TIE:1; + vuint32_t TEN:1; + } B; + } TCTRL; /* Timer Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t TIF:1; + } B; + } TFLG; /* Timer Flag Register */ + } RTI; /* RTI Channel */ + + struct { + union { + vuint32_t R; + } LDVAL; /* Timer Load Value Register */ + + union { + vuint32_t R; + } CVAL; /* Current Timer Value Register */ + + union { + vuint32_t R; + struct { + vuint32_t:30; + vuint32_t TIE:1; + vuint32_t TEN:1; + } B; + } TCTRL; /* Timer Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t TIF:1; + } B; + } TFLG; /* Timer Flag Register */ + } TIMER[4]; /* Timer Channels */ + + }; +/****************************************************************************/ +/* MODULE : System Timer Module (STM) */ +/****************************************************************************/ + struct STM_tag { + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t CPS:8; + vuint32_t:6; + vuint32_t FRZ:1; + vuint32_t TEN:1; + } B; + } CR; /* STM Control Register STM_CR (new in MPC563xM) Offset 0x0000 */ + + union { + vuint32_t R; + } CNT; /* STM Count Register STM_CNT (new in MPC563xM) Offset Offset 0x0004 */ + + uint32_t stm_reserved1[2]; /* Reserved (new in MPC563xM) Offset Offset 0x0008 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR0; /* STM Channel Control Register STM_CCR0 (new in MPC563xM) Offset 0x0010 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR0; /* STM Channel Interrupt Register STM_CIR0 (new in MPC563xM) Offset 0x0014 */ + + union { + vuint32_t R; + } CMP0; /* STM Channel Compare Register STM_CMP0 (new in MPC563xM) Offset Offset 0x0018 */ + + uint32_t stm_reserved2; /* Reserved (new in MPC563xM) Offset Offset 0x001C */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR1; /* STM Channel Control Register STM_CCR1 (new in MPC563xM) Offset 0x0020 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR1; /* STM Channel Interrupt Register STM_CIR1 (new in MPC563xM) Offset 0x0024 */ + + union { + vuint32_t R; + } CMP1; /* STM Channel Compare Register STM_CMP1 (new in MPC563xM) Offset Offset 0x0028 */ + + uint32_t stm_reserved3; /* Reserved (new in MPC563xM) Offset Offset 0x002C */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR2; /* STM Channel Control Register STM_CCR2 (new in MPC563xM) Offset 0x0030 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR2; /* STM Channel Interrupt Register STM_CIR2 (new in MPC563xM) Offset 0x0034 */ + + union { + vuint32_t R; + } CMP2; /* STM Channel Compare Register STM_CMP2 (new in MPC563xM) Offset Offset 0x0038 */ + + uint32_t stm_reserved4; /* Reserved (new in MPC563xM) Offset Offset 0x003C */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR3; /* STM Channel Control Register STM_CCR3 (new in MPC563xM) Offset 0x0040 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR3; /* STM Channel Interrupt Register STM_CIR3 (new in MPC563xM) Offset 0x0044 */ + + union { + vuint32_t R; + } CMP3; /* STM Channel Compare Register STM_CMP3 (new in MPC563xM) Offset Offset 0x0048 */ + + uint32_t stm_reserved5; /* Reserved (new in MPC563xM) Offset Offset 0x004C */ + }; + +/****************************************************************************/ +/* MODULE : SWT */ +/****************************************************************************/ + + struct SWT_tag { + union { + vuint32_t R; + struct { + vuint32_t MAP0:1; + vuint32_t MAP1:1; + vuint32_t MAP2:1; + vuint32_t MAP3:1; + vuint32_t MAP4:1; + vuint32_t MAP5:1; + vuint32_t MAP6:1; + vuint32_t MAP7:1; + vuint32_t:14; + vuint32_t KEY:1; + vuint32_t RIA:1; + vuint32_t WND:1; + vuint32_t ITR:1; + vuint32_t HLK:1; + vuint32_t SLK:1; + vuint32_t CSL:1; + vuint32_t STP:1; + vuint32_t FRZ:1; + vuint32_t WEN:1; + } B; + } MCR; /*SWT_CR *//* Module Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t TIF:1; + } B; + } IR; /* Interrupt register SWT_IR */ + + union { + vuint32_t R; + struct { + vuint32_t WTO:32; + } B; + } TO; /* Timeout register SWT_TO */ + + union { + vuint32_t R; + struct { + vuint32_t WST:32; + + } B; + } WN; /* Window register SWT_WN */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t WSC:16; + } B; + } SR; /* Service register SWT_SR */ + + union { + vuint32_t R; + struct { + vuint32_t CNT:32; + } B; + } CO; /* Counter output register SWT_CO */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t SK:16; + } B; + } SK; /* Service key register SWT_SK */ + }; +/****************************************************************************/ +/* MODULE : Power Management Controller (PMC) */ +/****************************************************************************/ + struct PMC_tag { + union { + vuint32_t R; + struct { + vuint32_t LVRER:1; /* LVIRR */ + vuint32_t LVREH:1; /* LVIHR */ + vuint32_t LVRE50:1; /* LVI5R */ + vuint32_t LVRE33:1; /* LVI3R */ + vuint32_t LVREC:1; /* LVI1R */ + vuint32_t:3; + vuint32_t LVIER:1; /* LVIRE */ + vuint32_t LVIEH:1; /* LVIHE */ + vuint32_t LVIE50:1; /* LVI5E */ + vuint32_t LVIE33:1; /* LVI3E */ + vuint32_t LVIC:1; /* LVI1E */ + vuint32_t:2; + vuint32_t TLK:1; + vuint32_t:16; + } B; + } MCR; /* Module Configuration register CFGR */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t LVDREGTRIM:4; /* LVI50TRIM */ + vuint32_t VDD33TRIM:4; /* BV33TRIM */ + vuint32_t LVD33TRIM:4; /* LVI33TRIM */ + vuint32_t VDDCTRIM:4; /* V12TRIM */ + vuint32_t LVDCTRIM:4; /* LVI33TRIM */ + } B; + } TRIMR; /* Trimming register */ + + union { + vuint32_t R; + struct { + vuint32_t:5; + vuint32_t LVFVSTBY:1; + vuint32_t BGRDY:1; /* BGS1 */ + vuint32_t BGTS:1; /* BGS2 */ + vuint32_t:5; + vuint32_t LVFCSTBY:1; + vuint32_t:1; + vuint32_t V33DIS:1; /* 3.3V Regulator Disable V33S */ + vuint32_t LVFCR:1; /* Clear LVFR LVIRC */ + vuint32_t LVFCH:1; /* Clear LVFH LVIHC */ + vuint32_t LVFC50:1; /* Clear LVF5 LVI5 */ + vuint32_t LVFC33:1; /* Clear LVF3 LVI3 */ + vuint32_t LVFCC:1; /* Clear LVFC LVI1 */ + vuint32_t:3; + vuint32_t LVFR:1; /* Low Voltage Flag Reset Supply LVIRF */ + vuint32_t LVFH:1; /* Low Voltage Flag VDDEH Supply LVIHF */ + vuint32_t LVF50:1; /* Low Voltage Flag 5V Supply LVI5F */ + vuint32_t LVF33:1; /* Low Voltage Flag 3.3V Supply LVI3F */ + vuint32_t LVFC:1; /* Low Voltage Flag Core (1.2V) LVI1F */ + vuint32_t:3; + + } B; + } SR; /* status register */ + }; +/****************************************************************************/ +/* MODULE : TSENS (Temperature Sensor) */ +/****************************************************************************/ + + struct TSENS_tag { + + union { + vuint32_t R; + struct { + vuint32_t TSCV2:16; + vuint32_t TSCV1:16; + } B; + } TCCR0; /* Temperature Sensor Calibration B @baseaddress + 0x00 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t TSCV3:16; + } B; + } TCCR1; /* Temperature Sensor Calibration A @baseaddress + 0x04 */ + + uint32_t TSENS_reserved0008[16382]; /* 0x0008-0xFFFF */ + + }; + +/* Define memories */ +/* Comments need to be moved for different memory sizes */ + +#define SRAM_START 0x40000000 + /*#define SRAM_SIZE 0xC000 48K SRAM */ + /*#define SRAM_SIZE 0x10000 64K SRAM */ +#define SRAM_SIZE 0x17800 /* 94K SRAM */ + /*#define SRAM_END 0x4000BFFF 48K SRAM */ + /*#define SRAM_END 0x4000FFFF 64K SRAM */ +#define SRAM_END 0x400177FF /* 94K SRAM */ + +#define FLASH_START 0x0 + /*#define FLASH_SIZE 0x100000 1M Flash */ +#define FLASH_SIZE 0x180000 /* 1.5M Flash */ + /*#define FLASH_END 0xFFFFF 1M Flash */ +#define FLASH_END 0x17FFFF /* 1.5M Flash */ + +/* Shadow Flash start and end address */ +#define FLASH_SHADOW_START 0x00FFC000 +#define FLASH_SHADOW_SIZE 0x4000 +#define FLASH_SHADOW_END 0x00FFFFFF + +/* Define instances of modules */ +#define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000) +#define EBI (*( volatile struct EBI_tag *) 0xC3F84000) +#define CFLASH0 (*( volatile struct FLASH_tag *) 0xC3F88000) +#define CFLASH1 (*( volatile struct FLASH_tag *) 0xC3FB0000) +#define CFLASH2 (*( volatile struct FLASH_tag *) 0xC3FB4000) +#define SIU (*( volatile struct SIU_tag *) 0xC3F90000) + +#define EMIOS (*( volatile struct EMIOS_tag *) 0xC3FA0000) +#define PMC (*( volatile struct PMC_tag *) 0xC3FBC000) +#define ETPU (*( volatile struct ETPU_tag *) 0xC3FC0000) +#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000) +#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000) +#define ETPU_DATA_RAM_END 0xC3FC8BFC +#define CODE_RAM (*( uint32_t *) 0xC3FD0000) +#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000) +#define PIT (*( volatile struct PIT_tag *) 0xC3FF0000) + +#define XBAR (*( volatile struct XBAR_tag *) 0xFFF04000) +#define SWT (*( volatile struct SWT_tag *) 0xFFF38000) +#define STM (*( volatile struct STM_tag *) 0xFFF3C000) +#define ECSM (*( volatile struct ECSM_tag *) 0xFFF40000) +#define EDMA (*( volatile struct EDMA_tag *) 0xFFF44000) +#define INTC (*( volatile struct INTC_tag *) 0xFFF48000) + +#define EQADC (*( volatile struct EQADC_tag *) 0xFFF80000) +#define DECFIL (*( volatile struct DECFIL_tag *) 0xFFF88000) + +#define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000) +#define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000) + +#define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFB0000) +#define ESCI_A_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB0006) +#define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFB4000) +#define ESCI_B_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB4006) + +#define CAN_A (*( volatile struct FLEXCAN2_tag *) 0xFFFC0000) +#define CAN_C (*( volatile struct FLEXCAN2_tag *) 0xFFFC8000) + +#define TSENS (*( volatile struct TSENS_tag *) 0xFFFEC000) + +#ifdef __MWERKS__ +#pragma pop +#endif /* + */ + +#ifdef __cplusplus +} +#endif /* + */ + +#endif /* ifdef _MPC563M_H */ +/********************************************************************* + * + * Copyright: + * Freescale Semiconductor, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Freescale + * Semiconductor, Inc. This software is provided on an "AS IS" + * basis and without warranty. + * + * To the maximum extent permitted by applicable law, Freescale + * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, + * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A + * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH + * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) + * AND ANY ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, + * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER + * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Freescale Semiconductor assumes no responsibility for the + * maintenance and support of this software + * + ********************************************************************/ + diff --git a/Project/os/hal/platforms/SPC56x/platform.dox b/Project/os/hal/platforms/SPC56x/platform.dox new file mode 100644 index 0000000..f9d5a8f --- /dev/null +++ b/Project/os/hal/platforms/SPC56x/platform.dox @@ -0,0 +1,77 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup SPC563 SPC563Mx Drivers + * @details This section describes all the supported drivers on the + * SPC563Mx/MPC563xM platform and the implementation details + * of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup SPC563_HAL SPC563Mx Initialization Support + * @details The SPC563Mx/MPC563xM HAL support is responsible for system + * initialization. + * + * @section spc563_hal_1 Supported HW resources + * - FMPLL. + * - INTC. + * - XBAR. + * - CFLASH0. + * . + * @section spc563_hal_2 SPC563Mx HAL driver implementation features + * - FMPLL startup and stabilization. + * - Clock tree initialization. + * - Clock source selection. + * - Flash wait states initialization based on the selected clock options. + * - SYSTICK initialization based on current clock and kernel required rate. + * - DMA support initialization. + * . + * @ingroup SPC563 + */ + +/** + * @defgroup SPC563_SERIAL SPC563Mx Serial Support + * @details The SPC563Mx/MPC563xM Serial driver uses the ESCI peripherals + * in a buffered, interrupt driven, implementation. + * + * @section spc563_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - ESCIA. + * - ESCIB. + * . + * @section spc563_serial_2 SPC563Mx Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each ESCI can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * - Programmable priority levels for each ESCI. + * . + * @ingroup SPC563 + */ diff --git a/Project/os/hal/platforms/SPC56x/platform.mk b/Project/os/hal/platforms/SPC56x/platform.mk new file mode 100644 index 0000000..6069e7d --- /dev/null +++ b/Project/os/hal/platforms/SPC56x/platform.mk @@ -0,0 +1,6 @@ +# List of all the SPC56x platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC56x/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC56x/serial_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC56x diff --git a/Project/os/hal/platforms/SPC56x/serial_lld.c b/Project/os/hal/platforms/SPC56x/serial_lld.c new file mode 100644 index 0000000..3b2af88 --- /dev/null +++ b/Project/os/hal/platforms/SPC56x/serial_lld.c @@ -0,0 +1,301 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file SPC56x/serial_lld.c + * @brief SPC563 low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief eSCI-A serial driver identifier. + */ +#if USE_SPC563_ESCIA || defined(__DOXYGEN__) +SerialDriver SD1; +#endif + +/** + * @brief eSCI-B serial driver identifier. + */ +#if USE_SPC563_ESCIB || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** + * @brief Driver default configuration. + */ +static const SerialConfig default_config = { + SERIAL_DEFAULT_BITRATE, + SD_MODE_NORMAL | SD_MODE_PARITY_NONE +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief eSCI initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration + */ +static void esci_init(SerialDriver *sdp, const SerialConfig *config) { + volatile struct ESCI_tag *escip = sdp->escip; + uint8_t mode = config->sc_mode; + + escip->CR2.R = 0; /* MDIS off. */ + escip->CR1.R = 0; + escip->LCR.R = 0; + escip->CR1.B.SBR = SPC563_SYSCLK / (16 * config->sc_speed); + if (mode & SD_MODE_LOOPBACK) + escip->CR1.B.LOOPS = 1; + switch (mode & SD_MODE_PARITY) { + case SD_MODE_PARITY_ODD: + escip->CR1.B.PT = 1; + case SD_MODE_PARITY_EVEN: + escip->CR1.B.PE = 1; + escip->CR1.B.M = 1; /* Makes it 8 bits data + 1 bit parity. */ + default: + ; + } + escip->LPR.R = 0; + escip->CR1.R |= 0x0000002C; /* RIE, TE, RE to 1. */ + escip->CR2.R |= 0x000F; /* ORIE, NFIE, FEIE, PFIE to 1. */ +} + +/** + * @brief eSCI de-initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] escip pointer to an eSCI I/O block + */ +static void esci_deinit(volatile struct ESCI_tag *escip) { + + escip->LPR.R = 0; + escip->SR.R = 0xFFFFFFFF; + escip->CR1.R = 0; + escip->CR2.R = 0x8000; /* MDIS on. */ +} + +/** + * @brief Error handling routine. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] sr eSCI SR register value + */ +static void set_error(SerialDriver *sdp, uint32_t sr) { + ioflags_t sts = 0; + + if (sr & 0x08000000) + sts |= SD_OVERRUN_ERROR; + if (sr & 0x04000000) + sts |= SD_NOISE_ERROR; + if (sr & 0x02000000) + sts |= SD_FRAMING_ERROR; + if (sr & 0x01000000) + sts |= SD_PARITY_ERROR; +/* if (sr & 0x00000000) + sts |= SD_BREAK_DETECTED;*/ + chSysLockFromIsr(); + chIOAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +/** + * @brief Common IRQ handler. + * + * @param[in] sdp pointer to a @p SerialDriver object + */ +static void serve_interrupt(SerialDriver *sdp) { + volatile struct ESCI_tag *escip = sdp->escip; + + uint32_t sr = escip->SR.R; + escip->SR.R = 0x3FFFFFFF; /* Does not clear TDRE | TC.*/ + if (sr & 0x0F000000) /* OR | NF | FE | PF. */ + set_error(sdp, sr); + if (sr & 0x20000000) { /* RDRF. */ + chSysLockFromIsr(); + sdIncomingDataI(sdp, escip->DR.B.D); + chSysUnlockFromIsr(); + } + if (escip->CR1.B.TIE && (sr & 0x80000000)) { /* TDRE. */ + msg_t b; + chSysLockFromIsr(); + b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) { + chIOAddFlagsI(sdp, IO_OUTPUT_EMPTY); + escip->CR1.B.TIE = 0; + } + else { + ESCI_A.SR.B.TDRE = 1; + escip->DR.R = (uint16_t)b; + } + chSysUnlockFromIsr(); + } +} + +#if USE_SPC563_ESCIA || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + if (ESCI_A.SR.B.TDRE) { + msg_t b = sdRequestDataI(&SD1); + if (b != Q_EMPTY) { + ESCI_A.SR.B.TDRE = 1; + ESCI_A.CR1.B.TIE = 1; + ESCI_A.DR.R = (uint16_t)b; + } + } +} +#endif + +#if USE_SPC563_ESCIB || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + if (ESCI_B.SR.B.TDRE) { + msg_t b = sdRequestDataI(&SD2); + if (b != Q_EMPTY) { + ESCI_B.SR.B.TDRE = 1; + ESCI_B.CR1.B.TIE = 1; + ESCI_B.DR.R = (uint16_t)b; + } + } +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if USE_SPC563_ESCIA || defined(__DOXYGEN__) +/** + * @brief eSCI-A interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(vector146) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD1); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if USE_SPC563_ESCIB || defined(__DOXYGEN__) +/** + * @brief eSCI-B interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(vector149) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD2); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if USE_SPC563_ESCIA + sdObjectInit(&SD1, NULL, notify1); + SD1.escip = &ESCI_A; + ESCI_A.CR2.R = 0x8000; /* MDIS ON. */ + INTC.PSR[146].R = SPC563_ESCIA_PRIORITY; +#endif + +#if USE_SPC563_ESCIB + sdObjectInit(&SD2, NULL, notify2); + SD2.escip = &ESCI_B; + ESCI_B.CR2.R = 0x8000; /* MDIS ON. */ + INTC.PSR[149].R = SPC563_ESCIB_PRIORITY; +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + esci_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) + esci_deinit(sdp->escip); +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/SPC56x/serial_lld.h b/Project/os/hal/platforms/SPC56x/serial_lld.h new file mode 100644 index 0000000..e025af7 --- /dev/null +++ b/Project/os/hal/platforms/SPC56x/serial_lld.h @@ -0,0 +1,164 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file SPC56x/serial_lld.h + * @brief SPC563 low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define SD_MODE_PARITY 0x03 /**< @brief Parity field mask. */ +#define SD_MODE_PARITY_NONE 0x00 /**< @brief No parity. */ +#define SD_MODE_PARITY_EVEN 0x01 /**< @brief Even parity. */ +#define SD_MODE_PARITY_ODD 0x02 /**< @brief Odd parity. */ + +#define SD_MODE_NORMAL 0x00 /**< @brief Normal operations. */ +#define SD_MODE_LOOPBACK 0x80 /**< @brief Internal loopback. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief eSCI-A driver enable switch. + * @details If set to @p TRUE the support for eSCI-A is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_SPC563_ESCIA) || defined(__DOXYGEN__) +#define USE_SPC563_ESCIA TRUE +#endif + +/** + * @brief eSCI-B driver enable switch. + * @details If set to @p TRUE the support for eSCI-B is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_SPC563_ESCIB) || defined(__DOXYGEN__) +#define USE_SPC563_ESCIB TRUE +#endif + +/** + * @brief eSCI-A interrupt priority level setting. + */ +#if !defined(SPC563_ESCIA_PRIORITY) || defined(__DOXYGEN__) +#define SPC563_ESCIA_PRIORITY 8 +#endif + +/** + * @brief eSCI-B interrupt priority level setting. + */ +#if !defined(SPC563_ESCIB_PRIORITY) || defined(__DOXYGEN__) +#define SPC563_ESCIB_PRIORITY 8 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Generic Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t sc_speed; + /** + * @brief Mode flags. + */ + uint8_t sc_mode; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the volatile eSCI registers block.*/ \ + volatile struct ESCI_tag *escip; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if USE_SPC563_ESCIA && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if USE_SPC563_ESCIB && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/SPC56x/typedefs.h b/Project/os/hal/platforms/SPC56x/typedefs.h new file mode 100644 index 0000000..40ab989 --- /dev/null +++ b/Project/os/hal/platforms/SPC56x/typedefs.h @@ -0,0 +1,38 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file SPC56x/typedefs.h + * @brief Dummy typedefs file. + */ + +#ifndef _TYPEDEFS_H_ +#define _TYPEDEFS_H_ + +#include "chtypes.h" + +#endif /* _TYPEDEFS_H_ */ diff --git a/Project/os/hal/platforms/STM32/GPIOv1/pal_lld.c b/Project/os/hal/platforms/STM32/GPIOv1/pal_lld.c new file mode 100644 index 0000000..7ff04d3 --- /dev/null +++ b/Project/os/hal/platforms/STM32/GPIOv1/pal_lld.c @@ -0,0 +1,191 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/GPIOv1/pal_lld.c + * @brief STM32F1xx GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +#if STM32_HAS_GPIOG +#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \ + RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \ + RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | \ + RCC_APB2ENR_IOPGEN | RCC_APB2ENR_AFIOEN) +#elif STM32_HAS_GPIOE +#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \ + RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \ + RCC_APB2ENR_IOPEEN | RCC_APB2ENR_AFIOEN) +#else +#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \ + RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \ + RCC_APB2ENR_AFIOEN) +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 I/O ports configuration. + * @details Ports A-D(E, F, G) clocks enabled, AFIO clock enabled. + * + * @param[in] config the STM32 ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + /* + * Enables the GPIO related clocks. + */ + rccEnableAPB2(APB2_EN_MASK, FALSE); + + /* + * Initial GPIO setup. + */ + GPIOA->ODR = config->PAData.odr; + GPIOA->CRH = config->PAData.crh; + GPIOA->CRL = config->PAData.crl; + GPIOB->ODR = config->PBData.odr; + GPIOB->CRH = config->PBData.crh; + GPIOB->CRL = config->PBData.crl; + GPIOC->ODR = config->PCData.odr; + GPIOC->CRH = config->PCData.crh; + GPIOC->CRL = config->PCData.crl; + GPIOD->ODR = config->PDData.odr; + GPIOD->CRH = config->PDData.crh; + GPIOD->CRL = config->PDData.crl; +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + GPIOE->ODR = config->PEData.odr; + GPIOE->CRH = config->PEData.crh; + GPIOE->CRL = config->PEData.crl; +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + GPIOF->ODR = config->PFData.odr; + GPIOF->CRH = config->PFData.crh; + GPIOF->CRL = config->PFData.crl; +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + GPIOG->ODR = config->PGData.odr; + GPIOG->CRH = config->PGData.crh; + GPIOG->CRL = config->PGData.crl; +#endif +#endif +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + static const uint8_t cfgtab[] = { + 4, /* PAL_MODE_RESET, implemented as input.*/ + 2, /* PAL_MODE_UNCONNECTED, implemented as push pull output 2MHz.*/ + 4, /* PAL_MODE_INPUT */ + 8, /* PAL_MODE_INPUT_PULLUP */ + 8, /* PAL_MODE_INPUT_PULLDOWN */ + 0, /* PAL_MODE_INPUT_ANALOG */ + 3, /* PAL_MODE_OUTPUT_PUSHPULL, 50MHz.*/ + 7, /* PAL_MODE_OUTPUT_OPENDRAIN, 50MHz.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 0xB, /* PAL_MODE_STM32_ALTERNATE_PUSHPULL, 50MHz.*/ + 0xF, /* PAL_MODE_STM32_ALTERNATE_OPENDRAIN, 50MHz.*/ + }; + uint32_t mh, ml, crh, crl, cfg; + unsigned i; + + if (mode == PAL_MODE_INPUT_PULLUP) + port->BSRR = mask; + else if (mode == PAL_MODE_INPUT_PULLDOWN) + port->BRR = mask; + cfg = cfgtab[mode]; + mh = ml = crh = crl = 0; + for (i = 0; i < 8; i++) { + ml <<= 4; + mh <<= 4; + crl <<= 4; + crh <<= 4; + if ((mask & 0x0080) == 0) + ml |= 0xf; + else + crl |= cfg; + if ((mask & 0x8000) == 0) + mh |= 0xf; + else + crh |= cfg; + mask <<= 1; + } + port->CRH = (port->CRH & mh) | crh; + port->CRL = (port->CRL & ml) | crl; +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/GPIOv1/pal_lld.h b/Project/os/hal/platforms/STM32/GPIOv1/pal_lld.h new file mode 100644 index 0000000..4ddebb3 --- /dev/null +++ b/Project/os/hal/platforms/STM32/GPIOv1/pal_lld.h @@ -0,0 +1,345 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/GPIOv1/pal_lld.h + * @brief STM32F1xx GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +/** + * @name STM32-specific I/O mode flags + * @{ + */ +/** + * @brief STM32 specific alternate push-pull output mode. + */ +#define PAL_MODE_STM32_ALTERNATE_PUSHPULL 16 + +/** + * @brief STM32 specific alternate open-drain output mode. + */ +#define PAL_MODE_STM32_ALTERNATE_OPENDRAIN 17 +/** @} */ + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief GPIO port setup info. + */ +typedef struct { + /** Initial value for ODR register.*/ + uint32_t odr; + /** Initial value for CRL register.*/ + uint32_t crl; + /** Initial value for CRH register.*/ + uint32_t crh; +} stm32_gpio_setup_t; + +/** + * @brief STM32 GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialize the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { + /** @brief Port A setup data.*/ + stm32_gpio_setup_t PAData; + /** @brief Port B setup data.*/ + stm32_gpio_setup_t PBData; + /** @brief Port C setup data.*/ + stm32_gpio_setup_t PCData; + /** @brief Port D setup data.*/ + stm32_gpio_setup_t PDData; +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + /** @brief Port E setup data.*/ + stm32_gpio_setup_t PEData; +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + /** @brief Port F setup data.*/ + stm32_gpio_setup_t PFData; +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + /** @brief Port G setup data.*/ + stm32_gpio_setup_t PGData; +#endif +#endif +#endif +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 16 + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef GPIO_TypeDef * ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/* The low level driver wraps the definitions already present in the STM32 */ +/* firmware library. */ +/*===========================================================================*/ + +/** + * @brief GPIO port A identifier. + */ +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) +#define IOPORT1 GPIOA +#endif + +/** + * @brief GPIO port B identifier. + */ +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) +#define IOPORT2 GPIOB +#endif + +/** + * @brief GPIO port C identifier. + */ +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) +#define IOPORT3 GPIOC +#endif + +/** + * @brief GPIO port D identifier. + */ +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) +#define IOPORT4 GPIOD +#endif + +/** + * @brief GPIO port E identifier. + */ +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) +#define IOPORT5 GPIOE +#endif + +/** + * @brief GPIO port F identifier. + */ +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) +#define IOPORT6 GPIOF +#endif + +/** + * @brief GPIO port G identifier. + */ +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) +#define IOPORT7 GPIOG +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief GPIO ports subsystem initialization. + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads an I/O port. + * @details This function is implemented by reading the GPIO IDR register, the + * implementation has no side effects. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->IDR) + +/** + * @brief Reads the output latch. + * @details This function is implemented by reading the GPIO ODR register, the + * implementation has no side effects. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->ODR) + +/** + * @brief Writes on a I/O port. + * @details This function is implemented by writing the GPIO ODR register, the + * implementation has no side effects. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->ODR = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) ((port)->BSRR = (bits)) + +/** + * @brief Clears a bits mask on a I/O port. + * @details This function is implemented by writing the GPIO BRR register, the + * implementation has no side effects. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) ((port)->BRR = (bits)) + +/** + * @brief Writes a group of bits. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset the group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group + * width are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + ((port)->BSRR = ((~(bits) & (mask)) << (16 + (offset))) | \ + (((bits) & (mask)) << (offset))) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) + +extern const PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/GPIOv2/pal_lld.c b/Project/os/hal/platforms/STM32/GPIOv2/pal_lld.c new file mode 100644 index 0000000..e402ff6 --- /dev/null +++ b/Project/os/hal/platforms/STM32/GPIOv2/pal_lld.c @@ -0,0 +1,231 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/GPIOv2/pal_lld.c + * @brief STM32L1xx/STM32F2xx/STM32F4xx GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +#if defined(STM32L1XX_MD) +#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \ + RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \ + RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN) +#elif defined(STM32F2XX) +#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \ + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \ + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \ + RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \ + RCC_AHB1ENR_GPIOIEN) +#define AHB1_LPEN_MASK AHB1_EN_MASK +#elif defined(STM32F4XX) +#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \ + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \ + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \ + RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \ + RCC_AHB1ENR_GPIOIEN) +#define AHB1_LPEN_MASK AHB1_EN_MASK +#else +#error "missing or unsupported platform for GPIOv2 PAL driver" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void initgpio(GPIO_TypeDef *gpiop, const stm32_gpio_setup_t *config) { + + gpiop->ODR = config->odr; + gpiop->MODER = config->moder; + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 I/O ports configuration. + * @details Ports A-D(E, F, G, H) clocks enabled. + * + * @param[in] config the STM32 ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + /* + * Enables the GPIO related clocks. + */ +#if defined(STM32L1XX_MD) + rccEnableAHB(AHB_EN_MASK, TRUE); +#elif defined(STM32F2XX) || defined(STM32F4XX) + RCC->AHB1ENR |= AHB1_EN_MASK; + RCC->AHB1LPENR |= AHB1_LPEN_MASK; +#endif + + /* + * Initial GPIO setup. + */ + initgpio(GPIOA, &config->PAData); + initgpio(GPIOB, &config->PBData); + initgpio(GPIOC, &config->PCData); + initgpio(GPIOD, &config->PDData); +#if STM32_HAS_GPIOE + initgpio(GPIOE, &config->PEData); +#endif +#if STM32_HAS_GPIOF + initgpio(GPIOF, &config->PFData); +#endif +#if STM32_HAS_GPIOG + initgpio(GPIOG, &config->PGData); +#endif +#if STM32_HAS_GPIOH + initgpio(GPIOH, &config->PHData); +#endif +#if STM32_HAS_GPIOI + initgpio(GPIOI, &config->PIData); +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum + * speed. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +#if 1 +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + uint32_t moder = (mode & PAL_STM32_MODE_MASK) >> 0; + uint32_t otyper = (mode & PAL_STM32_OTYPE_MASK) >> 2; + uint32_t ospeedr = (mode & PAL_STM32_OSPEED_MASK) >> 3; + uint32_t pupdr = (mode & PAL_STM32_PUDR_MASK) >> 5; + uint32_t altr = (mode & PAL_STM32_ALTERNATE_MASK) >> 7; + uint32_t bit = 0; + while (TRUE) { + if ((mask & 1) != 0) { + uint32_t altrmask, m1, m2, m4; + + altrmask = altr << ((bit & 7) * 4); + m4 = 15 << ((bit & 7) * 4); + if (bit < 8) + port->AFRL = (port->AFRL & ~m4) | altrmask; + else + port->AFRH = (port->AFRH & ~m4) | altrmask; + m1 = 1 << bit; + port->OTYPER = (port->OTYPER & ~m1) | otyper; + m2 = 3 << (bit * 2); + port->OSPEEDR = (port->OSPEEDR & ~m2) | ospeedr; + port->PUPDR = (port->PUPDR & ~m2) | pupdr; + port->MODER = (port->MODER & ~m2) | moder; + } + mask >>= 1; + if (!mask) + return; + otyper <<= 1; + ospeedr <<= 2; + pupdr <<= 2; + moder <<= 2; + bit++; + } +} +#else +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + uint32_t afrm, moderm, pupdrm, otyperm, ospeedrm; + uint32_t m1 = (uint32_t)mask; + uint32_t m2 = 0; + uint32_t m4l = 0; + uint32_t m4h = 0; + uint32_t bit = 0; + do { + if ((mask & 1) != 0) { + m2 |= 3 << bit; + if (bit < 16) + m4l |= 15 << ((bit & 14) * 2); + else + m4h |= 15 << ((bit & 14) * 2); + } + bit += 2; + mask >>= 1; + } while (mask); + + afrm = ((mode & PAL_STM32_ALTERNATE_MASK) >> 7) * 0x1111; + port->AFRL = (port->AFRL & ~m4l) | (afrm & m4l); + port->AFRH = (port->AFRH & ~m4h) | (afrm & m4h); + + ospeedrm = ((mode & PAL_STM32_OSPEED_MASK) >> 3) * 0x5555; + port->OSPEEDR = (port->OSPEEDR & ~m2) | (ospeedrm & m2); + + otyperm = ((mode & PAL_STM32_OTYPE_MASK) >> 2) * 0xffff; + port->OTYPER = (port->OTYPER & ~m1) | (otyperm & m1); + + pupdrm = ((mode & PAL_STM32_PUDR_MASK) >> 5) * 0x5555; + port->PUPDR = (port->PUPDR & ~m2) | (pupdrm & m2); + + moderm = ((mode & PAL_STM32_MODE_MASK) >> 0) * 0x5555; + port->MODER = (port->MODER & ~m2) | (moderm & m2); +} +#endif + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/GPIOv2/pal_lld.h b/Project/os/hal/platforms/STM32/GPIOv2/pal_lld.h new file mode 100644 index 0000000..c48539a --- /dev/null +++ b/Project/os/hal/platforms/STM32/GPIOv2/pal_lld.h @@ -0,0 +1,460 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/GPIOv2/pal_lld.h + * @brief STM32L1xx/STM32F2xx/STM32F4xx GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_RESET +#undef PAL_MODE_UNCONNECTED +#undef PAL_MODE_INPUT +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_PUSHPULL +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/** + * @name STM32-specific I/O mode flags + * @{ + */ +#define PAL_STM32_MODE_MASK (3 << 0) +#define PAL_STM32_MODE_INPUT (0 << 0) +#define PAL_STM32_MODE_OUTPUT (1 << 0) +#define PAL_STM32_MODE_ALTERNATE (2 << 0) +#define PAL_STM32_MODE_ANALOG (3 << 0) + +#define PAL_STM32_OTYPE_MASK (1 << 2) +#define PAL_STM32_OTYPE_PUSHPULL (0 << 2) +#define PAL_STM32_OTYPE_OPENDRAIN (1 << 2) + +#define PAL_STM32_OSPEED_MASK (3 << 3) +#define PAL_STM32_OSPEED_LOWEST (0 << 3) +#define PAL_STM32_OSPEED_MID1 (1 << 3) +#define PAL_STM32_OSPEED_MID2 (2 << 3) +#define PAL_STM32_OSPEED_HIGHEST (3 << 3) + +#define PAL_STM32_PUDR_MASK (3 << 5) +#define PAL_STM32_PUDR_FLOATING (0 << 5) +#define PAL_STM32_PUDR_PULLUP (1 << 5) +#define PAL_STM32_PUDR_PULLDOWN (2 << 5) + +#define PAL_STM32_ALTERNATE_MASK (15 << 7) +#define PAL_STM32_ALTERNATE(n) ((n) << 7) + +/** + * @brief Alternate function. + * + * @param[in] n alternate function selector + */ +#define PAL_MODE_ALTERNATE(n) (PAL_STM32_MODE_ALTERNATE | \ + PAL_STM32_ALTERNATE(n)) +/** @} */ + +/** + * @name Standard I/O mode flags + * @{ + */ +/** + * @brief This mode is implemented as input. + */ +#define PAL_MODE_RESET PAL_STM32_MODE_INPUT + +/** + * @brief This mode is implemented as output. + */ +#define PAL_MODE_UNCONNECTED PAL_STM32_MODE_OUTPUT + +/** + * @brief Regular input high-Z pad. + */ +#define PAL_MODE_INPUT PAL_STM32_MODE_INPUT + +/** + * @brief Input pad with weak pull up resistor. + */ +#define PAL_MODE_INPUT_PULLUP (PAL_STM32_MODE_INPUT | \ + PAL_STM32_PUDR_PULLUP) + +/** + * @brief Input pad with weak pull down resistor. + */ +#define PAL_MODE_INPUT_PULLDOWN (PAL_STM32_MODE_INPUT | \ + PAL_STM32_PUDR_PULLDOWN) + +/** + * @brief Analog input mode. + */ +#define PAL_MODE_INPUT_ANALOG PAL_STM32_MODE_ANALOG + +/** + * @brief Push-pull output pad. + */ +#define PAL_MODE_OUTPUT_PUSHPULL (PAL_STM32_MODE_OUTPUT | \ + PAL_STM32_OTYPE_PUSHPULL) + +/** + * @brief Open-drain output pad. + */ +#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_STM32_MODE_OUTPUT | \ + PAL_STM32_OTYPE_OPENDRAIN) +/** @} */ + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief STM32 GPIO registers block. + */ +typedef struct { + + volatile uint32_t MODER; + volatile uint32_t OTYPER; + volatile uint32_t OSPEEDR; + volatile uint32_t PUPDR; + volatile uint32_t IDR; + volatile uint32_t ODR; + volatile union { + uint32_t W; + struct { + uint16_t set; + uint16_t clear; + } H; + } BSRR; + volatile uint32_t LCKR; + volatile uint32_t AFRL; + volatile uint32_t AFRH; +} GPIO_TypeDef; + +/** + * @brief GPIO port setup info. + */ +typedef struct { + /** Initial value for MODER register.*/ + uint32_t moder; + /** Initial value for OTYPER register.*/ + uint32_t otyper; + /** Initial value for OSPEEDR register.*/ + uint32_t ospeedr; + /** Initial value for PUPDR register.*/ + uint32_t pupdr; + /** Initial value for ODR register.*/ + uint32_t odr; + /** Initial value for AFRL register.*/ + uint32_t afrl; + /** Initial value for AFRH register.*/ + uint32_t afrh; +} stm32_gpio_setup_t; + +/** + * @brief STM32 GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialize the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { + /** @brief Port A setup data.*/ + stm32_gpio_setup_t PAData; + /** @brief Port B setup data.*/ + stm32_gpio_setup_t PBData; + /** @brief Port C setup data.*/ + stm32_gpio_setup_t PCData; + /** @brief Port D setup data.*/ + stm32_gpio_setup_t PDData; +#if STM32_HAS_GPIOE + /** @brief Port E setup data.*/ + stm32_gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF + /** @brief Port F setup data.*/ + stm32_gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG + /** @brief Port G setup data.*/ + stm32_gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH + /** @brief Port H setup data.*/ + stm32_gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI + /** @brief Port I setup data.*/ + stm32_gpio_setup_t PIData; +#endif +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 16 + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef GPIO_TypeDef * ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/* The low level driver wraps the definitions already present in the STM32 */ +/* firmware library. */ +/*===========================================================================*/ + +/** + * @brief GPIO port A identifier. + */ +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) +#define IOPORT1 GPIOA +#endif + +/** + * @brief GPIO port B identifier. + */ +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) +#define IOPORT2 GPIOB +#endif + +/** + * @brief GPIO port C identifier. + */ +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) +#define IOPORT3 GPIOC +#endif + +/** + * @brief GPIO port D identifier. + */ +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) +#define IOPORT4 GPIOD +#endif + +/** + * @brief GPIO port E identifier. + */ +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) +#define IOPORT5 GPIOE +#endif + +/** + * @brief GPIO port F identifier. + */ +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) +#define IOPORT6 GPIOF +#endif + +/** + * @brief GPIO port G identifier. + */ +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) +#define IOPORT7 GPIOG +#endif + +/** + * @brief GPIO port H identifier. + */ +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) +#define IOPORT8 GPIOH +#endif + +/** + * @brief GPIO port I identifier. + */ +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) +#define IOPORT9 GPIOI +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief GPIO ports subsystem initialization. + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads an I/O port. + * @details This function is implemented by reading the GPIO IDR register, the + * implementation has no side effects. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->IDR) + +/** + * @brief Reads the output latch. + * @details This function is implemented by reading the GPIO ODR register, the + * implementation has no side effects. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->ODR) + +/** + * @brief Writes on a I/O port. + * @details This function is implemented by writing the GPIO ODR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->ODR = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) ((port)->BSRR.H.set = (uint16_t)(bits)) + +/** + * @brief Clears a bits mask on a I/O port. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) ((port)->BSRR.H.clear = (uint16_t)(bits)) + +/** + * @brief Writes a group of bits. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset the group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group + * width are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + ((port)->BSRR.W = ((~(bits) & (mask)) << (16 + (offset))) | \ + (((bits) & (mask)) << (offset))) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) + +extern const PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/RTCv1/rtc_lld.c b/Project/os/hal/platforms/STM32/RTCv1/rtc_lld.c new file mode 100644 index 0000000..86eecf0 --- /dev/null +++ b/Project/os/hal/platforms/STM32/RTCv1/rtc_lld.c @@ -0,0 +1,311 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file STM32/RTCv1/rtc_lld.c + * @brief STM32 RTC subsystem low level driver header. + * + * @addtogroup RTC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief RTC driver identifier. + */ +RTCDriver RTCD1; + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Wait for synchronization of RTC registers with APB1 bus. + * @details This function must be invoked before trying to read RTC registers + * in the backup domain: DIV, CNT, ALR. CR registers can always + * be read. + * + * @notapi + */ +#define rtc_lld_apb1_sync() {while ((RTC->CRL & RTC_CRL_RSF) == 0);} + +/** + * @brief Wait for for previous write operation complete. + * @details This function must be invoked before writing to any RTC registers + * + * @notapi + */ +#define rtc_lld_wait_write() {while ((RTC->CRL & RTC_CRL_RTOFF) == 0);} + +/** + * @brief Acquires write access to RTC registers. + * @details Before writing to the backup domain RTC registers the previous + * write operation must be completed. Use this function before + * writing to PRL, CNT, ALR registers. + * + * @notapi + */ +#define rtc_lld_acquire() {rtc_lld_wait_write(); RTC->CRL |= RTC_CRL_CNF;} + +/** + * @brief Releases write access to RTC registers. + * + * @notapi + */ +#define rtc_lld_release() {RTC->CRL &= ~RTC_CRL_CNF;} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief RTC interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(RTC_IRQHandler) { + uint16_t flags; + + CH_IRQ_PROLOGUE(); + + /* This wait works only when AHB1 bus was previously powered off by any + reason (standby, reset, etc). In other cases it does nothing.*/ + rtc_lld_apb1_sync(); + + /* Mask of all enabled and pending sources.*/ + flags = RTC->CRH & RTC->CRL; + RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); + + if (flags & RTC_CRL_SECF) + RTCD1.callback(&RTCD1, RTC_EVENT_SECOND); + + if (flags & RTC_CRL_ALRF) + RTCD1.callback(&RTCD1, RTC_EVENT_ALARM); + + if (flags & RTC_CRL_OWF) + RTCD1.callback(&RTCD1, RTC_EVENT_OVERFLOW); + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enable access to registers and initialize RTC if BKP domain + * was previously reseted. + * @note: Cold start time of LSE oscillator on STM32 platform + * takes about 3 seconds. + * + * @notapi + */ +void rtc_lld_init(void){ + + /* Required because access to PRL.*/ + rtc_lld_apb1_sync(); + + /* + * Writes preload register only if its value is not equal to desired value. + * + * Ref CD00171190: RM0008 Reference manual Cls 18.4.3 The RTC->PRL registers + * are write only. We must store the value for the pre-scaler in BKP->DR1 + * and BKP->DR1 so we know it has been set. + * The pre-scaler must not be set on every reset as RTC clock counts are + * lost when it is set. + */ + if ((STM32_RTCCLK - 1) != ((((uint32_t)BKP->DR1) << 16) | BKP->DR2)){ + rtc_lld_acquire(); + RTC->PRLH = (uint16_t)((STM32_RTCCLK - 1) >> 16) & 0x000F; + BKP->DR1 = (uint16_t)((STM32_RTCCLK - 1) >> 16) & 0x000F; + RTC->PRLL = (uint16_t)(((STM32_RTCCLK - 1)) & 0xFFFF); + BKP->DR2 = (uint16_t)(((STM32_RTCCLK - 1)) & 0xFFFF); + rtc_lld_release(); + } + + /* All interrupts initially disabled.*/ + rtc_lld_wait_write(); + RTC->CRH = 0; + + /* Callback initially disabled.*/ + RTCD1.callback = NULL; + + /* IRQ vector permanently assigned to this driver.*/ + nvicEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(STM32_RTC_IRQ_PRIORITY)); +} + +/** + * @brief Set current time. + * @note Fractional part will be silently ignored. There is no possibility + * to change it on STM32F1xx platform. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] timespec pointer to a @p RTCTime structure + * + * @notapi + */ +void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec) { + + (void)rtcp; + + rtc_lld_acquire(); + RTC->CNTH = (uint16_t)(timespec->tv_sec >> 16); + RTC->CNTL = (uint16_t)(timespec->tv_sec & 0xFFFF); + rtc_lld_release(); +} + +/** + * @brief Get current time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] timespec pointer to a @p RTCTime structure + * + * @notapi + */ +void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec) { + (void)rtcp; + + uint32_t time_frac; + + /* Required because access to CNT and DIV.*/ + rtc_lld_apb1_sync(); + + /* Loops until two consecutive read returning the same value.*/ + do { + timespec->tv_sec = ((uint32_t)(RTC->CNTH) << 16) + RTC->CNTL; + time_frac = (((uint32_t)RTC->DIVH) << 16) + (uint32_t)RTC->DIVL; + } while ((timespec->tv_sec) != (((uint32_t)(RTC->CNTH) << 16) + RTC->CNTL)); + + timespec->tv_msec = (uint16_t)(((STM32_RTCCLK - 1 - time_frac) * 1000) / + STM32_RTCCLK); +} + +/** + * @brief Set alarm time. + * + * @note Default value after BKP domain reset is 0xFFFFFFFF + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[in] alarmspec pointer to a @p RTCAlarm structure + * + * @notapi + */ +void rtc_lld_set_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + const RTCAlarm *alarmspec) { + + (void)rtcp; + (void)alarm; + + rtc_lld_acquire(); + if (alarmspec != NULL) { + RTC->ALRH = (uint16_t)(alarmspec->tv_sec >> 16); + RTC->ALRL = (uint16_t)(alarmspec->tv_sec & 0xFFFF); + } + else { + RTC->ALRH = 0; + RTC->ALRL = 0; + } + rtc_lld_release(); +} + +/** + * @brief Get current alarm. + * @note If an alarm has not been set then the returned alarm specification + * is not meaningful. + * + * @note Default value after BKP domain reset is 0xFFFFFFFF. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[out] alarmspec pointer to a @p RTCAlarm structure + * + * @notapi + */ +void rtc_lld_get_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + RTCAlarm *alarmspec) { + + (void)rtcp; + (void)alarm; + + /* Required because access to ALR.*/ + rtc_lld_apb1_sync(); + + alarmspec->tv_sec = ((RTC->ALRH << 16) + RTC->ALRL); +} + +/** + * @brief Enables or disables RTC callbacks. + * @details This function enables or disables callbacks, use a @p NULL pointer + * in order to disable a callback. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] callback callback function pointer or @p NULL + * + * @notapi + */ +void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) { + + if (callback != NULL) { + + /* IRQ sources enabled only after setting up the callback.*/ + rtcp->callback = callback; + + rtc_lld_wait_write(); + RTC->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF); + RTC->CRH = RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE; + } + else { + rtc_lld_wait_write(); + RTC->CRH = 0; + + /* Callback set to NULL only after disabling the IRQ sources.*/ + rtcp->callback = NULL; + } +} + +#endif /* HAL_USE_RTC */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/RTCv1/rtc_lld.h b/Project/os/hal/platforms/STM32/RTCv1/rtc_lld.h new file mode 100644 index 0000000..7cc53a3 --- /dev/null +++ b/Project/os/hal/platforms/STM32/RTCv1/rtc_lld.h @@ -0,0 +1,196 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file STM32/RTCv1/rtc_lld.h + * @brief STM32F1xx RTC subsystem low level driver header. + * + * @addtogroup RTC + * @{ + */ + +#ifndef _RTC_LLD_H_ +#define _RTC_LLD_H_ + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief This RTC implementation supports callbacks. + */ +#define RTC_SUPPORTS_CALLBACKS TRUE + +/** + * @brief One alarm comparator available. + */ +#define RTC_ALARMS 1 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if HAL_USE_RTC && !STM32_HAS_RTC +#error "RTC not present in the selected device" +#endif + +#if STM32_RTCCLK == 0 +#error "RTC clock not enabled" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an RTC alarm time stamp. + */ +typedef struct RTCAlarm RTCAlarm; + +/** + * @brief Type of a structure representing an RTC callbacks config. + */ +typedef struct RTCCallbackConfig RTCCallbackConfig; + +/** + * @brief Type of an RTC alarm. + * @details Meaningful on platforms with more than 1 alarm comparator. + */ +typedef uint32_t rtcalarm_t; + +/** + * @brief Type of an RTC event. + */ +typedef enum { + RTC_EVENT_SECOND = 0, /** Triggered every second. */ + RTC_EVENT_ALARM = 1, /** Triggered on alarm. */ + RTC_EVENT_OVERFLOW = 2 /** Triggered on counter overflow. */ +} rtcevent_t; + +/** + * @brief Type of a generic RTC callback. + */ +typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event); + +/** + * @brief Structure representing an RTC callbacks config. + */ +struct RTCCallbackConfig{ + /** + * @brief Generic RTC callback pointer. + */ + rtccb_t callback; +}; + +/** + * @brief Structure representing an RTC time stamp. + */ +struct RTCTime { + /** + * @brief Seconds since UNIX epoch. + */ + uint32_t tv_sec; + /** + * @brief Fractional part. + */ + uint32_t tv_msec; +}; + +/** + * @brief Structure representing an RTC alarm time stamp. + */ +struct RTCAlarm { + /** + * @brief Seconds since UNIX epoch. + */ + uint32_t tv_sec; +}; + +/** + * @brief Structure representing an RTC driver. + */ +struct RTCDriver{ + /** + * @brief Callback pointer. + */ + rtccb_t callback; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern RTCDriver RTCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void rtc_lld_init(void); + void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec); + void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec); + void rtc_lld_set_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + const RTCAlarm *alarmspec); + void rtc_lld_get_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + RTCAlarm *alarmspec); + void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_RTC */ + +#endif /* _RTC_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/USBv1/stm32_usb.h b/Project/os/hal/platforms/STM32/USBv1/stm32_usb.h new file mode 100644 index 0000000..728d105 --- /dev/null +++ b/Project/os/hal/platforms/STM32/USBv1/stm32_usb.h @@ -0,0 +1,254 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file stm32_usb.h + * @brief STM32 USB registers layout header. + * @note This file requires definitions from the ST STM32 header files + * stm32f10x.h or stm32l1xx.h. + * + * @addtogroup USB + * @{ + */ + +#ifndef _STM32_USB_H_ +#define _STM32_USB_H_ + +/** + * @brief Number of the available endpoints. + * @details This value does not include the endpoint 0 which is always present. + */ +#define USB_ENDOPOINTS_NUMBER 7 + +/** + * @brief USB registers block. + */ +typedef struct { + /** + * @brief Endpoint registers. + */ + volatile uint32_t EPR[USB_ENDOPOINTS_NUMBER + 1]; + /* + * @brief Reserved space. + */ + volatile uint32_t _r20[8]; + /* + * @brief Control Register. + */ + volatile uint32_t CNTR; + /* + * @brief Interrupt Status Register. + */ + volatile uint32_t ISTR; + /* + * @brief Frame Number Register. + */ + volatile uint32_t FNR; + /* + * @brief Device Address Register. + */ + volatile uint32_t DADDR; + /* + * @brief Buffer Table Address. + */ + volatile uint32_t BTABLE; +} stm32_usb_t; + +/** + * @brief USB descriptor registers block. + */ +typedef struct { + /** + * @brief TX buffer offset register. + */ + volatile uint32_t TXADDR0; + /** + * @brief TX counter register 0. + */ + volatile uint16_t TXCOUNT0; + /** + * @brief TX counter register 1. + */ + volatile uint16_t TXCOUNT1; + /** + * @brief RX buffer offset register. + */ + volatile uint32_t RXADDR0; + /** + * @brief RX counter register 0. + */ + volatile uint16_t RXCOUNT0; + /** + * @brief RX counter register 1. + */ + volatile uint16_t RXCOUNT1; +} stm32_usb_descriptor_t; + +/** + * @name Register aliases + * @{ + */ +#define RXADDR1 TXADDR0 +#define TXADDR1 RXADDR0 +/** @} */ + +/** + * @brief USB registers block numeric address. + */ +#define STM32_USB_BASE (APB1PERIPH_BASE + 0x5C00) + +/** + * @brief USB RAM numeric address. + */ +#define STM32_USBRAM_BASE (APB1PERIPH_BASE + 0x6000) + +/** + * @brief Pointer to the USB registers block. + */ +#define STM32_USB ((stm32_usb_t *)STM32_USB_BASE) + +/** + * @brief Pointer to the USB RAM. + */ +#define STM32_USBRAM ((uint32_t *)STM32_USBRAM_BASE) + +/** + * @brief Size of the dedicated packet memory. + */ +#define USB_PMA_SIZE 512 + +/** + * @brief Mask of all the toggling bits in the EPR register. + */ +#define EPR_TOGGLE_MASK (EPR_STAT_TX_MASK | EPR_DTOG_TX | \ + EPR_STAT_RX_MASK | EPR_DTOG_RX | \ + EPR_SETUP) + +#define EPR_EA_MASK 0x000F +#define EPR_STAT_TX_MASK 0x0030 +#define EPR_STAT_TX_DIS 0x0000 +#define EPR_STAT_TX_STALL 0x0010 +#define EPR_STAT_TX_NAK 0x0020 +#define EPR_STAT_TX_VALID 0x0030 +#define EPR_DTOG_TX 0x0040 +#define EPR_SWBUF_RX EPR_DTOG_TX +#define EPR_CTR_TX 0x0080 +#define EPR_EP_KIND 0x0100 +#define EPR_EP_DBL_BUF EPR_EP_KIND +#define EPR_EP_STATUS_OUT EPR_EP_KIND +#define EPR_EP_TYPE_MASK 0x0600 +#define EPR_EP_TYPE_BULK 0x0000 +#define EPR_EP_TYPE_CONTROL 0x0200 +#define EPR_EP_TYPE_ISO 0x0400 +#define EPR_EP_TYPE_INTERRUPT 0x0600 +#define EPR_SETUP 0x0800 +#define EPR_STAT_RX_MASK 0x3000 +#define EPR_STAT_RX_DIS 0x0000 +#define EPR_STAT_RX_STALL 0x1000 +#define EPR_STAT_RX_NAK 0x2000 +#define EPR_STAT_RX_VALID 0x3000 +#define EPR_DTOG_RX 0x4000 +#define EPR_SWBUF_TX EPR_DTOG_RX +#define EPR_CTR_RX 0x8000 + +#define CNTR_FRES 0x0001 +#define CNTR_PDWN 0x0002 +#define CNTR_LP_MODE 0x0004 +#define CNTR_FSUSP 0x0008 +#define CNTR_RESUME 0x0010 +#define CNTR_ESOFM 0x0100 +#define CNTR_SOFM 0x0200 +#define CNTR_RESETM 0x0400 +#define CNTR_SUSPM 0x0800 +#define CNTR_WKUPM 0x1000 +#define CNTR_ERRM 0x2000 +#define CNTR_PMAOVRM 0x4000 +#define CNTR_CTRM 0x8000 + +#define ISTR_EP_ID_MASK 0x000F +#define ISTR_DIR 0x0010 +#define ISTR_ESOF 0x0100 +#define ISTR_SOF 0x0200 +#define ISTR_RESET 0x0400 +#define ISTR_SUSP 0x0800 +#define ISTR_WKUP 0x1000 +#define ISTR_ERR 0x2000 +#define ISTR_PMAOVR 0x4000 +#define ISTR_CTR 0x8000 + +#define FNR_FN_MASK 0x07FF +#define FNR_LSOF 0x1800 +#define FNR_LCK 0x2000 +#define FNR_RXDM 0x4000 +#define FNR_RXDP 0x8000 + +#define DADDR_ADD_MASK 0x007F +#define DADDR_EF 0x0080 + +#define RXCOUNT_COUNT_MASK 0x03FF +#define TXCOUNT_COUNT_MASK 0x03FF + +#define EPR_SET(ep, epr) \ + STM32_USB->EPR[ep] = (epr) & ~EPR_TOGGLE_MASK + +#define EPR_TOGGLE(ep, epr) \ + STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] ^ ((epr) & EPR_TOGGLE_MASK)) + +#define EPR_SET_STAT_RX(ep, epr) \ + STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] & \ + ~(EPR_TOGGLE_MASK & ~EPR_STAT_RX_MASK)) ^ \ + (epr) + +#define EPR_SET_STAT_TX(ep, epr) \ + STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] & \ + ~(EPR_TOGGLE_MASK & ~EPR_STAT_TX_MASK)) ^ \ + (epr) + +#define EPR_CLEAR_CTR_RX(ep) \ + STM32_USB->EPR[ep] &= ~EPR_CTR_RX & ~EPR_TOGGLE_MASK + +#define EPR_CLEAR_CTR_TX(ep) \ + STM32_USB->EPR[ep] &= ~EPR_CTR_TX & ~EPR_TOGGLE_MASK + +/** + * @brief Returns an endpoint descriptor pointer. + */ +#define USB_GET_DESCRIPTOR(ep) \ + ((stm32_usb_descriptor_t *)((uint32_t)STM32_USBRAM_BASE + \ + (uint32_t)STM32_USB->BTABLE * 2 + \ + (uint32_t)(ep) * \ + sizeof(stm32_usb_descriptor_t))) + +/** + * @brief Converts from a PMA address to a physical address. + */ +#define USB_ADDR2PTR(addr) \ + ((uint32_t *)((addr) * 2 + STM32_USBRAM_BASE)) + +#endif /* _STM32_USB_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/USBv1/usb_lld.c b/Project/os/hal/platforms/STM32/USBv1/usb_lld.c new file mode 100644 index 0000000..d17d911 --- /dev/null +++ b/Project/os/hal/platforms/STM32/USBv1/usb_lld.c @@ -0,0 +1,746 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/USBv1/usb_lld.c + * @brief STM32 USB subsystem low level driver source. + * + * @addtogroup USB + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_USB || defined(__DOXYGEN__) + +#define BTABLE_ADDR 0x0000 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief USB1 driver identifier.*/ +#if STM32_USB_USE_USB1 || defined(__DOXYGEN__) +USBDriver USBD1; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** + * @brief EP0 state. + * @note It is an union because IN and OUT endpoints are never used at the + * same time for EP0. + */ +static union { + /** + * @brief IN EP0 state. + */ + USBInEndpointState in; + /** + * @brief OUT EP0 state. + */ + USBOutEndpointState out; +} ep0_state; + +/** + * @brief EP0 initialization structure. + */ +static const USBEndpointConfig ep0config = { + USB_EP_MODE_TYPE_CTRL | USB_EP_MODE_TRANSACTION, + _usb_ep0setup, + _usb_ep0in, + _usb_ep0out, + 0x40, + 0x40, + &ep0_state.in, + &ep0_state.out +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Resets the packet memory allocator. + * + * @param[in] usbp pointer to the @p USBDriver object + */ +static void pm_reset(USBDriver *usbp) { + + /* The first 64 bytes are reserved for the descriptors table. The effective + available RAM for endpoint buffers is just 448 bytes.*/ + usbp->pmnext = 64; +} + +/** + * @brief Resets the packet memory allocator. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] size size of the packet buffer to allocate + */ +static uint32_t pm_alloc(USBDriver *usbp, size_t size) { + uint32_t next; + + next = usbp->pmnext; + usbp->pmnext += size; + chDbgAssert(usbp->pmnext <= USB_PMA_SIZE, "pm_alloc(), #1", "PMA overflow"); + return next; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_USB_USE_USB1 || defined(__DOXYGEN__) +/** + * @brief USB high priority interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector8C) { + + CH_IRQ_PROLOGUE(); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief USB low priority interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector90) { + uint32_t istr; + size_t n; + USBDriver *usbp = &USBD1; + + CH_IRQ_PROLOGUE(); + + istr = STM32_USB->ISTR; + + /* USB bus reset condition handling.*/ + if (istr & ISTR_RESET) { + _usb_reset(usbp); + _usb_isr_invoke_event_cb(usbp, USB_EVENT_RESET); + STM32_USB->ISTR = ~ISTR_RESET; + } + + /* USB bus SUSPEND condition handling.*/ + if (istr & ISTR_SUSP) { + STM32_USB->CNTR |= CNTR_FSUSP; + _usb_isr_invoke_event_cb(usbp, USB_EVENT_SUSPEND); +#if STM32_USB_LOW_POWER_ON_SUSPEND + STM32_USB->CNTR |= CNTR_LP_MODE; +#endif + STM32_USB->ISTR = ~ISTR_SUSP; + } + + /* USB bus WAKEUP condition handling.*/ + if (istr & ISTR_WKUP) { + uint32_t fnr = STM32_USB->FNR; + if (!(fnr & FNR_RXDP)) { + STM32_USB->CNTR &= ~CNTR_FSUSP; + _usb_isr_invoke_event_cb(usbp, USB_EVENT_WAKEUP); + } +#if STM32_USB_LOW_POWER_ON_SUSPEND + else { + /* Just noise, going back in SUSPEND mode, reference manual 22.4.5, + table 169.*/ + STM32_USB->CNTR |= CNTR_LP_MODE; + } +#endif + STM32_USB->ISTR = ~ISTR_WKUP; + } + + /* SOF handling.*/ + if (istr & ISTR_SOF) { + _usb_isr_invoke_sof_cb(usbp); + STM32_USB->ISTR = ~ISTR_SOF; + } + + /* Endpoint events handling.*/ + while (istr & ISTR_CTR) { + uint32_t ep; + uint32_t epr = STM32_USB->EPR[ep = istr & ISTR_EP_ID_MASK]; + const USBEndpointConfig *epcp = usbp->epc[ep]; + + if (epr & EPR_CTR_TX) { + /* IN endpoint, transmission.*/ + EPR_CLEAR_CTR_TX(ep); + if (epcp->ep_mode & USB_EP_MODE_PACKET) { + /* Packet mode, just invokes the callback.*/ + _usb_isr_invoke_in_cb(usbp, ep); + } + else { + /* Transaction mode.*/ + n = (size_t)USB_GET_DESCRIPTOR(ep)->TXCOUNT0; + epcp->in_state->txbuf += n; + epcp->in_state->txcnt += n; + epcp->in_state->txsize -= n; + if (epcp->in_state->txsize > 0) { + /* Transfer not completed, there are more packets to send.*/ + if (epcp->in_state->txsize > epcp->in_maxsize) + n = epcp->in_maxsize; + else + n = epcp->in_state->txsize; + usb_lld_write_packet_buffer(usbp, ep, epcp->in_state->txbuf, n); + usb_lld_start_in(usbp, ep); + } + else { + /* Transfer completed, invokes the callback.*/ + _usb_isr_invoke_in_cb(usbp, ep); + } + } + } + if (epr & EPR_CTR_RX) { + EPR_CLEAR_CTR_RX(ep); + /* OUT endpoint, receive.*/ + if (epr & EPR_SETUP) { + /* Setup packets handling, setup packets are handled using a + specific callback.*/ + _usb_isr_invoke_setup_cb(usbp, ep); + } + else if (epcp->ep_mode & USB_EP_MODE_PACKET) { + /* Packet mode, just invokes the callback.*/ + _usb_isr_invoke_out_cb(usbp, ep); + } + else { + /* Transaction mode.*/ + n = usb_lld_read_packet_buffer(usbp, ep, + epcp->out_state->rxbuf, + epcp->out_state->rxsize); + usb_lld_start_out(usbp, ep); + epcp->out_state->rxbuf += n; + epcp->out_state->rxcnt += n; + epcp->out_state->rxsize -= n; + epcp->out_state->rxpkts -= 1; + if (epcp->out_state->rxpkts > 0) { + /* Transfer not completed, there are more packets to receive.*/ + EPR_SET_STAT_RX(ep, EPR_STAT_RX_VALID); + } + else { + /* Transfer completed, invokes the callback.*/ + _usb_isr_invoke_out_cb(usbp, ep); + } + } + } + istr = STM32_USB->ISTR; + } + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level USB driver initialization. + * + * @notapi + */ +void usb_lld_init(void) { + + /* Driver initialization.*/ + usbObjectInit(&USBD1); +} + +/** + * @brief Configures and activates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_start(USBDriver *usbp) { + + if (usbp->state == USB_STOP) { + /* Clock activation.*/ +#if STM32_USB_USE_USB1 + if (&USBD1 == usbp) { + /* USB clock enabled.*/ + rccEnableUSB(FALSE); + /* Powers up the transceiver while holding the USB in reset state.*/ + STM32_USB->CNTR = CNTR_FRES; + /* Enabling the USB IRQ vectors, this also gives enough time to allow + the transceiver power up (1uS).*/ + nvicEnableVector(19, + CORTEX_PRIORITY_MASK(STM32_USB_USB1_HP_IRQ_PRIORITY)); + nvicEnableVector(20, + CORTEX_PRIORITY_MASK(STM32_USB_USB1_LP_IRQ_PRIORITY)); + /* Releases the USB reset.*/ + STM32_USB->CNTR = 0; + } +#endif + /* Reset procedure enforced on driver start.*/ + _usb_reset(usbp); + } + /* Configuration.*/ +} + +/** + * @brief Deactivates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_stop(USBDriver *usbp) { + + /* If in ready state then disables the USB clock.*/ + if (usbp->state == USB_STOP) { +#if STM32_USB_USE_USB1 + if (&USBD1 == usbp) { + nvicDisableVector(19); + nvicDisableVector(20); + STM32_USB->CNTR = CNTR_PDWN | CNTR_FRES; + rccDisableUSB(FALSE); + } +#endif + } +} + +/** + * @brief USB low level reset routine. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_reset(USBDriver *usbp) { + uint32_t cntr; + + /* Post reset initialization.*/ + STM32_USB->BTABLE = 0; + STM32_USB->ISTR = 0; + STM32_USB->DADDR = DADDR_EF; + cntr = /*CNTR_ESOFM | */ CNTR_RESETM | CNTR_SUSPM | + CNTR_WKUPM | /*CNTR_ERRM | CNTR_PMAOVRM |*/ CNTR_CTRM; + /* The SOF interrupt is only enabled if a callback is defined for + this service because it is an high rate source.*/ + if (usbp->config->sof_cb != NULL) + cntr |= CNTR_SOFM; + STM32_USB->CNTR = cntr; + + /* Resets the packet memory allocator.*/ + pm_reset(usbp); + + /* EP0 initialization.*/ + usbp->epc[0] = &ep0config; + usb_lld_init_endpoint(usbp, 0); +} + +/** + * @brief Sets the USB address. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_set_address(USBDriver *usbp) { + + STM32_USB->DADDR = (uint32_t)(usbp->address) | DADDR_EF; +} + +/** + * @brief Enables an endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { + uint16_t nblocks, epr; + stm32_usb_descriptor_t *dp; + const USBEndpointConfig *epcp = usbp->epc[ep]; + + /* Setting the endpoint type.*/ + switch (epcp->ep_mode & USB_EP_MODE_TYPE) { + case USB_EP_MODE_TYPE_ISOC: + epr = EPR_EP_TYPE_ISO; + break; + case USB_EP_MODE_TYPE_BULK: + epr = EPR_EP_TYPE_BULK; + break; + case USB_EP_MODE_TYPE_INTR: + epr = EPR_EP_TYPE_INTERRUPT; + break; + default: + epr = EPR_EP_TYPE_CONTROL; + } + + /* IN endpoint settings, always in NAK mode initially.*/ + if (epcp->in_cb != NULL) + epr |= EPR_STAT_TX_NAK; + + /* OUT endpoint settings. If the endpoint is in packet mode then it must + start ready to accept data else it must start in NAK mode.*/ + if (epcp->out_cb != NULL) { + if (epcp->ep_mode & USB_EP_MODE_PACKET) { + usbp->receiving |= (1 << ep); + epr |= EPR_STAT_RX_VALID; + } + else + epr |= EPR_STAT_RX_NAK; + } + + /* EPxR register setup.*/ + EPR_SET(ep, epr | ep); + EPR_TOGGLE(ep, epr); + + /* Endpoint size and address initialization.*/ + if (epcp->out_maxsize > 62) + nblocks = (((((epcp->out_maxsize - 1) | 0x1f) + 1) / 32) << 10) | + 0x8000; + else + nblocks = ((((epcp->out_maxsize - 1) | 1) + 1) / 2) << 10; + dp = USB_GET_DESCRIPTOR(ep); + dp->TXCOUNT0 = 0; + dp->RXCOUNT0 = nblocks; + dp->TXADDR0 = pm_alloc(usbp, epcp->in_maxsize); + dp->RXADDR0 = pm_alloc(usbp, epcp->out_maxsize); +} + +/** + * @brief Disables all the active endpoints except the endpoint zero. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_disable_endpoints(USBDriver *usbp) { + unsigned i; + + /* Resets the packet memory allocator.*/ + pm_reset(usbp); + + /* Disabling all endpoints.*/ + for (i = 1; i <= USB_ENDOPOINTS_NUMBER; i++) { + EPR_TOGGLE(i, 0); + EPR_SET(i, 0); + } +} + +/** + * @brief Returns the status of an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The endpoint status. + * @retval EP_STATUS_DISABLED The endpoint is not active. + * @retval EP_STATUS_STALLED The endpoint is stalled. + * @retval EP_STATUS_ACTIVE The endpoint is active. + * + * @notapi + */ +usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + switch (STM32_USB->EPR[ep] & EPR_STAT_RX_MASK) { + case EPR_STAT_RX_DIS: + return EP_STATUS_DISABLED; + case EPR_STAT_RX_STALL: + return EP_STATUS_STALLED; + default: + return EP_STATUS_ACTIVE; + } +} + +/** + * @brief Returns the status of an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The endpoint status. + * @retval EP_STATUS_DISABLED The endpoint is not active. + * @retval EP_STATUS_STALLED The endpoint is stalled. + * @retval EP_STATUS_ACTIVE The endpoint is active. + * + * @notapi + */ +usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + switch (STM32_USB->EPR[ep] & EPR_STAT_TX_MASK) { + case EPR_STAT_TX_DIS: + return EP_STATUS_DISABLED; + case EPR_STAT_TX_STALL: + return EP_STATUS_STALLED; + default: + return EP_STATUS_ACTIVE; + } +} + +/** + * @brief Reads a setup packet from the dedicated packet buffer. + * @details This function must be invoked in the context of the @p setup_cb + * callback in order to read the received setup packet. + * @pre In order to use this function the endpoint must have been + * initialized as a control endpoint. + * @post The endpoint is ready to accept another packet. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the packet data + * + * @notapi + */ +void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { + uint32_t *pmap; + stm32_usb_descriptor_t *udp; + uint32_t n; + + (void)usbp; + udp = USB_GET_DESCRIPTOR(ep); + pmap = USB_ADDR2PTR(udp->RXADDR0); + for (n = 0; n < 4; n++) { + *(uint16_t *)buf = (uint16_t)*pmap++; + buf += 2; + } +} + +/** + * @brief Reads from a dedicated packet buffer. + * @pre In order to use this function he endpoint must have been + * initialized in packet mode. + * @note This function can be invoked both in thread and IRQ context. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the packet data + * @param[in] n maximum number of bytes to copy. This value must + * not exceed the maximum packet size for this endpoint. + * @return The received packet size regardless the specified + * @p n parameter. + * @retval 0 Zero size packet received. + * + * @notapi + */ +size_t usb_lld_read_packet_buffer(USBDriver *usbp, usbep_t ep, + uint8_t *buf, size_t n) { + uint32_t *pmap; + stm32_usb_descriptor_t *udp; + size_t count; + + (void)usbp; + udp = USB_GET_DESCRIPTOR(ep); + pmap = USB_ADDR2PTR(udp->RXADDR0); + count = (size_t)udp->RXCOUNT0 & RXCOUNT_COUNT_MASK; + if (n > count) + n = count; + n = (n + 1) / 2; + while (n > 0) { + *(uint16_t *)buf = (uint16_t)*pmap++; + buf += 2; + n--; + } + return count; +} + +/** + * @brief Writes to a dedicated packet buffer. + * @pre In order to use this function he endpoint must have been + * initialized in packet mode. + * @note This function can be invoked both in thread and IRQ context. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[in] buf buffer where to fetch the packet data + * @param[in] n maximum number of bytes to copy. This value must + * not exceed the maximum packet size for this endpoint. + * + * @notapi + */ +void usb_lld_write_packet_buffer(USBDriver *usbp, usbep_t ep, + const uint8_t *buf, size_t n) { + uint32_t *pmap; + stm32_usb_descriptor_t *udp; + + (void)usbp; + udp = USB_GET_DESCRIPTOR(ep); + pmap = USB_ADDR2PTR(udp->TXADDR0); + udp->TXCOUNT0 = (uint16_t)n; + n = (n + 1) / 2; + while (n > 0) { + *pmap++ = *(uint16_t *)buf; + buf += 2; + n--; + } +} + +/** + * @brief Prepares for a receive operation. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the received data + * @param[in] n maximum number of bytes to copy + * + * @notapi + */ +void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep, + uint8_t *buf, size_t n) { + USBOutEndpointState *osp = usbp->epc[ep]->out_state; + + osp->rxbuf = buf; + osp->rxsize = n; + osp->rxcnt = 0; + if (osp->rxsize == 0) /* Special case for zero sized packets.*/ + osp->rxpkts = 1; + else + osp->rxpkts = (uint16_t)((n + usbp->epc[ep]->out_maxsize - 1) / + usbp->epc[ep]->out_maxsize); +} + +/** + * @brief Prepares for a transmit operation. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[in] buf buffer where to fetch the data to be transmitted + * @param[in] n maximum number of bytes to copy + * + * @notapi + */ +void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep, + const uint8_t *buf, size_t n) { + USBInEndpointState *isp = usbp->epc[ep]->in_state; + + isp->txbuf = buf; + isp->txsize = n; + isp->txcnt = 0; + if (n > (size_t)usbp->epc[ep]->in_maxsize) + n = (size_t)usbp->epc[ep]->in_maxsize; + usb_lld_write_packet_buffer(usbp, ep, buf, n); +} + +/** + * @brief Starts a receive operation on an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + + EPR_SET_STAT_RX(ep, EPR_STAT_RX_VALID); +} + +/** + * @brief Starts a transmit operation on an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_start_in(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + + EPR_SET_STAT_TX(ep, EPR_STAT_TX_VALID); +} + +/** + * @brief Brings an OUT endpoint in the stalled state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + + EPR_SET_STAT_RX(ep, EPR_STAT_RX_STALL); +} + +/** + * @brief Brings an IN endpoint in the stalled state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + + EPR_SET_STAT_TX(ep, EPR_STAT_TX_STALL); +} + +/** + * @brief Brings an OUT endpoint in the active state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + + /* Makes sure to not put to NAK an endpoint that is already + transferring.*/ + if ((STM32_USB->EPR[ep] & EPR_STAT_RX_MASK) != EPR_STAT_RX_VALID) + EPR_SET_STAT_TX(ep, EPR_STAT_RX_NAK); +} + +/** + * @brief Brings an IN endpoint in the active state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + + /* Makes sure to not put to NAK an endpoint that is already + transferring.*/ + if ((STM32_USB->EPR[ep] & EPR_STAT_TX_MASK) != EPR_STAT_TX_VALID) + EPR_SET_STAT_TX(ep, EPR_STAT_TX_NAK); +} + +#endif /* HAL_USE_USB */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/USBv1/usb_lld.h b/Project/os/hal/platforms/STM32/USBv1/usb_lld.h new file mode 100644 index 0000000..84b4aca --- /dev/null +++ b/Project/os/hal/platforms/STM32/USBv1/usb_lld.h @@ -0,0 +1,407 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/USBv1/usb_lld.h + * @brief STM32 USB subsystem low level driver header. + * + * @addtogroup USB + * @{ + */ + +#ifndef _USB_LLD_H_ +#define _USB_LLD_H_ + +#if HAL_USE_USB || defined(__DOXYGEN__) + +#include "stm32_usb.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Maximum endpoint address. + */ +#define USB_MAX_ENDPOINTS USB_ENDOPOINTS_NUMBER + +/** + * @brief This device requires the address change after the status packet. + */ +#define USB_SET_ADDRESS_MODE USB_LATE_SET_ADDRESS + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief USB1 driver enable switch. + * @details If set to @p TRUE the support for USB1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_USB_USE_USB1) || defined(__DOXYGEN__) +#define STM32_USB_USE_USB1 TRUE +#endif + +/** + * @brief Enables the USB device low power mode on suspend. + */ +#if !defined(STM32_USB_LOW_POWER_ON_SUSPEND) || defined(__DOXYGEN__) +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#endif + +/** + * @brief USB1 interrupt priority level setting. + */ +#if !defined(STM32_USB_USB1_HP_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 +#endif + +/** + * @brief USB1 interrupt priority level setting. + */ +#if !defined(STM32_USB_USB1_LP_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_USB_USE_USB1 && !STM32_HAS_USB +#error "USB not present in the selected device" +#endif + +#if !STM32_USB_USE_USB1 +#error "USB driver activated but no USB peripheral assigned" +#endif + +#if STM32_USBCLK != 48000000 +#error "the USB driver requires a 48MHz clock" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an endpoint state structure. + */ +typedef struct { + /** + * @brief Pointer to the transmission buffer. + */ + const uint8_t *txbuf; + /** + * @brief Requested transmit transfer size. + */ + size_t txsize; + /** + * @brief Transmitted bytes so far. + */ + size_t txcnt; +} USBInEndpointState; + +/** + * @brief Type of an endpoint state structure. + */ +typedef struct { + /** + * @brief Number of packets to receive. + */ + uint16_t rxpkts; + /** + * @brief Pointer to the receive buffer. + */ + uint8_t *rxbuf; + /** + * @brief Requested receive transfer size. + */ + size_t rxsize; + /** + * @brief Received bytes so far. + */ + size_t rxcnt; +} USBOutEndpointState; + +/** + * @brief Type of an USB endpoint configuration structure. + * @note Platform specific restrictions may apply to endpoints. + */ +typedef struct { + /** + * @brief Type and mode of the endpoint. + */ + uint32_t ep_mode; + /** + * @brief Setup packet notification callback. + * @details This callback is invoked when a setup packet has been + * received. + * @post The application must immediately call @p usbReadPacket() in + * order to access the received packet. + * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL + * endpoints, it should be set to @p NULL for other endpoint + * types. + */ + usbepcallback_t setup_cb; + /** + * @brief IN endpoint notification callback. + * @details This field must be set to @p NULL if the IN endpoint is not + * used. + */ + usbepcallback_t in_cb; + /** + * @brief OUT endpoint notification callback. + * @details This field must be set to @p NULL if the OUT endpoint is not + * used. + */ + usbepcallback_t out_cb; + /** + * @brief IN endpoint maximum packet size. + * @details This field must be set to zero if the IN endpoint is not + * used. + */ + uint16_t in_maxsize; + /** + * @brief OUT endpoint maximum packet size. + * @details This field must be set to zero if the OUT endpoint is not + * used. + */ + uint16_t out_maxsize; + /** + * @brief @p USBEndpointState associated to the IN endpoint. + * @details This structure maintains the state of the IN endpoint when + * the endpoint is not in packet mode. Endpoints configured in + * packet mode must set this field to @p NULL. + */ + USBInEndpointState *in_state; + /** + * @brief @p USBEndpointState associated to the OUT endpoint. + * @details This structure maintains the state of the OUT endpoint when + * the endpoint is not in packet mode. Endpoints configured in + * packet mode must set this field to @p NULL. + */ + USBOutEndpointState *out_state; + /* End of the mandatory fields.*/ +} USBEndpointConfig; + +/** + * @brief Type of an USB driver configuration structure. + */ +typedef struct { + /** + * @brief USB events callback. + * @details This callback is invoked when an USB driver event is registered. + */ + usbeventcb_t event_cb; + /** + * @brief Device GET_DESCRIPTOR request callback. + * @note This callback is mandatory and cannot be set to @p NULL. + */ + usbgetdescriptor_t get_descriptor_cb; + /** + * @brief Requests hook callback. + * @details This hook allows to be notified of standard requests or to + * handle non standard requests. + */ + usbreqhandler_t requests_hook_cb; + /** + * @brief Start Of Frame callback. + */ + usbcallback_t sof_cb; + /* End of the mandatory fields.*/ +} USBConfig; + +/** + * @brief Structure representing an USB driver. + */ +struct USBDriver { + /** + * @brief Driver state. + */ + usbstate_t state; + /** + * @brief Current configuration data. + */ + const USBConfig *config; + /** + * @brief Field available to user, it can be used to associate an + * application-defined handler to the USB driver. + */ + void *param; + /** + * @brief Bit map of the transmitting IN endpoints. + */ + uint16_t transmitting; + /** + * @brief Bit map of the receiving OUT endpoints. + */ + uint16_t receiving; + /** + * @brief Active endpoints configurations. + */ + const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1]; + /** + * @brief Endpoint 0 state. + */ + usbep0state_t ep0state; + /** + * @brief Next position in the buffer to be transferred through endpoint 0. + */ + uint8_t *ep0next; + /** + * @brief Number of bytes yet to be transferred through endpoint 0. + */ + size_t ep0n; + /** + * @brief Endpoint 0 end transaction callback. + */ + usbcallback_t ep0endcb; + /** + * @brief Setup packet buffer. + */ + uint8_t setup[8]; + /** + * @brief Current USB device status. + */ + uint16_t status; + /** + * @brief Assigned USB address. + */ + uint8_t address; + /** + * @brief Current USB device configuration. + */ + uint8_t configuration; +#if defined(USB_DRIVER_EXT_FIELDS) + USB_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the next address in the packet memory. + */ + uint32_t pmnext; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Fetches a 16 bits word value from an USB message. + * + * @param[in] p pointer to the 16 bits word + * + * @notapi + */ +#define usb_lld_fetch_word(p) (*(uint16_t *)(p)) + +/** + * @brief Returns the current frame number. + * + * @param[in] usbp pointer to the @p USBDriver object + * @return The current frame number. + * + * @notapi + */ +#define usb_lld_get_frame_number(usbp) (STM32_USB->FNR & FNR_FN_MASK) + +/** + * @brief Returns the exact size of a receive transaction. + * @details The received size can be different from the size specified in + * @p usbStartReceiveI() because the last packet could have a size + * different from the expected one. + * @pre The OUT endpoint must have been configured in transaction mode + * in order to use this function. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return Received data size. + * + * @notapi + */ +#define usb_lld_get_transaction_size(usbp, ep) \ + ((usbp)->epc[ep]->out_state->rxcnt) + +/** + * @brief Returns the exact size of a received packet. + * @pre The OUT endpoint must have been configured in packet mode + * in order to use this function. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return Received data size. + * + * @notapi + */ +#define usb_lld_get_packet_size(usbp, ep) \ + ((size_t)USB_GET_DESCRIPTOR(ep)->RXCOUNT & RXCOUNT_COUNT_MASK) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_USB_USE_USB1 && !defined(__DOXYGEN__) +extern USBDriver USBD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void usb_lld_init(void); + void usb_lld_start(USBDriver *usbp); + void usb_lld_stop(USBDriver *usbp); + void usb_lld_reset(USBDriver *usbp); + void usb_lld_set_address(USBDriver *usbp); + void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep); + void usb_lld_disable_endpoints(USBDriver *usbp); + usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep); + usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep); + void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf); + size_t usb_lld_read_packet_buffer(USBDriver *usbp, usbep_t ep, + uint8_t *buf, size_t n); + void usb_lld_write_packet_buffer(USBDriver *usbp, usbep_t ep, + const uint8_t *buf, size_t n); + void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep, + uint8_t *buf, size_t n); + void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep, + const uint8_t *buf, size_t n); + void usb_lld_start_out(USBDriver *usbp, usbep_t ep); + void usb_lld_start_in(USBDriver *usbp, usbep_t ep); + void usb_lld_stall_out(USBDriver *usbp, usbep_t ep); + void usb_lld_stall_in(USBDriver *usbp, usbep_t ep); + void usb_lld_clear_out(USBDriver *usbp, usbep_t ep); + void usb_lld_clear_in(USBDriver *usbp, usbep_t ep); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_USB */ + +#endif /* _USB_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/can_lld.c b/Project/os/hal/platforms/STM32/can_lld.c new file mode 100644 index 0000000..f9407f4 --- /dev/null +++ b/Project/os/hal/platforms/STM32/can_lld.c @@ -0,0 +1,414 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/can_lld.c + * @brief STM32 CAN subsystem low level driver source. + * + * @addtogroup CAN + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_CAN || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ADC1 driver identifier.*/ +#if STM32_CAN_USE_CAN1 || defined(__DOXYGEN__) +CANDriver CAND1; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief CAN1 TX interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(CAN1_TX_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + /* No more events until a message is transmitted.*/ + CAN1->TSR = CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2; + chSysLockFromIsr(); + while (chSemGetCounterI(&CAND1.txsem) < 0) + chSemSignalI(&CAND1.txsem); + chEvtBroadcastI(&CAND1.txempty_event); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +/* + * @brief CAN1 RX0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(CAN1_RX0_IRQHandler) { + uint32_t rf0r; + + CH_IRQ_PROLOGUE(); + + rf0r = CAN1->RF0R; + if ((rf0r & CAN_RF0R_FMP0) > 0) { + /* No more receive events until the queue 0 has been emptied.*/ + CAN1->IER &= ~CAN_IER_FMPIE0; + chSysLockFromIsr(); + while (chSemGetCounterI(&CAND1.rxsem) < 0) + chSemSignalI(&CAND1.rxsem); + chEvtBroadcastI(&CAND1.rxfull_event); + chSysUnlockFromIsr(); + } + if ((rf0r & CAN_RF0R_FOVR0) > 0) { + /* Overflow events handling.*/ + CAN1->RF0R = CAN_RF0R_FOVR0; + canAddFlagsI(&CAND1, CAN_OVERFLOW_ERROR); + chSysLockFromIsr(); + chEvtBroadcastI(&CAND1.error_event); + chSysUnlockFromIsr(); + } + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN1 RX1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(CAN1_RX1_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + chSysHalt(); /* Not supported (yet).*/ + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief CAN1 SCE interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(CAN1_SCE_IRQHandler) { + uint32_t msr; + + CH_IRQ_PROLOGUE(); + + msr = CAN1->MSR; + CAN1->MSR = CAN_MSR_ERRI | CAN_MSR_WKUI | CAN_MSR_SLAKI; + /* Wakeup event.*/ + if (msr & CAN_MSR_WKUI) { + chSysLockFromIsr(); + chEvtBroadcastI(&CAND1.wakeup_event); + chSysUnlockFromIsr(); + } + /* Error event.*/ + if (msr & CAN_MSR_ERRI) { + canstatus_t flags; + uint32_t esr = CAN1->ESR; + + CAN1->ESR &= ~CAN_ESR_LEC; + flags = (canstatus_t)(esr & 7); + if ((esr & CAN_ESR_LEC) > 0) + flags |= CAN_FRAMING_ERROR; + chSysLockFromIsr(); + canAddFlagsI(&CAND1, flags | (canstatus_t)(flags < 16)); + chEvtBroadcastI(&CAND1.error_event); + chSysUnlockFromIsr(); + } + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level CAN driver initialization. + * + * @notapi + */ +void can_lld_init(void) { + +#if STM32_CAN_USE_CAN1 + /* Driver initialization.*/ + canObjectInit(&CAND1); + CAND1.can = CAN1; +#endif +} + +/** + * @brief Configures and activates the CAN peripheral. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_start(CANDriver *canp) { + + /* Clock activation.*/ +#if STM32_CAN_USE_CAN1 + if (&CAND1 == canp) { + nvicEnableVector(CAN1_TX_IRQn, + CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY)); + nvicEnableVector(CAN1_RX0_IRQn, + CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY)); + nvicEnableVector(CAN1_RX1_IRQn, + CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY)); + nvicEnableVector(CAN1_SCE_IRQn, + CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY)); + rccEnableCAN1(FALSE); + } +#endif + + /* Entering initialization mode. */ + canp->state = CAN_STARTING; + canp->can->MCR = CAN_MCR_INRQ; + while ((canp->can->MSR & CAN_MSR_INAK) == 0) + chThdSleepS(1); + /* BTR initialization.*/ + canp->can->BTR = canp->config->btr; + /* MCR initialization.*/ + canp->can->MCR = canp->config->mcr; + /* Filters initialization.*/ + canp->can->FMR |= CAN_FMR_FINIT; + if (canp->config->num > 0) { + uint32_t i, fmask; + CAN_FilterRegister_TypeDef *cfp; + + canp->can->FA1R = 0; + canp->can->FM1R = 0; + canp->can->FS1R = 0; + canp->can->FFA1R = 0; + cfp = canp->can->sFilterRegister; + fmask = 1; + for (i = 0; i < STM32_CAN_MAX_FILTERS; i++) { + if (i < canp->config->num) { + if (canp->config->filters[i].mode) + canp->can->FM1R |= fmask; + if (canp->config->filters[i].scale) + canp->can->FS1R |= fmask; + if (canp->config->filters[i].assignment) + canp->can->FFA1R |= fmask; + cfp->FR1 = canp->config->filters[i].register1; + cfp->FR2 = canp->config->filters[i].register2; + canp->can->FA1R |= fmask; + } + else { + cfp->FR1 = 0; + cfp->FR2 = 0; + } + /* Gives a chance for preemption since this is a rather long loop.*/ + chSysUnlock(); + cfp++; + fmask <<= 1; + chSysLock(); + } + } + else { + /* Setup a default filter.*/ + canp->can->sFilterRegister[0].FR1 = 0; + canp->can->sFilterRegister[0].FR2 = 0; + canp->can->FM1R = 0; + canp->can->FFA1R = 0; + canp->can->FS1R = 1; + canp->can->FA1R = 1; + } + canp->can->FMR &= ~CAN_FMR_FINIT; + /* Interrupt sources initialization.*/ + canp->can->IER = CAN_IER_TMEIE | CAN_IER_FMPIE0 | CAN_IER_FMPIE1 | + CAN_IER_WKUIE | CAN_IER_ERRIE | CAN_IER_LECIE | + CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE | + CAN_IER_FOVIE0 | CAN_IER_FOVIE1; +} + +/** + * @brief Deactivates the CAN peripheral. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_stop(CANDriver *canp) { + + /* If in ready state then disables the CAN peripheral.*/ + if (canp->state == CAN_READY) { +#if STM32_CAN_USE_CAN1 + if (&CAND1 == canp) { + CAN1->MCR = 0x00010002; /* Register reset value. */ + CAN1->IER = 0x00000000; /* All sources disabled. */ + nvicDisableVector(CAN1_TX_IRQn); + nvicDisableVector(CAN1_RX0_IRQn); + nvicDisableVector(CAN1_RX1_IRQn); + nvicDisableVector(CAN1_SCE_IRQn); + rccDisableCAN1(FALSE); + } +#endif + } +} + +/** + * @brief Determines whether a frame can be transmitted. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @return The queue space availability. + * @retval FALSE no space in the transmit queue. + * @retval TRUE transmit slot available. + * + * @notapi + */ +bool_t can_lld_can_transmit(CANDriver *canp) { + + return (canp->can->TSR & CAN_TSR_TME) != 0; +} + +/** + * @brief Inserts a frame into the transmit queue. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] ctfp pointer to the CAN frame to be transmitted + * + * @notapi + */ +void can_lld_transmit(CANDriver *canp, const CANTxFrame *ctfp) { + uint32_t tir; + CAN_TxMailBox_TypeDef *tmbp; + + /* Pointer to a free transmission mailbox.*/ + tmbp = &canp->can->sTxMailBox[(canp->can->TSR & CAN_TSR_CODE) >> 24]; + + /* Preparing the message.*/ + if (ctfp->IDE) + tir = ((uint32_t)ctfp->EID << 3) | ((uint32_t)ctfp->RTR << 1) | + CAN_TI0R_IDE; + else + tir = ((uint32_t)ctfp->SID << 21) | ((uint32_t)ctfp->RTR << 1); + tmbp->TDTR = ctfp->DLC; + tmbp->TDLR = ctfp->data32[0]; + tmbp->TDHR = ctfp->data32[1]; + tmbp->TIR = tir | CAN_TI0R_TXRQ; +} + +/** + * @brief Determines whether a frame has been received. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @return The queue space availability. + * @retval FALSE no space in the transmit queue. + * @retval TRUE transmit slot available. + * + * @notapi + */ +bool_t can_lld_can_receive(CANDriver *canp) { + + return (canp->can->RF0R & CAN_RF0R_FMP0) > 0; +} + +/** + * @brief Receives a frame from the input queue. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[out] crfp pointer to the buffer where the CAN frame is copied + * + * @notapi + */ +void can_lld_receive(CANDriver *canp, CANRxFrame *crfp) { + uint32_t r; + + /* Fetches the message.*/ + r = canp->can->sFIFOMailBox[0].RIR; + crfp->RTR = (r & CAN_RI0R_RTR) >> 1; + crfp->IDE = (r & CAN_RI0R_IDE) >> 2; + if (crfp->IDE) + crfp->EID = r >> 3; + else + crfp->SID = r >> 21; + r = canp->can->sFIFOMailBox[0].RDTR; + crfp->DLC = r & CAN_RDT0R_DLC; + crfp->FMI = (uint8_t)(r >> 8); + crfp->TIME = (uint16_t)(r >> 16); + crfp->data32[0] = canp->can->sFIFOMailBox[0].RDLR; + crfp->data32[1] = canp->can->sFIFOMailBox[0].RDHR; + + /* Releases the mailbox.*/ + canp->can->RF0R = CAN_RF0R_RFOM0; + + /* If the queue is empty re-enables the interrupt in order to generate + events again.*/ + if ((canp->can->RF0R & CAN_RF0R_FMP0) == 0) + canp->can->IER |= CAN_IER_FMPIE0; +} + +#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__) +/** + * @brief Enters the sleep mode. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_sleep(CANDriver *canp) { + + canp->can->MCR |= CAN_MCR_SLEEP; +} + +/** + * @brief Enforces leaving the sleep mode. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_wakeup(CANDriver *canp) { + + canp->can->MCR &= ~CAN_MCR_SLEEP; +} +#endif /* CAN_USE_SLEEP_MODE */ + +#endif /* HAL_USE_CAN */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/can_lld.h b/Project/os/hal/platforms/STM32/can_lld.h new file mode 100644 index 0000000..7f9ef19 --- /dev/null +++ b/Project/os/hal/platforms/STM32/can_lld.h @@ -0,0 +1,338 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/can_lld.h + * @brief STM32 CAN subsystem low level driver header. + * + * @addtogroup CAN + * @{ + */ + +#ifndef _CAN_LLD_H_ +#define _CAN_LLD_H_ + +#if HAL_USE_CAN || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * The following macros from the ST header file are replaced with better + * equivalents. + */ +#undef CAN_BTR_BRP +#undef CAN_BTR_TS1 +#undef CAN_BTR_TS2 +#undef CAN_BTR_SJW + +/** + * @brief This switch defines whether the driver implementation supports + * a low power switch mode with automatic an wakeup feature. + */ +#define CAN_SUPPORTS_SLEEP TRUE + +/** + * @name CAN registers helper macros + * @{ + */ +#define CAN_BTR_BRP(n) (n) /**< @brief BRP field macro.*/ +#define CAN_BTR_TS1(n) ((n) << 16) /**< @brief TS1 field macro.*/ +#define CAN_BTR_TS2(n) ((n) << 20) /**< @brief TS2 field macro.*/ +#define CAN_BTR_SJW(n) ((n) << 24) /**< @brief SJW field macro.*/ + +#define CAN_IDE_STD 0 /**< @brief Standard id. */ +#define CAN_IDE_EXT 1 /**< @brief Extended id. */ + +#define CAN_RTR_DATA 0 /**< @brief Data frame. */ +#define CAN_RTR_REMOTE 1 /**< @brief Remote frame. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief CAN1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_CAN_USE_CAN1) || defined(__DOXYGEN__) +#define STM32_CAN_USE_CAN1 TRUE +#endif + +/** + * @brief CAN1 interrupt priority level setting. + */ +#if !defined(STM32_CAN_CAN1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_CAN_USE_CAN1 && !STM32_HAS_CAN1 +#error "CAN1 not present in the selected device" +#endif + +#if !STM32_CAN_USE_CAN1 +#error "CAN driver activated but no CAN peripheral assigned" +#endif + +#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP +#error "CAN sleep mode not supported in this architecture" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief CAN status flags. + */ +typedef uint32_t canstatus_t; + +/** + * @brief CAN transmission frame. + * @note Accessing the frame data as word16 or word32 is not portable because + * machine data endianness, it can be still useful for a quick filling. + */ +typedef struct { + struct { + uint8_t DLC:4; /**< @brief Data length. */ + uint8_t RTR:1; /**< @brief Frame type. */ + uint8_t IDE:1; /**< @brief Identifier type. */ + }; + union { + struct { + uint32_t SID:11; /**< @brief Standard identifier.*/ + }; + struct { + uint32_t EID:29; /**< @brief Extended identifier.*/ + }; + }; + union { + uint8_t data8[8]; /**< @brief Frame data. */ + uint16_t data16[4]; /**< @brief Frame data. */ + uint32_t data32[2]; /**< @brief Frame data. */ + }; +} CANTxFrame; + +/** + * @brief CAN received frame. + * @note Accessing the frame data as word16 or word32 is not portable because + * machine data endianness, it can be still useful for a quick filling. + */ +typedef struct { + struct { + uint8_t FMI; /**< @brief Filter id. */ + uint16_t TIME; /**< @brief Time stamp. */ + }; + struct { + uint8_t DLC:4; /**< @brief Data length. */ + uint8_t RTR:1; /**< @brief Frame type. */ + uint8_t IDE:1; /**< @brief Identifier type. */ + }; + union { + struct { + uint32_t SID:11; /**< @brief Standard identifier.*/ + }; + struct { + uint32_t EID:29; /**< @brief Extended identifier.*/ + }; + }; + union { + uint8_t data8[8]; /**< @brief Frame data. */ + uint16_t data16[4]; /**< @brief Frame data. */ + uint32_t data32[2]; /**< @brief Frame data. */ + }; +} CANRxFrame; + +/** + * @brief CAN filter. + * @note Refer to the STM32 reference manual for info about filters. + */ +typedef struct { + /** + * @brief Filter mode. + * @note This bit represent the CAN_FM1R register bit associated to this + * filter (0=mask mode, 1=list mode). + */ + uint32_t mode:1; + /** + * @brief Filter scale. + * @note This bit represent the CAN_FS1R register bit associated to this + * filter (0=16 bits mode, 1=32 bits mode). + */ + uint32_t scale:1; + /** + * @brief Filter mode. + * @note This bit represent the CAN_FFA1R register bit associated to this + * filter, must be set to zero in this version of the driver. + */ + uint32_t assignment:1; + /** + * @brief Filter register 1 (identifier). + */ + uint32_t register1; + /** + * @brief Filter register 2 (mask/identifier depending on mode=0/1). + */ + uint32_t register2; +} CANFilter; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief CAN MCR register initialization data. + * @note Some bits in this register are enforced by the driver regardless + * their status in this field. + */ + uint32_t mcr; + /** + * @brief CAN BTR register initialization data. + * @note Some bits in this register are enforced by the driver regardless + * their status in this field. + */ + uint32_t btr; + /** + * @brief Number of elements into the filters array. + * @note By setting this field to zero a default filter is enabled that + * allows all frames, this should be adequate for simple applications. + */ + uint32_t num; + /** + * @brief Pointer to an array of @p CANFilter structures. + * @note This field can be set to @p NULL if the field @p num is set to + * zero. + */ + const CANFilter *filters; +} CANConfig; + +/** + * @brief Structure representing an CAN driver. + */ +typedef struct { + /** + * @brief Driver state. + */ + canstate_t state; + /** + * @brief Current configuration data. + */ + const CANConfig *config; + /** + * @brief Transmission queue semaphore. + */ + Semaphore txsem; + /** + * @brief Receive queue semaphore. + */ + Semaphore rxsem; + /** + * @brief One or more frames become available. + * @note After broadcasting this event it will not be broadcasted again + * until the received frames queue has been completely emptied. It + * is not broadcasted for each received frame. It is + * responsibility of the application to empty the queue by repeatedly + * invoking @p chReceive() when listening to this event. This behavior + * minimizes the interrupt served by the system because CAN traffic. + */ + EventSource rxfull_event; + /** + * @brief One or more transmission slots become available. + */ + EventSource txempty_event; + /** + * @brief A CAN bus error happened. + */ + EventSource error_event; + /** + * @brief Error flags set when an error event is broadcasted. + */ + canstatus_t status; +#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__) + /** + * @brief Entering sleep state event. + */ + EventSource sleep_event; + /** + * @brief Exiting sleep state event. + */ + EventSource wakeup_event; +#endif /* CAN_USE_SLEEP_MODE */ + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the CAN registers. + */ + CAN_TypeDef *can; +} CANDriver; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_CAN_USE_CAN1 && !defined(__DOXYGEN__) +extern CANDriver CAND1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void can_lld_init(void); + void can_lld_start(CANDriver *canp); + void can_lld_stop(CANDriver *canp); + bool_t can_lld_can_transmit(CANDriver *canp); + void can_lld_transmit(CANDriver *canp, const CANTxFrame *crfp); + bool_t can_lld_can_receive(CANDriver *canp); + void can_lld_receive(CANDriver *canp, CANRxFrame *ctfp); +#if CAN_USE_SLEEP_MODE + void can_lld_sleep(CANDriver *canp); + void can_lld_wakeup(CANDriver *canp); +#endif /* CAN_USE_SLEEP_MODE */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_CAN */ + +#endif /* _CAN_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/ext_lld.c b/Project/os/hal/platforms/STM32/ext_lld.c new file mode 100644 index 0000000..8fe4e83 --- /dev/null +++ b/Project/os/hal/platforms/STM32/ext_lld.c @@ -0,0 +1,622 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/ext_lld.c + * @brief STM32 EXT subsystem low level driver source. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EXTD1 driver identifier. + */ +EXTDriver EXTD1; + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief EXTI[0] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI0_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 0); + EXTD1.config->channels[0].cb(&EXTD1, 0); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[1] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI1_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 1); + EXTD1.config->channels[1].cb(&EXTD1, 1); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[2] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI2_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 2); + EXTD1.config->channels[2].cb(&EXTD1, 2); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[3] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI3_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 3); + EXTD1.config->channels[3].cb(&EXTD1, 3); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[4] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI4_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 4); + EXTD1.config->channels[4].cb(&EXTD1, 4); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[5]...EXTI[9] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI9_5_IRQHandler) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9)); + EXTI->PR = pr; + if (pr & (1 << 5)) + EXTD1.config->channels[5].cb(&EXTD1, 5); + if (pr & (1 << 6)) + EXTD1.config->channels[6].cb(&EXTD1, 6); + if (pr & (1 << 7)) + EXTD1.config->channels[7].cb(&EXTD1, 7); + if (pr & (1 << 8)) + EXTD1.config->channels[8].cb(&EXTD1, 8); + if (pr & (1 << 9)) + EXTD1.config->channels[9].cb(&EXTD1, 9); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[10]...EXTI[15] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI15_10_IRQHandler) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) | + (1 << 15)); + EXTI->PR = pr; + if (pr & (1 << 10)) + EXTD1.config->channels[10].cb(&EXTD1, 10); + if (pr & (1 << 11)) + EXTD1.config->channels[11].cb(&EXTD1, 11); + if (pr & (1 << 12)) + EXTD1.config->channels[12].cb(&EXTD1, 12); + if (pr & (1 << 13)) + EXTD1.config->channels[13].cb(&EXTD1, 13); + if (pr & (1 << 14)) + EXTD1.config->channels[14].cb(&EXTD1, 14); + if (pr & (1 << 15)) + EXTD1.config->channels[15].cb(&EXTD1, 15); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[16] interrupt handler (PVD). + * + * @isr + */ +CH_IRQ_HANDLER(PVD_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 16); + EXTD1.config->channels[16].cb(&EXTD1, 16); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[17] interrupt handler (RTC). + * + * @isr + */ +CH_IRQ_HANDLER(RTCAlarm_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 17); + EXTD1.config->channels[17].cb(&EXTD1, 17); + + CH_IRQ_EPILOGUE(); +} + +#if defined(STM32L1XX_MD) +/** + * @brief EXTI[18] interrupt handler (USB_FS_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 18); + EXTD1.config->channels[18].cb(&EXTD1, 18); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[19] interrupt handler (TAMPER_STAMP). + * + * @isr + */ +CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 19); + EXTD1.config->channels[19].cb(&EXTD1, 19); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[20] interrupt handler (RTC_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 20); + EXTD1.config->channels[20].cb(&EXTD1, 20); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[21]...EXTI[22] interrupt handler (COMP). + * + * @isr + */ +CH_IRQ_HANDLER(COMP_IRQHandler) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 21) | (1 << 22)); + EXTI->PR = pr; + if (pr & (1 << 21)) + EXTD1.config->channels[21].cb(&EXTD1, 21); + if (pr & (1 << 22)) + EXTD1.config->channels[22].cb(&EXTD1, 22); + + CH_IRQ_EPILOGUE(); +} + +#elif defined(STM32F2XX) || defined(STM32F4XX) +/** + * @brief EXTI[18] interrupt handler (OTG_FS_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 18); + EXTD1.config->channels[18].cb(&EXTD1, 18); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[19] interrupt handler (ETH_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 19); + EXTD1.config->channels[19].cb(&EXTD1, 19); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[20] interrupt handler (OTG_HS_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(OTG_HS_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 20); + EXTD1.config->channels[20].cb(&EXTD1, 20); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[21] interrupt handler (TAMPER_STAMP). + * + * @isr + */ +CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 21); + EXTD1.config->channels[21].cb(&EXTD1, 21); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[22] interrupt handler (RTC_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 22); + EXTD1.config->channels[22].cb(&EXTD1, 22); + + CH_IRQ_EPILOGUE(); +} + +#elif defined(STM32F10X_CL) +/** + * @brief EXTI[18] interrupt handler (OTG_FS_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 18); + EXTD1.config->channels[18].cb(&EXTD1, 18); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[19] interrupt handler (ETH_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 19); + EXTD1.config->channels[19].cb(&EXTD1, 19); + + CH_IRQ_EPILOGUE(); +} + +#else +/** + * @brief EXTI[18] interrupt handler (USB_FS_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 18); + EXTD1.config->channels[18].cb(&EXTD1, 18); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level EXT driver initialization. + * + * @notapi + */ +void ext_lld_init(void) { + + /* Driver initialization.*/ + extObjectInit(&EXTD1); +} + +/** + * @brief Configures and activates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_start(EXTDriver *extp) { + unsigned i; + uint32_t imr, emr, rtsr, ftsr; + + if (extp->state == EXT_STOP) { + /* Clock activation.*/ + nvicEnableVector(EXTI0_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY)); + nvicEnableVector(EXTI1_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY)); + nvicEnableVector(EXTI2_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY)); + nvicEnableVector(EXTI3_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY)); + nvicEnableVector(EXTI4_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY)); + nvicEnableVector(EXTI9_5_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY)); + nvicEnableVector(EXTI15_10_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY)); + nvicEnableVector(PVD_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY)); + nvicEnableVector(RTC_Alarm_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY)); +#if defined(STM32L1XX_MD) + /* EXTI vectors specific to STM32L1xx.*/ + nvicEnableVector(USB_FS_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); + nvicEnableVector(TAMPER_STAMP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); + nvicEnableVector(RTC_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY)); + nvicEnableVector(COMP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY)); +#elif defined(STM32F2XX) || defined(STM32F4XX) + /* EXTI vectors specific to STM32F2xx/STM32F4xx.*/ + nvicEnableVector(OTG_FS_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); + nvicEnableVector(ETH_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); + nvicEnableVector(OTG_HS_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY)); + nvicEnableVector(TAMP_STAMP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY)); + nvicEnableVector(RTC_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI22_IRQ_PRIORITY)); +#elif defined(STM32F10X_CL) + /* EXTI vectors specific to STM32F1xx Connectivity Line.*/ + nvicEnableVector(OTG_FS_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); + nvicEnableVector(ETH_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); +#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD_VL) + /* EXTI vectors specific to STM32F1xx Value Line.*/ +#else + /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/ + nvicEnableVector(USB_FS_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); +#endif + } + /* Configuration.*/ + imr = emr = rtsr = ftsr = 0; + for (i = 0; i < EXT_MAX_CHANNELS; i++) { + if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) { + if (extp->config->channels[i].cb != NULL) + imr |= (1 << i); + else + emr |= (1 << i); + if (extp->config->channels[i].mode & EXT_CH_MODE_RISING_EDGE) + rtsr |= (1 << i); + if (extp->config->channels[i].mode & EXT_CH_MODE_FALLING_EDGE) + ftsr |= (1 << i); + } + } +#if defined(STM32L1XX_MD) || defined(STM32F2XX) || defined(STM32F4XX) + SYSCFG->EXTICR[0] = extp->config->exti[0]; + SYSCFG->EXTICR[1] = extp->config->exti[1]; + SYSCFG->EXTICR[2] = extp->config->exti[2]; + SYSCFG->EXTICR[3] = extp->config->exti[3]; +#else /* STM32F1XX */ + AFIO->EXTICR[0] = extp->config->exti[0]; + AFIO->EXTICR[1] = extp->config->exti[1]; + AFIO->EXTICR[2] = extp->config->exti[2]; + AFIO->EXTICR[3] = extp->config->exti[3]; +#endif /* STM32F1XX */ + EXTI->SWIER = 0; + EXTI->RTSR = rtsr; + EXTI->FTSR = ftsr; + EXTI->PR = EXT_CHANNELS_MASK; + EXTI->EMR = emr; + EXTI->IMR = imr; +} + +/** + * @brief Deactivates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_stop(EXTDriver *extp) { + + if (extp->state == EXT_ACTIVE) { + nvicDisableVector(EXTI0_IRQn); + nvicDisableVector(EXTI1_IRQn); + nvicDisableVector(EXTI2_IRQn); + nvicDisableVector(EXTI3_IRQn); + nvicDisableVector(EXTI4_IRQn); + nvicDisableVector(EXTI9_5_IRQn); + nvicDisableVector(EXTI15_10_IRQn); + nvicDisableVector(PVD_IRQn); + nvicDisableVector(RTC_Alarm_IRQn); +#if defined(STM32L1XX_MD) + /* EXTI vectors specific to STM32L1xx.*/ + nvicDisableVector(USB_FS_WKUP_IRQn); + nvicDisableVector(TAMPER_STAMP_IRQn); + nvicDisableVector(RTC_WKUP_IRQn); + nvicDisableVector(COMP_IRQn); +#elif defined(STM32F2XX) || defined(STM32F4XX) + /* EXTI vectors specific to STM32F2xx/STM32F4xx.*/ + nvicDisableVector(OTG_FS_WKUP_IRQn); + nvicDisableVector(ETH_WKUP_IRQn); + nvicDisableVector(OTG_HS_WKUP_IRQn); + nvicDisableVector(TAMP_STAMP_IRQn); + nvicDisableVector(RTC_WKUP_IRQn); +#elif defined(STM32F10X_CL) + /* EXTI vectors specific to STM32F1xx Connectivity Line.*/ + nvicDisableVector(OTG_FS_WKUP_IRQn); + nvicDisableVector(ETH_WKUP_IRQn); +#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD_VL) + /* EXTI vectors specific to STM32F1xx Value Line.*/ +#else + /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/ + nvicDisableVector(USB_FS_WKUP_IRQn); +#endif + } + EXTI->EMR = 0; + EXTI->IMR = 0; + EXTI->PR = EXT_CHANNELS_MASK; +} + +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @notapi + */ +void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { + + if (extp->config->channels[channel].cb != NULL) + EXTI->IMR |= (1 << channel); + else + EXTI->EMR |= (1 << channel); + if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE) + EXTI->RTSR |= (1 << channel); + if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE) + EXTI->FTSR |= (1 << channel); +} + +/** + * @brief Disables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be disabled + * + * @notapi + */ +void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) { + + (void)extp; + + EXTI->IMR &= ~(1 << channel); + EXTI->EMR &= ~(1 << channel); + EXTI->RTSR &= ~(1 << channel); + EXTI->FTSR &= ~(1 << channel); + EXTI->PR = (1 << channel); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/ext_lld.h b/Project/os/hal/platforms/STM32/ext_lld.h new file mode 100644 index 0000000..ef1b3fc --- /dev/null +++ b/Project/os/hal/platforms/STM32/ext_lld.h @@ -0,0 +1,287 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/ext_lld.h + * @brief STM32 EXT subsystem low level driver header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_H_ +#define _EXT_LLD_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Available number of EXT channels. + */ +#define EXT_MAX_CHANNELS STM32_EXTI_NUM_CHANNELS + +/** + * @brief Mask of the available channels. + */ +#define EXT_CHANNELS_MASK ((1 << EXT_MAX_CHANNELS) - 1) + +/** + * @name EXTI configuration helpers + * @{ + */ +/** + * @brief EXTI-GPIO association macro. + * @details Helper macro to associate a GPIO to each of the Mx EXTI inputs. + */ +#define EXT_MODE_EXTI(m0, m1, m2, m3, m4, m5, m6, m7, \ + m8, m9, m10, m11, m12, m13, m14, m15) \ + { \ + ((m0) << 0) | ((m1) << 4) | ((m2) << 8) | ((m3) << 12), \ + ((m4) << 0) | ((m5) << 4) | ((m6) << 8) | ((m7) << 12), \ + ((m8) << 0) | ((m9) << 4) | ((m10) << 8) | ((m11) << 12), \ + ((m12) << 0) | ((m13) << 4) | ((m14) << 8) | ((m15) << 12) \ + } + +#define EXT_MODE_GPIOA 0 /**< @brief GPIOA identifier. */ +#define EXT_MODE_GPIOB 1 /**< @brief GPIOB identifier. */ +#define EXT_MODE_GPIOC 2 /**< @brief GPIOC identifier. */ +#define EXT_MODE_GPIOD 3 /**< @brief GPIOD identifier. */ +#define EXT_MODE_GPIOE 4 /**< @brief GPIOE identifier. */ +#define EXT_MODE_GPIOF 5 /**< @brief GPIOF identifier. */ +#define EXT_MODE_GPIOG 6 /**< @brief GPIOG identifier. */ +#define EXT_MODE_GPIOH 7 /**< @brief GPIOH identifier. */ +#define EXT_MODE_GPIOI 8 /**< @brief GPIOI identifier. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI1 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI2 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI3 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI4 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI9..5 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI15..10 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI16 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI17 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI18 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI19 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI20 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI21 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI21_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI21_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI22 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI22_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI22_IRQ_PRIORITY 6 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief EXT channel identifier. + */ +typedef uint32_t expchannel_t; + +/** + * @brief Type of an EXT generic notification callback. + * + * @param[in] extp pointer to the @p EXPDriver object triggering the + * callback + */ +typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); + +/** + * @brief Channel configuration structure. + */ +typedef struct { + /** + * @brief Channel mode. + */ + uint32_t mode; + /** + * @brief Channel callback. + * @details In the STM32 implementation a @p NULL callback pointer is + * valid and configures the channel as an event sources instead + * of an interrupt source. + */ + extcallback_t cb; +} EXTChannelConfig; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Channel configurations. + */ + EXTChannelConfig channels[EXT_MAX_CHANNELS]; + /* End of the mandatory fields.*/ + /** + * @brief Initialization values for EXTICRx registers. + */ + uint16_t exti[4]; +} EXTConfig; + +/** + * @brief Structure representing an EXT driver. + */ +struct EXTDriver { + /** + * @brief Driver state. + */ + extstate_t state; + /** + * @brief Current configuration data. + */ + const EXTConfig *config; + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern EXTDriver EXTD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_init(void); + void ext_lld_start(EXTDriver *extp); + void ext_lld_stop(EXTDriver *extp); + void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); + void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/gpt_lld.c b/Project/os/hal/platforms/STM32/gpt_lld.c new file mode 100644 index 0000000..e9a8791 --- /dev/null +++ b/Project/os/hal/platforms/STM32/gpt_lld.c @@ -0,0 +1,457 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/gpt_lld.c + * @brief STM32 GPT subsystem low level driver source. + * + * @addtogroup GPT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief GPTD1 driver identifier. + * @note The driver GPTD1 allocates the complex timer TIM1 when enabled. + */ +#if STM32_GPT_USE_TIM1 || defined(__DOXYGEN__) +GPTDriver GPTD1; +#endif + +/** + * @brief GPTD2 driver identifier. + * @note The driver GPTD2 allocates the timer TIM2 when enabled. + */ +#if STM32_GPT_USE_TIM2 || defined(__DOXYGEN__) +GPTDriver GPTD2; +#endif + +/** + * @brief GPTD3 driver identifier. + * @note The driver GPTD3 allocates the timer TIM3 when enabled. + */ +#if STM32_GPT_USE_TIM3 || defined(__DOXYGEN__) +GPTDriver GPTD3; +#endif + +/** + * @brief GPTD4 driver identifier. + * @note The driver GPTD4 allocates the timer TIM4 when enabled. + */ +#if STM32_GPT_USE_TIM4 || defined(__DOXYGEN__) +GPTDriver GPTD4; +#endif + +/** + * @brief GPTD5 driver identifier. + * @note The driver GPTD5 allocates the timer TIM5 when enabled. + */ +#if STM32_GPT_USE_TIM5 || defined(__DOXYGEN__) +GPTDriver GPTD5; +#endif + +/** + * @brief GPTD8 driver identifier. + * @note The driver GPTD8 allocates the timer TIM8 when enabled. + */ +#if STM32_GPT_USE_TIM8 || defined(__DOXYGEN__) +GPTDriver GPTD8; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared IRQ handler. + * + * @param[in] gptp pointer to a @p GPTDriver object + */ +static void gpt_lld_serve_interrupt(GPTDriver *gptp) { + + gptp->tim->SR = 0; + if (gptp->state == GPT_ONESHOT) { + gptp->state = GPT_READY; /* Back in GPT_READY state. */ + gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */ + } + gptp->config->callback(gptp); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_GPT_USE_TIM1 +/** + * @brief TIM2 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM1_UP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_GPT_USE_TIM1 */ + +#if STM32_GPT_USE_TIM2 +/** + * @brief TIM2 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM2_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_GPT_USE_TIM2 */ + +#if STM32_GPT_USE_TIM3 +/** + * @brief TIM3 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM3_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_GPT_USE_TIM3 */ + +#if STM32_GPT_USE_TIM4 +/** + * @brief TIM4 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM4_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD4); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_GPT_USE_TIM4 */ + +#if STM32_GPT_USE_TIM5 +/** + * @brief TIM5 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM5_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD5); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_GPT_USE_TIM5 */ + +#if STM32_GPT_USE_TIM8 +/** + * @brief TIM8 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM8_UP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD8); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_GPT_USE_TIM8 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level GPT driver initialization. + * + * @notapi + */ +void gpt_lld_init(void) { + +#if STM32_GPT_USE_TIM1 + /* Driver initialization.*/ + GPTD1.tim = STM32_TIM1; + gptObjectInit(&GPTD1); +#endif + +#if STM32_GPT_USE_TIM2 + /* Driver initialization.*/ + GPTD2.tim = STM32_TIM2; + gptObjectInit(&GPTD2); +#endif + +#if STM32_GPT_USE_TIM3 + /* Driver initialization.*/ + GPTD3.tim = STM32_TIM3; + gptObjectInit(&GPTD3); +#endif + +#if STM32_GPT_USE_TIM4 + /* Driver initialization.*/ + GPTD4.tim = STM32_TIM4; + gptObjectInit(&GPTD4); +#endif + +#if STM32_GPT_USE_TIM5 + /* Driver initialization.*/ + GPTD5.tim = STM32_TIM5; + gptObjectInit(&GPTD5); +#endif + +#if STM32_GPT_USE_TIM8 + /* Driver initialization.*/ + GPTD8.tim = STM32_TIM8; + gptObjectInit(&GPTD8); +#endif +} + +/** + * @brief Configures and activates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_start(GPTDriver *gptp) { + uint16_t psc; + + if (gptp->state == GPT_STOP) { + /* Clock activation.*/ +#if STM32_GPT_USE_TIM1 + if (&GPTD1 == gptp) { + rccEnableTIM1(FALSE); + rccResetTIM1(); + nvicEnableVector(TIM1_UP_IRQn, + CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY)); + gptp->clock = STM32_TIMCLK2; + } +#endif +#if STM32_GPT_USE_TIM2 + if (&GPTD2 == gptp) { + rccEnableTIM2(FALSE); + rccResetTIM2(); + nvicEnableVector(TIM2_IRQn, + CORTEX_PRIORITY_MASK(STM32_GPT_TIM2_IRQ_PRIORITY)); + gptp->clock = STM32_TIMCLK1; + } +#endif +#if STM32_GPT_USE_TIM3 + if (&GPTD3 == gptp) { + rccEnableTIM3(FALSE); + rccResetTIM3(); + nvicEnableVector(TIM3_IRQn, + CORTEX_PRIORITY_MASK(STM32_GPT_TIM3_IRQ_PRIORITY)); + gptp->clock = STM32_TIMCLK1; + } +#endif +#if STM32_GPT_USE_TIM4 + if (&GPTD4 == gptp) { + rccEnableTIM4(FALSE); + rccResetTIM4(); + nvicEnableVector(TIM4_IRQn, + CORTEX_PRIORITY_MASK(STM32_GPT_TIM4_IRQ_PRIORITY)); + gptp->clock = STM32_TIMCLK1; + } +#endif + +#if STM32_GPT_USE_TIM5 + if (&GPTD5 == gptp) { + rccEnableTIM5(FALSE); + rccResetTIM5(); + nvicEnableVector(TIM5_IRQn, + CORTEX_PRIORITY_MASK(STM32_GPT_TIM5_IRQ_PRIORITY)); + gptp->clock = STM32_TIMCLK1; + } +#endif + +#if STM32_GPT_USE_TIM8 + if (&GPTD8 == gptp) { + rccEnableTIM8(FALSE); + rccResetTIM8(); + nvicEnableVector(TIM8_UP_IRQn, + CORTEX_PRIORITY_MASK(STM32_GPT_TIM8_IRQ_PRIORITY)); + gptp->clock = STM32_TIMCLK2; + } +#endif + } + + /* Prescaler value calculation.*/ + psc = (uint16_t)((gptp->clock / gptp->config->frequency) - 1); + chDbgAssert(((uint32_t)(psc + 1) * gptp->config->frequency) == gptp->clock, + "gpt_lld_start(), #1", "invalid frequency"); + + /* Timer configuration.*/ + gptp->tim->CR1 = 0; /* Initially stopped. */ + gptp->tim->CR2 = TIM_CR2_CCDS; /* DMA on UE (if any). */ + gptp->tim->PSC = psc; /* Prescaler value. */ + gptp->tim->DIER = 0; +} + +/** + * @brief Deactivates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop(GPTDriver *gptp) { + + if (gptp->state == GPT_READY) { + gptp->tim->CR1 = 0; /* Timer disabled. */ + gptp->tim->DIER = 0; /* All IRQs disabled. */ + gptp->tim->SR = 0; /* Clear eventual pending IRQs. */ + +#if STM32_GPT_USE_TIM1 + if (&GPTD1 == gptp) { + nvicDisableVector(TIM1_UP_IRQn); + rccDisableTIM1(FALSE); + } +#endif +#if STM32_GPT_USE_TIM2 + if (&GPTD2 == gptp) { + nvicDisableVector(TIM2_IRQn); + rccDisableTIM2(FALSE); + } +#endif +#if STM32_GPT_USE_TIM3 + if (&GPTD3 == gptp) { + nvicDisableVector(TIM3_IRQn); + rccDisableTIM3(FALSE); + } +#endif +#if STM32_GPT_USE_TIM4 + if (&GPTD4 == gptp) { + nvicDisableVector(TIM4_IRQn); + rccDisableTIM4(FALSE); + } +#endif +#if STM32_GPT_USE_TIM5 + if (&GPTD5 == gptp) { + nvicDisableVector(TIM5_IRQn); + rccDisableTIM5(FALSE); + } +#endif +#if STM32_GPT_USE_TIM8 + if (&GPTD8 == gptp) { + nvicDisableVector(TIM8_UP_IRQn); + rccDisableTIM8(FALSE); + } +#endif + } +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @notapi + */ +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tim->ARR = interval - 1; /* Time constant. */ + gptp->tim->EGR = TIM_EGR_UG; /* Update event. */ + gptp->tim->CNT = 0; /* Reset counter. */ + /* NOTE: After generating the UG event it takes several clock cycles before + SR bit 0 goes to 1. This is because the clearing of CNT has been inserted + before the clearing of SR, to give it some time.*/ + gptp->tim->SR = 0; /* Clear pending IRQs (if any). */ + gptp->tim->DIER = TIM_DIER_UIE; /* Update Event IRQ enabled. */ + gptp->tim->CR1 = TIM_CR1_URS | TIM_CR1_CEN; +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop_timer(GPTDriver *gptp) { + + gptp->tim->CR1 = 0; /* Initially stopped. */ + gptp->tim->SR = 0; /* Clear pending IRQs (if any). */ + gptp->tim->DIER = 0; /* Interrupts disabled. */ +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @notapi + */ +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tim->ARR = interval - 1; /* Time constant. */ + gptp->tim->EGR = TIM_EGR_UG; /* Update event. */ + gptp->tim->SR = 0; /* Clear pending IRQs (if any). */ + gptp->tim->CR1 = TIM_CR1_OPM | TIM_CR1_URS | TIM_CR1_CEN; + while (!(gptp->tim->SR & TIM_SR_UIF)) + ; +} + +#endif /* HAL_USE_GPT */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/gpt_lld.h b/Project/os/hal/platforms/STM32/gpt_lld.h new file mode 100644 index 0000000..43189c1 --- /dev/null +++ b/Project/os/hal/platforms/STM32/gpt_lld.h @@ -0,0 +1,292 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/gpt_lld.h + * @brief STM32 GPT subsystem low level driver header. + * + * @addtogroup GPT + * @{ + */ + +#ifndef _GPT_LLD_H_ +#define _GPT_LLD_H_ + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief GPTD1 driver enable switch. + * @details If set to @p TRUE the support for GPTD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_GPT_USE_TIM1) || defined(__DOXYGEN__) +#define STM32_GPT_USE_TIM1 TRUE +#endif + +/** + * @brief GPTD2 driver enable switch. + * @details If set to @p TRUE the support for GPTD2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_GPT_USE_TIM2) || defined(__DOXYGEN__) +#define STM32_GPT_USE_TIM2 TRUE +#endif + +/** + * @brief GPTD3 driver enable switch. + * @details If set to @p TRUE the support for GPTD3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_GPT_USE_TIM3) || defined(__DOXYGEN__) +#define STM32_GPT_USE_TIM3 TRUE +#endif + +/** + * @brief GPTD4 driver enable switch. + * @details If set to @p TRUE the support for GPTD4 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_GPT_USE_TIM4) || defined(__DOXYGEN__) +#define STM32_GPT_USE_TIM4 TRUE +#endif + +/** + * @brief GPTD5 driver enable switch. + * @details If set to @p TRUE the support for GPTD5 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_GPT_USE_TIM5) || defined(__DOXYGEN__) +#define STM32_GPT_USE_TIM5 TRUE +#endif + +/** + * @brief GPTD8 driver enable switch. + * @details If set to @p TRUE the support for GPTD8 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_GPT_USE_TIM8) || defined(__DOXYGEN__) +#define STM32_GPT_USE_TIM8 TRUE +#endif + +/** + * @brief GPTD1 interrupt priority level setting. + */ +#if !defined(STM32_GPT_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD2 interrupt priority level setting. + */ +#if !defined(STM32_GPT_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD3 interrupt priority level setting. + */ +#if !defined(STM32_GPT_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD4 interrupt priority level setting. + */ +#if !defined(STM32_GPT_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD5 interrupt priority level setting. + */ +#if !defined(STM32_GPT_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD5 interrupt priority level setting. + */ +#if !defined(STM32_GPT_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_GPT_USE_TIM1 && !STM32_HAS_TIM1 +#error "TIM1 not present in the selected device" +#endif + +#if STM32_GPT_USE_TIM2 && !STM32_HAS_TIM2 +#error "TIM2 not present in the selected device" +#endif + +#if STM32_GPT_USE_TIM3 && !STM32_HAS_TIM3 +#error "TIM3 not present in the selected device" +#endif + +#if STM32_GPT_USE_TIM4 && !STM32_HAS_TIM4 +#error "TIM4 not present in the selected device" +#endif + +#if STM32_GPT_USE_TIM5 && !STM32_HAS_TIM5 +#error "TIM5 not present in the selected device" +#endif + +#if STM32_GPT_USE_TIM8 && !STM32_HAS_TIM8 +#error "TIM8 not present in the selected device" +#endif + +#if !STM32_GPT_USE_TIM1 && !STM32_GPT_USE_TIM2 && \ + !STM32_GPT_USE_TIM3 && !STM32_GPT_USE_TIM4 && \ + !STM32_GPT_USE_TIM5 && !STM32_GPT_USE_TIM8 +#error "GPT driver activated but no TIM peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPT frequency type. + */ +typedef uint32_t gptfreq_t; + +/** + * @brief GPT counter type. + */ +typedef uint16_t gptcnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + gptfreq_t frequency; + /** + * @brief Timer callback pointer. + * @note This callback is invoked on GPT counter events. + */ + gptcallback_t callback; + /* End of the mandatory fields.*/ +} GPTConfig; + +/** + * @brief Structure representing a GPT driver. + */ +struct GPTDriver { + /** + * @brief Driver state. + */ + gptstate_t state; + /** + * @brief Current configuration data. + */ + const GPTConfig *config; +#if defined(GPT_DRIVER_EXT_FIELDS) + GPT_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Timer base clock. + */ + uint32_t clock; + /** + * @brief Pointer to the TIMx registers block. + */ + stm32_tim_t *tim; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_GPT_USE_TIM1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD1; +#endif + +#if STM32_GPT_USE_TIM2 && !defined(__DOXYGEN__) +extern GPTDriver GPTD2; +#endif + +#if STM32_GPT_USE_TIM3 && !defined(__DOXYGEN__) +extern GPTDriver GPTD3; +#endif + +#if STM32_GPT_USE_TIM4 && !defined(__DOXYGEN__) +extern GPTDriver GPTD4; +#endif + +#if STM32_GPT_USE_TIM5 && !defined(__DOXYGEN__) +extern GPTDriver GPTD5; +#endif + +#if STM32_GPT_USE_TIM8 && !defined(__DOXYGEN__) +extern GPTDriver GPTD8; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void gpt_lld_init(void); + void gpt_lld_start(GPTDriver *gptp); + void gpt_lld_stop(GPTDriver *gptp); + void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); + void gpt_lld_stop_timer(GPTDriver *gptp); + void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT */ + +#endif /* _GPT_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/i2c_lld.c b/Project/os/hal/platforms/STM32/i2c_lld.c new file mode 100644 index 0000000..c81fdad --- /dev/null +++ b/Project/os/hal/platforms/STM32/i2c_lld.c @@ -0,0 +1,908 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file STM32/i2c_lld.c + * @brief STM32 I2C subsystem low level driver source. + * + * @addtogroup I2C + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define I2C1_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM, \ + STM32_I2C1_RX_DMA_CHN) + +#define I2C1_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_TX_DMA_STREAM, \ + STM32_I2C1_TX_DMA_CHN) + +#define I2C2_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_RX_DMA_STREAM, \ + STM32_I2C2_RX_DMA_CHN) + +#define I2C2_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_TX_DMA_STREAM, \ + STM32_I2C2_TX_DMA_CHN) + +#define I2C3_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_RX_DMA_STREAM, \ + STM32_I2C3_RX_DMA_CHN) + +#define I2C3_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_TX_DMA_STREAM, \ + STM32_I2C3_TX_DMA_CHN) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define I2C_EV5_MASTER_MODE_SELECT \ + ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | I2C_SR1_SB)) +#define I2C_EV6_MASTER_TRA_MODE_SELECTED \ + ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA) << 16) | \ + I2C_SR1_ADDR|I2C_SR1_TXE)) +#define I2C_EV6_MASTER_REC_MODE_SELECTED \ + ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16) | I2C_SR1_ADDR)) +#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED \ + ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) | \ + I2C_SR1_BTF | I2C_SR1_TXE)) +#define I2C_EV_MASK 0x00FFFFFF + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief I2C1 driver identifier.*/ +#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) +I2CDriver I2CD1; +#endif + +/** @brief I2C2 driver identifier.*/ +#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) +I2CDriver I2CD2; +#endif + +/** @brief I2C3 driver identifier.*/ +#if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__) +I2CDriver I2CD3; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/* The following variables have debugging purpose only and are included when + the option CH_DBG_ENABLE_ASSERTS is enabled.*/ +#if CH_DBG_ENABLE_ASSERTS +static volatile uint16_t dbgSR1; +static volatile uint16_t dbgSR2; +static volatile uint16_t dbgCR1; +static volatile uint16_t dbgCR2; +#endif /* CH_DBG_ENABLE_ASSERTS */ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Wakes up the waiting thread. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] msg wakeup message + * + * @notapi + */ +#define wakeup_isr(i2cp, msg) { \ + chSysLockFromIsr(); \ + if ((i2cp)->thread != NULL) { \ + Thread *tp = (i2cp)->thread; \ + (i2cp)->thread = NULL; \ + tp->p_u.rdymsg = (msg); \ + chSchReadyI(tp); \ + } \ + chSysUnlockFromIsr(); \ +} + +/** + * @brief Aborts an I2C transaction. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_abort_operation(I2CDriver *i2cp) { + I2C_TypeDef *dp = i2cp->i2c; + + /* Stops the I2C peripheral.*/ + dp->CR1 = I2C_CR1_SWRST; + dp->CR1 = 0; + dp->CR2 = 0; + dp->SR1 = 0; + + /* Stops the associated DMA streams.*/ + dmaStreamDisable(i2cp->dmatx); + dmaStreamDisable(i2cp->dmarx); +} + +/** + * @brief Handling of stalled I2C transactions. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_safety_timeout(void *p) { + I2CDriver *i2cp = (I2CDriver *)p; + + if (i2cp->thread) { + Thread *tp = i2cp->thread; + i2c_lld_abort_operation(i2cp); + i2cp->thread = NULL; + tp->p_u.rdymsg = RDY_TIMEOUT; + chSchReadyI(tp); + } +} + +/** + * @brief Set clock speed. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_set_clock(I2CDriver *i2cp) { + I2C_TypeDef *dp = i2cp->i2c; + uint16_t regCCR, clock_div; + int32_t clock_speed = i2cp->config->clock_speed; + i2cdutycycle_t duty = i2cp->config->duty_cycle; + + chDbgCheck((i2cp != NULL) && (clock_speed > 0) && (clock_speed <= 4000000), + "i2c_lld_set_clock"); + + /* CR2 Configuration.*/ + dp->CR2 &= (uint16_t)~I2C_CR2_FREQ; + dp->CR2 |= (uint16_t)I2C_CLK_FREQ; + + /* CCR Configuration.*/ + regCCR = 0; + clock_div = I2C_CCR_CCR; + + if (clock_speed <= 100000) { + /* Configure clock_div in standard mode.*/ + chDbgAssert(duty == STD_DUTY_CYCLE, + "i2c_lld_set_clock(), #1", + "Invalid standard mode duty cycle"); + + /* Standard mode clock_div calculate: Tlow/Thigh = 1/1.*/ + chDbgAssert((STM32_PCLK1 % (clock_speed * 2)) == 0, + "i2c_lld_set_clock(), #2", + "PCLK1 must be divided without remainder"); + clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 2)); + + chDbgAssert(clock_div >= 0x04, + "i2c_lld_set_clock(), #3", + "Clock divider less then 0x04 not allowed"); + regCCR |= (clock_div & I2C_CCR_CCR); + + /* Sets the Maximum Rise Time for standard mode.*/ + dp->TRISE = I2C_CLK_FREQ + 1; + } + else if (clock_speed <= 400000) { + /* Configure clock_div in fast mode.*/ + chDbgAssert((duty == FAST_DUTY_CYCLE_2) || (duty == FAST_DUTY_CYCLE_16_9), + "i2c_lld_set_clock(), #4", + "Invalid fast mode duty cycle"); + + if (duty == FAST_DUTY_CYCLE_2) { + /* Fast mode clock_div calculate: Tlow/Thigh = 2/1.*/ + chDbgAssert((STM32_PCLK1 % (clock_speed * 3)) == 0, + "i2c_lld_set_clock(), #5", + "PCLK1 must be divided without remainder"); + clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 3)); + } + else if (duty == FAST_DUTY_CYCLE_16_9) { + /* Fast mode clock_div calculate: Tlow/Thigh = 16/9.*/ + chDbgAssert((STM32_PCLK1 % (clock_speed * 25)) == 0, + "i2c_lld_set_clock(), #6", + "PCLK1 must be divided without remainder"); + clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 25)); + regCCR |= I2C_CCR_DUTY; + } + + chDbgAssert(clock_div >= 0x01, + "i2c_lld_set_clock(), #7", + "Clock divider less then 0x04 not allowed"); + regCCR |= (I2C_CCR_FS | (clock_div & I2C_CCR_CCR)); + + /* Sets the Maximum Rise Time for fast mode.*/ + dp->TRISE = (I2C_CLK_FREQ * 300 / 1000) + 1; + } + + chDbgAssert((clock_div <= I2C_CCR_CCR), + "i2c_lld_set_clock(), #8", "the selected clock is too low"); + + dp->CCR = regCCR; +} + +/** + * @brief Set operation mode of I2C hardware. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_set_opmode(I2CDriver *i2cp) { + I2C_TypeDef *dp = i2cp->i2c; + i2copmode_t opmode = i2cp->config->op_mode; + uint16_t regCR1; + + regCR1 = dp->CR1; + switch (opmode) { + case OPMODE_I2C: + regCR1 &= (uint16_t)~(I2C_CR1_SMBUS|I2C_CR1_SMBTYPE); + break; + case OPMODE_SMBUS_DEVICE: + regCR1 |= I2C_CR1_SMBUS; + regCR1 &= (uint16_t)~(I2C_CR1_SMBTYPE); + break; + case OPMODE_SMBUS_HOST: + regCR1 |= (I2C_CR1_SMBUS|I2C_CR1_SMBTYPE); + break; + } + dp->CR1 = regCR1; +} + +/** + * @brief I2C shared ISR code. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) { + I2C_TypeDef *dp = i2cp->i2c; + uint32_t regSR = dp->SR2; + uint32_t event = dp->SR1; + + /* Interrupts are disabled just before dmaStreamEnable() because there + is no need of interrupts until next transaction begin. All the work is + done by the DMA.*/ + switch (I2C_EV_MASK & (event | (regSR << 16))) { + case I2C_EV5_MASTER_MODE_SELECT: + dp->DR = i2cp->addr; + break; + case I2C_EV6_MASTER_REC_MODE_SELECTED: + dp->CR2 &= ~I2C_CR2_ITEVTEN; + dmaStreamEnable(i2cp->dmarx); + dp->CR2 |= I2C_CR2_LAST; /* Needed in receiver mode. */ + if (dmaStreamGetTransactionSize(i2cp->dmarx) < 2) + dp->CR1 &= ~I2C_CR1_ACK; + break; + case I2C_EV6_MASTER_TRA_MODE_SELECTED: + dp->CR2 &= ~I2C_CR2_ITEVTEN; + dmaStreamEnable(i2cp->dmatx); + break; + case I2C_EV8_2_MASTER_BYTE_TRANSMITTED: + /* Catches BTF event after the end of transmission.*/ + if (dmaStreamGetTransactionSize(i2cp->dmarx) > 0) { + /* Starts "read after write" operation, LSB = 1 -> receive.*/ + i2cp->addr |= 0x01; + dp->CR1 |= I2C_CR1_START | I2C_CR1_ACK; + return; + } + dp->CR2 &= ~I2C_CR2_ITEVTEN; + dp->CR1 |= I2C_CR1_STOP; + wakeup_isr(i2cp, RDY_OK); + break; + default: + break; + } + /* Clear ADDR flag. */ + if (event & (I2C_SR1_ADDR | I2C_SR1_ADD10)) + (void)dp->SR2; +} + +/** + * @brief DMA RX end IRQ handler. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] flags pre-shifted content of the ISR register + * + * @notapi + */ +static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags) { + I2C_TypeDef *dp = i2cp->i2c; + + /* DMA errors handling.*/ +#if defined(STM32_I2C_DMA_ERROR_HOOK) + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_I2C_DMA_ERROR_HOOK(i2cp); + } +#else + (void)flags; +#endif + + dmaStreamDisable(i2cp->dmarx); + + dp->CR2 &= ~I2C_CR2_LAST; + dp->CR1 &= ~I2C_CR1_ACK; + dp->CR1 |= I2C_CR1_STOP; + wakeup_isr(i2cp, RDY_OK); +} + +/** + * @brief DMA TX end IRQ handler. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) { + I2C_TypeDef *dp = i2cp->i2c; + + /* DMA errors handling.*/ +#if defined(STM32_I2C_DMA_ERROR_HOOK) + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_I2C_DMA_ERROR_HOOK(i2cp); + } +#else + (void)flags; +#endif + + dmaStreamDisable(i2cp->dmatx); + /* Enables interrupts to catch BTF event meaning transmission part complete. + Interrupt handler will decide to generate STOP or to begin receiving part + of R/W transaction itself.*/ + dp->CR2 |= I2C_CR2_ITEVTEN; +} + +/** + * @brief I2C error handler. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp) { + I2C_TypeDef *dp = i2cp->i2c; + i2cflags_t errors; + + /* Clears interrupt flags just to be safe.*/ + chSysLockFromIsr(); + dmaStreamDisable(i2cp->dmatx); + dmaStreamDisable(i2cp->dmarx); + chSysUnlockFromIsr(); + + errors = I2CD_NO_ERROR; + + if (dp->SR1 & I2C_SR1_BERR) { /* Bus error. */ + dp->SR1 &= ~I2C_SR1_BERR; + errors |= I2CD_BUS_ERROR; + } + if (dp->SR1 & I2C_SR1_ARLO) { /* Arbitration lost. */ + dp->SR1 &= ~I2C_SR1_ARLO; + errors |= I2CD_ARBITRATION_LOST; + } + if (dp->SR1 & I2C_SR1_AF) { /* Acknowledge fail. */ + dp->SR1 &= ~I2C_SR1_AF; + dp->CR2 &= ~I2C_CR2_ITEVTEN; + dp->CR1 |= I2C_CR1_STOP; /* Setting stop bit. */ + errors |= I2CD_ACK_FAILURE; + } + if (dp->SR1 & I2C_SR1_OVR) { /* Overrun. */ + dp->SR1 &= ~I2C_SR1_OVR; + errors |= I2CD_OVERRUN; + } + if (dp->SR1 & I2C_SR1_PECERR) { /* PEC error. */ + dp->SR1 &= ~I2C_SR1_PECERR; + errors |= I2CD_PEC_ERROR; + } + if (dp->SR1 & I2C_SR1_TIMEOUT) { /* SMBus Timeout. */ + dp->SR1 &= ~I2C_SR1_TIMEOUT; + errors |= I2CD_TIMEOUT; + } + if (dp->SR1 & I2C_SR1_SMBALERT) { /* SMBus alert. */ + dp->SR1 &= ~I2C_SR1_SMBALERT; + errors |= I2CD_SMB_ALERT; + } + + /* If some error has been identified then sends wakes the waiting thread.*/ + if (errors != I2CD_NO_ERROR) { + i2cp->errors = errors; + wakeup_isr(i2cp, RDY_RESET); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) +/** + * @brief I2C1 event interrupt handler. + * + * @notapi + */ +CH_IRQ_HANDLER(I2C1_EV_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + i2c_lld_serve_event_interrupt(&I2CD1); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief I2C1 error interrupt handler. + */ +CH_IRQ_HANDLER(I2C1_ER_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + i2c_lld_serve_error_interrupt(&I2CD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_I2C_USE_I2C1 */ + +#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) +/** + * @brief I2C2 event interrupt handler. + * + * @notapi + */ +CH_IRQ_HANDLER(I2C2_EV_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + i2c_lld_serve_event_interrupt(&I2CD2); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief I2C2 error interrupt handler. + * + * @notapi + */ +CH_IRQ_HANDLER(I2C2_ER_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + i2c_lld_serve_error_interrupt(&I2CD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_I2C_USE_I2C2 */ + +#if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__) +/** + * @brief I2C3 event interrupt handler. + * + * @notapi + */ +CH_IRQ_HANDLER(I2C3_EV_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + i2c_lld_serve_event_interrupt(&I2CD3); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief I2C3 error interrupt handler. + * + * @notapi + */ +CH_IRQ_HANDLER(I2C3_ER_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + i2c_lld_serve_error_interrupt(&I2CD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_I2C_USE_I2C3 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level I2C driver initialization. + * + * @notapi + */ +void i2c_lld_init(void) { + +#if STM32_I2C_USE_I2C1 + i2cObjectInit(&I2CD1); + I2CD1.thread = NULL; + I2CD1.i2c = I2C1; + I2CD1.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM); + I2CD1.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM); +#endif /* STM32_I2C_USE_I2C1 */ + +#if STM32_I2C_USE_I2C2 + i2cObjectInit(&I2CD2); + I2CD2.thread = NULL; + I2CD2.i2c = I2C2; + I2CD2.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM); + I2CD2.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM); +#endif /* STM32_I2C_USE_I2C2 */ + +#if STM32_I2C_USE_I2C3 + i2cObjectInit(&I2CD3); + I2CD3.thread = NULL; + I2CD3.i2c = I2C3; + I2CD3.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C3_RX_DMA_STREAM); + I2CD3.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C3_TX_DMA_STREAM); +#endif /* STM32_I2C_USE_I2C3 */ +} + +/** + * @brief Configures and activates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_start(I2CDriver *i2cp) { + I2C_TypeDef *dp = i2cp->i2c; + + i2cp->dmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE | + STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | + STM32_DMA_CR_TCIE; + + /* If in stopped state then enables the I2C and DMA clocks.*/ + if (i2cp->state == I2C_STOP) { + +#if STM32_I2C_USE_I2C1 + if (&I2CD1 == i2cp) { + bool_t b; + + rccResetI2C1(); + b = dmaStreamAllocate(i2cp->dmarx, + STM32_I2C_I2C1_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "i2c_lld_start(), #1", "stream already allocated"); + b = dmaStreamAllocate(i2cp->dmatx, + STM32_I2C_I2C1_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "i2c_lld_start(), #2", "stream already allocated"); + rccEnableI2C1(FALSE); + nvicEnableVector(I2C1_EV_IRQn, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); + nvicEnableVector(I2C1_ER_IRQn, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); + + i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); + } +#endif /* STM32_I2C_USE_I2C1 */ + +#if STM32_I2C_USE_I2C2 + if (&I2CD2 == i2cp) { + bool_t b; + + rccResetI2C2(); + b = dmaStreamAllocate(i2cp->dmarx, + STM32_I2C_I2C2_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "i2c_lld_start(), #3", "stream already allocated"); + b = dmaStreamAllocate(i2cp->dmatx, + STM32_I2C_I2C2_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "i2c_lld_start(), #4", "stream already allocated"); + rccEnableI2C2(FALSE); + nvicEnableVector(I2C2_EV_IRQn, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); + nvicEnableVector(I2C2_ER_IRQn, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); + + i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); + } +#endif /* STM32_I2C_USE_I2C2 */ + +#if STM32_I2C_USE_I2C3 + if (&I2CD3 == i2cp) { + bool_t b; + + rccResetI2C3(); + b = dmaStreamAllocate(i2cp->dmarx, + STM32_I2C_I2C3_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "i2c_lld_start(), #5", "stream already allocated"); + b = dmaStreamAllocate(i2cp->dmatx, + STM32_I2C_I2C3_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "i2c_lld_start(), #6", "stream already allocated"); + rccEnableI2C3(FALSE); + nvicEnableVector(I2C3_EV_IRQn, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY)); + nvicEnableVector(I2C3_ER_IRQn, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY)); + + i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY); + } +#endif /* STM32_I2C_USE_I2C3 */ + } + + /* DMA streams mode preparation in advance.*/ + dmaStreamSetMode(i2cp->dmatx, i2cp->dmamode | STM32_DMA_CR_DIR_M2P); + dmaStreamSetMode(i2cp->dmarx, i2cp->dmamode | STM32_DMA_CR_DIR_P2M); + + /* I2C registers pointed by the DMA.*/ + dmaStreamSetPeripheral(i2cp->dmarx, &dp->DR); + dmaStreamSetPeripheral(i2cp->dmatx, &dp->DR); + + /* Reset i2c peripheral.*/ + dp->CR1 = I2C_CR1_SWRST; + dp->CR1 = 0; + dp->CR2 = I2C_CR2_ITERREN | I2C_CR2_DMAEN; + + /* Setup I2C parameters.*/ + i2c_lld_set_clock(i2cp); + i2c_lld_set_opmode(i2cp); + + /* Ready to go.*/ + dp->CR1 |= I2C_CR1_PE; +} + +/** + * @brief Deactivates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_stop(I2CDriver *i2cp) { + + /* If not in stopped state then disables the I2C clock.*/ + if (i2cp->state != I2C_STOP) { + + /* I2C disable.*/ + i2c_lld_abort_operation(i2cp); + dmaStreamRelease(i2cp->dmatx); + dmaStreamRelease(i2cp->dmarx); + +#if STM32_I2C_USE_I2C1 + if (&I2CD1 == i2cp) { + nvicDisableVector(I2C1_EV_IRQn); + nvicDisableVector(I2C1_ER_IRQn); + rccDisableI2C1(FALSE); + } +#endif + +#if STM32_I2C_USE_I2C2 + if (&I2CD2 == i2cp) { + nvicDisableVector(I2C2_EV_IRQn); + nvicDisableVector(I2C2_ER_IRQn); + rccDisableI2C2(FALSE); + } +#endif + +#if STM32_I2C_USE_I2C3 + if (&I2CD3 == i2cp) { + nvicDisableVector(I2C3_EV_IRQn); + nvicDisableVector(I2C3_ER_IRQn); + rccDisableI2C3(FALSE); + } +#endif + } +} + +/** + * @brief Receives data via the I2C bus as master. + * @details Number of receiving bytes must be more than 1 because of stm32 + * hardware restrictions. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout) { + I2C_TypeDef *dp = i2cp->i2c; + VirtualTimer vt; + +#if defined(STM32F1XX_I2C) + chDbgCheck((rxbytes > 1), "i2c_lld_master_receive_timeout"); +#endif + + /* Global timeout for the whole operation.*/ + if (timeout != TIME_INFINITE) + chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp); + + /* Releases the lock from high level driver.*/ + chSysUnlock(); + + /* Initializes driver fields, LSB = 1 -> receive.*/ + i2cp->addr = (addr << 1) | 0x01; + i2cp->errors = 0; + + /* RX DMA setup.*/ + dmaStreamSetMemory0(i2cp->dmarx, rxbuf); + dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); + + /* Waits until BUSY flag is reset and the STOP from the previous operation + is completed, alternatively for a timeout condition.*/ + while ((dp->SR2 & I2C_SR2_BUSY) || (dp->CR1 & I2C_CR1_STOP)) { + chSysLock(); + if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) + return RDY_TIMEOUT; + chSysUnlock(); + } + + /* This lock will be released in high level driver.*/ + chSysLock(); + + /* Atomic check on the timer in order to make sure that a timeout didn't + happen outside the critical zone.*/ + if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) + return RDY_TIMEOUT; + + /* Starts the operation.*/ + dp->CR2 |= I2C_CR2_ITEVTEN; + dp->CR1 |= I2C_CR1_START | I2C_CR1_ACK; + + /* Waits for the operation completion or a timeout.*/ + i2cp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt)) + chVTResetI(&vt); + + return chThdSelf()->p_u.rdymsg; +} + +/** + * @brief Transmits data via the I2C bus as master. + * @details Number of receiving bytes must be 0 or more than 1 because of stm32 + * hardware restrictions. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[in] txbuf pointer to the transmit buffer + * @param[in] txbytes number of bytes to be transmitted + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout) { + I2C_TypeDef *dp = i2cp->i2c; + VirtualTimer vt; + +#if defined(STM32F1XX_I2C) + chDbgCheck(((rxbytes == 0) || ((rxbytes > 1) && (rxbuf != NULL))), + "i2c_lld_master_transmit_timeout"); +#endif + + /* Global timeout for the whole operation.*/ + if (timeout != TIME_INFINITE) + chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp); + + /* Releases the lock from high level driver.*/ + chSysUnlock(); + + /* Initializes driver fields, LSB = 0 -> write.*/ + i2cp->addr = addr << 1; + i2cp->errors = 0; + + /* TX DMA setup.*/ + dmaStreamSetMemory0(i2cp->dmatx, txbuf); + dmaStreamSetTransactionSize(i2cp->dmatx, txbytes); + + /* RX DMA setup.*/ + dmaStreamSetMemory0(i2cp->dmarx, rxbuf); + dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); + + /* Waits until BUSY flag is reset and the STOP from the previous operation + is completed, alternatively for a timeout condition.*/ + while ((dp->SR2 & I2C_SR2_BUSY) || (dp->CR1 & I2C_CR1_STOP)) { + chSysLock(); + if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) + return RDY_TIMEOUT; + chSysUnlock(); + } + + /* This lock will be released in high level driver.*/ + chSysLock(); + + /* Atomic check on the timer in order to make sure that a timeout didn't + happen outside the critical zone.*/ + if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) + return RDY_TIMEOUT; + + /* Starts the operation.*/ + dp->CR2 |= I2C_CR2_ITEVTEN; + dp->CR1 |= I2C_CR1_START; + + /* Waits for the operation completion or a timeout.*/ + i2cp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt)) + chVTResetI(&vt); + + return chThdSelf()->p_u.rdymsg; +} + +#endif /* HAL_USE_I2C */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/i2c_lld.h b/Project/os/hal/platforms/STM32/i2c_lld.h new file mode 100644 index 0000000..0bc19bf --- /dev/null +++ b/Project/os/hal/platforms/STM32/i2c_lld.h @@ -0,0 +1,470 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file STM32/i2c_lld.h + * @brief STM32 I2C subsystem low level driver header. + * + * @addtogroup I2C + * @{ + */ + +#ifndef _I2C_LLD_H_ +#define _I2C_LLD_H_ + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Peripheral clock frequency. + */ +#define I2C_CLK_FREQ ((STM32_PCLK1) / 1000000) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief I2C1 driver enable switch. + * @details If set to @p TRUE the support for I2C1 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__) +#define STM32_I2C_USE_I2C1 FALSE +#endif + +/** + * @brief I2C2 driver enable switch. + * @details If set to @p TRUE the support for I2C2 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__) +#define STM32_I2C_USE_I2C2 FALSE +#endif + +/** + * @brief I2C3 driver enable switch. + * @details If set to @p TRUE the support for I2C3 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_I2C_USE_I2C3) || defined(__DOXYGEN__) +#define STM32_I2C_USE_I2C3 FALSE +#endif + +/** + * @brief I2C1 interrupt priority level setting. + */ +#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#endif + +/** + * @brief I2C2 interrupt priority level setting. + */ +#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#endif + +/** + * @brief I2C3 interrupt priority level setting. + */ +#if !defined(STM32_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C3_IRQ_PRIORITY 10 +#endif + +/** +* @brief I2C1 DMA priority (0..3|lowest..highest). +* @note The priority level is used for both the TX and RX DMA streams but +* because of the streams ordering the RX stream has always priority +* over the TX stream. +*/ +#if !defined(STM32_I2C_I2C1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#endif + +/** +* @brief I2C2 DMA priority (0..3|lowest..highest). +* @note The priority level is used for both the TX and RX DMA streams but +* because of the streams ordering the RX stream has always priority +* over the TX stream. +*/ +#if !defined(STM32_I2C_I2C2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#endif + +/** +* @brief I2C3 DMA priority (0..3|lowest..highest). +* @note The priority level is used for both the TX and RX DMA streams but +* because of the streams ordering the RX stream has always priority +* over the TX stream. +*/ +#if !defined(STM32_I2C_I2C3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C3_DMA_PRIORITY 1 +#endif + +/** + * @brief I2C DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() +#endif + +#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) + +/** + * @brief DMA stream used for I2C1 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2C_I2C1_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#endif + +/** + * @brief DMA stream used for I2C1 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2C_I2C1_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#endif + +/** + * @brief DMA stream used for I2C2 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2C_I2C2_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#endif + +/** + * @brief DMA stream used for I2C2 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2C_I2C2_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#endif + +/** + * @brief DMA stream used for I2C3 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2C_I2C3_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#endif + +/** + * @brief DMA stream used for I2C3 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2C_I2C3_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#endif + +#else /* !STM32_ADVANCED_DMA */ + +/* Fixed streams for platforms using the old DMA peripheral, the values are + valid for both STM32F1xx and STM32L1xx.*/ +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +#endif /* !STM32_ADVANCED_DMA*/ + +/* Flag for whole STM32F1XX family. */ +#if defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_LD) || defined(STM32F10X_MD) || \ + defined(STM32F10X_HD) || defined(STM32F10X_XL) || \ + defined(STM32F10X_CL) +#define STM32F1XX_I2C +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** @brief error checks */ +#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1 +#error "I2C1 not present in the selected device" +#endif + +#if STM32_I2C_USE_I2C2 && !STM32_HAS_I2C2 +#error "I2C2 not present in the selected device" +#endif + +#if STM32_I2C_USE_I2C3 && !STM32_HAS_I2C3 +#error "I2C3 not present in the selected device" +#endif + +#if !STM32_I2C_USE_I2C1 && !STM32_I2C_USE_I2C2 && \ + !STM32_I2C_USE_I2C3 +#error "I2C driver activated but no I2C peripheral assigned" +#endif + +#if STM32_I2C_USE_I2C1 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM, \ + STM32_I2C1_RX_DMA_MSK) +#error "invalid DMA stream associated to I2C1 RX" +#endif + +#if STM32_I2C_USE_I2C1 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_TX_DMA_STREAM, \ + STM32_I2C1_TX_DMA_MSK) +#error "invalid DMA stream associated to I2C1 TX" +#endif + +#if STM32_I2C_USE_I2C2 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_RX_DMA_STREAM, \ + STM32_I2C2_RX_DMA_MSK) +#error "invalid DMA stream associated to I2C2 RX" +#endif + +#if STM32_I2C_USE_I2C2 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_TX_DMA_STREAM, \ + STM32_I2C2_TX_DMA_MSK) +#error "invalid DMA stream associated to I2C2 TX" +#endif + +#if STM32_I2C_USE_I2C3 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_RX_DMA_STREAM, \ + STM32_I2C3_RX_DMA_MSK) +#error "invalid DMA stream associated to I2C3 RX" +#endif + +#if STM32_I2C_USE_I2C3 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_TX_DMA_STREAM, \ + STM32_I2C3_TX_DMA_MSK) +#error "invalid DMA stream associated to I2C3 TX" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/* Check clock range. */ +#if defined(STM32F4XX) +#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 42) +#error "I2C peripheral clock frequency out of range." +#endif + +#elif defined(STM32L1XX_MD) +#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 32) +#error "I2C peripheral clock frequency out of range." +#endif + +#elif defined(STM32F2XX) +#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 30) +#error "I2C peripheral clock frequency out of range." +#endif + +#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD_VL) +#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 24) +#error "I2C peripheral clock frequency out of range." +#endif + +#elif defined(STM32F10X_LD) || defined(STM32F10X_MD) || \ + defined(STM32F10X_HD) || defined(STM32F10X_XL) || \ + defined(STM32F10X_CL) +#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 36) +#error "I2C peripheral clock frequency out of range." +#endif +#else +#error "unspecified, unsupported or invalid STM32 platform" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing I2C address. + */ +typedef uint16_t i2caddr_t; + +/** + * @brief I2C Driver condition flags type. + */ +typedef uint32_t i2cflags_t; + +/** + * @brief Supported modes for the I2C bus. + */ +typedef enum { + OPMODE_I2C = 1, + OPMODE_SMBUS_DEVICE = 2, + OPMODE_SMBUS_HOST = 3, +} i2copmode_t; + +/** + * @brief Supported duty cycle modes for the I2C bus. + */ +typedef enum { + STD_DUTY_CYCLE = 1, + FAST_DUTY_CYCLE_2 = 2, + FAST_DUTY_CYCLE_16_9 = 3, +} i2cdutycycle_t; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + i2copmode_t op_mode; /**< @brief Specifies the I2C mode. */ + uint32_t clock_speed; /**< @brief Specifies the clock frequency. + @note Must be set to a value lower + than 400kHz. */ + i2cdutycycle_t duty_cycle; /**< @brief Specifies the I2C fast mode + duty cycle. */ +} I2CConfig; + +/** + * @brief Type of a structure representing an I2C driver. + */ +typedef struct I2CDriver I2CDriver; + +/** + * @brief Structure representing an I2C driver. + */ +struct I2CDriver{ + /** + * @brief Driver state. + */ + i2cstate_t state; + /** + * @brief Current configuration data. + */ + const I2CConfig *config; + /** + * @brief Error flags. + */ + i2cflags_t errors; +#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* I2C_USE_MUTUAL_EXCLUSION */ +#if defined(I2C_DRIVER_EXT_FIELDS) + I2C_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Thread waiting for I/O completion. + */ + Thread *thread; + /** + * @brief Current slave address without R/W bit. + */ + i2caddr_t addr; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; + /** + * @brief Receive DMA channel. + */ + const stm32_dma_stream_t *dmarx; + /** + * @brief Transmit DMA channel. + */ + const stm32_dma_stream_t *dmatx; + /** + * @brief Pointer to the I2Cx registers block. + */ + I2C_TypeDef *i2c; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Get errors from I2C driver. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +#define i2c_lld_get_errors(i2cp) ((i2cp)->errors) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +#if STM32_I2C_USE_I2C1 +extern I2CDriver I2CD1; +#endif + +#if STM32_I2C_USE_I2C2 +extern I2CDriver I2CD2; +#endif + +#if STM32_I2C_USE_I2C3 +extern I2CDriver I2CD3; +#endif +#endif /* !defined(__DOXYGEN__) */ + +#ifdef __cplusplus +extern "C" { +#endif + void i2c_lld_init(void); + void i2c_lld_start(I2CDriver *i2cp); + void i2c_lld_stop(I2CDriver *i2cp); + msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); + msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_I2C */ + +#endif /* _I2C_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/icu_lld.c b/Project/os/hal/platforms/STM32/icu_lld.c new file mode 100644 index 0000000..0f8bc4b --- /dev/null +++ b/Project/os/hal/platforms/STM32/icu_lld.c @@ -0,0 +1,515 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/icu_lld.c + * @brief STM32 ICU subsystem low level driver header. + * + * @addtogroup ICU + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief ICUD1 driver identifier. + * @note The driver ICUD1 allocates the complex timer TIM1 when enabled. + */ +#if STM32_ICU_USE_TIM1 || defined(__DOXYGEN__) +ICUDriver ICUD1; +#endif + +/** + * @brief ICUD2 driver identifier. + * @note The driver ICUD1 allocates the timer TIM2 when enabled. + */ +#if STM32_ICU_USE_TIM2 || defined(__DOXYGEN__) +ICUDriver ICUD2; +#endif + +/** + * @brief ICUD3 driver identifier. + * @note The driver ICUD1 allocates the timer TIM3 when enabled. + */ +#if STM32_ICU_USE_TIM3 || defined(__DOXYGEN__) +ICUDriver ICUD3; +#endif + +/** + * @brief ICUD4 driver identifier. + * @note The driver ICUD4 allocates the timer TIM4 when enabled. + */ +#if STM32_ICU_USE_TIM4 || defined(__DOXYGEN__) +ICUDriver ICUD4; +#endif + +/** + * @brief ICUD5 driver identifier. + * @note The driver ICUD5 allocates the timer TIM5 when enabled. + */ +#if STM32_ICU_USE_TIM5 || defined(__DOXYGEN__) +ICUDriver ICUD5; +#endif + +/** + * @brief ICUD8 driver identifier. + * @note The driver ICUD8 allocates the timer TIM8 when enabled. + */ +#if STM32_ICU_USE_TIM8 || defined(__DOXYGEN__) +ICUDriver ICUD8; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared IRQ handler. + * + * @param[in] icup pointer to the @p ICUDriver object + */ +static void icu_lld_serve_interrupt(ICUDriver *icup) { + uint16_t sr; + + sr = icup->tim->SR & icup->tim->DIER; + icup->tim->SR = 0; + if ((sr & TIM_SR_CC1IF) != 0) + _icu_isr_invoke_period_cb(icup); + if ((sr & TIM_SR_CC2IF) != 0) + _icu_isr_invoke_width_cb(icup); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_ICU_USE_TIM1 +/** + * @brief TIM1 compare interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM1_CC_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD1); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief TIM1 compare interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM1_UP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ICU_USE_TIM1 */ + +#if STM32_ICU_USE_TIM2 +/** + * @brief TIM2 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM2_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ICU_USE_TIM2 */ + +#if STM32_ICU_USE_TIM3 +/** + * @brief TIM3 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM3_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ICU_USE_TIM3 */ + +#if STM32_ICU_USE_TIM4 +/** + * @brief TIM4 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM4_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD4); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ICU_USE_TIM4 */ + +#if STM32_ICU_USE_TIM5 +/** + * @brief TIM5 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM5_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD5); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ICU_USE_TIM5 */ + +#if STM32_ICU_USE_TIM8 +/** + * @brief TIM8 compare interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM8_CC_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD8); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief TIM8 compare interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM8_UP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD8); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ICU_USE_TIM8 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ICU driver initialization. + * + * @notapi + */ +void icu_lld_init(void) { + +#if STM32_ICU_USE_TIM1 + /* Driver initialization.*/ + icuObjectInit(&ICUD1); + ICUD1.tim = STM32_TIM1; +#endif + +#if STM32_ICU_USE_TIM2 + /* Driver initialization.*/ + icuObjectInit(&ICUD2); + ICUD2.tim = STM32_TIM2; +#endif + +#if STM32_ICU_USE_TIM3 + /* Driver initialization.*/ + icuObjectInit(&ICUD3); + ICUD3.tim = STM32_TIM3; +#endif + +#if STM32_ICU_USE_TIM4 + /* Driver initialization.*/ + icuObjectInit(&ICUD4); + ICUD4.tim = STM32_TIM4; +#endif + +#if STM32_ICU_USE_TIM5 + /* Driver initialization.*/ + icuObjectInit(&ICUD5); + ICUD5.tim = STM32_TIM5; +#endif + +#if STM32_ICU_USE_TIM8 + /* Driver initialization.*/ + icuObjectInit(&ICUD8); + ICUD8.tim = STM32_TIM8; +#endif +} + +/** + * @brief Configures and activates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_start(ICUDriver *icup) { + uint32_t psc; + + if (icup->state == ICU_STOP) { + /* Clock activation and timer reset.*/ +#if STM32_ICU_USE_TIM1 + if (&ICUD1 == icup) { + rccEnableTIM1(FALSE); + rccResetTIM1(); + nvicEnableVector(TIM1_CC_IRQn, + CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY)); + nvicEnableVector(TIM1_UP_IRQn, + CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY)); + icup->clock = STM32_TIMCLK2; + } +#endif +#if STM32_ICU_USE_TIM2 + if (&ICUD2 == icup) { + rccEnableTIM2(FALSE); + rccResetTIM2(); + nvicEnableVector(TIM2_IRQn, + CORTEX_PRIORITY_MASK(STM32_ICU_TIM2_IRQ_PRIORITY)); + icup->clock = STM32_TIMCLK1; + } +#endif +#if STM32_ICU_USE_TIM3 + if (&ICUD3 == icup) { + rccEnableTIM3(FALSE); + rccResetTIM3(); + nvicEnableVector(TIM3_IRQn, + CORTEX_PRIORITY_MASK(STM32_ICU_TIM3_IRQ_PRIORITY)); + icup->clock = STM32_TIMCLK1; + } +#endif +#if STM32_ICU_USE_TIM4 + if (&ICUD4 == icup) { + rccEnableTIM4(FALSE); + rccResetTIM4(); + nvicEnableVector(TIM4_IRQn, + CORTEX_PRIORITY_MASK(STM32_ICU_TIM4_IRQ_PRIORITY)); + icup->clock = STM32_TIMCLK1; + } +#endif + +#if STM32_ICU_USE_TIM5 + if (&ICUD5 == icup) { + rccEnableTIM5(FALSE); + rccResetTIM5(); + nvicEnableVector(TIM5_IRQn, + CORTEX_PRIORITY_MASK(STM32_ICU_TIM5_IRQ_PRIORITY)); + icup->clock = STM32_TIMCLK1; + } +#endif +#if STM32_ICU_USE_TIM8 + if (&ICUD8 == icup) { + rccEnableTIM8(FALSE); + rccResetTIM8(); + nvicEnableVector(TIM8_CC_IRQn, + CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY)); + nvicEnableVector(TIM8_UP_IRQn, + CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY)); + icup->clock = STM32_TIMCLK2; + } +#endif + } + else { + /* Driver re-configuration scenario, it must be stopped first.*/ + icup->tim->CR1 = 0; /* Timer disabled. */ + icup->tim->DIER = 0; /* All IRQs disabled. */ + icup->tim->SR = 0; /* Clear eventual pending IRQs. */ + icup->tim->CCR[0] = 0; /* Comparator 1 disabled. */ + icup->tim->CCR[1] = 0; /* Comparator 2 disabled. */ + icup->tim->CNT = 0; /* Counter reset to zero. */ + } + + /* Timer configuration.*/ + psc = (icup->clock / icup->config->frequency) - 1; + chDbgAssert((psc <= 0xFFFF) && + ((psc + 1) * icup->config->frequency) == icup->clock, + "icu_lld_start(), #1", "invalid frequency"); + icup->tim->PSC = (uint16_t)psc; + icup->tim->ARR = 0xFFFF; + + /* CCMR1_CC1S = 01 = CH1 Input on TI1. + CCMR1_CC2S = 10 = CH2 Input on TI1.*/ + icup->tim->CCMR1 = TIM_CCMR1_CC1S_0 | + TIM_CCMR1_CC2S_1; + /* SMCR_TS = 101, input is TI1FP1. + SMCR_SMS = 100, reset on rising edge.*/ + icup->tim->SMCR = TIM_SMCR_TS_2 | TIM_SMCR_TS_0 | + TIM_SMCR_SMS_2; + /* The CCER settings depend on the selected trigger mode. + ICU_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge. + ICU_INPUT_ACTIVE_LOW: Active on falling edge, idle on rising edge.*/ + if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) + icup->tim->CCER = TIM_CCER_CC1E | + TIM_CCER_CC2E | TIM_CCER_CC2P; + else + icup->tim->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P | + TIM_CCER_CC2E; +} + +/** + * @brief Deactivates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_stop(ICUDriver *icup) { + + if (icup->state == ICU_READY) { + /* Clock deactivation.*/ + icup->tim->CR1 = 0; /* Timer disabled. */ + icup->tim->DIER = 0; /* All IRQs disabled. */ + icup->tim->SR = 0; /* Clear eventual pending IRQs. */ + +#if STM32_ICU_USE_TIM1 + if (&ICUD1 == icup) { + nvicDisableVector(TIM1_CC_IRQn); + nvicDisableVector(TIM1_UP_IRQn); + rccDisableTIM1(FALSE); + } +#endif +#if STM32_ICU_USE_TIM2 + if (&ICUD2 == icup) { + nvicDisableVector(TIM2_IRQn); + rccDisableTIM2(FALSE); + } +#endif +#if STM32_ICU_USE_TIM3 + if (&ICUD3 == icup) { + nvicDisableVector(TIM3_IRQn); + rccDisableTIM3(FALSE); + } +#endif +#if STM32_ICU_USE_TIM4 + if (&ICUD4 == icup) { + nvicDisableVector(TIM4_IRQn); + rccDisableTIM4(FALSE); + } +#endif +#if STM32_ICU_USE_TIM5 + if (&ICUD5 == icup) { + nvicDisableVector(TIM5_IRQn); + rccDisableTIM5(FALSE); + } +#endif + } +#if STM32_ICU_USE_TIM8 + if (&ICUD8 == icup) { + nvicDisableVector(TIM8_CC_IRQn); + nvicDisableVector(TIM8_UP_IRQn); + rccDisableTIM8(FALSE); + } +#endif +} + +/** + * @brief Enables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_enable(ICUDriver *icup) { + + icup->tim->SR = 0; /* Clear pending IRQs (if any). */ + if (icup->config->period_cb != NULL) + icup->tim->DIER |= TIM_DIER_CC1IE; + if (icup->config->width_cb != NULL) + icup->tim->DIER |= TIM_DIER_CC2IE; + icup->tim->CR1 = TIM_CR1_URS | TIM_CR1_CEN; +} + +/** + * @brief Disables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_disable(ICUDriver *icup) { + + icup->tim->CR1 = 0; /* Initially stopped. */ + icup->tim->SR = 0; /* Clear pending IRQs (if any). */ + icup->tim->DIER = 0; /* Interrupts disabled. */ +} + +#endif /* HAL_USE_ICU */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/icu_lld.h b/Project/os/hal/platforms/STM32/icu_lld.h new file mode 100644 index 0000000..a8d74c7 --- /dev/null +++ b/Project/os/hal/platforms/STM32/icu_lld.h @@ -0,0 +1,330 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/icu_lld.h + * @brief STM32 ICU subsystem low level driver header. + * + * @addtogroup ICU + * @{ + */ + +#ifndef _ICU_LLD_H_ +#define _ICU_LLD_H_ + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ICUD1 driver enable switch. + * @details If set to @p TRUE the support for ICUD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ICU_USE_TIM1) || defined(__DOXYGEN__) +#define STM32_ICU_USE_TIM1 TRUE +#endif + +/** + * @brief ICUD2 driver enable switch. + * @details If set to @p TRUE the support for ICUD2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ICU_USE_TIM2) || defined(__DOXYGEN__) +#define STM32_ICU_USE_TIM2 TRUE +#endif + +/** + * @brief ICUD3 driver enable switch. + * @details If set to @p TRUE the support for ICUD3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ICU_USE_TIM3) || defined(__DOXYGEN__) +#define STM32_ICU_USE_TIM3 TRUE +#endif + +/** + * @brief ICUD4 driver enable switch. + * @details If set to @p TRUE the support for ICUD4 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ICU_USE_TIM4) || defined(__DOXYGEN__) +#define STM32_ICU_USE_TIM4 TRUE +#endif + +/** + * @brief ICUD5 driver enable switch. + * @details If set to @p TRUE the support for ICUD5 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ICU_USE_TIM5) || defined(__DOXYGEN__) +#define STM32_ICU_USE_TIM5 TRUE +#endif + +/** + * @brief ICUD8 driver enable switch. + * @details If set to @p TRUE the support for ICUD8 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ICU_USE_TIM8) || defined(__DOXYGEN__) +#define STM32_ICU_USE_TIM8 TRUE +#endif + +/** + * @brief ICUD1 interrupt priority level setting. + */ +#if !defined(STM32_ICU_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#endif + +/** + * @brief ICUD2 interrupt priority level setting. + */ +#if !defined(STM32_ICU_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#endif + +/** + * @brief ICUD3 interrupt priority level setting. + */ +#if !defined(STM32_ICU_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#endif + +/** + * @brief ICUD4 interrupt priority level setting. + */ +#if !defined(STM32_ICU_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#endif + +/** + * @brief ICUD5 interrupt priority level setting. + */ +#if !defined(STM32_ICU_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#endif + +/** + * @brief ICUD8 interrupt priority level setting. + */ +#if !defined(STM32_ICU_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_ICU_USE_TIM1 && !STM32_HAS_TIM1 +#error "TIM1 not present in the selected device" +#endif + +#if STM32_ICU_USE_TIM2 && !STM32_HAS_TIM2 +#error "TIM2 not present in the selected device" +#endif + +#if STM32_ICU_USE_TIM3 && !STM32_HAS_TIM3 +#error "TIM3 not present in the selected device" +#endif + +#if STM32_ICU_USE_TIM4 && !STM32_HAS_TIM4 +#error "TIM4 not present in the selected device" +#endif + +#if STM32_ICU_USE_TIM5 && !STM32_HAS_TIM5 +#error "TIM5 not present in the selected device" +#endif + +#if STM32_ICU_USE_TIM8 && !STM32_HAS_TIM8 +#error "TIM8 not present in the selected device" +#endif + +#if !STM32_ICU_USE_TIM1 && !STM32_ICU_USE_TIM2 && \ + !STM32_ICU_USE_TIM3 && !STM32_ICU_USE_TIM4 && \ + !STM32_ICU_USE_TIM5 && !STM32_ICU_USE_TIM8 +#error "ICU driver activated but no TIM peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ICU driver mode. + */ +typedef enum { + ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge. */ + ICU_INPUT_ACTIVE_LOW = 1, /**< Trigger on falling edge. */ +} icumode_t; + +/** + * @brief ICU frequency type. + */ +typedef uint32_t icufreq_t; + +/** + * @brief ICU counter type. + */ +typedef uint16_t icucnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Driver mode. + */ + icumode_t mode; + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + icufreq_t frequency; + /** + * @brief Callback for pulse width measurement. + */ + icucallback_t width_cb; + /** + * @brief Callback for cycle period measurement. + */ + icucallback_t period_cb; + /* End of the mandatory fields.*/ +} ICUConfig; + +/** + * @brief Structure representing an ICU driver. + */ +struct ICUDriver { + /** + * @brief Driver state. + */ + icustate_t state; + /** + * @brief Current configuration data. + */ + const ICUConfig *config; +#if defined(ICU_DRIVER_EXT_FIELDS) + ICU_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Timer base clock. + */ + uint32_t clock; + /** + * @brief Pointer to the TIMx registers block. + */ + stm32_tim_t *tim; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the width of the latest pulse. + * @details The pulse width is defined as number of ticks between the start + * edge and the stop edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @notapi + */ +#define icu_lld_get_width(icup) ((icup)->tim->CCR[1] + 1) + +/** + * @brief Returns the width of the latest cycle. + * @details The cycle width is defined as number of ticks between a start + * edge and the next start edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @notapi + */ +#define icu_lld_get_period(icup) ((icup)->tim->CCR[0] + 1) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_ICU_USE_TIM1 && !defined(__DOXYGEN__) +extern ICUDriver ICUD1; +#endif + +#if STM32_ICU_USE_TIM2 && !defined(__DOXYGEN__) +extern ICUDriver ICUD2; +#endif + +#if STM32_ICU_USE_TIM3 && !defined(__DOXYGEN__) +extern ICUDriver ICUD3; +#endif + +#if STM32_ICU_USE_TIM4 && !defined(__DOXYGEN__) +extern ICUDriver ICUD4; +#endif + +#if STM32_ICU_USE_TIM5 && !defined(__DOXYGEN__) +extern ICUDriver ICUD5; +#endif + +#if STM32_ICU_USE_TIM8 && !defined(__DOXYGEN__) +extern ICUDriver ICUD8; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void icu_lld_init(void); + void icu_lld_start(ICUDriver *icup); + void icu_lld_stop(ICUDriver *icup); + void icu_lld_enable(ICUDriver *icup); + void icu_lld_disable(ICUDriver *icup); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ICU */ + +#endif /* _ICU_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/pwm_lld.c b/Project/os/hal/platforms/STM32/pwm_lld.c new file mode 100644 index 0000000..eab5f88 --- /dev/null +++ b/Project/os/hal/platforms/STM32/pwm_lld.c @@ -0,0 +1,644 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/pwm_lld.c + * @brief STM32 PWM subsystem low level driver header. + * + * @addtogroup PWM + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief PWMD1 driver identifier. + * @note The driver PWMD1 allocates the complex timer TIM1 when enabled. + */ +#if STM32_PWM_USE_TIM1 || defined(__DOXYGEN__) +PWMDriver PWMD1; +#endif + +/** + * @brief PWMD2 driver identifier. + * @note The driver PWMD2 allocates the timer TIM2 when enabled. + */ +#if STM32_PWM_USE_TIM2 || defined(__DOXYGEN__) +PWMDriver PWMD2; +#endif + +/** + * @brief PWMD3 driver identifier. + * @note The driver PWMD3 allocates the timer TIM3 when enabled. + */ +#if STM32_PWM_USE_TIM3 || defined(__DOXYGEN__) +PWMDriver PWMD3; +#endif + +/** + * @brief PWMD4 driver identifier. + * @note The driver PWMD4 allocates the timer TIM4 when enabled. + */ +#if STM32_PWM_USE_TIM4 || defined(__DOXYGEN__) +PWMDriver PWMD4; +#endif + +/** + * @brief PWMD5 driver identifier. + * @note The driver PWMD5 allocates the timer TIM5 when enabled. + */ +#if STM32_PWM_USE_TIM5 || defined(__DOXYGEN__) +PWMDriver PWMD5; +#endif + +/** + * @brief PWMD8 driver identifier. + * @note The driver PWMD5 allocates the timer TIM5 when enabled. + */ +#if STM32_PWM_USE_TIM8 || defined(__DOXYGEN__) +PWMDriver PWMD8; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +#if STM32_PWM_USE_TIM2 || STM32_PWM_USE_TIM3 || STM32_PWM_USE_TIM4 || \ + STM32_PWM_USE_TIM5 || defined(__DOXYGEN__) +/** + * @brief Common TIM2...TIM5 IRQ handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @param[in] pwmp pointer to a @p PWMDriver object + */ +static void serve_interrupt(PWMDriver *pwmp) { + uint16_t sr; + + sr = pwmp->tim->SR; + sr &= pwmp->tim->DIER; + pwmp->tim->SR = ~(TIM_SR_CC1IF | TIM_SR_CC2IF | TIM_SR_CC3IF | + TIM_SR_CC4IF | TIM_SR_UIF); + if ((sr & TIM_SR_CC1IF) != 0) + pwmp->config->channels[0].callback(pwmp); + if ((sr & TIM_SR_CC2IF) != 0) + pwmp->config->channels[1].callback(pwmp); + if ((sr & TIM_SR_CC3IF) != 0) + pwmp->config->channels[2].callback(pwmp); + if ((sr & TIM_SR_CC4IF) != 0) + pwmp->config->channels[3].callback(pwmp); + if ((sr & TIM_SR_UIF) != 0) + pwmp->config->callback(pwmp); +} +#endif /* STM32_PWM_USE_TIM2 || ... || STM32_PWM_USE_TIM5 */ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_PWM_USE_TIM1 +/** + * @brief TIM1 update interrupt handler. + * @note It is assumed that this interrupt is only activated if the callback + * pointer is not equal to @p NULL in order to not perform an extra + * check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM1_UP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + STM32_TIM1->SR = ~TIM_SR_UIF; + PWMD1.config->callback(&PWMD1); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief TIM1 compare interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM1_CC_IRQHandler) { + uint16_t sr; + + CH_IRQ_PROLOGUE(); + + sr = STM32_TIM1->SR & STM32_TIM1->DIER; + STM32_TIM1->SR = ~(TIM_SR_CC1IF | TIM_SR_CC2IF | + TIM_SR_CC3IF | TIM_SR_CC4IF); + if ((sr & TIM_SR_CC1IF) != 0) + PWMD1.config->channels[0].callback(&PWMD1); + if ((sr & TIM_SR_CC2IF) != 0) + PWMD1.config->channels[1].callback(&PWMD1); + if ((sr & TIM_SR_CC3IF) != 0) + PWMD1.config->channels[2].callback(&PWMD1); + if ((sr & TIM_SR_CC4IF) != 0) + PWMD1.config->channels[3].callback(&PWMD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_PWM_USE_TIM1 */ + +#if STM32_PWM_USE_TIM2 +/** + * @brief TIM2 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM2_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&PWMD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_PWM_USE_TIM2 */ + +#if STM32_PWM_USE_TIM3 +/** + * @brief TIM3 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM3_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&PWMD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_PWM_USE_TIM3 */ + +#if STM32_PWM_USE_TIM4 +/** + * @brief TIM4 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM4_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&PWMD4); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_PWM_USE_TIM4 */ + +#if STM32_PWM_USE_TIM5 +/** + * @brief TIM5 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM5_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&PWMD5); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_PWM_USE_TIM5 */ + +#if STM32_PWM_USE_TIM8 +/** + * @brief TIM8 update interrupt handler. + * @note It is assumed that this interrupt is only activated if the callback + * pointer is not equal to @p NULL in order to not perform an extra + * check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM8_UP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + STM32_TIM8->SR = ~TIM_SR_UIF; + PWMD8.config->callback(&PWMD8); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief TIM8 compare interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(TIM8_CC_IRQHandler) { + uint16_t sr; + + CH_IRQ_PROLOGUE(); + + sr = STM32_TIM8->SR & STM32_TIM8->DIER; + STM32_TIM8->SR = ~(TIM_SR_CC1IF | TIM_SR_CC2IF | TIM_SR_CC3IF | TIM_SR_CC4IF); + if ((sr & TIM_SR_CC1IF) != 0) + PWMD8.config->channels[0].callback(&PWMD8); + if ((sr & TIM_SR_CC2IF) != 0) + PWMD8.config->channels[1].callback(&PWMD8); + if ((sr & TIM_SR_CC3IF) != 0) + PWMD8.config->channels[2].callback(&PWMD8); + if ((sr & TIM_SR_CC4IF) != 0) + PWMD8.config->channels[3].callback(&PWMD8); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_PWM_USE_TIM8 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level PWM driver initialization. + * + * @notapi + */ +void pwm_lld_init(void) { + +#if STM32_PWM_USE_TIM1 + /* Driver initialization.*/ + pwmObjectInit(&PWMD1); + PWMD1.tim = STM32_TIM1; +#endif + +#if STM32_PWM_USE_TIM2 + /* Driver initialization.*/ + pwmObjectInit(&PWMD2); + PWMD2.tim = STM32_TIM2; +#endif + +#if STM32_PWM_USE_TIM3 + /* Driver initialization.*/ + pwmObjectInit(&PWMD3); + PWMD3.tim = STM32_TIM3; +#endif + +#if STM32_PWM_USE_TIM4 + /* Driver initialization.*/ + pwmObjectInit(&PWMD4); + PWMD4.tim = STM32_TIM4; +#endif + +#if STM32_PWM_USE_TIM5 + /* Driver initialization.*/ + pwmObjectInit(&PWMD5); + PWMD5.tim = STM32_TIM5; +#endif + +#if STM32_PWM_USE_TIM8 + /* Driver initialization.*/ + pwmObjectInit(&PWMD8); + PWMD8.tim = STM32_TIM8; +#endif +} + +/** + * @brief Configures and activates the PWM peripheral. + * @note Starting a driver that is already in the @p PWM_READY state + * disables all the active channels. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_start(PWMDriver *pwmp) { + uint32_t psc; + uint16_t ccer; + + if (pwmp->state == PWM_STOP) { + /* Clock activation and timer reset.*/ +#if STM32_PWM_USE_TIM1 + if (&PWMD1 == pwmp) { + rccEnableTIM1(FALSE); + rccResetTIM1(); + nvicEnableVector(TIM1_UP_IRQn, + CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY)); + nvicEnableVector(TIM1_CC_IRQn, + CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY)); + pwmp->clock = STM32_TIMCLK2; + } +#endif +#if STM32_PWM_USE_TIM2 + if (&PWMD2 == pwmp) { + rccEnableTIM2(FALSE); + rccResetTIM2(); + nvicEnableVector(TIM2_IRQn, + CORTEX_PRIORITY_MASK(STM32_PWM_TIM2_IRQ_PRIORITY)); + pwmp->clock = STM32_TIMCLK1; + } +#endif +#if STM32_PWM_USE_TIM3 + if (&PWMD3 == pwmp) { + rccEnableTIM3(FALSE); + rccResetTIM3(); + nvicEnableVector(TIM3_IRQn, + CORTEX_PRIORITY_MASK(STM32_PWM_TIM3_IRQ_PRIORITY)); + pwmp->clock = STM32_TIMCLK1; + } +#endif +#if STM32_PWM_USE_TIM4 + if (&PWMD4 == pwmp) { + rccEnableTIM4(FALSE); + rccResetTIM4(); + nvicEnableVector(TIM4_IRQn, + CORTEX_PRIORITY_MASK(STM32_PWM_TIM4_IRQ_PRIORITY)); + pwmp->clock = STM32_TIMCLK1; + } +#endif + +#if STM32_PWM_USE_TIM5 + if (&PWMD5 == pwmp) { + rccEnableTIM5(FALSE); + rccResetTIM5(); + nvicEnableVector(TIM5_IRQn, + CORTEX_PRIORITY_MASK(STM32_PWM_TIM5_IRQ_PRIORITY)); + pwmp->clock = STM32_TIMCLK1; + } +#endif +#if STM32_PWM_USE_TIM8 + if (&PWMD8 == pwmp) { + rccEnableTIM8(FALSE); + rccResetTIM8(); + nvicEnableVector(TIM8_UP_IRQn, + CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY)); + nvicEnableVector(TIM8_CC_IRQn, + CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY)); + pwmp->clock = STM32_TIMCLK2; + } +#endif + + /* All channels configured in PWM1 mode with preload enabled and will + stay that way until the driver is stopped.*/ + pwmp->tim->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | + TIM_CCMR1_OC1PE | + TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2 | + TIM_CCMR1_OC2PE; + pwmp->tim->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 | + TIM_CCMR2_OC3PE | + TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2 | + TIM_CCMR2_OC4PE; + } + else { + /* Driver re-configuration scenario, it must be stopped first.*/ + pwmp->tim->CR1 = 0; /* Timer disabled. */ + pwmp->tim->DIER = 0; /* All IRQs disabled. */ + pwmp->tim->SR = 0; /* Clear eventual pending IRQs. */ + pwmp->tim->CCR[0] = 0; /* Comparator 1 disabled. */ + pwmp->tim->CCR[1] = 0; /* Comparator 2 disabled. */ + pwmp->tim->CCR[2] = 0; /* Comparator 3 disabled. */ + pwmp->tim->CCR[3] = 0; /* Comparator 4 disabled. */ + pwmp->tim->CNT = 0; /* Counter reset to zero. */ + } + + /* Timer configuration.*/ + psc = (pwmp->clock / pwmp->config->frequency) - 1; + chDbgAssert((psc <= 0xFFFF) && + ((psc + 1) * pwmp->config->frequency) == pwmp->clock, + "pwm_lld_start(), #1", "invalid frequency"); + pwmp->tim->PSC = (uint16_t)psc; + pwmp->tim->ARR = (uint16_t)(pwmp->period - 1); + pwmp->tim->CR2 = pwmp->config->cr2; + + /* Output enables and polarities setup.*/ + ccer = 0; + switch (pwmp->config->channels[0].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + ccer |= TIM_CCER_CC1P; + case PWM_OUTPUT_ACTIVE_HIGH: + ccer |= TIM_CCER_CC1E; + default: + ; + } + switch (pwmp->config->channels[1].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + ccer |= TIM_CCER_CC2P; + case PWM_OUTPUT_ACTIVE_HIGH: + ccer |= TIM_CCER_CC2E; + default: + ; + } + switch (pwmp->config->channels[2].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + ccer |= TIM_CCER_CC3P; + case PWM_OUTPUT_ACTIVE_HIGH: + ccer |= TIM_CCER_CC3E; + default: + ; + } + switch (pwmp->config->channels[3].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + ccer |= TIM_CCER_CC4P; + case PWM_OUTPUT_ACTIVE_HIGH: + ccer |= TIM_CCER_CC4E; + default: + ; + } +#if STM32_PWM_USE_ADVANCED +#if STM32_PWM_USE_TIM1 && !STM32_PWM_USE_TIM8 + if (&PWMD1 == pwmp) { +#endif +#if !STM32_PWM_USE_TIM1 && STM32_PWM_USE_TIM8 + if (&PWMD8 == pwmp) { +#endif +#if STM32_PWM_USE_TIM1 && STM32_PWM_USE_TIM8 + if ((&PWMD1 == pwmp) || (&PWMD8 == pwmp)) { +#endif + switch (pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: + ccer |= TIM_CCER_CC1NP; + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: + ccer |= TIM_CCER_CC1NE; + default: + ; + } + switch (pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: + ccer |= TIM_CCER_CC2NP; + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: + ccer |= TIM_CCER_CC2NE; + default: + ; + } + switch (pwmp->config->channels[2].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: + ccer |= TIM_CCER_CC3NP; + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: + ccer |= TIM_CCER_CC3NE; + default: + ; + } + } +#endif /* STM32_PWM_USE_ADVANCED*/ + + pwmp->tim->CCER = ccer; + pwmp->tim->EGR = TIM_EGR_UG; /* Update event. */ + pwmp->tim->DIER = pwmp->config->callback == NULL ? 0 : TIM_DIER_UIE; + pwmp->tim->SR = 0; /* Clear pending IRQs. */ +#if STM32_PWM_USE_TIM1 || STM32_PWM_USE_TIM8 +#if STM32_PWM_USE_ADVANCED + pwmp->tim->BDTR = pwmp->config->bdtr | TIM_BDTR_MOE; +#else + pwmp->tim->BDTR = TIM_BDTR_MOE; +#endif +#endif + /* Timer configured and started.*/ + pwmp->tim->CR1 = TIM_CR1_ARPE | TIM_CR1_URS | TIM_CR1_CEN; +} + +/** + * @brief Deactivates the PWM peripheral. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_stop(PWMDriver *pwmp) { + + /* If in ready state then disables the PWM clock.*/ + if (pwmp->state == PWM_READY) { + pwmp->tim->CR1 = 0; /* Timer disabled. */ + pwmp->tim->DIER = 0; /* All IRQs disabled. */ + pwmp->tim->SR = 0; /* Clear eventual pending IRQs. */ +#if STM32_PWM_USE_TIM1 || STM32_PWM_USE_TIM8 + pwmp->tim->BDTR = 0; +#endif + +#if STM32_PWM_USE_TIM1 + if (&PWMD1 == pwmp) { + nvicDisableVector(TIM1_UP_IRQn); + nvicDisableVector(TIM1_CC_IRQn); + rccDisableTIM1(FALSE); + } +#endif +#if STM32_PWM_USE_TIM2 + if (&PWMD2 == pwmp) { + nvicDisableVector(TIM2_IRQn); + rccDisableTIM2(FALSE); + } +#endif +#if STM32_PWM_USE_TIM3 + if (&PWMD3 == pwmp) { + nvicDisableVector(TIM3_IRQn); + rccDisableTIM3(FALSE); + } +#endif +#if STM32_PWM_USE_TIM4 + if (&PWMD4 == pwmp) { + nvicDisableVector(TIM4_IRQn); + rccDisableTIM4(FALSE); + } +#endif +#if STM32_PWM_USE_TIM5 + if (&PWMD5 == pwmp) { + nvicDisableVector(TIM5_IRQn); + rccDisableTIM5(FALSE); + } +#endif +#if STM32_PWM_USE_TIM8 + if (&PWMD8 == pwmp) { + nvicDisableVector(TIM8_UP_IRQn); + nvicDisableVector(TIM8_CC_IRQn); + rccDisableTIM8(FALSE); + } +#endif + } +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note The function has effect at the next cycle start. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @notapi + */ +void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width) { + + pwmp->tim->CCR[channel] = width; /* New duty cycle. */ + /* If there is a callback defined for the channel then the associated + interrupt must be enabled.*/ + if (pwmp->config->channels[channel].callback != NULL) { + uint32_t dier = pwmp->tim->DIER; + /* If the IRQ is not already enabled care must be taken to clear it, + it is probably already pending because the timer is running.*/ + if ((dier & (2 << channel)) == 0) { + pwmp->tim->DIER = dier | (2 << channel); + pwmp->tim->SR = ~(2 << channel); + } + } +} + +/** + * @brief Disables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note The function has effect at the next cycle start. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * + * @notapi + */ +void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { + + pwmp->tim->CCR[channel] = 0; + pwmp->tim->DIER &= ~(2 << channel); +} + +#endif /* HAL_USE_PWM */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/pwm_lld.h b/Project/os/hal/platforms/STM32/pwm_lld.h new file mode 100644 index 0000000..9313cf7 --- /dev/null +++ b/Project/os/hal/platforms/STM32/pwm_lld.h @@ -0,0 +1,409 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/pwm_lld.h + * @brief STM32 PWM subsystem low level driver header. + * + * @addtogroup PWM + * @{ + */ + +#ifndef _PWM_LLD_H_ +#define _PWM_LLD_H_ + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Number of PWM channels per PWM driver. + */ +#define PWM_CHANNELS 4 + +/** + * @brief Complementary output modes mask. + * @note This is an STM32-specific setting. + */ +#define PWM_COMPLEMENTARY_OUTPUT_MASK 0xF0 + +/** + * @brief Complementary output not driven. + * @note This is an STM32-specific setting. + */ +#define PWM_COMPLEMENTARY_OUTPUT_DISABLED 0x00 + +/** + * @brief Complementary output, active is logic level one. + * @note This is an STM32-specific setting. + * @note This setting is only available if the configuration option + * @p STM32_PWM_USE_ADVANCED is set to TRUE and only for advanced + * timers TIM1 and TIM8. + */ +#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH 0x10 + +/** + * @brief Complementary output, active is logic level zero. + * @note This is an STM32-specific setting. + * @note This setting is only available if the configuration option + * @p STM32_PWM_USE_ADVANCED is set to TRUE and only for advanced + * timers TIM1 and TIM8. + */ +#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW 0x20 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief If advanced timer features switch. + * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are + * enabled. + * @note The default is @p TRUE. + */ +#if !defined(STM32_PWM_USE_ADVANCED) || defined(__DOXYGEN__) +#define STM32_PWM_USE_ADVANCED TRUE +#endif + +/** + * @brief PWMD1 driver enable switch. + * @details If set to @p TRUE the support for PWMD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_PWM_USE_TIM1) || defined(__DOXYGEN__) +#define STM32_PWM_USE_TIM1 TRUE +#endif + +/** + * @brief PWMD2 driver enable switch. + * @details If set to @p TRUE the support for PWMD2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_PWM_USE_TIM2) || defined(__DOXYGEN__) +#define STM32_PWM_USE_TIM2 TRUE +#endif + +/** + * @brief PWMD3 driver enable switch. + * @details If set to @p TRUE the support for PWMD3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_PWM_USE_TIM3) || defined(__DOXYGEN__) +#define STM32_PWM_USE_TIM3 TRUE +#endif + +/** + * @brief PWMD4 driver enable switch. + * @details If set to @p TRUE the support for PWMD4 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_PWM_USE_TIM4) || defined(__DOXYGEN__) +#define STM32_PWM_USE_TIM4 TRUE +#endif + +/** + * @brief PWMD5 driver enable switch. + * @details If set to @p TRUE the support for PWMD5 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_PWM_USE_TIM5) || defined(__DOXYGEN__) +#define STM32_PWM_USE_TIM5 TRUE +#endif + +/** + * @brief PWMD8 driver enable switch. + * @details If set to @p TRUE the support for PWMD8 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_PWM_USE_TIM8) || defined(__DOXYGEN__) +#define STM32_PWM_USE_TIM8 TRUE +#endif + +/** + * @brief PWMD1 interrupt priority level setting. + */ +#if !defined(STM32_PWM_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWMD2 interrupt priority level setting. + */ +#if !defined(STM32_PWM_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWMD3 interrupt priority level setting. + */ +#if !defined(STM32_PWM_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWMD4 interrupt priority level setting. + */ +#if !defined(STM32_PWM_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWMD5 interrupt priority level setting. + */ +#if !defined(STM32_PWM_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWMD8 interrupt priority level setting. + */ +#if !defined(STM32_PWM_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#endif +/** @} */ + +/*===========================================================================*/ +/* Configuration checks. */ +/*===========================================================================*/ + +#if STM32_PWM_USE_TIM1 && !STM32_HAS_TIM1 +#error "TIM1 not present in the selected device" +#endif + +#if STM32_PWM_USE_TIM2 && !STM32_HAS_TIM2 +#error "TIM2 not present in the selected device" +#endif + +#if STM32_PWM_USE_TIM3 && !STM32_HAS_TIM3 +#error "TIM3 not present in the selected device" +#endif + +#if STM32_PWM_USE_TIM4 && !STM32_HAS_TIM4 +#error "TIM4 not present in the selected device" +#endif + +#if STM32_PWM_USE_TIM5 && !STM32_HAS_TIM5 +#error "TIM5 not present in the selected device" +#endif + +#if STM32_PWM_USE_TIM8 && !STM32_HAS_TIM8 +#error "TIM8 not present in the selected device" +#endif + +#if !STM32_PWM_USE_TIM1 && !STM32_PWM_USE_TIM2 && \ + !STM32_PWM_USE_TIM3 && !STM32_PWM_USE_TIM4 && \ + !STM32_PWM_USE_TIM5 && !STM32_PWM_USE_TIM8 +#error "PWM driver activated but no TIM peripheral assigned" +#endif + +#if STM32_PWM_USE_ADVANCED && !STM32_PWM_USE_TIM1 && !STM32_PWM_USE_TIM8 +#error "advanced mode selected but no advanced timer assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief PWM mode type. + */ +typedef uint32_t pwmmode_t; + +/** + * @brief PWM channel type. + */ +typedef uint8_t pwmchannel_t; + +/** + * @brief PWM counter type. + */ +typedef uint16_t pwmcnt_t; + +/** + * @brief PWM driver channel configuration structure. + */ +typedef struct { + /** + * @brief Channel active logic level. + */ + pwmmode_t mode; + /** + * @brief Channel callback pointer. + * @note This callback is invoked on the channel compare event. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /* End of the mandatory fields.*/ +} PWMChannelConfig; + +/** + * @brief PWM driver configuration structure. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + uint32_t frequency; + /** + * @brief PWM period in ticks. + * @note The low level can use assertions in order to catch invalid + * period specifications. + */ + pwmcnt_t period; + /** + * @brief Periodic callback pointer. + * @note This callback is invoked on PWM counter reset. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /** + * @brief Channels configurations. + */ + PWMChannelConfig channels[PWM_CHANNELS]; + /* End of the mandatory fields.*/ + /** + * @brief TIM CR2 register initialization data. + * @note The value of this field should normally be equal to zero. + */ + uint16_t cr2; +#if STM32_PWM_USE_ADVANCED || defined(__DOXYGEN__) + /** + * @brief TIM BDTR (break & dead-time) register initialization data. + * @note The value of this field should normally be equal to zero. + */ \ + uint16_t bdtr; +#endif +} PWMConfig; + +/** + * @brief Structure representing a PWM driver. + */ +struct PWMDriver { + /** + * @brief Driver state. + */ + pwmstate_t state; + /** + * @brief Current driver configuration data. + */ + const PWMConfig *config; + /** + * @brief Current PWM period in ticks. + */ + pwmcnt_t period; +#if defined(PWM_DRIVER_EXT_FIELDS) + PWM_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Timer base clock. + */ + uint32_t clock; + /** + * @brief Pointer to the TIMx registers block. + */ + stm32_tim_t *tim; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note The function has effect at the next cycle start. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @notapi + */ +#define pwm_lld_change_period(pwmp, period) \ + ((pwmp)->tim->ARR = (uint16_t)((period) - 1)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_PWM_USE_TIM1 && !defined(__DOXYGEN__) +extern PWMDriver PWMD1; +#endif + +#if STM32_PWM_USE_TIM2 && !defined(__DOXYGEN__) +extern PWMDriver PWMD2; +#endif + +#if STM32_PWM_USE_TIM3 && !defined(__DOXYGEN__) +extern PWMDriver PWMD3; +#endif + +#if STM32_PWM_USE_TIM4 && !defined(__DOXYGEN__) +extern PWMDriver PWMD4; +#endif + +#if STM32_PWM_USE_TIM5 && !defined(__DOXYGEN__) +extern PWMDriver PWMD5; +#endif + +#if STM32_PWM_USE_TIM8 && !defined(__DOXYGEN__) +extern PWMDriver PWMD8; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void pwm_lld_init(void); + void pwm_lld_start(PWMDriver *pwmp); + void pwm_lld_stop(PWMDriver *pwmp); + void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width); + void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PWM */ + +#endif /* _PWM_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/sdc_lld.c b/Project/os/hal/platforms/STM32/sdc_lld.c new file mode 100644 index 0000000..30f912a --- /dev/null +++ b/Project/os/hal/platforms/STM32/sdc_lld.c @@ -0,0 +1,738 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/sdc_lld.c + * @brief STM32 SDC subsystem low level driver source. + * + * @addtogroup SDC + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SDC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief SDCD1 driver identifier.*/ +SDCDriver SDCD1; + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +#if STM32_SDC_UNALIGNED_SUPPORT +/** + * @brief Buffer for temporary storage during unaligned transfers. + */ +static union { + uint32_t alignment; + uint8_t buf[SDC_BLOCK_SIZE]; +} u; +#endif + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Reads one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to read + * @param[out] buf pointer to the read buffer, it must be aligned to + * four bytes boundary + * @param[in] n number of blocks to read + * @return The operation status. + * @retval FALSE operation succeeded, the requested blocks have been + * read. + * @retval TRUE operation failed, the state of the buffer is uncertain. + * + * @notapi + */ +static bool_t sdc_lld_read_multiple(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf, uint32_t n) { + uint32_t resp[1]; + + /* Checks for errors and waits for the card to be ready for reading.*/ + if (_sdc_wait_for_transfer_state(sdcp)) + return TRUE; + + /* Prepares the DMA channel for reading.*/ + dmaStreamSetMemory0(STM32_DMA2_STREAM4, buf); + dmaStreamSetTransactionSize(STM32_DMA2_STREAM4, + (n * SDC_BLOCK_SIZE) / sizeof (uint32_t)); + dmaStreamSetMode(STM32_DMA2_STREAM4, + STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_PSIZE_WORD | + STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC); + + /* Setting up data transfer. + Options: Card to Controller, Block mode, DMA mode, 512 bytes blocks.*/ + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | + SDIO_MASK_DATAENDIE | SDIO_MASK_STBITERRIE; + SDIO->DLEN = n * SDC_BLOCK_SIZE; + SDIO->DCTRL = SDIO_DCTRL_DTDIR | + SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 | + SDIO_DCTRL_DMAEN | + SDIO_DCTRL_DTEN; + + /* DMA channel activation.*/ + dmaStreamEnable(STM32_DMA2_STREAM4); + + /* Read multiple blocks command.*/ + if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0) + startblk *= SDC_BLOCK_SIZE; + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_READ_MULTIPLE_BLOCK, + startblk, resp) || + SDC_R1_ERROR(resp[0])) + goto error; + + chSysLock(); + if (SDIO->MASK != 0) { + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_read_multiple(), #1", "not NULL"); + sdcp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_read_multiple(), #2", "not NULL"); + } + if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { + chSysUnlock(); + goto error; + } + dmaStreamDisable(STM32_DMA2_STREAM4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->DCTRL = 0; + chSysUnlock(); + + return sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_STOP_TRANSMISSION, 0, resp); +error: + dmaStreamDisable(STM32_DMA2_STREAM4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = 0; + SDIO->DCTRL = 0; + return TRUE; +} + +/** + * @brief Reads one block. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to read + * @param[out] buf pointer to the read buffer, it must be aligned to + * four bytes boundary + * @return The operation status. + * @retval FALSE operation succeeded, the requested blocks have been + * read. + * @retval TRUE operation failed, the state of the buffer is uncertain. + * + * @notapi + */ +static bool_t sdc_lld_read_single(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf) { + uint32_t resp[1]; + + /* Checks for errors and waits for the card to be ready for reading.*/ + if (_sdc_wait_for_transfer_state(sdcp)) + return TRUE; + + /* Prepares the DMA channel for reading.*/ + dmaStreamSetMemory0(STM32_DMA2_STREAM4, buf); + dmaStreamSetTransactionSize(STM32_DMA2_STREAM4, + SDC_BLOCK_SIZE / sizeof (uint32_t)); + dmaStreamSetMode(STM32_DMA2_STREAM4, + STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_PSIZE_WORD | + STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC); + + /* Setting up data transfer. + Options: Card to Controller, Block mode, DMA mode, 512 bytes blocks.*/ + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | + SDIO_MASK_DATAENDIE | SDIO_MASK_STBITERRIE; + SDIO->DLEN = SDC_BLOCK_SIZE; + SDIO->DCTRL = SDIO_DCTRL_DTDIR | + SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 | + SDIO_DCTRL_DMAEN | + SDIO_DCTRL_DTEN; + + /* DMA channel activation.*/ + dmaStreamEnable(STM32_DMA2_STREAM4); + + /* Read single block command.*/ + if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0) + startblk *= SDC_BLOCK_SIZE; + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_READ_SINGLE_BLOCK, + startblk, resp) || + SDC_R1_ERROR(resp[0])) + goto error; + + chSysLock(); + if (SDIO->MASK != 0) { + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_read_single(), #1", "not NULL"); + sdcp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_read_single(), #2", "not NULL"); + } + if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { + chSysUnlock(); + goto error; + } + dmaStreamDisable(STM32_DMA2_STREAM4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->DCTRL = 0; + chSysUnlock(); + + return FALSE; +error: + dmaStreamDisable(STM32_DMA2_STREAM4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = 0; + SDIO->DCTRL = 0; + return TRUE; +} + +/** + * @brief Writes one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to write + * @param[out] buf pointer to the write buffer, it must be aligned to + * four bytes boundary + * @param[in] n number of blocks to write + * @return The operation status. + * @retval FALSE operation succeeded, the requested blocks have been + * written. + * @retval TRUE operation failed. + * + * @notapi + */ +static bool_t sdc_lld_write_multiple(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf, uint32_t n) { + uint32_t resp[1]; + + /* Checks for errors and waits for the card to be ready for writing.*/ + if (_sdc_wait_for_transfer_state(sdcp)) + return TRUE; + + /* Prepares the DMA channel for writing.*/ + dmaStreamSetMemory0(STM32_DMA2_STREAM4, buf); + dmaStreamSetTransactionSize(STM32_DMA2_STREAM4, + (n * SDC_BLOCK_SIZE) / sizeof (uint32_t)); + dmaStreamSetMode(STM32_DMA2_STREAM4, + STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) | + STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_PSIZE_WORD | + STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC); + + /* Write multiple blocks command.*/ + if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0) + startblk *= SDC_BLOCK_SIZE; + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_WRITE_MULTIPLE_BLOCK, + startblk, resp) || + SDC_R1_ERROR(resp[0])) + return TRUE; + + /* Setting up data transfer. + Options: Controller to Card, Block mode, DMA mode, 512 bytes blocks.*/ + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | + SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE | + SDIO_MASK_STBITERRIE; + SDIO->DLEN = n * SDC_BLOCK_SIZE; + SDIO->DCTRL = SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 | + SDIO_DCTRL_DMAEN | + SDIO_DCTRL_DTEN; + + /* DMA channel activation.*/ + dmaStreamEnable(STM32_DMA2_STREAM4); + + /* Note the mask is checked before going to sleep because the interrupt + may have occurred before reaching the critical zone.*/ + chSysLock(); + if (SDIO->MASK != 0) { + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_write_multiple(), #1", "not NULL"); + sdcp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_write_multiple(), #2", "not NULL"); + } + if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { + chSysUnlock(); + goto error; + } + dmaStreamDisable(STM32_DMA2_STREAM4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->DCTRL = 0; + chSysUnlock(); + + return sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_STOP_TRANSMISSION, 0, resp); +error: + dmaStreamDisable(STM32_DMA2_STREAM4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = 0; + SDIO->DCTRL = 0; + return TRUE; +} + +/** + * @brief Writes one block. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to write + * @param[out] buf pointer to the write buffer, it must be aligned to + * four bytes boundary + * @param[in] n number of blocks to write + * @return The operation status. + * @retval FALSE operation succeeded, the requested blocks have been + * written. + * @retval TRUE operation failed. + * + * @notapi + */ +static bool_t sdc_lld_write_single(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf) { + uint32_t resp[1]; + + /* Checks for errors and waits for the card to be ready for writing.*/ + if (_sdc_wait_for_transfer_state(sdcp)) + return TRUE; + + /* Prepares the DMA channel for writing.*/ + dmaStreamSetMemory0(STM32_DMA2_STREAM4, buf); + dmaStreamSetTransactionSize(STM32_DMA2_STREAM4, + SDC_BLOCK_SIZE / sizeof (uint32_t)); + dmaStreamSetMode(STM32_DMA2_STREAM4, + STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) | + STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_PSIZE_WORD | + STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC); + + /* Write single block command.*/ + if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0) + startblk *= SDC_BLOCK_SIZE; + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_WRITE_BLOCK, + startblk, resp) || + SDC_R1_ERROR(resp[0])) + return TRUE; + + /* Setting up data transfer. + Options: Controller to Card, Block mode, DMA mode, 512 bytes blocks.*/ + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | + SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE | + SDIO_MASK_STBITERRIE; + SDIO->DLEN = SDC_BLOCK_SIZE; + SDIO->DCTRL = SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 | + SDIO_DCTRL_DMAEN | + SDIO_DCTRL_DTEN; + + /* DMA channel activation.*/ + dmaStreamEnable(STM32_DMA2_STREAM4); + + /* Note the mask is checked before going to sleep because the interrupt + may have occurred before reaching the critical zone.*/ + chSysLock(); + if (SDIO->MASK != 0) { + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_write_single(), #1", "not NULL"); + sdcp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_write_single(), #2", "not NULL"); + } + if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { + chSysUnlock(); + goto error; + } + dmaStreamDisable(STM32_DMA2_STREAM4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->DCTRL = 0; + chSysUnlock(); + + return FALSE; +error: + dmaStreamDisable(STM32_DMA2_STREAM4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = 0; + SDIO->DCTRL = 0; + return TRUE; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief SDIO IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(SDIO_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + if (SDCD1.thread != NULL) { + chSchReadyI(SDCD1.thread); + SDCD1.thread = NULL; + } + chSysUnlockFromIsr(); + + /* Disables the source but the status flags are not reset because the + read/write functions need to check them.*/ + SDIO->MASK = 0; + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SDC driver initialization. + * + * @notapi + */ +void sdc_lld_init(void) { + + sdcObjectInit(&SDCD1); + SDCD1.thread = NULL; +} + +/** + * @brief Configures and activates the SDC peripheral. + * + * @param[in] sdcp pointer to the @p SDCDriver object, must be @p NULL, + * this driver does not require any configuration + * + * @notapi + */ +void sdc_lld_start(SDCDriver *sdcp) { + + if (sdcp->state == SDC_STOP) { + /* Note, the DMA must be enabled before the IRQs.*/ + dmaStreamAllocate(STM32_DMA2_STREAM4, 0, NULL, NULL); + dmaStreamSetPeripheral(STM32_DMA2_STREAM4, &SDIO->FIFO); + nvicEnableVector(SDIO_IRQn, + CORTEX_PRIORITY_MASK(STM32_SDC_SDIO_IRQ_PRIORITY)); + rccEnableSDIO(FALSE); + } + /* Configuration, card clock is initially stopped.*/ + SDIO->POWER = 0; + SDIO->CLKCR = 0; + SDIO->DCTRL = 0; + SDIO->DTIMER = STM32_SDC_DATATIMEOUT; +} + +/** + * @brief Deactivates the SDC peripheral. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_stop(SDCDriver *sdcp) { + + if ((sdcp->state == SDC_READY) || (sdcp->state == SDC_ACTIVE)) { + SDIO->POWER = 0; + SDIO->CLKCR = 0; + SDIO->DCTRL = 0; + SDIO->DTIMER = 0; + + /* Clock deactivation.*/ + nvicDisableVector(SDIO_IRQn); + dmaStreamRelease(STM32_DMA2_STREAM4); + rccDisableSDIO(FALSE); + } +} + +/** + * @brief Starts the SDIO clock and sets it to init mode (400kHz or less). + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_start_clk(SDCDriver *sdcp) { + + (void)sdcp; + /* Initial clock setting: 400kHz, 1bit mode.*/ + SDIO->CLKCR = STM32_SDIO_DIV_LS; + SDIO->POWER |= SDIO_POWER_PWRCTRL_0 | SDIO_POWER_PWRCTRL_1; + SDIO->CLKCR |= SDIO_CLKCR_CLKEN; +} + +/** + * @brief Sets the SDIO clock to data mode (25MHz or less). + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_set_data_clk(SDCDriver *sdcp) { + + (void)sdcp; + SDIO->CLKCR = (SDIO->CLKCR & 0xFFFFFF00) | STM32_SDIO_DIV_HS; +} + +/** + * @brief Stops the SDIO clock. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_stop_clk(SDCDriver *sdcp) { + + (void)sdcp; + SDIO->CLKCR = 0; + SDIO->POWER = 0; +} + +/** + * @brief Switches the bus to 4 bits mode. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] mode bus mode + * + * @notapi + */ +void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) { + uint32_t clk = SDIO->CLKCR & ~SDIO_CLKCR_WIDBUS; + + (void)sdcp; + switch (mode) { + case SDC_MODE_1BIT: + SDIO->CLKCR = clk; + break; + case SDC_MODE_4BIT: + SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_0; + break; + case SDC_MODE_8BIT: + SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_1; + } +} + +/** + * @brief Sends an SDIO command with no response expected. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * + * @notapi + */ +void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) { + + (void)sdcp; + SDIO->ARG = arg; + SDIO->CMD = (uint32_t)cmd | SDIO_CMD_CPSMEN; + while ((SDIO->STA & SDIO_STA_CMDSENT) == 0) + ; + SDIO->ICR = SDIO_ICR_CMDSENTC; +} + +/** + * @brief Sends an SDIO command with a short response expected. + * @note The CRC is not verified. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * @param[out] resp pointer to the response buffer (one word) + * @return The operation status. + * @retval FALSE the operation succeeded. + * @retval TRUE the operation failed because timeout, CRC check or + * other errors. + * + * @notapi + */ +bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp) { + uint32_t sta; + + (void)sdcp; + SDIO->ARG = arg; + SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN; + while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | + SDIO_STA_CCRCFAIL)) == 0) + ; + SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC; + if ((sta & (SDIO_STA_CTIMEOUT)) != 0) + return TRUE; + *resp = SDIO->RESP1; + return FALSE; +} + +/** + * @brief Sends an SDIO command with a short response expected and CRC. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * @param[out] resp pointer to the response buffer (one word) + * @return The operation status. + * @retval FALSE the operation succeeded. + * @retval TRUE the operation failed because timeout, CRC check or + * other errors. + * + * @notapi + */ +bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp) { + uint32_t sta; + + (void)sdcp; + SDIO->ARG = arg; + SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN; + while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | + SDIO_STA_CCRCFAIL)) == 0) + ; + SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC; + if ((sta & (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)) != 0) + return TRUE; + *resp = SDIO->RESP1; + return FALSE; +} + +/** + * @brief Sends an SDIO command with a long response expected and CRC. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * @param[out] resp pointer to the response buffer (four words) + * @return The operation status. + * @retval FALSE the operation succeeded. + * @retval TRUE the operation failed because timeout, CRC check or + * other errors. + * + * @notapi + */ +bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp) { + + uint32_t sta; + + (void)sdcp; + SDIO->ARG = arg; + SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_WAITRESP_1 | + SDIO_CMD_CPSMEN; + while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | + SDIO_STA_CCRCFAIL)) == 0) + ; + SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC; + if ((sta & (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)) != 0) + return TRUE; + *resp = SDIO->RESP1; + return FALSE; +} + +/** + * @brief Reads one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to read + * @param[out] buf pointer to the read buffer + * @param[in] n number of blocks to read + * @return The operation status. + * @retval FALSE operation succeeded, the requested blocks have been + * read. + * @retval TRUE operation failed, the state of the buffer is uncertain. + * + * @notapi + */ +bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf, uint32_t n) { + +#if STM32_SDC_UNALIGNED_SUPPORT + if (((unsigned)buf & 3) != 0) { + uint32_t i; + for (i = 0; i < n; i++) { + if (sdc_lld_read_single(sdcp, startblk, u.buf)) + return TRUE; + memcpy(buf, u.buf, SDC_BLOCK_SIZE); + buf += SDC_BLOCK_SIZE; + startblk++; + } + return FALSE; + } +#endif + if (n == 1) + return sdc_lld_read_single(sdcp, startblk, buf); + return sdc_lld_read_multiple(sdcp, startblk, buf, n); +} + +/** + * @brief Writes one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to write + * @param[out] buf pointer to the write buffer + * @param[in] n number of blocks to write + * @return The operation status. + * @retval FALSE operation succeeded, the requested blocks have been + * written. + * @retval TRUE operation failed. + * + * @notapi + */ +bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf, uint32_t n) { + +#if STM32_SDC_UNALIGNED_SUPPORT + if (((unsigned)buf & 3) != 0) { + uint32_t i; + for (i = 0; i < n; i++) { + memcpy(u.buf, buf, SDC_BLOCK_SIZE); + buf += SDC_BLOCK_SIZE; + if (sdc_lld_write_single(sdcp, startblk, u.buf)) + return TRUE; + startblk++; + } + return FALSE; + } +#endif + if (n == 1) + return sdc_lld_write_single(sdcp, startblk, buf); + return sdc_lld_write_multiple(sdcp, startblk, buf, n); +} + +#endif /* HAL_USE_SDC */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/sdc_lld.h b/Project/os/hal/platforms/STM32/sdc_lld.h new file mode 100644 index 0000000..22904d3 --- /dev/null +++ b/Project/os/hal/platforms/STM32/sdc_lld.h @@ -0,0 +1,215 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/sdc_lld.h + * @brief STM32 SDC subsystem low level driver header. + * + * @addtogroup SDC + * @{ + */ + +#ifndef _SDC_LLD_H_ +#define _SDC_LLD_H_ + +#if HAL_USE_SDC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief SDIO data timeout in SDIO clock cycles. + */ +#if !defined(STM32_SDC_DATATIMEOUT) || defined(__DOXYGEN__) +#define STM32_SDC_DATATIMEOUT 0x000FFFFF +#endif + +/** + * @brief SDIO DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_SDC_SDIO_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#endif + +/** + * @brief SDIO interrupt priority level setting. + */ +#if !defined(STM32_SDC_SDIO_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#endif + +/** + * @brief SDIO support for unaligned transfers. + */ +#if !defined(STM32_SDC_UNALIGNED_SUPPORT) || defined(__DOXYGEN__) +#define STM32_SDC_UNALIGNED_SUPPORT TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM32_HAS_SDIO +#error "SDIO not present in the selected device" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/* + * SDIO clock divider. + */ +#if STM32_HCLK > 48000000 +#define STM32_SDIO_DIV_HS 0x01 +#define STM32_SDIO_DIV_LS 0xB2 +#else +#define STM32_SDIO_DIV_HS 0x00 +#define STM32_SDIO_DIV_LS 0x76 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of SDIO bus mode. + */ +typedef enum { + SDC_MODE_1BIT = 0, + SDC_MODE_4BIT, + SDC_MODE_8BIT +} sdcbusmode_t; + +/** + * @brief Type of card flags. + */ +typedef uint32_t sdcmode_t; + +/** + * @brief Type of a structure representing an SDC driver. + */ +typedef struct SDCDriver SDCDriver; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} SDCConfig; + +/** + * @brief Structure representing an SDC driver. + */ +struct SDCDriver { + /** + * @brief Driver state. + */ + sdcstate_t state; + /** + * @brief Current configuration data. + */ + const SDCConfig *config; + /** + * @brief Various flags regarding the mounted card. + */ + sdcmode_t cardmode; + /** + * @brief Card CID. + */ + uint32_t cid[4]; + /** + * @brief Card CSD. + */ + uint32_t csd[4]; + /** + * @brief Card RCA. + */ + uint32_t rca; + /* End of the mandatory fields.*/ + /** + * @brief Thread waiting for I/O completion IRQ. + */ + Thread *thread; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern SDCDriver SDCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sdc_lld_init(void); + void sdc_lld_start(SDCDriver *sdcp); + void sdc_lld_stop(SDCDriver *sdcp); + void sdc_lld_start_clk(SDCDriver *sdcp); + void sdc_lld_set_data_clk(SDCDriver *sdcp); + void sdc_lld_stop_clk(SDCDriver *sdcp); + void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode); + void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg); + bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp); + bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp); + bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp); + bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf, uint32_t n); + bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf, uint32_t n); + bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp); + bool_t sdc_lld_is_write_protected(SDCDriver *sdcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SDC */ + +#endif /* _SDC_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/serial_lld.c b/Project/os/hal/platforms/STM32/serial_lld.c new file mode 100644 index 0000000..f11d26c --- /dev/null +++ b/Project/os/hal/platforms/STM32/serial_lld.c @@ -0,0 +1,528 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/serial_lld.c + * @brief STM32 low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief USART1 serial driver identifier.*/ +#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) +SerialDriver SD1; +#endif + +/** @brief USART2 serial driver identifier.*/ +#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/** @brief USART3 serial driver identifier.*/ +#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) +SerialDriver SD3; +#endif + +/** @brief UART4 serial driver identifier.*/ +#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) +SerialDriver SD4; +#endif + +/** @brief UART5 serial driver identifier.*/ +#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) +SerialDriver SD5; +#endif + +/** @brief USART6 serial driver identifier.*/ +#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) +SerialDriver SD6; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = +{ + SERIAL_DEFAULT_BITRATE, + 0, + USART_CR2_STOP1_BITS | USART_CR2_LINEN, + 0 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief USART initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration + */ +static void usart_init(SerialDriver *sdp, const SerialConfig *config) { + USART_TypeDef *u = sdp->usart; + + /* + * Baud rate setting. + */ +#if STM32_HAS_USART6 + if ((sdp->usart == USART1) || (sdp->usart == USART6)) +#else + if (sdp->usart == USART1) +#endif + u->BRR = STM32_PCLK2 / config->sc_speed; + else + u->BRR = STM32_PCLK1 / config->sc_speed; + + /* + * Note that some bits are enforced. + */ + u->CR1 = config->sc_cr1 | USART_CR1_UE | USART_CR1_PEIE | + USART_CR1_RXNEIE | USART_CR1_TE | + USART_CR1_RE; + u->CR2 = config->sc_cr2 | USART_CR2_LBDIE; + u->CR3 = config->sc_cr3 | USART_CR3_EIE; + u->SR = 0; + (void)u->SR; /* SR reset step 1.*/ + (void)u->DR; /* SR reset step 2.*/ +} + +/** + * @brief USART de-initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] u pointer to an USART I/O block + */ +static void usart_deinit(USART_TypeDef *u) { + + u->CR1 = 0; + u->CR2 = 0; + u->CR3 = 0; +} + +#if STM32_SERIAL_USE_USART1 || STM32_SERIAL_USE_USART2 || \ + STM32_SERIAL_USE_USART3 || STM32_SERIAL_USE_UART4 || \ + STM32_SERIAL_USE_UART5 || STM32_SERIAL_USE_USART6 +/** + * @brief Error handling routine. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] sr USART SR register value + */ +static void set_error(SerialDriver *sdp, uint16_t sr) { + ioflags_t sts = 0; + + if (sr & USART_SR_ORE) + sts |= SD_OVERRUN_ERROR; + if (sr & USART_SR_PE) + sts |= SD_PARITY_ERROR; + if (sr & USART_SR_FE) + sts |= SD_FRAMING_ERROR; + if (sr & USART_SR_NE) + sts |= SD_NOISE_ERROR; + chSysLockFromIsr(); + chIOAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +/** + * @brief Common IRQ handler. + * + * @param[in] sdp communication channel associated to the USART + */ +static void serve_interrupt(SerialDriver *sdp) { + USART_TypeDef *u = sdp->usart; + uint16_t cr1 = u->CR1; + uint16_t sr = u->SR; /* SR reset step 1.*/ + uint16_t dr = u->DR; /* SR reset step 2.*/ + + /* Error condition detection.*/ + if (sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE | USART_SR_PE)) + set_error(sdp, sr); + /* Special case, LIN break detection.*/ + if (sr & USART_SR_LBD) { + chSysLockFromIsr(); + chIOAddFlagsI(sdp, SD_BREAK_DETECTED); + chSysUnlockFromIsr(); + u->SR &= ~USART_SR_LBD; + } + /* Data available.*/ + if (sr & USART_SR_RXNE) { + chSysLockFromIsr(); + sdIncomingDataI(sdp, (uint8_t)dr); + chSysUnlockFromIsr(); + } + /* Transmission buffer empty.*/ + if ((cr1 & USART_CR1_TXEIE) && (sr & USART_SR_TXE)) { + msg_t b; + chSysLockFromIsr(); + b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) { + chIOAddFlagsI(sdp, IO_OUTPUT_EMPTY); + u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE; + } + else + u->DR = b; + chSysUnlockFromIsr(); + } + /* Physical transmission end.*/ + if (sr & USART_SR_TC) { + chSysLockFromIsr(); + chIOAddFlagsI(sdp, IO_TRANSMISSION_END); + chSysUnlockFromIsr(); + u->CR1 = cr1 & ~USART_CR1_TCIE; + u->SR &= ~USART_SR_TC; + } +} +#endif + +#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + USART1->CR1 |= USART_CR1_TXEIE; +} +#endif + +#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + USART2->CR1 |= USART_CR1_TXEIE; +} +#endif + +#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) +static void notify3(GenericQueue *qp) { + + (void)qp; + USART3->CR1 |= USART_CR1_TXEIE; +} +#endif + +#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) +static void notify4(GenericQueue *qp) { + + (void)qp; + UART4->CR1 |= USART_CR1_TXEIE; +} +#endif + +#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) +static void notify5(GenericQueue *qp) { + + (void)qp; + UART5->CR1 |= USART_CR1_TXEIE; +} +#endif + +#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) +static void notify6(GenericQueue *qp) { + + (void)qp; + USART6->CR1 |= USART_CR1_TXEIE; +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) +/** + * @brief USART1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART1_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD1); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) +/** + * @brief USART2 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART2_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD2); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) +/** + * @brief USART3 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART3_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD3); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) +/** + * @brief UART4 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(UART4_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD4); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) +/** + * @brief UART5 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(UART5_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD5); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) +/** + * @brief USART1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART6_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD6); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if STM32_SERIAL_USE_USART1 + sdObjectInit(&SD1, NULL, notify1); + SD1.usart = USART1; +#endif + +#if STM32_SERIAL_USE_USART2 + sdObjectInit(&SD2, NULL, notify2); + SD2.usart = USART2; +#endif + +#if STM32_SERIAL_USE_USART3 + sdObjectInit(&SD3, NULL, notify3); + SD3.usart = USART3; +#endif + +#if STM32_SERIAL_USE_UART4 + sdObjectInit(&SD4, NULL, notify4); + SD4.usart = UART4; +#endif + +#if STM32_SERIAL_USE_UART5 + sdObjectInit(&SD5, NULL, notify5); + SD5.usart = UART5; +#endif + +#if STM32_SERIAL_USE_USART6 + sdObjectInit(&SD6, NULL, notify6); + SD6.usart = USART6; +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + + if (sdp->state == SD_STOP) { +#if STM32_SERIAL_USE_USART1 + if (&SD1 == sdp) { + rccEnableUSART1(FALSE); + nvicEnableVector(USART1_IRQn, + CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY)); + } +#endif +#if STM32_SERIAL_USE_USART2 + if (&SD2 == sdp) { + rccEnableUSART2(FALSE); + nvicEnableVector(USART2_IRQn, + CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY)); + } +#endif +#if STM32_SERIAL_USE_USART3 + if (&SD3 == sdp) { + rccEnableUSART3(FALSE); + nvicEnableVector(USART3_IRQn, + CORTEX_PRIORITY_MASK(STM32_SERIAL_USART3_PRIORITY)); + } +#endif +#if STM32_SERIAL_USE_UART4 + if (&SD4 == sdp) { + rccEnableUART4(FALSE); + nvicEnableVector(UART4_IRQn, + CORTEX_PRIORITY_MASK(STM32_SERIAL_UART4_PRIORITY)); + } +#endif +#if STM32_SERIAL_USE_UART5 + if (&SD5 == sdp) { + rccEnableUART5(FALSE); + nvicEnableVector(UART5_IRQn, + CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY)); + } +#endif +#if STM32_SERIAL_USE_USART6 + if (&SD6 == sdp) { + rccEnableUSART6(FALSE); + nvicEnableVector(USART6_IRQn, + CORTEX_PRIORITY_MASK(STM32_SERIAL_USART6_PRIORITY)); + } +#endif + } + usart_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) { + usart_deinit(sdp->usart); +#if STM32_SERIAL_USE_USART1 + if (&SD1 == sdp) { + rccDisableUSART1(FALSE); + nvicDisableVector(USART1_IRQn); + return; + } +#endif +#if STM32_SERIAL_USE_USART2 + if (&SD2 == sdp) { + rccDisableUSART2(FALSE); + nvicDisableVector(USART2_IRQn); + return; + } +#endif +#if STM32_SERIAL_USE_USART3 + if (&SD3 == sdp) { + rccDisableUSART3(FALSE); + nvicDisableVector(USART3_IRQn); + return; + } +#endif +#if STM32_SERIAL_USE_UART4 + if (&SD4 == sdp) { + rccDisableUART4(FALSE); + nvicDisableVector(UART4_IRQn); + return; + } +#endif +#if STM32_SERIAL_USE_UART5 + if (&SD5 == sdp) { + rccDisableUART5(FALSE); + nvicDisableVector(UART5_IRQn); + return; + } +#endif +#if STM32_SERIAL_USE_USART6 + if (&SD6 == sdp) { + rccDisableUSART6(FALSE); + nvicDisableVector(USART6_IRQn); + return; + } +#endif + } +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/serial_lld.h b/Project/os/hal/platforms/STM32/serial_lld.h new file mode 100644 index 0000000..5a989c8 --- /dev/null +++ b/Project/os/hal/platforms/STM32/serial_lld.h @@ -0,0 +1,283 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/serial_lld.h + * @brief STM32 low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief USART1 driver enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SERIAL_USE_USART1) || defined(__DOXYGEN__) +#define STM32_SERIAL_USE_USART1 TRUE +#endif + +/** + * @brief USART2 driver enable switch. + * @details If set to @p TRUE the support for USART2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SERIAL_USE_USART2) || defined(__DOXYGEN__) +#define STM32_SERIAL_USE_USART2 TRUE +#endif + +/** + * @brief USART3 driver enable switch. + * @details If set to @p TRUE the support for USART3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SERIAL_USE_USART3) || defined(__DOXYGEN__) +#define STM32_SERIAL_USE_USART3 TRUE +#endif + +/** + * @brief UART4 driver enable switch. + * @details If set to @p TRUE the support for UART4 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SERIAL_USE_UART4) || defined(__DOXYGEN__) +#define STM32_SERIAL_USE_UART4 TRUE +#endif + +/** + * @brief UART5 driver enable switch. + * @details If set to @p TRUE the support for UART5 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SERIAL_USE_UART5) || defined(__DOXYGEN__) +#define STM32_SERIAL_USE_UART5 TRUE +#endif + +/** + * @brief USART6 driver enable switch. + * @details If set to @p TRUE the support for USART6 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SERIAL_USE_USART6) || defined(__DOXYGEN__) +#define STM32_SERIAL_USE_USART6 TRUE +#endif + +/** + * @brief USART1 interrupt priority level setting. + */ +#if !defined(STM32_SERIAL_USART1_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SERIAL_USART1_PRIORITY 12 +#endif + +/** + * @brief USART2 interrupt priority level setting. + */ +#if !defined(STM32_SERIAL_USART2_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SERIAL_USART2_PRIORITY 12 +#endif + +/** + * @brief USART3 interrupt priority level setting. + */ +#if !defined(STM32_SERIAL_USART3_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SERIAL_USART3_PRIORITY 12 +#endif + +/** + * @brief UART4 interrupt priority level setting. + */ +#if !defined(STM32_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SERIAL_UART4_PRIORITY 12 +#endif + +/** + * @brief UART5 interrupt priority level setting. + */ +#if !defined(STM32_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SERIAL_UART5_PRIORITY 12 +#endif + +/** + * @brief USART6 interrupt priority level setting. + */ +#if !defined(STM32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SERIAL_USART6_PRIORITY 12 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_SERIAL_USE_USART1 && !STM32_HAS_USART1 +#error "USART1 not present in the selected device" +#endif + +#if STM32_SERIAL_USE_USART2 && !STM32_HAS_USART2 +#error "USART2 not present in the selected device" +#endif + +#if STM32_SERIAL_USE_USART3 && !STM32_HAS_USART3 +#error "USART3 not present in the selected device" +#endif + +#if STM32_SERIAL_USE_UART4 && !STM32_HAS_UART4 +#error "UART4 not present in the selected device" +#endif + +#if STM32_SERIAL_USE_UART5 && !STM32_HAS_UART5 +#error "UART5 not present in the selected device" +#endif + +#if STM32_SERIAL_USE_USART6 && !STM32_HAS_USART6 +#error "USART6 not present in the selected device" +#endif + +#if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2 && \ + !STM32_SERIAL_USE_USART3 && !STM32_SERIAL_USE_UART4 && \ + !STM32_SERIAL_USE_UART5 && !STM32_SERIAL_USE_USART6 +#error "SERIAL driver activated but no USART/UART peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t sc_speed; + /** + * @brief Initialization value for the CR1 register. + */ + uint16_t sc_cr1; + /** + * @brief Initialization value for the CR2 register. + */ + uint16_t sc_cr2; + /** + * @brief Initialization value for the CR3 register. + */ + uint16_t sc_cr3; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the USART registers block.*/ \ + USART_TypeDef *usart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* + * Extra USARTs definitions here (missing from the ST header file). + */ +#define USART_CR2_STOP1_BITS (0 << 12) /**< @brief CR2 1 stop bit value.*/ +#define USART_CR2_STOP0P5_BITS (1 << 12) /**< @brief CR2 0.5 stop bit value.*/ +#define USART_CR2_STOP2_BITS (2 << 12) /**< @brief CR2 2 stop bit value.*/ +#define USART_CR2_STOP1P5_BITS (3 << 12) /**< @brief CR2 1.5 stop bit value.*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_SERIAL_USE_USART1 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if STM32_SERIAL_USE_USART2 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif +#if STM32_SERIAL_USE_USART3 && !defined(__DOXYGEN__) +extern SerialDriver SD3; +#endif +#if STM32_SERIAL_USE_UART4 && !defined(__DOXYGEN__) +extern SerialDriver SD4; +#endif +#if STM32_SERIAL_USE_UART5 && !defined(__DOXYGEN__) +extern SerialDriver SD5; +#endif +#if STM32_SERIAL_USE_USART6 && !defined(__DOXYGEN__) +extern SerialDriver SD6; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/spi_lld.c b/Project/os/hal/platforms/STM32/spi_lld.c new file mode 100644 index 0000000..c71fcad --- /dev/null +++ b/Project/os/hal/platforms/STM32/spi_lld.c @@ -0,0 +1,491 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/spi_lld.c + * @brief STM32 SPI subsystem low level driver source. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define SPI1_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_RX_DMA_STREAM, \ + STM32_SPI1_RX_DMA_CHN) + +#define SPI1_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_TX_DMA_STREAM, \ + STM32_SPI1_TX_DMA_CHN) + +#define SPI2_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_RX_DMA_STREAM, \ + STM32_SPI2_RX_DMA_CHN) + +#define SPI2_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_TX_DMA_STREAM, \ + STM32_SPI2_TX_DMA_CHN) + +#define SPI3_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_RX_DMA_STREAM, \ + STM32_SPI3_RX_DMA_CHN) + +#define SPI3_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_TX_DMA_STREAM, \ + STM32_SPI3_TX_DMA_CHN) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief SPI1 driver identifier.*/ +#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__) +SPIDriver SPID1; +#endif + +/** @brief SPI2 driver identifier.*/ +#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__) +SPIDriver SPID2; +#endif + +/** @brief SPI3 driver identifier.*/ +#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__) +SPIDriver SPID3; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +static uint16_t dummytx; +static uint16_t dummyrx; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared end-of-rx service routine. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_SPI_DMA_ERROR_HOOK) + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_SPI_DMA_ERROR_HOOK(spip); + } +#else + (void)flags; +#endif + + /* Stop everything.*/ + dmaStreamDisable(spip->dmatx); + dmaStreamDisable(spip->dmarx); + + /* Portable SPI ISR code defined in the high level driver, note, it is + a macro.*/ + _spi_isr_code(spip); +} + +/** + * @brief Shared end-of-tx service routine. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_SPI_DMA_ERROR_HOOK) + (void)spip; + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_SPI_DMA_ERROR_HOOK(spip); + } +#else + (void)spip; + (void)flags; +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + + dummytx = 0xFFFF; + +#if STM32_SPI_USE_SPI1 + spiObjectInit(&SPID1); + SPID1.spi = SPI1; + SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM); + SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM); + SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE; + SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE; +#endif + +#if STM32_SPI_USE_SPI2 + spiObjectInit(&SPID2); + SPID2.spi = SPI2; + SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM); + SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM); + SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE; + SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | + STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE; +#endif + +#if STM32_SPI_USE_SPI3 + spiObjectInit(&SPID3); + SPID3.spi = SPI3; + SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM); + SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM); + SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE; + SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | + STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE; +#endif +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + /* If in stopped state then enables the SPI and DMA clocks.*/ + if (spip->state == SPI_STOP) { +#if STM32_SPI_USE_SPI1 + if (&SPID1 == spip) { + bool_t b; + b = dmaStreamAllocate(spip->dmarx, + STM32_SPI_SPI1_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated"); + b = dmaStreamAllocate(spip->dmatx, + STM32_SPI_SPI1_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated"); + rccEnableSPI1(FALSE); + } +#endif +#if STM32_SPI_USE_SPI2 + if (&SPID2 == spip) { + bool_t b; + b = dmaStreamAllocate(spip->dmarx, + STM32_SPI_SPI2_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated"); + b = dmaStreamAllocate(spip->dmatx, + STM32_SPI_SPI2_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated"); + rccEnableSPI2(FALSE); + } +#endif +#if STM32_SPI_USE_SPI3 + if (&SPID3 == spip) { + bool_t b; + b = dmaStreamAllocate(spip->dmarx, + STM32_SPI_SPI3_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated"); + b = dmaStreamAllocate(spip->dmatx, + STM32_SPI_SPI3_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated"); + rccEnableSPI3(FALSE); + } +#endif + + /* DMA setup.*/ + dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DR); + dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR); + } + + /* Configuration-specific DMA setup.*/ + if ((spip->config->cr1 & SPI_CR1_DFF) == 0) { /* 8 bits transfers. */ + spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; + spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; + } + else { /* 16 bits transfers. */ + spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + } + /* SPI setup and enable.*/ + spip->spi->CR1 = 0; + spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM | + SPI_CR1_SSI; + spip->spi->CR2 = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN; + spip->spi->CR1 |= SPI_CR1_SPE; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + /* If in ready state then disables the SPI clock.*/ + if (spip->state == SPI_READY) { + + /* SPI disable.*/ + spip->spi->CR1 = 0; + dmaStreamRelease(spip->dmarx); + dmaStreamRelease(spip->dmatx); + +#if STM32_SPI_USE_SPI1 + if (&SPID1 == spip) + rccDisableSPI1(FALSE); +#endif +#if STM32_SPI_USE_SPI2 + if (&SPID2 == spip) + rccDisableSPI2(FALSE); +#endif +#if STM32_SPI_USE_SPI3 + if (&SPID3 == spip) + rccDisableSPI3(FALSE); +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This asynchronous function starts the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @post At the end of the operation the configured callback is invoked. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + dmaStreamSetMemory0(spip->dmarx, &dummyrx); + dmaStreamSetTransactionSize(spip->dmarx, n); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode); + + dmaStreamSetMemory0(spip->dmatx, &dummytx); + dmaStreamSetTransactionSize(spip->dmatx, n); + dmaStreamSetMode(spip->dmatx, spip->txdmamode); + + dmaStreamEnable(spip->dmarx); + dmaStreamEnable(spip->dmatx); +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + dmaStreamSetMemory0(spip->dmarx, rxbuf); + dmaStreamSetTransactionSize(spip->dmarx, n); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC); + + dmaStreamSetMemory0(spip->dmatx, txbuf); + dmaStreamSetTransactionSize(spip->dmatx, n); + dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC); + + dmaStreamEnable(spip->dmarx); + dmaStreamEnable(spip->dmatx); +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + dmaStreamSetMemory0(spip->dmarx, &dummyrx); + dmaStreamSetTransactionSize(spip->dmarx, n); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode); + + dmaStreamSetMemory0(spip->dmatx, txbuf); + dmaStreamSetTransactionSize(spip->dmatx, n); + dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC); + + dmaStreamEnable(spip->dmarx); + dmaStreamEnable(spip->dmatx); +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + dmaStreamSetMemory0(spip->dmarx, rxbuf); + dmaStreamSetTransactionSize(spip->dmarx, n); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC); + + dmaStreamSetMemory0(spip->dmatx, &dummytx); + dmaStreamSetTransactionSize(spip->dmatx, n); + dmaStreamSetMode(spip->dmatx, spip->txdmamode); + + dmaStreamEnable(spip->dmarx); + dmaStreamEnable(spip->dmatx); +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + spip->spi->DR = frame; + while ((spip->spi->SR & SPI_SR_RXNE) == 0) + ; + return spip->spi->DR; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/spi_lld.h b/Project/os/hal/platforms/STM32/spi_lld.h new file mode 100644 index 0000000..a88bd7e --- /dev/null +++ b/Project/os/hal/platforms/STM32/spi_lld.h @@ -0,0 +1,392 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/spi_lld.h + * @brief STM32 SPI subsystem low level driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for SPI1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__) +#define STM32_SPI_USE_SPI1 TRUE +#endif + +/** + * @brief SPI2 driver enable switch. + * @details If set to @p TRUE the support for SPI2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__) +#define STM32_SPI_USE_SPI2 TRUE +#endif + +/** + * @brief SPI3 driver enable switch. + * @details If set to @p TRUE the support for SPI3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__) +#define STM32_SPI_USE_SPI3 FALSE +#endif + +/** + * @brief SPI1 interrupt priority level setting. + */ +#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#endif + +/** + * @brief SPI2 interrupt priority level setting. + */ +#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#endif + +/** + * @brief SPI3 interrupt priority level setting. + */ +#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#endif + +/** + * @brief SPI1 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA streams but + * because of the streams ordering the RX stream has always priority + * over the TX stream. + */ +#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#endif + +/** + * @brief SPI2 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA streams but + * because of the streams ordering the RX stream has always priority + * over the TX stream. + */ +#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#endif + +/** + * @brief SPI3 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA streams but + * because of the streams ordering the RX stream has always priority + * over the TX stream. + */ +#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#endif + +/** + * @brief SPI DMA error hook. + */ +#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() +#endif + +#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) + +/** + * @brief DMA stream used for SPI1 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI1_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#endif + +/** + * @brief DMA stream used for SPI1 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI1_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#endif + +/** + * @brief DMA stream used for SPI2 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI2_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#endif + +/** + * @brief DMA stream used for SPI2 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI2_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#endif + +/** + * @brief DMA stream used for SPI3 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI3_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#endif + +/** + * @brief DMA stream used for SPI3 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI3_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#endif + +#else /* !STM32_ADVANCED_DMA */ + +/* Fixed streams for platforms using the old DMA peripheral, the values are + valid for both STM32F1xx and STM32L1xx.*/ +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) + +#endif /* !STM32_ADVANCED_DMA*/ +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1 +#error "SPI1 not present in the selected device" +#endif + +#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2 +#error "SPI2 not present in the selected device" +#endif + +#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3 +#error "SPI3 not present in the selected device" +#endif + +#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3 +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +#if STM32_SPI_USE_SPI1 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK) +#error "invalid DMA stream associated to SPI1 RX" +#endif + +#if STM32_SPI_USE_SPI1 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK) +#error "invalid DMA stream associated to SPI1 TX" +#endif + +#if STM32_SPI_USE_SPI2 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK) +#error "invalid DMA stream associated to SPI2 RX" +#endif + +#if STM32_SPI_USE_SPI2 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK) +#error "invalid DMA stream associated to SPI2 TX" +#endif + +#if STM32_SPI_USE_SPI3 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK) +#error "invalid DMA stream associated to SPI3 RX" +#endif + +#if STM32_SPI_USE_SPI3 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK) +#error "invalid DMA stream associated to SPI3 TX" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief SPI initialization data. + */ + uint16_t cr1; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver{ + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SPIx registers block. + */ + SPI_TypeDef *spi; + /** + * @brief Receive DMA stream. + */ + const stm32_dma_stream_t *dmarx; + /** + * @brief Transmit DMA stream. + */ + const stm32_dma_stream_t *dmatx; + /** + * @brief RX DMA mode bit mask. + */ + uint32_t rxdmamode; + /** + * @brief TX DMA mode bit mask. + */ + uint32_t txdmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__) +extern SPIDriver SPID2; +#endif + +#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__) +extern SPIDriver SPID3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/stm32.h b/Project/os/hal/platforms/STM32/stm32.h new file mode 100644 index 0000000..eaa8ba8 --- /dev/null +++ b/Project/os/hal/platforms/STM32/stm32.h @@ -0,0 +1,180 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/stm32.h + * @brief STM32 common header. + * @pre One of the following macros must be defined before including + * this header, the macro selects the inclusion of the appropriate + * vendor header: + * - STM32F10X_LD_VL for Value Line Low Density devices. + * - STM32F10X_MD_VL for Value Line Medium Density devices. + * - STM32F10X_LD for Performance Low Density devices. + * - STM32F10X_MD for Performance Medium Density devices. + * - STM32F10X_HD for Performance High Density devices. + * - STM32F10X_XL for Performance eXtra Density devices. + * - STM32F10X_CL for Connectivity Line devices. + * - STM32F2XX for High-performance STM32 F-2 devices. + * - STM32F4XX for High-performance STM32 F-4 devices. + * - STM32L1XX_MD for Ultra Low Power Medium-density devices. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _STM32_H_ +#define _STM32_H_ + +#if defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD_VL) || defined(STM32F10X_LD) || \ + defined(STM32F10X_MD) || defined(STM32F10X_HD) || \ + defined(STM32F10X_XL) || defined(STM32F10X_CL) || \ + defined(__DOXYGEN__) +#include "stm32f10x.h" + +/* Resolving naming anomalies related to the STM32F1xx sub-family.*/ +#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn +#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn +#if defined(STM32F10X_XL) +#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn +#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn +#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD_VL) +#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn +#endif + +#elif defined(STM32F2XX) +#include "stm32f2xx.h" + +/* Resolving naming anomalies related to the STM32F2xx sub-family.*/ +#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn +#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn + +#elif defined(STM32F4XX) +#include "stm32f4xx.h" + +/* Resolving naming anomalies related to the STM32F4xx sub-family.*/ +#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn +#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn + +#elif defined(STM32L1XX_MD) +#include "stm32l1xx.h" + +#else +#error "STM32 device not specified" +#endif + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 TIM registers block. + * @note Redefined from the ST headers because the non uniform + * declaration of the CCR registers among the various + * sub-families. + */ +typedef struct { + volatile uint16_t CR1; + uint16_t _resvd0; + volatile uint16_t CR2; + uint16_t _resvd1; + volatile uint16_t SMCR; + uint16_t _resvd2; + volatile uint16_t DIER; + uint16_t _resvd3; + volatile uint16_t SR; + uint16_t _resvd4; + volatile uint16_t EGR; + uint16_t _resvd5; + volatile uint16_t CCMR1; + uint16_t _resvd6; + volatile uint16_t CCMR2; + uint16_t _resvd7; + volatile uint16_t CCER; + uint16_t _resvd8; + volatile uint32_t CNT; + volatile uint16_t PSC; + uint16_t _resvd9; + volatile uint32_t ARR; + volatile uint16_t RCR; + uint16_t _resvd10; + volatile uint32_t CCR[4]; + volatile uint16_t BDTR; + uint16_t _resvd11; + volatile uint16_t DCR; + uint16_t _resvd12; + volatile uint16_t DMAR; + uint16_t _resvd13; + volatile uint16_t OR; + uint16_t _resvd14; +} stm32_tim_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name TIM units references + * @{ + */ +#define STM32_TIM1 ((stm32_tim_t *)TIM1_BASE) +#define STM32_TIM2 ((stm32_tim_t *)TIM2_BASE) +#define STM32_TIM3 ((stm32_tim_t *)TIM3_BASE) +#define STM32_TIM4 ((stm32_tim_t *)TIM4_BASE) +#define STM32_TIM5 ((stm32_tim_t *)TIM5_BASE) +#define STM32_TIM6 ((stm32_tim_t *)TIM6_BASE) +#define STM32_TIM7 ((stm32_tim_t *)TIM7_BASE) +#define STM32_TIM8 ((stm32_tim_t *)TIM8_BASE) +#define STM32_TIM9 ((stm32_tim_t *)TIM9_BASE) +#define STM32_TIM10 ((stm32_tim_t *)TIM10_BASE) +#define STM32_TIM11 ((stm32_tim_t *)TIM11_BASE) +#define STM32_TIM12 ((stm32_tim_t *)TIM12_BASE) +#define STM32_TIM13 ((stm32_tim_t *)TIM13_BASE) +#define STM32_TIM14 ((stm32_tim_t *)TIM14_BASE) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#endif /* _STM32_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/uart_lld.c b/Project/os/hal/platforms/STM32/uart_lld.c new file mode 100644 index 0000000..de53db6 --- /dev/null +++ b/Project/os/hal/platforms/STM32/uart_lld.c @@ -0,0 +1,591 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/uart_lld.c + * @brief STM32 low level UART driver code. + * + * @addtogroup UART + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define USART1_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART1_RX_DMA_STREAM, \ + STM32_USART1_RX_DMA_CHN) + +#define USART1_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART1_TX_DMA_STREAM, \ + STM32_USART1_TX_DMA_CHN) + +#define USART2_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART2_RX_DMA_STREAM, \ + STM32_USART2_RX_DMA_CHN) + +#define USART2_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART2_TX_DMA_STREAM, \ + STM32_USART2_TX_DMA_CHN) + +#define USART3_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART3_RX_DMA_STREAM, \ + STM32_USART3_RX_DMA_CHN) + +#define USART3_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM, \ + STM32_USART3_TX_DMA_CHN) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief USART1 UART driver identifier.*/ +#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) +UARTDriver UARTD1; +#endif + +/** @brief USART2 UART driver identifier.*/ +#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) +UARTDriver UARTD2; +#endif + +/** @brief USART3 UART driver identifier.*/ +#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) +UARTDriver UARTD3; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Status bits translation. + * + * @param[in] sr USART SR register value + * + * @return The error flags. + */ +static uartflags_t translate_errors(uint16_t sr) { + uartflags_t sts = 0; + + if (sr & USART_SR_ORE) + sts |= UART_OVERRUN_ERROR; + if (sr & USART_SR_PE) + sts |= UART_PARITY_ERROR; + if (sr & USART_SR_FE) + sts |= UART_FRAMING_ERROR; + if (sr & USART_SR_NE) + sts |= UART_NOISE_ERROR; + if (sr & USART_SR_LBD) + sts |= UART_BREAK_DETECTED; + return sts; +} + +/** + * @brief Puts the receiver in the UART_RX_IDLE state. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void set_rx_idle_loop(UARTDriver *uartp) { + uint32_t mode; + + /* RX DMA channel preparation, if the char callback is defined then the + TCIE interrupt is enabled too.*/ + if (uartp->config->rxchar_cb == NULL) + mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC; + else + mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE; + dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf); + dmaStreamSetTransactionSize(uartp->dmarx, 1); + dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode); + dmaStreamEnable(uartp->dmarx); +} + +/** + * @brief USART de-initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void usart_stop(UARTDriver *uartp) { + + /* Stops RX and TX DMA channels.*/ + dmaStreamDisable(uartp->dmarx); + dmaStreamDisable(uartp->dmatx); + + /* Stops USART operations.*/ + uartp->usart->CR1 = 0; + uartp->usart->CR2 = 0; + uartp->usart->CR3 = 0; +} + +/** + * @brief USART initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void usart_start(UARTDriver *uartp) { + uint16_t cr1; + USART_TypeDef *u = uartp->usart; + + /* Defensive programming, starting from a clean state.*/ + usart_stop(uartp); + + /* Baud rate setting.*/ + if (uartp->usart == USART1) + u->BRR = STM32_PCLK2 / uartp->config->speed; + else + u->BRR = STM32_PCLK1 / uartp->config->speed; + + /* Resetting eventual pending status flags.*/ + (void)u->SR; /* SR reset step 1.*/ + (void)u->DR; /* SR reset step 2.*/ + u->SR = 0; + + /* Note that some bits are enforced because required for correct driver + operations.*/ + if (uartp->config->txend2_cb == NULL) + cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE; + else + cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE | + USART_CR1_TCIE; + u->CR1 = uartp->config->cr1 | cr1; + u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE; + u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR | + USART_CR3_EIE; + + /* Starting the receiver idle loop.*/ + set_rx_idle_loop(uartp); +} + +/** + * @brief RX DMA common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_UART_DMA_ERROR_HOOK) + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_UART_DMA_ERROR_HOOK(uartp); + } +#else + (void)flags; +#endif + + if (uartp->rxstate == UART_RX_IDLE) { + /* Receiver in idle state, a callback is generated, if enabled, for each + received character and then the driver stays in the same state.*/ + if (uartp->config->rxchar_cb != NULL) + uartp->config->rxchar_cb(uartp, uartp->rxbuf); + } + else { + /* Receiver in active state, a callback is generated, if enabled, after + a completed transfer.*/ + dmaStreamDisable(uartp->dmarx); + uartp->rxstate = UART_RX_COMPLETE; + if (uartp->config->rxend_cb != NULL) + uartp->config->rxend_cb(uartp); + + /* If the callback didn't explicitly change state then the receiver + automatically returns to the idle state.*/ + if (uartp->rxstate == UART_RX_COMPLETE) { + uartp->rxstate = UART_RX_IDLE; + set_rx_idle_loop(uartp); + } + } +} + +/** + * @brief TX DMA common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_UART_DMA_ERROR_HOOK) + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_UART_DMA_ERROR_HOOK(uartp); + } +#else + (void)flags; +#endif + + dmaStreamDisable(uartp->dmatx); + + /* A callback is generated, if enabled, after a completed transfer.*/ + uartp->txstate = UART_TX_COMPLETE; + if (uartp->config->txend1_cb != NULL) + uartp->config->txend1_cb(uartp); + + /* If the callback didn't explicitly change state then the transmitter + automatically returns to the idle state.*/ + if (uartp->txstate == UART_TX_COMPLETE) + uartp->txstate = UART_TX_IDLE; +} + +/** + * @brief USART common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void serve_usart_irq(UARTDriver *uartp) { + uint16_t sr; + USART_TypeDef *u = uartp->usart; + + sr = u->SR; /* SR reset step 1.*/ + (void)u->DR; /* SR reset step 2.*/ + if (sr & (USART_SR_LBD | USART_SR_ORE | USART_SR_NE | + USART_SR_FE | USART_SR_PE)) { + u->SR = ~USART_SR_LBD; + if (uartp->config->rxerr_cb != NULL) + uartp->config->rxerr_cb(uartp, translate_errors(sr)); + } + if (sr & USART_SR_TC) { + u->SR = ~USART_SR_TC; + + /* End of transmission, a callback is generated.*/ + if (uartp->config->txend2_cb != NULL) + uartp->config->txend2_cb(uartp); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) +/** + * @brief USART1 IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART1_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + serve_usart_irq(&UARTD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_UART_USE_USART1 */ + +#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) +/** + * @brief USART2 IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART2_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + serve_usart_irq(&UARTD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_UART_USE_USART2 */ + +#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) +/** + * @brief USART3 IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART3_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + serve_usart_irq(&UARTD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_UART_USE_USART3 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level UART driver initialization. + * + * @notapi + */ +void uart_lld_init(void) { + +#if STM32_UART_USE_USART1 + uartObjectInit(&UARTD1); + UARTD1.usart = USART1; + UARTD1.dmarx = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM); + UARTD1.dmatx = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM); +#endif + +#if STM32_UART_USE_USART2 + uartObjectInit(&UARTD2); + UARTD2.usart = USART2; + UARTD2.dmarx = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM); + UARTD2.dmatx = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM); +#endif + +#if STM32_UART_USE_USART3 + uartObjectInit(&UARTD3); + UARTD3.usart = USART3; + UARTD3.dmarx = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM); + UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM); +#endif +} + +/** + * @brief Configures and activates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_start(UARTDriver *uartp) { + + uartp->dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + + if (uartp->state == UART_STOP) { +#if STM32_UART_USE_USART1 + if (&UARTD1 == uartp) { + bool_t b; + b = dmaStreamAllocate(uartp->dmarx, + STM32_UART_USART1_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated"); + b = dmaStreamAllocate(uartp->dmatx, + STM32_UART_USART1_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated"); + rccEnableUSART1(FALSE); + nvicEnableVector(USART1_IRQn, + CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY)); + uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); + } +#endif + +#if STM32_UART_USE_USART2 + if (&UARTD2 == uartp) { + bool_t b; + b = dmaStreamAllocate(uartp->dmarx, + STM32_UART_USART2_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated"); + b = dmaStreamAllocate(uartp->dmatx, + STM32_UART_USART2_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated"); + rccEnableUSART2(FALSE); + nvicEnableVector(USART2_IRQn, + CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY)); + uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); + } +#endif + +#if STM32_UART_USE_USART3 + if (&UARTD3 == uartp) { + bool_t b; + b = dmaStreamAllocate(uartp->dmarx, + STM32_UART_USART3_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated"); + b = dmaStreamAllocate(uartp->dmatx, + STM32_UART_USART3_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated"); + rccEnableUSART3(FALSE); + nvicEnableVector(USART3_IRQn, + CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY)); + uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); + } +#endif + + /* Static DMA setup, the transfer size depends on the USART settings, + it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/ + if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) + uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->DR); + dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->DR); + uartp->rxbuf = 0; + } + + uartp->rxstate = UART_RX_IDLE; + uartp->txstate = UART_TX_IDLE; + usart_start(uartp); +} + +/** + * @brief Deactivates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_stop(UARTDriver *uartp) { + + if (uartp->state == UART_READY) { + usart_stop(uartp); + dmaStreamRelease(uartp->dmarx); + dmaStreamRelease(uartp->dmatx); + +#if STM32_UART_USE_USART1 + if (&UARTD1 == uartp) { + nvicDisableVector(USART1_IRQn); + rccDisableUSART1(FALSE); + return; + } +#endif + +#if STM32_UART_USE_USART2 + if (&UARTD2 == uartp) { + nvicDisableVector(USART2_IRQn); + rccDisableUSART2(FALSE); + return; + } +#endif + +#if STM32_UART_USE_USART3 + if (&UARTD3 == uartp) { + nvicDisableVector(USART3_IRQn); + rccDisableUSART3(FALSE); + return; + } +#endif + } +} + +/** + * @brief Starts a transmission on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { + + /* TX DMA channel preparation and start.*/ + dmaStreamSetMemory0(uartp->dmatx, txbuf); + dmaStreamSetTransactionSize(uartp->dmatx, n); + dmaStreamSetMode(uartp->dmatx, uartp->dmamode | STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE); + dmaStreamEnable(uartp->dmatx); +} + +/** + * @brief Stops any ongoing transmission. + * @note Stopping a transmission also suppresses the transmission callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not transmitted by the + * stopped transmit operation. + * + * @notapi + */ +size_t uart_lld_stop_send(UARTDriver *uartp) { + + dmaStreamDisable(uartp->dmatx); + return dmaStreamGetTransactionSize(uartp->dmatx); +} + +/** + * @brief Starts a receive operation on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { + + /* Stopping previous activity (idle state).*/ + dmaStreamDisable(uartp->dmarx); + + /* RX DMA channel preparation and start.*/ + dmaStreamSetMemory0(uartp->dmarx, rxbuf); + dmaStreamSetTransactionSize(uartp->dmarx, n); + dmaStreamSetMode(uartp->dmarx, uartp->dmamode | STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE); + dmaStreamEnable(uartp->dmarx); +} + +/** + * @brief Stops any ongoing receive operation. + * @note Stopping a receive operation also suppresses the receive callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not received by the + * stopped receive operation. + * + * @notapi + */ +size_t uart_lld_stop_receive(UARTDriver *uartp) { + size_t n; + + dmaStreamDisable(uartp->dmarx); + n = dmaStreamGetTransactionSize(uartp->dmarx); + set_rx_idle_loop(uartp); + return n; +} + +#endif /* HAL_USE_UART */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32/uart_lld.h b/Project/os/hal/platforms/STM32/uart_lld.h new file mode 100644 index 0000000..972fa49 --- /dev/null +++ b/Project/os/hal/platforms/STM32/uart_lld.h @@ -0,0 +1,430 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32/uart_lld.h + * @brief STM32 low level UART driver header. + * + * @addtogroup UART + * @{ + */ + +#ifndef _UART_LLD_H_ +#define _UART_LLD_H_ + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief UART driver on USART1 enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__) +#define STM32_UART_USE_USART1 TRUE +#endif + +/** + * @brief UART driver on USART2 enable switch. + * @details If set to @p TRUE the support for USART2 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__) +#define STM32_UART_USE_USART2 TRUE +#endif + +/** + * @brief UART driver on USART3 enable switch. + * @details If set to @p TRUE the support for USART3 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__) +#define STM32_UART_USE_USART3 TRUE +#endif + +/** + * @brief USART1 interrupt priority level setting. + */ +#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#endif + +/** + * @brief USART2 interrupt priority level setting. + */ +#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#endif + +/** + * @brief USART3 interrupt priority level setting. + */ +#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#endif + +/** + * @brief USART1 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART1_DMA_PRIORITY 0 +#endif + +/** + * @brief USART2 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART2_DMA_PRIORITY 0 +#endif + +/** + * @brief USART3 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART3_DMA_PRIORITY 0 +#endif + +/** + * @brief USART1 DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() +#endif + +#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) + +/** + * @brief DMA stream used for USART1 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART1_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#endif + +/** + * @brief DMA stream used for USART1 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART1_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#endif + +/** + * @brief DMA stream used for USART2 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART2_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#endif + +/** + * @brief DMA stream used for USART2 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART2_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#endif + +/** + * @brief DMA stream used for USART3 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART3_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#endif + +/** + * @brief DMA stream used for USART3 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART3_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#endif + +#else /* !STM32_ADVANCED_DMA */ + +/* Fixed streams for platforms using the old DMA peripheral, the values are + valid for both STM32F1xx and STM32L1xx.*/ +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) + +#endif /* !STM32_ADVANCED_DMA*/ +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_UART_USE_USART1 && !STM32_HAS_USART1 +#error "USART1 not present in the selected device" +#endif + +#if STM32_UART_USE_USART2 && !STM32_HAS_USART2 +#error "USART2 not present in the selected device" +#endif + +#if STM32_UART_USE_USART3 && !STM32_HAS_USART3 +#error "USART3 not present in the selected device" +#endif + +#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 && \ + !STM32_UART_USE_USART3 +#error "UART driver activated but no USART/UART peripheral assigned" +#endif + +#if STM32_UART_USE_USART1 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM, \ + STM32_USART1_RX_DMA_MSK) +#error "invalid DMA stream associated to USART1 RX" +#endif + +#if STM32_UART_USE_USART1 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_TX_DMA_STREAM, \ + STM32_USART1_TX_DMA_MSK) +#error "invalid DMA stream associated to USART1 TX" +#endif + +#if STM32_UART_USE_USART2 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_RX_DMA_STREAM, \ + STM32_USART2_RX_DMA_MSK) +#error "invalid DMA stream associated to USART2 RX" +#endif + +#if STM32_UART_USE_USART2 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_TX_DMA_STREAM, \ + STM32_USART2_TX_DMA_MSK) +#error "invalid DMA stream associated to USART2 TX" +#endif + +#if STM32_UART_USE_USART3 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_RX_DMA_STREAM, \ + STM32_USART3_RX_DMA_MSK) +#error "invalid DMA stream associated to USART3 RX" +#endif + +#if STM32_UART_USE_USART3 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_TX_DMA_STREAM, \ + STM32_USART3_TX_DMA_MSK) +#error "invalid DMA stream associated to USART3 TX" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief UART driver condition flags type. + */ +typedef uint32_t uartflags_t; + +/** + * @brief Structure representing an UART driver. + */ +typedef struct UARTDriver UARTDriver; + +/** + * @brief Generic UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +typedef void (*uartcb_t)(UARTDriver *uartp); + +/** + * @brief Character received UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] c received character + */ +typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); + +/** + * @brief Receive error UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] e receive error mask + */ +typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief End of transmission buffer callback. + */ + uartcb_t txend1_cb; + /** + * @brief Physical end of transmission callback. + */ + uartcb_t txend2_cb; + /** + * @brief Receive buffer filled callback. + */ + uartcb_t rxend_cb; + /** + * @brief Character received while out if the @p UART_RECEIVE state. + */ + uartccb_t rxchar_cb; + /** + * @brief Receive error callback. + */ + uartecb_t rxerr_cb; + /* End of the mandatory fields.*/ + /** + * @brief Bit rate. + */ + uint32_t speed; + /** + * @brief Initialization value for the CR1 register. + */ + uint16_t cr1; + /** + * @brief Initialization value for the CR2 register. + */ + uint16_t cr2; + /** + * @brief Initialization value for the CR3 register. + */ + uint16_t cr3; +} UARTConfig; + +/** + * @brief Structure representing an UART driver. + */ +struct UARTDriver { + /** + * @brief Driver state. + */ + uartstate_t state; + /** + * @brief Transmitter state. + */ + uarttxstate_t txstate; + /** + * @brief Receiver state. + */ + uartrxstate_t rxstate; + /** + * @brief Current configuration data. + */ + const UARTConfig *config; +#if defined(UART_DRIVER_EXT_FIELDS) + UART_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the USART registers block. + */ + USART_TypeDef *usart; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; + /** + * @brief Receive DMA channel. + */ + const stm32_dma_stream_t *dmarx; + /** + * @brief Transmit DMA channel. + */ + const stm32_dma_stream_t *dmatx; + /** + * @brief Default receive buffer while into @p UART_RX_IDLE state. + */ + volatile uint16_t rxbuf; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__) +extern UARTDriver UARTD1; +#endif + +#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__) +extern UARTDriver UARTD2; +#endif + +#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__) +extern UARTDriver UARTD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void uart_lld_init(void); + void uart_lld_start(UARTDriver *uartp); + void uart_lld_stop(UARTDriver *uartp); + void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf); + size_t uart_lld_stop_send(UARTDriver *uartp); + void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf); + size_t uart_lld_stop_receive(UARTDriver *uartp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_UART */ + +#endif /* _UART_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F1xx/adc_lld.c b/Project/os/hal/platforms/STM32F1xx/adc_lld.c new file mode 100644 index 0000000..8785688 --- /dev/null +++ b/Project/os/hal/platforms/STM32F1xx/adc_lld.c @@ -0,0 +1,239 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F1xx/adc_lld.c + * @brief STM32F1xx ADC subsystem low level driver source. + * + * @addtogroup ADC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ADC1 driver identifier.*/ +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +ADCDriver ADCD1; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared ADC DMA ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { + + /* DMA errors handling.*/ + if ((flags & STM32_DMA_ISR_TEIF) != 0) { + /* DMA, this could help only if the DMA tries to access an unmapped + address space or violates alignment rules.*/ + _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); + } + else { + if ((flags & STM32_DMA_ISR_HTIF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + if ((flags & STM32_DMA_ISR_TCIF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +#if STM32_ADC_USE_ADC1 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); + ADCD1.adc = ADC1; + ADCD1.dmastp = STM32_DMA1_STREAM1; + ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_TEIE; + + /* Temporary activation.*/ + rccEnableADC1(FALSE); + ADC1->CR1 = 0; + ADC1->CR2 = ADC_CR2_ADON; + + /* Reset calibration just to be safe.*/ + ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL; + while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0) + ; + + /* Calibration.*/ + ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL; + while ((ADC1->CR2 & ADC_CR2_CAL) != 0) + ; + + /* Return the ADC in low power mode.*/ + ADC1->CR2 = 0; + rccDisableADC1(FALSE); +#endif +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + /* If in stopped state then enables the ADC and DMA clocks.*/ + if (adcp->state == ADC_STOP) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC1_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); + rccEnableADC1(FALSE); + } +#endif + + /* ADC setup, the calibration procedure has already been performed + during initialization.*/ + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + } +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + /* If in ready state then disables the ADC clock.*/ + if (adcp->state == ADC_READY) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + ADC1->CR1 = 0; + ADC1->CR2 = 0; + dmaStreamRelease(adcp->dmastp); + rccDisableADC1(FALSE); + } +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + uint32_t mode, n; + const ADCConversionGroup *grpp = adcp->grpp; + + /* DMA setup.*/ + mode = adcp->dmamode; + if (grpp->circular) + mode |= STM32_DMA_CR_CIRC; + if (adcp->depth > 1) { + /* If the buffer depth is greater than one then the half transfer interrupt + interrupt is enabled in order to allows streaming processing.*/ + mode |= STM32_DMA_CR_HTIE; + n = (uint32_t)grpp->num_channels * (uint32_t)adcp->depth; + } + else + n = (uint32_t)grpp->num_channels; + dmaStreamSetMemory0(adcp->dmastp, adcp->samples); + dmaStreamSetTransactionSize(adcp->dmastp, n); + dmaStreamSetMode(adcp->dmastp, mode); + dmaStreamEnable(adcp->dmastp); + + /* ADC setup.*/ + adcp->adc->CR1 = grpp->cr1 | ADC_CR1_SCAN; + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON; + adcp->adc->SMPR1 = grpp->smpr1; + adcp->adc->SMPR2 = grpp->smpr2; + adcp->adc->SQR1 = grpp->sqr1; + adcp->adc->SQR2 = grpp->sqr2; + adcp->adc->SQR3 = grpp->sqr3; + + /* ADC start by writing ADC_CR2_ADON a second time.*/ + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON; +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + dmaStreamDisable(adcp->dmastp); + adcp->adc->CR2 = 0; +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F1xx/adc_lld.h b/Project/os/hal/platforms/STM32F1xx/adc_lld.h new file mode 100644 index 0000000..894c7e6 --- /dev/null +++ b/Project/os/hal/platforms/STM32F1xx/adc_lld.h @@ -0,0 +1,404 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F1xx/adc_lld.h + * @brief STM32F1xx ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Triggers selection + * @{ + */ +#define ADC_CR2_EXTSEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */ +#define ADC_CR2_EXTSEL_SWSTART (7 << 17) /**< @brief Software trigger. */ +/** @} */ + +/** + * @name Available analog channels + * @{ + */ +#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ +#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ +#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ +#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ +#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ +#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ +#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ +#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ +#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ +#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ +#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ +#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ +#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ +#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ +#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ +#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ +#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ +#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */ +/** @} */ + +/** + * @name Sampling rates + * @{ + */ +#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */ +#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */ +#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */ +#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */ +#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */ +#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */ +#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */ +#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC1 TRUE +#endif + +/** + * @brief ADC1 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC1 interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 +#error "ADC1 not present in the selected device" +#endif + +#if !STM32_ADC_USE_ADC1 +#error "ADC driver activated but no ADC peripheral assigned" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_DMAFAILURE = 0 /**< DMA operations failure. */ +} adcerror_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief ADC error callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] err ADC error code + */ +typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note The use of this configuration structure requires knowledge of + * STM32 ADC cell registers interface, please refer to the STM32 + * reference manual for details. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool_t circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /** + * @brief Error callback or @p NULL. + */ + adcerrorcallback_t error_cb; + /* End of the mandatory fields.*/ + /** + * @brief ADC CR1 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR1_SCAN that is enforced inside the driver. + */ + uint32_t cr1; + /** + * @brief ADC CR2 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are + * enforced inside the driver. + */ + uint32_t cr2; + /** + * @brief ADC SMPR1 register initialization data. + * @details In this field must be specified the sample times for channels + * 10...17. + */ + uint32_t smpr1; + /** + * @brief ADC SMPR2 register initialization data. + * @details In this field must be specified the sample times for channels + * 0...9. + */ + uint32_t smpr2; + /** + * @brief ADC SQR1 register initialization data. + * @details Conversion group sequence 13...16 + sequence length. + */ + uint32_t sqr1; + /** + * @brief ADC SQR2 register initialization data. + * @details Conversion group sequence 7...12. + */ + uint32_t sqr2; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 1...6. + */ + uint32_t sqr3; +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the ADCx registers block. + */ + ADC_TypeDef *adc; + /** + * @brief Pointer to associated SMA channel. + */ + const stm32_dma_stream_t *dmastp; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Sequences building helper macros + * @{ + */ +/** + * @brief Number of channels in a conversion sequence. + */ +#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) + +#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ +#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ +#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ +#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ +#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ +#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ + +#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ +#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ +#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ +#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ +#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ +#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ + +#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ +#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ +#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ +#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ +/** @} */ + +/** + * @name Sampling rate settings helper macros + * @{ + */ +#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ +#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ + +#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ +#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor + sampling time. */ +#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference + sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F1xx/hal_lld.c b/Project/os/hal/platforms/STM32F1xx/hal_lld.c new file mode 100644 index 0000000..f14f2b9 --- /dev/null +++ b/Project/os/hal/platforms/STM32F1xx/hal_lld.c @@ -0,0 +1,288 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F1xx/hal_lld.c + * @brief STM32F1xx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the backup domain. + * @note WARNING! Changing clock source impossible without resetting + * of the whole BKP domain. + */ +static void hal_lld_backup_domain_init(void) { + + /* Backup domain access enabled and left open.*/ + PWR->CR |= PWR_CR_DBP; + + /* Reset BKP domain if different clock source selected.*/ + if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){ + /* Backup domain reset.*/ + RCC->BDCR = RCC_BDCR_BDRST; + RCC->BDCR = 0; + } + + /* If enabled then the LSE is started.*/ +#if STM32_LSE_ENABLED + RCC->BDCR |= RCC_BDCR_LSEON; + while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ +#endif + +#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK + /* If the backup domain hasn't been initialized yet then proceed with + initialization.*/ + if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { + /* Selects clock source.*/ + RCC->BDCR |= STM32_RTCSEL; + + /* RTC clock enabled.*/ + RCC->BDCR |= RCC_BDCR_RTCEN; + } +#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */ +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* Reset of all peripherals.*/ + rccResetAPB1(0xFFFFFFFF); + rccResetAPB2(0xFFFFFFFF); + + /* SysTick initialization using the system clock.*/ + SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + + /* DWT cycle counter enable.*/ + SCS_DEMCR |= SCS_DEMCR_TRCENA; + DWT_CTRL |= DWT_CTRL_CYCCNTENA; + + /* PWR and BD clocks enabled.*/ + rccEnablePWRInterface(FALSE); + rccEnableBKPInterface(FALSE); + + /* Initializes the backup domain.*/ + hal_lld_backup_domain_init(); + +#if defined(STM32_DMA_REQUIRED) + dmaInit(); +#endif + + /* Programmable voltage detector enable.*/ +#if STM32_PVD_ENABLE + PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); +#endif /* STM32_PVD_ENABLE */ +} + +/** + * @brief STM32 clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +#if defined(STM32F10X_LD) || defined(STM32F10X_LD_VL) || \ + defined(STM32F10X_MD) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD) || defined(STM32F10X_XL) || \ + defined(__DOXYGEN__) +/* + * Clocks initialization for all sub-families except CL. + */ +void stm32_clock_init(void) { + +#if !STM32_NO_INIT + /* HSI setup, it enforces the reset situation in order to handle possible + problems with JTAG probes and re-initializations.*/ + RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ + while (!(RCC->CR & RCC_CR_HSIRDY)) + ; /* Wait until HSI is stable. */ + RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ + RCC->CFGR = 0; /* CFGR reset value. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) + ; /* Waits until HSI is selected. */ + +#if STM32_HSE_ENABLED + /* HSE activation.*/ + RCC->CR |= RCC_CR_HSEON; + while (!(RCC->CR & RCC_CR_HSERDY)) + ; /* Waits until HSE is stable. */ +#endif + +#if STM32_LSI_ENABLED + /* LSI activation.*/ + RCC->CSR |= RCC_CSR_LSION; + while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) + ; /* Waits until LSI is stable. */ +#endif + +#if STM32_ACTIVATE_PLL + /* PLL activation.*/ + RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC; + RCC->CR |= RCC_CR_PLLON; + while (!(RCC->CR & RCC_CR_PLLRDY)) + ; /* Waits until PLL is stable. */ +#endif + + /* Clock settings.*/ +#if STM32_HAS_USB + RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE | + STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | + STM32_HPRE; +#else + RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE | + STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | + STM32_HPRE; +#endif + + /* Flash setup and final clock selection. */ + FLASH->ACR = STM32_FLASHBITS; + + /* Switching to the configured clock source if it is different from HSI.*/ +#if (STM32_SW != STM32_SW_HSI) + /* Switches clock source.*/ + RCC->CFGR |= STM32_SW; + while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) + ; /* Waits selection complete. */ +#endif +#endif /* !STM32_NO_INIT */ +} + +#elif defined(STM32F10X_CL) +/* + * Clocks initialization for the CL sub-family. + */ +void stm32_clock_init(void) { + +#if !STM32_NO_INIT + /* HSI setup.*/ + RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ + while (!(RCC->CR & RCC_CR_HSIRDY)) + ; /* Wait until HSI is stable. */ + RCC->CFGR = 0; + RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) + ; /* Wait until HSI is the source.*/ + +#if STM32_HSE_ENABLED + /* HSE activation.*/ + RCC->CR |= RCC_CR_HSEON; + while (!(RCC->CR & RCC_CR_HSERDY)) + ; /* Waits until HSE is stable. */ +#endif + +#if STM32_LSI_ENABLED + /* LSI activation.*/ + RCC->CSR |= RCC_CSR_LSION; + while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) + ; /* Waits until LSI is stable. */ +#endif + + /* Settings of various dividers and multipliers in CFGR2.*/ + RCC->CFGR2 = STM32_PLL3MUL | STM32_PLL2MUL | STM32_PREDIV2 | + STM32_PREDIV1 | STM32_PREDIV1SRC; + + /* PLL2 setup, if activated.*/ +#if STM32_ACTIVATE_PLL2 + RCC->CR |= RCC_CR_PLL2ON; + while (!(RCC->CR & RCC_CR_PLL2RDY)) + ; /* Waits until PLL2 is stable. */ +#endif + + /* PLL3 setup, if activated.*/ +#if STM32_ACTIVATE_PLL3 + RCC->CR |= RCC_CR_PLL3ON; + while (!(RCC->CR & RCC_CR_PLL3RDY)) + ; /* Waits until PLL3 is stable. */ +#endif + + /* PLL1 setup, if activated.*/ +#if STM32_ACTIVATE_PLL1 + RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC; + RCC->CR |= RCC_CR_PLLON; + while (!(RCC->CR & RCC_CR_PLLRDY)) + ; /* Waits until PLL1 is stable. */ +#endif + + /* Clock settings.*/ +#if STM32_HAS_OTG1 + RCC->CFGR = STM32_MCOSEL | STM32_OTGFSPRE | STM32_PLLMUL | STM32_PLLSRC | + STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; +#else + RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLSRC | + STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; +#endif + + /* Flash setup and final clock selection. */ + FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */ + + /* Switching to the configured clock source if it is different from HSI.*/ +#if (STM32_SW != STM32_SW_HSI) + RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) + ; +#endif +#endif /* !STM32_NO_INIT */ +} +#else +void stm32_clock_init(void) {} +#endif + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F1xx/hal_lld.h b/Project/os/hal/platforms/STM32F1xx/hal_lld.h new file mode 100644 index 0000000..e348ce5 --- /dev/null +++ b/Project/os/hal/platforms/STM32F1xx/hal_lld.h @@ -0,0 +1,264 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F1xx/hal_lld.h + * @brief STM32F1xx HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - STM32_LSECLK. + * - STM32_HSECLK. + * . + * One of the following macros must also be defined: + * - STM32F10X_LD_VL for Value Line Low Density devices. + * - STM32F10X_MD_VL for Value Line Medium Density devices. + * - STM32F10X_LD for Performance Low Density devices. + * - STM32F10X_MD for Performance Medium Density devices. + * - STM32F10X_HD for Performance High Density devices. + * - STM32F10X_XL for Performance eXtra Density devices. + * - STM32F10X_CL for Connectivity Line devices. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "stm32.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS TRUE + +/** + * @name Internal clock sources + * @{ + */ +#define STM32_HSICLK 8000000 /**< High speed internal clock. */ +#define STM32_LSICLK 40000 /**< Low speed internal clock. */ +/** @} */ + +/** + * @name PWR_CR register bits definitions + * @{ + */ +#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */ +#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */ +#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */ +#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */ +#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */ +#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */ +#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */ +#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */ +/** @} */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name STM32F1xx capabilities + * @{ + */ +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS TRUE +#define STM32_RTC_IS_CALENDAR FALSE +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Disables the PWR/RCC initialization in the HAL. + */ +#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) +#define STM32_NO_INIT FALSE +#endif + +/** + * @brief Enables or disables the programmable voltage detector. + */ +#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__) +#define STM32_PVD_ENABLE FALSE +#endif + +/** + * @brief Sets voltage level for programmable voltage detector. + */ +#if !defined(STM32_PLS) || defined(__DOXYGEN__) +#define STM32_PLS STM32_PLS_LEV0 +#endif + +/** + * @brief Enables or disables the HSI clock source. + */ +#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSI_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the HSE clock source. + */ +#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSE_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSE clock source. + */ +#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSE_ENABLED FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if defined(__DOXYGEN__) +/** + * @name Platform identification + * @{ + */ +#define PLATFORM_NAME "STM32" +/** @} */ + +#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD_VL) || defined(__DOXYGEN__) +#include "hal_lld_f100.h" + +#elif defined(STM32F10X_LD) || defined(STM32F10X_MD) || \ + defined(STM32F10X_HD) || defined(STM32F10X_XL) || \ + defined(__DOXYGEN__) +#include "hal_lld_f103.h" + +#elif defined(STM32F10X_CL) || defined(__DOXYGEN__) +#include "hal_lld_f105_f107.h" + +#else +#error "unspecified, unsupported or invalid STM32 platform" +#endif + +/* There are differences in vector names in the various sub-families, + normalizing.*/ +#if defined(STM32F10X_XL) +#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn +#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn +#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn +#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn +#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn +#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn + +#elif defined(STM32F10X_LD_VL)|| defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD_VL) +#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn +#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn +#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing a system clock frequency. + */ +typedef uint32_t halclock_t; + +/** + * @brief Type of the realtime free counter value. + */ +typedef uint32_t halrtcnt_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the current value of the system free running counter. + * @note This service is implemented by returning the content of the + * DWT_CYCCNT register. + * + * @return The value of the system free running counter of + * type halrtcnt_t. + * + * @notapi + */ +#define hal_lld_get_counter_value() DWT_CYCCNT + +/** + * @brief Realtime counter frequency. + * @note The DWT_CYCCNT register is incremented directly by the system + * clock so this function returns STM32_HCLK. + * + * @return The realtime counter frequency of type halclock_t. + * + * @notapi + */ +#define hal_lld_get_counter_frequency() STM32_HCLK + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* STM32 DMA and RCC helpers.*/ +#include "stm32_dma.h" +#include "stm32_rcc.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void stm32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/Project/os/hal/platforms/STM32F1xx/hal_lld_f100.h new file mode 100644 index 0000000..c71c122 --- /dev/null +++ b/Project/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -0,0 +1,952 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup STM32F100_HAL STM32F100 HAL Support + * @details HAL support for STM32 Value Line LD, MD and HD sub-families. + * + * @ingroup HAL + */ + +/** + * @file STM32F1xx/hal_lld_f100.h + * @brief STM32F100 Value Line HAL subsystem low level driver header. + * + * @addtogroup STM32F100_HAL + * @{ + */ + +#ifndef _HAL_LLD_F100_H_ +#define _HAL_LLD_F100_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Platform identification + * @{ + */ +#if defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32F1 Value Line" + +#elif defined(STM32F10X_LD_VL) +#define PLATFORM_NAME "STM32F1 Value Line Low Density" + +#elif defined(STM32F10X_MD_VL) +#define PLATFORM_NAME "STM32F1 Value Line Medium Density" +#else +#error "unsupported STM32 Value Line member" +#endif +/** @} */ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Maximum system clock frequency. + */ +#define STM32_SYSCLK_MAX 24000000 + +/** + * @brief Maximum HSE clock frequency. + */ +#define STM32_HSECLK_MAX 24000000 + +/** + * @brief Minimum HSE clock frequency. + */ +#define STM32_HSECLK_MIN 1000000 + +/** + * @brief Maximum LSE clock frequency. + */ +#define STM32_LSECLK_MAX 1000000 + +/** + * @brief Minimum LSE clock frequency. + */ +#define STM32_LSECLK_MIN 32768 + +/** + * @brief Maximum PLLs input clock frequency. + */ +#define STM32_PLLIN_MAX 24000000 + +/** + * @brief Maximum PLLs input clock frequency. + */ +#define STM32_PLLIN_MIN 1000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define STM32_PLLOUT_MAX 24000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define STM32_PLLOUT_MIN 16000000 + +/** + * @brief Maximum APB1 clock frequency. + */ +#define STM32_PCLK1_MAX 24000000 + +/** + * @brief Maximum APB2 clock frequency. + */ +#define STM32_PCLK2_MAX 24000000 + +/** + * @brief Maximum ADC clock frequency. + */ +#define STM32_ADCCLK_MAX 12000000 +/** @} */ + +/** + * @name RCC_CFGR register bits definitions + * @{ + */ +#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ +#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ +#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ + +#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ +#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ +#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ +#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ +#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ +#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ +#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ +#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ +#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ + +#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */ +#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */ +#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */ +#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ +#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ + +#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ +#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ +#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ +#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ +#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ + +#define STM32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */ +#define STM32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */ +#define STM32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */ +#define STM32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */ + +#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ +#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */ + +#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */ +#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */ + +#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ +#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */ +#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */ +#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */ +#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ +/** @} */ + +/** + * @name RCC_BDCR register bits definitions + * @{ + */ +#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */ +#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */ +#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */ +#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */ +#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as + RTC clock. */ +/** @} */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +#if defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) +/** + * @name STM32F100 LD capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 0 + +/* DAC attributes.*/ +#define STM32_HAS_DAC TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 FALSE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 18 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE FALSE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C2 FALSE +#define STM32_I2C2_RX_DMA_MSK 0 +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK 0 +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C3 FALSE +#define STM32_SPI3_RX_DMA_MSK 0 +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK 0 +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI2 FALSE +#define STM32_SPI2_RX_DMA_MSK 0 +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK 0 +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 FALSE +#define STM32_SPI3_RX_DMA_MSK 0 +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK 0 +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 FALSE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 TRUE +#define STM32_HAS_TIM16 TRUE +#define STM32_HAS_TIM17 TRUE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART3 FALSE +#define STM32_USART3_RX_DMA_MSK 0 +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK 0 +#define STM32_USART3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART4 FALSE +#define STM32_UART4_RX_DMA_MSK 0 +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK 0 +#define STM32_UART4_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART5 FALSE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 + +/* USB attributes.*/ +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ +#endif /* defined(STM32F10X_LD_VL) */ + +#if defined(STM32F10X_MD_VL) || defined(__DOXYGEN__) +/** + * @name STM32F100 MD capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 0 + +/* DAC attributes.*/ +#define STM32_HAS_DAC TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 FALSE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 19 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C3 FALSE +#define STM32_I2C3_RX_DMA_MSK 0 +#define STM32_I2C3_RX_DMA_CHN 0x00000000 +#define STM32_I2C3_TX_DMA_MSK 0 +#define STM32_I2C3_TX_DMA_CHN 0x00000000 + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 FALSE +#define STM32_SPI3_RX_DMA_MSK 0 +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK 0 +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 TRUE +#define STM32_HAS_TIM16 TRUE +#define STM32_HAS_TIM17 TRUE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_USART3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART4 FALSE +#define STM32_UART4_RX_DMA_MSK 0 +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK 0 +#define STM32_UART4_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART5 FALSE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 + +/* USB attributes.*/ +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ +#endif /* defined(STM32F10X_MD_VL) */ + +/*===========================================================================*/ +/* Platform specific friendly IRQ names. */ +/*===========================================================================*/ + +/** + * @name IRQ VECTOR names + * @{ + */ +#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ +#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line + detect. */ +#define TAMPER_IRQHandler Vector48 /**< Tamper. */ +#define RTC_IRQHandler Vector4C /**< RTC. */ +#define FLASH_IRQHandler Vector50 /**< Flash. */ +#define RCC_IRQHandler Vector54 /**< RCC. */ +#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ +#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ +#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ +#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ +#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ +#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ +#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ +#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ +#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ +#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ +#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ +#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ +#define ADC1_2_IRQHandler Vector88 /**< ADC1_2. */ +#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ +#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ +#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ +#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and + Commutation. */ +#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ +#define TIM2_IRQHandler VectorB0 /**< TIM2. */ +#define TIM3_IRQHandler VectorB4 /**< TIM3. */ +#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) +#define TIM4_IRQHandler VectorB8 /**< TIM4. */ +#endif +#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ +#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ +#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) +#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ +#define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */ +#endif +#define SPI1_IRQHandler VectorCC /**< SPI1. */ +#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) +#define SPI2_IRQHandler VectorD0 /**< SPI2. */ +#endif +#define USART1_IRQHandler VectorD4 /**< USART1. */ +#define USART2_IRQHandler VectorD8 /**< USART2. */ +#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) +#define USART3_IRQHandler VectorDC /**< USART3. */ +#endif +#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ +#define RTC_Alarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ +#define CEC_IRQHandler VectorE8 /**< CEC. */ +#define TIM12_IRQHandler VectorEC /**< TIM12. */ +#define TIM13_IRQHandler VectorF0 /**< TIM13. */ +#define TIM14_IRQHandler VectorF4 /**< TIM14. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Main clock source selection. + * @note If the selected clock source is not the PLL then the PLL is not + * initialized and started. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_SW) || defined(__DOXYGEN__) +#define STM32_SW STM32_SW_PLL +#endif + +/** + * @brief Clock source for the PLL. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) +#define STM32_PLLSRC STM32_PLLSRC_HSE +#endif + +/** + * @brief Crystal PLL pre-divider. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__) +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#endif + +/** + * @brief PLL multiplier value. + * @note The allowed range is 2...16. + * @note The default value is calculated for a 24MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLMUL_VALUE 3 +#endif + +/** + * @brief AHB prescaler value. + * @note The default value is calculated for a 24MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_HPRE) || defined(__DOXYGEN__) +#define STM32_HPRE STM32_HPRE_DIV1 +#endif + +/** + * @brief APB1 prescaler value. + */ +#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#endif + +/** + * @brief APB2 prescaler value. + */ +#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#endif + +/** + * @brief ADC prescaler value. + */ +#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__) +#define STM32_ADCPRE STM32_ADCPRE_DIV2 +#endif + +/** + * @brief MCO pin setting. + */ +#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__) +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#endif + +/** + * @brief RTC clock source. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCSEL STM32_RTCSEL_LSI +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * HSI related checks. + */ +#if STM32_HSI_ENABLED +#else /* !STM32_HSI_ENABLED */ + +#if STM32_SW == STM32_SW_HSI +#error "HSI not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "HSI not enabled, required by STM32_MCOSEL" +#endif + +#endif /* !STM32_HSI_ENABLED */ + +/* + * HSE related checks. + */ +#if STM32_HSE_ENABLED + +#if STM32_HSECLK == 0 +#error "HSE frequency not defined" +#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) +#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" +#endif + +#else /* !STM32_HSE_ENABLED */ + +#if STM32_SW == STM32_SW_HSE +#error "HSE not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE) +#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)) +#error "HSE not enabled, required by STM32_MCOSEL" +#endif + +#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#error "HSE not enabled, required by STM32_RTCSELSEL" +#endif + +#endif /* !STM32_HSE_ENABLED */ + +/* + * LSI related checks. + */ +#if STM32_LSI_ENABLED +#else /* !STM32_LSI_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSI +#error "LSI not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSI_ENABLED */ + +/* + * LSE related checks. + */ +#if STM32_LSE_ENABLED + +#if (STM32_LSECLK == 0) +#error "LSE frequency not defined" +#endif + +#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) +#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" +#endif + +#else /* !STM32_LSE_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSE +#error "LSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSE_ENABLED */ + +/* PLL activation conditions.*/ +#if (STM32_SW == STM32_SW_PLL) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \ + defined(__DOXYGEN__) +/** + * @brief PLL activation flag. + */ +#define STM32_ACTIVATE_PLL TRUE +#else +#define STM32_ACTIVATE_PLL FALSE +#endif + +/* HSE prescaler setting check.*/ +#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \ + (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2) +#error "invalid STM32_PLLXTPRE value specified" +#endif + +/** + * @brief PLLMUL field. + */ +#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \ + defined(__DOXYGEN__) +#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) +#else +#error "invalid STM32_PLLMUL_VALUE value specified" +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1 +#define STM32_PLLCLKIN (STM32_HSECLK / 1) +#else +#define STM32_PLLCLKIN (STM32_HSECLK / 2) +#endif +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLCLKIN (STM32_HSICLK / 2) +#else +#error "invalid STM32_PLLSRC value specified" +#endif + +/* PLL input frequency range check.*/ +#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX) +#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) + +/* PLL output frequency range check.*/ +#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX) +#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)" +#endif + +/** + * @brief System clock source. + */ +#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__) +#define STM32_SYSCLK STM32_PLLCLKOUT +#elif (STM32_SW == STM32_SW_HSI) +#define STM32_SYSCLK STM32_HSICLK +#elif (STM32_SW == STM32_SW_HSE) +#define STM32_SYSCLK STM32_HSECLK +#else +#error "invalid STM32_SYSCLK_SW value specified" +#endif + +/* Check on the system clock.*/ +#if STM32_SYSCLK > STM32_SYSCLK_MAX +#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief AHB frequency. + */ +#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK (STM32_SYSCLK / 1) +#elif STM32_HPRE == STM32_HPRE_DIV2 +#define STM32_HCLK (STM32_SYSCLK / 2) +#elif STM32_HPRE == STM32_HPRE_DIV4 +#define STM32_HCLK (STM32_SYSCLK / 4) +#elif STM32_HPRE == STM32_HPRE_DIV8 +#define STM32_HCLK (STM32_SYSCLK / 8) +#elif STM32_HPRE == STM32_HPRE_DIV16 +#define STM32_HCLK (STM32_SYSCLK / 16) +#elif STM32_HPRE == STM32_HPRE_DIV64 +#define STM32_HCLK (STM32_SYSCLK / 64) +#elif STM32_HPRE == STM32_HPRE_DIV128 +#define STM32_HCLK (STM32_SYSCLK / 128) +#elif STM32_HPRE == STM32_HPRE_DIV256 +#define STM32_HCLK (STM32_SYSCLK / 256) +#elif STM32_HPRE == STM32_HPRE_DIV512 +#define STM32_HCLK (STM32_SYSCLK / 512) +#else +#error "invalid STM32_HPRE value specified" +#endif + +/* AHB frequency check.*/ +#if STM32_HCLK > STM32_SYSCLK_MAX +#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief APB1 frequency. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK1 (STM32_HCLK / 1) +#elif STM32_PPRE1 == STM32_PPRE1_DIV2 +#define STM32_PCLK1 (STM32_HCLK / 2) +#elif STM32_PPRE1 == STM32_PPRE1_DIV4 +#define STM32_PCLK1 (STM32_HCLK / 4) +#elif STM32_PPRE1 == STM32_PPRE1_DIV8 +#define STM32_PCLK1 (STM32_HCLK / 8) +#elif STM32_PPRE1 == STM32_PPRE1_DIV16 +#define STM32_PCLK1 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE1 value specified" +#endif + +/* APB1 frequency check.*/ +#if STM32_PCLK1 > STM32_PCLK1_MAX +#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" +#endif + +/** + * @brief APB2 frequency. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK2 (STM32_HCLK / 1) +#elif STM32_PPRE2 == STM32_PPRE2_DIV2 +#define STM32_PCLK2 (STM32_HCLK / 2) +#elif STM32_PPRE2 == STM32_PPRE2_DIV4 +#define STM32_PCLK2 (STM32_HCLK / 4) +#elif STM32_PPRE2 == STM32_PPRE2_DIV8 +#define STM32_PCLK2 (STM32_HCLK / 8) +#elif STM32_PPRE2 == STM32_PPRE2_DIV16 +#define STM32_PCLK2 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE2 value specified" +#endif + +/* APB2 frequency check.*/ +#if STM32_PCLK2 > STM32_PCLK2_MAX +#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" +#endif + +/** + * @brief RTC clock. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__) +#define STM32_RTCCLK STM32_LSECLK +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM32_RTCCLK STM32_LSICLK +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM32_RTCCLK (STM32_HSECLK / 128) +#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK +#define STM32_RTCCLK 0 +#else +#error "invalid source selected for RTC clock" +#endif + +/** + * @brief ADC frequency. + */ +#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__) +#define STM32_ADCCLK (STM32_PCLK2 / 2) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV4 +#define STM32_ADCCLK (STM32_PCLK2 / 4) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV6 +#define STM32_ADCCLK (STM32_PCLK2 / 6) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV8 +#define STM32_ADCCLK (STM32_PCLK2 / 8) +#else +#error "invalid STM32_ADCPRE value specified" +#endif + +/* ADC frequency check.*/ +#if STM32_ADCCLK > STM32_ADCCLK_MAX +#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)" +#endif + +/** + * @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK1 (STM32_PCLK1 * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK1 * 2) +#endif + +/** + * @brief Timers 1, 8, 9, 10, 11 clock. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK2 (STM32_PCLK2 * 1) +#else +#define STM32_TIMCLK2 (STM32_PCLK2 * 2) +#endif + +/** + * @brief Flash settings. + */ +#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__) +#define STM32_FLASHBITS 0x00000010 +#elif STM32_HCLK <= 48000000 +#define STM32_FLASHBITS 0x00000011 +#else +#define STM32_FLASHBITS 0x00000012 +#endif + +#endif /* _HAL_LLD_F100_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/Project/os/hal/platforms/STM32F1xx/hal_lld_f103.h new file mode 100644 index 0000000..73f5683 --- /dev/null +++ b/Project/os/hal/platforms/STM32F1xx/hal_lld_f103.h @@ -0,0 +1,1299 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup STM32F103_HAL STM32F103 HAL Support + * @details HAL support for STM32 Performance Line LD, MD and HD sub-families. + * + * @ingroup HAL + */ + +/** + * @file STM32F1xx/hal_lld_f103.h + * @brief STM32F103 Performance Line HAL subsystem low level driver header. + * + * @addtogroup STM32F103_HAL + * @{ + */ + +#ifndef _HAL_LLD_F103_H_ +#define _HAL_LLD_F103_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Platform identification + * @{ + */ +#if defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32F1 Performance Line" + +#elif defined(STM32F10X_LD) +#define PLATFORM_NAME "STM32F1 Performance Line Low Density" + +#elif defined(STM32F10X_MD) +#define PLATFORM_NAME "STM32F1 Performance Line Medium Density" + +#elif defined(STM32F10X_HD) +#define PLATFORM_NAME "STM32F1 Performance Line High Density" + +#elif defined(STM32F10X_XL) +#define PLATFORM_NAME "STM32F1 Performance Line eXtra Density" + +#else +#error "unsupported STM32 Performance Line member" +#endif +/** @} */ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Maximum system clock frequency. + */ +#define STM32_SYSCLK_MAX 72000000 + +/** + * @brief Maximum HSE clock frequency. + */ +#define STM32_HSECLK_MAX 25000000 + +/** + * @brief Minimum HSE clock frequency. + */ +#define STM32_HSECLK_MIN 1000000 + +/** + * @brief Maximum LSE clock frequency. + */ +#define STM32_LSECLK_MAX 1000000 + +/** + * @brief Minimum LSE clock frequency. + */ +#define STM32_LSECLK_MIN 32768 + +/** + * @brief Maximum PLLs input clock frequency. + */ +#define STM32_PLLIN_MAX 25000000 + +/** + * @brief Maximum PLLs input clock frequency. + */ +#define STM32_PLLIN_MIN 1000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define STM32_PLLOUT_MAX 72000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define STM32_PLLOUT_MIN 16000000 + +/** + * @brief Maximum APB1 clock frequency. + */ +#define STM32_PCLK1_MAX 36000000 + +/** + * @brief Maximum APB2 clock frequency. + */ +#define STM32_PCLK2_MAX 72000000 + +/** + * @brief Maximum ADC clock frequency. + */ +#define STM32_ADCCLK_MAX 14000000 +/** @} */ + +/** + * @name RCC_CFGR register bits definitions + * @{ + */ +#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ +#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ +#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ + +#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ +#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ +#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ +#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ +#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ +#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ +#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ +#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ +#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ + +#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */ +#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */ +#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */ +#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ +#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ + +#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ +#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ +#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ +#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ +#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ + +#define STM32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */ +#define STM32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */ +#define STM32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */ +#define STM32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */ + +#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ +#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */ + +#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */ +#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */ + +#define STM32_USBPRE_DIV1P5 (0 << 22) /**< PLLOUT divided by 1.5. */ +#define STM32_USBPRE_DIV1 (1 << 22) /**< PLLOUT divided by 1. */ + +#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ +#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */ +#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */ +#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */ +#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ +/** @} */ + +/** + * @name RCC_BDCR register bits definitions + * @{ + */ +#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */ +#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */ +#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */ +#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */ +#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as + RTC clock. */ +/** @} */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +#if defined(STM32F10X_LD) || defined(__DOXYGEN__) +/** + * @name STM32F103 LD capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 14 + +/* DAC attributes.*/ +#define STM32_HAS_DAC FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 FALSE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 19 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE FALSE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C2 FALSE +#define STM32_I2C2_RX_DMA_MSK 0 +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK 0 +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C3 FALSE +#define STM32_SPI3_RX_DMA_MSK 0 +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK 0 +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI2 FALSE +#define STM32_SPI2_RX_DMA_MSK 0 +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK 0 +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 FALSE +#define STM32_SPI3_RX_DMA_MSK 0 +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK 0 +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 FALSE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 FALSE +#define STM32_HAS_TIM7 FALSE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART3 FALSE +#define STM32_USART3_RX_DMA_MSK 0 +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK 0 +#define STM32_USART3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART4 FALSE +#define STM32_UART4_RX_DMA_MSK 0 +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK 0 +#define STM32_UART4_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART5 FALSE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 + +/* USB attributes.*/ +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ +#endif /* defined(STM32F10X_LD) */ + +#if defined(STM32F10X_MD) || defined(__DOXYGEN__) +/** + * @name STM32F103 MD capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 14 + +/* DAC attributes.*/ +#define STM32_HAS_DAC FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 FALSE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 19 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C3 FALSE +#define STM32_I2C3_RX_DMA_MSK 0 +#define STM32_I2C3_RX_DMA_CHN 0x00000000 +#define STM32_I2C3_TX_DMA_MSK 0 +#define STM32_I2C3_TX_DMA_CHN 0x00000000 + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTCSEL_HAS_SUBSECONDS TRUE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 FALSE +#define STM32_SPI3_RX_DMA_MSK 0 +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK 0 +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 FALSE +#define STM32_HAS_TIM7 FALSE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_USART3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART4 FALSE +#define STM32_UART4_RX_DMA_MSK 0 +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK 0 +#define STM32_UART4_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART5 FALSE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 + +/* USB attributes.*/ +#define STM32_HAS_USB TRUE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ +#endif /* defined(STM32F10X_MD) */ + +#if defined(STM32F10X_HD) || defined(__DOXYGEN__) +/** + * @name STM32F103 HD capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 TRUE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 14 + +/* DAC attributes.*/ +#define STM32_HAS_DAC TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 TRUE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 19 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C3 FALSE +#define STM32_I2C3_RX_DMA_MSK 0 +#define STM32_I2C3_RX_DMA_CHN 0x00000000 +#define STM32_I2C3_TX_DMA_MSK 0 +#define STM32_I2C3_TX_DMA_CHN 0x00000000 + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTCSEL_HAS_SUBSECONDS TRUE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO TRUE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 TRUE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 TRUE +#define STM32_HAS_TIM9 TRUE +#define STM32_HAS_TIM10 TRUE +#define STM32_HAS_TIM11 TRUE +#define STM32_HAS_TIM12 TRUE +#define STM32_HAS_TIM13 TRUE +#define STM32_HAS_TIM14 TRUE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_USART3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART4 TRUE +#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_UART4_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART5 TRUE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 + +/* USB attributes.*/ +#define STM32_HAS_USB TRUE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ +#endif /* defined(STM32F10X_HD) */ + +#if defined(STM32F10X_XL) || defined(__DOXYGEN__) +/** + * @name STM32F103 XL capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 TRUE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 14 + +/* DAC attributes.*/ +#define STM32_HAS_DAC TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 TRUE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 19 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C3 FALSE +#define STM32_I2C3_RX_DMA_MSK 0 +#define STM32_I2C3_RX_DMA_CHN 0x00000000 +#define STM32_I2C3_TX_DMA_MSK 0 +#define STM32_I2C3_TX_DMA_CHN 0x00000000 + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTCSEL_HAS_SUBSECONDS TRUE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO TRUE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 TRUE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 TRUE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_USART3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART4 TRUE +#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_UART4_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART5 TRUE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 + +/* USB attributes.*/ +#define STM32_HAS_USB TRUE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ +#endif /* defined(STM32F10X_XL) */ + +/*===========================================================================*/ +/* Platform specific friendly IRQ names. */ +/*===========================================================================*/ + +/** + * @name IRQ VECTOR names + * @{ + */ +#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ +#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line + detect. */ +#define TAMPER_IRQHandler Vector48 /**< Tamper. */ +#define RTC_IRQHandler Vector4C /**< RTC. */ +#define FLASH_IRQHandler Vector50 /**< Flash. */ +#define RCC_IRQHandler Vector54 /**< RCC. */ +#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ +#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ +#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ +#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ +#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ +#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ +#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ +#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ +#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ +#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ +#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ +#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ +#define ADC1_2_IRQHandler Vector88 /**< ADC1_2. */ +#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */ +#define USB_HP_IRQHandler Vector8C /**< USB High Priority, CAN1 TX.*/ +#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */ +#define USB_LP_IRQHandler Vector90 /**< USB Low Priority, CAN1 RX0.*/ +#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ +#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ +#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ +#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ +#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ +#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and + Commutation. */ +#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ +#define TIM2_IRQHandler VectorB0 /**< TIM2. */ +#define TIM3_IRQHandler VectorB4 /**< TIM3. */ +#define TIM4_IRQHandler VectorB8 /**< TIM4. */ +#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ +#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ +#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ +#define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */ +#define SPI1_IRQHandler VectorCC /**< SPI1. */ +#define SPI2_IRQHandler VectorD0 /**< SPI2. */ +#define USART1_IRQHandler VectorD4 /**< USART1. */ +#define USART2_IRQHandler VectorD8 /**< USART2. */ +#define USART3_IRQHandler VectorDC /**< USART3. */ +#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ +#define RTC_Alarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ +#define USB_FS_WKUP_IRQHandler VectorE8 /**< USB Wakeup from suspend. */ +#define TIM8_BRK_IRQHandler VectorEC /**< TIM8 Break. */ +#define TIM8_UP_IRQHandler VectorF0 /**< TIM8 Update. */ +#define TIM8_TRG_COM_IRQHandler VectorF4 /**< TIM8 Trigger and + Commutation. */ +#define TIM8_CC_IRQHandler VectorF8 /**< TIM8 Capture Compare. */ +#define ADC3_IRQHandler VectorFC /**< ADC3. */ +#define FSMC_IRQHandler Vector100 /**< FSMC. */ +#define SDIO_IRQHandler Vector104 /**< SDIO. */ +#define TIM5_IRQHandler Vector108 /**< TIM5. */ +#define SPI3_IRQHandler Vector10C /**< SPI3. */ +#define UART4_IRQHandler Vector110 /**< UART4. */ +#define UART5_IRQHandler Vector114 /**< UART5. */ +#define TIM6_IRQHandler Vector118 /**< TIM6. */ +#define TIM7_IRQHandler Vector11C /**< TIM7. */ +#define DMA2_Ch1_IRQHandler Vector120 /**< DMA2 Channel1. */ +#define DMA2_Ch2_IRQHandler Vector124 /**< DMA2 Channel2. */ +#define DMA2_Ch3_IRQHandler Vector128 /**< DMA2 Channel3. */ +#define DMA2_Ch4_5_IRQHandler Vector12C /**< DMA2 Channel4 & Channel5. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Main clock source selection. + * @note If the selected clock source is not the PLL then the PLL is not + * initialized and started. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_SW) || defined(__DOXYGEN__) +#define STM32_SW STM32_SW_PLL +#endif + +/** + * @brief Clock source for the PLL. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) +#define STM32_PLLSRC STM32_PLLSRC_HSE +#endif + +/** + * @brief Crystal PLL pre-divider. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__) +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#endif + +/** + * @brief PLL multiplier value. + * @note The allowed range is 2...16. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLMUL_VALUE 9 +#endif + +/** + * @brief AHB prescaler value. + * @note The default value is calculated for a 72MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(STM32_HPRE) || defined(__DOXYGEN__) +#define STM32_HPRE STM32_HPRE_DIV1 +#endif + +/** + * @brief APB1 prescaler value. + */ +#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#endif + +/** + * @brief APB2 prescaler value. + */ +#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#endif + +/** + * @brief ADC prescaler value. + */ +#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__) +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#endif + +/** + * @brief USB clock setting. + */ +#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__) +#define STM32_USB_CLOCK_REQUIRED TRUE +#endif + +/** + * @brief USB prescaler initialization. + */ +#if !defined(STM32_USBPRE) || defined(__DOXYGEN__) +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#endif + +/** + * @brief MCO pin setting. + */ +#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__) +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#endif + +/** + * @brief RTC clock source. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCSEL STM32_RTCSEL_LSI +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * HSI related checks. + */ +#if STM32_HSI_ENABLED +#else /* !STM32_HSI_ENABLED */ + +#if STM32_SW == STM32_SW_HSI +#error "HSI not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "HSI not enabled, required by STM32_MCOSEL" +#endif + +#endif /* !STM32_HSI_ENABLED */ + +/* + * HSE related checks. + */ +#if STM32_HSE_ENABLED + +#if STM32_HSECLK == 0 +#error "HSE frequency not defined" +#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) +#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" +#endif + +#else /* !STM32_HSE_ENABLED */ + +#if STM32_SW == STM32_SW_HSE +#error "HSE not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE) +#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) +#error "HSE not enabled, required by STM32_MCOSEL" +#endif + +#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#error "HSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_HSE_ENABLED */ + +/* + * LSI related checks. + */ +#if STM32_LSI_ENABLED +#else /* !STM32_LSI_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSI +#error "LSI not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSI_ENABLED */ + +/* + * LSE related checks. + */ +#if STM32_LSE_ENABLED + +#if (STM32_LSECLK == 0) +#error "LSE frequency not defined" +#endif + +#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) +#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" +#endif + +#else /* !STM32_LSE_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSE +#error "LSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSE_ENABLED */ + +/* PLL activation conditions.*/ +#if STM32_USB_CLOCK_REQUIRED || \ + (STM32_SW == STM32_SW_PLL) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \ + defined(__DOXYGEN__) +/** + * @brief PLL activation flag. + */ +#define STM32_ACTIVATE_PLL TRUE +#else +#define STM32_ACTIVATE_PLL FALSE +#endif + +/* HSE prescaler setting check.*/ +#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \ + (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2) +#error "invalid STM32_PLLXTPRE value specified" +#endif + +/** + * @brief PLLMUL field. + */ +#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \ + defined(__DOXYGEN__) +#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) +#else +#error "invalid STM32_PLLMUL_VALUE value specified" +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1 +#define STM32_PLLCLKIN (STM32_HSECLK / 1) +#else +#define STM32_PLLCLKIN (STM32_HSECLK / 2) +#endif +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLCLKIN (STM32_HSICLK / 2) +#else +#error "invalid STM32_PLLSRC value specified" +#endif + +/* PLL input frequency range check.*/ +#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX) +#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) + +/* PLL output frequency range check.*/ +#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX) +#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)" +#endif + +/** + * @brief System clock source. + */ +#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__) +#define STM32_SYSCLK STM32_PLLCLKOUT +#elif (STM32_SW == STM32_SW_HSI) +#define STM32_SYSCLK STM32_HSICLK +#elif (STM32_SW == STM32_SW_HSE) +#define STM32_SYSCLK STM32_HSECLK +#else +#error "invalid STM32_SYSCLK_SW value specified" +#endif + +/* Check on the system clock.*/ +#if STM32_SYSCLK > STM32_SYSCLK_MAX +#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief AHB frequency. + */ +#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK (STM32_SYSCLK / 1) +#elif STM32_HPRE == STM32_HPRE_DIV2 +#define STM32_HCLK (STM32_SYSCLK / 2) +#elif STM32_HPRE == STM32_HPRE_DIV4 +#define STM32_HCLK (STM32_SYSCLK / 4) +#elif STM32_HPRE == STM32_HPRE_DIV8 +#define STM32_HCLK (STM32_SYSCLK / 8) +#elif STM32_HPRE == STM32_HPRE_DIV16 +#define STM32_HCLK (STM32_SYSCLK / 16) +#elif STM32_HPRE == STM32_HPRE_DIV64 +#define STM32_HCLK (STM32_SYSCLK / 64) +#elif STM32_HPRE == STM32_HPRE_DIV128 +#define STM32_HCLK (STM32_SYSCLK / 128) +#elif STM32_HPRE == STM32_HPRE_DIV256 +#define STM32_HCLK (STM32_SYSCLK / 256) +#elif STM32_HPRE == STM32_HPRE_DIV512 +#define STM32_HCLK (STM32_SYSCLK / 512) +#else +#error "invalid STM32_HPRE value specified" +#endif + +/* AHB frequency check.*/ +#if STM32_HCLK > STM32_SYSCLK_MAX +#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief APB1 frequency. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK1 (STM32_HCLK / 1) +#elif STM32_PPRE1 == STM32_PPRE1_DIV2 +#define STM32_PCLK1 (STM32_HCLK / 2) +#elif STM32_PPRE1 == STM32_PPRE1_DIV4 +#define STM32_PCLK1 (STM32_HCLK / 4) +#elif STM32_PPRE1 == STM32_PPRE1_DIV8 +#define STM32_PCLK1 (STM32_HCLK / 8) +#elif STM32_PPRE1 == STM32_PPRE1_DIV16 +#define STM32_PCLK1 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE1 value specified" +#endif + +/* APB1 frequency check.*/ +#if STM32_PCLK1 > STM32_PCLK1_MAX +#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" +#endif + +/** + * @brief APB2 frequency. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK2 (STM32_HCLK / 1) +#elif STM32_PPRE2 == STM32_PPRE2_DIV2 +#define STM32_PCLK2 (STM32_HCLK / 2) +#elif STM32_PPRE2 == STM32_PPRE2_DIV4 +#define STM32_PCLK2 (STM32_HCLK / 4) +#elif STM32_PPRE2 == STM32_PPRE2_DIV8 +#define STM32_PCLK2 (STM32_HCLK / 8) +#elif STM32_PPRE2 == STM32_PPRE2_DIV16 +#define STM32_PCLK2 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE2 value specified" +#endif + +/* APB2 frequency check.*/ +#if STM32_PCLK2 > STM32_PCLK2_MAX +#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" +#endif + +/** + * @brief RTC clock. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__) +#define STM32_RTCCLK STM32_LSECLK +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM32_RTCCLK STM32_LSICLK +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM32_RTCCLK (STM32_HSECLK / 128) +#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK +#define STM32_RTCCLK 0 +#else +#error "invalid source selected for RTC clock" +#endif + +/** + * @brief ADC frequency. + */ +#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__) +#define STM32_ADCCLK (STM32_PCLK2 / 2) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV4 +#define STM32_ADCCLK (STM32_PCLK2 / 4) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV6 +#define STM32_ADCCLK (STM32_PCLK2 / 6) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV8 +#define STM32_ADCCLK (STM32_PCLK2 / 8) +#else +#error "invalid STM32_ADCPRE value specified" +#endif + +/* ADC frequency check.*/ +#if STM32_ADCCLK > STM32_ADCCLK_MAX +#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)" +#endif + +/** + * @brief USB frequency. + */ +#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__) +#define STM32_USBCLK ((STM32_PLLCLKOUT * 2) / 3) +#elif (STM32_USBPRE == STM32_USBPRE_DIV1) +#define STM32_USBCLK STM32_PLLCLKOUT +#else +#error "invalid STM32_USBPRE value specified" +#endif + +/** + * @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK1 (STM32_PCLK1 * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK1 * 2) +#endif + +/** + * @brief Timers 1, 8, 9, 10, 11 clock. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK2 (STM32_PCLK2 * 1) +#else +#define STM32_TIMCLK2 (STM32_PCLK2 * 2) +#endif + +/** + * @brief Flash settings. + */ +#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__) +#define STM32_FLASHBITS 0x00000010 +#elif STM32_HCLK <= 48000000 +#define STM32_FLASHBITS 0x00000011 +#else +#define STM32_FLASHBITS 0x00000012 +#endif + +#endif /* _HAL_LLD_F103_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/Project/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h new file mode 100644 index 0000000..747a213 --- /dev/null +++ b/Project/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -0,0 +1,1048 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup STM32F10X_CL_HAL STM32F105/F107 HAL Support + * @details HAL support for STM32 Connectivity Line sub-family. + * + * @ingroup HAL + */ + +/** + * @file STM32F1xx/hal_lld_f105_f107.h + * @brief STM32F10x Connectivity Line HAL subsystem low level driver header. + * + * @addtogroup STM32F10X_CL_HAL + * @{ + */ + +#ifndef _HAL_LLD_F105_F107_H_ +#define _HAL_LLD_F105_F107_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Platform identification + * @{ + */ +#define PLATFORM_NAME "STM32F1 Connectivity Line" +/** @} */ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Maximum system clock frequency. + */ +#define STM32_SYSCLK_MAX 72000000 + +/** + * @brief Maximum HSE clock frequency. + */ +#define STM32_HSECLK_MAX 50000000 + +/** + * @brief Minimum HSE clock frequency. + */ +#define STM32_HSECLK_MIN 1000000 + +/** + * @brief Maximum LSE clock frequency. + */ +#define STM32_LSECLK_MAX 1000000 + +/** + * @brief Minimum LSE clock frequency. + */ +#define STM32_LSECLK_MIN 32768 + +/** + * @brief Maximum PLLs input clock frequency. + */ +#define STM32_PLL1IN_MAX 12000000 + +/** + * @brief Maximum PLL1 input clock frequency. + */ +#define STM32_PLL1IN_MIN 3000000 + +/** + * @brief Maximum PLL1 input clock frequency. + */ +#define STM32_PLL23IN_MAX 5000000 + +/** + * @brief Maximum PLL2 and PLL3 input clock frequency. + */ +#define STM32_PLL23IN_MIN 3000000 + +/** + * @brief Maximum PLL1 VCO clock frequency. + */ +#define STM32_PLL1VCO_MAX 144000000 + +/** + * @brief Maximum PLL1 VCO clock frequency. + */ +#define STM32_PLL1VCO_MIN 36000000 + +/** + * @brief Maximum PLL2 and PLL3 VCO clock frequency. + */ +#define STM32_PLL23VCO_MAX 148000000 + +/** + * @brief Maximum PLL2 and PLL3 VCO clock frequency. + */ +#define STM32_PLL23VCO_MIN 80000000 + +/** + * @brief Maximum APB1 clock frequency. + */ +#define STM32_PCLK1_MAX 36000000 + +/** + * @brief Maximum APB2 clock frequency. + */ +#define STM32_PCLK2_MAX 72000000 + +/** + * @brief Maximum ADC clock frequency. + */ +#define STM32_ADCCLK_MAX 14000000 + +/** + * @brief Maximum SPI/I2S clock frequency. + */ +#define STM32_SPII2S_MAX 18000000 +/** @} */ + +/** + * @name RCC_CFGR register bits definitions + * @{ + */ +#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ +#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ +#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ + +#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ +#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ +#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ +#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ +#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ +#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ +#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ +#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ +#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ + +#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */ +#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */ +#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */ +#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ +#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ + +#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ +#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ +#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ +#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ +#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ + +#define STM32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */ +#define STM32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */ +#define STM32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */ +#define STM32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */ + +#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ +#define STM32_PLLSRC_PREDIV1 (1 << 16) /**< PLL clock source is + PREDIV1. */ + +#define STM32_OTGFSPRE_DIV2 (1 << 22) /**< HCLK*2 divided by 2. */ +#define STM32_OTGFSPRE_DIV3 (0 << 22) /**< HCLK*2 divided by 3. */ + +#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ +#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */ +#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */ +#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */ +#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ +#define STM32_MCOSEL_PLL2 (8 << 24) /**< PLL2 clock on MCO pin. */ +#define STM32_MCOSEL_PLL3DIV2 (9 << 24) /**< PLL3/2 clock on MCO pin. */ +#define STM32_MCOSEL_XT1 (10 << 24) /**< XT1 clock on MCO pin. */ +#define STM32_MCOSEL_PLL3 (11 << 24) /**< PLL3 clock on MCO pin. */ +/** @} */ + +/** + * @name RCC_BDCR register bits definitions + * @{ + */ +#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */ +#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */ +#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */ +#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */ +#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as + RTC clock. */ +/** @} */ + +/** + * @name RCC_CFGR2 register bits definitions + * @{ + */ +#define STM32_PREDIV1SRC_HSE (0 << 16) /**< PREDIV1 source is HSE. */ +#define STM32_PREDIV1SRC_PLL2 (1 << 16) /**< PREDIV1 source is PLL2. */ +/** @} */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name STM32F105/F107 CL capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 TRUE +#define STM32_CAN_MAX_FILTERS 28 + +/* DAC attributes.*/ +#define STM32_HAS_DAC TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 TRUE + +/* ETH attributes.*/ +#define STM32_HAS_ETH TRUE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 20 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C3 FALSE +#define STM32_I2C3_RX_DMA_MSK 0 +#define STM32_I2C3_RX_DMA_CHN 0x00000000 +#define STM32_I2C3_TX_DMA_MSK 0 +#define STM32_I2C3_TX_DMA_CHN 0x00000000 + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 TRUE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_USART3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART4 TRUE +#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_UART4_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART5 TRUE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 + +/* USB attributes.*/ +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 TRUE +#define STM32_HAS_OTG2 FALSE +/** @} */ + +/*===========================================================================*/ +/* Platform specific friendly IRQ names. */ +/*===========================================================================*/ + +/** + * @name IRQ VECTOR names + * @{ + */ +#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ +#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line + detect. */ +#define TAMPER_IRQHandler Vector48 /**< Tamper. */ +#define RTC_IRQHandler Vector4C /**< RTC. */ +#define FLASH_IRQHandler Vector50 /**< Flash. */ +#define RCC_IRQHandler Vector54 /**< RCC. */ +#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ +#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ +#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ +#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ +#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ +#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ +#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ +#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ +#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ +#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ +#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ +#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ +#define ADC1_2_IRQHandler Vector88 /**< ADC1 and ADC2. */ +#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */ +#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */ +#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ +#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ +#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ +#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ +#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ +#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and + Commutation. */ +#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ +#define TIM2_IRQHandler VectorB0 /**< TIM2. */ +#define TIM3_IRQHandler VectorB4 /**< TIM3. */ +#define TIM4_IRQHandler VectorB8 /**< TIM4. */ +#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ +#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ +#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ +#define I2C2_ER_IRQHandler VectorC8 /**< I2C1 Error. */ +#define SPI1_IRQHandler VectorCC /**< SPI1. */ +#define SPI2_IRQHandler VectorD0 /**< SPI2. */ +#define USART1_IRQHandler VectorD4 /**< USART1. */ +#define USART2_IRQHandler VectorD8 /**< USART2. */ +#define USART3_IRQHandler VectorDC /**< USART3. */ +#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ +#define RTC_Alarm_IRQHandler VectorE4 /**< RTC alarm through EXTI + line. */ +#define OTG_FS_WKUP_IRQHandler VectorE8 /**< USB OTG FS Wakeup through + EXTI line. */ +#define TIM5_IRQHandler Vector108 /**< TIM5. */ +#define SPI3_IRQHandler Vector10C /**< SPI3. */ +#define UART4_IRQHandler Vector110 /**< UART4. */ +#define UART5_IRQHandler Vector114 /**< UART5. */ +#define TIM6_IRQHandler Vector118 /**< TIM6. */ +#define TIM7_IRQHandler Vector11C /**< TIM7. */ +#define DMA2_Ch1_IRQHandler Vector120 /**< DMA2 Channel1. */ +#define DMA2_Ch2_IRQHandler Vector124 /**< DMA2 Channel2. */ +#define DMA2_Ch3_IRQHandler Vector128 /**< DMA2 Channel3. */ +#define DMA2_Ch4_IRQHandler Vector12C /**< DMA2 Channel4. */ +#define DMA2_Ch5_IRQHandler Vector130 /**< DMA2 Channel5. */ +#define ETH_IRQHandler Vector134 /**< Ethernet. */ +#define ETH_WKUP_IRQHandler Vector138 /**< Ethernet Wakeup through + EXTI line. */ +#define CAN2_TX_IRQHandler Vector13C /**< CAN2 TX. */ +#define CAN2_RX0_IRQHandler Vector140 /**< CAN2 RX0. */ +#define CAN2_RX1_IRQHandler Vector144 /**< CAN2 RX1. */ +#define CAN2_SCE_IRQHandler Vector148 /**< CAN2 SCE. */ +#define OTG_FS_IRQHandler Vector14C /**< USB OTG FS. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Main clock source selection. + * @note The default value is calculated for a 72MHz system clock from + * a 25MHz crystal using both PLL and PLL2. + */ +#if !defined(STM32_SW) || defined(__DOXYGEN__) +#define STM32_SW STM32_SW_PLL +#endif + +/** + * @brief Clock source for the PLL. + * @note The default value is calculated for a 72MHz system clock from + * a 25MHz crystal using both PLL and PLL2. + */ +#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) +#define STM32_PLLSRC STM32_PLLSRC_PREDIV1 +#endif + +/** + * @brief PREDIV1 clock source. + * @note The default value is calculated for a 72MHz system clock from + * a 25MHz crystal using both PLL and PLL2. + */ +#if !defined(STM32_PREDIV1SRC) || defined(__DOXYGEN__) +#define STM32_PREDIV1SRC STM32_PREDIV1SRC_HSE +#endif + +/** + * @brief PREDIV1 division factor. + * @note The allowed range is 1...16. + * @note The default value is calculated for a 72MHz system clock from + * a 25MHz crystal using both PLL and PLL2. + */ +#if !defined(STM32_PREDIV1_VALUE) || defined(__DOXYGEN__) +#define STM32_PREDIV1_VALUE 5 +#endif + +/** + * @brief PLL multiplier value. + * @note The allowed range is 4...9. + * @note The default value is calculated for a 72MHz system clock from + * a 25MHz crystal using both PLL and PLL2. + */ +#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLMUL_VALUE 9 +#endif + +/** + * @brief PREDIV2 division factor. + * @note The allowed range is 1...16. + * @note The default value is calculated for a 72MHz system clock from + * a 25MHz crystal using both PLL and PLL2. + */ +#if !defined(STM32_PREDIV2_VALUE) || defined(__DOXYGEN__) +#define STM32_PREDIV2_VALUE 5 +#endif + +/** + * @brief PLL2 multiplier value. + * @note The default value is calculated for a 72MHz system clock from + * a 25MHz crystal using both PLL and PLL2. + */ +#if !defined(STM32_PLL2MUL_VALUE) || defined(__DOXYGEN__) +#define STM32_PLL2MUL_VALUE 8 +#endif + +/** + * @brief PLL3 multiplier value. + * @note The default value is calculated for a 50MHz clock from + * a 25MHz crystal. + */ +#if !defined(STM32_PLL3MUL_VALUE) || defined(__DOXYGEN__) +#define STM32_PLL3MUL_VALUE 10 +#endif + +/** + * @brief AHB prescaler value. + * @note The default value is calculated for a 72MHz system clock from + * a 25MHz crystal using both PLL and PLL2. + */ +#if !defined(STM32_HPRE) || defined(__DOXYGEN__) +#define STM32_HPRE STM32_HPRE_DIV1 +#endif + +/** + * @brief APB1 prescaler value. + */ +#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#endif + +/** + * @brief APB2 prescaler value. + */ +#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#endif + +/** + * @brief ADC prescaler value. + */ +#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__) +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#endif + +/** + * @brief USB clock setting. + */ +#if !defined(STM32_OTG_CLOCK_REQUIRED) || defined(__DOXYGEN__) +#define STM32_OTG_CLOCK_REQUIRED TRUE +#endif + +/** + * @brief OTG prescaler initialization. + */ +#if !defined(STM32_OTGFSPRE) || defined(__DOXYGEN__) +#define STM32_OTGFSPRE STM32_OTGFSPRE_DIV3 +#endif + +/** + * @brief Dedicated I2S clock setting. + */ +#if !defined(STM32_I2S_CLOCK_REQUIRED) || defined(__DOXYGEN__) +#define STM32_I2S_CLOCK_REQUIRED FALSE +#endif + +/** + * @brief MCO pin setting. + */ +#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__) +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#endif + +/** + * @brief RTC clock source. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * HSI related checks. + */ +#if STM32_HSI_ENABLED +#else /* !STM32_HSI_ENABLED */ + +#if STM32_SW == STM32_SW_HSI +#error "HSI not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "HSI not enabled, required by STM32_MCOSEL" +#endif + +#endif /* !STM32_HSI_ENABLED */ + +/* + * HSE related checks. + */ +#if STM32_HSE_ENABLED + +#if STM32_HSECLK == 0 +#error "HSE frequency not defined" +#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) +#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" +#endif + +#else /* !STM32_HSE_ENABLED */ + +#if STM32_SW == STM32_SW_HSE +#error "HSE not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_PREDIV1) +#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLL2DIV2) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLL3DIV2) || \ + (STM32_MCOSEL == STM32_MCOSEL_XT1) +#error "HSE not enabled, required by STM32_MCOSEL" +#endif + +#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#error "HSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_HSE_ENABLED */ + +/* + * LSI related checks. + */ +#if STM32_LSI_ENABLED +#else /* !STM32_LSI_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSI +#error "LSI not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSI_ENABLED */ + +/* + * LSE related checks. + */ +#if STM32_LSE_ENABLED + +#if (STM32_LSECLK == 0) +#error "LSE frequency not defined" +#endif + +#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) +#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" +#endif + +#else /* !STM32_LSE_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSE +#error "LSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSE_ENABLED */ + +/* PLL1 activation conditions.*/ +#if STM32_OTG_CLOCK_REQUIRED || \ + (STM32_SW == STM32_SW_PLL) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \ + defined(__DOXYGEN__) +/** + * @brief PLL1 activation flag. + */ +#define STM32_ACTIVATE_PLL1 TRUE +#else +#define STM32_ACTIVATE_PLL1 FALSE +#endif + +/* PLL2 activation conditions.*/ +#if STM32_OTG_CLOCK_REQUIRED || \ + (STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLL2DIV2) || \ + defined(__DOXYGEN__) +/** + * @brief PLL2 activation flag. + */ +#define STM32_ACTIVATE_PLL2 TRUE +#else +#define STM32_ACTIVATE_PLL2 FALSE +#endif + +/* PLL3 activation conditions.*/ +#if STM32_I2S_CLOCK_REQUIRED || \ + (STM32_MCOSEL == STM32_MCOSEL_PLL3DIV2) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLL3) || \ + defined(__DOXYGEN__) +/** + * @brief PLL3 activation flag. + */ +#define STM32_ACTIVATE_PLL3 TRUE +#else +#define STM32_ACTIVATE_PLL3 FALSE +#endif + +/** + * @brief PREDIV1 field. + */ +#if (STM32_PREDIV1_VALUE >= 1) && (STM32_PREDIV1_VALUE <= 16) || \ + defined(__DOXYGEN__) +#define STM32_PREDIV1 ((STM32_PREDIV1_VALUE - 1) << 0) +#else +#error "invalid STM32_PREDIV1_VALUE value specified" +#endif + +/** + * @brief PREDIV2 field. + */ +#if (STM32_PREDIV2_VALUE >= 1) && (STM32_PREDIV2_VALUE <= 16) || \ + defined(__DOXYGEN__) +#define STM32_PREDIV2 ((STM32_PREDIV2_VALUE - 1) << 4) +#else +#error "invalid STM32_PREDIV2_VALUE value specified" +#endif + +/** + * @brief PLLMUL field. + */ +#if ((STM32_PLLMUL_VALUE >= 4) && (STM32_PLLMUL_VALUE <= 9)) || \ + defined(__DOXYGEN__) +#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) +#else +#error "invalid STM32_PLLMUL_VALUE value specified" +#endif + +/** + * @brief PLL2MUL field. + */ +#if ((STM32_PLL2MUL_VALUE >= 8) && (STM32_PLL2MUL_VALUE <= 14)) || \ + defined(__DOXYGEN__) +#define STM32_PLL2MUL ((STM32_PLL2MUL_VALUE - 2) << 8) +#elif (STM32_PLL2MUL_VALUE == 16) +#define STM32_PLL2MUL (14 << 8) +#elif (STM32_PLL2MUL_VALUE == 20) +#define STM32_PLL2MUL (15 << 8) +#else +#error "invalid STM32_PLL2MUL_VALUE value specified" +#endif + +/** + * @brief PLL3MUL field. + */ +#if ((STM32_PLL3MUL_VALUE >= 8) && (STM32_PLL3MUL_VALUE <= 14)) || \ + defined(__DOXYGEN__) +#define STM32_PLL3MUL ((STM32_PLL3MUL_VALUE - 2) << 12) +#elif (STM32_PLL3MUL_VALUE == 16) +#define STM32_PLL3MUL (14 << 12) +#elif (STM32_PLL3MUL_VALUE == 20) +#define STM32_PLL3MUL (15 << 12) +#else +#error "invalid STM32_PLL3MUL_VALUE value specified" +#endif + +/** + * @brief PLL2 input frequency. + */ +#define STM32_PLL2CLKIN (STM32_HSECLK / STM32_PREDIV2_VALUE) + +/* PLL2 input frequency range check.*/ +#if (STM32_PLL2CLKIN < STM32_PLL23IN_MIN) || \ + (STM32_PLL2CLKIN > STM32_PLL23IN_MAX) +#error "STM32_PLL2CLKIN outside acceptable range (STM32_PLL23IN_MIN...STM32_PLL23IN_MAX)" +#endif + +/** + * @brief PLL2 output clock frequency. + */ +#define STM32_PLL2CLKOUT (STM32_PLL2CLKIN * STM32_PLL2MUL_VALUE) + +/** + * @brief PLL2 VCO clock frequency. + */ +#define STM32_PLL2VCO (STM32_PLL2CLKOUT * 2) + +/* PLL2 output frequency range check.*/ +#if (STM32_PLL2VCO < STM32_PLL23VCO_MIN) || \ + (STM32_PLL2VCO > STM32_PLL23VCO_MAX) +#error "STM32_PLL2VCO outside acceptable range (STM32_PLL23VCO_MIN...STM32_PLL23VCO_MAX)" +#endif + +/** + * @brief PLL3 input frequency. + */ +#define STM32_PLL3CLKIN (STM32_HSECLK / STM32_PREDIV2_VALUE) + +/* PLL3 input frequency range check.*/ +#if (STM32_PLL3CLKIN < STM32_PLL23IN_MIN) || \ + (STM32_PLL3CLKIN > STM32_PLL23IN_MAX) +#error "STM32_PLL3CLKIN outside acceptable range (STM32_PLL23IN_MIN...STM32_PLL23IN_MAX)" +#endif + +/** + * @brief PLL3 output clock frequency. + */ +#define STM32_PLL3CLKOUT (STM32_PLL3CLKIN * STM32_PLL3MUL_VALUE) + +/** + * @brief PLL3 VCO clock frequency. + */ +#define STM32_PLL3VCO (STM32_PLL3CLKOUT * 2) + +/* PLL3 output frequency range check.*/ +#if (STM32_PLL3VCO < STM32_PLL23VCO_MIN) || \ + (STM32_PLL3VCO > STM32_PLL23VCO_MAX) +#error "STM32_PLL3CLKOUT outside acceptable range (STM32_PLL23VCO_MIN...STM32_PLL23VCO_MAX)" +#endif + +/** + * @brief PREDIV1 input frequency. + */ +#if (STM32_PREDIV1SRC == STM32_PREDIV1SRC_HSE) || defined(__DOXYGEN__) +#define STM32_PREDIV1CLK STM32_HSECLK +#elif STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2 +#define STM32_PREDIV1CLK STM32_PLL2CLKOUT +#else +#error "invalid STM32_PREDIV1SRC value specified" +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (STM32_PLLSRC == STM32_PLLSRC_PREDIV1) || defined(__DOXYGEN__) +#define STM32_PLLCLKIN (STM32_PREDIV1CLK / STM32_PREDIV1_VALUE) +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLCLKIN (STM32_HSICLK / 2) +#else +#error "invalid STM32_PLLSRC value specified" +#endif + +/* PLL input frequency range check.*/ +#if (STM32_PLLCLKIN < STM32_PLL1IN_MIN) || (STM32_PLLCLKIN > STM32_PLL1IN_MAX) +#error "STM32_PLLCLKIN outside acceptable range (STM32_PLL1IN_MIN...STM32_PLL1IN_MAX)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) + +/** + * @brief PLL VCO clock frequency. + */ +#define STM32_PLLVCO (STM32_PLLCLKOUT * 2) + +/* PLL output frequency range check.*/ +#if (STM32_PLLVCO < STM32_PLL1VCO_MIN) || (STM32_PLLVCO > STM32_PLL1VCO_MAX) +#error "STM32_PLLVCO outside acceptable range (STM32_PLL1VCO_MIN...STM32_PLL1VCO_MAX)" +#endif + +/** + * @brief System clock source. + */ +#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__) +#define STM32_SYSCLK STM32_PLLCLKOUT +#elif (STM32_SW == STM32_SW_HSI) +#define STM32_SYSCLK STM32_HSICLK +#elif (STM32_SW == STM32_SW_HSE) +#define STM32_SYSCLK STM32_HSECLK +#else +#error "invalid STM32_SYSCLK_SW value specified" +#endif + +/* Check on the system clock.*/ +#if STM32_SYSCLK > STM32_SYSCLK_MAX +#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief AHB frequency. + */ +#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK (STM32_SYSCLK / 1) +#elif STM32_HPRE == STM32_HPRE_DIV2 +#define STM32_HCLK (STM32_SYSCLK / 2) +#elif STM32_HPRE == STM32_HPRE_DIV4 +#define STM32_HCLK (STM32_SYSCLK / 4) +#elif STM32_HPRE == STM32_HPRE_DIV8 +#define STM32_HCLK (STM32_SYSCLK / 8) +#elif STM32_HPRE == STM32_HPRE_DIV16 +#define STM32_HCLK (STM32_SYSCLK / 16) +#elif STM32_HPRE == STM32_HPRE_DIV64 +#define STM32_HCLK (STM32_SYSCLK / 64) +#elif STM32_HPRE == STM32_HPRE_DIV128 +#define STM32_HCLK (STM32_SYSCLK / 128) +#elif STM32_HPRE == STM32_HPRE_DIV256 +#define STM32_HCLK (STM32_SYSCLK / 256) +#elif STM32_HPRE == STM32_HPRE_DIV512 +#define STM32_HCLK (STM32_SYSCLK / 512) +#else +#error "invalid STM32_HPRE value specified" +#endif + +/* AHB frequency check.*/ +#if STM32_HCLK > STM32_SYSCLK_MAX +#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief APB1 frequency. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK1 (STM32_HCLK / 1) +#elif STM32_PPRE1 == STM32_PPRE1_DIV2 +#define STM32_PCLK1 (STM32_HCLK / 2) +#elif STM32_PPRE1 == STM32_PPRE1_DIV4 +#define STM32_PCLK1 (STM32_HCLK / 4) +#elif STM32_PPRE1 == STM32_PPRE1_DIV8 +#define STM32_PCLK1 (STM32_HCLK / 8) +#elif STM32_PPRE1 == STM32_PPRE1_DIV16 +#define STM32_PCLK1 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE1 value specified" +#endif + +/* APB1 frequency check.*/ +#if STM32_PCLK1 > STM32_PCLK1_MAX +#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" +#endif + +/** + * @brief APB2 frequency. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK2 (STM32_HCLK / 1) +#elif STM32_PPRE2 == STM32_PPRE2_DIV2 +#define STM32_PCLK2 (STM32_HCLK / 2) +#elif STM32_PPRE2 == STM32_PPRE2_DIV4 +#define STM32_PCLK2 (STM32_HCLK / 4) +#elif STM32_PPRE2 == STM32_PPRE2_DIV8 +#define STM32_PCLK2 (STM32_HCLK / 8) +#elif STM32_PPRE2 == STM32_PPRE2_DIV16 +#define STM32_PCLK2 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE2 value specified" +#endif + +/* APB2 frequency check.*/ +#if STM32_PCLK2 > STM32_PCLK2_MAX +#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" +#endif + +/** + * @brief RTC clock. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__) +#define STM32_RTCCLK STM32_LSECLK +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM32_RTCCLK STM32_LSICLK +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM32_RTCCLK (STM32_HSECLK / 128) +#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK +#define STM32_RTCCLK 0 +#else +#error "invalid source selected for RTC clock" +#endif + +/** + * @brief ADC frequency. + */ +#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__) +#define STM32_ADCCLK (STM32_PCLK2 / 2) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV4 +#define STM32_ADCCLK (STM32_PCLK2 / 4) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV6 +#define STM32_ADCCLK (STM32_PCLK2 / 6) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV8 +#define STM32_ADCCLK (STM32_PCLK2 / 8) +#else +#error "invalid STM32_ADCPRE value specified" +#endif + +/* ADC frequency check.*/ +#if STM32_ADCCLK > STM32_ADCCLK_MAX +#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)" +#endif + +/** + * @brief OTG frequency. + */ +#if (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV3) || defined(__DOXYGEN__) +#define STM32_OTGFSCLK (STM32_PLLVCO / 3) +#elif (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV2) +#define STM32_OTGFSCLK (STM32_PLLVCO / 2) +#else +#error "invalid STM32_OTGFSPRE value specified" +#endif + +/** + * @brief Timers 2, 3, 4, 5, 6, 7 clock. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK1 (STM32_PCLK1 * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK1 * 2) +#endif + +/** + * @brief Timers 1, 8 clock. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK2 (STM32_PCLK2 * 1) +#else +#define STM32_TIMCLK2 (STM32_PCLK2 * 2) +#endif + +/** + * @brief Flash settings. + */ +#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__) +#define STM32_FLASHBITS 0x00000010 +#elif STM32_HCLK <= 48000000 +#define STM32_FLASHBITS 0x00000011 +#else +#define STM32_FLASHBITS 0x00000012 +#endif + +#endif /* _HAL_LLD_F105_F107_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F1xx/platform.dox b/Project/os/hal/platforms/STM32F1xx/platform.dox new file mode 100644 index 0000000..48a3f14 --- /dev/null +++ b/Project/os/hal/platforms/STM32F1xx/platform.dox @@ -0,0 +1,401 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup STM32F1xx_DRIVERS STM32F1xx Drivers + * @details This section describes all the supported drivers on the STM32F1xx + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup STM32F1xx_HAL STM32F1xx Initialization Support + * @details The STM32F1xx HAL support is responsible for system initialization. + * + * @section stm32f1xx_hal_1 Supported HW resources + * - PLL1. + * - PLL2 (where present). + * - RCC. + * - Flash. + * . + * @section stm32f1xx_hal_2 STM32F1xx HAL driver implementation features + * - PLLs startup and stabilization. + * - Clock tree initialization. + * - Clock source selection. + * - Flash wait states initialization based on the selected clock options. + * - SYSTICK initialization based on current clock and kernel required rate. + * - DMA support initialization. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_ADC STM32F1xx ADC Support + * @details The STM32F1xx ADC driver supports the ADC peripherals using DMA + * channels for maximum performance. + * + * @section stm32f1xx_adc_1 Supported HW resources + * - ADC1. + * - DMA1. + * . + * @section stm32f1xx_adc_2 STM32F1xx ADC driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Streaming conversion using DMA for maximum performance. + * - Programmable ADC interrupt priority level. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - DMA errors detection. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_CAN STM32F1xx CAN Support + * @details The STM32F1xx CAN driver uses the CAN peripherals. + * + * @section stm32f1xx_can_1 Supported HW resources + * - bxCAN1. + * . + * @section stm32f1xx_can_2 STM32F1xx CAN driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Support for bxCAN sleep mode. + * - Programmable bxCAN interrupts priority level. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_EXT STM32F1xx EXT Support + * @details The STM32F1xx EXT driver uses the EXTI peripheral. + * + * @section stm32f1xx_ext_1 Supported HW resources + * - EXTI. + * . + * @section stm32f1xx_ext_2 STM32F1xx EXT driver implementation features + * - Each EXTI channel can be independently enabled and programmed. + * - Programmable EXTI interrupts priority level. + * - Capability to work as event sources (WFE) rather than interrupt sources. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_GPT STM32F1xx GPT Support + * @details The STM32F1xx GPT driver uses the TIMx peripherals. + * + * @section stm32f1xx_gpt_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * - TIM4. + * - TIM5. + * . + * @section stm32f1xx_gpt_2 STM32F1xx GPT driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_I2C STM32F1xx I2C Support + * @details The STM32F1xx I2C driver uses the I2Cx peripherals. + * + * @section stm32f1xx_i2c_1 Supported HW resources + * - I2C1. + * - I2C2. + * . + * @section stm32f1xx_i2c_2 STM32F1xx I2C driver implementation features + * - Each I2C port can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable I2Cx interrupts priority level. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_ICU STM32F1xx ICU Support + * @details The STM32F1xx ICU driver uses the TIMx peripherals. + * + * @section stm32f1xx_icu_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * - TIM4. + * - TIM5. + * . + * @section stm32f1xx_icu_2 STM32F1xx ICU driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_MAC STM32F1xx MAC Support + * @details The STM32 MAC driver supports the ETH peripheral. + * + * @section at91sam7_mac_1 Supported HW resources + * - ETH. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_PAL STM32F1xx PAL Support + * @details The STM32F1xx PAL driver uses the GPIO peripherals. + * + * @section stm32f1xx_pal_1 Supported HW resources + * - AFIO. + * - GPIOA. + * - GPIOB. + * - GPIOC. + * - GPIOD. + * - GPIOE (where present). + * - GPIOF (where present). + * - GPIOG (where present). + * . + * @section stm32f1xx_pal_2 STM32F1xx PAL driver implementation features + * The PAL driver implementation fully supports the following hardware + * capabilities: + * - 16 bits wide ports. + * - Atomic set/reset functions. + * - Atomic set+reset function (atomic bus operations). + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section stm32f1xx_pal_3 Supported PAL setup modes + * The STM32F1xx PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_PULLUP. + * - @p PAL_MODE_INPUT_PULLDOWN. + * - @p PAL_MODE_INPUT_ANALOG. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * - @p PAL_MODE_OUTPUT_OPENDRAIN. + * - @p PAL_MODE_STM32F1xx_ALTERNATE_PUSHPULL (non standard). + * - @p PAL_MODE_STM32F1xx_ALTERNATE_OPENDRAIN (non standard). + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section stm32f1xx_pal_4 Suboptimal behavior + * The STM32F1xx GPIO is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Pad/port toggling operations are not atomic. + * - Pad/group mode setup is not atomic. + * - Writing on pads/groups/ports programmed as input with pull-up/down + * resistor can change the resistor setting because the output latch is + * used for resistor selection. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_PWM STM32F1xx PWM Support + * @details The STM32F1xx PWM driver uses the TIMx peripherals. + * + * @section stm32f1xx_pwm_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * - TIM4. + * - TIM5. + * . + * @section stm32f1xx_pwm_2 STM32F1xx PWM driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Four independent PWM channels per timer. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_RTC STM32F1xx RTC Support + * @details The STM32F1xx RTC driver uses the RTC peripheral. + * + * @section stm32f1xx_rtc_1 Supported HW resources + * - RTC. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_SDC STM32F1xx SDC Support + * @details The STM32F1xx SDC driver uses the SDIO peripheral. + * + * @section stm32f1xx_sdc_1 Supported HW resources + * - SDIO. + * - DMA2. + * . + * @section stm32f1xx_sdc_2 STM32F1xx SDC driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Programmable interrupt priority. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_SERIAL STM32F1xx Serial Support + * @details The STM32F1xx Serial driver uses the USART/UART peripherals in a + * buffered, interrupt driven, implementation. + * + * @section stm32f1xx_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - USART1. + * - USART2. + * - USART3 (where present). + * - UART4 (where present). + * - UART5 (where present). + * . + * @section stm32f1xx_serial_2 STM32F1xx Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART/USART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * - Programmable priority levels for each UART/USART. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_SPI STM32F1xx SPI Support + * @details The SPI driver supports the STM32F1xx SPI peripherals using DMA + * channels for maximum performance. + * + * @section stm32f1xx_spi_1 Supported HW resources + * - SPI1. + * - SPI2. + * - SPI3 (where present). + * - DMA1. + * - DMA2 (where present). + * . + * @section stm32f1xx_spi_2 STM32F1xx SPI driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each SPI can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable interrupt priority levels for each SPI. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - Programmable DMA error hook. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_UART STM32F1xx UART Support + * @details The UART driver supports the STM32F1xx USART peripherals using DMA + * channels for maximum performance. + * + * @section stm32f1xx_uart_1 Supported HW resources + * The UART driver can support any of the following hardware resources: + * - USART1. + * - USART2. + * - USART3 (where present). + * - UART4 (where present). + * - DMA1. + * - DMA2 (where present). + * . + * @section stm32f1xx_uart_2 STM32F1xx UART driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART/USART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable interrupt priority levels for each UART/USART. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - Programmable DMA error hook. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_USB STM32F1xx USB Support + * @details The USB driver supports the STM32F1xx USB peripheral. + * + * @section stm32f1xx_usb_1 Supported HW resources + * The USB driver can support any of the following hardware resources: + * - USB. + * . + * @section stm32f1xx_usb_2 STM32F1xx USB driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Programmable interrupt priority levels. + * - Each endpoint programmable in Control, Bulk and Interrupt modes. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_PLATFORM_DRIVERS STM32F1xx Platform Drivers + * @details Platform support drivers. Platform drivers do not implement HAL + * standard driver templates, their role is to support platform + * specific functionalities. + * + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_DMA STM32F1xx DMA Support + * @details This DMA helper driver is used by the other drivers in order to + * access the shared DMA resources in a consistent way. + * + * @section stm32f1xx_dma_1 Supported HW resources + * The DMA driver can support any of the following hardware resources: + * - DMA1. + * - DMA2 (where present). + * . + * @section stm32f1xx_dma_2 STM32F1xx DMA driver implementation features + * - Exports helper functions/macros to the other drivers that share the + * DMA resource. + * - Automatic DMA clock stop when not in use by any driver. + * - DMA streams and interrupt vectors sharing among multiple drivers. + * . + * @ingroup STM32F1xx_PLATFORM_DRIVERS + */ + +/** + * @defgroup STM32F1xx_RCC STM32F1xx RCC Support + * @details This RCC helper driver is used by the other drivers in order to + * access the shared RCC resources in a consistent way. + * + * @section stm32f1xx_rcc_1 Supported HW resources + * - RCC. + * . + * @section stm32f1xx_rcc_2 STM32F1xx RCC driver implementation features + * - Peripherals reset. + * - Peripherals clock enable. + * - Peripherals clock disable. + * . + * @ingroup STM32F1xx_PLATFORM_DRIVERS + */ diff --git a/Project/os/hal/platforms/STM32F1xx/platform.mk b/Project/os/hal/platforms/STM32F1xx/platform.mk new file mode 100644 index 0000000..ce1d9f8 --- /dev/null +++ b/Project/os/hal/platforms/STM32F1xx/platform.mk @@ -0,0 +1,25 @@ +# List of all the STM32F1xx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/stm32_dma.c \ + ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32F1xx/adc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/i2c_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/uart_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/RTCv1/rtc_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F1xx \ + ${CHIBIOS}/os/hal/platforms/STM32 \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1 \ + ${CHIBIOS}/os/hal/platforms/STM32/USBv1 \ + ${CHIBIOS}/os/hal/platforms/STM32/RTCv1 diff --git a/Project/os/hal/platforms/STM32F1xx/stm32_dma.c b/Project/os/hal/platforms/STM32F1xx/stm32_dma.c new file mode 100644 index 0000000..63fbd34 --- /dev/null +++ b/Project/os/hal/platforms/STM32F1xx/stm32_dma.c @@ -0,0 +1,503 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F1xx/stm32_dma.c + * @brief DMA helper driver code. + * + * @addtogroup STM32F1xx_DMA + * @details DMA sharing helper driver. In the STM32 the DMA streams are a + * shared resource, this driver allows to allocate and free DMA + * streams at runtime in order to allow all the other device + * drivers to coordinate the access to the resource. + * @note The DMA ISR handlers are all declared into this module because + * sharing, the various device drivers can associate a callback to + * ISRs when allocating streams. + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/* The following macro is only defined if some driver requiring DMA services + has been enabled.*/ +#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Mask of the DMA1 streams in @p dma_streams_mask. + */ +#define STM32_DMA1_STREAMS_MASK 0x0000007F + +/** + * @brief Mask of the DMA2 streams in @p dma_streams_mask. + */ +#define STM32_DMA2_STREAMS_MASK 0x00000F80 + +/** + * @brief Post-reset value of the stream CCR register. + */ +#define STM32_DMA_CCR_RESET_VALUE 0x00000000 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief DMA streams descriptors. + * @details This table keeps the association between an unique stream + * identifier and the involved physical registers. + * @note Don't use this array directly, use the appropriate wrapper macros + * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc. + */ +const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { + {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn}, + {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn}, + {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn}, + {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn}, + {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn}, + {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn}, + {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn}, +#if STM32_HAS_DMA2 || defined(__DOXYGEN__) + {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn}, + {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn}, + {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn}, +#if defined(STM32F10X_CL) || defined(__DOXYGEN__) + {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn}, + {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn}, +#else /* !STM32F10X_CL */ + {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_5_IRQn}, + {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel4_5_IRQn}, +#endif /* !STM32F10X_CL */ +#endif /* STM32_HAS_DMA2 */ +}; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief DMA ISR redirector type. + */ +typedef struct { + stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ + void *dma_param; /**< @brief DMA callback parameter. */ +} dma_isr_redir_t; + +/** + * @brief Mask of the allocated streams. + */ +static uint32_t dma_streams_mask; + +/** + * @brief DMA IRQ redirectors. + */ +static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief DMA1 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[0].dma_func) + dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 4; + if (dma_isr_redir[1].dma_func) + dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 8; + if (dma_isr_redir[2].dma_func) + dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 12; + if (dma_isr_redir[3].dma_func) + dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[4].dma_func) + dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 6 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 20; + if (dma_isr_redir[5].dma_func) + dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 7 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 24; + if (dma_isr_redir[6].dma_func) + dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +#if STM32_HAS_DMA2 || defined(__DOXYGEN__) +/** + * @brief DMA2 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch1_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[7].dma_func) + dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 4; + if (dma_isr_redir[8].dma_func) + dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch3_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 8; + if (dma_isr_redir[9].dma_func) + dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +#if defined(STM32F10X_CL) || defined(__DOXYGEN__) +/** + * @brief DMA2 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch4_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 12; + if (dma_isr_redir[10].dma_func) + dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[11].dma_func) + dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} +#else /* !STM32F10X_CL */ +/** + * @brief DMA2 streams 4 and 5 shared interrupt handler. + * @note This IRQ is shared between DMA2 channels 4 and 5 so it is a + * bit less efficient because an extra check. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + /* Check on channel 4.*/ + flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; + if (flags & STM32_DMA_ISR_MASK) { + DMA2->IFCR = STM32_DMA_ISR_MASK << 12; + if (dma_isr_redir[10].dma_func) + dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); + } + + /* Check on channel 5.*/ + flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK; + if (flags & STM32_DMA_ISR_MASK) { + DMA2->IFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[11].dma_func) + dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); + } + + CH_IRQ_EPILOGUE(); +} +#endif /* !STM32F10X_CL */ +#endif /* STM32_HAS_DMA2 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA helper initialization. + * + * @init + */ +void dmaInit(void) { + int i; + + dma_streams_mask = 0; + for (i = 0; i < STM32_DMA_STREAMS; i++) { + _stm32_dma_streams[i].channel->CCR = 0; + dma_isr_redir[i].dma_func = NULL; + } + DMA1->IFCR = 0xFFFFFFFF; +#if STM32_HAS_DMA2 + DMA2->IFCR = 0xFFFFFFFF; +#endif +} + +/** + * @brief Allocates a DMA stream. + * @details The stream is allocated and, if required, the DMA clock enabled. + * The function also enables the IRQ vector associated to the stream + * and initializes its priority. + * @pre The stream must not be already in use or an error is returned. + * @post The stream is allocated and the default ISR handler redirected + * to the specified function. + * @post The stream ISR vector is enabled and its priority configured. + * @post The stream must be freed using @p dmaStreamRelease() before it can + * be reused with another peripheral. + * @post The stream is in its post-reset state. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] priority IRQ priority mask for the DMA stream + * @param[in] func handling function pointer, can be @p NULL + * @param[in] param a parameter to be passed to the handling function + * @return The operation status. + * @retval FALSE no error, stream taken. + * @retval TRUE error, stream already taken. + * + * @special + */ +bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param) { + + chDbgCheck(dmastp != NULL, "dmaAllocate"); + + /* Checks if the stream is already taken.*/ + if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) + return TRUE; + + /* Marks the stream as allocated.*/ + dma_isr_redir[dmastp->selfindex].dma_func = func; + dma_isr_redir[dmastp->selfindex].dma_param = param; + dma_streams_mask |= (1 << dmastp->selfindex); + + /* Enabling DMA clocks required by the current streams set.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) + rccEnableDMA1(FALSE); +#if STM32_HAS_DMA2 + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) + rccEnableDMA2(FALSE); +#endif + + /* Putting the stream in a safe state.*/ + dmaStreamDisable(dmastp); + dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE; + + /* Enables the associated IRQ vector if a callback is defined.*/ + if (func != NULL) + nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); + + return FALSE; +} + +/** + * @brief Releases a DMA stream. + * @details The stream is freed and, if required, the DMA clock disabled. + * Trying to release a unallocated stream is an illegal operation + * and is trapped if assertions are enabled. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post The stream is again available. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { + + chDbgCheck(dmastp != NULL, "dmaRelease"); + + /* Check if the streams is not taken.*/ + chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, + "dmaRelease(), #1", "not allocated"); + + /* Disables the associated IRQ vector.*/ + nvicDisableVector(dmastp->vector); + + /* Marks the stream as not allocated.*/ + dma_streams_mask &= ~(1 << dmastp->selfindex); + + /* Shutting down clocks that are no more required, if any.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) + rccDisableDMA1(FALSE); +#if STM32_HAS_DMA2 + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) + rccDisableDMA2(FALSE); +#endif +} + +#endif /* STM32_DMA_REQUIRED */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F1xx/stm32_dma.h b/Project/os/hal/platforms/STM32F1xx/stm32_dma.h new file mode 100644 index 0000000..2d47ccb --- /dev/null +++ b/Project/os/hal/platforms/STM32F1xx/stm32_dma.h @@ -0,0 +1,404 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F1xx/stm32_dma.h + * @brief DMA helper driver header. + * @note This file requires definitions from the ST header file stm32f10x.h. + * @note This driver uses the new naming convention used for the STM32F2xx + * so the "DMA channels" are referred as "DMA streams". + * + * @addtogroup STM32F1xx_DMA + * @{ + */ + +#ifndef _STM32_DMA_H_ +#define _STM32_DMA_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Total number of DMA streams. + * @note This is the total number of streams among all the DMA units. + */ +#if STM32_HAS_DMA2 || defined(__DOXYGEN__) +#define STM32_DMA_STREAMS 12 +#else +#define STM32_DMA_STREAMS 7 +#endif + +/** + * @brief Mask of the ISR bits passed to the DMA callback functions. + */ +#define STM32_DMA_ISR_MASK 0x0F + +/** + * @brief Returns the channel associated to the specified stream. + * + * @param[in] n the stream number (0...STM32_DMA_STREAMS-1) + * @param[in] c a stream/channel association word, one channel per + * nibble, not associated channels must be set to 0xF + * @return Always zero, in this platform there is no dynamic + * association between streams and channels. + */ +#define STM32_DMA_GETCHANNEL(n, c) 0 + +/** + * @brief Returns a DMA stream identifier mask. + * + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return A DMA stream identifier mask. + */ +#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ + (1 << STM32_DMA_STREAM_ID(dma, stream)) + +/** + * @brief Checks if a DMA stream unique identifier belongs to a mask. + * @param[in] id the stream numeric identifier + * @param[in] mask the stream numeric identifiers mask + * + * @retval The check result. + * @retval FALSE id does not belong to the mask. + * @retval TRUE id belongs to the mask. + */ +#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask))) + +/** + * @name DMA streams identifiers + * @{ + */ +/** + * @brief Returns an unique numeric identifier for a DMA stream. + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return An unique numeric stream identifier. + */ +#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1)) + +/** + * @brief Returns a pointer to a stm32_dma_stream_t structure. + * + * @param[in] id the stream numeric identifier + * @return A pointer to the stm32_dma_stream_t constant structure + * associated to the DMA stream. + */ +#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) + +#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0) +#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1) +#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2) +#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3) +#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4) +#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5) +#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6) +#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(7) +#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(8) +#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(9) +#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(10) +#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(11) +/** @} */ + +/** + * @name CR register constants common to all DMA types + * @{ + */ +#define STM32_DMA_CR_EN DMA_CCR1_EN +#define STM32_DMA_CR_TEIE DMA_CCR1_TEIE +#define STM32_DMA_CR_HTIE DMA_CCR1_HTIE +#define STM32_DMA_CR_TCIE DMA_CCR1_TCIE +#define STM32_DMA_CR_DIR_MASK (DMA_CCR1_DIR | DMA_CCR1_MEM2MEM) +#define STM32_DMA_CR_DIR_P2M 0 +#define STM32_DMA_CR_DIR_M2P DMA_CCR1_DIR +#define STM32_DMA_CR_DIR_M2M DMA_CCR1_MEM2MEM +#define STM32_DMA_CR_CIRC DMA_CCR1_CIRC +#define STM32_DMA_CR_PINC DMA_CCR1_PINC +#define STM32_DMA_CR_MINC DMA_CCR1_MINC +#define STM32_DMA_CR_PSIZE_MASK DMA_CCR1_PSIZE +#define STM32_DMA_CR_PSIZE_BYTE 0 +#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR1_PSIZE_0 +#define STM32_DMA_CR_PSIZE_WORD DMA_CCR1_PSIZE_1 +#define STM32_DMA_CR_MSIZE_MASK DMA_CCR1_MSIZE +#define STM32_DMA_CR_MSIZE_BYTE 0 +#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR1_MSIZE_0 +#define STM32_DMA_CR_MSIZE_WORD DMA_CCR1_MSIZE_1 +#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_MSIZE_MASK | \ + STM32_DMA_CR_MSIZE_MASK) +#define STM32_DMA_CR_PL_MASK DMA_CCR1_PL +#define STM32_DMA_CR_PL(n) ((n) << 12) +/** @} */ + +/** + * @name CR register constants only found in enhanced DMA + * @{ + */ +#define STM32_DMA_CR_DMEIE 0 /**< @brief Ignored by normal DMA. */ +#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */ +#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */ +/** @} */ + +/** + * @name Status flags passed to the ISR callbacks + * @{ + */ +#define STM32_DMA_ISR_FEIF 0 +#define STM32_DMA_ISR_DMEIF 0 +#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1 +#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1 +#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA stream descriptor structure. + */ +typedef struct { + DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ + volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ + uint8_t ishift; /**< @brief Bits offset in xIFCR + register. */ + uint8_t selfindex; /**< @brief Index to self in array. */ + uint8_t vector; /**< @brief Associated IRQ vector. */ +} stm32_dma_stream_t; + +/** + * @brief STM32 DMA ISR function type. + * + * @param[in] p parameter for the registered function + * @param[in] flags pre-shifted content of the ISR register, the bits + * are aligned to bit zero + */ +typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Associates a peripheral data register to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the CPAR register + * + * @special + */ +#define dmaStreamSetPeripheral(dmastp, addr) { \ + (dmastp)->channel->CPAR = (uint32_t)(addr); \ +} + +/** + * @brief Associates a memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the CMAR register + * + * @special + */ +#define dmaStreamSetMemory0(dmastp, addr) { \ + (dmastp)->channel->CMAR = (uint32_t)(addr); \ +} + +/** + * @brief Sets the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] size value to be written in the CNDTR register + * + * @special + */ +#define dmaStreamSetTransactionSize(dmastp, size) { \ + (dmastp)->channel->CNDTR = (uint32_t)(size); \ +} + +/** + * @brief Returns the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @return The number of transfers to be performed. + * + * @special + */ +#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR)) + +/** + * @brief Programs the stream mode settings. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register + * + * @special + */ +#define dmaStreamSetMode(dmastp, mode) { \ + (dmastp)->channel->CCR = (uint32_t)(mode); \ +} + +/** + * @brief DMA stream enable. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamEnable(dmastp) { \ + (dmastp)->channel->CCR |= STM32_DMA_CR_EN; \ +} + +/** + * @brief DMA stream disable. + * @details The function disables the specified stream and then clears any + * pending interrupt. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamDisable(dmastp) { \ + (dmastp)->channel->CCR &= ~STM32_DMA_CR_EN; \ + dmaStreamClearInterrupt(dmastp); \ +} + +/** + * @brief DMA stream interrupt sources clear. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamClearInterrupt(dmastp) { \ + *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ +} + +/** + * @brief Starts a memory to memory operation using the specified stream. + * @note The default transfer data mode is "byte to byte" but it can be + * changed by specifying extra options in the @p mode parameter. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register, this value + * is implicitly ORed with: + * - @p STM32_DMA_CR_MINC + * - @p STM32_DMA_CR_PINC + * - @p STM32_DMA_CR_DIR_M2M + * - @p STM32_DMA_CR_EN + * . + * @param[in] src source address + * @param[in] dst destination address + * @param[in] n number of data units to copy + */ +#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ + dmaStreamSetPeripheral(dmastp, src); \ + dmaStreamSetMemory0(dmastp, dst); \ + dmaStreamSetTransactionSize(dmastp, n); \ + dmaStreamSetMode(dmastp, (mode) | \ + STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ + STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ +} + +/** + * @brief Polled wait for DMA transfer end. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + */ +#define dmaWaitCompletion(dmastp) { \ + while ((dmastp)->channel->CNDTR > 0) \ + ; \ + dmaStreamDisable(dmastp); \ +} + +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void dmaInit(void); + bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param); + void dmaStreamRelease(const stm32_dma_stream_t *dmastp); +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_DMA_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F1xx/stm32_rcc.h b/Project/os/hal/platforms/STM32F1xx/stm32_rcc.h new file mode 100644 index 0000000..c329b0c --- /dev/null +++ b/Project/os/hal/platforms/STM32F1xx/stm32_rcc.h @@ -0,0 +1,942 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F1xx/stm32_rcc.h + * @brief RCC helper driver header. + * @note This file requires definitions from the ST header file + * @p stm32f10x.h. + * + * @addtogroup STM32F1xx_RCC + * @{ + */ + +#ifndef _STM32_RCC_ +#define _STM32_RCC_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic RCC operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the APB1 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB1(mask, lp) { \ + RCC->APB1ENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB1 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB1(mask, lp) { \ + RCC->APB1ENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * + * @api + */ +#define rccResetAPB1(mask) { \ + RCC->APB1RSTR |= (mask); \ + RCC->APB1RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the APB2 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB2(mask, lp) { \ + RCC->APB2ENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB2 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB2(mask, lp) { \ + RCC->APB2ENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * + * @api + */ +#define rccResetAPB2(mask) { \ + RCC->APB2RSTR |= (mask); \ + RCC->APB2RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB(mask, lp) { \ + RCC->AHBENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB(mask, lp) { \ + RCC->AHBENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define rccResetAHB(mask) { \ + RCC->AHBRSTR |= (mask); \ + RCC->AHBRSTR = 0; \ +} +/** @} */ + +/** + * @name ADC peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the ADC1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Disables the ADC1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Resets the ADC1 peripheral. + * + * @api + */ +#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) +/** @} */ + +/** + * @name Backup domain interface specific RCC operations + * @{ + */ +/** + * @brief Enables the BKP interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableBKPInterface(lp) rccEnableAPB1((RCC_APB1ENR_BKPEN), lp) + +/** + * @brief Disables BKP interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableBKPInterface(lp) rccDisableAPB1((RCC_APB1ENR_BKPEN), lp) + +/** + * @brief Resets the Backup Domain interface. + * + * @api + */ +#define rccResetBKPInterface() rccResetAPB1(RCC_APB1ENR_BKPRST) + +/** + * @brief Resets the entire Backup Domain. + * + * @api + */ +#define rccResetBKP() (RCC->BDCR |= RCC_BDCR_BDRST) +/** @} */ + +/** + * @name PWR interface specific RCC operations + * @{ + */ +/** + * @brief Enables the PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Disables PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Resets the PWR interface. + * + * @api + */ +#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST) +/** @} */ + +/** + * @name CAN peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the CAN1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp) + +/** + * @brief Disables the CAN1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp) + +/** + * @brief Resets the CAN1 peripheral. + * + * @api + */ +#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST) +/** @} */ + +/** + * @name DMA peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the DMA1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Disables the DMA1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Resets the DMA1 peripheral. + * @note Not supported in this family, does nothing. + * + * @api + */ +#define rccResetDMA1() + +/** + * @brief Enables the DMA2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp) + +/** + * @brief Disables the DMA2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHBENR_DMA2EN, lp) + +/** + * @brief Resets the DMA1 peripheral. + * @note Not supported in this family, does nothing. + * + * @api + */ +#define rccResetDMA2() +/** @} */ + +/** + * @name ETH peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the ETH peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableETH(lp) rccEnableAHB(RCC_AHBENR_ETHMACEN | \ + RCC_AHBENR_ETHMACTXEN | \ + RCC_AHBENR_ETHMACRXEN, lp) + +/** + * @brief Disables the ETH peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableETH(lp) rccDisableAHB(RCC_AHBENR_ETHMACEN | \ + RCC_AHBENR_ETHMACTXEN | \ + RCC_AHBENR_ETHMACRXEN, lp) + +/** + * @brief Resets the ETH peripheral. + * + * @api + */ +#define rccResetETH() rccResetAHB(RCC_AHBRSTR_ETHMACRST) +/** @} */ + +/** + * @name I2C peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Disables the I2C1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Resets the I2C1 peripheral. + * + * @api + */ +#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) + +/** + * @brief Enables the I2C2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Disables the I2C2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Resets the I2C2 peripheral. + * + * @api + */ +#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) +/** @} */ + +/** + * @name SDIO peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the SDIO peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSDIO(lp) rccEnableAHB(RCC_AHBENR_SDIOEN, lp) + +/** + * @brief Disables the SDIO peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSDIO(lp) rccDisableAHB(RCC_AHBENR_SDIOEN, lp) + +/** + * @brief Resets the SDIO peripheral. + * @note Not supported in this family, does nothing. + * + * @api + */ +#define rccResetSDIO() +/** @} */ + +/** + * @name SPI peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Disables the SPI1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Resets the SPI1 peripheral. + * + * @api + */ +#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) + +/** + * @brief Enables the SPI2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Disables the SPI2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Resets the SPI2 peripheral. + * + * @api + */ +#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) + +/** + * @brief Enables the SPI3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp) + +/** + * @brief Disables the SPI3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp) + +/** + * @brief Resets the SPI3 peripheral. + * + * @api + */ +#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST) +/** @} */ + +/** + * @name TIM peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Disables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Resets the TIM1 peripheral. + * + * @api + */ +#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST) + +/** + * @brief Enables the TIM2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Disables the TIM2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Resets the TIM2 peripheral. + * + * @api + */ +#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) + +/** + * @brief Enables the TIM3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Disables the TIM3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Resets the TIM3 peripheral. + * + * @api + */ +#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) + +/** + * @brief Enables the TIM4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Disables the TIM4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Resets the TIM4 peripheral. + * + * @api + */ +#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST) + +/** + * @brief Enables the TIM5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp) + +/** + * @brief Disables the TIM5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp) + +/** + * @brief Resets the TIM5 peripheral. + * + * @api + */ +#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST) + +/** + * @brief Enables the TIM8 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp) + +/** + * @brief Disables the TIM8 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp) + +/** + * @brief Resets the TIM8 peripheral. + * + * @api + */ +#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST) +/** @} */ + +/** + * @name USART/UART peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the USART1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Disables the USART1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) + +/** + * @brief Enables the USART2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Disables the USART2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Resets the USART2 peripheral. + * + * @api + */ +#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) + +/** + * @brief Enables the USART3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Disables the USART3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Resets the USART3 peripheral. + * + * @api + */ +#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST) + +/** + * @brief Enables the UART4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp) + +/** + * @brief Disables the UART4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp) + +/** + * @brief Resets the UART4 peripheral. + * + * @api + */ +#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST) + +/** + * @brief Enables the UART5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp) + +/** + * @brief Disables the UART5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp) + +/** + * @brief Resets the UART5 peripheral. + * + * @api + */ +#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST) +/** @} */ + +/** + * @name USB peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the USB peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp) + +/** + * @brief Disables the USB peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp) + +/** + * @brief Resets the USB peripheral. + * + * @api + */ +#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_RCC_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F1xx/stm32f10x.h b/Project/os/hal/platforms/STM32F1xx/stm32f10x.h new file mode 100644 index 0000000..6697b96 --- /dev/null +++ b/Project/os/hal/platforms/STM32F1xx/stm32f10x.h @@ -0,0 +1,8357 @@ +/** + ****************************************************************************** + * @file stm32f10x.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F10x Connectivity line, + * High density, High density value line, Medium density, + * Medium density Value line, Low density, Low density Value line + * and XL-density devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral�s drivers in application code(i.e. + * code will be based on direct access to peripheral�s registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral�s registers hardware + * + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x + * @{ + */ + +#ifndef __STM32F10x_H +#define __STM32F10x_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) + /* CHIBIOS FIX */ +#include "board.h" + /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ + /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ + /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ + /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ + /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ + /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */ + /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */ + /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ +#endif +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + + - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers + where the Flash memory density ranges between 16 and 32 Kbytes. + - Low-density value line devices are STM32F100xx microcontrollers where the Flash + memory density ranges between 16 and 32 Kbytes. + - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers + where the Flash memory density ranges between 64 and 128 Kbytes. + - Medium-density value line devices are STM32F100xx microcontrollers where the + Flash memory density ranges between 64 and 128 Kbytes. + - High-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 256 and 512 Kbytes. + - High-density value line devices are STM32F100xx microcontrollers where the + Flash memory density ranges between 256 and 512 Kbytes. + - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 512 and 1024 Kbytes. + - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. + */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) + #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)" +#endif + +#if !defined USE_STDPERIPH_DRIVER +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined HSE_VALUE + #ifdef STM32F10X_CL + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ + #else + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #endif /* STM32F10X_CL */ +#endif /* HSE_VALUE */ + + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ + +#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ + +/** + * @brief STM32F10x Standard Peripheral Library version number + */ +#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F10X_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#ifdef STM32F10X_XL + #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ +#else + #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ +#endif /* STM32F10X_XL */ +#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @brief STM32F10x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + +#ifdef STM32F10X_LD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + USB_FS_WKUP_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +#endif /* STM32F10X_LD */ + +#ifdef STM32F10X_LD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55 /*!< TIM7 Interrupt */ +#endif /* STM32F10X_LD_VL */ + +#ifdef STM32F10X_MD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + USB_FS_WKUP_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +#endif /* STM32F10X_MD */ + +#ifdef STM32F10X_MD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55 /*!< TIM7 Interrupt */ +#endif /* STM32F10X_MD_VL */ + +#ifdef STM32F10X_HD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + USB_FS_WKUP_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ +#endif /* STM32F10X_HD */ + +#ifdef STM32F10X_HD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ + TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ + TIM14_IRQn = 45, /*!< TIM14 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ + DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is + mapped at position 60 only if the MISC_REMAP bit in + the AFIO_MAPR2 register is set) */ +#endif /* STM32F10X_HD_VL */ + +#ifdef STM32F10X_XL + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + USB_FS_WKUP_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ +#endif /* STM32F10X_XL */ + +#ifdef STM32F10X_CL + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ +#endif /* STM32F10X_CL */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +/* CHIBIOS FIX */ +/*#include "system_stm32f10x.h"*/ +#include + +/** @addtogroup Exported_types + * @{ + */ + +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT +#define HSE_Value HSE_VALUE +#define HSI_Value HSI_VALUE +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMPR1; + __IO uint32_t SMPR2; + __IO uint32_t JOFR1; + __IO uint32_t JOFR2; + __IO uint32_t JOFR3; + __IO uint32_t JOFR4; + __IO uint32_t HTR; + __IO uint32_t LTR; + __IO uint32_t SQR1; + __IO uint32_t SQR2; + __IO uint32_t SQR3; + __IO uint32_t JSQR; + __IO uint32_t JDR1; + __IO uint32_t JDR2; + __IO uint32_t JDR3; + __IO uint32_t JDR4; + __IO uint32_t DR; +} ADC_TypeDef; + +/** + * @brief Backup Registers + */ + +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DR1; + uint16_t RESERVED1; + __IO uint16_t DR2; + uint16_t RESERVED2; + __IO uint16_t DR3; + uint16_t RESERVED3; + __IO uint16_t DR4; + uint16_t RESERVED4; + __IO uint16_t DR5; + uint16_t RESERVED5; + __IO uint16_t DR6; + uint16_t RESERVED6; + __IO uint16_t DR7; + uint16_t RESERVED7; + __IO uint16_t DR8; + uint16_t RESERVED8; + __IO uint16_t DR9; + uint16_t RESERVED9; + __IO uint16_t DR10; + uint16_t RESERVED10; + __IO uint16_t RTCCR; + uint16_t RESERVED11; + __IO uint16_t CR; + uint16_t RESERVED12; + __IO uint16_t CSR; + uint16_t RESERVED13[5]; + __IO uint16_t DR11; + uint16_t RESERVED14; + __IO uint16_t DR12; + uint16_t RESERVED15; + __IO uint16_t DR13; + uint16_t RESERVED16; + __IO uint16_t DR14; + uint16_t RESERVED17; + __IO uint16_t DR15; + uint16_t RESERVED18; + __IO uint16_t DR16; + uint16_t RESERVED19; + __IO uint16_t DR17; + uint16_t RESERVED20; + __IO uint16_t DR18; + uint16_t RESERVED21; + __IO uint16_t DR19; + uint16_t RESERVED22; + __IO uint16_t DR20; + uint16_t RESERVED23; + __IO uint16_t DR21; + uint16_t RESERVED24; + __IO uint16_t DR22; + uint16_t RESERVED25; + __IO uint16_t DR23; + uint16_t RESERVED26; + __IO uint16_t DR24; + uint16_t RESERVED27; + __IO uint16_t DR25; + uint16_t RESERVED28; + __IO uint16_t DR26; + uint16_t RESERVED29; + __IO uint16_t DR27; + uint16_t RESERVED30; + __IO uint16_t DR28; + uint16_t RESERVED31; + __IO uint16_t DR29; + uint16_t RESERVED32; + __IO uint16_t DR30; + uint16_t RESERVED33; + __IO uint16_t DR31; + uint16_t RESERVED34; + __IO uint16_t DR32; + uint16_t RESERVED35; + __IO uint16_t DR33; + uint16_t RESERVED36; + __IO uint16_t DR34; + uint16_t RESERVED37; + __IO uint16_t DR35; + uint16_t RESERVED38; + __IO uint16_t DR36; + uint16_t RESERVED39; + __IO uint16_t DR37; + uint16_t RESERVED40; + __IO uint16_t DR38; + uint16_t RESERVED41; + __IO uint16_t DR39; + uint16_t RESERVED42; + __IO uint16_t DR40; + uint16_t RESERVED43; + __IO uint16_t DR41; + uint16_t RESERVED44; + __IO uint16_t DR42; + uint16_t RESERVED45; +} BKP_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; + __IO uint32_t TDTR; + __IO uint32_t TDLR; + __IO uint32_t TDHR; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; + __IO uint32_t RDTR; + __IO uint32_t RDLR; + __IO uint32_t RDHR; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; + __IO uint32_t MSR; + __IO uint32_t TSR; + __IO uint32_t RF0R; + __IO uint32_t RF1R; + __IO uint32_t IER; + __IO uint32_t ESR; + __IO uint32_t BTR; + uint32_t RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FMR; + __IO uint32_t FM1R; + uint32_t RESERVED2; + __IO uint32_t FS1R; + uint32_t RESERVED3; + __IO uint32_t FFA1R; + uint32_t RESERVED4; + __IO uint32_t FA1R; + uint32_t RESERVED5[8]; +#ifndef STM32F10X_CL + CAN_FilterRegister_TypeDef sFilterRegister[14]; +#else + CAN_FilterRegister_TypeDef sFilterRegister[28]; +#endif /* STM32F10X_CL */ +} CAN_TypeDef; + +/** + * @brief Consumer Electronics Control (CEC) + */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t OAR; + __IO uint32_t PRES; + __IO uint32_t ESR; + __IO uint32_t CSR; + __IO uint32_t TXD; + __IO uint32_t RXD; +} CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; + __IO uint8_t IDR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CR; +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SWTRIGR; + __IO uint32_t DHR12R1; + __IO uint32_t DHR12L1; + __IO uint32_t DHR8R1; + __IO uint32_t DHR12R2; + __IO uint32_t DHR12L2; + __IO uint32_t DHR8R2; + __IO uint32_t DHR12RD; + __IO uint32_t DHR12LD; + __IO uint32_t DHR8RD; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + __IO uint32_t SR; +#endif +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; + __IO uint32_t CR; +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t CNDTR; + __IO uint32_t CPAR; + __IO uint32_t CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t IFCR; +} DMA_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + uint32_t RESERVED8[567]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + uint32_t RESERVED9[9]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; + __IO uint32_t KEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t CR; + __IO uint32_t AR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WRPR; +#ifdef STM32F10X_XL + uint32_t RESERVED1[8]; + __IO uint32_t KEYR2; + uint32_t RESERVED2; + __IO uint32_t SR2; + __IO uint32_t CR2; + __IO uint32_t AR2; +#endif /* STM32F10X_XL */ +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint16_t RDP; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRP0; + __IO uint16_t WRP1; + __IO uint16_t WRP2; + __IO uint16_t WRP3; +} OB_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; + __IO uint32_t SR2; + __IO uint32_t PMEM2; + __IO uint32_t PATT2; + uint32_t RESERVED0; + __IO uint32_t ECCR2; +} FSMC_Bank2_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; + __IO uint32_t SR3; + __IO uint32_t PMEM3; + __IO uint32_t PATT3; + uint32_t RESERVED0; + __IO uint32_t ECCR3; +} FSMC_Bank3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; + __IO uint32_t SR4; + __IO uint32_t PMEM4; + __IO uint32_t PATT4; + __IO uint32_t PIO4; +} FSMC_Bank4_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t CRL; + __IO uint32_t CRH; + __IO uint32_t IDR; + __IO uint32_t ODR; + __IO uint32_t BSRR; + __IO uint32_t BRR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/** + * @brief Alternate Function I/O + */ + +typedef struct +{ + __IO uint32_t EVCR; + __IO uint32_t MAPR; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t MAPR2; +} AFIO_TypeDef; +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t OAR1; + uint16_t RESERVED2; + __IO uint16_t OAR2; + uint16_t RESERVED3; + __IO uint16_t DR; + uint16_t RESERVED4; + __IO uint16_t SR1; + uint16_t RESERVED5; + __IO uint16_t SR2; + uint16_t RESERVED6; + __IO uint16_t CCR; + uint16_t RESERVED7; + __IO uint16_t TRISE; + uint16_t RESERVED8; +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; + __IO uint32_t PR; + __IO uint32_t RLR; + __IO uint32_t SR; +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t APB2RSTR; + __IO uint32_t APB1RSTR; + __IO uint32_t AHBENR; + __IO uint32_t APB2ENR; + __IO uint32_t APB1ENR; + __IO uint32_t BDCR; + __IO uint32_t CSR; + +#ifdef STM32F10X_CL + __IO uint32_t AHBRSTR; + __IO uint32_t CFGR2; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + uint32_t RESERVED0; + __IO uint32_t CFGR2; +#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint16_t CRH; + uint16_t RESERVED0; + __IO uint16_t CRL; + uint16_t RESERVED1; + __IO uint16_t PRLH; + uint16_t RESERVED2; + __IO uint16_t PRLL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRH; + uint16_t RESERVED8; + __IO uint16_t ALRL; + uint16_t RESERVED9; +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; + __IO uint32_t CLKCR; + __IO uint32_t ARG; + __IO uint32_t CMD; + __I uint32_t RESPCMD; + __I uint32_t RESP1; + __I uint32_t RESP2; + __I uint32_t RESP3; + __I uint32_t RESP4; + __IO uint32_t DTIMER; + __IO uint32_t DLEN; + __IO uint32_t DCTRL; + __I uint32_t DCOUNT; + __I uint32_t STA; + __IO uint32_t ICR; + __IO uint32_t MASK; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCNT; + uint32_t RESERVED1[13]; + __IO uint32_t FIFO; +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SR; + uint16_t RESERVED2; + __IO uint16_t DR; + uint16_t RESERVED3; + __IO uint16_t CRCPR; + uint16_t RESERVED4; + __IO uint16_t RXCRCR; + uint16_t RESERVED5; + __IO uint16_t TXCRCR; + uint16_t RESERVED6; + __IO uint16_t I2SCFGR; + uint16_t RESERVED7; + __IO uint16_t I2SPR; + uint16_t RESERVED8; +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SMCR; + uint16_t RESERVED2; + __IO uint16_t DIER; + uint16_t RESERVED3; + __IO uint16_t SR; + uint16_t RESERVED4; + __IO uint16_t EGR; + uint16_t RESERVED5; + __IO uint16_t CCMR1; + uint16_t RESERVED6; + __IO uint16_t CCMR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ARR; + uint16_t RESERVED11; + __IO uint16_t RCR; + uint16_t RESERVED12; + __IO uint16_t CCR1; + uint16_t RESERVED13; + __IO uint16_t CCR2; + uint16_t RESERVED14; + __IO uint16_t CCR3; + uint16_t RESERVED15; + __IO uint16_t CCR4; + uint16_t RESERVED16; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DCR; + uint16_t RESERVED18; + __IO uint16_t DMAR; + uint16_t RESERVED19; +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; + uint16_t RESERVED0; + __IO uint16_t DR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CR1; + uint16_t RESERVED3; + __IO uint16_t CR2; + uint16_t RESERVED4; + __IO uint16_t CR3; + uint16_t RESERVED5; + __IO uint16_t GTPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFR; + __IO uint32_t SR; +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define CEC_BASE (APB1PERIPH_BASE + 0x7800) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) +#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) +#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) + +#define SDIO_BASE (PERIPH_BASE + 0x18000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ + +#define ETH_BASE (AHBPERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ + +#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define BKP ((BKP_TypeDef *) BKP_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) +#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ +#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ +#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ +#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ +#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ + +/*!< PVD level configuration */ +#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ +#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ +#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ +#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ +#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ +#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ +#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ +#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ + +#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR11 register *******************/ +#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR12 register *******************/ +#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR13 register *******************/ +#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR14 register *******************/ +#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR15 register *******************/ +#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR16 register *******************/ +#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR17 register *******************/ +#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_DR18 register ********************/ +#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR19 register *******************/ +#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR20 register *******************/ +#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR21 register *******************/ +#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR22 register *******************/ +#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR23 register *******************/ +#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR24 register *******************/ +#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR25 register *******************/ +#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR26 register *******************/ +#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR27 register *******************/ +#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR28 register *******************/ +#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR29 register *******************/ +#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR30 register *******************/ +#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR31 register *******************/ +#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR32 register *******************/ +#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR33 register *******************/ +#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR34 register *******************/ +#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR35 register *******************/ +#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR36 register *******************/ +#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR37 register *******************/ +#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR38 register *******************/ +#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR39 register *******************/ +#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR40 register *******************/ +#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR41 register *******************/ +#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR42 register *******************/ +#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ +#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ +#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ +#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ +#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ +#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ +#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ +#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ +#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ +#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ +#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ + +#ifdef STM32F10X_CL + #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ + #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ + #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ + #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ +#endif /* STM32F10X_CL */ + +/******************* Bit definition for RCC_CFGR register *******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ + +/*!< ADCPPRE configuration */ +#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ + +#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ + +#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ +#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ + +#ifdef STM32F10X_CL + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ + #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ + + #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ + #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ + #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ + #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#else + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#endif /* STM32F10X_CL */ + +/*!<****************** Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ + +#ifdef STM32F10X_CL + #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ + #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ + #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ + #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ + #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ + #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ +#endif /* STM32F10X_CL */ + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ +#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ +#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ +#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ +#endif + +#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ +#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ +#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ +#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ +#endif + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ + #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ + #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ + #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ + #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ +#endif + +#ifdef STM32F10X_XL + #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ + #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ + #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ +#endif /* STM32F10X_XL */ + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ +#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ +#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ +#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ +#endif + +#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ +#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ + #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ + #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ + #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) + #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) + #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ + #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ + #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ + #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ + #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ + #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ + #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ +#endif + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ + #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ + #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ + #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ + #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ + #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ + #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ + #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ + #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ + #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ +#endif + +#ifdef STM32F10X_CL + #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ +#endif /* STM32F10X_CL */ + +#ifdef STM32F10X_XL + #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ + #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ + #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ +#endif /* STM32F10X_XL */ + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ +#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ +#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ + +/* CHIBIOS FIX */ +//#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_XL) + #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ + #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ +#endif + +#ifdef STM32F10X_CL + #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ + #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ + #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ + #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ +#endif /* STM32F10X_CL */ + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ +#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ +#endif + +#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ +#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ +#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ +#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ +#endif + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ + #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ + #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ + #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ + #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ +#endif + +#ifdef STM32F10X_XL + #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ + #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ + #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ +#endif + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ +#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ +#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ +#endif + +#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ +#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ + #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ + #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ + #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +/* CHIBIOS FIX */ +//#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) +#if defined (STM32F10X_XL) || defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) + #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ +#endif + +/* CHIBIOS FIX */ +//#if defined (STM32F10X_HD) || defined (STM32F10X_CL) +#if defined (STM32F10X_XL) || defined (STM32F10X_HD) || defined (STM32F10X_CL) + #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ + #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ + #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ + #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ + #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ + #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ + #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ +#endif + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ + #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ + #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ + #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ +#endif + +#ifdef STM32F10X_HD_VL + #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ + #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ + #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ + #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ + #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ + #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ + #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ +#endif /* STM32F10X_HD_VL */ + +#ifdef STM32F10X_CL + #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ +#endif /* STM32F10X_CL */ + +#ifdef STM32F10X_XL + #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ + #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ + #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ +#endif /* STM32F10X_XL */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< RTC congiguration */ +#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ +#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ +#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ + +#ifdef STM32F10X_CL +/******************* Bit definition for RCC_AHBRSTR register ****************/ + #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ + #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ + +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ + +/*!< PREDIV2 configuration */ + #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ + #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ + #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ + +/*!< PLL2MUL configuration */ + #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ + #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ + #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + + #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ + #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ + #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ + #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ + #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ + #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ + #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ + #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ + #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ + +/*!< PLL3MUL configuration */ + #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ + #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ + #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ + + #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ + #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ + #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ + #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ + #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ + #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ + #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ + #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ + #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ + + #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ + #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ + #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ + #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ + #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ +#endif + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function I/O */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ +#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ +#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ +#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ +#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ +#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ +#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ +#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ +#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ +#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ +#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ +#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ +#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ +#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ +#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ +#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ +#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ +#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ +#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ +#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ +#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ +#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ +#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ +#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ +#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ +#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ +#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ +#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ +#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ +#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ +#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ +#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ +#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ +#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ +#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ +#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ +#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ +#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ +#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ +#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ +#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ +#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ +#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ +#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ +#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ +#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ + +#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ +#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ +#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ +#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ +#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ +#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ +#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ +#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ +#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ +#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ +#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ +#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ +#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ +#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ +#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ +#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ +#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ +#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ +#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ +#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ +#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ +#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ +#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ +#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ +#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ +#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ +#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ +#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ +#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ +#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ +#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for AFIO_EVCR register *******************/ +#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ +#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ +#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ + +/*!< PIN configuration */ +#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ +#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ +#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ +#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ +#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ +#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ +#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ +#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ +#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ +#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ +#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ +#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ +#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ +#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ +#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ +#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ + +#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ +#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ +#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ +#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ + +/*!< PORT configuration */ +#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ +#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ +#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ +#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ +#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ + +#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ + +/****************** Bit definition for AFIO_MAPR register *******************/ +#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ +#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ +#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ + +#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +/* USART3_REMAP configuration */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +/*!< TIM1_REMAP configuration */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< TIM2_REMAP configuration */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +/*!< TIM3_REMAP configuration */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ + +/*!< CAN_REMAP configuration */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ + +/*!< SWJ_CFG configuration */ +#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ + +#ifdef STM32F10X_CL +/*!< ETH_REMAP configuration */ + #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ + +/*!< CAN2_REMAP configuration */ + #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ + +/*!< MII_RMII_SEL configuration */ + #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ + +/*!< SPI3_REMAP configuration */ + #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ + +/*!< TIM2ITR1_IREMAP configuration */ + #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ + +/*!< PTP_PPS_REMAP configuration */ + #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ +#endif + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ + +/*!< EXTI1 configuration */ +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ + +/*!< EXTI2 configuration */ +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ + +/*!< EXTI3 configuration */ +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ + +/* EXTI5 configuration */ +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ + +/*!< EXTI6 configuration */ +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ + +/*!< EXTI7 configuration */ +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ + +/*!< EXTI9 configuration */ +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ + +/*!< EXTI10 configuration */ +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ + +/*!< EXTI11 configuration */ +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ + +/* EXTI13 configuration */ +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ + +/*!< EXTI14 configuration */ +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ + +/*!< EXTI15 configuration */ +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/****************** Bit definition for AFIO_MAPR2 register ******************/ +#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ +#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ +#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ +#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ +#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ +#endif + +#ifdef STM32F10X_HD_VL +#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ +#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ +#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ +#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */ +#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */ +#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */ +#endif + +#ifdef STM32F10X_XL +/****************** Bit definition for AFIO_MAPR2 register ******************/ +#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ +#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ +#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ +#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ +#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ +#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ +#endif + +/******************************************************************************/ +/* */ +/* SystemTick */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SysTick_CTRL register *****************/ +#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ +#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ +#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ + +/***************** Bit definition for SysTick_LOAD register *****************/ +#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ + +/***************** Bit definition for SysTick_VAL register ******************/ +#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ + +/***************** Bit definition for SysTick_CALIB register ****************/ +#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ + +/******************************************************************************/ +/* */ +/* Nested Vectored Interrupt Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for NVIC_ISER register *******************/ +#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICER register *******************/ +#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ISPR register *******************/ +#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICPR register *******************/ +#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_IABR register *******************/ +#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ +#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_PRI0 register *******************/ +#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ + +/****************** Bit definition for NVIC_PRI1 register *******************/ +#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ + +/****************** Bit definition for NVIC_PRI2 register *******************/ +#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ + +/****************** Bit definition for NVIC_PRI3 register *******************/ +#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ + +/****************** Bit definition for NVIC_PRI4 register *******************/ +#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ + +/****************** Bit definition for NVIC_PRI5 register *******************/ +#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ + +/****************** Bit definition for NVIC_PRI6 register *******************/ +#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ + +/****************** Bit definition for NVIC_PRI7 register *******************/ +#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ + +/****************** Bit definition for SCB_CPUID register *******************/ +#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ +#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ + +/******************* Bit definition for SCB_ICSR register *******************/ +#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ +#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ +#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ + +/******************* Bit definition for SCB_VTOR register *******************/ +#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ +#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ + +/*!<***************** Bit definition for SCB_AIRCR register *******************/ +#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ +#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ + +#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ +#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +/* prority group configuration */ +#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ +#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ + +#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ +#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ + +/******************* Bit definition for SCB_SCR register ********************/ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ + +/******************** Bit definition for SCB_CCR register *******************/ +#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ +#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ +#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ +#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ +#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ +#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + +/******************* Bit definition for SCB_SHPR register ********************/ +#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + +/****************** Bit definition for SCB_SHCSR register *******************/ +#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ +#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ +#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ +#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ +#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ +#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ +#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ +#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ +#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ +#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ +#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ +#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ +#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ +#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ + +/******************* Bit definition for SCB_CFSR register *******************/ +/*!< MFSR */ +#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ +#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ +#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ +#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ +#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ +/*!< BFSR */ +#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ +#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ +#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ +#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ +#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ +#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ +/*!< UFSR */ +#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ +#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ +#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ +#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ +#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ +#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ + +/******************* Bit definition for SCB_HFSR register *******************/ +#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ +#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ +#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ + +/******************* Bit definition for SCB_DFSR register *******************/ +#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ +#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ +#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ + +/******************* Bit definition for SCB_MMFAR register ******************/ +#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ + +/******************* Bit definition for SCB_BFAR register *******************/ +#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ + +/******************* Bit definition for SCB_afsr register *******************/ +#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ +#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ +#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ +#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ +#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ +#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ +#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ +#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ +#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ +#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ +#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ +#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ +#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ +#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ +#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ +#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ +#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ +#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ +#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ +#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ +#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR1 register *******************/ +#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ +#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR2 register *******************/ +#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR3 register *******************/ +#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/*!<****************** Bit definition for DMA_CCR4 register *******************/ +#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CCR5 register *******************/ +#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/******************* Bit definition for DMA_CCR6 register *******************/ +#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR7 register *******************/ +#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNDTR1 register ******************/ +#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR2 register ******************/ +#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR3 register ******************/ +#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR4 register ******************/ +#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR5 register ******************/ +#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR6 register ******************/ +#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR7 register ******************/ +#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR1 register *******************/ +#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR2 register *******************/ +#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR3 register *******************/ +#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR4 register *******************/ +#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR5 register *******************/ +#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR6 register *******************/ +#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR7 register *******************/ +#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR1 register *******************/ +#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR2 register *******************/ +#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR3 register *******************/ +#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + + +/****************** Bit definition for DMA_CMAR4 register *******************/ +#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR5 register *******************/ +#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR6 register *******************/ +#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR7 register *******************/ +#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint8_t)0x01) /*!< Analog watchdog flag */ +#define ADC_SR_EOC ((uint8_t)0x02) /*!< End of conversion */ +#define ADC_SR_JEOC ((uint8_t)0x04) /*!< Injected channel end of conversion */ +#define ADC_SR_JSTRT ((uint8_t)0x08) /*!< Injected channel Start flag */ +#define ADC_SR_STRT ((uint8_t)0x10) /*!< Regular channel Start flag */ + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ +#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ +#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ +#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ +#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ + +#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ + +#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ + + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ +#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ +#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */ +#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */ +#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ +#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ + +#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ + +#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ +#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ +#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ +#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */ + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */ + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ +#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ +#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ +#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ +#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ +#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ + +#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ +#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ +#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ +#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ + +#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ +#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ +#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ + +#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */ + +/***************** Bit definition for DAC_DHR12R1 register ******************/ +#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L1 register ******************/ +#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R1 register ******************/ +#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12R2 register ******************/ +#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L2 register ******************/ +#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R2 register ******************/ +#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12RD register ******************/ +#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12LD register ******************/ +#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8RD register ******************/ +#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */ + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */ + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */ + +/******************** Bit definition for DAC_SR register ********************/ +#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */ + +/******************************************************************************/ +/* */ +/* CEC */ +/* */ +/******************************************************************************/ +/******************** Bit definition for CEC_CFGR register ******************/ +#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ +#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */ +#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */ +#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */ + +/******************** Bit definition for CEC_OAR register ******************/ +#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */ +#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */ + +/******************** Bit definition for CEC_PRES register ******************/ +#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */ + +/******************** Bit definition for CEC_ESR register ******************/ +#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */ +#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */ +#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */ +#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */ +#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */ +#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */ +#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finished Error */ + +/******************** Bit definition for CEC_CSR register ******************/ +#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */ +#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */ +#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */ +#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */ +#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */ +#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */ +#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */ +#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */ + +/******************** Bit definition for CEC_TXD register ******************/ +#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */ + +/******************** Bit definition for CEC_RXD register ******************/ +#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN ((uint16_t)0x0001) /*!< Counter enable */ +#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!< Update disable */ +#define TIM_CR1_URS ((uint16_t)0x0004) /*!< Update request source */ +#define TIM_CR1_OPM ((uint16_t)0x0008) /*!< One pulse mode */ +#define TIM_CR1_DIR ((uint16_t)0x0010) /*!< Direction */ + +#define TIM_CR1_CMS ((uint16_t)0x0060) /*!< CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!< Bit 0 */ +#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!< Bit 1 */ + +#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!< Auto-reload preload enable */ + +#define TIM_CR1_CKD ((uint16_t)0x0300) /*!< CKD[1:0] bits (clock division) */ +#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +/******************* Bit definition for TIM_CR2 register ********************/ +#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!< Capture/Compare Preloaded Control */ +#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!< Capture/Compare Control Update Selection */ +#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!< Capture/Compare DMA Selection */ + +#define TIM_CR2_MMS ((uint16_t)0x0070) /*!< MMS[2:0] bits (Master Mode Selection) */ +#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!< TI1 Selection */ +#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!< Output Idle state 1 (OC1 output) */ +#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!< Output Idle state 1 (OC1N output) */ +#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!< Output Idle state 2 (OC2 output) */ +#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!< Output Idle state 2 (OC2N output) */ +#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!< Output Idle state 3 (OC3 output) */ +#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!< Output Idle state 3 (OC3N output) */ +#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!< Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCR register *******************/ +#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!< Bit 2 */ + +#define TIM_SMCR_TS ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */ +#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!< Master/slave mode */ + +#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */ +#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!< Bit 1 */ +#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!< Bit 2 */ +#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!< Bit 3 */ + +#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!< External clock enable */ +#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!< External trigger polarity */ + +/******************* Bit definition for TIM_DIER register *******************/ +#define TIM_DIER_UIE ((uint16_t)0x0001) /*!< Update interrupt enable */ +#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */ +#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */ +#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */ +#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */ +#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!< COM interrupt enable */ +#define TIM_DIER_TIE ((uint16_t)0x0040) /*!< Trigger interrupt enable */ +#define TIM_DIER_BIE ((uint16_t)0x0080) /*!< Break interrupt enable */ +#define TIM_DIER_UDE ((uint16_t)0x0100) /*!< Update DMA request enable */ +#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */ +#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */ +#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */ +#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */ +#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!< COM DMA request enable */ +#define TIM_DIER_TDE ((uint16_t)0x4000) /*!< Trigger DMA request enable */ + +/******************** Bit definition for TIM_SR register ********************/ +#define TIM_SR_UIF ((uint16_t)0x0001) /*!< Update interrupt Flag */ +#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt Flag */ +#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt Flag */ +#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt Flag */ +#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt Flag */ +#define TIM_SR_COMIF ((uint16_t)0x0020) /*!< COM interrupt Flag */ +#define TIM_SR_TIF ((uint16_t)0x0040) /*!< Trigger interrupt Flag */ +#define TIM_SR_BIF ((uint16_t)0x0080) /*!< Break interrupt Flag */ +#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!< Capture/Compare 1 Overcapture Flag */ +#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!< Capture/Compare 2 Overcapture Flag */ +#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!< Capture/Compare 3 Overcapture Flag */ +#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!< Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_EGR register ********************/ +#define TIM_EGR_UG ((uint8_t)0x01) /*!< Update Generation */ +#define TIM_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */ +#define TIM_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */ +#define TIM_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */ +#define TIM_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */ +#define TIM_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */ +#define TIM_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation */ +#define TIM_EGR_BG ((uint8_t)0x80) /*!< Break Generation */ + +/****************** Bit definition for TIM_CCMR1 register *******************/ +#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!< Bit 1 */ + +#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */ +#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */ + +#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */ + +#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */ +#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */ + +#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ +#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ + +#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */ +#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */ + +/****************** Bit definition for TIM_CCMR2 register *******************/ +#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!< Bit 1 */ + +#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */ +#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */ + +#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */ + +#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */ +#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */ + +#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ +#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ + +#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */ +#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!< Capture/Compare 1 output enable */ +#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!< Capture/Compare 1 output Polarity */ +#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!< Capture/Compare 1 Complementary output enable */ +#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!< Capture/Compare 1 Complementary output Polarity */ +#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!< Capture/Compare 2 output enable */ +#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!< Capture/Compare 2 output Polarity */ +#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!< Capture/Compare 2 Complementary output enable */ +#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!< Capture/Compare 2 Complementary output Polarity */ +#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!< Capture/Compare 3 output enable */ +#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!< Capture/Compare 3 output Polarity */ +#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!< Capture/Compare 3 Complementary output enable */ +#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!< Capture/Compare 3 Complementary output Polarity */ +#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!< Capture/Compare 4 output enable */ +#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!< Capture/Compare 4 output Polarity */ +#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!< Capture/Compare 4 Complementary output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */ + +/******************* Bit definition for TIM_ARR register ********************/ +#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */ + +/******************* Bit definition for TIM_RCR register ********************/ +#define TIM_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value */ + +/******************* Bit definition for TIM_CCR1 register *******************/ +#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CCR2 register *******************/ +#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CCR3 register *******************/ +#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CCR4 register *******************/ +#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!< Bit 7 */ + +#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */ +#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */ +#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */ +#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!< Break enable */ +#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!< Break Polarity */ +#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!< Automatic Output enable */ +#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!< Main Output enable */ + +/******************* Bit definition for TIM_DCR register ********************/ +#define TIM_DCR_DBA ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */ +#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!< Bit 4 */ + +#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!< Bit 1 */ +#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!< Bit 2 */ +#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!< Bit 3 */ +#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!< Bit 4 */ + +/******************* Bit definition for TIM_DMAR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */ + +/******************************************************************************/ +/* */ +/* Real-Time Clock */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CRH register ********************/ +#define RTC_CRH_SECIE ((uint8_t)0x01) /*!< Second Interrupt Enable */ +#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!< Alarm Interrupt Enable */ +#define RTC_CRH_OWIE ((uint8_t)0x04) /*!< OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CRL register ********************/ +#define RTC_CRL_SECF ((uint8_t)0x01) /*!< Second Flag */ +#define RTC_CRL_ALRF ((uint8_t)0x02) /*!< Alarm Flag */ +#define RTC_CRL_OWF ((uint8_t)0x04) /*!< OverfloW Flag */ +#define RTC_CRL_RSF ((uint8_t)0x08) /*!< Registers Synchronized Flag */ +#define RTC_CRL_CNF ((uint8_t)0x10) /*!< Configuration Flag */ +#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!< RTC operation OFF */ + +/******************* Bit definition for RTC_PRLH register *******************/ +#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!< RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PRLL register *******************/ +#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!< RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!< RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!< RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Low */ + +/******************* Bit definition for RTC_ALRH register *******************/ +#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm High */ + +/******************* Bit definition for RTC_ALRL register *******************/ +#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm Low */ + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PR register ********************/ +#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ + +/******************* Bit definition for IWDG_RLR register *******************/ +#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ + +/******************* Bit definition for IWDG_SR register ********************/ +#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ +#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ + +/******************************************************************************/ +/* */ +/* Window WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CR register ********************/ +#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */ +#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */ +#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */ +#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */ +#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */ +#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */ +#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */ + +#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */ + +/******************* Bit definition for WWDG_CFR register *******************/ +#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */ +#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */ + +#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */ +#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */ + +#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_SR register ********************/ +#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Flexible Static Memory Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for FSMC_BCR1 register *******************/ +#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BCR2 register *******************/ +#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BCR3 register *******************/ +#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */ +#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BCR4 register *******************/ +#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BTR1 register ******************/ +#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BTR2 register *******************/ +#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/******************* Bit definition for FSMC_BTR3 register *******************/ +#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BTR4 register *******************/ +#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR1 register ******************/ +#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR2 register ******************/ +#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/ +#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR3 register ******************/ +#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR4 register ******************/ +#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_PCR2 register *******************/ +#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!< Memory type */ + +#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */ +#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/****************** Bit definition for FSMC_PCR3 register *******************/ +#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!< Memory type */ + +#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ +#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/****************** Bit definition for FSMC_PCR4 register *******************/ +#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */ + +#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ +#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/******************* Bit definition for FSMC_SR2 register *******************/ +#define FSMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +#define FSMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +#define FSMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +#define FSMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ +#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ + +/******************* Bit definition for FSMC_SR3 register *******************/ +#define FSMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +#define FSMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +#define FSMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +#define FSMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ +#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ + +/******************* Bit definition for FSMC_SR4 register *******************/ +#define FSMC_SR4_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +#define FSMC_SR4_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +#define FSMC_SR4_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +#define FSMC_SR4_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ +#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ + +/****************** Bit definition for FSMC_PMEM2 register ******************/ +#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */ +#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */ +#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */ +#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ +#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PMEM3 register ******************/ +#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */ +#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */ +#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */ +#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ +#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PMEM4 register ******************/ +#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */ +#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */ +#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */ +#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ +#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PATT2 register ******************/ +#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */ +#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ +#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ +#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ +#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PATT3 register ******************/ +#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */ +#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ +#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ +#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ +#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PATT4 register ******************/ +#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */ +#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ +#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ +#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ +#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PIO4 register *******************/ +#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!< IOSET4[7:0] bits (I/O 4 setup time) */ +#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */ +#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */ +#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ +#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_ECCR2 register ******************/ +#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ + +/****************** Bit definition for FSMC_ECCR3 register ******************/ +#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ + +/******************************************************************************/ +/* */ +/* SD host Interface */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for SDIO_POWER register ******************/ +#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */ +#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */ + +/****************** Bit definition for SDIO_CLKCR register ******************/ +#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */ +#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */ +#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */ +#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */ + +#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ +#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */ +#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */ + +#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */ +#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */ + +/******************* Bit definition for SDIO_ARG register *******************/ +#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */ + +/******************* Bit definition for SDIO_CMD register *******************/ +#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */ + +#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */ +#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */ +#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */ + +#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */ +#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ +#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */ +#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */ +#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */ +#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */ +#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */ + +/***************** Bit definition for SDIO_RESPCMD register *****************/ +#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */ + +/****************** Bit definition for SDIO_RESP0 register ******************/ +#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP1 register ******************/ +#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP2 register ******************/ +#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP3 register ******************/ +#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP4 register ******************/ +#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_DTIMER register *****************/ +#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */ + +/****************** Bit definition for SDIO_DLEN register *******************/ +#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */ + +/****************** Bit definition for SDIO_DCTRL register ******************/ +#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */ +#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */ +#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */ +#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */ + +#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */ +#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */ +#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */ +#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */ +#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */ + +/****************** Bit definition for SDIO_DCOUNT register *****************/ +#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */ + +/****************** Bit definition for SDIO_STA register ********************/ +#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */ +#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */ +#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */ +#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */ +#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */ +#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */ +#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */ +#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */ +#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */ +#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */ +#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */ +#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */ +#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */ +#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */ +#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ +#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ +#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */ +#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */ +#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */ +#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */ +#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */ +#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */ +#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */ +#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */ + +/******************* Bit definition for SDIO_ICR register *******************/ +#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */ +#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */ +#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */ +#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */ +#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */ +#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */ +#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */ +#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */ +#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */ +#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */ +#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */ +#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */ +#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */ + +/****************** Bit definition for SDIO_MASK register *******************/ +#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */ +#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */ +#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */ +#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */ +#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */ +#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */ +#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */ +#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */ +#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */ +#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */ +#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */ +#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */ +#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */ +#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */ +#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */ +#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */ +#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */ +#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */ +#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */ +#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */ +#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */ +#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */ + +/***************** Bit definition for SDIO_FIFOCNT register *****************/ +#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */ + +/****************** Bit definition for SDIO_FIFO register *******************/ +#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */ + +/******************************************************************************/ +/* */ +/* USB Device FS */ +/* */ +/******************************************************************************/ + +/*!< Endpoint-specific registers */ +/******************* Bit definition for USB_EP0R register *******************/ +#define USB_EP0R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP1R register *******************/ +#define USB_EP1R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP2R register *******************/ +#define USB_EP2R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP3R register *******************/ +#define USB_EP3R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP4R register *******************/ +#define USB_EP4R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP5R register *******************/ +#define USB_EP5R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP6R register *******************/ +#define USB_EP6R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP7R register *******************/ +#define USB_EP7R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/*!< Common registers */ +/******************* Bit definition for USB_CNTR register *******************/ +#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB Reset */ +#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power down */ +#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */ +#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force suspend */ +#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< Resume request */ +#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */ +#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */ +#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */ +#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */ +#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< Error Interrupt Mask */ +#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */ + +/******************* Bit definition for USB_ISTR register *******************/ +#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */ +#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */ +#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */ +#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */ +#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< USB RESET request */ +#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< Suspend mode request */ +#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */ +#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< Error */ +#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */ +#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct Transfer */ + +/******************* Bit definition for USB_FNR register ********************/ +#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */ +#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */ +#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */ +#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< Receive Data - Line Status */ +#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< Receive Data + Line Status */ + +/****************** Bit definition for USB_DADDR register *******************/ +#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */ +#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!< Bit 0 */ +#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!< Bit 1 */ +#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!< Bit 2 */ +#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!< Bit 3 */ +#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!< Bit 4 */ +#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!< Bit 5 */ +#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!< Bit 6 */ + +#define USB_DADDR_EF ((uint8_t)0x80) /*!< Enable Function */ + +/****************** Bit definition for USB_BTABLE register ******************/ +#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!< Buffer Table */ + +/*!< Buffer descriptor table */ +/***************** Bit definition for USB_ADDR0_TX register *****************/ +#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_TX register *****************/ +#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_TX register *****************/ +#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_TX register *****************/ +#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_TX register *****************/ +#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_TX register *****************/ +#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_TX register *****************/ +#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_TX register *****************/ +#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_TX register ****************/ +#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */ + +/***************** Bit definition for USB_COUNT1_TX register ****************/ +#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */ + +/***************** Bit definition for USB_COUNT2_TX register ****************/ +#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */ + +/***************** Bit definition for USB_COUNT3_TX register ****************/ +#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */ + +/***************** Bit definition for USB_COUNT4_TX register ****************/ +#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */ + +/***************** Bit definition for USB_COUNT5_TX register ****************/ +#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */ + +/***************** Bit definition for USB_COUNT6_TX register ****************/ +#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */ + +/***************** Bit definition for USB_COUNT7_TX register ****************/ +#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ +#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */ + +/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ +#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */ + +/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ +#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */ + +/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ +#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */ + +/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ +#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */ + +/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ +#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */ + +/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ +#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */ + +/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ +#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */ + +/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ +#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */ + +/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ +#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */ + +/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ +#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */ + +/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ +#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */ + +/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ +#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */ + +/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ +#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */ + +/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ +#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */ + +/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ +#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_ADDR0_RX register *****************/ +#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_RX register *****************/ +#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_RX register *****************/ +#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_RX register *****************/ +#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_RX register *****************/ +#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_RX register *****************/ +#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_RX register *****************/ +#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_RX register *****************/ +#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_RX register ****************/ +#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT1_RX register ****************/ +#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT2_RX register ****************/ +#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT3_RX register ****************/ +#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT4_RX register ****************/ +#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT5_RX register ****************/ +#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT6_RX register ****************/ +#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT7_RX register ****************/ +#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ +#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ +#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ +#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ +#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ +#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ +#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ +#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ +#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ +#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ +#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ +#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ +#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ +#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ +#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ +#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ +#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/******************************************************************************/ +/* */ +/* Controller Area Network */ +/* */ +/******************************************************************************/ + +/*!< CAN control and status registers */ +/******************* Bit definition for CAN_MCR register ********************/ +#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!< Initialization Request */ +#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!< Sleep Mode Request */ +#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!< Transmit FIFO Priority */ +#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!< Receive FIFO Locked Mode */ +#define CAN_MCR_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */ +#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */ +#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */ +#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */ +#define CAN_MCR_RESET ((uint16_t)0x8000) /*!< CAN software master reset */ + +/******************* Bit definition for CAN_MSR register ********************/ +#define CAN_MSR_INAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */ +#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */ +#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!< Error Interrupt */ +#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!< Wakeup Interrupt */ +#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */ +#define CAN_MSR_TXM ((uint16_t)0x0100) /*!< Transmit Mode */ +#define CAN_MSR_RXM ((uint16_t)0x0200) /*!< Receive Mode */ +#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!< Last Sample Point */ +#define CAN_MSR_RX ((uint16_t)0x0800) /*!< CAN Rx Signal */ + +/******************* Bit definition for CAN_TSR register ********************/ +#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */ +#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */ +#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */ +#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */ +#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */ +#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */ +#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */ +#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */ +#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */ +#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */ +#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */ +#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */ +#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */ +#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */ +#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */ +#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */ + +#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */ +#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */ +#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */ +#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */ + +#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */ +#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RF0R register *******************/ +#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!< FIFO 0 Message Pending */ +#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!< FIFO 0 Full */ +#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!< FIFO 0 Overrun */ +#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!< Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RF1R register *******************/ +#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!< FIFO 1 Message Pending */ +#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!< FIFO 1 Full */ +#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!< FIFO 1 Overrun */ +#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!< Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_IER register *******************/ +#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */ +#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */ +#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */ +#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */ +#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */ +#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */ +#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */ +#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */ +#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */ +#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ESR register *******************/ +#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */ +#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */ +#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */ + +#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */ +#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + +#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */ + +/******************* Bit definition for CAN_BTR register ********************/ +#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */ +#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */ +#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */ +#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */ +#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */ +#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!< Silent Mode */ + +/*!< Mailbox registers */ +/****************** Bit definition for CAN_TI0R register ********************/ +#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TDT0R register *******************/ +#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/****************** Bit definition for CAN_TDL0R register *******************/ +#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/****************** Bit definition for CAN_TDH0R register *******************/ +#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_TI1R register *******************/ +#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT1R register ******************/ +#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_TDL1R register ******************/ +#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_TDH1R register ******************/ +#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_TI2R register *******************/ +#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ +#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT2R register ******************/ +#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_TDL2R register ******************/ +#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_TDH2R register ******************/ +#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_RI0R register *******************/ +#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT0R register ******************/ +#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ +#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_RDL0R register ******************/ +#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_RDH0R register ******************/ +#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_RI1R register *******************/ +#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ +#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT1R register ******************/ +#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ +#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_RDL1R register ******************/ +#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_RDH1R register ******************/ +#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/*!< CAN filter registers */ +/******************* Bit definition for CAN_FMR register ********************/ +#define CAN_FMR_FINIT ((uint8_t)0x01) /*!< Filter Init Mode */ + +/******************* Bit definition for CAN_FM1R register *******************/ +#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!< Filter Mode */ +#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */ +#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */ +#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */ +#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */ +#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */ +#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */ +#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */ +#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */ +#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */ +#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */ +#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */ +#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */ +#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */ +#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */ + +/******************* Bit definition for CAN_FS1R register *******************/ +#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */ +#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */ +#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */ +#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */ +#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */ +#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */ +#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */ +#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */ +#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */ +#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */ +#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */ +#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */ +#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */ +#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */ +#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */ + +/****************** Bit definition for CAN_FFA1R register *******************/ +#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!< Filter FIFO Assignment */ +#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!< Filter FIFO Assignment for Filter 0 */ +#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!< Filter FIFO Assignment for Filter 1 */ +#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!< Filter FIFO Assignment for Filter 2 */ +#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!< Filter FIFO Assignment for Filter 3 */ +#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!< Filter FIFO Assignment for Filter 4 */ +#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!< Filter FIFO Assignment for Filter 5 */ +#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!< Filter FIFO Assignment for Filter 6 */ +#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!< Filter FIFO Assignment for Filter 7 */ +#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!< Filter FIFO Assignment for Filter 8 */ +#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!< Filter FIFO Assignment for Filter 9 */ +#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!< Filter FIFO Assignment for Filter 10 */ +#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!< Filter FIFO Assignment for Filter 11 */ +#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!< Filter FIFO Assignment for Filter 12 */ +#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!< Filter FIFO Assignment for Filter 13 */ + +/******************* Bit definition for CAN_FA1R register *******************/ +#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!< Filter Active */ +#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!< Filter 0 Active */ +#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!< Filter 1 Active */ +#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!< Filter 2 Active */ +#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!< Filter 3 Active */ +#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!< Filter 4 Active */ +#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!< Filter 5 Active */ +#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!< Filter 6 Active */ +#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!< Filter 7 Active */ +#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!< Filter 8 Active */ +#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!< Filter 9 Active */ +#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!< Filter 10 Active */ +#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!< Filter 11 Active */ +#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!< Filter 12 Active */ +#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!< Filter 13 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */ +#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */ +#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */ + +#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ +#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */ +#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */ +#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */ + +#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */ +#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */ +#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */ +#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */ +#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */ +#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */ +#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ +#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CR2 register ********************/ +#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */ +#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */ +#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */ +#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_SR register ********************/ +#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */ +#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */ +#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */ +#define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */ +#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */ +#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */ +#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */ +#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */ + +/******************** Bit definition for SPI_DR register ********************/ +#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ + +/******************* Bit definition for SPI_CRCPR register ******************/ +#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ + +/****************** Bit definition for SPI_RXCRCR register ******************/ +#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */ + +/****************** Bit definition for SPI_TXCRCR register ******************/ +#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */ + +/****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!< DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!< Bit 0 */ +#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!< Bit 1 */ + +#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!< I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!< I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!< I2S Enable */ +#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!< I2S mode selection */ + +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */ +#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!< Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!< Master Clock Output Enable */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CR1 register ********************/ +#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ +#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */ +#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */ +#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */ +#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */ +#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */ +#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */ +#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */ +#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */ +#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */ +#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */ +#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */ +#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */ +#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */ + +/******************* Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */ + +#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */ +#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */ +#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */ +#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */ +#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */ + +/******************* Bit definition for I2C_OAR1 register *******************/ +#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */ +#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */ + +#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */ +#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */ +#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */ + +#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OAR2 register *******************/ +#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */ +#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */ + +/******************** Bit definition for I2C_DR register ********************/ +#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */ + +/******************* Bit definition for I2C_SR1 register ********************/ +#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */ +#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */ +#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */ +#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */ +#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */ +#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */ +#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */ +#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */ +#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */ +#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */ +#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */ +#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */ +#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */ +#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */ + +/******************* Bit definition for I2C_SR2 register ********************/ +#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */ +#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */ +#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */ +#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */ +#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */ +#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */ +#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */ +#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */ + +/******************* Bit definition for I2C_CCR register ********************/ +#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */ +#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */ + +/****************** Bit definition for I2C_TRISE register *******************/ +#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* */ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for USART_SR register *******************/ +#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */ +#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */ +#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */ +#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */ +#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */ +#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */ +#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */ +#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */ +#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */ +#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */ + +/******************* Bit definition for USART_DR register *******************/ +#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CR1 register *******************/ +#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */ +#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */ +#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */ +#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */ +#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */ +#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */ +#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */ +#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */ +#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */ +#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */ +#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */ +#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */ +#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< USART Oversmapling 8-bits */ + +/****************** Bit definition for USART_CR2 register *******************/ +#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */ +#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */ +#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */ +#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */ +#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */ +#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */ + +#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */ +#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */ + +/****************** Bit definition for USART_CR3 register *******************/ +#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */ +#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */ +#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */ +#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */ +#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */ +#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */ +#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */ +#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */ +#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */ +#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */ +#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */ +#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One Bit method */ + +/****************** Bit definition for USART_GTPR register ******************/ +#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ +#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */ + +#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for DBGMCU_IDCODE register *****************/ +#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */ + +#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ +#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */ +#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */ +#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */ +#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */ +#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */ +#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */ +#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */ +#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */ +#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */ + +/****************** Bit definition for DBGMCU_CR register *******************/ +#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */ +#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ +#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ +#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */ + +#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ +#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */ +#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */ +#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!< Debug CAN2 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!< Debug TIM12 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!< Debug TIM13 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!< Debug TIM14 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!< Debug TIM9 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!< Debug TIM10 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!< Debug TIM11 stopped when Core is halted */ + +/******************************************************************************/ +/* */ +/* FLASH and Option Bytes Registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACR register ******************/ +#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */ +#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */ +#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */ +#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */ + +#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */ +#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */ +#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!< Prefetch Buffer Status */ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ + +/***************** Bit definition for FLASH_OPTKEYR register ****************/ +#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ + +/****************** Bit definition for FLASH_SR register *******************/ +#define FLASH_SR_BSY ((uint8_t)0x01) /*!< Busy */ +#define FLASH_SR_PGERR ((uint8_t)0x04) /*!< Programming Error */ +#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!< Write Protection Error */ +#define FLASH_SR_EOP ((uint8_t)0x20) /*!< End of operation */ + +/******************* Bit definition for FLASH_CR register *******************/ +#define FLASH_CR_PG ((uint16_t)0x0001) /*!< Programming */ +#define FLASH_CR_PER ((uint16_t)0x0002) /*!< Page Erase */ +#define FLASH_CR_MER ((uint16_t)0x0004) /*!< Mass Erase */ +#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */ +#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */ +#define FLASH_CR_STRT ((uint16_t)0x0040) /*!< Start */ +#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!< Lock */ +#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */ +#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!< Error Interrupt Enable */ +#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!< End of operation interrupt enable */ + +/******************* Bit definition for FLASH_AR register *******************/ +#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!< Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!< Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!< User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!< nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */ +#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!< BFB2 */ + +/****************** Bit definition for FLASH_WRPR register ******************/ +#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for FLASH_RDP register *******************/ +#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ +#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRP0 register ******************/ +#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP1 register ******************/ +#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP2 register ******************/ +#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP3 register ******************/ +#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + +#ifdef STM32F10X_CL +/******************************************************************************/ +/* Ethernet MAC Registers bits definitions */ +/******************************************************************************/ +/* Bit definition for Ethernet MAC Control Register register */ +#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ +#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ +#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ + #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ + #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ + #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ + #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ + #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ + #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ + #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ + #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ +#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ +#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ +#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ +#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ +#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ +#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ +#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ +#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ +#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling + a transmission attempt during retries after a collision: 0 =< r <2^k */ + #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ + #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ + #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ + #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ +#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ +#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ +#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ + +/* Bit definition for Ethernet MAC Frame Filter Register */ +#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ +#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ +#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ +#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ +#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ + #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ + #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ + #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ +#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ +#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ +#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ +#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ +#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ +#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ + +/* Bit definition for Ethernet MAC Hash Table High Register */ +#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ + +/* Bit definition for Ethernet MAC Hash Table Low Register */ +#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ + +/* Bit definition for Ethernet MAC MII Address Register */ +#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ +#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ +#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ + #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ + #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ + #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ +#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ +#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ + +/* Bit definition for Ethernet MAC MII Data Register */ +#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ + +/* Bit definition for Ethernet MAC Flow Control Register */ +#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ +#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ +#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ + #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ + #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ + #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ + #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ +#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ +#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ +#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ +#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ + +/* Bit definition for Ethernet MAC VLAN Tag Register */ +#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ +#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ + +/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ +#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ +/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. + Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ +/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask + Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask + Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask + Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask + Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - + RSVD - Filter1 Command - RSVD - Filter0 Command + Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset + Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 + Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ + +/* Bit definition for Ethernet MAC PMT Control and Status Register */ +#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ +#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ +#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ +#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ +#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ +#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ + +/* Bit definition for Ethernet MAC Status Register */ +#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ +#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ +#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ +#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ +#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ + +/* Bit definition for Ethernet MAC Interrupt Mask Register */ +#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ +#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ + +/* Bit definition for Ethernet MAC Address0 High Register */ +#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ + +/* Bit definition for Ethernet MAC Address0 Low Register */ +#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ + +/* Bit definition for Ethernet MAC Address1 High Register */ +#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ +#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ +#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ + #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ + +/* Bit definition for Ethernet MAC Address1 Low Register */ +#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ + +/* Bit definition for Ethernet MAC Address2 High Register */ +#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ +#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ +#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ + #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ + +/* Bit definition for Ethernet MAC Address2 Low Register */ +#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ + +/* Bit definition for Ethernet MAC Address3 High Register */ +#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ +#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ +#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ + #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ + +/* Bit definition for Ethernet MAC Address3 Low Register */ +#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ + +/******************************************************************************/ +/* Ethernet MMC Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet MMC Contol Register */ +#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ +#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ +#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ +#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ + +/* Bit definition for Ethernet MMC Receive Interrupt Register */ +#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmit Interrupt Register */ +#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ +#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ +#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ +#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ +#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ +#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ + +/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ +#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ + +/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ +#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ + +/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ +#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ + +/******************************************************************************/ +/* Ethernet PTP Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet PTP Time Stamp Contol Register */ +#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ +#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ +#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ +#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ +#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ +#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ + +/* Bit definition for Ethernet PTP Sub-Second Increment Register */ +#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ + +/* Bit definition for Ethernet PTP Time Stamp High Register */ +#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ + +/* Bit definition for Ethernet PTP Time Stamp Low Register */ +#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ +#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ + +/* Bit definition for Ethernet PTP Time Stamp High Update Register */ +#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ + +/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ +#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ +#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ + +/* Bit definition for Ethernet PTP Time Stamp Addend Register */ +#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ + +/* Bit definition for Ethernet PTP Target Time High Register */ +#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ + +/* Bit definition for Ethernet PTP Target Time Low Register */ +#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ + +/******************************************************************************/ +/* Ethernet DMA Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet DMA Bus Mode Register */ +#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ +#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ +#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ +#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ + #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ + #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ + #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ + #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ +#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ + #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ + #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ + #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ + #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ +#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ +#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ + +/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ +#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ + +/* Bit definition for Ethernet DMA Receive Poll Demand Register */ +#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ + +/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ +#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ + +/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ +#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ + +/* Bit definition for Ethernet DMA Status Register */ +#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ + /* combination with EBS[2:0] for GetFlagStatus function */ + #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ + #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ + #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ + #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ + #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ + #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ + #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ + #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ + #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ + #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ + #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ + #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ + #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ + #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ + #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ + +/* Bit definition for Ethernet DMA Operation Mode Register */ +#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ +#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ +#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ +#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ +#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ +#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ + #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ + #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ + #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ + #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ + #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ + #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ + #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ + #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ +#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ +#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ +#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ + #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ + #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ + #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ + #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ +#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ +#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ + +/* Bit definition for Ethernet DMA Interrupt Enable Register */ +#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ +#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ +#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ +#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ +#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ +#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ +#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ +#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ +#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ +#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ +#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ +#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ +#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ +#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ +#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ + +/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ +#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ +#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ +#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ + +/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ +#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ + +/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ +#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ + +/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ +#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ + +/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ +#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ +#endif /* STM32F10X_CL */ + +/** + * @} + */ + + /** + * @} + */ + +#ifdef USE_STDPERIPH_DRIVER + #include "stm32f10x_conf.h" +#endif + +/** @addtogroup Exported_macro + * @{ + */ + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_H */ + +/** + * @} + */ + + /** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Project/os/hal/platforms/STM32F2xx/adc_lld.c b/Project/os/hal/platforms/STM32F2xx/adc_lld.c new file mode 100644 index 0000000..1b566c2 --- /dev/null +++ b/Project/os/hal/platforms/STM32F2xx/adc_lld.c @@ -0,0 +1,423 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F2xx/adc_lld.c + * @brief STM32F2xx ADC subsystem low level driver source. + * + * @addtogroup ADC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define ADC1_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN) + +#define ADC2_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_CHN) + +#define ADC3_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_CHN) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ADC1 driver identifier.*/ +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +ADCDriver ADCD1; +#endif + +/** @brief ADC2 driver identifier.*/ +#if STM32_ADC_USE_ADC2 || defined(__DOXYGEN__) +ADCDriver ADCD2; +#endif + +/** @brief ADC3 driver identifier.*/ +#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__) +ADCDriver ADCD3; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief ADC DMA ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { + + /* DMA errors handling.*/ + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + /* DMA, this could help only if the DMA tries to access an unmapped + address space or violates alignment rules.*/ + _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); + } + else { + /* It is possible that the conversion group has already be reset by the + ADC error handler, in this case this interrupt is spurious.*/ + if (adcp->grpp != NULL) { + if ((flags & STM32_DMA_ISR_HTIF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + if ((flags & STM32_DMA_ISR_TCIF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } + } + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 || STM32_ADC_USE_ADC3 || \ + defined(__DOXYGEN__) +/** + * @brief ADC interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) { + uint32_t sr; + + CH_IRQ_PROLOGUE(); + +#if STM32_ADC_USE_ADC1 + sr = ADC1->SR; + ADC1->SR = 0; + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + if (ADCD1.grpp != NULL) + _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW); + } + /* TODO: Add here analog watchdog handling.*/ +#endif /* STM32_ADC_USE_ADC1 */ + +#if STM32_ADC_USE_ADC2 + sr = ADC2->SR; + ADC2->SR = 0; + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD2.dmastp) > 0)) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + if (ADCD2.grpp != NULL) + _adc_isr_error_code(&ADCD2, ADC_ERR_OVERFLOW); + } + /* TODO: Add here analog watchdog handling.*/ +#endif /* STM32_ADC_USE_ADC2 */ + +#if STM32_ADC_USE_ADC3 + sr = ADC3->SR; + ADC3->SR = 0; + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD3.dmastp) > 0)) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + if (ADCD3.grpp != NULL) + _adc_isr_error_code(&ADCD3, ADC_ERR_OVERFLOW); + } + /* TODO: Add here analog watchdog handling.*/ +#endif /* STM32_ADC_USE_ADC3 */ + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +#if STM32_ADC_USE_ADC1 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); + ADCD1.adc = ADC1; + ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM); + ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; +#endif + +#if STM32_ADC_USE_ADC2 + /* Driver initialization.*/ + adcObjectInit(&ADCD2); + ADCD2.adc = ADC2; + ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM); + ADCD2.dmamode = STM32_DMA_CR_CHSEL(ADC2_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; +#endif + +#if STM32_ADC_USE_ADC3 + /* Driver initialization.*/ + adcObjectInit(&ADCD3); + ADCD3.adc = ADC3; + ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM); + ADCD3.dmamode = STM32_DMA_CR_CHSEL(ADC3_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; +#endif + + /* The shared vector is initialized on driver initialization and never + disabled.*/ + nvicEnableVector(ADC_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY)); +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + /* If in stopped state then enables the ADC and DMA clocks.*/ + if (adcp->state == ADC_STOP) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC1_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); + rccEnableADC1(FALSE); + } +#endif /* STM32_ADC_USE_ADC1 */ + +#if STM32_ADC_USE_ADC2 + if (&ADCD2 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC2_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR); + rccEnableADC2(FALSE); + } +#endif /* STM32_ADC_USE_ADC2 */ + +#if STM32_ADC_USE_ADC3 + if (&ADCD3 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC3_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #3", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR); + rccEnableADC3(FALSE); + } +#endif /* STM32_ADC_USE_ADC3 */ + + /* This is a common register but apparently it requires that at least one + of the ADCs is clocked in order to allow writing, see bug 3575297.*/ + ADC->CCR = STM32_ADC_ADCPRE << 16; + + /* ADC initial setup, starting the analog part here in order to reduce + the latency when starting a conversion.*/ + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + adcp->adc->CR2 = ADC_CR2_ADON; + } +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + /* If in ready state then disables the ADC clock.*/ + if (adcp->state == ADC_READY) { + dmaStreamRelease(adcp->dmastp); + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) + rccDisableADC1(FALSE); +#endif + +#if STM32_ADC_USE_ADC2 + if (&ADCD2 == adcp) + rccDisableADC2(FALSE); +#endif + +#if STM32_ADC_USE_ADC3 + if (&ADCD3 == adcp) + rccDisableADC3(FALSE); +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + uint32_t mode; + const ADCConversionGroup *grpp = adcp->grpp; + + /* DMA setup.*/ + mode = adcp->dmamode; + if (grpp->circular) { + mode |= STM32_DMA_CR_CIRC; + } + if (adcp->depth > 1) { + /* If the buffer depth is greater than one then the half transfer interrupt + interrupt is enabled in order to allows streaming processing.*/ + mode |= STM32_DMA_CR_HTIE; + } + dmaStreamSetMemory0(adcp->dmastp, adcp->samples); + dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * + (uint32_t)adcp->depth); + dmaStreamSetMode(adcp->dmastp, mode); + dmaStreamEnable(adcp->dmastp); + + /* ADC setup.*/ + adcp->adc->SR = 0; + adcp->adc->SMPR1 = grpp->smpr1; + adcp->adc->SMPR2 = grpp->smpr2; + adcp->adc->SQR1 = grpp->sqr1; + adcp->adc->SQR2 = grpp->sqr2; + adcp->adc->SQR3 = grpp->sqr3; + + /* ADC configuration and start, the start is performed using the method + specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/ + adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN; + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT | ADC_CR2_DMA | + ADC_CR2_DDS | ADC_CR2_ADON; +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + dmaStreamDisable(adcp->dmastp); + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + adcp->adc->CR2 = ADC_CR2_ADON; +} + +/** + * @brief Enables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + */ +void adcSTM32EnableTSVREFE(void) { + + ADC->CCR |= ADC_CCR_TSVREFE; +} + +/** + * @brief Disables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + */ +void adcSTM32DisableTSVREFE(void) { + + ADC->CCR &= ~ADC_CCR_TSVREFE; +} + +/** + * @brief Enables the VBATE bit. + * @details The VBATE bit is required in order to sample the VBAT channel. + * @note This is an STM32-only functionality. + */ +void adcSTM32EnableVBATE(void) { + + ADC->CCR |= ADC_CCR_VBATE; +} + +/** + * @brief Disables the VBATE bit. + * @details The VBATE bit is required in order to sample the VBAT channel. + * @note This is an STM32-only functionality. + */ +void adcSTM32DisableVBATE(void) { + + ADC->CCR &= ~ADC_CCR_VBATE; +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F2xx/adc_lld.h b/Project/os/hal/platforms/STM32F2xx/adc_lld.h new file mode 100644 index 0000000..67f4717 --- /dev/null +++ b/Project/os/hal/platforms/STM32F2xx/adc_lld.h @@ -0,0 +1,574 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F2xx/adc_lld.h + * @brief STM32F2xx ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Minimum ADC clock frequency. + */ +#define STM32_ADCCLK_MIN 600000 + +/** + * @brief Maximum ADC clock frequency. + */ +#define STM32_ADCCLK_MAX 30000000 +/** @} */ + +/** + * @name Triggers selection + * @{ + */ +#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */ +/** @} */ + +/** + * @name ADC clock divider settings + * @{ + */ +#define ADC_CCR_ADCPRE_DIV2 0 +#define ADC_CCR_ADCPRE_DIV4 1 +#define ADC_CCR_ADCPRE_DIV6 2 +#define ADC_CCR_ADCPRE_DIV8 3 +/** @} */ + +/** + * @name Available analog channels + * @{ + */ +#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ +#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ +#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ +#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ +#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ +#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ +#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ +#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ +#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ +#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ +#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ +#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ +#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ +#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ +#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ +#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ +#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor. + @note Available onADC1 only. */ +#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. + @note Available onADC1 only. */ +#define ADC_CHANNEL_VBAT 18 /**< @brief VBAT. + @note Available onADC1 only. */ +/** @} */ + +/** + * @name Sampling rates + * @{ + */ +#define ADC_SAMPLE_3 0 /**< @brief 3 cycles sampling time. */ +#define ADC_SAMPLE_15 1 /**< @brief 15 cycles sampling time. */ +#define ADC_SAMPLE_28 2 /**< @brief 28 cycles sampling time. */ +#define ADC_SAMPLE_56 3 /**< @brief 56 cycles sampling time. */ +#define ADC_SAMPLE_84 4 /**< @brief 84 cycles sampling time. */ +#define ADC_SAMPLE_112 5 /**< @brief 112 cycles sampling time. */ +#define ADC_SAMPLE_144 6 /**< @brief 144 cycles sampling time. */ +#define ADC_SAMPLE_480 7 /**< @brief 480 cycles sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ADC common clock divider. + * @note This setting is influenced by the VDDA voltage and other + * external conditions, please refer to the STM32F2xx datasheet + * for more info.
+ * See section 5.3.20 "12-bit ADC characteristics". + */ +#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__) +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2 +#endif + +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC1 TRUE +#endif + +/** + * @brief ADC2 driver enable switch. + * @details If set to @p TRUE the support for ADC2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC2) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC2 TRUE +#endif + +/** + * @brief ADC3 driver enable switch. + * @details If set to @p TRUE the support for ADC3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC3 TRUE +#endif + +/** + * @brief DMA stream used for ADC1 operations. + */ +#if !defined(STM32_ADC_ADC1_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#endif + +/** + * @brief DMA stream used for ADC2 operations. + */ +#if !defined(STM32_ADC_ADC2_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#endif + +/** + * @brief DMA stream used for ADC3 operations. + */ +#if !defined(STM32_ADC_ADC3_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#endif + +/** + * @brief ADC1 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC2 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC3 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC interrupt priority level setting. + * @note This setting is shared among ADC1, ADC2 and ADC3 because + * all ADCs share the same vector. + */ +#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC1 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC2 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC3 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 +#error "ADC1 not present in the selected device" +#endif + +#if STM32_ADC_USE_ADC2 && !STM32_HAS_ADC2 +#error "ADC2 not present in the selected device" +#endif + +#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3 +#error "ADC3 not present in the selected device" +#endif + +#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && !STM32_ADC_USE_ADC3 +#error "ADC driver activated but no ADC peripheral assigned" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_MSK) +#error "invalid DMA stream associated to ADC1" +#endif + +#if STM32_ADC_USE_ADC2 && \ + !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_MSK) +#error "invalid DMA stream associated to ADC2" +#endif + +#if STM32_ADC_USE_ADC3 && \ + !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_MSK) +#error "invalid DMA stream associated to ADC3" +#endif + +/* ADC clock related settings and checks.*/ +#if STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV2 +#define STM32_ADCCLK (STM32_PCLK2 / 2) +#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV4 +#define STM32_ADCCLK (STM32_PCLK2 / 4) +#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV6 +#define STM32_ADCCLK (STM32_PCLK2 / 6) +#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV8 +#define STM32_ADCCLK (STM32_PCLK2 / 8) +#else +#error "invalid STM32_ADC_ADCPRE value specified" +#endif + +#if (STM32_ADCCLK < STM32_ADCCLK_MIN) || (STM32_ADCCLK > STM32_ADCCLK_MAX) +#error "STM32_ADCCLK outside acceptable range (STM32_ADCCLK_MIN...STM32_ADCCLK_MAX)" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ + ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */ +} adcerror_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief ADC error callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] err ADC error code + */ +typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note The use of this configuration structure requires knowledge of + * STM32 ADC cell registers interface, please refer to the STM32 + * reference manual for details. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool_t circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /** + * @brief Error callback or @p NULL. + */ + adcerrorcallback_t error_cb; + /* End of the mandatory fields.*/ + /** + * @brief ADC CR1 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR1_SCAN that is enforced inside the driver. + */ + uint32_t cr1; + /** + * @brief ADC CR2 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are + * enforced inside the driver. + */ + uint32_t cr2; + /** + * @brief ADC SMPR1 register initialization data. + * @details In this field must be specified the sample times for channels + * 10...18. + */ + uint32_t smpr1; + /** + * @brief ADC SMPR2 register initialization data. + * @details In this field must be specified the sample times for channels + * 0...9. + */ + uint32_t smpr2; + /** + * @brief ADC SQR1 register initialization data. + * @details Conversion group sequence 13...16 + sequence length. + */ + uint32_t sqr1; + /** + * @brief ADC SQR2 register initialization data. + * @details Conversion group sequence 7...12. + */ + uint32_t sqr2; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 1...6. + */ + uint32_t sqr3; +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the ADCx registers block. + */ + ADC_TypeDef *adc; + /** + * @brief Pointer to associated SMA channel. + */ + const stm32_dma_stream_t *dmastp; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Sequences building helper macros + * @{ + */ +/** + * @brief Number of channels in a conversion sequence. + */ +#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) + +#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ +#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ +#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ +#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ +#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ +#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ + +#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ +#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ +#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ +#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ +#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ +#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ + +#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ +#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ +#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ +#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ +/** @} */ + +/** + * @name Sampling rate settings helper macros + * @{ + */ +#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ +#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ + +#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ +#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor + sampling time. */ +#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference + sampling time. */ +#define ADC_SMPR1_SMP_VBAT(n) ((n) << 24) /**< @brief VBAT sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#if STM32_ADC_USE_ADC2 && !defined(__DOXYGEN__) +extern ADCDriver ADCD2; +#endif + +#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__) +extern ADCDriver ADCD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); + void adcSTM32EnableTSVREFE(void); + void adcSTM32DisableTSVREFE(void); + void adcSTM32EnableVBATE(void); + void adcSTM32DisableVBATE(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F2xx/hal_lld.c b/Project/os/hal/platforms/STM32F2xx/hal_lld.c new file mode 100644 index 0000000..174dc4f --- /dev/null +++ b/Project/os/hal/platforms/STM32F2xx/hal_lld.c @@ -0,0 +1,220 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F2xx/hal_lld.c + * @brief STM32F2xx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the backup domain. + */ +static void hal_lld_backup_domain_init(void) { + + /* Backup domain access enabled and left open.*/ + PWR->CR |= PWR_CR_DBP; + + /* Reset BKP domain if different clock source selected.*/ + if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){ + /* Backup domain reset.*/ + RCC->BDCR = RCC_BDCR_BDRST; + RCC->BDCR = 0; + } + + /* If enabled then the LSE is started.*/ +#if STM32_LSE_ENABLED + RCC->BDCR |= RCC_BDCR_LSEON; + while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ +#endif + +#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK + /* If the backup domain hasn't been initialized yet then proceed with + initialization.*/ + if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { + /* Selects clock source.*/ + RCC->BDCR |= STM32_RTCSEL; + + /* RTC clock enabled.*/ + RCC->BDCR |= RCC_BDCR_RTCEN; + } +#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */ +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* Reset of all peripherals. AHB3 is not reseted because it could have + been initialized in the board initialization file (board.c).*/ + rccResetAHB1(!0); + rccResetAHB2(!0); + rccResetAHB3(!0); + rccResetAPB1(!RCC_APB1RSTR_PWRRST); + rccResetAPB2(!0); + + /* SysTick initialization using the system clock.*/ + SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + + /* DWT cycle counter enable.*/ + SCS_DEMCR |= SCS_DEMCR_TRCENA; + DWT_CTRL |= DWT_CTRL_CYCCNTENA; + + /* PWR clock enabled.*/ + rccEnablePWRInterface(FALSE); + + /* Initializes the backup domain.*/ + hal_lld_backup_domain_init(); + +#if defined(STM32_DMA_REQUIRED) + dmaInit(); +#endif + + /* Programmable voltage detector enable.*/ +#if STM32_PVD_ENABLE + PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); +#endif /* STM32_PVD_ENABLE */ +} + +/** + * @brief STM32F2xx clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +void stm32_clock_init(void) { + +#if !STM32_NO_INIT + /* PWR clock enable.*/ + RCC->APB1ENR = RCC_APB1ENR_PWREN; + + /* PWR initialization.*/ + PWR->CR = 0; + + /* Initial clocks setup and wait for HSI stabilization, the MSI clock is + always enabled because it is the fallback clock when PLL the fails.*/ + RCC->CR |= RCC_CR_HSION; + while ((RCC->CR & RCC_CR_HSIRDY) == 0) + ; /* Waits until HSI is stable. */ + +#if STM32_HSE_ENABLED + /* HSE activation.*/ + RCC->CR |= RCC_CR_HSEON; + while ((RCC->CR & RCC_CR_HSERDY) == 0) + ; /* Waits until HSE is stable. */ +#endif + +#if STM32_LSI_ENABLED + /* LSI activation.*/ + RCC->CSR |= RCC_CSR_LSION; + while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) + ; /* Waits until LSI is stable. */ +#endif + +#if STM32_LSE_ENABLED + /* LSE activation, have to unlock the register.*/ + if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) { + PWR->CR |= PWR_CR_DBP; + RCC->BDCR |= RCC_BDCR_LSEON; + PWR->CR &= ~PWR_CR_DBP; + } + while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ +#endif + +#if STM32_ACTIVATE_PLL + /* PLL activation.*/ + RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN | STM32_PLLM; + RCC->CR |= RCC_CR_PLLON; + while (!(RCC->CR & RCC_CR_PLLRDY)) + ; /* Waits until PLL is stable. */ +#endif + +#if STM32_ACTIVATE_PLLI2S + /* PLLI2S activation.*/ + RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN; + RCC->CR |= RCC_CR_PLLI2SON; + while (!(RCC->CR & RCC_CR_PLLI2SRDY)) + ; /* Waits until PLLI2S is stable. */ +#endif + + /* Other clock-related settings (dividers, MCO etc).*/ + RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL | + STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; + + /* Flash setup.*/ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | + STM32_FLASHBITS; + + /* Switching to the configured clock source if it is different from MSI.*/ +#if (STM32_SW != STM32_SW_HSI) + RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) + ; +#endif +#endif /* STM32_NO_INIT */ + + /* SYSCFG clock enabled here because it is a multi-functional unit shared + among multiple drivers.*/ + rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); +} + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F2xx/hal_lld.h b/Project/os/hal/platforms/STM32F2xx/hal_lld.h new file mode 100644 index 0000000..095a62f --- /dev/null +++ b/Project/os/hal/platforms/STM32F2xx/hal_lld.h @@ -0,0 +1,1407 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F4xx/hal_lld.h + * @brief STM32F4xx HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - STM32_LSECLK. + * - STM32_HSECLK. + * - STM32_VDD (as hundredths of Volt). + * . + * One of the following macros must also be defined: + * - STM32F4XX for High-performance STM32 F-4 devices. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "stm32.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS TRUE + +/** + * @name Platform identification + * @{ + */ +#define PLATFORM_NAME "STM32F2 High Performance" +/** @} */ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Maximum system clock frequency. + */ +#define STM32_SYSCLK_MAX 120000000 + +/** + * @brief Maximum HSE clock frequency. + */ +#define STM32_HSECLK_MAX 26000000 + +/** + * @brief Minimum HSE clock frequency. + */ +#define STM32_HSECLK_MIN 1000000 + +/** + * @brief Maximum LSE clock frequency. + */ +#define STM32_LSECLK_MAX 1000000 + +/** + * @brief Minimum LSE clock frequency. + */ +#define STM32_LSECLK_MIN 32768 + +/** + * @brief Maximum PLLs input clock frequency. + */ +#define STM32_PLLIN_MAX 2000000 + +/** + * @brief Minimum PLLs input clock frequency. + */ +#define STM32_PLLIN_MIN 950000 + +/** + * @brief Maximum PLLs VCO clock frequency. + */ +#define STM32_PLLVCO_MAX 432000000 + +/** + * @brief Maximum PLLs VCO clock frequency. + */ +#define STM32_PLLVCO_MIN 192000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define STM32_PLLOUT_MAX 120000000 + +/** + * @brief Minimum PLL output clock frequency. + */ +#define STM32_PLLOUT_MIN 24000000 + +/** + * @brief Maximum APB1 clock frequency. + */ +#define STM32_PCLK1_MAX 30000000 + +/** + * @brief Maximum APB2 clock frequency. + */ +#define STM32_PCLK2_MAX 60000000 + +/** + * @brief Maximum SPI/I2S clock frequency. + */ +#define STM32_SPII2S_MAX 37500000 +/** @} */ + +/** + * @name Internal clock sources + * @{ + */ +#define STM32_HSICLK 16000000 /**< High speed internal clock. */ +#define STM32_LSICLK 32000 /**< Low speed internal clock. */ +/** @} */ + +/** + * @name PWR_CR register bits definitions + * @{ + */ +#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */ +#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */ +#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */ +#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */ +#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */ +#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */ +#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */ +#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */ +/** @} */ + +/** + * @name RCC_PLLCFGR register bits definitions + * @{ + */ +#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */ +#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */ +#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */ +#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */ +#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */ + +#define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */ +#define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */ +/** @} */ + +/** + * @name RCC_CFGR register bits definitions + * @{ + */ +#define STM32_SW_MASK (3 << 0) /**< SW mask. */ +#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ +#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ +#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ + +#define STM32_HPRE_MASK (15 << 4) /**< HPRE mask. */ +#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ +#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ +#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ +#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ +#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ +#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ +#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ +#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ +#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ + +#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */ +#define STM32_PPRE1_DIV1 (0 << 10) /**< HCLK divided by 1. */ +#define STM32_PPRE1_DIV2 (4 << 10) /**< HCLK divided by 2. */ +#define STM32_PPRE1_DIV4 (5 << 10) /**< HCLK divided by 4. */ +#define STM32_PPRE1_DIV8 (6 << 10) /**< HCLK divided by 8. */ +#define STM32_PPRE1_DIV16 (7 << 10) /**< HCLK divided by 16. */ + +#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */ +#define STM32_PPRE2_DIV1 (0 << 13) /**< HCLK divided by 1. */ +#define STM32_PPRE2_DIV2 (4 << 13) /**< HCLK divided by 2. */ +#define STM32_PPRE2_DIV4 (5 << 13) /**< HCLK divided by 4. */ +#define STM32_PPRE2_DIV8 (6 << 13) /**< HCLK divided by 8. */ +#define STM32_PPRE2_DIV16 (7 << 13) /**< HCLK divided by 16. */ + +#define STM32_RTCPRE_MASK (31 << 16) /**< RTCPRE mask. */ + +#define STM32_MCO1SEL_MASK (3 << 21) /**< MCO1 mask. */ +#define STM32_MCO1SEL_HSI (0 << 21) /**< HSI clock on MCO1 pin. */ +#define STM32_MCO1SEL_LSE (1 << 21) /**< LSE clock on MCO1 pin. */ +#define STM32_MCO1SEL_HSE (2 << 21) /**< HSE clock on MCO1 pin. */ +#define STM32_MCO1SEL_PLL (3 << 21) /**< PLL clock on MCO1 pin. */ + +#define STM32_I2SSRC_MASK (1 << 23) /**< I2CSRC mask. */ +#define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */ +#define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */ + +#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */ +#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */ +#define STM32_MCO1PRE_DIV2 (4 << 24) /**< MCO1 divided by 2. */ +#define STM32_MCO1PRE_DIV3 (5 << 24) /**< MCO1 divided by 3. */ +#define STM32_MCO1PRE_DIV4 (6 << 24) /**< MCO1 divided by 4. */ +#define STM32_MCO1PRE_DIV5 (7 << 24) /**< MCO1 divided by 5. */ + +#define STM32_MCO2PRE_MASK (7 << 27) /**< MCO2PRE mask. */ +#define STM32_MCO2PRE_DIV1 (0 << 27) /**< MCO2 divided by 1. */ +#define STM32_MCO2PRE_DIV2 (4 << 27) /**< MCO2 divided by 2. */ +#define STM32_MCO2PRE_DIV3 (5 << 27) /**< MCO2 divided by 3. */ +#define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */ +#define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */ + +#define STM32_MCO2SEL_MASK (3U << 30) /**< MCO2 mask. */ +#define STM32_MCO2SEL_SYSCLK (0U << 30) /**< SYSCLK clock on MCO2 pin. */ +#define STM32_MCO2SEL_PLLI2S (1U << 30) /**< PLLI2S clock on MCO2 pin. */ +#define STM32_MCO2SEL_HSE (2U << 30) /**< HSE clock on MCO2 pin. */ +#define STM32_MCO2SEL_PLL (3U << 30) /**< PLL clock on MCO2 pin. */ + +#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock. */ +#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock. */ +#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock. */ +#define STM32_RTC_HSE (3 << 8) /**< HSE divided by programmable + prescaler used as RTC clock*/ + +/** + * @name RCC_PLLI2SCFGR register bits definitions + * @{ + */ +#define STM32_PLLI2SN_MASK (511 << 6) /**< PLLI2SN mask. */ +#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */ +/** @} */ + +/** + * @name RCC_BDCR register bits definitions + * @{ + */ +#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */ +#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */ +#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */ +#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */ +#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */ +/** @} */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name STM32F4xx capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_ADC1_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC2 TRUE +#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) | \ + STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_ADC2_DMA_CHN 0x00001100 + +#define STM32_HAS_ADC3 TRUE +#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \ + STM32_DMA_STREAM_ID_MSK(2, 1)) +#define STM32_ADC3_DMA_CHN 0x00000022 + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 TRUE +#define STM32_CAN_MAX_FILTERS 28 + +/* DAC attributes.*/ +#define STM32_HAS_DAC TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA TRUE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 TRUE + +/* ETH attributes.*/ +#define STM32_HAS_ETH TRUE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 23 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOH TRUE +#define STM32_HAS_GPIOI TRUE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) | \ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C1_RX_DMA_CHN 0x00100001 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) | \ + (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x11000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) | \ + STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_I2C2_RX_DMA_CHN 0x00007700 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C2_TX_DMA_CHN 0x70000000 + +#define STM32_HAS_I2C3 TRUE +#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_I2C3_RX_DMA_CHN 0x00000300 +#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C3_TX_DMA_CHN 0x00030000 + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS FALSE +#define STM32_RTC_IS_CALENDAR TRUE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO TRUE +#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \ + STM32_DMA_STREAM_ID_MSK(2, 6)) +#define STM32_SDC_SDIO_DMA_CHN 0x04004000 + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \ + STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_SPI1_RX_DMA_CHN 0x00000303 +#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_SPI1_TX_DMA_CHN 0x00303000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) | \ + STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) | \ + STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 TRUE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 TRUE +#define STM32_HAS_TIM9 TRUE +#define STM32_HAS_TIM10 TRUE +#define STM32_HAS_TIM11 TRUE +#define STM32_HAS_TIM12 TRUE +#define STM32_HAS_TIM13 TRUE +#define STM32_HAS_TIM14 TRUE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) | \ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00400400 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 7)) +#define STM32_USART1_TX_DMA_CHN 0x40000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART2_RX_DMA_CHN 0x00400000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_TX_DMA_CHN 0x04000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) +#define STM32_USART3_RX_DMA_CHN 0x00000040 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) | \ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART3_TX_DMA_CHN 0x00074000 + +#define STM32_HAS_UART4 TRUE +#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_UART4_RX_DMA_CHN 0x00000400 +#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_UART4_TX_DMA_CHN 0x00040000 + +#define STM32_HAS_UART5 TRUE +#define STM32_UART5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0)) +#define STM32_UART5_RX_DMA_CHN 0x00000004 +#define STM32_UART5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_UART5_TX_DMA_CHN 0x40000000 + +#define STM32_HAS_USART6 TRUE +#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) | \ + STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_USART6_RX_DMA_CHN 0x00000550 +#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) | \ + STM32_DMA_STREAM_ID_MSK(2, 7)) +#define STM32_USART6_TX_DMA_CHN 0x55000000 + +/* USB attributes.*/ +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 TRUE +#define STM32_HAS_OTG2 TRUE +/** @} */ + +/*===========================================================================*/ +/* Platform specific friendly IRQ names. */ +/*===========================================================================*/ + +/** + * @name IRQ VECTOR names + * @{ + */ +#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ +#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line + detect. */ +#define TAMP_STAMP_IRQHandler Vector48 /**< Tamper and TimeStamp + through EXTI Line. */ +#define RTC_WKUP_IRQHandler Vector4C /**< RTC wakeup EXTI Line. */ +#define FLASH_IRQHandler Vector50 /**< Flash. */ +#define RCC_IRQHandler Vector54 /**< RCC. */ +#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ +#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ +#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ +#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ +#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ +#define DMA1_Stream0_IRQHandler Vector6C /**< DMA1 Stream 0. */ +#define DMA1_Stream1_IRQHandler Vector70 /**< DMA1 Stream 1. */ +#define DMA1_Stream2_IRQHandler Vector74 /**< DMA1 Stream 2. */ +#define DMA1_Stream3_IRQHandler Vector78 /**< DMA1 Stream 3. */ +#define DMA1_Stream4_IRQHandler Vector7C /**< DMA1 Stream 4. */ +#define DMA1_Stream5_IRQHandler Vector80 /**< DMA1 Stream 5. */ +#define DMA1_Stream6_IRQHandler Vector84 /**< DMA1 Stream 6. */ +#define ADC1_2_3_IRQHandler Vector88 /**< ADC1, ADC2 and ADC3. */ +#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */ +#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */ +#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ +#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ +#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ +#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ +#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ +#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and + Commutation. */ +#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ +#define TIM2_IRQHandler VectorB0 /**< TIM2. */ +#define TIM3_IRQHandler VectorB4 /**< TIM3. */ +#define TIM4_IRQHandler VectorB8 /**< TIM4. */ +#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ +#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ +#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ +#define I2C2_ER_IRQHandler VectorC8 /**< I2C1 Error. */ +#define SPI1_IRQHandler VectorCC /**< SPI1. */ +#define SPI2_IRQHandler VectorD0 /**< SPI2. */ +#define USART1_IRQHandler VectorD4 /**< USART1. */ +#define USART2_IRQHandler VectorD8 /**< USART2. */ +#define USART3_IRQHandler VectorDC /**< USART3. */ +#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ +#define RTC_Alarm_IRQHandler VectorE4 /**< RTC alarms (A and B) + through EXTI line. */ +#define OTG_FS_WKUP_IRQHandler VectorE8 /**< USB OTG FS Wakeup through + EXTI line. */ +#define TIM8_BRK_IRQHandler VectorEC /**< TIM8 Break. */ +#define TIM8_UP_IRQHandler VectorF0 /**< TIM8 Update. */ +#define TIM8_TRG_COM_IRQHandler VectorF4 /**< TIM8 Trigger and + Commutation. */ +#define TIM8_CC_IRQHandler VectorF8 /**< TIM8 Capture Compare. */ +#define DMA1_Stream7_IRQHandler VectorFC /**< DMA1 Stream 7. */ +#define FSMC_IRQHandler Vector100 /**< FSMC. */ +#define SDIO_IRQHandler Vector104 /**< SDIO. */ +#define TIM5_IRQHandler Vector108 /**< TIM5. */ +#define SPI3_IRQHandler Vector10C /**< SPI3. */ +#define UART4_IRQHandler Vector110 /**< UART4. */ +#define UART5_IRQHandler Vector114 /**< UART5. */ +#define TIM6_IRQHandler Vector118 /**< TIM6. */ +#define TIM7_IRQHandler Vector11C /**< TIM7. */ +#define DMA2_Stream0_IRQHandler Vector120 /**< DMA2 Stream0. */ +#define DMA2_Stream1_IRQHandler Vector124 /**< DMA2 Stream1. */ +#define DMA2_Stream2_IRQHandler Vector128 /**< DMA2 Stream2. */ +#define DMA2_Stream3_IRQHandler Vector12C /**< DMA2 Stream3. */ +#define DMA2_Stream4_IRQHandler Vector130 /**< DMA2 Stream4. */ +#define ETH_IRQHandler Vector134 /**< Ethernet. */ +#define ETH_WKUP_IRQHandler Vector138 /**< Ethernet Wakeup through + EXTI line. */ +#define CAN2_TX_IRQHandler Vector13C /**< CAN2 TX. */ +#define CAN2_RX0_IRQHandler Vector140 /**< CAN2 RX0. */ +#define CAN2_RX1_IRQHandler Vector144 /**< CAN2 RX1. */ +#define CAN2_SCE_IRQHandler Vector148 /**< CAN2 SCE. */ +#define OTG_FS_IRQHandler Vector14C /**< USB OTG FS. */ +#define DMA2_Stream5_IRQHandler Vector150 /**< DMA2 Stream5. */ +#define DMA2_Stream6_IRQHandler Vector154 /**< DMA2 Stream6. */ +#define DMA2_Stream7_IRQHandler Vector158 /**< DMA2 Stream7. */ +#define USART6_IRQHandler Vector15C /**< USART6. */ +#define I2C3_EV_IRQHandler Vector160 /**< I2C3 Event. */ +#define I2C3_ER_IRQHandler Vector164 /**< I2C3 Error. */ +#define OTG_HS_EP1_OUT_IRQHandler Vector168 /**< USB OTG HS End Point 1 Out.*/ +#define OTG_HS_EP1_IN_IRQHandler Vector16C /**< USB OTG HS End Point 1 In. */ +#define OTG_HS_WKUP_IRQHandler Vector170 /**< USB OTG HS Wakeup through + EXTI line. */ +#define OTG_HS_IRQHandler Vector174 /**< USB OTG HS. */ +#define DCMI_IRQHandler Vector178 /**< DCMI. */ +#define CRYP_IRQHandler Vector17C /**< CRYP. */ +#define HASH_RNG_IRQHandler Vector180 /**< Hash and Rng. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Disables the PWR/RCC initialization in the HAL. + */ +#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) +#define STM32_NO_INIT FALSE +#endif + +/** + * @brief Enables or disables the programmable voltage detector. + */ +#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__) +#define STM32_PVD_ENABLE FALSE +#endif + +/** + * @brief Sets voltage level for programmable voltage detector. + */ +#if !defined(STM32_PLS) || defined(__DOXYGEN__) +#define STM32_PLS STM32_PLS_LEV0 +#endif + +/** + * @brief Enables or disables the HSI clock source. + */ +#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSI_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the HSE clock source. + */ +#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSE_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSE clock source. + */ +#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSE_ENABLED FALSE +#endif + +/** + * @brief USB/SDIO clock setting. + */ +#if !defined(STM32_CLOCK48_REQUIRED) || defined(__DOXYGEN__) +#define STM32_CLOCK48_REQUIRED TRUE +#endif + +/** + * @brief Main clock source selection. + * @note If the selected clock source is not the PLL then the PLL is not + * initialized and started. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_SW) || defined(__DOXYGEN__) +#define STM32_SW STM32_SW_PLL +#endif + +/** + * @brief Clock source for the PLLs. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 120MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) +#define STM32_PLLSRC STM32_PLLSRC_HSE +#endif + +/** + * @brief PLLM divider value. + * @note The allowed values are 2..63. + * @note The default value is calculated for a 120MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLM_VALUE 8 +#endif + +/** + * @brief PLLN multiplier value. + * @note The allowed values are 192..432. + * @note The default value is calculated for a 120MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLN_VALUE 240 +#endif + +/** + * @brief PLLP divider value. + * @note The allowed values are 2, 4, 6, 8. + * @note The default value is calculated for a 120MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLP_VALUE 2 +#endif + +/** + * @brief PLLQ multiplier value. + * @note The allowed values are 2..15. + * @note The default value is calculated for a 120MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLQ_VALUE 5 +#endif + +/** + * @brief AHB prescaler value. + * @note The default value is calculated for a 120MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_HPRE) || defined(__DOXYGEN__) +#define STM32_HPRE STM32_HPRE_DIV1 +#endif + +/** + * @brief APB1 prescaler value. + */ +#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#endif + +/** + * @brief APB2 prescaler value. + */ +#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#endif + +/** + * @brief RTC clock source. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCSEL STM32_RTCSEL_LSE +#endif + +/** + * @brief RTC HSE prescaler value. + */ +#if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__) +#define STM32_RTCPRE_VALUE 8 +#endif + +/** + * @brief MC01 clock source value. + * @note The default value outputs HSI clock on MC01 pin. + */ +#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__) +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#endif + +/** + * @brief MC01 prescaler value. + * @note The default value outputs HSI clock on MC01 pin. + */ +#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__) +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#endif + +/** + * @brief MC02 clock source value. + * @note The default value outputs SYSCLK / 5 on MC02 pin. + */ +#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__) +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#endif + +/** + * @brief MC02 prescaler value. + * @note The default value outputs SYSCLK / 5 on MC02 pin. + */ +#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__) +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#endif + +/** + * @brief I2S clock source. + */ +#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__) +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#endif + +/** + * @brief PLLI2SN multiplier value. + * @note The allowed values are 192..432. + */ +#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLI2SN_VALUE 192 +#endif + +/** + * @brief PLLI2SR multiplier value. + * @note The allowed values are 2..7. + */ +#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLI2SR_VALUE 5 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** + * @brief Maximum frequency thresholds and wait states for flash access. + * @note The values are valid for 2.7V to 3.6V supply range. + */ +#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__) +#define STM32_0WS_THRESHOLD 30000000 +#define STM32_1WS_THRESHOLD 60000000 +#define STM32_2WS_THRESHOLD 90000000 +#define STM32_3WS_THRESHOLD 120000000 +#define STM32_4WS_THRESHOLD 0 +#define STM32_5WS_THRESHOLD 0 +#define STM32_6WS_THRESHOLD 0 +#define STM32_7WS_THRESHOLD 0 +#elif (STM32_VDD >= 240) && (STM32_VDD < 270) +#define STM32_0WS_THRESHOLD 24000000 +#define STM32_1WS_THRESHOLD 48000000 +#define STM32_2WS_THRESHOLD 72000000 +#define STM32_3WS_THRESHOLD 96000000 +#define STM32_4WS_THRESHOLD 120000000 +#define STM32_5WS_THRESHOLD 0 +#define STM32_6WS_THRESHOLD 0 +#define STM32_7WS_THRESHOLD 0 +#elif (STM32_VDD >= 210) && (STM32_VDD < 240) +#define STM32_0WS_THRESHOLD 18000000 +#define STM32_1WS_THRESHOLD 36000000 +#define STM32_2WS_THRESHOLD 54000000 +#define STM32_3WS_THRESHOLD 72000000 +#define STM32_4WS_THRESHOLD 90000000 +#define STM32_5WS_THRESHOLD 108000000 +#define STM32_6WS_THRESHOLD 120000000 +#define STM32_7WS_THRESHOLD 0 +#elif (STM32_VDD >= 180) && (STM32_VDD < 210) +#define STM32_0WS_THRESHOLD 16000000 +#define STM32_1WS_THRESHOLD 32000000 +#define STM32_2WS_THRESHOLD 48000000 +#define STM32_3WS_THRESHOLD 64000000 +#define STM32_4WS_THRESHOLD 80000000 +#define STM32_5WS_THRESHOLD 96000000 +#define STM32_6WS_THRESHOLD 112000000 +#define STM32_7WS_THRESHOLD 120000000 +#else +#error "invalid VDD voltage specified" +#endif + +/* + * HSI related checks. + */ +#if STM32_HSI_ENABLED +#else /* !STM32_HSI_ENABLED */ + +#if STM32_SW == STM32_SW_HSI +#error "HSI not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || \ + ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "HSI not enabled, required by STM32_MCO1SEL" +#endif + +#if (STM32_MCO2SEL == STM32_MCO2SEL_HSI) || \ + ((STM32_MCO2SEL == STM32_MCO2SEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "HSI not enabled, required by STM32_MCO2SEL" +#endif + +#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_I2SSRC" +#endif + +#endif /* !STM32_HSI_ENABLED */ + +/* + * HSE related checks. + */ +#if STM32_HSE_ENABLED + +#if STM32_HSECLK == 0 +#error "HSE frequency not defined" +#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) +#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" +#endif + +#else /* !STM32_HSE_ENABLED */ + +#if STM32_SW == STM32_SW_HSE +#error "HSE not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE) +#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCO1SEL == STM32_MCO1SEL_HSE) || \ + ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) +#error "HSE not enabled, required by STM32_MCO1SEL" +#endif + +#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || \ + ((STM32_MCO2SEL == STM32_MCO2SEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) +#error "HSE not enabled, required by STM32_MCO2SEL" +#endif + +#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE) +#error "HSE not enabled, required by STM32_I2SSRC" +#endif + +#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#error "HSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_HSE_ENABLED */ + +/* + * LSI related checks. + */ +#if STM32_LSI_ENABLED +#else /* !STM32_LSI_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSI +#error "LSI not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSI_ENABLED */ + +/* + * LSE related checks. + */ +#if STM32_LSE_ENABLED + +#if (STM32_LSECLK == 0) +#error "LSE frequency not defined" +#endif + +#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) +#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" +#endif + +#else /* !STM32_LSE_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSE +#error "LSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSE_ENABLED */ + +/** + * @brief STM32_PLLM field. + */ +#if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) || \ + defined(__DOXYGEN__) +#define STM32_PLLM (STM32_PLLM_VALUE << 0) +#else +#error "invalid STM32_PLLM_VALUE value specified" +#endif + +/** + * @brief PLLs input clock frequency. + */ +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE) +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLCLKIN (STM32_HSICLK / STM32_PLLM_VALUE) +#else +#error "invalid STM32_PLLSRC value specified" +#endif + +/* + * PLLs input frequency range check. + */ +#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX) +#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" +#endif + +/* + * PLL enable check. + */ +#if STM32_CLOCK48_REQUIRED || \ + (STM32_SW == STM32_SW_PLL) || \ + (STM32_MCO1SEL == STM32_MCO1SEL_PLL) || \ + (STM32_MCO2SEL == STM32_MCO2SEL_PLL) || \ + defined(__DOXYGEN__) +/** + * @brief PLL activation flag. + */ +#define STM32_ACTIVATE_PLL TRUE +#else +#define STM32_ACTIVATE_PLL FALSE +#endif + +/** + * @brief STM32_PLLN field. + */ +#if ((STM32_PLLN_VALUE >= 64) && (STM32_PLLN_VALUE <= 432)) || \ + defined(__DOXYGEN__) +#define STM32_PLLN (STM32_PLLN_VALUE << 6) +#else +#error "invalid STM32_PLLN_VALUE value specified" +#endif + +/** + * @brief STM32_PLLP field. + */ +#if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__) +#define STM32_PLLP (0 << 16) +#elif STM32_PLLP_VALUE == 4 +#define STM32_PLLP (1 << 16) +#elif STM32_PLLP_VALUE == 6 +#define STM32_PLLP (2 << 16) +#elif STM32_PLLP_VALUE == 8 +#define STM32_PLLP (3 << 16) +#else +#error "invalid STM32_PLLP_VALUE value specified" +#endif + +/** + * @brief STM32_PLLQ field. + */ +#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 15)) || \ + defined(__DOXYGEN__) +#define STM32_PLLQ (STM32_PLLQ_VALUE << 24) +#else +#error "invalid STM32_PLLQ_VALUE value specified" +#endif + +/** + * @brief PLL VCO frequency. + */ +#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE) + +/* + * PLL VCO frequency range check. + */ +#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX) +#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE) + +/* + * PLL output frequency range check. + */ +#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX) +#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)" +#endif + +/** + * @brief System clock source. + */ +#if STM32_NO_INIT || defined(__DOXYGEN__) +#define STM32_SYSCLK STM32_HSICLK +#elif (STM32_SW == STM32_SW_HSI) +#define STM32_SYSCLK STM32_HSICLK +#elif (STM32_SW == STM32_SW_HSE) +#define STM32_SYSCLK STM32_HSECLK +#elif (STM32_SW == STM32_SW_PLL) +#define STM32_SYSCLK STM32_PLLCLKOUT +#else +#error "invalid STM32_SW value specified" +#endif + +/* Check on the system clock.*/ +#if STM32_SYSCLK > STM32_SYSCLK_MAX +#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief AHB frequency. + */ +#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK (STM32_SYSCLK / 1) +#elif STM32_HPRE == STM32_HPRE_DIV2 +#define STM32_HCLK (STM32_SYSCLK / 2) +#elif STM32_HPRE == STM32_HPRE_DIV4 +#define STM32_HCLK (STM32_SYSCLK / 4) +#elif STM32_HPRE == STM32_HPRE_DIV8 +#define STM32_HCLK (STM32_SYSCLK / 8) +#elif STM32_HPRE == STM32_HPRE_DIV16 +#define STM32_HCLK (STM32_SYSCLK / 16) +#elif STM32_HPRE == STM32_HPRE_DIV64 +#define STM32_HCLK (STM32_SYSCLK / 64) +#elif STM32_HPRE == STM32_HPRE_DIV128 +#define STM32_HCLK (STM32_SYSCLK / 128) +#elif STM32_HPRE == STM32_HPRE_DIV256 +#define STM32_HCLK (STM32_SYSCLK / 256) +#elif STM32_HPRE == STM32_HPRE_DIV512 +#define STM32_HCLK (STM32_SYSCLK / 512) +#else +#error "invalid STM32_HPRE value specified" +#endif + +/* + * AHB frequency check. + */ +#if STM32_HCLK > STM32_SYSCLK_MAX +#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief APB1 frequency. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK1 (STM32_HCLK / 1) +#elif STM32_PPRE1 == STM32_PPRE1_DIV2 +#define STM32_PCLK1 (STM32_HCLK / 2) +#elif STM32_PPRE1 == STM32_PPRE1_DIV4 +#define STM32_PCLK1 (STM32_HCLK / 4) +#elif STM32_PPRE1 == STM32_PPRE1_DIV8 +#define STM32_PCLK1 (STM32_HCLK / 8) +#elif STM32_PPRE1 == STM32_PPRE1_DIV16 +#define STM32_PCLK1 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE1 value specified" +#endif + +/* + * APB1 frequency check. + */ +#if STM32_PCLK1 > STM32_PCLK1_MAX +#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" +#endif + +/** + * @brief APB2 frequency. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK2 (STM32_HCLK / 1) +#elif STM32_PPRE2 == STM32_PPRE2_DIV2 +#define STM32_PCLK2 (STM32_HCLK / 2) +#elif STM32_PPRE2 == STM32_PPRE2_DIV4 +#define STM32_PCLK2 (STM32_HCLK / 4) +#elif STM32_PPRE2 == STM32_PPRE2_DIV8 +#define STM32_PCLK2 (STM32_HCLK / 8) +#elif STM32_PPRE2 == STM32_PPRE2_DIV16 +#define STM32_PCLK2 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE2 value specified" +#endif + +/* + * APB2 frequency check. + */ +#if STM32_PCLK2 > STM32_PCLK2_MAX +#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" +#endif + +/* + * PLLI2S enable check. + */ +#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || defined(__DOXYGEN__) +/** + * @brief PLL activation flag. + */ +#define STM32_ACTIVATE_PLLI2S TRUE +#else +#define STM32_ACTIVATE_PLLI2S FALSE +#endif + +/** + * @brief STM32_PLLI2SN field. + */ +#if ((STM32_PLLI2SN_VALUE >= 192) && (STM32_PLLI2SN_VALUE <= 432)) || \ + defined(__DOXYGEN__) +#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6) +#else +#error "invalid STM32_PLLI2SN_VALUE value specified" +#endif + +/** + * @brief STM32_PLLI2SR field. + */ +#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) || \ + defined(__DOXYGEN__) +#define STM32_PLLI2SR (STM32_PLLI2SR_VALUE << 28) +#else +#error "invalid STM32_PLLI2SR_VALUE value specified" +#endif + +/** + * @brief PLL VCO frequency. + */ +#define STM32_PLLI2SVCO (STM32_PLLCLKIN * STM32_PLLI2SN_VALUE) + +/* + * PLLI2S VCO frequency range check. + */ +#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) || \ + (STM32_PLLI2SVCO > STM32_PLLVCO_MAX) +#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" +#endif + +/** + * @brief PLLI2S output clock frequency. + */ +#define STM32_PLLI2SCLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR) + +/* + * PLLI2S output frequency range check. + */ +#if STM32_PLLI2SCLKOUT > STM32_SPII2S_MAX +#error "STM32_PLLI2SCLKOUT outside acceptable range (STM32_SPII2S_MAX)" +#endif + +/** + * @brief MCO1 divider clock. + */ +#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__) +#define STM32_MCO1DIVCLK STM32_HSICLK +#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE +#define STM32_MCO1DIVCLK STM32_LSECLK +#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE +#define STM32_MCO1DIVCLK STM32_HSECLK +#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL +#define STM32_MCO1DIVCLK STM32_PLLCLKOUT +#else +#error "invalid STM32_MCO1SEL value specified" +#endif + +/** + * @brief MCO1 output pin clock. + */ +#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__) +#define STM32_MCO1CLK STM32_MCO1DIVCLK +#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2 +#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2) +#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3 +#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3) +#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4 +#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4) +#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5 +#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5) +#else +#error "invalid STM32_MCO1PRE value specified" +#endif + +/** + * @brief MCO2 divider clock. + */ +#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__) +#define STM32_MCO2DIVCLK STM32_HSECLK +#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL +#define STM32_MCO2DIVCLK STM32_PLLCLKOUT +#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK +#define STM32_MCO2DIVCLK STM32_SYSCLK +#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S +#define STM32_MCO2DIVCLK STM32_PLLI2S +#else +#error "invalid STM32_MCO2SEL value specified" +#endif + +/** + * @brief MCO2 output pin clock. + */ +#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__) +#define STM32_MCO2CLK STM32_MCO2DIVCLK +#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2 +#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2) +#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3 +#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3) +#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4 +#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4) +#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5 +#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5) +#else +#error "invalid STM32_MCO2PRE value specified" +#endif + +/** + * @brief RTC HSE divider setting. + */ +#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \ + defined(__DOXYGEN__) +#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16) +#else +#error "invalid STM32_RTCPRE value specified" +#endif + +/** + * @brief HSE divider toward RTC clock. + */ +#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \ + defined(__DOXYGEN__) +#define STM32_HSEDIVCLK (STM32_HSECLK / STM32_RTCPRE_VALUE) +#else +#error "invalid STM32_RTCPRE value specified" +#endif + +/** + * @brief RTC clock. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__) +#define STM32_RTCCLK 0 +#elif STM32_RTCSEL == STM32_RTCSEL_LSE +#define STM32_RTCCLK STM32_LSECLK +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM32_RTCCLK STM32_LSICLK +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM32_RTCCLK STM32_HSEDIVCLK +#else +#error "invalid STM32_RTCSEL value specified" +#endif + +/** + * @brief RTC HSE divider setting. + */ +#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \ + defined(__DOXYGEN__) +#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16) +#else +#error "invalid STM32_RTCPRE value specified" +#endif + +/** + * @brief 48MHz frequency. + */ +#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__) +#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE) +#else +#define STM32_PLL48CLK 0 +#endif + +/** + * @brief Timers 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14 clock. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK1 (STM32_PCLK1 * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK1 * 2) +#endif + +/** + * @brief Timers 1, 8 clock. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK2 (STM32_PCLK2 * 1) +#else +#define STM32_TIMCLK2 (STM32_PCLK2 * 2) +#endif + +/** + * @brief Flash settings. + */ +#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__) +#define STM32_FLASHBITS 0x00000000 +#elif STM32_HCLK <= STM32_1WS_THRESHOLD +#define STM32_FLASHBITS 0x00000001 +#elif STM32_HCLK <= STM32_2WS_THRESHOLD +#define STM32_FLASHBITS 0x00000002 +#elif STM32_HCLK <= STM32_3WS_THRESHOLD +#define STM32_FLASHBITS 0x00000003 +#elif STM32_HCLK <= STM32_4WS_THRESHOLD +#define STM32_FLASHBITS 0x00000004 +#elif STM32_HCLK <= STM32_5WS_THRESHOLD +#define STM32_FLASHBITS 0x00000005 +#elif STM32_HCLK <= STM32_6WS_THRESHOLD +#define STM32_FLASHBITS 0x00000006 +#else +#define STM32_FLASHBITS 0x00000007 +#endif + +/* There are differences in vector names in the various sub-families, + normalizing.*/ +#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn +#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn +#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn +#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn +#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn +#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing a system clock frequency. + */ +typedef uint32_t halclock_t; + +/** + * @brief Type of the realtime free counter value. + */ +typedef uint32_t halrtcnt_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the current value of the system free running counter. + * @note This service is implemented by returning the content of the + * DWT_CYCCNT register. + * + * @return The value of the system free running counter of + * type halrtcnt_t. + * + * @notapi + */ +#define hal_lld_get_counter_value() DWT_CYCCNT + +/** + * @brief Realtime counter frequency. + * @note The DWT_CYCCNT register is incremented directly by the system + * clock so this function returns STM32_HCLK. + * + * @return The realtime counter frequency of type halclock_t. + * + * @notapi + */ +#define hal_lld_get_counter_frequency() STM32_HCLK + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* STM32 DMA and RCC helpers.*/ +#include "stm32_dma.h" +#include "stm32_rcc.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void stm32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F2xx/platform.dox b/Project/os/hal/platforms/STM32F2xx/platform.dox new file mode 100644 index 0000000..d649b15 --- /dev/null +++ b/Project/os/hal/platforms/STM32F2xx/platform.dox @@ -0,0 +1,366 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup STM32F2xx_DRIVERS STM32F2xx Drivers + * @details This section describes all the supported drivers on the STM32F2xx + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup STM32F2xx_HAL STM32F2xx Initialization Support + * @details The STM32F2xx HAL support is responsible for system initialization. + * + * @section stm32f2xx_hal_1 Supported HW resources + * - PLL1. + * - PLL2. + * - RCC. + * - Flash. + * . + * @section stm32f2xx_hal_2 STM32F2xx HAL driver implementation features + * - PLL startup and stabilization. + * - Clock tree initialization. + * - Clock source selection. + * - Flash wait states initialization based on the selected clock options. + * - SYSTICK initialization based on current clock and kernel required rate. + * - DMA support initialization. + * . + * @ingroup STM32F2xx_DRIVERS + */ + +/** + * @defgroup STM32F2xx_ADC STM32F2xx ADC Support + * @details The STM32F2xx ADC driver supports the ADC peripherals using DMA + * channels for maximum performance. + * + * @section stm32f2xx_adc_1 Supported HW resources + * - ADC1. + * - ADC2. + * - ADC3. + * - DMA2. + * . + * @section stm32f2xx_adc_2 STM32F2xx ADC driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Streaming conversion using DMA for maximum performance. + * - Programmable ADC interrupt priority level. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - DMA and ADC errors detection. + * . + * @ingroup STM32F2xx_DRIVERS + */ + +/** + * @defgroup STM32F2xx_CAN STM32F2xx CAN Support + * @details The STM32F2xx CAN driver uses the CAN peripherals. + * + * @section stm32f2xx_can_1 Supported HW resources + * - bxCAN1. + * . + * @section stm32f2xx_can_2 STM32F2xx CAN driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Support for bxCAN sleep mode. + * - Programmable bxCAN interrupts priority level. + * . + * @ingroup STM32F2xx_DRIVERS + */ + +/** + * @defgroup STM32F2xx_EXT STM32F2xx EXT Support + * @details The STM32F2xx EXT driver uses the EXTI peripheral. + * + * @section stm32f2xx_ext_1 Supported HW resources + * - EXTI. + * . + * @section stm32f2xx_ext_2 STM32F2xx EXT driver implementation features + * - Each EXTI channel can be independently enabled and programmed. + * - Programmable EXTI interrupts priority level. + * - Capability to work as event sources (WFE) rather than interrupt sources. + * . + * @ingroup STM32F2xx_DRIVERS + */ + +/** + * @defgroup STM32F2xx_GPT STM32F2xx GPT Support + * @details The STM32F2xx GPT driver uses the TIMx peripherals. + * + * @section stm32f2xx_gpt_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * - TIM4. + * - TIM5. + * - TIM8. + * . + * @section stm32f2xx_gpt_2 STM32F2xx GPT driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F2xx_DRIVERS + */ + +/** + * @defgroup STM32F2xx_ICU STM32F2xx ICU Support + * @details The STM32F2xx ICU driver uses the TIMx peripherals. + * + * @section stm32f2xx_icu_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * - TIM4. + * - TIM5. + * - TIM8. + * . + * @section stm32f2xx_icu_2 STM32F2xx ICU driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F2xx_DRIVERS + */ + +/** + * @defgroup STM32F2xx_MAC STM32F2xx MAC Support + * @details The STM32F2xx MAC driver supports the ETH peripheral. + * + * @section stm32f2xx_mac_1 Supported HW resources + * - ETH. + * - PHY (external). + * . + * @section stm32f2xx_mac_2 STM32F2xx MAC driver implementation features + * - Dedicated DMA operations. + * - Support for checksum off-loading. + * . + * @ingroup STM32F2xx_DRIVERS + */ + +/** + * @defgroup STM32F2xx_PAL STM32F2xx PAL Support + * @details The STM32F2xx PAL driver uses the GPIO peripherals. + * + * @section stm32f2xx_pal_1 Supported HW resources + * - GPIOA. + * - GPIOB. + * - GPIOC. + * - GPIOD. + * - GPIOE. + * - GPIOF. + * - GPIOG. + * - GPIOH. + * - GPIOI. + * . + * @section stm32f2xx_pal_2 STM32F2xx PAL driver implementation features + * The PAL driver implementation fully supports the following hardware + * capabilities: + * - 16 bits wide ports. + * - Atomic set/reset functions. + * - Atomic set+reset function (atomic bus operations). + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section stm32f2xx_pal_3 Supported PAL setup modes + * The STM32F2xx PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_PULLUP. + * - @p PAL_MODE_INPUT_PULLDOWN. + * - @p PAL_MODE_INPUT_ANALOG. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * - @p PAL_MODE_OUTPUT_OPENDRAIN. + * - @p PAL_MODE_ALTERNATE (non standard). + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section stm32f2xx_pal_4 Suboptimal behavior + * The STM32F2xx GPIO is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Pad/port toggling operations are not atomic. + * - Pad/group mode setup is not atomic. + * . + * @ingroup STM32F2xx_DRIVERS + */ + +/** + * @defgroup STM32F2xx_PWM STM32F2xx PWM Support + * @details The STM32F2xx PWM driver uses the TIMx peripherals. + * + * @section stm32f2xx_pwm_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * - TIM4. + * - TIM5. + * - TIM8. + * . + * @section stm32f2xx_pwm_2 STM32F2xx PWM driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Four independent PWM channels per timer. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F2xx_DRIVERS + */ + +/** + * @defgroup STM32F2xx_SDC STM32F2xx SDC Support + * @details The STM32F2xx SDC driver uses the SDIO peripheral. + * + * @section stm32f2xx_sdc_1 Supported HW resources + * - SDIO. + * - DMA2. + * . + * @section stm32f2xx_sdc_2 STM32F4xx SDC driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Programmable interrupt priority. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * . + * @ingroup STM32F2xx_DRIVERS + */ + +/** + * @defgroup STM32F2xx_SERIAL STM32F2xx Serial Support + * @details The STM32F2xx Serial driver uses the USART/UART peripherals in a + * buffered, interrupt driven, implementation. + * + * @section stm32f2xx_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - USART1. + * - USART2. + * - USART3. + * - UART4. + * - UART5. + * - USART6. + * . + * @section stm32f2xx_serial_2 STM32F2xx Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART/USART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * - Programmable priority levels for each UART/USART. + * . + * @ingroup STM32F2xx_DRIVERS + */ + +/** + * @defgroup STM32F2xx_SPI STM32F2xx SPI Support + * @details The SPI driver supports the STM32F2xx SPI peripherals using DMA + * channels for maximum performance. + * + * @section stm32f2xx_spi_1 Supported HW resources + * - SPI1. + * - SPI2. + * - SPI3. + * - DMA1. + * - DMA2. + * . + * @section stm32f2xx_spi_2 STM32F2xx SPI driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each SPI can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable interrupt priority levels for each SPI. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - Programmable DMA error hook. + * . + * @ingroup STM32F2xx_DRIVERS + */ + +/** + * @defgroup STM32F2xx_UART STM32F2xx UART Support + * @details The UART driver supports the STM32F2xx USART peripherals using DMA + * channels for maximum performance. + * + * @section stm32f2xx_uart_1 Supported HW resources + * The UART driver can support any of the following hardware resources: + * - USART1. + * - USART2. + * - USART3. + * - DMA1. + * - DMA2. + * . + * @section stm32f2xx_uart_2 STM32F2xx UART driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART/USART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable interrupt priority levels for each UART/USART. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - Programmable DMA error hook. + * . + * @ingroup STM32F2xx_DRIVERS + */ + +/** + * @defgroup STM32F2xx_PLATFORM_DRIVERS STM32F2xx Platform Drivers + * @details Platform support drivers. Platform drivers do not implement HAL + * standard driver templates, their role is to support platform + * specific functionalities. + * + * @ingroup STM32F2xx_DRIVERS + */ + +/** + * @defgroup STM32F2xx_DMA STM32F2xx DMA Support + * @details This DMA helper driver is used by the other drivers in order to + * access the shared DMA resources in a consistent way. + * + * @section stm32f2xx_dma_1 Supported HW resources + * The DMA driver can support any of the following hardware resources: + * - DMA1. + * - DMA2. + * . + * @section stm32f2xx_dma_2 STM32F2xx DMA driver implementation features + * - Exports helper functions/macros to the other drivers that share the + * DMA resource. + * - Automatic DMA clock stop when not in use by any driver. + * - DMA streams and interrupt vectors sharing among multiple drivers. + * . + * @ingroup STM32F2xx_PLATFORM_DRIVERS + */ + +/** + * @defgroup STM32F2xx_RCC STM32F2xx RCC Support + * @details This RCC helper driver is used by the other drivers in order to + * access the shared RCC resources in a consistent way. + * + * @section stm32f2xx_rcc_1 Supported HW resources + * - RCC. + * . + * @section stm32f2xx_rcc_2 STM32F2xx RCC driver implementation features + * - Peripherals reset. + * - Peripherals clock enable. + * - Peripherals clock disable. + * . + * @ingroup STM32F2xx_PLATFORM_DRIVERS + */ diff --git a/Project/os/hal/platforms/STM32F2xx/platform.mk b/Project/os/hal/platforms/STM32F2xx/platform.mk new file mode 100644 index 0000000..1a32a68 --- /dev/null +++ b/Project/os/hal/platforms/STM32F2xx/platform.mk @@ -0,0 +1,20 @@ +# List of all the STM32F2xx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F2xx/stm32_dma.c \ + ${CHIBIOS}/os/hal/platforms/STM32F2xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32F2xx/adc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/i2c_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/uart_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F2xx \ + ${CHIBIOS}/os/hal/platforms/STM32 \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 diff --git a/Project/os/hal/platforms/STM32F2xx/stm32_dma.c b/Project/os/hal/platforms/STM32F2xx/stm32_dma.c new file mode 100644 index 0000000..b629167 --- /dev/null +++ b/Project/os/hal/platforms/STM32F2xx/stm32_dma.c @@ -0,0 +1,539 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F2xx/stm32_dma.c + * @brief Enhanced DMA helper driver code. + * + * @addtogroup STM32F2xx_DMA + * @details DMA sharing helper driver. In the STM32 the DMA streams are a + * shared resource, this driver allows to allocate and free DMA + * streams at runtime in order to allow all the other device + * drivers to coordinate the access to the resource. + * @note The DMA ISR handlers are all declared into this module because + * sharing, the various device drivers can associate a callback to + * ISRs when allocating streams. + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/* The following macro is only defined if some driver requiring DMA services + has been enabled.*/ +#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Mask of the DMA1 streams in @p dma_streams_mask. + */ +#define STM32_DMA1_STREAMS_MASK 0x000000FF + +/** + * @brief Mask of the DMA2 streams in @p dma_streams_mask. + */ +#define STM32_DMA2_STREAMS_MASK 0x0000FF00 + +/** + * @brief Post-reset value of the stream CR register. + */ +#define STM32_DMA_CR_RESET_VALUE 0x00000000 + +/** + * @brief Post-reset value of the stream FCR register. + */ +#define STM32_DMA_FCR_RESET_VALUE 0x00000021 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief DMA streams descriptors. + * @details This table keeps the association between an unique stream + * identifier and the involved physical registers. + * @note Don't use this array directly, use the appropriate wrapper macros + * instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc. + */ +const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { + {DMA1_Stream0, &DMA1->LIFCR, 0, 0, DMA1_Stream0_IRQn}, + {DMA1_Stream1, &DMA1->LIFCR, 6, 1, DMA1_Stream1_IRQn}, + {DMA1_Stream2, &DMA1->LIFCR, 16, 2, DMA1_Stream2_IRQn}, + {DMA1_Stream3, &DMA1->LIFCR, 22, 3, DMA1_Stream3_IRQn}, + {DMA1_Stream4, &DMA1->HIFCR, 0, 4, DMA1_Stream4_IRQn}, + {DMA1_Stream5, &DMA1->HIFCR, 6, 5, DMA1_Stream5_IRQn}, + {DMA1_Stream6, &DMA1->HIFCR, 16, 6, DMA1_Stream6_IRQn}, + {DMA1_Stream7, &DMA1->HIFCR, 22, 7, DMA1_Stream7_IRQn}, + {DMA2_Stream0, &DMA2->LIFCR, 0, 8, DMA2_Stream0_IRQn}, + {DMA2_Stream1, &DMA2->LIFCR, 6, 9, DMA2_Stream1_IRQn}, + {DMA2_Stream2, &DMA2->LIFCR, 16, 10, DMA2_Stream2_IRQn}, + {DMA2_Stream3, &DMA2->LIFCR, 22, 11, DMA2_Stream3_IRQn}, + {DMA2_Stream4, &DMA2->HIFCR, 0, 12, DMA2_Stream4_IRQn}, + {DMA2_Stream5, &DMA2->HIFCR, 6, 13, DMA2_Stream5_IRQn}, + {DMA2_Stream6, &DMA2->HIFCR, 16, 14, DMA2_Stream6_IRQn}, + {DMA2_Stream7, &DMA2->HIFCR, 22, 15, DMA2_Stream7_IRQn}, +}; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief DMA ISR redirector type. + */ +typedef struct { + stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ + void *dma_param; /**< @brief DMA callback parameter. */ +} dma_isr_redir_t; + +/** + * @brief Mask of the allocated streams. + */ +static uint32_t dma_streams_mask; + +/** + * @brief DMA IRQ redirectors. + */ +static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief DMA1 stream 0 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream0_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->LISR >> 0) & STM32_DMA_ISR_MASK; + DMA1->LIFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[0].dma_func) + dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream1_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->LISR >> 6) & STM32_DMA_ISR_MASK; + DMA1->LIFCR = STM32_DMA_ISR_MASK << 6; + if (dma_isr_redir[1].dma_func) + dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream2_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->LISR >> 16) & STM32_DMA_ISR_MASK; + DMA1->LIFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[2].dma_func) + dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream3_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->LISR >> 22) & STM32_DMA_ISR_MASK; + DMA1->LIFCR = STM32_DMA_ISR_MASK << 22; + if (dma_isr_redir[3].dma_func) + dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream4_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->HISR >> 0) & STM32_DMA_ISR_MASK; + DMA1->HIFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[4].dma_func) + dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->HISR >> 6) & STM32_DMA_ISR_MASK; + DMA1->HIFCR = STM32_DMA_ISR_MASK << 6; + if (dma_isr_redir[5].dma_func) + dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 6 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream6_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->HISR >> 16) & STM32_DMA_ISR_MASK; + DMA1->HIFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[6].dma_func) + dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 7 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream7_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->HISR >> 22) & STM32_DMA_ISR_MASK; + DMA1->HIFCR = STM32_DMA_ISR_MASK << 22; + if (dma_isr_redir[7].dma_func) + dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 0 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream0_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->LISR >> 0) & STM32_DMA_ISR_MASK; + DMA2->LIFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[8].dma_func) + dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream1_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->LISR >> 6) & STM32_DMA_ISR_MASK; + DMA2->LIFCR = STM32_DMA_ISR_MASK << 6; + if (dma_isr_redir[9].dma_func) + dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream2_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->LISR >> 16) & STM32_DMA_ISR_MASK; + DMA2->LIFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[10].dma_func) + dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream3_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->LISR >> 22) & STM32_DMA_ISR_MASK; + DMA2->LIFCR = STM32_DMA_ISR_MASK << 22; + if (dma_isr_redir[11].dma_func) + dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream4_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->HISR >> 0) & STM32_DMA_ISR_MASK; + DMA2->HIFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[12].dma_func) + dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->HISR >> 6) & STM32_DMA_ISR_MASK; + DMA2->HIFCR = STM32_DMA_ISR_MASK << 6; + if (dma_isr_redir[13].dma_func) + dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 6 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream6_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->HISR >> 16) & STM32_DMA_ISR_MASK; + DMA2->HIFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[14].dma_func) + dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 7 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream7_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->HISR >> 22) & STM32_DMA_ISR_MASK; + DMA2->HIFCR = STM32_DMA_ISR_MASK << 22; + if (dma_isr_redir[15].dma_func) + dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA helper initialization. + * + * @init + */ +void dmaInit(void) { + int i; + + dma_streams_mask = 0; + for (i = 0; i < STM32_DMA_STREAMS; i++) { + _stm32_dma_streams[i].stream->CR = 0; + dma_isr_redir[i].dma_func = NULL; + } + DMA1->LIFCR = 0xFFFFFFFF; + DMA1->HIFCR = 0xFFFFFFFF; + DMA2->LIFCR = 0xFFFFFFFF; + DMA2->HIFCR = 0xFFFFFFFF; +} + +/** + * @brief Allocates a DMA stream. + * @details The stream is allocated and, if required, the DMA clock enabled. + * The function also enables the IRQ vector associated to the stream + * and initializes its priority. + * @pre The stream must not be already in use or an error is returned. + * @post The stream is allocated and the default ISR handler redirected + * to the specified function. + * @post The stream ISR vector is enabled and its priority configured. + * @post The stream must be freed using @p dmaStreamRelease() before it can + * be reused with another peripheral. + * @post The stream is in its post-reset state. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] priority IRQ priority mask for the DMA stream + * @param[in] func handling function pointer, can be @p NULL + * @param[in] param a parameter to be passed to the handling function + * @return The operation status. + * @retval FALSE no error, stream taken. + * @retval TRUE error, stream already taken. + * + * @special + */ +bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param) { + + chDbgCheck(dmastp != NULL, "dmaAllocate"); + + /* Checks if the stream is already taken.*/ + if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) + return TRUE; + + /* Marks the stream as allocated.*/ + dma_isr_redir[dmastp->selfindex].dma_func = func; + dma_isr_redir[dmastp->selfindex].dma_param = param; + dma_streams_mask |= (1 << dmastp->selfindex); + + /* Enabling DMA clocks required by the current streams set.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) + rccEnableDMA1(FALSE); + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) + rccEnableDMA2(FALSE); + + /* Putting the stream in a safe state.*/ + dmaStreamDisable(dmastp); + dmastp->stream->CR = STM32_DMA_CR_RESET_VALUE; + dmastp->stream->FCR = STM32_DMA_FCR_RESET_VALUE; + + /* Enables the associated IRQ vector if a callback is defined.*/ + if (func != NULL) + nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); + + return FALSE; +} + +/** + * @brief Releases a DMA stream. + * @details The stream is freed and, if required, the DMA clock disabled. + * Trying to release a unallocated stream is an illegal operation + * and is trapped if assertions are enabled. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post The stream is again available. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { + + chDbgCheck(dmastp != NULL, "dmaRelease"); + + /* Check if the streams is not taken.*/ + chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, + "dmaRelease(), #1", "not allocated"); + + /* Disables the associated IRQ vector.*/ + nvicDisableVector(dmastp->vector); + + /* Marks the stream as not allocated.*/ + dma_streams_mask &= ~(1 << dmastp->selfindex); + + /* Shutting down clocks that are no more required, if any.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) + rccDisableDMA1(FALSE); + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) + rccDisableDMA2(FALSE); +} + +#endif /* STM32_DMA_REQUIRED */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F2xx/stm32_dma.h b/Project/os/hal/platforms/STM32F2xx/stm32_dma.h new file mode 100644 index 0000000..1f2c6e7 --- /dev/null +++ b/Project/os/hal/platforms/STM32F2xx/stm32_dma.h @@ -0,0 +1,458 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F2xx/stm32_dma.h + * @brief Enhanced-DMA helper driver header. + * @note This file requires definitions from the ST STM32F2xx header file + * stm32f2xx.h. + * + * @addtogroup STM32F2xx_DMA + * @{ + */ + +#ifndef _STM32_DMA_H_ +#define _STM32_DMA_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Total number of DMA streams. + * @note This is the total number of streams among all the DMA units. + */ +#define STM32_DMA_STREAMS 16 + +/** + * @brief Mask of the ISR bits passed to the DMA callback functions. + */ +#define STM32_DMA_ISR_MASK 0x3D + +/** + * @brief Returns the channel associated to the specified stream. + * + * @param[in] id the unique numeric stream identifier + * @param[in] c a stream/channel association word, one channel per + * nibble + * @return Returns the channel associated to the stream. + */ +#define STM32_DMA_GETCHANNEL(id, c) (((c) >> (((id) & 7) * 4)) & 7) + +/** + * @brief Returns an unique numeric identifier for a DMA stream. + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return An unique numeric stream identifier. + */ +#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 8) + (stream)) + +/** + * @brief Returns a DMA stream identifier mask. + * + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return A DMA stream identifier mask. + */ +#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ + (1 << STM32_DMA_STREAM_ID(dma, stream)) + +/** + * @brief Checks if a DMA stream unique identifier belongs to a mask. + * @param[in] id the stream numeric identifier + * @param[in] mask the stream numeric identifiers mask + * + * @retval The check result. + * @retval FALSE id does not belong to the mask. + * @retval TRUE id belongs to the mask. + */ +#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask))) + +/** + * @name DMA streams identifiers + * @{ + */ +/** + * @brief Returns a pointer to a stm32_dma_stream_t structure. + * + * @param[in] id the stream numeric identifier + * @return A pointer to the stm32_dma_stream_t constant structure + * associated to the DMA stream. + */ +#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) + +#define STM32_DMA1_STREAM0 STM32_DMA_STREAM(0) +#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(1) +#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(2) +#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(3) +#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(4) +#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(5) +#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(6) +#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(7) +#define STM32_DMA2_STREAM0 STM32_DMA_STREAM(8) +#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(9) +#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(10) +#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(11) +#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(12) +#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(13) +#define STM32_DMA2_STREAM6 STM32_DMA_STREAM(14) +#define STM32_DMA2_STREAM7 STM32_DMA_STREAM(15) +/** @} */ + +/** + * @name CR register constants common to all DMA types + * @{ + */ +#define STM32_DMA_CR_EN DMA_SxCR_EN +#define STM32_DMA_CR_TEIE DMA_SxCR_TEIE +#define STM32_DMA_CR_HTIE DMA_SxCR_HTIE +#define STM32_DMA_CR_TCIE DMA_SxCR_TCIE +#define STM32_DMA_CR_DIR_MASK DMA_SxCR_DIR +#define STM32_DMA_CR_DIR_P2M 0 +#define STM32_DMA_CR_DIR_M2P DMA_SxCR_DIR_0 +#define STM32_DMA_CR_DIR_M2M DMA_SxCR_DIR_1 +#define STM32_DMA_CR_CIRC DMA_SxCR_CIRC +#define STM32_DMA_CR_PINC DMA_SxCR_PINC +#define STM32_DMA_CR_MINC DMA_SxCR_MINC +#define STM32_DMA_CR_PSIZE_MASK DMA_SxCR_PSIZE +#define STM32_DMA_CR_PSIZE_BYTE 0 +#define STM32_DMA_CR_PSIZE_HWORD DMA_SxCR_PSIZE_0 +#define STM32_DMA_CR_PSIZE_WORD DMA_SxCR_PSIZE_1 +#define STM32_DMA_CR_MSIZE_MASK DMA_SxCR_MSIZE +#define STM32_DMA_CR_MSIZE_BYTE 0 +#define STM32_DMA_CR_MSIZE_HWORD DMA_SxCR_MSIZE_0 +#define STM32_DMA_CR_MSIZE_WORD DMA_SxCR_MSIZE_1 +#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_MSIZE_MASK | \ + STM32_DMA_CR_MSIZE_MASK) +#define STM32_DMA_CR_PL_MASK DMA_SxCR_PL +#define STM32_DMA_CR_PL(n) ((n) << 16) +/** @} */ + +/** + * @name CR register constants only found in STM32F2xx/STM32F4xx + * @{ + */ +#define STM32_DMA_CR_DMEIE DMA_SxCR_DMEIE +#define STM32_DMA_CR_PFCTRL DMA_SxCR_PFCTRL +#define STM32_DMA_CR_PINCOS DMA_SxCR_PINCOS +#define STM32_DMA_CR_DBM DMA_SxCR_DBM +#define STM32_DMA_CR_CT DMA_SxCR_CT +#define STM32_DMA_CR_PBURST_MASK DMA_SxCR_PBURST +#define STM32_DMA_CR_PBURST_SINGLE 0 +#define STM32_DMA_CR_PBURST_INCR4 DMA_SxCR_PBURST_0 +#define STM32_DMA_CR_PBURST_INCR8 DMA_SxCR_PBURST_1 +#define STM32_DMA_CR_PBURST_INCR16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) +#define STM32_DMA_CR_MBURST_MASK DMA_SxCR_MBURST +#define STM32_DMA_CR_MBURST_SINGLE 0 +#define STM32_DMA_CR_MBURST_INCR4 DMA_SxCR_MBURST_0 +#define STM32_DMA_CR_MBURST_INCR8 DMA_SxCR_MBURST_1 +#define STM32_DMA_CR_MBURST_INCR16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) +#define STM32_DMA_CR_CHSEL_MASK DMA_SxCR_CHSEL +#define STM32_DMA_CR_CHSEL(n) ((n) << 25) +/** @} */ + +/** + * @name FCR register constants only found in STM32F2xx/STM32F4xx + * @{ + */ +#define STM32_DMA_FCR_FEIE DMA_SxFCR_FEIE +#define STM32_DMA_FCR_FS_MASK DMA_SxFCR_FS +#define STM32_DMA_FCR_DMDIS DMA_SxFCR_DMDIS +#define STM32_DMA_FCR_FTH_MASK DMA_SxFCR_FTH +#define STM32_DMA_FCR_FTH_1Q 0 +#define STM32_DMA_FCR_FTH_HALF DMA_SxFCR_FTH_0 +#define STM32_DMA_FCR_FTH_3Q DMA_SxFCR_FTH_1 +#define STM32_DMA_FCR_FTH_FULL (DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1) +/** @} */ + +/** + * @name Status flags passed to the ISR callbacks + */ +#define STM32_DMA_ISR_FEIF DMA_LISR_FEIF0 +#define STM32_DMA_ISR_DMEIF DMA_LISR_DMEIF0 +#define STM32_DMA_ISR_TEIF DMA_LISR_TEIF0 +#define STM32_DMA_ISR_HTIF DMA_LISR_HTIF0 +#define STM32_DMA_ISR_TCIF DMA_LISR_TCIF0 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA stream descriptor structure. + */ +typedef struct { + DMA_Stream_TypeDef *stream; /**< @brief Associated DMA stream. */ + volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ + uint8_t ishift; /**< @brief Bits offset in xIFCR + register. */ + uint8_t selfindex; /**< @brief Index to self in array. */ + uint8_t vector; /**< @brief Associated IRQ vector. */ +} stm32_dma_stream_t; + +/** + * @brief STM32 DMA ISR function type. + * + * @param[in] p parameter for the registered function + * @param[in] flags pre-shifted content of the xISR register, the bits + * are aligned to bit zero + */ +typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Associates a peripheral data register to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the PAR register + * + * @special + */ +#define dmaStreamSetPeripheral(dmastp, addr) { \ + (dmastp)->stream->PAR = (uint32_t)(addr); \ +} + +/** + * @brief Associates a memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the M0AR register + * + * @special + */ +#define dmaStreamSetMemory0(dmastp, addr) { \ + (dmastp)->stream->M0AR = (uint32_t)(addr); \ +} + +/** + * @brief Associates an alternate memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the M1AR register + * + * @special + */ +#define dmaStreamSetMemory1(dmastp, addr) { \ + (dmastp)->stream->M1AR = (uint32_t)(addr); \ +} + +/** + * @brief Sets the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] size value to be written in the CNDTR register + * + * @special + */ +#define dmaStreamSetTransactionSize(dmastp, size) { \ + (dmastp)->stream->NDTR = (uint32_t)(size); \ +} + +/** + * @brief Returns the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @return The number of transfers to be performed. + * + * @special + */ +#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->stream->NDTR)) + +/** + * @brief Programs the stream mode settings. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CR register + * + * @special + */ +#define dmaStreamSetMode(dmastp, mode) { \ + (dmastp)->stream->CR = (uint32_t)(mode); \ +} + +/** + * @brief Programs the stream FIFO settings. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the FCR register + * + * @special + */ +#define dmaStreamSetFIFO(dmastp, mode) { \ + (dmastp)->stream->FCR = (uint32_t)(mode); \ +} + +/** + * @brief DMA stream enable. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamEnable(dmastp) { \ + (dmastp)->stream->CR |= STM32_DMA_CR_EN; \ +} + +/** + * @brief DMA stream disable. + * @details The function disables the specified stream, waits for the disable + * operation to complete and then clears any pending interrupt. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamDisable(dmastp) { \ + (dmastp)->stream->CR &= ~STM32_DMA_CR_EN; \ + while (((dmastp)->stream->CR & STM32_DMA_CR_EN) != 0) \ + ; \ + dmaStreamClearInterrupt(dmastp); \ +} + +/** + * @brief DMA stream interrupt sources clear. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamClearInterrupt(dmastp) { \ + *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ +} + +/** + * @brief Starts a memory to memory operation using the specified stream. + * @note The default transfer data mode is "byte to byte" but it can be + * changed by specifying extra options in the @p mode parameter. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register, this value + * is implicitly ORed with: + * - @p STM32_DMA_CR_MINC + * - @p STM32_DMA_CR_PINC + * - @p STM32_DMA_CR_DIR_M2M + * - @p STM32_DMA_CR_EN + * . + * @param[in] src source address + * @param[in] dst destination address + * @param[in] n number of data units to copy + */ +#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ + dmaStreamSetPeripheral(dmastp, src); \ + dmaStreamSetMemory0(dmastp, dst); \ + dmaStreamSetTransactionSize(dmastp, n); \ + dmaStreamSetMode(dmastp, (mode) | \ + STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ + STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ +} + +/** + * @brief Polled wait for DMA transfer end. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + */ +#define dmaWaitCompletion(dmastp) { \ + while ((dmastp)->stream->NDTR > 0) \ + ; \ + dmaStreamDisable(dmastp); \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void dmaInit(void); + bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param); + void dmaStreamRelease(const stm32_dma_stream_t *dmastp); +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_DMA_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F2xx/stm32_rcc.h b/Project/os/hal/platforms/STM32F2xx/stm32_rcc.h new file mode 100644 index 0000000..848333e --- /dev/null +++ b/Project/os/hal/platforms/STM32F2xx/stm32_rcc.h @@ -0,0 +1,1078 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F2xx/stm32_rcc.h + * @brief RCC helper driver header. + * @note This file requires definitions from the ST header file + * @p stm32f2xx.h. + * + * @addtogroup STM32F2xx_RCC + * @{ + */ +#ifndef _STM32_RCC_ +#define _STM32_RCC_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic RCC operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB1(mask, lp) { \ + RCC->APB1ENR |= (mask); \ + if (lp) \ + RCC->APB1LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB1(mask, lp) { \ + RCC->APB1ENR &= ~(mask); \ + if (lp) \ + RCC->APB1LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * + * @api + */ +#define rccResetAPB1(mask) { \ + RCC->APB1RSTR |= (mask); \ + RCC->APB1RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB2(mask, lp) { \ + RCC->APB2ENR |= (mask); \ + if (lp) \ + RCC->APB2LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB2(mask, lp) { \ + RCC->APB2ENR &= ~(mask); \ + if (lp) \ + RCC->APB2LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * + * @api + */ +#define rccResetAPB2(mask) { \ + RCC->APB2RSTR |= (mask); \ + RCC->APB2RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB1 bus. + * + * @param[in] mask AHB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB1(mask, lp) { \ + RCC->AHB1ENR |= (mask); \ + if (lp) \ + RCC->AHB1LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB1 bus. + * + * @param[in] mask AHB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB1(mask, lp) { \ + RCC->AHB1ENR &= ~(mask); \ + if (lp) \ + RCC->AHB1LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB1 bus. + * + * @param[in] mask AHB1 peripherals mask + * + * @api + */ +#define rccResetAHB1(mask) { \ + RCC->AHB1RSTR |= (mask); \ + RCC->AHB1RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB2 bus. + * + * @param[in] mask AHB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB2(mask, lp) { \ + RCC->AHB2ENR |= (mask); \ + if (lp) \ + RCC->AHB2LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB2 bus. + * + * @param[in] mask AHB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB2(mask, lp) { \ + RCC->AHB2ENR &= ~(mask); \ + if (lp) \ + RCC->AHB2LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB2 bus. + * + * @param[in] mask AHB2 peripherals mask + * + * @api + */ +#define rccResetAHB2(mask) { \ + RCC->AHB2RSTR |= (mask); \ + RCC->AHB2RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus. + * + * @param[in] mask AHB3 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB3(mask, lp) { \ + RCC->AHB3ENR |= (mask); \ + if (lp) \ + RCC->AHB3LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus. + * + * @param[in] mask AHB3 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB3(mask, lp) { \ + RCC->AHB3ENR &= ~(mask); \ + if (lp) \ + RCC->AHB3LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB3 (FSMC) bus. + * + * @param[in] mask AHB3 peripherals mask + * + * @api + */ +#define rccResetAHB3(mask) { \ + RCC->AHB3RSTR |= (mask); \ + RCC->AHB3RSTR = 0; \ +} +/** @} */ + +/** + * @name ADC peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the ADC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Disables the ADC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Resets the ADC1 peripheral. + * + * @api + */ +#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) + +/** + * @brief Enables the ADC2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC2(lp) rccEnableAPB2(RCC_APB2ENR_ADC2EN, lp) + +/** + * @brief Disables the ADC2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC2(lp) rccDisableAPB2(RCC_APB2ENR_ADC2EN, lp) + +/** + * @brief Resets the ADC2 peripheral. + * + * @api + */ +#define rccResetADC2() rccResetAPB2(RCC_APB2RSTR_ADC2RST) + +/** + * @brief Enables the ADC3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC3(lp) rccEnableAPB2(RCC_APB2ENR_ADC3EN, lp) + +/** + * @brief Disables the ADC3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC3(lp) rccDisableAPB2(RCC_APB2ENR_ADC3EN, lp) + +/** + * @brief Resets the ADC3 peripheral. + * + * @api + */ +#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST) +/** @} */ + +/** + * @name DMA peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp) + +/** + * @brief Disables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA1(lp) rccDisableAHB1(RCC_AHB1ENR_DMA1EN, lp) + +/** + * @brief Resets the DMA1 peripheral. + * + * @api + */ +#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST) + +/** + * @brief Enables the DMA2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp) + +/** + * @brief Disables the DMA2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA2(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2EN, lp) + +/** + * @brief Resets the DMA2 peripheral. + * + * @api + */ +#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST) +/** @} */ + +/** + * @name PWR interface specific RCC operations + * @{ + */ +/** + * @brief Enables the PWR interface clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Disables PWR interface clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Resets the PWR interface. + * + * @api + */ +#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST) +/** @} */ + + +/** + * @name CAN peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the CAN1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp) + +/** + * @brief Disables the CAN1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp) + +/** + * @brief Resets the CAN1 peripheral. + * + * @api + */ +#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST) + +/** + * @brief Enables the CAN2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableCAN2(lp) rccEnableAPB1(RCC_APB1ENR_CAN2EN, lp) + +/** + * @brief Disables the CAN2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableCAN2(lp) rccDisableAPB1(RCC_APB1ENR_CAN2EN, lp) + +/** + * @brief Resets the CAN2 peripheral. + * + * @api + */ +#define rccResetCAN2() rccResetAPB1(RCC_APB1RSTR_CAN2RST) +/** @} */ + +/** + * @name ETH peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the ETH peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN | \ + RCC_AHB1ENR_ETHMACTXEN | \ + RCC_AHB1ENR_ETHMACRXEN, lp) + +/** + * @brief Disables the ETH peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableETH(lp) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \ + RCC_AHB1ENR_ETHMACTXEN | \ + RCC_AHB1ENR_ETHMACRXEN, lp) + +/** + * @brief Resets the ETH peripheral. + * + * @api + */ +#define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETHMACRST) +/** @} */ + +/** + * @name I2C peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Disables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Resets the I2C1 peripheral. + * + * @api + */ +#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) + +/** + * @brief Enables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Disables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Resets the I2C2 peripheral. + * + * @api + */ +#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) + +/** + * @brief Enables the I2C3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C3(lp) rccEnableAPB1(RCC_APB1ENR_I2C3EN, lp) + +/** + * @brief Disables the I2C3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C3(lp) rccDisableAPB1(RCC_APB1ENR_I2C3EN, lp) + +/** + * @brief Resets the I2C3 peripheral. + * + * @api + */ +#define rccResetI2C3() rccResetAPB1(RCC_APB1RSTR_I2C3RST) +/** @} */ + +/** + * @name OTG peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the OTG_FS peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2LPENR_OTGFSLPEN, lp) + +/** + * @brief Disables the OTG_FS peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableOTG_FS(lp) rccEnableAHB2(RCC_AHB2LPENR_OTGFSLPEN, lp) + +/** + * @brief Resets the OTG_FS peripheral. + * + * @api + */ +#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST) +/** @} */ + +/** + * @name SDIO peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the SDIO peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSDIO(lp) rccEnableAPB2(RCC_APB2ENR_SDIOEN, lp) + +/** + * @brief Disables the SDIO peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSDIO(lp) rccDisableAPB2(RCC_APB2ENR_SDIOEN, lp) + +/** + * @brief Resets the SDIO peripheral. + * @note Not supported in this family, does nothing. + * + * @api + */ +#define rccResetSDIO() rccResetAPB2(RCC_APB2RSTR_SDIORST) +/** @} */ + +/** + * @name SPI peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Disables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Resets the SPI1 peripheral. + * + * @api + */ +#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) + +/** + * @brief Enables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Disables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Resets the SPI2 peripheral. + * + * @api + */ +#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) + +/** + * @brief Enables the SPI3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp) + +/** + * @brief Disables the SPI3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp) + +/** + * @brief Resets the SPI3 peripheral. + * + * @api + */ +#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST) +/** @} */ + +/** + * @name TIM peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Disables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Resets the TIM1 peripheral. + * + * @api + */ +#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST) + +/** + * @brief Enables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Disables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Resets the TIM2 peripheral. + * + * @api + */ +#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) + +/** + * @brief Enables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Disables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Resets the TIM3 peripheral. + * + * @api + */ +#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) + +/** + * @brief Enables the TIM4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Disables the TIM4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Resets the TIM4 peripheral. + * + * @api + */ +#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST) + +/** + * @brief Enables the TIM5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp) + +/** + * @brief Disables the TIM5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp) + +/** + * @brief Resets the TIM5 peripheral. + * + * @api + */ +#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST) + +/** + * @brief Enables the TIM8 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp) + +/** + * @brief Disables the TIM8 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp) + +/** + * @brief Resets the TIM8 peripheral. + * + * @api + */ +#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST) +/** @} */ + +/** + * @name USART/UART peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Disables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) + +/** + * @brief Enables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Disables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Resets the USART2 peripheral. + * + * @api + */ +#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) + +/** + * @brief Enables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Disables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Resets the USART3 peripheral. + * + * @api + */ +#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST) + +/** + * @brief Enables the USART6 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp) + +/** + * @brief Disables the USART6 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART6(lp) rccDisableAPB2(RCC_APB2ENR_USART6EN, lp) + +/** + * @brief Enables the UART4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp) + +/** + * @brief Disables the UART4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp) + +/** + * @brief Resets the UART4 peripheral. + * + * @api + */ +#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST) + +/** + * @brief Enables the UART5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp) + +/** + * @brief Disables the UART5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp) + +/** + * @brief Resets the UART5 peripheral. + * + * @api + */ +#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST) + +/** + * @brief Resets the USART6 peripheral. + * + * @api + */ +#define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_RCC_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F2xx/stm32f2xx.h b/Project/os/hal/platforms/STM32F2xx/stm32f2xx.h new file mode 100644 index 0000000..6409ba1 --- /dev/null +++ b/Project/os/hal/platforms/STM32F2xx/stm32f2xx.h @@ -0,0 +1,6878 @@ +/** + ****************************************************************************** + * @file stm32f2xx.h + * @author MCD Application Team + * @version V1.0.0 + * @date 18-April-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F2xx devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx + * @{ + */ + +#ifndef __STM32F2xx_H +#define __STM32F2xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F2XX) + #define STM32F2XX +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (STM32F2XX) + #error "Please select first the target STM32F2XX device used in your application (in stm32f2xx.h file)" +#endif + +#if !defined (USE_STDPERIPH_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ + +/** + * @brief STM32F2Xxx Standard Peripherals Library version number V1.0.0 + */ +#define __STM32F2XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F2XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32F2XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F2XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F2XX_STDPERIPH_VERSION ((__STM32F2XX_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F2XX_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F2XX_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F2XX_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __MPU_PRESENT 1 /*!< STM32F2XX provide an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F2XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @brief STM32F2XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80 /*!< Hash and Rng global interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +/* CHIBIOS FIX */ +/* #include "system_stm32f2xx.h" */ +#include + +/** @addtogroup Exported_types + * @{ + */ +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RESERVED8; + __IO uint32_t PTPTSSR; /* added for STM32F2xx */ + uint32_t RESERVED9[565]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARSWTR; /* added for STM32F2xx */ + uint32_t RESERVED10[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */ +} FLASH_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FSMC_Bank2_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FSMC_Bank3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ + __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ + __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ + __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ + __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ +} FSMC_Bank4_TypeDef; + +/** + * @brief General Purpose I/O + */ +/* CHIBIOS FIX */ +#if 0 +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ + __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x24-0x28 */ +} GPIO_TypeDef; +#endif + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + uint32_t RESERVED3; /*!< Reserved, 0x38 */ + uint32_t RESERVED4; /*!< Reserved, 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + uint32_t RESERVED5; /*!< Reserved, 0x44 */ + uint32_t RESERVED6; /*!< Reserved, 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + uint16_t RESERVED11; /*!< Reserved, 0x46 */ + __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + uint16_t RESERVED12; /*!< Reserved, 0x4A */ + __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint16_t RESERVED13; /*!< Reserved, 0x4E */ + __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ + uint16_t RESERVED14; /*!< Reserved, 0x52 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief Crypto Processor + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ +} CRYP_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */ +} HASH_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) +#define BKPSRAM_BASE (AHB1PERIPH_BASE + 0x4000) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) +#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) +#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) + +/*!< FSMC Bankx registers base address */ +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t )0xE0042000) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) +#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint8_t)0x01) /*!. + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F4xx/adc_lld.c + * @brief STM32F4xx ADC subsystem low level driver source. + * + * @addtogroup ADC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define ADC1_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN) + +#define ADC2_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_CHN) + +#define ADC3_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_CHN) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ADC1 driver identifier.*/ +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +ADCDriver ADCD1; +#endif + +/** @brief ADC2 driver identifier.*/ +#if STM32_ADC_USE_ADC2 || defined(__DOXYGEN__) +ADCDriver ADCD2; +#endif + +/** @brief ADC3 driver identifier.*/ +#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__) +ADCDriver ADCD3; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief ADC DMA ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { + + /* DMA errors handling.*/ + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + /* DMA, this could help only if the DMA tries to access an unmapped + address space or violates alignment rules.*/ + _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); + } + else { + /* It is possible that the conversion group has already be reset by the + ADC error handler, in this case this interrupt is spurious.*/ + if (adcp->grpp != NULL) { + if ((flags & STM32_DMA_ISR_HTIF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + if ((flags & STM32_DMA_ISR_TCIF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } + } + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 || STM32_ADC_USE_ADC3 || \ + defined(__DOXYGEN__) +/** + * @brief ADC interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) { + uint32_t sr; + + CH_IRQ_PROLOGUE(); + +#if STM32_ADC_USE_ADC1 + sr = ADC1->SR; + ADC1->SR = 0; + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + if (ADCD1.grpp != NULL) + _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW); + } + /* TODO: Add here analog watchdog handling.*/ +#endif /* STM32_ADC_USE_ADC1 */ + +#if STM32_ADC_USE_ADC2 + sr = ADC2->SR; + ADC2->SR = 0; + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD2.dmastp) > 0)) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + if (ADCD2.grpp != NULL) + _adc_isr_error_code(&ADCD2, ADC_ERR_OVERFLOW); + } + /* TODO: Add here analog watchdog handling.*/ +#endif /* STM32_ADC_USE_ADC2 */ + +#if STM32_ADC_USE_ADC3 + sr = ADC3->SR; + ADC3->SR = 0; + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD3.dmastp) > 0)) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + if (ADCD3.grpp != NULL) + _adc_isr_error_code(&ADCD3, ADC_ERR_OVERFLOW); + } + /* TODO: Add here analog watchdog handling.*/ +#endif /* STM32_ADC_USE_ADC3 */ + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +#if STM32_ADC_USE_ADC1 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); + ADCD1.adc = ADC1; + ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM); + ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; +#endif + +#if STM32_ADC_USE_ADC2 + /* Driver initialization.*/ + adcObjectInit(&ADCD2); + ADCD2.adc = ADC2; + ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM); + ADCD2.dmamode = STM32_DMA_CR_CHSEL(ADC2_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; +#endif + +#if STM32_ADC_USE_ADC3 + /* Driver initialization.*/ + adcObjectInit(&ADCD3); + ADCD3.adc = ADC3; + ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM); + ADCD3.dmamode = STM32_DMA_CR_CHSEL(ADC3_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; +#endif + + /* The shared vector is initialized on driver initialization and never + disabled.*/ + nvicEnableVector(ADC_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY)); +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + /* If in stopped state then enables the ADC and DMA clocks.*/ + if (adcp->state == ADC_STOP) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC1_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); + rccEnableADC1(FALSE); + } +#endif /* STM32_ADC_USE_ADC1 */ + +#if STM32_ADC_USE_ADC2 + if (&ADCD2 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC2_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR); + rccEnableADC2(FALSE); + } +#endif /* STM32_ADC_USE_ADC2 */ + +#if STM32_ADC_USE_ADC3 + if (&ADCD3 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC3_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #3", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR); + rccEnableADC3(FALSE); + } +#endif /* STM32_ADC_USE_ADC3 */ + + /* This is a common register but apparently it requires that at least one + of the ADCs is clocked in order to allow writing, see bug 3575297.*/ + ADC->CCR = STM32_ADC_ADCPRE << 16; + + /* ADC initial setup, starting the analog part here in order to reduce + the latency when starting a conversion.*/ + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + adcp->adc->CR2 = ADC_CR2_ADON; + } +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + /* If in ready state then disables the ADC clock.*/ + if (adcp->state == ADC_READY) { + dmaStreamRelease(adcp->dmastp); + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) + rccDisableADC1(FALSE); +#endif + +#if STM32_ADC_USE_ADC2 + if (&ADCD2 == adcp) + rccDisableADC2(FALSE); +#endif + +#if STM32_ADC_USE_ADC3 + if (&ADCD3 == adcp) + rccDisableADC3(FALSE); +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + uint32_t mode; + const ADCConversionGroup *grpp = adcp->grpp; + + /* DMA setup.*/ + mode = adcp->dmamode; + if (grpp->circular) { + mode |= STM32_DMA_CR_CIRC; + } + if (adcp->depth > 1) { + /* If the buffer depth is greater than one then the half transfer interrupt + interrupt is enabled in order to allows streaming processing.*/ + mode |= STM32_DMA_CR_HTIE; + } + dmaStreamSetMemory0(adcp->dmastp, adcp->samples); + dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * + (uint32_t)adcp->depth); + dmaStreamSetMode(adcp->dmastp, mode); + dmaStreamEnable(adcp->dmastp); + + /* ADC setup.*/ + adcp->adc->SR = 0; + adcp->adc->SMPR1 = grpp->smpr1; + adcp->adc->SMPR2 = grpp->smpr2; + adcp->adc->SQR1 = grpp->sqr1; + adcp->adc->SQR2 = grpp->sqr2; + adcp->adc->SQR3 = grpp->sqr3; + + /* ADC configuration and start, the start is performed using the method + specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/ + adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN; + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT | ADC_CR2_DMA | + ADC_CR2_DDS | ADC_CR2_ADON; +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + dmaStreamDisable(adcp->dmastp); + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + adcp->adc->CR2 = ADC_CR2_ADON; +} + +/** + * @brief Enables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + */ +void adcSTM32EnableTSVREFE(void) { + + ADC->CCR |= ADC_CCR_TSVREFE; +} + +/** + * @brief Disables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + */ +void adcSTM32DisableTSVREFE(void) { + + ADC->CCR &= ~ADC_CCR_TSVREFE; +} + +/** + * @brief Enables the VBATE bit. + * @details The VBATE bit is required in order to sample the VBAT channel. + * @note This is an STM32-only functionality. + */ +void adcSTM32EnableVBATE(void) { + + ADC->CCR |= ADC_CCR_VBATE; +} + +/** + * @brief Disables the VBATE bit. + * @details The VBATE bit is required in order to sample the VBAT channel. + * @note This is an STM32-only functionality. + */ +void adcSTM32DisableVBATE(void) { + + ADC->CCR &= ~ADC_CCR_VBATE; +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F4xx/adc_lld.h b/Project/os/hal/platforms/STM32F4xx/adc_lld.h new file mode 100644 index 0000000..cb7f84b --- /dev/null +++ b/Project/os/hal/platforms/STM32F4xx/adc_lld.h @@ -0,0 +1,574 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F4xx/adc_lld.h + * @brief STM32F4xx ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Minimum ADC clock frequency. + */ +#define STM32_ADCCLK_MIN 600000 + +/** + * @brief Maximum ADC clock frequency. + */ +#define STM32_ADCCLK_MAX 36000000 +/** @} */ + +/** + * @name Triggers selection + * @{ + */ +#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */ +/** @} */ + +/** + * @name ADC clock divider settings + * @{ + */ +#define ADC_CCR_ADCPRE_DIV2 0 +#define ADC_CCR_ADCPRE_DIV4 1 +#define ADC_CCR_ADCPRE_DIV6 2 +#define ADC_CCR_ADCPRE_DIV8 3 +/** @} */ + +/** + * @name Available analog channels + * @{ + */ +#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ +#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ +#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ +#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ +#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ +#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ +#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ +#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ +#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ +#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ +#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ +#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ +#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ +#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ +#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ +#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ +#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor. + @note Available onADC1 only. */ +#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. + @note Available onADC1 only. */ +#define ADC_CHANNEL_VBAT 18 /**< @brief VBAT. + @note Available onADC1 only. */ +/** @} */ + +/** + * @name Sampling rates + * @{ + */ +#define ADC_SAMPLE_3 0 /**< @brief 3 cycles sampling time. */ +#define ADC_SAMPLE_15 1 /**< @brief 15 cycles sampling time. */ +#define ADC_SAMPLE_28 2 /**< @brief 28 cycles sampling time. */ +#define ADC_SAMPLE_56 3 /**< @brief 56 cycles sampling time. */ +#define ADC_SAMPLE_84 4 /**< @brief 84 cycles sampling time. */ +#define ADC_SAMPLE_112 5 /**< @brief 112 cycles sampling time. */ +#define ADC_SAMPLE_144 6 /**< @brief 144 cycles sampling time. */ +#define ADC_SAMPLE_480 7 /**< @brief 480 cycles sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ADC common clock divider. + * @note This setting is influenced by the VDDA voltage and other + * external conditions, please refer to the STM32F4xx datasheet + * for more info.
+ * See section 5.3.20 "12-bit ADC characteristics". + */ +#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__) +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2 +#endif + +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC1 TRUE +#endif + +/** + * @brief ADC2 driver enable switch. + * @details If set to @p TRUE the support for ADC2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC2) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC2 TRUE +#endif + +/** + * @brief ADC3 driver enable switch. + * @details If set to @p TRUE the support for ADC3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC3 TRUE +#endif + +/** + * @brief DMA stream used for ADC1 operations. + */ +#if !defined(STM32_ADC_ADC1_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#endif + +/** + * @brief DMA stream used for ADC2 operations. + */ +#if !defined(STM32_ADC_ADC2_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#endif + +/** + * @brief DMA stream used for ADC3 operations. + */ +#if !defined(STM32_ADC_ADC3_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#endif + +/** + * @brief ADC1 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC2 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC3 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC interrupt priority level setting. + * @note This setting is shared among ADC1, ADC2 and ADC3 because + * all ADCs share the same vector. + */ +#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC1 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC2 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC3 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 +#error "ADC1 not present in the selected device" +#endif + +#if STM32_ADC_USE_ADC2 && !STM32_HAS_ADC2 +#error "ADC2 not present in the selected device" +#endif + +#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3 +#error "ADC3 not present in the selected device" +#endif + +#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && !STM32_ADC_USE_ADC3 +#error "ADC driver activated but no ADC peripheral assigned" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_MSK) +#error "invalid DMA stream associated to ADC1" +#endif + +#if STM32_ADC_USE_ADC2 && \ + !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_MSK) +#error "invalid DMA stream associated to ADC2" +#endif + +#if STM32_ADC_USE_ADC3 && \ + !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_MSK) +#error "invalid DMA stream associated to ADC3" +#endif + +/* ADC clock related settings and checks.*/ +#if STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV2 +#define STM32_ADCCLK (STM32_PCLK2 / 2) +#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV4 +#define STM32_ADCCLK (STM32_PCLK2 / 4) +#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV6 +#define STM32_ADCCLK (STM32_PCLK2 / 6) +#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV8 +#define STM32_ADCCLK (STM32_PCLK2 / 8) +#else +#error "invalid STM32_ADC_ADCPRE value specified" +#endif + +#if (STM32_ADCCLK < STM32_ADCCLK_MIN) || (STM32_ADCCLK > STM32_ADCCLK_MAX) +#error "STM32_ADCCLK outside acceptable range (STM32_ADCCLK_MIN...STM32_ADCCLK_MAX)" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ + ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */ +} adcerror_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief ADC error callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] err ADC error code + */ +typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note The use of this configuration structure requires knowledge of + * STM32 ADC cell registers interface, please refer to the STM32 + * reference manual for details. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool_t circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /** + * @brief Error callback or @p NULL. + */ + adcerrorcallback_t error_cb; + /* End of the mandatory fields.*/ + /** + * @brief ADC CR1 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR1_SCAN that is enforced inside the driver. + */ + uint32_t cr1; + /** + * @brief ADC CR2 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are + * enforced inside the driver. + */ + uint32_t cr2; + /** + * @brief ADC SMPR1 register initialization data. + * @details In this field must be specified the sample times for channels + * 10...18. + */ + uint32_t smpr1; + /** + * @brief ADC SMPR2 register initialization data. + * @details In this field must be specified the sample times for channels + * 0...9. + */ + uint32_t smpr2; + /** + * @brief ADC SQR1 register initialization data. + * @details Conversion group sequence 13...16 + sequence length. + */ + uint32_t sqr1; + /** + * @brief ADC SQR2 register initialization data. + * @details Conversion group sequence 7...12. + */ + uint32_t sqr2; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 1...6. + */ + uint32_t sqr3; +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the ADCx registers block. + */ + ADC_TypeDef *adc; + /** + * @brief Pointer to associated SMA channel. + */ + const stm32_dma_stream_t *dmastp; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Sequences building helper macros + * @{ + */ +/** + * @brief Number of channels in a conversion sequence. + */ +#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) + +#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ +#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ +#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ +#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ +#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ +#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ + +#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ +#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ +#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ +#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ +#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ +#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ + +#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ +#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ +#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ +#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ +/** @} */ + +/** + * @name Sampling rate settings helper macros + * @{ + */ +#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ +#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ + +#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ +#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor + sampling time. */ +#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference + sampling time. */ +#define ADC_SMPR1_SMP_VBAT(n) ((n) << 24) /**< @brief VBAT sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#if STM32_ADC_USE_ADC2 && !defined(__DOXYGEN__) +extern ADCDriver ADCD2; +#endif + +#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__) +extern ADCDriver ADCD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); + void adcSTM32EnableTSVREFE(void); + void adcSTM32DisableTSVREFE(void); + void adcSTM32EnableVBATE(void); + void adcSTM32DisableVBATE(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F4xx/hal_lld.c b/Project/os/hal/platforms/STM32F4xx/hal_lld.c new file mode 100644 index 0000000..f2de0b7 --- /dev/null +++ b/Project/os/hal/platforms/STM32F4xx/hal_lld.c @@ -0,0 +1,222 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F4xx/hal_lld.c + * @brief STM32F4xx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the backup domain. + */ +static void hal_lld_backup_domain_init(void) { + + /* Backup domain access enabled and left open.*/ + PWR->CR |= PWR_CR_DBP; + + /* Reset BKP domain if different clock source selected.*/ + if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) { + /* Backup domain reset.*/ + RCC->BDCR = RCC_BDCR_BDRST; + RCC->BDCR = 0; + } + + /* If enabled then the LSE is started.*/ +#if STM32_LSE_ENABLED + RCC->BDCR |= RCC_BDCR_LSEON; + while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ +#endif + +#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK + /* If the backup domain hasn't been initialized yet then proceed with + initialization.*/ + if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { + /* Selects clock source.*/ + RCC->BDCR |= STM32_RTCSEL; + + /* RTC clock enabled.*/ + RCC->BDCR |= RCC_BDCR_RTCEN; + } +#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */ +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* Reset of all peripherals. AHB3 is not reseted because it could have + been initialized in the board initialization file (board.c).*/ + rccResetAHB1(!0); + rccResetAHB2(!0); + rccResetAHB3(!0); + rccResetAPB1(!RCC_APB1RSTR_PWRRST); + rccResetAPB2(!0); + + /* SysTick initialization using the system clock.*/ + SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + + /* DWT cycle counter enable.*/ + SCS_DEMCR |= SCS_DEMCR_TRCENA; + DWT_CTRL |= DWT_CTRL_CYCCNTENA; + + /* PWR clock enabled.*/ + rccEnablePWRInterface(FALSE); + + /* Initializes the backup domain.*/ + hal_lld_backup_domain_init(); + +#if defined(STM32_DMA_REQUIRED) + dmaInit(); +#endif + + /* Programmable voltage detector enable.*/ +#if STM32_PVD_ENABLE + PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); +#endif /* STM32_PVD_ENABLE */ +} + +/** + * @brief STM32F2xx clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +void stm32_clock_init(void) { + +#if !STM32_NO_INIT + /* PWR clock enable.*/ + RCC->APB1ENR = RCC_APB1ENR_PWREN; + + /* PWR initialization.*/ + PWR->CR = STM32_VOS; + while ((PWR->CSR & PWR_CSR_VOSRDY) == 0) + ; /* Waits until power regulator is stable. */ + + /* Initial clocks setup and wait for HSI stabilization, the MSI clock is + always enabled because it is the fallback clock when PLL the fails.*/ + RCC->CR |= RCC_CR_HSION; + while ((RCC->CR & RCC_CR_HSIRDY) == 0) + ; /* Waits until HSI is stable. */ + +#if STM32_HSE_ENABLED + /* HSE activation.*/ + RCC->CR |= RCC_CR_HSEON; + while ((RCC->CR & RCC_CR_HSERDY) == 0) + ; /* Waits until HSE is stable. */ +#endif + +#if STM32_LSI_ENABLED + /* LSI activation.*/ + RCC->CSR |= RCC_CSR_LSION; + while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) + ; /* Waits until LSI is stable. */ +#endif + +#if STM32_LSE_ENABLED + /* LSE activation, have to unlock the register.*/ + if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) { + PWR->CR |= PWR_CR_DBP; + RCC->BDCR |= RCC_BDCR_LSEON; + PWR->CR &= ~PWR_CR_DBP; + } + while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ +#endif + +#if STM32_ACTIVATE_PLL + /* PLL activation.*/ + RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN | STM32_PLLM; + RCC->CR |= RCC_CR_PLLON; + while (!(RCC->CR & RCC_CR_PLLRDY)) + ; /* Waits until PLL is stable. */ +#endif + +#if STM32_ACTIVATE_PLLI2S + /* PLLI2S activation.*/ + RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN; + RCC->CR |= RCC_CR_PLLI2SON; + while (!(RCC->CR & RCC_CR_PLLI2SRDY)) + ; /* Waits until PLLI2S is stable. */ +#endif + + /* Other clock-related settings (dividers, MCO etc).*/ + RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL | + STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; + + /* Flash setup.*/ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | + STM32_FLASHBITS; + + /* Switching to the configured clock source if it is different from MSI.*/ +#if (STM32_SW != STM32_SW_HSI) + RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) + ; +#endif +#endif /* STM32_NO_INIT */ + + /* SYSCFG clock enabled here because it is a multi-functional unit shared + among multiple drivers.*/ + rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); +} + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F4xx/hal_lld.h b/Project/os/hal/platforms/STM32F4xx/hal_lld.h new file mode 100644 index 0000000..c97ce41 --- /dev/null +++ b/Project/os/hal/platforms/STM32F4xx/hal_lld.h @@ -0,0 +1,1427 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F4xx/hal_lld.h + * @brief STM32F4xx HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - STM32_LSECLK. + * - STM32_HSECLK. + * - STM32_VDD (as hundredths of Volt). + * . + * One of the following macros must also be defined: + * - STM32F4XX for High-performance STM32 F-4 devices. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "stm32.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS TRUE + +/** + * @name Platform identification + * @{ + */ +#define PLATFORM_NAME "STM32F4 High Performance & DSP" +/** @} */ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Maximum HSE clock frequency. + */ +#define STM32_HSECLK_MAX 26000000 + +/** + * @brief Minimum HSE clock frequency. + */ +#define STM32_HSECLK_MIN 1000000 + +/** + * @brief Maximum LSE clock frequency. + */ +#define STM32_LSECLK_MAX 1000000 + +/** + * @brief Minimum LSE clock frequency. + */ +#define STM32_LSECLK_MIN 32768 + +/** + * @brief Maximum PLLs input clock frequency. + */ +#define STM32_PLLIN_MAX 2000000 + +/** + * @brief Minimum PLLs input clock frequency. + */ +#define STM32_PLLIN_MIN 950000 + +/** + * @brief Maximum PLLs VCO clock frequency. + */ +#define STM32_PLLVCO_MAX 432000000 + +/** + * @brief Maximum PLLs VCO clock frequency. + */ +#define STM32_PLLVCO_MIN 192000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define STM32_PLLOUT_MAX 168000000 + +/** + * @brief Minimum PLL output clock frequency. + */ +#define STM32_PLLOUT_MIN 24000000 + +/** + * @brief Maximum APB1 clock frequency. + */ +#define STM32_PCLK1_MAX 42000000 + +/** + * @brief Maximum APB2 clock frequency. + */ +#define STM32_PCLK2_MAX 84000000 + +/** + * @brief Maximum SPI/I2S clock frequency. + */ +#define STM32_SPII2S_MAX 37500000 +/** @} */ + +/** + * @name Internal clock sources + * @{ + */ +#define STM32_HSICLK 16000000 /**< High speed internal clock. */ +#define STM32_LSICLK 32000 /**< Low speed internal clock. */ +/** @} */ + +/** + * @name PWR_CR register bits definitions + * @{ + */ +#define STM32_VOS_MASK (1 << 14) /**< Core voltage mask. */ +#define STM32_VOS_LOW (0 << 14) /**< Core voltage set to low. */ +#define STM32_VOS_HIGH (1 << 14) /**< Core voltage set to high. */ + +#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */ +#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */ +#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */ +#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */ +#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */ +#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */ +#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */ +#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */ +/** @} */ + +/** + * @name RCC_PLLCFGR register bits definitions + * @{ + */ +#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */ +#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */ +#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */ +#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */ +#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */ + +#define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */ +#define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */ +/** @} */ + +/** + * @name RCC_CFGR register bits definitions + * @{ + */ +#define STM32_SW_MASK (3 << 0) /**< SW mask. */ +#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ +#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ +#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ + +#define STM32_HPRE_MASK (15 << 4) /**< HPRE mask. */ +#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ +#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ +#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ +#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ +#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ +#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ +#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ +#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ +#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ + +#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */ +#define STM32_PPRE1_DIV1 (0 << 10) /**< HCLK divided by 1. */ +#define STM32_PPRE1_DIV2 (4 << 10) /**< HCLK divided by 2. */ +#define STM32_PPRE1_DIV4 (5 << 10) /**< HCLK divided by 4. */ +#define STM32_PPRE1_DIV8 (6 << 10) /**< HCLK divided by 8. */ +#define STM32_PPRE1_DIV16 (7 << 10) /**< HCLK divided by 16. */ + +#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */ +#define STM32_PPRE2_DIV1 (0 << 13) /**< HCLK divided by 1. */ +#define STM32_PPRE2_DIV2 (4 << 13) /**< HCLK divided by 2. */ +#define STM32_PPRE2_DIV4 (5 << 13) /**< HCLK divided by 4. */ +#define STM32_PPRE2_DIV8 (6 << 13) /**< HCLK divided by 8. */ +#define STM32_PPRE2_DIV16 (7 << 13) /**< HCLK divided by 16. */ + +#define STM32_RTCPRE_MASK (31 << 16) /**< RTCPRE mask. */ + +#define STM32_MCO1SEL_MASK (3 << 21) /**< MCO1 mask. */ +#define STM32_MCO1SEL_HSI (0 << 21) /**< HSI clock on MCO1 pin. */ +#define STM32_MCO1SEL_LSE (1 << 21) /**< LSE clock on MCO1 pin. */ +#define STM32_MCO1SEL_HSE (2 << 21) /**< HSE clock on MCO1 pin. */ +#define STM32_MCO1SEL_PLL (3 << 21) /**< PLL clock on MCO1 pin. */ + +#define STM32_I2SSRC_MASK (1 << 23) /**< I2CSRC mask. */ +#define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */ +#define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */ + +#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */ +#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */ +#define STM32_MCO1PRE_DIV2 (4 << 24) /**< MCO1 divided by 2. */ +#define STM32_MCO1PRE_DIV3 (5 << 24) /**< MCO1 divided by 3. */ +#define STM32_MCO1PRE_DIV4 (6 << 24) /**< MCO1 divided by 4. */ +#define STM32_MCO1PRE_DIV5 (7 << 24) /**< MCO1 divided by 5. */ + +#define STM32_MCO2PRE_MASK (7 << 27) /**< MCO2PRE mask. */ +#define STM32_MCO2PRE_DIV1 (0 << 27) /**< MCO2 divided by 1. */ +#define STM32_MCO2PRE_DIV2 (4 << 27) /**< MCO2 divided by 2. */ +#define STM32_MCO2PRE_DIV3 (5 << 27) /**< MCO2 divided by 3. */ +#define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */ +#define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */ + +#define STM32_MCO2SEL_MASK (3U << 30) /**< MCO2 mask. */ +#define STM32_MCO2SEL_SYSCLK (0U << 30) /**< SYSCLK clock on MCO2 pin. */ +#define STM32_MCO2SEL_PLLI2S (1U << 30) /**< PLLI2S clock on MCO2 pin. */ +#define STM32_MCO2SEL_HSE (2U << 30) /**< HSE clock on MCO2 pin. */ +#define STM32_MCO2SEL_PLL (3U << 30) /**< PLL clock on MCO2 pin. */ + +#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock. */ +#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock. */ +#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock. */ +#define STM32_RTC_HSE (3 << 8) /**< HSE divided by programmable + prescaler used as RTC clock*/ + +/** + * @name RCC_PLLI2SCFGR register bits definitions + * @{ + */ +#define STM32_PLLI2SN_MASK (511 << 6) /**< PLLI2SN mask. */ +#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */ +/** @} */ + +/** + * @name RCC_BDCR register bits definitions + * @{ + */ +#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */ +#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */ +#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */ +#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */ +#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */ +/** @} */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name STM32F4xx capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_ADC1_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC2 TRUE +#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) | \ + STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_ADC2_DMA_CHN 0x00001100 + +#define STM32_HAS_ADC3 TRUE +#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \ + STM32_DMA_STREAM_ID_MSK(2, 1)) +#define STM32_ADC3_DMA_CHN 0x00000022 + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 TRUE +#define STM32_CAN_MAX_FILTERS 28 + +/* DAC attributes.*/ +#define STM32_HAS_DAC TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA TRUE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 TRUE + +/* ETH attributes.*/ +#define STM32_HAS_ETH TRUE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 23 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOH TRUE +#define STM32_HAS_GPIOI TRUE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) | \ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C1_RX_DMA_CHN 0x00100001 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) | \ + (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x11000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) | \ + STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_I2C2_RX_DMA_CHN 0x00007700 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C2_TX_DMA_CHN 0x70000000 + +#define STM32_HAS_I2C3 TRUE +#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_I2C3_RX_DMA_CHN 0x00000300 +#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C3_TX_DMA_CHN 0x00030000 + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS TRUE +#define STM32_RTC_IS_CALENDAR TRUE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO TRUE +#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \ + STM32_DMA_STREAM_ID_MSK(2, 6)) +#define STM32_SDC_SDIO_DMA_CHN 0x04004000 + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \ + STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_SPI1_RX_DMA_CHN 0x00000303 +#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_SPI1_TX_DMA_CHN 0x00303000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) | \ + STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) | \ + STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 TRUE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 TRUE +#define STM32_HAS_TIM9 TRUE +#define STM32_HAS_TIM10 TRUE +#define STM32_HAS_TIM11 TRUE +#define STM32_HAS_TIM12 TRUE +#define STM32_HAS_TIM13 TRUE +#define STM32_HAS_TIM14 TRUE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) | \ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00400400 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 7)) +#define STM32_USART1_TX_DMA_CHN 0x40000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART2_RX_DMA_CHN 0x00400000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_TX_DMA_CHN 0x04000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) +#define STM32_USART3_RX_DMA_CHN 0x00000040 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) | \ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART3_TX_DMA_CHN 0x00074000 + +#define STM32_HAS_UART4 TRUE +#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_UART4_RX_DMA_CHN 0x00000400 +#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_UART4_TX_DMA_CHN 0x00040000 + +#define STM32_HAS_UART5 TRUE +#define STM32_UART5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0)) +#define STM32_UART5_RX_DMA_CHN 0x00000004 +#define STM32_UART5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_UART5_TX_DMA_CHN 0x40000000 + +#define STM32_HAS_USART6 TRUE +#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) | \ + STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_USART6_RX_DMA_CHN 0x00000550 +#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) | \ + STM32_DMA_STREAM_ID_MSK(2, 7)) +#define STM32_USART6_TX_DMA_CHN 0x55000000 + +/* USB attributes.*/ +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 TRUE +#define STM32_HAS_OTG2 TRUE +/** @} */ + +/*===========================================================================*/ +/* Platform specific friendly IRQ names. */ +/*===========================================================================*/ + +/** + * @name IRQ VECTOR names + * @{ + */ +#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ +#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line + detect. */ +#define TAMP_STAMP_IRQHandler Vector48 /**< Tamper and TimeStamp + through EXTI Line. */ +#define RTC_WKUP_IRQHandler Vector4C /**< RTC wakeup EXTI Line. */ +#define FLASH_IRQHandler Vector50 /**< Flash. */ +#define RCC_IRQHandler Vector54 /**< RCC. */ +#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ +#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ +#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ +#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ +#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ +#define DMA1_Stream0_IRQHandler Vector6C /**< DMA1 Stream 0. */ +#define DMA1_Stream1_IRQHandler Vector70 /**< DMA1 Stream 1. */ +#define DMA1_Stream2_IRQHandler Vector74 /**< DMA1 Stream 2. */ +#define DMA1_Stream3_IRQHandler Vector78 /**< DMA1 Stream 3. */ +#define DMA1_Stream4_IRQHandler Vector7C /**< DMA1 Stream 4. */ +#define DMA1_Stream5_IRQHandler Vector80 /**< DMA1 Stream 5. */ +#define DMA1_Stream6_IRQHandler Vector84 /**< DMA1 Stream 6. */ +#define ADC1_2_3_IRQHandler Vector88 /**< ADC1, ADC2 and ADC3. */ +#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */ +#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */ +#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ +#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ +#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ +#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ +#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ +#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and + Commutation. */ +#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ +#define TIM2_IRQHandler VectorB0 /**< TIM2. */ +#define TIM3_IRQHandler VectorB4 /**< TIM3. */ +#define TIM4_IRQHandler VectorB8 /**< TIM4. */ +#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ +#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ +#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ +#define I2C2_ER_IRQHandler VectorC8 /**< I2C1 Error. */ +#define SPI1_IRQHandler VectorCC /**< SPI1. */ +#define SPI2_IRQHandler VectorD0 /**< SPI2. */ +#define USART1_IRQHandler VectorD4 /**< USART1. */ +#define USART2_IRQHandler VectorD8 /**< USART2. */ +#define USART3_IRQHandler VectorDC /**< USART3. */ +#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ +#define RTC_Alarm_IRQHandler VectorE4 /**< RTC alarms (A and B) + through EXTI line. */ +#define OTG_FS_WKUP_IRQHandler VectorE8 /**< USB OTG FS Wakeup through + EXTI line. */ +#define TIM8_BRK_IRQHandler VectorEC /**< TIM8 Break. */ +#define TIM8_UP_IRQHandler VectorF0 /**< TIM8 Update. */ +#define TIM8_TRG_COM_IRQHandler VectorF4 /**< TIM8 Trigger and + Commutation. */ +#define TIM8_CC_IRQHandler VectorF8 /**< TIM8 Capture Compare. */ +#define DMA1_Stream7_IRQHandler VectorFC /**< DMA1 Stream 7. */ +#define FSMC_IRQHandler Vector100 /**< FSMC. */ +#define SDIO_IRQHandler Vector104 /**< SDIO. */ +#define TIM5_IRQHandler Vector108 /**< TIM5. */ +#define SPI3_IRQHandler Vector10C /**< SPI3. */ +#define UART4_IRQHandler Vector110 /**< UART4. */ +#define UART5_IRQHandler Vector114 /**< UART5. */ +#define TIM6_IRQHandler Vector118 /**< TIM6. */ +#define TIM7_IRQHandler Vector11C /**< TIM7. */ +#define DMA2_Stream0_IRQHandler Vector120 /**< DMA2 Stream0. */ +#define DMA2_Stream1_IRQHandler Vector124 /**< DMA2 Stream1. */ +#define DMA2_Stream2_IRQHandler Vector128 /**< DMA2 Stream2. */ +#define DMA2_Stream3_IRQHandler Vector12C /**< DMA2 Stream3. */ +#define DMA2_Stream4_IRQHandler Vector130 /**< DMA2 Stream4. */ +#define ETH_IRQHandler Vector134 /**< Ethernet. */ +#define ETH_WKUP_IRQHandler Vector138 /**< Ethernet Wakeup through + EXTI line. */ +#define CAN2_TX_IRQHandler Vector13C /**< CAN2 TX. */ +#define CAN2_RX0_IRQHandler Vector140 /**< CAN2 RX0. */ +#define CAN2_RX1_IRQHandler Vector144 /**< CAN2 RX1. */ +#define CAN2_SCE_IRQHandler Vector148 /**< CAN2 SCE. */ +#define OTG_FS_IRQHandler Vector14C /**< USB OTG FS. */ +#define DMA2_Stream5_IRQHandler Vector150 /**< DMA2 Stream5. */ +#define DMA2_Stream6_IRQHandler Vector154 /**< DMA2 Stream6. */ +#define DMA2_Stream7_IRQHandler Vector158 /**< DMA2 Stream7. */ +#define USART6_IRQHandler Vector15C /**< USART6. */ +#define I2C3_EV_IRQHandler Vector160 /**< I2C3 Event. */ +#define I2C3_ER_IRQHandler Vector164 /**< I2C3 Error. */ +#define OTG_HS_EP1_OUT_IRQHandler Vector168 /**< USB OTG HS End Point 1 Out.*/ +#define OTG_HS_EP1_IN_IRQHandler Vector16C /**< USB OTG HS End Point 1 In. */ +#define OTG_HS_WKUP_IRQHandler Vector170 /**< USB OTG HS Wakeup through + EXTI line. */ +#define OTG_HS_IRQHandler Vector174 /**< USB OTG HS. */ +#define DCMI_IRQHandler Vector178 /**< DCMI. */ +#define CRYP_IRQHandler Vector17C /**< CRYP. */ +#define HASH_RNG_IRQHandler Vector180 /**< Hash and Rng. */ +#define FPU_IRQHandler Vector184 /**< Floating Point Unit. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Disables the PWR/RCC initialization in the HAL. + */ +#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) +#define STM32_NO_INIT FALSE +#endif + +/** + * @brief Core voltage selection. + * @note This setting affects all the performance and clock related + * settings, the maximum performance is only obtainable selecting + * the maximum voltage. + */ +#if !defined(STM32_VOS) || defined(__DOXYGEN__) +#define STM32_VOS STM32_VOS_HIGH +#endif + +/** + * @brief Enables or disables the programmable voltage detector. + */ +#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__) +#define STM32_PVD_ENABLE FALSE +#endif + +/** + * @brief Sets voltage level for programmable voltage detector. + */ +#if !defined(STM32_PLS) || defined(__DOXYGEN__) +#define STM32_PLS STM32_PLS_LEV0 +#endif + +/** + * @brief Enables or disables the HSI clock source. + */ +#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSI_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the HSE clock source. + */ +#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSE_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSE clock source. + */ +#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSE_ENABLED FALSE +#endif + +/** + * @brief USB/SDIO clock setting. + */ +#if !defined(STM32_CLOCK48_REQUIRED) || defined(__DOXYGEN__) +#define STM32_CLOCK48_REQUIRED TRUE +#endif + +/** + * @brief Main clock source selection. + * @note If the selected clock source is not the PLL then the PLL is not + * initialized and started. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_SW) || defined(__DOXYGEN__) +#define STM32_SW STM32_SW_PLL +#endif + +/** + * @brief Clock source for the PLLs. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) +#define STM32_PLLSRC STM32_PLLSRC_HSE +#endif + +/** + * @brief PLLM divider value. + * @note The allowed values are 2..63. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLM_VALUE 8 +#endif + +/** + * @brief PLLN multiplier value. + * @note The allowed values are 192..432. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLN_VALUE 336 +#endif + +/** + * @brief PLLP divider value. + * @note The allowed values are 2, 4, 6, 8. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLP_VALUE 2 +#endif + +/** + * @brief PLLQ multiplier value. + * @note The allowed values are 2..15. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLQ_VALUE 7 +#endif + +/** + * @brief AHB prescaler value. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. + */ +#if !defined(STM32_HPRE) || defined(__DOXYGEN__) +#define STM32_HPRE STM32_HPRE_DIV1 +#endif + +/** + * @brief APB1 prescaler value. + */ +#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#endif + +/** + * @brief APB2 prescaler value. + */ +#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#endif + +/** + * @brief RTC clock source. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCSEL STM32_RTCSEL_LSE +#endif + +/** + * @brief RTC HSE prescaler value. + */ +#if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__) +#define STM32_RTCPRE_VALUE 8 +#endif + +/** + * @brief MC01 clock source value. + * @note The default value outputs HSI clock on MC01 pin. + */ +#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__) +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#endif + +/** + * @brief MC01 prescaler value. + * @note The default value outputs HSI clock on MC01 pin. + */ +#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__) +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#endif + +/** + * @brief MC02 clock source value. + * @note The default value outputs SYSCLK / 5 on MC02 pin. + */ +#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__) +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#endif + +/** + * @brief MC02 prescaler value. + * @note The default value outputs SYSCLK / 5 on MC02 pin. + */ +#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__) +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#endif + +/** + * @brief I2S clock source. + */ +#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__) +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#endif + +/** + * @brief PLLI2SN multiplier value. + * @note The allowed values are 192..432. + */ +#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLI2SN_VALUE 192 +#endif + +/** + * @brief PLLI2SR multiplier value. + * @note The allowed values are 2..7. + */ +#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLI2SR_VALUE 5 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** + * @brief Maximum SYSCLK. + * @note It is a function of the core voltage setting. + */ +#if (STM32_VOS == STM32_VOS_HIGH) || defined(__DOXYGEN__) +#define STM32_SYSCLK_MAX 168000000 +#else +#define STM32_SYSCLK_MAX 144000000 +#endif + +/** + * @brief Maximum frequency thresholds and wait states for flash access. + * @note The values are valid for 2.7V to 3.6V supply range. + */ +#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__) +#define STM32_0WS_THRESHOLD 30000000 +#define STM32_1WS_THRESHOLD 60000000 +#define STM32_2WS_THRESHOLD 90000000 +#define STM32_3WS_THRESHOLD 120000000 +#define STM32_4WS_THRESHOLD 150000000 +#define STM32_5WS_THRESHOLD 168000000 +#define STM32_6WS_THRESHOLD 0 +#define STM32_7WS_THRESHOLD 0 +#elif (STM32_VDD >= 240) && (STM32_VDD < 270) +#define STM32_0WS_THRESHOLD 24000000 +#define STM32_1WS_THRESHOLD 48000000 +#define STM32_2WS_THRESHOLD 72000000 +#define STM32_3WS_THRESHOLD 96000000 +#define STM32_4WS_THRESHOLD 120000000 +#define STM32_5WS_THRESHOLD 144000000 +#define STM32_6WS_THRESHOLD 168000000 +#define STM32_7WS_THRESHOLD 0 +#elif (STM32_VDD >= 210) && (STM32_VDD < 240) +#define STM32_0WS_THRESHOLD 18000000 +#define STM32_1WS_THRESHOLD 36000000 +#define STM32_2WS_THRESHOLD 54000000 +#define STM32_3WS_THRESHOLD 72000000 +#define STM32_4WS_THRESHOLD 90000000 +#define STM32_5WS_THRESHOLD 108000000 +#define STM32_6WS_THRESHOLD 120000000 +#define STM32_7WS_THRESHOLD 138000000 +#elif (STM32_VDD >= 180) && (STM32_VDD < 210) +#define STM32_0WS_THRESHOLD 16000000 +#define STM32_1WS_THRESHOLD 32000000 +#define STM32_2WS_THRESHOLD 48000000 +#define STM32_3WS_THRESHOLD 64000000 +#define STM32_4WS_THRESHOLD 80000000 +#define STM32_5WS_THRESHOLD 96000000 +#define STM32_6WS_THRESHOLD 112000000 +#define STM32_7WS_THRESHOLD 128000000 +#else +#error "invalid VDD voltage specified" +#endif + +/* + * HSI related checks. + */ +#if STM32_HSI_ENABLED +#else /* !STM32_HSI_ENABLED */ + +#if STM32_SW == STM32_SW_HSI +#error "HSI not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || \ + ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "HSI not enabled, required by STM32_MCO1SEL" +#endif + +#if (STM32_MCO2SEL == STM32_MCO2SEL_HSI) || \ + ((STM32_MCO2SEL == STM32_MCO2SEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "HSI not enabled, required by STM32_MCO2SEL" +#endif + +#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_I2SSRC" +#endif + +#endif /* !STM32_HSI_ENABLED */ + +/* + * HSE related checks. + */ +#if STM32_HSE_ENABLED + +#if STM32_HSECLK == 0 +#error "HSE frequency not defined" +#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) +#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" +#endif + +#else /* !STM32_HSE_ENABLED */ + +#if STM32_SW == STM32_SW_HSE +#error "HSE not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE) +#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCO1SEL == STM32_MCO1SEL_HSE) || \ + ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) +#error "HSE not enabled, required by STM32_MCO1SEL" +#endif + +#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || \ + ((STM32_MCO2SEL == STM32_MCO2SEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) +#error "HSE not enabled, required by STM32_MCO2SEL" +#endif + +#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE) +#error "HSE not enabled, required by STM32_I2SSRC" +#endif + +#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#error "HSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_HSE_ENABLED */ + +/* + * LSI related checks. + */ +#if STM32_LSI_ENABLED +#else /* !STM32_LSI_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSI +#error "LSI not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSI_ENABLED */ + +/* + * LSE related checks. + */ +#if STM32_LSE_ENABLED + +#if (STM32_LSECLK == 0) +#error "LSE frequency not defined" +#endif + +#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) +#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" +#endif + +#else /* !STM32_LSE_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSE +#error "LSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSE_ENABLED */ + +/** + * @brief STM32_PLLM field. + */ +#if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) || \ + defined(__DOXYGEN__) +#define STM32_PLLM (STM32_PLLM_VALUE << 0) +#else +#error "invalid STM32_PLLM_VALUE value specified" +#endif + +/** + * @brief PLLs input clock frequency. + */ +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE) +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLCLKIN (STM32_HSICLK / STM32_PLLM_VALUE) +#else +#error "invalid STM32_PLLSRC value specified" +#endif + +/* + * PLLs input frequency range check. + */ +#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX) +#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" +#endif + +/* + * PLL enable check. + */ +#if STM32_CLOCK48_REQUIRED || \ + (STM32_SW == STM32_SW_PLL) || \ + (STM32_MCO1SEL == STM32_MCO1SEL_PLL) || \ + (STM32_MCO2SEL == STM32_MCO2SEL_PLL) || \ + defined(__DOXYGEN__) +/** + * @brief PLL activation flag. + */ +#define STM32_ACTIVATE_PLL TRUE +#else +#define STM32_ACTIVATE_PLL FALSE +#endif + +/** + * @brief STM32_PLLN field. + */ +#if ((STM32_PLLN_VALUE >= 64) && (STM32_PLLN_VALUE <= 432)) || \ + defined(__DOXYGEN__) +#define STM32_PLLN (STM32_PLLN_VALUE << 6) +#else +#error "invalid STM32_PLLN_VALUE value specified" +#endif + +/** + * @brief STM32_PLLP field. + */ +#if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__) +#define STM32_PLLP (0 << 16) +#elif STM32_PLLP_VALUE == 4 +#define STM32_PLLP (1 << 16) +#elif STM32_PLLP_VALUE == 6 +#define STM32_PLLP (2 << 16) +#elif STM32_PLLP_VALUE == 8 +#define STM32_PLLP (3 << 16) +#else +#error "invalid STM32_PLLP_VALUE value specified" +#endif + +/** + * @brief STM32_PLLQ field. + */ +#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 15)) || \ + defined(__DOXYGEN__) +#define STM32_PLLQ (STM32_PLLQ_VALUE << 24) +#else +#error "invalid STM32_PLLQ_VALUE value specified" +#endif + +/** + * @brief PLL VCO frequency. + */ +#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE) + +/* + * PLL VCO frequency range check. + */ +#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX) +#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE) + +/* + * PLL output frequency range check. + */ +#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX) +#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)" +#endif + +/** + * @brief System clock source. + */ +#if STM32_NO_INIT || defined(__DOXYGEN__) +#define STM32_SYSCLK STM32_HSICLK +#elif (STM32_SW == STM32_SW_HSI) +#define STM32_SYSCLK STM32_HSICLK +#elif (STM32_SW == STM32_SW_HSE) +#define STM32_SYSCLK STM32_HSECLK +#elif (STM32_SW == STM32_SW_PLL) +#define STM32_SYSCLK STM32_PLLCLKOUT +#else +#error "invalid STM32_SW value specified" +#endif + +/* Check on the system clock.*/ +#if STM32_SYSCLK > STM32_SYSCLK_MAX +#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief AHB frequency. + */ +#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK (STM32_SYSCLK / 1) +#elif STM32_HPRE == STM32_HPRE_DIV2 +#define STM32_HCLK (STM32_SYSCLK / 2) +#elif STM32_HPRE == STM32_HPRE_DIV4 +#define STM32_HCLK (STM32_SYSCLK / 4) +#elif STM32_HPRE == STM32_HPRE_DIV8 +#define STM32_HCLK (STM32_SYSCLK / 8) +#elif STM32_HPRE == STM32_HPRE_DIV16 +#define STM32_HCLK (STM32_SYSCLK / 16) +#elif STM32_HPRE == STM32_HPRE_DIV64 +#define STM32_HCLK (STM32_SYSCLK / 64) +#elif STM32_HPRE == STM32_HPRE_DIV128 +#define STM32_HCLK (STM32_SYSCLK / 128) +#elif STM32_HPRE == STM32_HPRE_DIV256 +#define STM32_HCLK (STM32_SYSCLK / 256) +#elif STM32_HPRE == STM32_HPRE_DIV512 +#define STM32_HCLK (STM32_SYSCLK / 512) +#else +#error "invalid STM32_HPRE value specified" +#endif + +/* + * AHB frequency check. + */ +#if STM32_HCLK > STM32_SYSCLK_MAX +#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief APB1 frequency. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK1 (STM32_HCLK / 1) +#elif STM32_PPRE1 == STM32_PPRE1_DIV2 +#define STM32_PCLK1 (STM32_HCLK / 2) +#elif STM32_PPRE1 == STM32_PPRE1_DIV4 +#define STM32_PCLK1 (STM32_HCLK / 4) +#elif STM32_PPRE1 == STM32_PPRE1_DIV8 +#define STM32_PCLK1 (STM32_HCLK / 8) +#elif STM32_PPRE1 == STM32_PPRE1_DIV16 +#define STM32_PCLK1 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE1 value specified" +#endif + +/* + * APB1 frequency check. + */ +#if STM32_PCLK1 > STM32_PCLK1_MAX +#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" +#endif + +/** + * @brief APB2 frequency. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK2 (STM32_HCLK / 1) +#elif STM32_PPRE2 == STM32_PPRE2_DIV2 +#define STM32_PCLK2 (STM32_HCLK / 2) +#elif STM32_PPRE2 == STM32_PPRE2_DIV4 +#define STM32_PCLK2 (STM32_HCLK / 4) +#elif STM32_PPRE2 == STM32_PPRE2_DIV8 +#define STM32_PCLK2 (STM32_HCLK / 8) +#elif STM32_PPRE2 == STM32_PPRE2_DIV16 +#define STM32_PCLK2 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE2 value specified" +#endif + +/* + * APB2 frequency check. + */ +#if STM32_PCLK2 > STM32_PCLK2_MAX +#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" +#endif + +/* + * PLLI2S enable check. + */ +#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || defined(__DOXYGEN__) +/** + * @brief PLL activation flag. + */ +#define STM32_ACTIVATE_PLLI2S TRUE +#else +#define STM32_ACTIVATE_PLLI2S FALSE +#endif + +/** + * @brief STM32_PLLI2SN field. + */ +#if ((STM32_PLLI2SN_VALUE >= 192) && (STM32_PLLI2SN_VALUE <= 432)) || \ + defined(__DOXYGEN__) +#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6) +#else +#error "invalid STM32_PLLI2SN_VALUE value specified" +#endif + +/** + * @brief STM32_PLLI2SR field. + */ +#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) || \ + defined(__DOXYGEN__) +#define STM32_PLLI2SR (STM32_PLLI2SR_VALUE << 28) +#else +#error "invalid STM32_PLLI2SR_VALUE value specified" +#endif + +/** + * @brief PLL VCO frequency. + */ +#define STM32_PLLI2SVCO (STM32_PLLCLKIN * STM32_PLLI2SN_VALUE) + +/* + * PLLI2S VCO frequency range check. + */ +#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) || \ + (STM32_PLLI2SVCO > STM32_PLLVCO_MAX) +#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" +#endif + +/** + * @brief PLLI2S output clock frequency. + */ +#define STM32_PLLI2SCLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR) + +/* + * PLLI2S output frequency range check. + */ +#if STM32_PLLI2SCLKOUT > STM32_SPII2S_MAX +#error "STM32_PLLI2SCLKOUT outside acceptable range (STM32_SPII2S_MAX)" +#endif + +/** + * @brief MCO1 divider clock. + */ +#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__) +#define STM32_MCO1DIVCLK STM32_HSICLK +#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE +#define STM32_MCO1DIVCLK STM32_LSECLK +#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE +#define STM32_MCO1DIVCLK STM32_HSECLK +#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL +#define STM32_MCO1DIVCLK STM32_PLLCLKOUT +#else +#error "invalid STM32_MCO1SEL value specified" +#endif + +/** + * @brief MCO1 output pin clock. + */ +#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__) +#define STM32_MCO1CLK STM32_MCO1DIVCLK +#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2 +#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2) +#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3 +#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3) +#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4 +#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4) +#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5 +#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5) +#else +#error "invalid STM32_MCO1PRE value specified" +#endif + +/** + * @brief MCO2 divider clock. + */ +#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__) +#define STM32_MCO2DIVCLK STM32_HSECLK +#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL +#define STM32_MCO2DIVCLK STM32_PLLCLKOUT +#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK +#define STM32_MCO2DIVCLK STM32_SYSCLK +#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S +#define STM32_MCO2DIVCLK STM32_PLLI2S +#else +#error "invalid STM32_MCO2SEL value specified" +#endif + +/** + * @brief MCO2 output pin clock. + */ +#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__) +#define STM32_MCO2CLK STM32_MCO2DIVCLK +#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2 +#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2) +#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3 +#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3) +#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4 +#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4) +#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5 +#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5) +#else +#error "invalid STM32_MCO2PRE value specified" +#endif + +/** + * @brief RTC HSE divider setting. + */ +#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \ + defined(__DOXYGEN__) +#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16) +#else +#error "invalid STM32_RTCPRE value specified" +#endif + +/** + * @brief HSE divider toward RTC clock. + */ +#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \ + defined(__DOXYGEN__) +#define STM32_HSEDIVCLK (STM32_HSECLK / STM32_RTCPRE_VALUE) +#else +#error "invalid STM32_RTCPRE value specified" +#endif + +/** + * @brief RTC clock. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__) +#define STM32_RTCCLK 0 +#elif STM32_RTCSEL == STM32_RTCSEL_LSE +#define STM32_RTCCLK STM32_LSECLK +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM32_RTCCLK STM32_LSICLK +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM32_RTCCLK STM32_HSEDIVCLK +#else +#error "invalid STM32_RTCSEL value specified" +#endif + +/** + * @brief RTC HSE divider setting. + */ +#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \ + defined(__DOXYGEN__) +#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16) +#else +#error "invalid STM32_RTCPRE value specified" +#endif + +/** + * @brief 48MHz frequency. + */ +#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__) +#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE) +#else +#define STM32_PLL48CLK 0 +#endif + +/** + * @brief Timers 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14 clock. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK1 (STM32_PCLK1 * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK1 * 2) +#endif + +/** + * @brief Timers 1, 8 clock. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK2 (STM32_PCLK2 * 1) +#else +#define STM32_TIMCLK2 (STM32_PCLK2 * 2) +#endif + +/** + * @brief Flash settings. + */ +#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__) +#define STM32_FLASHBITS 0x00000000 +#elif STM32_HCLK <= STM32_1WS_THRESHOLD +#define STM32_FLASHBITS 0x00000001 +#elif STM32_HCLK <= STM32_2WS_THRESHOLD +#define STM32_FLASHBITS 0x00000002 +#elif STM32_HCLK <= STM32_3WS_THRESHOLD +#define STM32_FLASHBITS 0x00000003 +#elif STM32_HCLK <= STM32_4WS_THRESHOLD +#define STM32_FLASHBITS 0x00000004 +#elif STM32_HCLK <= STM32_5WS_THRESHOLD +#define STM32_FLASHBITS 0x00000005 +#elif STM32_HCLK <= STM32_6WS_THRESHOLD +#define STM32_FLASHBITS 0x00000006 +#else +#define STM32_FLASHBITS 0x00000007 +#endif + +/* There are differences in vector names in the various sub-families, + normalizing.*/ +#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn +#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn +#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn +#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn +#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn +#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing a system clock frequency. + */ +typedef uint32_t halclock_t; + +/** + * @brief Type of the realtime free counter value. + */ +typedef uint32_t halrtcnt_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the current value of the system free running counter. + * @note This service is implemented by returning the content of the + * DWT_CYCCNT register. + * + * @return The value of the system free running counter of + * type halrtcnt_t. + * + * @notapi + */ +#define hal_lld_get_counter_value() DWT_CYCCNT + +/** + * @brief Realtime counter frequency. + * @note The DWT_CYCCNT register is incremented directly by the system + * clock so this function returns STM32_HCLK. + * + * @return The realtime counter frequency of type halclock_t. + * + * @notapi + */ +#define hal_lld_get_counter_frequency() STM32_HCLK + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* STM32 DMA and RCC helpers.*/ +#include "stm32_dma.h" +#include "stm32_rcc.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void stm32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F4xx/platform.dox b/Project/os/hal/platforms/STM32F4xx/platform.dox new file mode 100644 index 0000000..e8b94c8 --- /dev/null +++ b/Project/os/hal/platforms/STM32F4xx/platform.dox @@ -0,0 +1,366 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup STM32F4xx_DRIVERS STM32F4xx Drivers + * @details This section describes all the supported drivers on the STM32F4xx + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup STM32F4xx_HAL STM32F4xx Initialization Support + * @details The STM32F4xx HAL support is responsible for system initialization. + * + * @section stm32f4xx_hal_1 Supported HW resources + * - PLL1. + * - PLL2. + * - RCC. + * - Flash. + * . + * @section stm32f4xx_hal_2 STM32F4xx HAL driver implementation features + * - PLL startup and stabilization. + * - Clock tree initialization. + * - Clock source selection. + * - Flash wait states initialization based on the selected clock options. + * - SYSTICK initialization based on current clock and kernel required rate. + * - DMA support initialization. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_ADC STM32F4xx ADC Support + * @details The STM32F4xx ADC driver supports the ADC peripherals using DMA + * channels for maximum performance. + * + * @section stm32f4xx_adc_1 Supported HW resources + * - ADC1. + * - ADC2. + * - ADC3. + * - DMA2. + * . + * @section stm32f4xx_adc_2 STM32F4xx ADC driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Streaming conversion using DMA for maximum performance. + * - Programmable ADC interrupt priority level. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - DMA and ADC errors detection. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_CAN STM32F4xx CAN Support + * @details The STM32F4xx CAN driver uses the CAN peripherals. + * + * @section stm32f4xx_can_1 Supported HW resources + * - bxCAN1. + * . + * @section stm32f4xx_can_2 STM32F4xx CAN driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Support for bxCAN sleep mode. + * - Programmable bxCAN interrupts priority level. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_EXT STM32F4xx EXT Support + * @details The STM32F4xx EXT driver uses the EXTI peripheral. + * + * @section stm32f4xx_ext_1 Supported HW resources + * - EXTI. + * . + * @section stm32f4xx_ext_2 STM32F4xx EXT driver implementation features + * - Each EXTI channel can be independently enabled and programmed. + * - Programmable EXTI interrupts priority level. + * - Capability to work as event sources (WFE) rather than interrupt sources. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_GPT STM32F4xx GPT Support + * @details The STM32F4xx GPT driver uses the TIMx peripherals. + * + * @section stm32f4xx_gpt_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * - TIM4. + * - TIM5. + * - TIM8. + * . + * @section stm32f4xx_gpt_2 STM32F4xx GPT driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_ICU STM32F4xx ICU Support + * @details The STM32F4xx ICU driver uses the TIMx peripherals. + * + * @section stm32f4xx_icu_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * - TIM4. + * - TIM5. + * - TIM8. + * . + * @section stm32f4xx_icu_2 STM32F4xx ICU driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_MAC STM32F4xx MAC Support + * @details The STM32F4xx MAC driver supports the ETH peripheral. + * + * @section stm32f4xx_mac_1 Supported HW resources + * - ETH. + * - PHY (external). + * . + * @section stm32f4xx_mac_2 STM32F4xx MAC driver implementation features + * - Dedicated DMA operations. + * - Support for checksum off-loading. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_PAL STM32F4xx PAL Support + * @details The STM32F4xx PAL driver uses the GPIO peripherals. + * + * @section stm32f4xx_pal_1 Supported HW resources + * - GPIOA. + * - GPIOB. + * - GPIOC. + * - GPIOD. + * - GPIOE. + * - GPIOF. + * - GPIOG. + * - GPIOH. + * - GPIOI. + * . + * @section stm32f4xx_pal_2 STM32F4xx PAL driver implementation features + * The PAL driver implementation fully supports the following hardware + * capabilities: + * - 16 bits wide ports. + * - Atomic set/reset functions. + * - Atomic set+reset function (atomic bus operations). + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section stm32f4xx_pal_3 Supported PAL setup modes + * The STM32F4xx PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_PULLUP. + * - @p PAL_MODE_INPUT_PULLDOWN. + * - @p PAL_MODE_INPUT_ANALOG. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * - @p PAL_MODE_OUTPUT_OPENDRAIN. + * - @p PAL_MODE_ALTERNATE (non standard). + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section stm32f4xx_pal_4 Suboptimal behavior + * The STM32F4xx GPIO is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Pad/port toggling operations are not atomic. + * - Pad/group mode setup is not atomic. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_PWM STM32F4xx PWM Support + * @details The STM32F4xx PWM driver uses the TIMx peripherals. + * + * @section stm32f4xx_pwm_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * - TIM4. + * - TIM5. + * - TIM8. + * . + * @section stm32f4xx_pwm_2 STM32F4xx PWM driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Four independent PWM channels per timer. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_SDC STM32F4xx SDC Support + * @details The STM32F4xx SDC driver uses the SDIO peripheral. + * + * @section stm32f4xx_sdc_1 Supported HW resources + * - SDIO. + * - DMA2. + * . + * @section stm32f4xx_sdc_2 STM32F4xx SDC driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Programmable interrupt priority. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_SERIAL STM32F4xx Serial Support + * @details The STM32F4xx Serial driver uses the USART/UART peripherals in a + * buffered, interrupt driven, implementation. + * + * @section stm32f4xx_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - USART1. + * - USART2. + * - USART3. + * - UART4. + * - UART5. + * - USART6. + * . + * @section stm32f4xx_serial_2 STM32F4xx Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART/USART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * - Programmable priority levels for each UART/USART. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_SPI STM32F4xx SPI Support + * @details The SPI driver supports the STM32F4xx SPI peripherals using DMA + * channels for maximum performance. + * + * @section stm32f4xx_spi_1 Supported HW resources + * - SPI1. + * - SPI2. + * - SPI3. + * - DMA1. + * - DMA2. + * . + * @section stm32f4xx_spi_2 STM32F4xx SPI driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each SPI can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable interrupt priority levels for each SPI. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - Programmable DMA error hook. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_UART STM32F4xx UART Support + * @details The UART driver supports the STM32F4xx USART peripherals using DMA + * channels for maximum performance. + * + * @section stm32f4xx_uart_1 Supported HW resources + * The UART driver can support any of the following hardware resources: + * - USART1. + * - USART2. + * - USART3. + * - DMA1. + * - DMA2. + * . + * @section stm32f4xx_uart_2 STM32F4xx UART driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART/USART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable interrupt priority levels for each UART/USART. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - Programmable DMA error hook. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_PLATFORM_DRIVERS STM32F4xx Platform Drivers + * @details Platform support drivers. Platform drivers do not implement HAL + * standard driver templates, their role is to support platform + * specific functionalities. + * + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_DMA STM32F4xx DMA Support + * @details This DMA helper driver is used by the other drivers in order to + * access the shared DMA resources in a consistent way. + * + * @section stm32f4xx_dma_1 Supported HW resources + * The DMA driver can support any of the following hardware resources: + * - DMA1. + * - DMA2. + * . + * @section stm32f4xx_dma_2 STM32F4xx DMA driver implementation features + * - Exports helper functions/macros to the other drivers that share the + * DMA resource. + * - Automatic DMA clock stop when not in use by any driver. + * - DMA streams and interrupt vectors sharing among multiple drivers. + * . + * @ingroup STM32F4xx_PLATFORM_DRIVERS + */ + +/** + * @defgroup STM32F4xx_RCC STM32F4xx RCC Support + * @details This RCC helper driver is used by the other drivers in order to + * access the shared RCC resources in a consistent way. + * + * @section stm32f4xx_rcc_1 Supported HW resources + * - RCC. + * . + * @section stm32f4xx_rcc_2 STM32F4xx RCC driver implementation features + * - Peripherals reset. + * - Peripherals clock enable. + * - Peripherals clock disable. + * . + * @ingroup STM32F4xx_PLATFORM_DRIVERS + */ diff --git a/Project/os/hal/platforms/STM32F4xx/platform.mk b/Project/os/hal/platforms/STM32F4xx/platform.mk new file mode 100644 index 0000000..87d939c --- /dev/null +++ b/Project/os/hal/platforms/STM32F4xx/platform.mk @@ -0,0 +1,20 @@ +# List of all the STM32F4xx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/stm32_dma.c \ + ${CHIBIOS}/os/hal/platforms/STM32F4xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32F4xx/adc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/i2c_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/uart_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F4xx \ + ${CHIBIOS}/os/hal/platforms/STM32 \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \ No newline at end of file diff --git a/Project/os/hal/platforms/STM32F4xx/stm32_dma.c b/Project/os/hal/platforms/STM32F4xx/stm32_dma.c new file mode 100644 index 0000000..900e995 --- /dev/null +++ b/Project/os/hal/platforms/STM32F4xx/stm32_dma.c @@ -0,0 +1,539 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F4xx/stm32_dma.c + * @brief Enhanced DMA helper driver code. + * + * @addtogroup STM32F4xx_DMA + * @details DMA sharing helper driver. In the STM32 the DMA streams are a + * shared resource, this driver allows to allocate and free DMA + * streams at runtime in order to allow all the other device + * drivers to coordinate the access to the resource. + * @note The DMA ISR handlers are all declared into this module because + * sharing, the various device drivers can associate a callback to + * ISRs when allocating streams. + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/* The following macro is only defined if some driver requiring DMA services + has been enabled.*/ +#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Mask of the DMA1 streams in @p dma_streams_mask. + */ +#define STM32_DMA1_STREAMS_MASK 0x000000FF + +/** + * @brief Mask of the DMA2 streams in @p dma_streams_mask. + */ +#define STM32_DMA2_STREAMS_MASK 0x0000FF00 + +/** + * @brief Post-reset value of the stream CR register. + */ +#define STM32_DMA_CR_RESET_VALUE 0x00000000 + +/** + * @brief Post-reset value of the stream FCR register. + */ +#define STM32_DMA_FCR_RESET_VALUE 0x00000021 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief DMA streams descriptors. + * @details This table keeps the association between an unique stream + * identifier and the involved physical registers. + * @note Don't use this array directly, use the appropriate wrapper macros + * instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc. + */ +const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { + {DMA1_Stream0, &DMA1->LIFCR, 0, 0, DMA1_Stream0_IRQn}, + {DMA1_Stream1, &DMA1->LIFCR, 6, 1, DMA1_Stream1_IRQn}, + {DMA1_Stream2, &DMA1->LIFCR, 16, 2, DMA1_Stream2_IRQn}, + {DMA1_Stream3, &DMA1->LIFCR, 22, 3, DMA1_Stream3_IRQn}, + {DMA1_Stream4, &DMA1->HIFCR, 0, 4, DMA1_Stream4_IRQn}, + {DMA1_Stream5, &DMA1->HIFCR, 6, 5, DMA1_Stream5_IRQn}, + {DMA1_Stream6, &DMA1->HIFCR, 16, 6, DMA1_Stream6_IRQn}, + {DMA1_Stream7, &DMA1->HIFCR, 22, 7, DMA1_Stream7_IRQn}, + {DMA2_Stream0, &DMA2->LIFCR, 0, 8, DMA2_Stream0_IRQn}, + {DMA2_Stream1, &DMA2->LIFCR, 6, 9, DMA2_Stream1_IRQn}, + {DMA2_Stream2, &DMA2->LIFCR, 16, 10, DMA2_Stream2_IRQn}, + {DMA2_Stream3, &DMA2->LIFCR, 22, 11, DMA2_Stream3_IRQn}, + {DMA2_Stream4, &DMA2->HIFCR, 0, 12, DMA2_Stream4_IRQn}, + {DMA2_Stream5, &DMA2->HIFCR, 6, 13, DMA2_Stream5_IRQn}, + {DMA2_Stream6, &DMA2->HIFCR, 16, 14, DMA2_Stream6_IRQn}, + {DMA2_Stream7, &DMA2->HIFCR, 22, 15, DMA2_Stream7_IRQn}, +}; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief DMA ISR redirector type. + */ +typedef struct { + stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ + void *dma_param; /**< @brief DMA callback parameter. */ +} dma_isr_redir_t; + +/** + * @brief Mask of the allocated streams. + */ +static uint32_t dma_streams_mask; + +/** + * @brief DMA IRQ redirectors. + */ +static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief DMA1 stream 0 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream0_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->LISR >> 0) & STM32_DMA_ISR_MASK; + DMA1->LIFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[0].dma_func) + dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream1_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->LISR >> 6) & STM32_DMA_ISR_MASK; + DMA1->LIFCR = STM32_DMA_ISR_MASK << 6; + if (dma_isr_redir[1].dma_func) + dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream2_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->LISR >> 16) & STM32_DMA_ISR_MASK; + DMA1->LIFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[2].dma_func) + dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream3_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->LISR >> 22) & STM32_DMA_ISR_MASK; + DMA1->LIFCR = STM32_DMA_ISR_MASK << 22; + if (dma_isr_redir[3].dma_func) + dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream4_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->HISR >> 0) & STM32_DMA_ISR_MASK; + DMA1->HIFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[4].dma_func) + dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->HISR >> 6) & STM32_DMA_ISR_MASK; + DMA1->HIFCR = STM32_DMA_ISR_MASK << 6; + if (dma_isr_redir[5].dma_func) + dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 6 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream6_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->HISR >> 16) & STM32_DMA_ISR_MASK; + DMA1->HIFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[6].dma_func) + dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 7 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream7_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->HISR >> 22) & STM32_DMA_ISR_MASK; + DMA1->HIFCR = STM32_DMA_ISR_MASK << 22; + if (dma_isr_redir[7].dma_func) + dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 0 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream0_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->LISR >> 0) & STM32_DMA_ISR_MASK; + DMA2->LIFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[8].dma_func) + dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream1_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->LISR >> 6) & STM32_DMA_ISR_MASK; + DMA2->LIFCR = STM32_DMA_ISR_MASK << 6; + if (dma_isr_redir[9].dma_func) + dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream2_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->LISR >> 16) & STM32_DMA_ISR_MASK; + DMA2->LIFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[10].dma_func) + dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream3_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->LISR >> 22) & STM32_DMA_ISR_MASK; + DMA2->LIFCR = STM32_DMA_ISR_MASK << 22; + if (dma_isr_redir[11].dma_func) + dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream4_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->HISR >> 0) & STM32_DMA_ISR_MASK; + DMA2->HIFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[12].dma_func) + dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->HISR >> 6) & STM32_DMA_ISR_MASK; + DMA2->HIFCR = STM32_DMA_ISR_MASK << 6; + if (dma_isr_redir[13].dma_func) + dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 6 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream6_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->HISR >> 16) & STM32_DMA_ISR_MASK; + DMA2->HIFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[14].dma_func) + dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 7 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream7_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->HISR >> 22) & STM32_DMA_ISR_MASK; + DMA2->HIFCR = STM32_DMA_ISR_MASK << 22; + if (dma_isr_redir[15].dma_func) + dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA helper initialization. + * + * @init + */ +void dmaInit(void) { + int i; + + dma_streams_mask = 0; + for (i = 0; i < STM32_DMA_STREAMS; i++) { + _stm32_dma_streams[i].stream->CR = 0; + dma_isr_redir[i].dma_func = NULL; + } + DMA1->LIFCR = 0xFFFFFFFF; + DMA1->HIFCR = 0xFFFFFFFF; + DMA2->LIFCR = 0xFFFFFFFF; + DMA2->HIFCR = 0xFFFFFFFF; +} + +/** + * @brief Allocates a DMA stream. + * @details The stream is allocated and, if required, the DMA clock enabled. + * The function also enables the IRQ vector associated to the stream + * and initializes its priority. + * @pre The stream must not be already in use or an error is returned. + * @post The stream is allocated and the default ISR handler redirected + * to the specified function. + * @post The stream ISR vector is enabled and its priority configured. + * @post The stream must be freed using @p dmaStreamRelease() before it can + * be reused with another peripheral. + * @post The stream is in its post-reset state. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] priority IRQ priority mask for the DMA stream + * @param[in] func handling function pointer, can be @p NULL + * @param[in] param a parameter to be passed to the handling function + * @return The operation status. + * @retval FALSE no error, stream taken. + * @retval TRUE error, stream already taken. + * + * @special + */ +bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param) { + + chDbgCheck(dmastp != NULL, "dmaAllocate"); + + /* Checks if the stream is already taken.*/ + if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) + return TRUE; + + /* Marks the stream as allocated.*/ + dma_isr_redir[dmastp->selfindex].dma_func = func; + dma_isr_redir[dmastp->selfindex].dma_param = param; + dma_streams_mask |= (1 << dmastp->selfindex); + + /* Enabling DMA clocks required by the current streams set.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) + rccEnableDMA1(FALSE); + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) + rccEnableDMA2(FALSE); + + /* Putting the stream in a safe state.*/ + dmaStreamDisable(dmastp); + dmastp->stream->CR = STM32_DMA_CR_RESET_VALUE; + dmastp->stream->FCR = STM32_DMA_FCR_RESET_VALUE; + + /* Enables the associated IRQ vector if a callback is defined.*/ + if (func != NULL) + nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); + + return FALSE; +} + +/** + * @brief Releases a DMA stream. + * @details The stream is freed and, if required, the DMA clock disabled. + * Trying to release a unallocated stream is an illegal operation + * and is trapped if assertions are enabled. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post The stream is again available. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { + + chDbgCheck(dmastp != NULL, "dmaRelease"); + + /* Check if the streams is not taken.*/ + chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, + "dmaRelease(), #1", "not allocated"); + + /* Disables the associated IRQ vector.*/ + nvicDisableVector(dmastp->vector); + + /* Marks the stream as not allocated.*/ + dma_streams_mask &= ~(1 << dmastp->selfindex); + + /* Shutting down clocks that are no more required, if any.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) + rccDisableDMA1(FALSE); + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) + rccDisableDMA2(FALSE); +} + +#endif /* STM32_DMA_REQUIRED */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F4xx/stm32_dma.h b/Project/os/hal/platforms/STM32F4xx/stm32_dma.h new file mode 100644 index 0000000..4983b9e --- /dev/null +++ b/Project/os/hal/platforms/STM32F4xx/stm32_dma.h @@ -0,0 +1,458 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F4xx/stm32_dma.h + * @brief Enhanced-DMA helper driver header. + * @note This file requires definitions from the ST STM32F4xx header file + * stm32f4xx.h. + * + * @addtogroup STM32F4xx_DMA + * @{ + */ + +#ifndef _STM32_DMA_H_ +#define _STM32_DMA_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Total number of DMA streams. + * @note This is the total number of streams among all the DMA units. + */ +#define STM32_DMA_STREAMS 16 + +/** + * @brief Mask of the ISR bits passed to the DMA callback functions. + */ +#define STM32_DMA_ISR_MASK 0x3D + +/** + * @brief Returns the channel associated to the specified stream. + * + * @param[in] id the unique numeric stream identifier + * @param[in] c a stream/channel association word, one channel per + * nibble + * @return Returns the channel associated to the stream. + */ +#define STM32_DMA_GETCHANNEL(id, c) (((c) >> (((id) & 7) * 4)) & 7) + +/** + * @brief Returns an unique numeric identifier for a DMA stream. + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return An unique numeric stream identifier. + */ +#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 8) + (stream)) + +/** + * @brief Returns a DMA stream identifier mask. + * + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return A DMA stream identifier mask. + */ +#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ + (1 << STM32_DMA_STREAM_ID(dma, stream)) + +/** + * @brief Checks if a DMA stream unique identifier belongs to a mask. + * @param[in] id the stream numeric identifier + * @param[in] mask the stream numeric identifiers mask + * + * @retval The check result. + * @retval FALSE id does not belong to the mask. + * @retval TRUE id belongs to the mask. + */ +#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask))) + +/** + * @name DMA streams identifiers + * @{ + */ +/** + * @brief Returns a pointer to a stm32_dma_stream_t structure. + * + * @param[in] id the stream numeric identifier + * @return A pointer to the stm32_dma_stream_t constant structure + * associated to the DMA stream. + */ +#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) + +#define STM32_DMA1_STREAM0 STM32_DMA_STREAM(0) +#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(1) +#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(2) +#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(3) +#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(4) +#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(5) +#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(6) +#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(7) +#define STM32_DMA2_STREAM0 STM32_DMA_STREAM(8) +#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(9) +#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(10) +#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(11) +#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(12) +#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(13) +#define STM32_DMA2_STREAM6 STM32_DMA_STREAM(14) +#define STM32_DMA2_STREAM7 STM32_DMA_STREAM(15) +/** @} */ + +/** + * @name CR register constants common to all DMA types + * @{ + */ +#define STM32_DMA_CR_EN DMA_SxCR_EN +#define STM32_DMA_CR_TEIE DMA_SxCR_TEIE +#define STM32_DMA_CR_HTIE DMA_SxCR_HTIE +#define STM32_DMA_CR_TCIE DMA_SxCR_TCIE +#define STM32_DMA_CR_DIR_MASK DMA_SxCR_DIR +#define STM32_DMA_CR_DIR_P2M 0 +#define STM32_DMA_CR_DIR_M2P DMA_SxCR_DIR_0 +#define STM32_DMA_CR_DIR_M2M DMA_SxCR_DIR_1 +#define STM32_DMA_CR_CIRC DMA_SxCR_CIRC +#define STM32_DMA_CR_PINC DMA_SxCR_PINC +#define STM32_DMA_CR_MINC DMA_SxCR_MINC +#define STM32_DMA_CR_PSIZE_MASK DMA_SxCR_PSIZE +#define STM32_DMA_CR_PSIZE_BYTE 0 +#define STM32_DMA_CR_PSIZE_HWORD DMA_SxCR_PSIZE_0 +#define STM32_DMA_CR_PSIZE_WORD DMA_SxCR_PSIZE_1 +#define STM32_DMA_CR_MSIZE_MASK DMA_SxCR_MSIZE +#define STM32_DMA_CR_MSIZE_BYTE 0 +#define STM32_DMA_CR_MSIZE_HWORD DMA_SxCR_MSIZE_0 +#define STM32_DMA_CR_MSIZE_WORD DMA_SxCR_MSIZE_1 +#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_MSIZE_MASK | \ + STM32_DMA_CR_MSIZE_MASK) +#define STM32_DMA_CR_PL_MASK DMA_SxCR_PL +#define STM32_DMA_CR_PL(n) ((n) << 16) +/** @} */ + +/** + * @name CR register constants only found in STM32F2xx/STM32F4xx + * @{ + */ +#define STM32_DMA_CR_DMEIE DMA_SxCR_DMEIE +#define STM32_DMA_CR_PFCTRL DMA_SxCR_PFCTRL +#define STM32_DMA_CR_PINCOS DMA_SxCR_PINCOS +#define STM32_DMA_CR_DBM DMA_SxCR_DBM +#define STM32_DMA_CR_CT DMA_SxCR_CT +#define STM32_DMA_CR_PBURST_MASK DMA_SxCR_PBURST +#define STM32_DMA_CR_PBURST_SINGLE 0 +#define STM32_DMA_CR_PBURST_INCR4 DMA_SxCR_PBURST_0 +#define STM32_DMA_CR_PBURST_INCR8 DMA_SxCR_PBURST_1 +#define STM32_DMA_CR_PBURST_INCR16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) +#define STM32_DMA_CR_MBURST_MASK DMA_SxCR_MBURST +#define STM32_DMA_CR_MBURST_SINGLE 0 +#define STM32_DMA_CR_MBURST_INCR4 DMA_SxCR_MBURST_0 +#define STM32_DMA_CR_MBURST_INCR8 DMA_SxCR_MBURST_1 +#define STM32_DMA_CR_MBURST_INCR16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) +#define STM32_DMA_CR_CHSEL_MASK DMA_SxCR_CHSEL +#define STM32_DMA_CR_CHSEL(n) ((n) << 25) +/** @} */ + +/** + * @name FCR register constants only found in STM32F2xx/STM32F4xx + * @{ + */ +#define STM32_DMA_FCR_FEIE DMA_SxFCR_FEIE +#define STM32_DMA_FCR_FS_MASK DMA_SxFCR_FS +#define STM32_DMA_FCR_DMDIS DMA_SxFCR_DMDIS +#define STM32_DMA_FCR_FTH_MASK DMA_SxFCR_FTH +#define STM32_DMA_FCR_FTH_1Q 0 +#define STM32_DMA_FCR_FTH_HALF DMA_SxFCR_FTH_0 +#define STM32_DMA_FCR_FTH_3Q DMA_SxFCR_FTH_1 +#define STM32_DMA_FCR_FTH_FULL (DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1) +/** @} */ + +/** + * @name Status flags passed to the ISR callbacks + */ +#define STM32_DMA_ISR_FEIF DMA_LISR_FEIF0 +#define STM32_DMA_ISR_DMEIF DMA_LISR_DMEIF0 +#define STM32_DMA_ISR_TEIF DMA_LISR_TEIF0 +#define STM32_DMA_ISR_HTIF DMA_LISR_HTIF0 +#define STM32_DMA_ISR_TCIF DMA_LISR_TCIF0 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA stream descriptor structure. + */ +typedef struct { + DMA_Stream_TypeDef *stream; /**< @brief Associated DMA stream. */ + volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ + uint8_t ishift; /**< @brief Bits offset in xIFCR + register. */ + uint8_t selfindex; /**< @brief Index to self in array. */ + uint8_t vector; /**< @brief Associated IRQ vector. */ +} stm32_dma_stream_t; + +/** + * @brief STM32 DMA ISR function type. + * + * @param[in] p parameter for the registered function + * @param[in] flags pre-shifted content of the xISR register, the bits + * are aligned to bit zero + */ +typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Associates a peripheral data register to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the PAR register + * + * @special + */ +#define dmaStreamSetPeripheral(dmastp, addr) { \ + (dmastp)->stream->PAR = (uint32_t)(addr); \ +} + +/** + * @brief Associates a memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the M0AR register + * + * @special + */ +#define dmaStreamSetMemory0(dmastp, addr) { \ + (dmastp)->stream->M0AR = (uint32_t)(addr); \ +} + +/** + * @brief Associates an alternate memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the M1AR register + * + * @special + */ +#define dmaStreamSetMemory1(dmastp, addr) { \ + (dmastp)->stream->M1AR = (uint32_t)(addr); \ +} + +/** + * @brief Sets the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] size value to be written in the CNDTR register + * + * @special + */ +#define dmaStreamSetTransactionSize(dmastp, size) { \ + (dmastp)->stream->NDTR = (uint32_t)(size); \ +} + +/** + * @brief Returns the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @return The number of transfers to be performed. + * + * @special + */ +#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->stream->NDTR)) + +/** + * @brief Programs the stream mode settings. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CR register + * + * @special + */ +#define dmaStreamSetMode(dmastp, mode) { \ + (dmastp)->stream->CR = (uint32_t)(mode); \ +} + +/** + * @brief Programs the stream FIFO settings. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the FCR register + * + * @special + */ +#define dmaStreamSetFIFO(dmastp, mode) { \ + (dmastp)->stream->FCR = (uint32_t)(mode); \ +} + +/** + * @brief DMA stream enable. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamEnable(dmastp) { \ + (dmastp)->stream->CR |= STM32_DMA_CR_EN; \ +} + +/** + * @brief DMA stream disable. + * @details The function disables the specified stream, waits for the disable + * operation to complete and then clears any pending interrupt. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamDisable(dmastp) { \ + (dmastp)->stream->CR &= ~STM32_DMA_CR_EN; \ + while (((dmastp)->stream->CR & STM32_DMA_CR_EN) != 0) \ + ; \ + dmaStreamClearInterrupt(dmastp); \ +} + +/** + * @brief DMA stream interrupt sources clear. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamClearInterrupt(dmastp) { \ + *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ +} + +/** + * @brief Starts a memory to memory operation using the specified stream. + * @note The default transfer data mode is "byte to byte" but it can be + * changed by specifying extra options in the @p mode parameter. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register, this value + * is implicitly ORed with: + * - @p STM32_DMA_CR_MINC + * - @p STM32_DMA_CR_PINC + * - @p STM32_DMA_CR_DIR_M2M + * - @p STM32_DMA_CR_EN + * . + * @param[in] src source address + * @param[in] dst destination address + * @param[in] n number of data units to copy + */ +#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ + dmaStreamSetPeripheral(dmastp, src); \ + dmaStreamSetMemory0(dmastp, dst); \ + dmaStreamSetTransactionSize(dmastp, n); \ + dmaStreamSetMode(dmastp, (mode) | \ + STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ + STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ +} + +/** + * @brief Polled wait for DMA transfer end. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + */ +#define dmaWaitCompletion(dmastp) { \ + while ((dmastp)->stream->NDTR > 0) \ + ; \ + dmaStreamDisable(dmastp); \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void dmaInit(void); + bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param); + void dmaStreamRelease(const stm32_dma_stream_t *dmastp); +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_DMA_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F4xx/stm32_rcc.h b/Project/os/hal/platforms/STM32F4xx/stm32_rcc.h new file mode 100644 index 0000000..e1ee39d --- /dev/null +++ b/Project/os/hal/platforms/STM32F4xx/stm32_rcc.h @@ -0,0 +1,1078 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32F4xx/stm32_rcc.h + * @brief RCC helper driver header. + * @note This file requires definitions from the ST header file + * @p stm32f4xx.h. + * + * @addtogroup STM32F4xx_RCC + * @{ + */ +#ifndef _STM32_RCC_ +#define _STM32_RCC_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic RCC operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB1(mask, lp) { \ + RCC->APB1ENR |= (mask); \ + if (lp) \ + RCC->APB1LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB1(mask, lp) { \ + RCC->APB1ENR &= ~(mask); \ + if (lp) \ + RCC->APB1LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * + * @api + */ +#define rccResetAPB1(mask) { \ + RCC->APB1RSTR |= (mask); \ + RCC->APB1RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB2(mask, lp) { \ + RCC->APB2ENR |= (mask); \ + if (lp) \ + RCC->APB2LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB2(mask, lp) { \ + RCC->APB2ENR &= ~(mask); \ + if (lp) \ + RCC->APB2LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * + * @api + */ +#define rccResetAPB2(mask) { \ + RCC->APB2RSTR |= (mask); \ + RCC->APB2RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB1 bus. + * + * @param[in] mask AHB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB1(mask, lp) { \ + RCC->AHB1ENR |= (mask); \ + if (lp) \ + RCC->AHB1LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB1 bus. + * + * @param[in] mask AHB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB1(mask, lp) { \ + RCC->AHB1ENR &= ~(mask); \ + if (lp) \ + RCC->AHB1LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB1 bus. + * + * @param[in] mask AHB1 peripherals mask + * + * @api + */ +#define rccResetAHB1(mask) { \ + RCC->AHB1RSTR |= (mask); \ + RCC->AHB1RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB2 bus. + * + * @param[in] mask AHB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB2(mask, lp) { \ + RCC->AHB2ENR |= (mask); \ + if (lp) \ + RCC->AHB2LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB2 bus. + * + * @param[in] mask AHB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB2(mask, lp) { \ + RCC->AHB2ENR &= ~(mask); \ + if (lp) \ + RCC->AHB2LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB2 bus. + * + * @param[in] mask AHB2 peripherals mask + * + * @api + */ +#define rccResetAHB2(mask) { \ + RCC->AHB2RSTR |= (mask); \ + RCC->AHB2RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus. + * + * @param[in] mask AHB3 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB3(mask, lp) { \ + RCC->AHB3ENR |= (mask); \ + if (lp) \ + RCC->AHB3LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus. + * + * @param[in] mask AHB3 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB3(mask, lp) { \ + RCC->AHB3ENR &= ~(mask); \ + if (lp) \ + RCC->AHB3LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB3 (FSMC) bus. + * + * @param[in] mask AHB3 peripherals mask + * + * @api + */ +#define rccResetAHB3(mask) { \ + RCC->AHB3RSTR |= (mask); \ + RCC->AHB3RSTR = 0; \ +} +/** @} */ + +/** + * @name ADC peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the ADC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Disables the ADC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Resets the ADC1 peripheral. + * + * @api + */ +#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) + +/** + * @brief Enables the ADC2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC2(lp) rccEnableAPB2(RCC_APB2ENR_ADC2EN, lp) + +/** + * @brief Disables the ADC2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC2(lp) rccDisableAPB2(RCC_APB2ENR_ADC2EN, lp) + +/** + * @brief Resets the ADC2 peripheral. + * + * @api + */ +#define rccResetADC2() rccResetAPB2(RCC_APB2RSTR_ADC2RST) + +/** + * @brief Enables the ADC3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC3(lp) rccEnableAPB2(RCC_APB2ENR_ADC3EN, lp) + +/** + * @brief Disables the ADC3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC3(lp) rccDisableAPB2(RCC_APB2ENR_ADC3EN, lp) + +/** + * @brief Resets the ADC3 peripheral. + * + * @api + */ +#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST) +/** @} */ + +/** + * @name DMA peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp) + +/** + * @brief Disables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA1(lp) rccDisableAHB1(RCC_AHB1ENR_DMA1EN, lp) + +/** + * @brief Resets the DMA1 peripheral. + * + * @api + */ +#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST) + +/** + * @brief Enables the DMA2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp) + +/** + * @brief Disables the DMA2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA2(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2EN, lp) + +/** + * @brief Resets the DMA2 peripheral. + * + * @api + */ +#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST) +/** @} */ + +/** + * @name PWR interface specific RCC operations + * @{ + */ +/** + * @brief Enables the PWR interface clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Disables PWR interface clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Resets the PWR interface. + * + * @api + */ +#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST) +/** @} */ + + +/** + * @name CAN peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the CAN1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp) + +/** + * @brief Disables the CAN1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp) + +/** + * @brief Resets the CAN1 peripheral. + * + * @api + */ +#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST) + +/** + * @brief Enables the CAN2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableCAN2(lp) rccEnableAPB1(RCC_APB1ENR_CAN2EN, lp) + +/** + * @brief Disables the CAN2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableCAN2(lp) rccDisableAPB1(RCC_APB1ENR_CAN2EN, lp) + +/** + * @brief Resets the CAN2 peripheral. + * + * @api + */ +#define rccResetCAN2() rccResetAPB1(RCC_APB1RSTR_CAN2RST) +/** @} */ + +/** + * @name ETH peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the ETH peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN | \ + RCC_AHB1ENR_ETHMACTXEN | \ + RCC_AHB1ENR_ETHMACRXEN, lp) + +/** + * @brief Disables the ETH peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableETH(lp) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \ + RCC_AHB1ENR_ETHMACTXEN | \ + RCC_AHB1ENR_ETHMACRXEN, lp) + +/** + * @brief Resets the ETH peripheral. + * + * @api + */ +#define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETHMACRST) +/** @} */ + +/** + * @name I2C peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Disables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Resets the I2C1 peripheral. + * + * @api + */ +#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) + +/** + * @brief Enables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Disables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Resets the I2C2 peripheral. + * + * @api + */ +#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) + +/** + * @brief Enables the I2C3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C3(lp) rccEnableAPB1(RCC_APB1ENR_I2C3EN, lp) + +/** + * @brief Disables the I2C3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C3(lp) rccDisableAPB1(RCC_APB1ENR_I2C3EN, lp) + +/** + * @brief Resets the I2C3 peripheral. + * + * @api + */ +#define rccResetI2C3() rccResetAPB1(RCC_APB1RSTR_I2C3RST) +/** @} */ + +/** + * @name OTG peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the OTG_FS peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2LPENR_OTGFSLPEN, lp) + +/** + * @brief Disables the OTG_FS peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableOTG_FS(lp) rccEnableAHB2(RCC_AHB2LPENR_OTGFSLPEN, lp) + +/** + * @brief Resets the OTG_FS peripheral. + * + * @api + */ +#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST) +/** @} */ + +/** + * @name SDIO peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the SDIO peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSDIO(lp) rccEnableAPB2(RCC_APB2ENR_SDIOEN, lp) + +/** + * @brief Disables the SDIO peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSDIO(lp) rccDisableAPB2(RCC_APB2ENR_SDIOEN, lp) + +/** + * @brief Resets the SDIO peripheral. + * @note Not supported in this family, does nothing. + * + * @api + */ +#define rccResetSDIO() rccResetAPB2(RCC_APB2RSTR_SDIORST) +/** @} */ + +/** + * @name SPI peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Disables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Resets the SPI1 peripheral. + * + * @api + */ +#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) + +/** + * @brief Enables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Disables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Resets the SPI2 peripheral. + * + * @api + */ +#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) + +/** + * @brief Enables the SPI3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp) + +/** + * @brief Disables the SPI3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp) + +/** + * @brief Resets the SPI3 peripheral. + * + * @api + */ +#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST) +/** @} */ + +/** + * @name TIM peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Disables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Resets the TIM1 peripheral. + * + * @api + */ +#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST) + +/** + * @brief Enables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Disables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Resets the TIM2 peripheral. + * + * @api + */ +#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) + +/** + * @brief Enables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Disables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Resets the TIM3 peripheral. + * + * @api + */ +#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) + +/** + * @brief Enables the TIM4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Disables the TIM4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Resets the TIM4 peripheral. + * + * @api + */ +#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST) + +/** + * @brief Enables the TIM5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp) + +/** + * @brief Disables the TIM5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp) + +/** + * @brief Resets the TIM5 peripheral. + * + * @api + */ +#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST) + +/** + * @brief Enables the TIM8 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp) + +/** + * @brief Disables the TIM8 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp) + +/** + * @brief Resets the TIM8 peripheral. + * + * @api + */ +#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST) +/** @} */ + +/** + * @name USART/UART peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Disables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) + +/** + * @brief Enables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Disables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Resets the USART2 peripheral. + * + * @api + */ +#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) + +/** + * @brief Enables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Disables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Resets the USART3 peripheral. + * + * @api + */ +#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST) + +/** + * @brief Enables the USART6 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp) + +/** + * @brief Disables the USART6 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART6(lp) rccDisableAPB2(RCC_APB2ENR_USART6EN, lp) + +/** + * @brief Enables the UART4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp) + +/** + * @brief Disables the UART4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp) + +/** + * @brief Resets the UART4 peripheral. + * + * @api + */ +#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST) + +/** + * @brief Enables the UART5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp) + +/** + * @brief Disables the UART5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp) + +/** + * @brief Resets the UART5 peripheral. + * + * @api + */ +#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST) + +/** + * @brief Resets the USART6 peripheral. + * + * @api + */ +#define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_RCC_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32F4xx/stm32f4xx.h b/Project/os/hal/platforms/STM32F4xx/stm32f4xx.h new file mode 100644 index 0000000..f4e88fc --- /dev/null +++ b/Project/os/hal/platforms/STM32F4xx/stm32f4xx.h @@ -0,0 +1,7002 @@ +/** + ****************************************************************************** + * @file stm32f4xx.h + * @author MCD Application Team + * @version V1.0.0 + * @date 30-September-2011 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F4xx devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx + * @{ + */ + +#ifndef __STM32F4xx_H +#define __STM32F4xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F4XX) + #define STM32F4XX +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (STM32F4XX) + #error "Please select first the target STM32F4XX device used in your application (in stm32f4xx.h file)" +#endif + +#if !defined (USE_STDPERIPH_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief STM32F4XX Standard Peripherals Library version number V1.0.0 + */ +#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F4XX_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @brief STM32F4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ + FPU_IRQn = 81 /*!< FPU global interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +/* CHIBIOS FIX */ +/*#include "system_stm32f4xx.h"*/ +#include + +/** @addtogroup Exported_types + * @{ + */ +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RESERVED8; + __IO uint32_t PTPTSSR; + uint32_t RESERVED9[565]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARSWTR; + uint32_t RESERVED10[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */ +} FLASH_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FSMC_Bank2_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FSMC_Bank3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ + __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ + __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ + __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ + __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ +} FSMC_Bank4_TypeDef; + +/** + * @brief General Purpose I/O + */ +/* CHIBIOS FIX */ +#if 0 +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ + __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; +#endif + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + uint16_t RESERVED11; /*!< Reserved, 0x46 */ + __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + uint16_t RESERVED12; /*!< Reserved, 0x4A */ + __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint16_t RESERVED13; /*!< Reserved, 0x4E */ + __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ + uint16_t RESERVED14; /*!< Reserved, 0x52 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief Crypto Processor + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ +} CRYP_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */ +} HASH_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */ +#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ +#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ +#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ +#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ +#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ +#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) +#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) +#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) + +/*!< FSMC Bankx registers base address */ +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t )0xE0042000) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) +#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint8_t)0x01) /*!. + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32L1xx/adc_lld.c + * @brief STM32L1xx ADC subsystem low level driver source. + * + * @addtogroup ADC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ADC1 driver identifier.*/ +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +ADCDriver ADCD1; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief ADC DMA ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { + + /* DMA errors handling.*/ + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + /* DMA, this could help only if the DMA tries to access an unmapped + address space or violates alignment rules.*/ + _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); + } + else { + /* It is possible that the conversion group has already be reset by the + ADC error handler, in this case this interrupt is spurious.*/ + if (adcp->grpp != NULL) { + if ((flags & STM32_DMA_ISR_HTIF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + if ((flags & STM32_DMA_ISR_TCIF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } + } + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +/** + * @brief ADC interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(ADC1_IRQHandler) { + uint32_t sr; + + CH_IRQ_PROLOGUE(); + + sr = ADC1->SR; + ADC1->SR = 0; + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + if (ADCD1.grpp != NULL) + _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW); + } + /* TODO: Add here analog watchdog handling.*/ + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +#if STM32_ADC_USE_ADC1 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); + ADCD1.adc = ADC1; + ADCD1.dmastp = STM32_DMA1_STREAM1; + ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; +#endif + + /* The shared vector is initialized on driver initialization and never + disabled.*/ + nvicEnableVector(ADC1_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY)); +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + /* If in stopped state then enables the ADC and DMA clocks.*/ + if (adcp->state == ADC_STOP) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC1_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); + rccEnableADC1(FALSE); + } +#endif /* STM32_ADC_USE_ADC1 */ + + /* ADC initial setup, starting the analog part here in order to reduce + the latency when starting a conversion.*/ + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + adcp->adc->CR2 = ADC_CR2_ADON; + } +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + /* If in ready state then disables the ADC clock and analog part.*/ + if (adcp->state == ADC_READY) { + dmaStreamRelease(adcp->dmastp); + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) + rccDisableADC1(FALSE); +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + uint32_t mode; + const ADCConversionGroup *grpp = adcp->grpp; + + /* DMA setup.*/ + mode = adcp->dmamode; + if (grpp->circular) { + mode |= STM32_DMA_CR_CIRC; + } + if (adcp->depth > 1) { + /* If the buffer depth is greater than one then the half transfer interrupt + interrupt is enabled in order to allows streaming processing.*/ + mode |= STM32_DMA_CR_HTIE; + } + dmaStreamSetMemory0(adcp->dmastp, adcp->samples); + dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * + (uint32_t)adcp->depth); + dmaStreamSetMode(adcp->dmastp, mode); + dmaStreamEnable(adcp->dmastp); + + /* ADC setup.*/ + adcp->adc->SR = 0; + adcp->adc->SMPR1 = grpp->smpr1; + adcp->adc->SMPR2 = grpp->smpr2; + adcp->adc->SMPR3 = grpp->smpr3; + adcp->adc->SQR1 = grpp->sqr1; + adcp->adc->SQR2 = grpp->sqr2; + adcp->adc->SQR3 = grpp->sqr3; + adcp->adc->SQR4 = grpp->sqr4; + adcp->adc->SQR5 = grpp->sqr5; + + /* ADC configuration and start, the start is performed using the method + specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/ + adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN; + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT | ADC_CR2_DMA | + ADC_CR2_DDS | ADC_CR2_ADON; +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + dmaStreamDisable(adcp->dmastp); + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + adcp->adc->CR2 = ADC_CR2_ADON; +} + +/** + * @brief Enables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + */ +void adcSTM32EnableTSVREFE(void) { + + ADC->CCR |= ADC_CCR_TSVREFE; +} + +/** + * @brief Disables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + */ +void adcSTM32DisableTSVREFE(void) { + + ADC->CCR &= ~ADC_CCR_TSVREFE; +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32L1xx/adc_lld.h b/Project/os/hal/platforms/STM32L1xx/adc_lld.h new file mode 100644 index 0000000..d403087 --- /dev/null +++ b/Project/os/hal/platforms/STM32L1xx/adc_lld.h @@ -0,0 +1,480 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32L1xx/adc_lld.h + * @brief STM32L1xx ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Triggers selection + * @{ + */ +#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */ +/** @} */ + +/** + * @name ADC clock divider settings + * @{ + */ +#define ADC_CCR_ADCPRE_DIV1 0 +#define ADC_CCR_ADCPRE_DIV2 1 +#define ADC_CCR_ADCPRE_DIV4 2 +/** @} */ + +/** + * @name Available analog channels + * @{ + */ +#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ +#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ +#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ +#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ +#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ +#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ +#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ +#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ +#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ +#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ +#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ +#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ +#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ +#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ +#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ +#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ +#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ +#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */ +#define ADC_CHANNEL_IN18 18 /**< @brief External analog input 18. */ +#define ADC_CHANNEL_IN19 19 /**< @brief External analog input 19. */ +#define ADC_CHANNEL_IN20 20 /**< @brief External analog input 20. */ +#define ADC_CHANNEL_IN21 21 /**< @brief External analog input 21. */ +#define ADC_CHANNEL_IN22 22 /**< @brief External analog input 22. */ +#define ADC_CHANNEL_IN23 23 /**< @brief External analog input 23. */ +#define ADC_CHANNEL_IN24 24 /**< @brief External analog input 24. */ +#define ADC_CHANNEL_IN25 25 /**< @brief External analog input 25. */ +/** @} */ + +/** + * @name Sampling rates + * @{ + */ +#define ADC_SAMPLE_4 0 /**< @brief 4 cycles sampling time. */ +#define ADC_SAMPLE_9 1 /**< @brief 9 cycles sampling time. */ +#define ADC_SAMPLE_16 2 /**< @brief 16 cycles sampling time. */ +#define ADC_SAMPLE_24 3 /**< @brief 24 cycles sampling time. */ +#define ADC_SAMPLE_48 4 /**< @brief 48 cycles sampling time. */ +#define ADC_SAMPLE_96 5 /**< @brief 96 cycles sampling time. */ +#define ADC_SAMPLE_192 6 /**< @brief 192 cycles sampling time. */ +#define ADC_SAMPLE_384 7 /**< @brief 384 cycles sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC1 TRUE +#endif + +/** + * @brief ADC common clock divider. + * @note This setting is influenced by the VDDA voltage and other + * external conditions, please refer to the STM32L15x datasheet + * for more info.
+ * See section 6.3.15 "12-bit ADC characteristics". + */ +#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__) +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV1 +#endif + +/** + * @brief ADC1 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC interrupt priority level setting. + */ +#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC1 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 +#error "ADC1 not present in the selected device" +#endif + +#if !STM32_ADC_USE_ADC1 +#error "ADC driver activated but no ADC peripheral assigned" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ + ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */ +} adcerror_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief ADC error callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] err ADC error code + */ +typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note The use of this configuration structure requires knowledge of + * STM32 ADC cell registers interface, please refer to the STM32 + * reference manual for details. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool_t circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /** + * @brief Error callback or @p NULL. + */ + adcerrorcallback_t error_cb; + /* End of the mandatory fields.*/ + /** + * @brief ADC CR1 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR1_SCAN that is enforced inside the driver. + */ + uint32_t cr1; + /** + * @brief ADC CR2 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are + * enforced inside the driver. + */ + uint32_t cr2; + /** + * @brief ADC SMPR1 register initialization data. + * @details In this field must be specified the sample times for channels + * 20...25. + */ + uint32_t smpr1; + /** + * @brief ADC SMPR2 register initialization data. + * @details In this field must be specified the sample times for channels + * 10...19. + */ + uint32_t smpr2; + /** + * @brief ADC SMPR3 register initialization data. + * @details In this field must be specified the sample times for channels + * 0...9. + */ + uint32_t smpr3; + /** + * @brief ADC SQR1 register initialization data. + * @details Conversion group sequence 25...27 + sequence length. + */ + uint32_t sqr1; + /** + * @brief ADC SQR2 register initialization data. + * @details Conversion group sequence 19...24. + */ + uint32_t sqr2; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 13...18. + */ + uint32_t sqr3; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 7...12. + */ + uint32_t sqr4; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 1...6. + */ + uint32_t sqr5; +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the ADCx registers block. + */ + ADC_TypeDef *adc; + /** + * @brief Pointer to associated SMA channel. + */ + const stm32_dma_stream_t *dmastp; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Sequences building helper macros + * @{ + */ +/** + * @brief Number of channels in a conversion sequence. + */ +#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) + +#define ADC_SQR5_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ +#define ADC_SQR5_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ +#define ADC_SQR5_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ +#define ADC_SQR5_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ +#define ADC_SQR5_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ +#define ADC_SQR5_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ + +#define ADC_SQR4_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ +#define ADC_SQR4_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ +#define ADC_SQR4_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ +#define ADC_SQR4_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ +#define ADC_SQR4_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ +#define ADC_SQR4_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ + +#define ADC_SQR3_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ +#define ADC_SQR3_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ +#define ADC_SQR3_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ +#define ADC_SQR3_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ +#define ADC_SQR3_SQ17_N(n) ((n) << 20) /**< @brief 17th channel in seq.*/ +#define ADC_SQR3_SQ18_N(n) ((n) << 25) /**< @brief 18th channel in seq.*/ + +#define ADC_SQR2_SQ19_N(n) ((n) << 0) /**< @brief 19th channel in seq.*/ +#define ADC_SQR2_SQ20_N(n) ((n) << 5) /**< @brief 20th channel in seq.*/ +#define ADC_SQR2_SQ21_N(n) ((n) << 10) /**< @brief 21th channel in seq.*/ +#define ADC_SQR2_SQ22_N(n) ((n) << 15) /**< @brief 22th channel in seq.*/ +#define ADC_SQR2_SQ23_N(n) ((n) << 20) /**< @brief 23th channel in seq.*/ +#define ADC_SQR2_SQ24_N(n) ((n) << 25) /**< @brief 24th channel in seq.*/ + +#define ADC_SQR1_SQ25_N(n) ((n) << 0) /**< @brief 25th channel in seq.*/ +#define ADC_SQR1_SQ26_N(n) ((n) << 5) /**< @brief 26th channel in seq.*/ +#define ADC_SQR1_SQ27_N(n) ((n) << 10) /**< @brief 27th channel in seq.*/ +/** @} */ + +/** + * @name Sampling rate settings helper macros + * @{ + */ +#define ADC_SMPR3_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ +#define ADC_SMPR3_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SMPR3_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SMPR3_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SMPR3_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SMPR3_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SMPR3_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SMPR3_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SMPR3_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SMPR3_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ + +#define ADC_SMPR2_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SMPR2_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SMPR2_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SMPR2_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SMPR2_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SMPR2_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ +#define ADC_SMPR2_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor + sampling time. */ +#define ADC_SMPR2_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference + sampling time. */ +#define ADC_SMPR2_SMP_AN18(n) ((n) << 24) /**< @brief AN18 sampling time. */ +#define ADC_SMPR2_SMP_AN19(n) ((n) << 27) /**< @brief AN19 sampling time. */ + +#define ADC_SMPR1_SMP_AN20(n) ((n) << 0) /**< @brief AN20 sampling time. */ +#define ADC_SMPR1_SMP_AN21(n) ((n) << 3) /**< @brief AN21 sampling time. */ +#define ADC_SMPR1_SMP_AN22(n) ((n) << 6) /**< @brief AN22 sampling time. */ +#define ADC_SMPR1_SMP_AN23(n) ((n) << 9) /**< @brief AN23 sampling time. */ +#define ADC_SMPR1_SMP_AN24(n) ((n) << 12) /**< @brief AN24 sampling time. */ +#define ADC_SMPR1_SMP_AN25(n) ((n) << 15) /**< @brief AN25 sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); + void adcSTM32EnableTSVREFE(void); + void adcSTM32DisableTSVREFE(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32L1xx/hal_lld.c b/Project/os/hal/platforms/STM32L1xx/hal_lld.c new file mode 100644 index 0000000..3686e1c --- /dev/null +++ b/Project/os/hal/platforms/STM32L1xx/hal_lld.c @@ -0,0 +1,237 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32L1xx/hal_lld.c + * @brief STM32L1xx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the backup domain. + */ +static void hal_lld_backup_domain_init(void) { + + /* Backup domain access enabled and left open.*/ + PWR->CR |= PWR_CR_DBP; + + /* Reset BKP domain if different clock source selected.*/ + if ((RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL){ + /* Backup domain reset.*/ + RCC->CSR |= RCC_CSR_RTCRST; + RCC->CSR &= ~RCC_CSR_RTCRST; + } + + /* If enabled then the LSE is started.*/ +#if STM32_LSE_ENABLED + RCC->CSR |= RCC_CSR_LSEON; + while ((RCC->CSR & RCC_CSR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ +#endif + +#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK + /* If the backup domain hasn't been initialized yet then proceed with + initialization.*/ + if ((RCC->CSR & RCC_CSR_RTCEN) == 0) { + /* Selects clock source.*/ + RCC->CSR |= STM32_RTCSEL; + + /* RTC clock enabled.*/ + RCC->CSR |= RCC_CSR_RTCEN; + } +#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */ +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* Reset of all peripherals.*/ + rccResetAHB(!RCC_AHBRSTR_FLITFRST); + rccResetAPB1(!RCC_APB1RSTR_PWRRST); + rccResetAPB2(!0); + + /* SysTick initialization using the system clock.*/ + SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + + /* DWT cycle counter enable.*/ + SCS_DEMCR |= SCS_DEMCR_TRCENA; + DWT_CTRL |= DWT_CTRL_CYCCNTENA; + + /* PWR clock enabled.*/ + rccEnablePWRInterface(FALSE); + + /* Initializes the backup domain.*/ + hal_lld_backup_domain_init(); + +#if defined(STM32_DMA_REQUIRED) + dmaInit(); +#endif + + /* Programmable voltage detector enable.*/ +#if STM32_PVD_ENABLE + PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); +#endif /* STM32_PVD_ENABLE */ +} + +/** + * @brief STM32L1xx voltage, clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +#if defined(STM32L1XX_MD) || defined(__DOXYGEN__) +/** + * @brief Clocks and internal voltage initialization. + */ +void stm32_clock_init(void) { + +#if !STM32_NO_INIT + /* PWR clock enable.*/ + RCC->APB1ENR = RCC_APB1ENR_PWREN; + + /* Core voltage setup.*/ + while ((PWR->CSR & PWR_CSR_VOSF) != 0) + ; /* Waits until regulator is stable. */ + PWR->CR = STM32_VOS; + while ((PWR->CSR & PWR_CSR_VOSF) != 0) + ; /* Waits until regulator is stable. */ + + /* Initial clocks setup and wait for MSI stabilization, the MSI clock is + always enabled because it is the fallback clock when PLL the fails. + Trim fields are not altered from reset values.*/ + RCC->CFGR = 0; + RCC->ICSCR = (RCC->ICSCR & ~STM32_MSIRANGE_MASK) | STM32_MSIRANGE; + RCC->CSR = RCC_CSR_RMVF; + RCC->CR = RCC_CR_MSION; + while ((RCC->CR & RCC_CR_MSIRDY) == 0) + ; /* Waits until MSI is stable. */ + +#if STM32_HSI_ENABLED + /* HSI activation.*/ + RCC->CR |= RCC_CR_HSION; + while ((RCC->CR & RCC_CR_HSIRDY) == 0) + ; /* Waits until HSI is stable. */ +#endif + +#if STM32_HSE_ENABLED + /* HSE activation.*/ + RCC->CR |= RCC_CR_HSEON; + while ((RCC->CR & RCC_CR_HSERDY) == 0) + ; /* Waits until HSE is stable. */ +#endif + +#if STM32_LSI_ENABLED + /* LSI activation.*/ + RCC->CSR |= RCC_CSR_LSION; + while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) + ; /* Waits until LSI is stable. */ +#endif + +#if STM32_LSE_ENABLED + /* LSE activation, have to unlock the register.*/ + if ((RCC->CSR & RCC_CSR_LSEON) == 0) { + PWR->CR |= PWR_CR_DBP; + RCC->CSR |= RCC_CSR_LSEON; + PWR->CR &= ~PWR_CR_DBP; + } + while ((RCC->CSR & RCC_CSR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ +#endif + +#if STM32_ACTIVATE_PLL + /* PLL activation.*/ + RCC->CFGR |= STM32_PLLDIV | STM32_PLLMUL | STM32_PLLSRC; + RCC->CR |= RCC_CR_PLLON; + while (!(RCC->CR & RCC_CR_PLLRDY)) + ; /* Waits until PLL is stable. */ +#endif + + /* Other clock-related settings (dividers, MCO etc).*/ + RCC->CR |= STM32_RTCPRE; + RCC->CFGR |= STM32_MCOPRE | STM32_MCOSEL | + STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; + RCC->CSR |= STM32_RTCSEL; + + /* Flash setup and final clock selection.*/ +#if defined(STM32_FLASHBITS1) + FLASH->ACR = STM32_FLASHBITS1; +#endif +#if defined(STM32_FLASHBITS2) + FLASH->ACR = STM32_FLASHBITS2; +#endif + + /* Switching to the configured clock source if it is different from MSI.*/ +#if (STM32_SW != STM32_SW_MSI) + RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) + ; +#endif +#endif /* STM32_NO_INIT */ + + /* SYSCFG clock enabled here because it is a multi-functional unit shared + among multiple drivers.*/ + rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); +} +#else +void stm32_clock_init(void) {} +#endif + +/** @} */ diff --git a/Project/os/hal/platforms/STM32L1xx/hal_lld.h b/Project/os/hal/platforms/STM32L1xx/hal_lld.h new file mode 100644 index 0000000..c486bac --- /dev/null +++ b/Project/os/hal/platforms/STM32L1xx/hal_lld.h @@ -0,0 +1,1068 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32L1xx/hal_lld.h + * @brief STM32L1xx HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - STM32_LSECLK. + * - STM32_HSECLK. + * . + * One of the following macros must also be defined: + * - STM32L1XX_MD for Ultra Low Power Medium-density devices. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "stm32.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS TRUE + +/** + * @name Platform identification + * @{ + */ +#define PLATFORM_NAME "STM32L1 Ultra Low Power Medium Density" +/** @} */ + +/** + * @name Internal clock sources + * @{ + */ +#define STM32_HSICLK 16000000 /**< High speed internal clock. */ +#define STM32_LSICLK 38000 /**< Low speed internal clock. */ +/** @} */ + +/** + * @name PWR_CR register bits definitions + * @{ + */ +#define STM32_VOS_MASK (3 << 11) /**< Core voltage mask. */ +#define STM32_VOS_1P8 (1 << 11) /**< Core voltage 1.8 Volts. */ +#define STM32_VOS_1P5 (2 << 11) /**< Core voltage 1.5 Volts. */ +#define STM32_VOS_1P2 (3 << 11) /**< Core voltage 1.2 Volts. */ + +#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */ +#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */ +#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */ +#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */ +#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */ +#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */ +#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */ +#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */ +/** @} */ + +/** + * @name RCC_CR register bits definitions + * @{ + */ +#define STM32_RTCPRE_MASK (3 << 29) /**< RTCPRE mask. */ +#define STM32_RTCPRE_DIV2 (0 << 29) /**< HSE divided by 2. */ +#define STM32_RTCPRE_DIV4 (1 << 29) /**< HSE divided by 4. */ +#define STM32_RTCPRE_DIV8 (2 << 29) /**< HSE divided by 2. */ +#define STM32_RTCPRE_DIV16 (3 << 29) /**< HSE divided by 16. */ +/** @} */ + +/** + * @name RCC_CFGR register bits definitions + * @{ + */ +#define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */ +#define STM32_SW_HSI (1 << 0) /**< SYSCLK source is HSI. */ +#define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */ +#define STM32_SW_PLL (3 << 0) /**< SYSCLK source is PLL. */ + +#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ +#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ +#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ +#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ +#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ +#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ +#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ +#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ +#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ + +#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */ +#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */ +#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */ +#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ +#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ + +#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ +#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ +#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ +#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ +#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ + +#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ +#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */ + +#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ +#define STM32_MCOSEL_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */ +#define STM32_MCOSEL_HSI (2 << 24) /**< HSI clock on MCO pin. */ +#define STM32_MCOSEL_MSI (3 << 24) /**< MSI clock on MCO pin. */ +#define STM32_MCOSEL_HSE (4 << 24) /**< HSE clock on MCO pin. */ +#define STM32_MCOSEL_PLL (5 << 24) /**< PLL clock on MCO pin. */ +#define STM32_MCOSEL_LSI (6 << 24) /**< LSI clock on MCO pin. */ +#define STM32_MCOSEL_LSE (7 << 24) /**< LSE clock on MCO pin. */ + +#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */ +#define STM32_MCOPRE_DIV2 (1 << 28) /**< MCO divided by 1. */ +#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 1. */ +#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 1. */ +#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 1. */ +/** @} */ + +/** + * @name RCC_ICSCR register bits definitions + * @{ + */ +#define STM32_MSIRANGE_MASK (7 << 13) /**< MSIRANGE field mask. */ +#define STM32_MSIRANGE_64K (0 << 13) /**< 64kHz nominal. */ +#define STM32_MSIRANGE_128K (1 << 13) /**< 128kHz nominal. */ +#define STM32_MSIRANGE_256K (2 << 13) /**< 256kHz nominal. */ +#define STM32_MSIRANGE_512K (3 << 13) /**< 512kHz nominal. */ +#define STM32_MSIRANGE_1M (4 << 13) /**< 1MHz nominal. */ +#define STM32_MSIRANGE_2M (5 << 13) /**< 2MHz nominal. */ +#define STM32_MSIRANGE_4M (6 << 13) /**< 4MHz nominal */ +/** @} */ + +/** + * @name RCC_CSR register bits definitions + * @{ + */ +#define STM32_RTCSEL_MASK (3 << 16) /**< RTC source mask. */ +#define STM32_RTCSEL_NOCLOCK (0 << 16) /**< No RTC source. */ +#define STM32_RTCSEL_LSE (1 << 16) /**< RTC source is LSE. */ +#define STM32_RTCSEL_LSI (2 << 16) /**< RTC source is LSI. */ +#define STM32_RTCSEL_HSEDIV (3 << 16) /**< RTC source is HSE divided. */ +/** @} */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name STM32L1xx capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 0 + +/* DAC attributes.*/ +#define STM32_HAS_DAC TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 FALSE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 23 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH TRUE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C3 FALSE +#define STM32_I2C3_RX_DMA_MSK 0 +#define STM32_I2C3_RX_DMA_CHN 0x00000000 +#define STM32_I2C3_TX_DMA_MSK 0 +#define STM32_I2C3_TX_DMA_CHN 0x00000000 + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS FALSE +#define STM32_RTC_IS_CALENDAR TRUE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 FALSE +#define STM32_SPI3_RX_DMA_MSK 0 +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK 0 +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 FALSE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 TRUE +#define STM32_HAS_TIM10 TRUE +#define STM32_HAS_TIM11 TRUE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_USART3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART4 FALSE +#define STM32_UART4_RX_DMA_MSK 0 +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK 0 +#define STM32_UART4_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART5 FALSE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 + +/* USB attributes.*/ +#define STM32_HAS_USB TRUE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ + +/*===========================================================================*/ +/* Platform specific friendly IRQ names. */ +/*===========================================================================*/ + +/** + * @name IRQ VECTOR names + * @{ + */ +#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ +#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line + detect. */ +#define TAMPER_STAMP_IRQHandler Vector48 /**< Tamper and Time Stamp + through EXTI. */ +#define RTC_WKUP_IRQHandler Vector4C /**< RTC Wakeup Timer through + EXTI. */ +#define FLASH_IRQHandler Vector50 /**< Flash. */ +#define RCC_IRQHandler Vector54 /**< RCC. */ +#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ +#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ +#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ +#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ +#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ +#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ +#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ +#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ +#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ +#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ +#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ +#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ +#define ADC1_IRQHandler Vector88 /**< ADC1. */ +#define USB_HP_IRQHandler Vector8C /**< USB High Priority. */ +#define USB_LP_IRQHandler Vector90 /**< USB Low Priority. */ +#define DAC_IRQHandler Vector94 /**< DAC. */ +#define COMP_IRQHandler Vector98 /**< Comparator through EXTI. */ +#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ +#define TIM9_IRQHandler VectorA0 /**< TIM9. */ +#define TIM10_IRQHandler VectorA4 /**< TIM10. */ +#define TIM11_IRQHandler VectorA8 /**< TIM11. */ +#define LCD_IRQHandler VectorAC /**< LCD. */ +#define TIM2_IRQHandler VectorB0 /**< TIM2. */ +#define TIM3_IRQHandler VectorB4 /**< TIM3. */ +#define TIM4_IRQHandler VectorB8 /**< TIM4. */ +#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ +#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ +#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ +#define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */ +#define SPI1_IRQHandler VectorCC /**< SPI1. */ +#define SPI2_IRQHandler VectorD0 /**< SPI2. */ +#define USART1_IRQHandler VectorD4 /**< USART1. */ +#define USART2_IRQHandler VectorD8 /**< USART2. */ +#define USART3_IRQHandler VectorDC /**< USART3. */ +#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ +#define RTC_Alarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ +#define USB_FS_WKUP_IRQHandler VectorE8 /**< USB Wakeup from suspend. */ +#define TIM6_IRQHandler VectorEC /**< TIM6. */ +#define TIM7_IRQHandler VectorF0 /**< TIM7. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Disables the PWR/RCC initialization in the HAL. + */ +#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) +#define STM32_NO_INIT FALSE +#endif + +/** + * @brief Core voltage selection. + * @note This setting affects all the performance and clock related + * settings, the maximum performance is only obtainable selecting + * the maximum voltage. + */ +#if !defined(STM32_VOS) || defined(__DOXYGEN__) +#define STM32_VOS STM32_VOS_1P8 +#endif + +/** + * @brief Enables or disables the programmable voltage detector. + */ +#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__) +#define STM32_PVD_ENABLE FALSE +#endif + +/** + * @brief Sets voltage level for programmable voltage detector. + */ +#if !defined(STM32_PLS) || defined(__DOXYGEN__) +#define STM32_PLS STM32_PLS_LEV0 +#endif + +/** + * @brief Enables or disables the HSI clock source. + */ +#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the HSE clock source. + */ +#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSE_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the LSE clock source. + */ +#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSE_ENABLED FALSE +#endif + +/** + * @brief ADC clock setting. + */ +#if !defined(STM32_ADC_CLOCK_ENABLED) || defined(__DOXYGEN__) +#define STM32_ADC_CLOCK_ENABLED TRUE +#endif + +/** + * @brief USB clock setting. + */ +#if !defined(STM32_USB_CLOCK_ENABLED) || defined(__DOXYGEN__) +#define STM32_USB_CLOCK_ENABLED TRUE +#endif + +/** + * @brief MSI frequency setting. + */ +#if !defined(STM32_MSIRANGE) || defined(__DOXYGEN__) +#define STM32_MSIRANGE STM32_MSIRANGE_2M +#endif + +/** + * @brief Main clock source selection. + * @note If the selected clock source is not the PLL then the PLL is not + * initialized and started. + * @note The default value is calculated for a 32MHz system clock from + * the internal 16MHz HSI clock. + */ +#if !defined(STM32_SW) || defined(__DOXYGEN__) +#define STM32_SW STM32_SW_PLL +#endif + +/** + * @brief Clock source for the PLL. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 32MHz system clock from + * the internal 16MHz HSI clock. + */ +#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) +#define STM32_PLLSRC STM32_PLLSRC_HSI +#endif + +/** + * @brief PLL multiplier value. + * @note The allowed values are 3, 4, 6, 8, 12, 16, 32, 48. + * @note The default value is calculated for a 32MHz system clock from + * the internal 16MHz HSI clock. + */ +#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLMUL_VALUE 6 +#endif + +/** + * @brief PLL divider value. + * @note The allowed values are 2, 3, 4. + * @note The default value is calculated for a 32MHz system clock from + * the internal 16MHz HSI clock. + */ +#if !defined(STM32_PLLDIV_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLDIV_VALUE 3 +#endif + +/** + * @brief AHB prescaler value. + * @note The default value is calculated for a 32MHz system clock from + * the internal 16MHz HSI clock. + */ +#if !defined(STM32_HPRE) || defined(__DOXYGEN__) +#define STM32_HPRE STM32_HPRE_DIV1 +#endif + +/** + * @brief APB1 prescaler value. + */ +#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#endif + +/** + * @brief APB2 prescaler value. + */ +#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#endif + +/** + * @brief MCO clock source. + */ +#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__) +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#endif + +/** + * @brief MCO divider setting. + */ +#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__) +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#endif + +/** + * @brief RTC/LCD clock source. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCSEL STM32_RTCSEL_LSE +#endif + +/** + * @brief HSE divider toward RTC setting. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCPRE STM32_RTCPRE_DIV2 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Voltage related limits.*/ +#if (STM32_VOS == STM32_VOS_1P8) || defined(__DOXYGEN__) +/** + * @brief Maximum HSE clock frequency at current voltage setting. + */ +#define STM32_HSECLK_MAX 32000000 + +/** + * @brief Maximum SYSCLK clock frequency at current voltage setting. + */ +#define STM32_SYSCLK_MAX 32000000 + +/** + * @brief Maximum VCO clock frequency at current voltage setting. + */ +#define STM32_PLLVCO_MAX 96000000 + +/** + * @brief Minimum VCO clock frequency at current voltage setting. + */ +#define STM32_PLLVCO_MIN 6000000 + +/** + * @brief Maximum APB1 clock frequency. + */ +#define STM32_PCLK1_MAX 32000000 + +/** + * @brief Maximum APB2 clock frequency. + */ +#define STM32_PCLK2_MAX 32000000 + +/** + * @brief Maximum frequency not requiring a wait state for flash accesses. + */ +#define STM32_0WS_THRESHOLD 16000000 + +/** + * @brief HSI availability at current voltage settings. + */ +#define STM32_HSI_AVAILABLE TRUE + +#elif STM32_VOS == STM32_VOS_1P5 +#define STM32_HSECLK_MAX 16000000 +#define STM32_SYSCLK_MAX 16000000 +#define STM32_PLLVCO_MAX 48000000 +#define STM32_PLLVCO_MIN 6000000 +#define STM32_PCLK1_MAX 16000000 +#define STM32_PCLK2_MAX 16000000 +#define STM32_0WS_THRESHOLD 8000000 +#define STM32_HSI_AVAILABLE TRUE +#elif STM32_VOS == STM32_VOS_1P2 +#define STM32_HSECLK_MAX 4000000 +#define STM32_SYSCLK_MAX 4000000 +#define STM32_PLLVCO_MAX 24000000 +#define STM32_PLLVCO_MIN 6000000 +#define STM32_PCLK1_MAX 4000000 +#define STM32_PCLK2_MAX 4000000 +#define STM32_0WS_THRESHOLD 2000000 +#define STM32_HSI_AVAILABLE FALSE +#else +#error "invalid STM32_VOS value specified" +#endif + +/* HSI related checks.*/ +#if STM32_HSI_ENABLED +#if !STM32_HSI_AVAILABLE + #error "impossible to activate HSI under the current voltage settings" +#endif +#else /* !STM32_HSI_ENABLED */ +#if STM32_ADC_CLOCK_ENABLED || \ + (STM32_SW == STM32_SW_HSI) || \ + ((STM32_SW == STM32_SW_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) || \ + (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "required HSI clock is not enabled" +#endif +#endif /* !STM32_HSI_ENABLED */ + +/* HSE related checks.*/ +#if STM32_HSE_ENABLED +#if STM32_HSECLK == 0 +#error "impossible to activate HSE" +#endif +#if (STM32_HSECLK < 1000000) || (STM32_HSECLK > STM32_HSECLK_MAX) +#error "STM32_HSECLK outside acceptable range (1MHz...STM32_HSECLK_MAX)" +#endif +#else /* !STM32_HSE_ENABLED */ +#if (STM32_SW == STM32_SW_HSE) || \ + ((STM32_SW == STM32_SW_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \ + (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \ + (STM_RTC_SOURCE == STM32_RTCSEL_HSEDIV) +#error "required HSE clock is not enabled" +#endif +#endif /* !STM32_HSE_ENABLED */ + +/* LSI related checks.*/ +#if STM32_LSI_ENABLED +#else /* !STM32_LSI_ENABLED */ +#if STM_RTCCLK == STM32_LSICLK +#error "required LSI clock is not enabled" +#endif +#endif /* !STM32_LSI_ENABLED */ + +/* LSE related checks.*/ +#if STM32_LSE_ENABLED +#if (STM32_LSECLK == 0) +#error "impossible to activate LSE" +#endif +#if (STM32_LSECLK < 1000) || (STM32_LSECLK > 1000000) +#error "STM32_LSECLK outside acceptable range (1...1000kHz)" +#endif +#else /* !STM32_LSE_ENABLED */ +#if STM_RTCCLK == STM32_LSECLK +#error "required LSE clock is not enabled" +#endif +#endif /* !STM32_LSE_ENABLED */ + +/* PLL related checks.*/ +#if STM32_USB_CLOCK_ENABLED || \ + (STM32_SW == STM32_SW_PLL) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLL) || \ + defined(__DOXYGEN__) +/** + * @brief PLL activation flag. + */ +#define STM32_ACTIVATE_PLL TRUE +#else +#define STM32_ACTIVATE_PLL FALSE +#endif + +/** + * @brief PLLMUL field. + */ +#if (STM32_PLLMUL_VALUE == 3) || defined(__DOXYGEN__) +#define STM32_PLLMUL (0 << 18) +#elif STM32_PLLMUL_VALUE == 4 +#define STM32_PLLMUL (1 << 18) +#elif STM32_PLLMUL_VALUE == 6 +#define STM32_PLLMUL (2 << 18) +#elif STM32_PLLMUL_VALUE == 8 +#define STM32_PLLMUL (3 << 18) +#elif STM32_PLLMUL_VALUE == 12 +#define STM32_PLLMUL (4 << 18) +#elif STM32_PLLMUL_VALUE == 16 +#define STM32_PLLMUL (5 << 18) +#elif STM32_PLLMUL_VALUE == 24 +#define STM32_PLLMUL (6 << 18) +#elif STM32_PLLMUL_VALUE == 32 +#define STM32_PLLMUL (7 << 18) +#elif STM32_PLLMUL_VALUE == 48 +#define STM32_PLLMUL (8 << 18) +#else +#error "invalid STM32_PLLMUL_VALUE value specified" +#endif + +/** + * @brief PLLDIV field. + */ +#if (STM32_PLLDIV_VALUE == 2) || defined(__DOXYGEN__) +#define STM32_PLLDIV (1 << 22) +#elif STM32_PLLDIV_VALUE == 3 +#define STM32_PLLDIV (2 << 22) +#elif STM32_PLLDIV_VALUE == 4 +#define STM32_PLLDIV (3 << 22) +#else +#error "invalid STM32_PLLDIV_VALUE value specified" +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#define STM32_PLLCLKIN STM32_HSECLK +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLCLKIN STM32_HSICLK +#else +#error "invalid STM32_PLLSRC value specified" +#endif + +/* PLL input frequency range check.*/ +#if (STM32_PLLCLKIN < 2000000) || (STM32_PLLCLKIN > 24000000) +#error "STM32_PLLCLKIN outside acceptable range (2...24MHz)" +#endif + +/** + * @brief PLL VCO frequency. + */ +#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) + +/* PLL output frequency range check.*/ +#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX) +#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLDIV_VALUE) + +/* PLL output frequency range check.*/ +#if (STM32_PLLCLKOUT < 2000000) || (STM32_PLLCLKOUT > 32000000) +#error "STM32_PLLCLKOUT outside acceptable range (2...32MHz)" +#endif + +/** + * @brief MSI frequency. + * @note Values are taken from the STM8Lxx datasheet. + */ +#if STM32_MSIRANGE == STM32_MSIRANGE_64K +#define STM32_MSICLK 65500 +#elif STM32_MSIRANGE == STM32_MSIRANGE_128K +#define STM32_MSICLK 131000 +#elif STM32_MSIRANGE == STM32_MSIRANGE_256K +#define STM32_MSICLK 262000 +#elif STM32_MSIRANGE == STM32_MSIRANGE_512K +#define STM32_MSICLK 524000 +#elif STM32_MSIRANGE == STM32_MSIRANGE_1M +#define STM32_MSICLK 1050000 +#elif STM32_MSIRANGE == STM32_MSIRANGE_2M +#define STM32_MSICLK 2100000 +#elif STM32_MSIRANGE == STM32_MSIRANGE_4M +#define STM32_MSICLK 4200000 +#else +#error "invalid STM32_MSIRANGE value specified" +#endif + +/** + * @brief System clock source. + */ +#if STM32_NO_INIT || defined(__DOXYGEN__) +#define STM32_SYSCLK 2100000 +#elif (STM32_SW == STM32_SW_MSI) +#define STM32_SYSCLK STM32_MSICLK +#elif (STM32_SW == STM32_SW_HSI) +#define STM32_SYSCLK STM32_HSICLK +#elif (STM32_SW == STM32_SW_HSE) +#define STM32_SYSCLK STM32_HSECLK +#elif (STM32_SW == STM32_SW_PLL) +#define STM32_SYSCLK STM32_PLLCLKOUT +#else +#error "invalid STM32_SW value specified" +#endif + +/* Check on the system clock.*/ +#if STM32_SYSCLK > STM32_SYSCLK_MAX +#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief AHB frequency. + */ +#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK (STM32_SYSCLK / 1) +#elif STM32_HPRE == STM32_HPRE_DIV2 +#define STM32_HCLK (STM32_SYSCLK / 2) +#elif STM32_HPRE == STM32_HPRE_DIV4 +#define STM32_HCLK (STM32_SYSCLK / 4) +#elif STM32_HPRE == STM32_HPRE_DIV8 +#define STM32_HCLK (STM32_SYSCLK / 8) +#elif STM32_HPRE == STM32_HPRE_DIV16 +#define STM32_HCLK (STM32_SYSCLK / 16) +#elif STM32_HPRE == STM32_HPRE_DIV64 +#define STM32_HCLK (STM32_SYSCLK / 64) +#elif STM32_HPRE == STM32_HPRE_DIV128 +#define STM32_HCLK (STM32_SYSCLK / 128) +#elif STM32_HPRE == STM32_HPRE_DIV256 +#define STM32_HCLK (STM32_SYSCLK / 256) +#elif STM32_HPRE == STM32_HPRE_DIV512 +#define STM32_HCLK (STM32_SYSCLK / 512) +#else +#error "invalid STM32_HPRE value specified" +#endif + +/* AHB frequency check.*/ +#if STM32_HCLK > STM32_SYSCLK_MAX +#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief APB1 frequency. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK1 (STM32_HCLK / 1) +#elif STM32_PPRE1 == STM32_PPRE1_DIV2 +#define STM32_PCLK1 (STM32_HCLK / 2) +#elif STM32_PPRE1 == STM32_PPRE1_DIV4 +#define STM32_PCLK1 (STM32_HCLK / 4) +#elif STM32_PPRE1 == STM32_PPRE1_DIV8 +#define STM32_PCLK1 (STM32_HCLK / 8) +#elif STM32_PPRE1 == STM32_PPRE1_DIV16 +#define STM32_PCLK1 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE1 value specified" +#endif + +/* APB1 frequency check.*/ +#if STM32_PCLK1 > STM32_PCLK1_MAX +#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" +#endif + +/** + * @brief APB2 frequency. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK2 (STM32_HCLK / 1) +#elif STM32_PPRE2 == STM32_PPRE2_DIV2 +#define STM32_PCLK2 (STM32_HCLK / 2) +#elif STM32_PPRE2 == STM32_PPRE2_DIV4 +#define STM32_PCLK2 (STM32_HCLK / 4) +#elif STM32_PPRE2 == STM32_PPRE2_DIV8 +#define STM32_PCLK2 (STM32_HCLK / 8) +#elif STM32_PPRE2 == STM32_PPRE2_DIV16 +#define STM32_PCLK2 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE2 value specified" +#endif + +/* APB2 frequency check.*/ +#if STM32_PCLK2 > STM32_PCLK2_MAX +#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" +#endif + +/** + * @brief MCO divider clock. + */ +#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__) +#define STM_MCODIVCLK 0 +#elif STM32_MCOSEL == STM32_MCOSEL_HSI +#define STM_MCODIVCLK STM32_HSICLK +#elif STM32_MCOSEL == STM32_MCOSEL_MSI +#define STM_MCODIVCLK STM32_MSICLK +#elif STM32_MCOSEL == STM32_MCOSEL_HSE +#define STM_MCODIVCLK STM32_HSECLK +#elif STM32_MCOSEL == STM32_MCOSEL_PLL +#define STM_MCODIVCLK STM32_PLLCLKOUT +#elif STM32_MCOSEL == STM32_MCOSEL_LSI +#define STM_MCODIVCLK STM32_LSICLK +#elif STM32_MCOSEL == STM32_MCOSEL_LSE +#define STM_MCODIVCLK STM32_LSECLK +#else +#error "invalid STM32_MCOSEL value specified" +#endif + +/** + * @brief MCO output pin clock. + */ +#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__) +#define STM_MCOCLK STM_MCODIVCLK +#elif STM32_MCOPRE == STM32_MCOPRE_DIV2 +#define STM_MCOCLK (STM_MCODIVCLK / 2) +#elif STM32_MCOPRE == STM32_MCOPRE_DIV4 +#define STM_MCOCLK (STM_MCODIVCLK / 4) +#elif STM32_MCOPRE == STM32_MCOPRE_DIV8 +#define STM_MCOCLK (STM_MCODIVCLK / 8) +#elif STM32_MCOPRE == STM32_MCOPRE_DIV16 +#define STM_MCOCLK (STM_MCODIVCLK / 16) +#else +#error "invalid STM32_MCOPRE value specified" +#endif + +/** + * @brief HSE divider toward RTC clock. + */ +#if (STM32_RTCPRE == STM32_RTCPRE_DIV2) || defined(__DOXYGEN__) +#define STM32_HSEDIVCLK (STM32_HSECLK / 2) +#elif (STM32_RTCPRE == STM32_RTCPRE_DIV4) || defined(__DOXYGEN__) +#define STM32_HSEDIVCLK (STM32_HSECLK / 4) +#elif (STM32_RTCPRE == STM32_RTCPRE_DIV8) || defined(__DOXYGEN__) +#define STM32_HSEDIVCLK (STM32_HSECLK / 8) +#elif (STM32_RTCPRE == STM32_RTCPRE_DIV16) || defined(__DOXYGEN__) +#define STM32_HSEDIVCLK (STM32_HSECLK / 16) +#else +#error "invalid STM32_RTCPRE value specified" +#endif + +/** + * @brief RTC/LCD clock. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__) +#define STM_RTCCLK 0 +#elif STM32_RTCSEL == STM32_RTCSEL_LSE +#define STM_RTCCLK STM32_LSECLK +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM_RTCCLK STM32_LSICLK +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM_RTCCLK STM32_HSEDIVCLK +#else +#error "invalid STM32_RTCSEL value specified" +#endif + +/** + * @brief ADC frequency. + */ +#define STM32_ADCCLK STM32_HSICLK + +/** + * @brief USB frequency. + */ +#define STM32_USBCLK (STM32_PLLVCO / 2) + +/** + * @brief Timers 2, 3, 4, 6, 7 clock. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK1 (STM32_PCLK1 * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK1 * 2) +#endif + +/** + * @brief Timers 9, 10, 11 clock. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK2 (STM32_PCLK2 * 1) +#else +#define STM32_TIMCLK2 (STM32_PCLK2 * 2) +#endif + +/** + * @brief Flash settings. + */ +#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__) +#define STM32_FLASHBITS1 0x00000000 +#else +#define STM32_FLASHBITS1 0x00000004 +#define STM32_FLASHBITS2 0x00000007 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing a system clock frequency. + */ +typedef uint32_t halclock_t; + +/** + * @brief Type of the realtime free counter value. + */ +typedef uint32_t halrtcnt_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the current value of the system free running counter. + * @note This service is implemented by returning the content of the + * DWT_CYCCNT register. + * + * @return The value of the system free running counter of + * type halrtcnt_t. + * + * @notapi + */ +#define hal_lld_get_counter_value() DWT_CYCCNT + +/** + * @brief Realtime counter frequency. + * @note The DWT_CYCCNT register is incremented directly by the system + * clock so this function returns STM32_HCLK. + * + * @return The realtime counter frequency of type halclock_t. + * + * @notapi + */ +#define hal_lld_get_counter_frequency() STM32_HCLK + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* STM32 DMA and RCC helpers.*/ +#include "stm32_dma.h" +#include "stm32_rcc.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void stm32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32L1xx/platform.dox b/Project/os/hal/platforms/STM32L1xx/platform.dox new file mode 100644 index 0000000..eee6beb --- /dev/null +++ b/Project/os/hal/platforms/STM32L1xx/platform.dox @@ -0,0 +1,318 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup STM32L1xx_DRIVERS STM32L1xx Drivers + * @details This section describes all the supported drivers on the STM32L1xx + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup STM32L1xx_HAL STM32L1xx Initialization Support + * @details The STM32L1xx HAL support is responsible for system initialization. + * + * @section stm32l1xx_hal_1 Supported HW resources + * - PLL1. + * - RCC. + * - Flash. + * . + * @section stm32l1xx_hal_2 STM32L1xx HAL driver implementation features + * - PLL startup and stabilization. + * - Clock tree initialization. + * - Clock source selection. + * - Flash wait states initialization based on the selected clock options. + * - SYSTICK initialization based on current clock and kernel required rate. + * - DMA support initialization. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_ADC STM32L1xx ADC Support + * @details The STM32L1xx ADC driver supports the ADC peripherals using DMA + * channels for maximum performance. + * + * @section stm32l1xx_adc_1 Supported HW resources + * - ADC1. + * - DMA1. + * . + * @section stm32l1xx_adc_2 STM32L1xx ADC driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Streaming conversion using DMA for maximum performance. + * - Programmable ADC interrupt priority level. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - DMA and ADC errors detection. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_EXT STM32L1xx EXT Support + * @details The STM32L1xx EXT driver uses the EXTI peripheral. + * + * @section stm32l1xx_ext_1 Supported HW resources + * - EXTI. + * . + * @section stm32l1xx_ext_2 STM32L1xx EXT driver implementation features + * - Each EXTI channel can be independently enabled and programmed. + * - Programmable EXTI interrupts priority level. + * - Capability to work as event sources (WFE) rather than interrupt sources. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_GPT STM32L1xx GPT Support + * @details The STM32L1xx GPT driver uses the TIMx peripherals. + * + * @section stm32l1xx_gpt_1 Supported HW resources + * - TIM2. + * - TIM3. + * - TIM4. + * . + * @section stm32l1xx_gpt_2 STM32L1xx GPT driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_ICU STM32L1xx ICU Support + * @details The STM32L1xx ICU driver uses the TIMx peripherals. + * + * @section stm32l1xx_icu_1 Supported HW resources + * - TIM2. + * - TIM3. + * - TIM4. + * . + * @section stm32l1xx_icu_2 STM32L1xx ICU driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_PAL STM32L1xx PAL Support + * @details The STM32L1xx PAL driver uses the GPIO peripherals. + * + * @section stm32l1xx_pal_1 Supported HW resources + * - GPIOA. + * - GPIOB. + * - GPIOC. + * - GPIOD. + * - GPIOE. + * - GPIOH. + * . + * @section stm32l1xx_pal_2 STM32L1xx PAL driver implementation features + * The PAL driver implementation fully supports the following hardware + * capabilities: + * - 16 bits wide ports. + * - Atomic set/reset functions. + * - Atomic set+reset function (atomic bus operations). + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section stm32l1xx_pal_3 Supported PAL setup modes + * The STM32L1xx PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_PULLUP. + * - @p PAL_MODE_INPUT_PULLDOWN. + * - @p PAL_MODE_INPUT_ANALOG. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * - @p PAL_MODE_OUTPUT_OPENDRAIN. + * - @p PAL_MODE_ALTERNATE (non standard). + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section stm32l1xx_pal_4 Suboptimal behavior + * The STM32L1xx GPIO is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Pad/port toggling operations are not atomic. + * - Pad/group mode setup is not atomic. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_PWM STM32L1xx PWM Support + * @details The STM32L1xx PWM driver uses the TIMx peripherals. + * + * @section stm32l1xx_pwm_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * - TIM4. + * . + * @section stm32l1xx_pwm_2 STM32L1xx PWM driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Four independent PWM channels per timer. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_SERIAL STM32L1xx Serial Support + * @details The STM32L1xx Serial driver uses the USART/UART peripherals in a + * buffered, interrupt driven, implementation. + * + * @section stm32l1xx_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - USART1. + * - USART2. + * - USART3 (where present). + * - UART4 (where present). + * - UART5 (where present). + * . + * @section stm32l1xx_serial_2 STM32L1xx Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART/USART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * - Programmable priority levels for each UART/USART. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_SPI STM32L1xx SPI Support + * @details The SPI driver supports the STM32L1xx SPI peripherals using DMA + * channels for maximum performance. + * + * @section stm32l1xx_spi_1 Supported HW resources + * - SPI1. + * - SPI2. + * - SPI3 (where present). + * - DMA1. + * - DMA2 (where present). + * . + * @section stm32l1xx_spi_2 STM32L1xx SPI driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each SPI can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable interrupt priority levels for each SPI. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - Programmable DMA error hook. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_UART STM32L1xx UART Support + * @details The UART driver supports the STM32L1xx USART peripherals using DMA + * channels for maximum performance. + * + * @section stm32l1xx_uart_1 Supported HW resources + * The UART driver can support any of the following hardware resources: + * - USART1. + * - USART2. + * - USART3 (where present). + * - DMA1. + * . + * @section stm32l1xx_uart_2 STM32L1xx UART driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART/USART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable interrupt priority levels for each UART/USART. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - Programmable DMA error hook. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_USB STM32L1xx USB Support + * @details The USB driver supports the STM32L1xx USB peripheral. + * + * @section stm32l1xx_usb_1 Supported HW resources + * The USB driver can support any of the following hardware resources: + * - USB. + * . + * @section stm32l1xx_usb_2 STM32L1xx USB driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Programmable interrupt priority levels. + * - Each endpoint programmable in Control, Bulk and Interrupt modes. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_PLATFORM_DRIVERS STM32L1xx Platform Drivers + * @details Platform support drivers. Platform drivers do not implement HAL + * standard driver templates, their role is to support platform + * specific functionalities. + * + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_DMA STM32L1xx DMA Support + * @details This DMA helper driver is used by the other drivers in order to + * access the shared DMA resources in a consistent way. + * + * @section stm32l1xx_dma_1 Supported HW resources + * The DMA driver can support any of the following hardware resources: + * - DMA1. + * . + * @section stm32l1xx_dma_2 STM32L1xx DMA driver implementation features + * - Exports helper functions/macros to the other drivers that share the + * DMA resource. + * - Automatic DMA clock stop when not in use by any driver. + * - DMA streams and interrupt vectors sharing among multiple drivers. + * . + * @ingroup STM32L1xx_PLATFORM_DRIVERS + */ + +/** + * @defgroup STM32L1xx_RCC STM32L1xx RCC Support + * @details This RCC helper driver is used by the other drivers in order to + * access the shared RCC resources in a consistent way. + * + * @section stm32f1xx_rcc_1 Supported HW resources + * - RCC. + * . + * @section stm32l1xx_rcc_2 STM32L1xx RCC driver implementation features + * - Peripherals reset. + * - Peripherals clock enable. + * - Peripherals clock disable. + * . + * @ingroup STM32L1xx_PLATFORM_DRIVERS + */ diff --git a/Project/os/hal/platforms/STM32L1xx/platform.mk b/Project/os/hal/platforms/STM32L1xx/platform.mk new file mode 100644 index 0000000..2b23eac --- /dev/null +++ b/Project/os/hal/platforms/STM32L1xx/platform.mk @@ -0,0 +1,21 @@ +# List of all the STM32L1xx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/stm32_dma.c \ + ${CHIBIOS}/os/hal/platforms/STM32L1xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32L1xx/adc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/i2c_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/uart_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32L1xx \ + ${CHIBIOS}/os/hal/platforms/STM32 \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \ + ${CHIBIOS}/os/hal/platforms/STM32/DMAv1 \ + ${CHIBIOS}/os/hal/platforms/STM32/USBv1 diff --git a/Project/os/hal/platforms/STM32L1xx/stm32_dma.c b/Project/os/hal/platforms/STM32L1xx/stm32_dma.c new file mode 100644 index 0000000..9c100fc --- /dev/null +++ b/Project/os/hal/platforms/STM32L1xx/stm32_dma.c @@ -0,0 +1,355 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32L1xx/stm32_dma.c + * @brief DMA helper driver code. + * + * @addtogroup STM32L1xx_DMA + * @details DMA sharing helper driver. In the STM32 the DMA streams are a + * shared resource, this driver allows to allocate and free DMA + * streams at runtime in order to allow all the other device + * drivers to coordinate the access to the resource. + * @note The DMA ISR handlers are all declared into this module because + * sharing, the various device drivers can associate a callback to + * ISRs when allocating streams. + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/* The following macro is only defined if some driver requiring DMA services + has been enabled.*/ +#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Mask of the DMA1 streams in @p dma_streams_mask. + */ +#define STM32_DMA1_STREAMS_MASK 0x0000007F + +/** + * @brief Mask of the DMA2 streams in @p dma_streams_mask. + */ +#define STM32_DMA2_STREAMS_MASK 0x00000F80 + +/** + * @brief Post-reset value of the stream CCR register. + */ +#define STM32_DMA_CCR_RESET_VALUE 0x00000000 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief DMA streams descriptors. + * @details This table keeps the association between an unique stream + * identifier and the involved physical registers. + * @note Don't use this array directly, use the appropriate wrapper macros + * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc. + */ +const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { + {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn}, + {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn}, + {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn}, + {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn}, + {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn}, + {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn}, + {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn} +}; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief DMA ISR redirector type. + */ +typedef struct { + stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ + void *dma_param; /**< @brief DMA callback parameter. */ +} dma_isr_redir_t; + +/** + * @brief Mask of the allocated streams. + */ +static uint32_t dma_streams_mask; + +/** + * @brief DMA IRQ redirectors. + */ +static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief DMA1 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[0].dma_func) + dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 4; + if (dma_isr_redir[1].dma_func) + dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 8; + if (dma_isr_redir[2].dma_func) + dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 12; + if (dma_isr_redir[3].dma_func) + dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[4].dma_func) + dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 6 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 20; + if (dma_isr_redir[5].dma_func) + dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 7 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 24; + if (dma_isr_redir[6].dma_func) + dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA helper initialization. + * + * @init + */ +void dmaInit(void) { + int i; + + dma_streams_mask = 0; + for (i = 0; i < STM32_DMA_STREAMS; i++) { + _stm32_dma_streams[i].channel->CCR = 0; + dma_isr_redir[i].dma_func = NULL; + } + DMA1->IFCR = 0xFFFFFFFF; +} + +/** + * @brief Allocates a DMA stream. + * @details The stream is allocated and, if required, the DMA clock enabled. + * The function also enables the IRQ vector associated to the stream + * and initializes its priority. + * @pre The stream must not be already in use or an error is returned. + * @post The stream is allocated and the default ISR handler redirected + * to the specified function. + * @post The stream ISR vector is enabled and its priority configured. + * @post The stream must be freed using @p dmaStreamRelease() before it can + * be reused with another peripheral. + * @post The stream is in its post-reset state. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] priority IRQ priority mask for the DMA stream + * @param[in] func handling function pointer, can be @p NULL + * @param[in] param a parameter to be passed to the handling function + * @return The operation status. + * @retval FALSE no error, stream taken. + * @retval TRUE error, stream already taken. + * + * @special + */ +bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param) { + + chDbgCheck(dmastp != NULL, "dmaAllocate"); + + /* Checks if the stream is already taken.*/ + if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) + return TRUE; + + /* Marks the stream as allocated.*/ + dma_isr_redir[dmastp->selfindex].dma_func = func; + dma_isr_redir[dmastp->selfindex].dma_param = param; + dma_streams_mask |= (1 << dmastp->selfindex); + + /* Enabling DMA clocks required by the current streams set.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) + rccEnableDMA1(FALSE); + + /* Putting the stream in a safe state.*/ + dmaStreamDisable(dmastp); + dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE; + + /* Enables the associated IRQ vector if a callback is defined.*/ + if (func != NULL) + nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); + + return FALSE; +} + +/** + * @brief Releases a DMA stream. + * @details The stream is freed and, if required, the DMA clock disabled. + * Trying to release a unallocated stream is an illegal operation + * and is trapped if assertions are enabled. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post The stream is again available. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { + + chDbgCheck(dmastp != NULL, "dmaRelease"); + + /* Check if the streams is not taken.*/ + chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, + "dmaRelease(), #1", "not allocated"); + + /* Disables the associated IRQ vector.*/ + nvicDisableVector(dmastp->vector); + + /* Marks the stream as not allocated.*/ + dma_streams_mask &= ~(1 << dmastp->selfindex); + + /* Shutting down clocks that are no more required, if any.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) + rccDisableDMA1(FALSE); +} + +#endif /* STM32_DMA_REQUIRED */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32L1xx/stm32_dma.h b/Project/os/hal/platforms/STM32L1xx/stm32_dma.h new file mode 100644 index 0000000..a850ebd --- /dev/null +++ b/Project/os/hal/platforms/STM32L1xx/stm32_dma.h @@ -0,0 +1,394 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32L1xx/stm32_dma.h + * @brief DMA helper driver header. + * @note This file requires definitions from the ST header file stm32l1xx.h. + * @note This driver uses the new naming convention used for the STM32F2xx + * so the "DMA channels" are referred as "DMA streams". + * + * @addtogroup STM32L1xx_DMA + * @{ + */ + +#ifndef _STM32_DMA_H_ +#define _STM32_DMA_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Total number of DMA streams. + * @note This is the total number of streams among all the DMA units. + */ +#define STM32_DMA_STREAMS 7 + +/** + * @brief Mask of the ISR bits passed to the DMA callback functions. + */ +#define STM32_DMA_ISR_MASK 0x0F + +/** + * @brief Returns the channel associated to the specified stream. + * + * @param[in] n the stream number (0...STM32_DMA_STREAMS-1) + * @param[in] c a stream/channel association word, one channel per + * nibble, not associated channels must be set to 0xF + * @return Always zero, in this platform there is no dynamic + * association between streams and channels. + */ +#define STM32_DMA_GETCHANNEL(n, c) 0 + +/** + * @name DMA streams identifiers + * @{ + */ +/** + * @brief Returns an unique numeric identifier for a DMA stream. + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return An unique numeric stream identifier. + */ +#define STM32_DMA_STREAM_ID(dma, stream) ((stream) - 1) + +/** + * @brief Returns a DMA stream identifier mask. + * + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return A DMA stream identifier mask. + */ +#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ + (1 << STM32_DMA_STREAM_ID(dma, stream)) + +/** + * @brief Checks if a DMA stream unique identifier belongs to a mask. + * @param[in] id the stream numeric identifier + * @param[in] mask the stream numeric identifiers mask + * + * @retval The check result. + * @retval FALSE id does not belong to the mask. + * @retval TRUE id belongs to the mask. + */ +#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask))) + +/** + * @brief Returns a pointer to a stm32_dma_stream_t structure. + * + * @param[in] id the stream numeric identifier + * @return A pointer to the stm32_dma_stream_t constant structure + * associated to the DMA stream. + */ +#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) + +#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0) +#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1) +#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2) +#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3) +#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4) +#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5) +#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6) +/** @} */ + +/** + * @name CR register constants common to all DMA types + * @{ + */ +#define STM32_DMA_CR_EN DMA_CCR1_EN +#define STM32_DMA_CR_TEIE DMA_CCR1_TEIE +#define STM32_DMA_CR_HTIE DMA_CCR1_HTIE +#define STM32_DMA_CR_TCIE DMA_CCR1_TCIE +#define STM32_DMA_CR_DIR_MASK (DMA_CCR1_DIR | DMA_CCR1_MEM2MEM) +#define STM32_DMA_CR_DIR_P2M 0 +#define STM32_DMA_CR_DIR_M2P DMA_CCR1_DIR +#define STM32_DMA_CR_DIR_M2M DMA_CCR1_MEM2MEM +#define STM32_DMA_CR_CIRC DMA_CCR1_CIRC +#define STM32_DMA_CR_PINC DMA_CCR1_PINC +#define STM32_DMA_CR_MINC DMA_CCR1_MINC +#define STM32_DMA_CR_PSIZE_MASK DMA_CCR1_PSIZE +#define STM32_DMA_CR_PSIZE_BYTE 0 +#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR1_PSIZE_0 +#define STM32_DMA_CR_PSIZE_WORD DMA_CCR1_PSIZE_1 +#define STM32_DMA_CR_MSIZE_MASK DMA_CCR1_MSIZE +#define STM32_DMA_CR_MSIZE_BYTE 0 +#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR1_MSIZE_0 +#define STM32_DMA_CR_MSIZE_WORD DMA_CCR1_MSIZE_1 +#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_MSIZE_MASK | \ + STM32_DMA_CR_MSIZE_MASK) +#define STM32_DMA_CR_PL_MASK DMA_CCR1_PL +#define STM32_DMA_CR_PL(n) ((n) << 12) +/** @} */ + +/** + * @name CR register constants only found in enhanced DMA + * @{ + */ +#define STM32_DMA_CR_DMEIE 0 /**< @brief Ignored by normal DMA. */ +#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */ +#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */ +/** @} */ + +/** + * @name Status flags passed to the ISR callbacks + * @{ + */ +#define STM32_DMA_ISR_FEIF 0 +#define STM32_DMA_ISR_DMEIF 0 +#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1 +#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1 +#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA stream descriptor structure. + */ +typedef struct { + DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ + volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ + uint8_t ishift; /**< @brief Bits offset in xIFCR + register. */ + uint8_t selfindex; /**< @brief Index to self in array. */ + uint8_t vector; /**< @brief Associated IRQ vector. */ +} stm32_dma_stream_t; + +/** + * @brief STM32 DMA ISR function type. + * + * @param[in] p parameter for the registered function + * @param[in] flags pre-shifted content of the ISR register, the bits + * are aligned to bit zero + */ +typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Associates a peripheral data register to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the CPAR register + * + * @special + */ +#define dmaStreamSetPeripheral(dmastp, addr) { \ + (dmastp)->channel->CPAR = (uint32_t)(addr); \ +} + +/** + * @brief Associates a memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the CMAR register + * + * @special + */ +#define dmaStreamSetMemory0(dmastp, addr) { \ + (dmastp)->channel->CMAR = (uint32_t)(addr); \ +} + +/** + * @brief Sets the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] size value to be written in the CNDTR register + * + * @special + */ +#define dmaStreamSetTransactionSize(dmastp, size) { \ + (dmastp)->channel->CNDTR = (uint32_t)(size); \ +} + +/** + * @brief Returns the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @return The number of transfers to be performed. + * + * @special + */ +#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR)) + +/** + * @brief Programs the stream mode settings. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register + * + * @special + */ +#define dmaStreamSetMode(dmastp, mode) { \ + (dmastp)->channel->CCR = (uint32_t)(mode); \ +} + +/** + * @brief DMA stream enable. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamEnable(dmastp) { \ + (dmastp)->channel->CCR |= STM32_DMA_CR_EN; \ +} + +/** + * @brief DMA stream disable. + * @details The function disables the specified stream and then clears any + * pending interrupt. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamDisable(dmastp) { \ + (dmastp)->channel->CCR &= ~STM32_DMA_CR_EN; \ + dmaStreamClearInterrupt(dmastp); \ +} + +/** + * @brief DMA stream interrupt sources clear. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamClearInterrupt(dmastp) { \ + *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ +} + +/** + * @brief Starts a memory to memory operation using the specified stream. + * @note The default transfer data mode is "byte to byte" but it can be + * changed by specifying extra options in the @p mode parameter. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register, this value + * is implicitly ORed with: + * - @p STM32_DMA_CR_MINC + * - @p STM32_DMA_CR_PINC + * - @p STM32_DMA_CR_DIR_M2M + * - @p STM32_DMA_CR_EN + * . + * @param[in] src source address + * @param[in] dst destination address + * @param[in] n number of data units to copy + */ +#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ + dmaStreamSetPeripheral(dmastp, src); \ + dmaStreamSetMemory0(dmastp, dst); \ + dmaStreamSetTransactionSize(dmastp, n); \ + dmaStreamSetMode(dmastp, (mode) | \ + STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ + STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ +} + +/** + * @brief Polled wait for DMA transfer end. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + */ +#define dmaWaitCompletion(dmastp) { \ + while ((dmastp)->channel->CNDTR > 0) \ + ; \ + dmaStreamDisable(dmastp); \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void dmaInit(void); + bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param); + void dmaStreamRelease(const stm32_dma_stream_t *dmastp); +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_DMA_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32L1xx/stm32_rcc.h b/Project/os/hal/platforms/STM32L1xx/stm32_rcc.h new file mode 100644 index 0000000..901eb17 --- /dev/null +++ b/Project/os/hal/platforms/STM32L1xx/stm32_rcc.h @@ -0,0 +1,591 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM32L1xx/stm32_rcc.h + * @brief RCC helper driver header. + * @note This file requires definitions from the ST header file + * @p stm32l1xx.h. + * + * @addtogroup STM32L1xx_RCC + * @{ + */ + +#ifndef _STM32_RCC_ +#define _STM32_RCC_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic RCC operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB1(mask, lp) { \ + RCC->APB1ENR |= (mask); \ + if (lp) \ + RCC->APB1LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB1(mask, lp) { \ + RCC->APB1ENR &= ~(mask); \ + if (lp) \ + RCC->APB1LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * + * @api + */ +#define rccResetAPB1(mask) { \ + RCC->APB1RSTR |= (mask); \ + RCC->APB1RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB2(mask, lp) { \ + RCC->APB2ENR |= (mask); \ + if (lp) \ + RCC->APB2LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB2(mask, lp) { \ + RCC->APB2ENR &= ~(mask); \ + if (lp) \ + RCC->APB2LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * + * @api + */ +#define rccResetAPB2(mask) { \ + RCC->APB2RSTR |= (mask); \ + RCC->APB2RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB(mask, lp) { \ + RCC->AHBENR |= (mask); \ + if (lp) \ + RCC->AHBLPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB(mask, lp) { \ + RCC->AHBENR &= ~(mask); \ + if (lp) \ + RCC->AHBLPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define rccResetAHB(mask) { \ + RCC->AHBRSTR |= (mask); \ + RCC->AHBRSTR = 0; \ +} +/** @} */ + +/** + * @name ADC peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the ADC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Disables the ADC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Resets the ADC1 peripheral. + * + * @api + */ +#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) +/** @} */ + +/** + * @name DMA peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Disables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Resets the DMA1 peripheral. + * + * @api + */ +#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST) +/** @} */ + +/** + * @name PWR interface specific RCC operations + * @{ + */ +/** + * @brief Enables the PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Disables PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Resets the PWR interface. + * + * @api + */ +#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST) +/** @} */ + +/** + * @name I2C peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Disables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Resets the I2C1 peripheral. + * + * @api + */ +#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) + +/** + * @brief Enables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Disables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Resets the I2C2 peripheral. + * + * @api + */ +#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) +/** @} */ + +/** + * @name SPI peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Disables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Resets the SPI1 peripheral. + * + * @api + */ +#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) + +/** + * @brief Enables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Disables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Resets the SPI2 peripheral. + * + * @api + */ +#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) +/** @} */ + +/** + * @name TIM peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Disables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Resets the TIM2 peripheral. + * + * @api + */ +#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) + +/** + * @brief Enables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Disables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Resets the TIM3 peripheral. + * + * @api + */ +#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) + +/** + * @brief Enables the TIM4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Disables the TIM4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Resets the TIM4 peripheral. + * + * @api + */ +#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST) +/** @} */ + +/** + * @name USART/UART peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Disables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) + +/** + * @brief Enables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Disables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Resets the USART2 peripheral. + * + * @api + */ +#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) + +/** + * @brief Enables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Disables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Resets the USART3 peripheral. + * + * @api + */ +#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST) +/** @} */ + +/** + * @name USB peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the USB peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp) + +/** + * @brief Disables the USB peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp) + +/** + * @brief Resets the USB peripheral. + * + * @api + */ +#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_RCC_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM32L1xx/stm32l1xx.h b/Project/os/hal/platforms/STM32L1xx/stm32l1xx.h new file mode 100644 index 0000000..9c665d2 --- /dev/null +++ b/Project/os/hal/platforms/STM32L1xx/stm32l1xx.h @@ -0,0 +1,5141 @@ +/** + ****************************************************************************** + * @file stm32l1xx.h + * @author MCD Application Team + * @version V1.0.0 + * @date 31-December-2010 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32L1xx devices. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l1xx + * @{ + */ + +#ifndef __STM32L1XX_H +#define __STM32L1XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32L device used in your + application + */ + +#if !defined (STM32L1XX_MD) + #define STM32L1XX_MD /*!< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices */ +#endif +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + + - Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx + microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. + + */ + +#if !defined (STM32L1XX_MD) + #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)" +#endif + +#if !defined USE_STDPERIPH_DRIVER +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + Timeout value + */ +#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */ + +#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#define LSI_VALUE ((uint32_t)37000) /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ + +/** + * @brief STM32L1xx Standard Peripheral Library version number + */ +#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32L1XX_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief STM32L1xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __MPU_PRESENT 1 /*!< STM32L provides MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/*!< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32L specific Interrupt Numbers ***********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< Tamper and Time Stamp through EXTI Line Interrupts */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ + USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ + DAC_IRQn = 21, /*!< DAC Interrupt */ + COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + LCD_IRQn = 24, /*!< LCD Interrupt */ + TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ + TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ + TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ + TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 44 /*!< TIM7 global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +/* CHIBIOS FIX */ +/*#include "system_stm32l1xx.h"*/ +#include + +/** @addtogroup Exported_types + * @{ + */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) +/* ARM Compiler + ------------ + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source + module. Using the 'Options for File' dialog you can simply change the + 'Code / Const' area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the + 'Options for Target' dialog. +*/ + #define __RAM_FUNC FLASH_Status + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ + #define __RAM_FUNC __ramfunc FLASH_Status + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".data")))". +*/ + #define __RAM_FUNC FLASH_Status __attribute__((section(".data"))) + +#elif defined ( __TASKING__ ) +/* TASKING Compiler + ---------------- + RAM functions are defined using a specific toolchain pragma. This pragma is + defined in the stm32l1xx_flash_ramfunc.c +*/ + #define __RAM_FUNC FLASH_Status + +#endif + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMPR1; + __IO uint32_t SMPR2; + __IO uint32_t SMPR3; + __IO uint32_t JOFR1; + __IO uint32_t JOFR2; + __IO uint32_t JOFR3; + __IO uint32_t JOFR4; + __IO uint32_t HTR; + __IO uint32_t LTR; + __IO uint32_t SQR1; + __IO uint32_t SQR2; + __IO uint32_t SQR3; + __IO uint32_t SQR4; + __IO uint32_t SQR5; + __IO uint32_t JSQR; + __IO uint32_t JDR1; + __IO uint32_t JDR2; + __IO uint32_t JDR3; + __IO uint32_t JDR4; + __IO uint32_t DR; +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; + __IO uint32_t CCR; +} ADC_Common_TypeDef; + + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; + __IO uint8_t IDR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CR; +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SWTRIGR; + __IO uint32_t DHR12R1; + __IO uint32_t DHR12L1; + __IO uint32_t DHR8R1; + __IO uint32_t DHR12R2; + __IO uint32_t DHR12L2; + __IO uint32_t DHR8R2; + __IO uint32_t DHR12RD; + __IO uint32_t DHR12LD; + __IO uint32_t DHR8RD; + __IO uint32_t DOR1; + __IO uint32_t DOR2; + __IO uint32_t SR; +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; + __IO uint32_t CR; + __IO uint32_t APB1FZ; + __IO uint32_t APB2FZ; +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t CNDTR; + __IO uint32_t CPAR; + __IO uint32_t CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t IFCR; +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; + __IO uint32_t PECR; + __IO uint32_t PDKEYR; + __IO uint32_t PEKEYR; + __IO uint32_t PRGKEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t OBR; + __IO uint32_t WRPR; +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint32_t RDP; + __IO uint32_t USER; + __IO uint32_t WRP01; + __IO uint32_t WRP23; +} OB_TypeDef; + +/** + * @brief General Purpose IO + */ +/* CHIBIOS FIX */ +#if 0 +typedef struct +{ + __IO uint32_t MODER; + __IO uint16_t OTYPER; + uint16_t RESERVED0; + __IO uint32_t OSPEEDR; + __IO uint32_t PUPDR; + __IO uint16_t IDR; + uint16_t RESERVED1; + __IO uint16_t ODR; + uint16_t RESERVED2; + __IO uint16_t BSRRL; /* BSRR register is split to 2 * 16-bit fields BSRRL */ + __IO uint16_t BSRRH; /* BSRR register is split to 2 * 16-bit fields BSRRH */ + __IO uint32_t LCKR; + __IO uint32_t AFR[2]; +} GPIO_TypeDef; +#endif + +/** + * @brief SysTem Configuration + */ + +typedef struct +{ + __IO uint32_t MEMRMP; + __IO uint32_t PMC; + __IO uint32_t EXTICR[4]; +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t OAR1; + uint16_t RESERVED2; + __IO uint16_t OAR2; + uint16_t RESERVED3; + __IO uint16_t DR; + uint16_t RESERVED4; + __IO uint16_t SR1; + uint16_t RESERVED5; + __IO uint16_t SR2; + uint16_t RESERVED6; + __IO uint16_t CCR; + uint16_t RESERVED7; + __IO uint16_t TRISE; + uint16_t RESERVED8; +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; + __IO uint32_t PR; + __IO uint32_t RLR; + __IO uint32_t SR; +} IWDG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t FCR; + __IO uint32_t SR; + __IO uint32_t CLR; + uint32_t RESERVED; + __IO uint32_t RAM[16]; +} LCD_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t ICSCR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t AHBRSTR; + __IO uint32_t APB2RSTR; + __IO uint32_t APB1RSTR; + __IO uint32_t AHBENR; + __IO uint32_t APB2ENR; + __IO uint32_t APB1ENR; + __IO uint32_t AHBLPENR; + __IO uint32_t APB2LPENR; + __IO uint32_t APB1LPENR; + __IO uint32_t CSR; +} RCC_TypeDef; + +/** + * @brief Routing Interface + */ + +typedef struct +{ + __IO uint32_t ICR; + __IO uint32_t ASCR1; + __IO uint32_t ASCR2; + __IO uint32_t HYSCR1; + __IO uint32_t HYSCR2; + __IO uint32_t HYSCR3; +} RI_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; + __IO uint32_t DR; + __IO uint32_t CR; + __IO uint32_t ISR; + __IO uint32_t PRER; + __IO uint32_t WUTR; + __IO uint32_t CALIBR; + __IO uint32_t ALRMAR; + __IO uint32_t ALRMBR; + __IO uint32_t WPR; + uint32_t RESERVED1; + uint32_t RESERVED2; + __IO uint32_t TSTR; + __IO uint32_t TSDR; + uint32_t RESERVED3; + uint32_t RESERVED4; + __IO uint32_t TAFCR; + uint32_t RESERVED5; + uint32_t RESERVED6; + uint32_t RESERVED7; + __IO uint32_t BKP0R; + __IO uint32_t BKP1R; + __IO uint32_t BKP2R; + __IO uint32_t BKP3R; + __IO uint32_t BKP4R; + __IO uint32_t BKP5R; + __IO uint32_t BKP6R; + __IO uint32_t BKP7R; + __IO uint32_t BKP8R; + __IO uint32_t BKP9R; + __IO uint32_t BKP10R; + __IO uint32_t BKP11R; + __IO uint32_t BKP12R; + __IO uint32_t BKP13R; + __IO uint32_t BKP14R; + __IO uint32_t BKP15R; + __IO uint32_t BKP16R; + __IO uint32_t BKP17R; + __IO uint32_t BKP18R; + __IO uint32_t BKP19R; +} RTC_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SR; + uint16_t RESERVED2; + __IO uint16_t DR; + uint16_t RESERVED3; + __IO uint16_t CRCPR; + uint16_t RESERVED4; + __IO uint16_t RXCRCR; + uint16_t RESERVED5; + __IO uint16_t TXCRCR; + uint16_t RESERVED6; +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SMCR; + uint16_t RESERVED2; + __IO uint16_t DIER; + uint16_t RESERVED3; + __IO uint16_t SR; + uint16_t RESERVED4; + __IO uint16_t EGR; + uint16_t RESERVED5; + __IO uint16_t CCMR1; + uint16_t RESERVED6; + __IO uint16_t CCMR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ARR; + uint16_t RESERVED11; + uint32_t RESERVED12; + __IO uint16_t CCR1; + uint16_t RESERVED13; + __IO uint16_t CCR2; + uint16_t RESERVED14; + __IO uint16_t CCR3; + uint16_t RESERVED15; + __IO uint16_t CCR4; + uint16_t RESERVED16; + uint32_t RESERVED17; + __IO uint16_t DCR; + uint16_t RESERVED18; + __IO uint16_t DMAR; + uint16_t RESERVED19; + __IO uint16_t OR; + uint16_t RESERVED20; +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; + uint16_t RESERVED0; + __IO uint16_t DR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CR1; + uint16_t RESERVED3; + __IO uint16_t CR2; + uint16_t RESERVED4; + __IO uint16_t CR3; + uint16_t RESERVED5; + __IO uint16_t GTPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFR; + __IO uint32_t SR; +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define LCD_BASE (APB1PERIPH_BASE + 0x2400) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define COMP_BASE (APB1PERIPH_BASE + 0x7C00) +#define RI_BASE (APB1PERIPH_BASE + 0x7C04) + +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define TIM9_BASE (APB2PERIPH_BASE + 0x0800) +#define TIM10_BASE (APB2PERIPH_BASE + 0x0C00) +#define TIM11_BASE (APB2PERIPH_BASE + 0x1000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC_BASE (APB2PERIPH_BASE + 0x2700) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) + +#define GPIOA_BASE (AHBPERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHBPERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHBPERIPH_BASE + 0x1000) +#define GPIOH_BASE (AHBPERIPH_BASE + 0x1400) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) +#define RCC_BASE (AHBPERIPH_BASE + 0x3800) + + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */ +#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */ + +#define DMA1_BASE (AHBPERIPH_BASE + 0x6000) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080) + + +#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define LCD ((LCD_TypeDef *) LCD_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define COMP ((COMP_TypeDef *) COMP_BASE) +#define RI ((RI_TypeDef *) RI_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) + +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */ +#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */ +#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */ +#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */ +#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */ +#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */ +#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */ +#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */ +#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */ + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ +#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ +#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ +#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ +#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ + +#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ + +#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */ +#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */ + +#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ + +#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */ +#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */ + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ +#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ + +#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */ +#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + +#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ +#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */ +#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */ +#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ + +#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */ +#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */ +#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */ + +#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */ +#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ +#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */ + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */ +#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */ +#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */ +#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */ +#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */ +#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */ +#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */ +#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */ +#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SMPR3 register *******************/ +#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */ + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */ +#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */ +#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */ +#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ +#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */ +#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */ +#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */ +#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */ +#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */ +#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */ +#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */ +#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */ +#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR4 register *******************/ +#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR5 register *******************/ +#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ +#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ + + +/******************* Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */ +#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */ +#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */ +#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */ +#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */ +#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */ +#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */ + +/******************* Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/ +#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for COMP_CSR register ********************/ +#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */ +#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */ +#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */ +#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */ + +#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */ +#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */ + +#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */ +#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */ + +#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */ +#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */ + +#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */ +#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */ +#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter (DAC) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!. + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM8L/hal_lld.c + * @brief STM8L HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * @details Clock sources initialization, HSI is assumed to be already + * started after reset. + * @note If the @p STM8L_CLOCK_INIT option is set to @p FALSE then the + * initialization is not performed and is left to the application. + * + * @notapi + */ +void hal_lld_init(void) { + +#if !STM8L_NO_CLOCK_INIT + /* Makes sure that HSI is stable before proceeding.*/ + CLK->ICKCR |= CLK_ICKCR_HSION; + while ((CLK->ICKCR & CLK_ICKCR_HSIRDY) == 0) + ; + + /* LSI startup and stabilization if required.*/ +#if STM8L_LSI_ENABLED + CLK->ICKCR |= CLK_ICKCR_LSION; + while ((CLK->ICKCR & CLK_ICKCR_LSIRDY) == 0) + ; +#endif + + /* HSE startup and stabilization if required.*/ +#if STM8L_HSE_ENABLED +#if HSEBYPASS + CLK->ECKCR |= CLK_ECKCR_HSEON | CLK_ECKCR_HSEBYP; +#else + CLK->ECKCR |= CLK_ECKCR_HSEON; +#endif + while ((CLK->ECKCR & CLK_ECKCR_HSERDY) == 0) + ; +#endif + + /* LSE startup and stabilization if required.*/ +#if STM8L_LSE_ENABLED +#if LSEBYPASS + CLK->ECKCR |= CLK_ECKCR_LSEON | CLK_ECKCR_LSEBYP; +#else + CLK->ECKCR |= CLK_ECKCR_LSEON; +#endif + while ((CLK->ECKCR & CLK_ECKCR_LSERDY) == 0) + ; +#endif + + /* Setting up clock dividers.*/ + CLK->CKDIVR = STM8L_SYSCLK_DIVIDER << 0; + + /* SYSCLK switch to the selected source, not necessary if it is HSI.*/ +#if STM8L_SYSCLK_SOURCE != CLK_SYSSEL_HSI + /* Switching clock (manual switch mode).*/ + CLK->SWR = STM8L_SYSCLK_SOURCE; + while ((CLK->SWCR & CLK_SWCR_SWIF) == 0) + ; + CLK->SWCR = CLK_SWCR_SWEN; +#endif + + /* Clocks initially all disabled, note the boot ROM clock is disabled + because the boot loader is no more required and it draws precious uAs.*/ + CLK->PCKENR1 = 0; + CLK->PCKENR2 = 0; + CLK->PCKENR3 = 0; + + /* Other clock related initializations.*/ + CLK->CSSR = 0; + CLK->CCOR = 0; + + /* HSI disabled if it is no more required.*/ +#if !STM8L_HSI_ENABLED + CLK->ICKCR &= ~CLK_ICKCR_HSION; +#endif +#endif /* !STM8L_NO_CLOCK_INIT */ +} + +/** @} */ diff --git a/Project/os/hal/platforms/STM8L/hal_lld.h b/Project/os/hal/platforms/STM8L/hal_lld.h new file mode 100644 index 0000000..10384ed --- /dev/null +++ b/Project/os/hal/platforms/STM8L/hal_lld.h @@ -0,0 +1,293 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM8L/hal_lld.h + * @brief STM8L HAL subsystem low level driver source. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - HSECLK (@p 0 if disabled or frequency in Hertz). + * - HSEBYPASS (@p TRUE if external oscillator rather than a crystal). + * - LSECLK (@p 0 if disabled or frequency in Hertz). + * - LSEBYPASS (@p TRUE if external oscillator rather than a crystal). + * . + * One of the following macros must also be defined: + * - STM8L15X_MD for Medium Density devices. + * - STM8L15X_MDP for Medium Density Plus devices. + * - STM8L15X_HD for High Density devices. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#undef FALSE +#undef TRUE +#include "stm8l15x.h" +#define FALSE 0 +#define TRUE (!FALSE) + +#if defined (STM8L15X_MD) +#include "hal_lld_stm8l_md.h" +#elif defined (STM8L15X_MDP) +#include "hal_lld_stm8l_mdp.h" +#elif defined (STM8L15X_HD) +#include "hal_lld_stm8l_hd.h" +#else +#error "unspecified, unsupported or invalid STM8L platform" +#endif + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "STM8L" + +#define LSICLK 38000 /**< Low speed internal clock. */ +#define HSICLK 16000000 /**< High speed internal clock. */ + +#define CLK_SYSSEL_HSI 1 /**< HSI system clock selector. */ +#define CLK_SYSSEL_LSI 2 /**< LSI system clock selector. */ +#define CLK_SYSSEL_HSE 4 /**< HSE system clock selector. */ +#define CLK_SYSSEL_LSE 8 /**< LSE system clock selector. */ + +#define CLK_SYSCLK_DIV1 0 /**< Source clock divided by 1. */ +#define CLK_SYSCLK_DIV2 1 /**< Source clock divided by 2. */ +#define CLK_SYSCLK_DIV4 2 /**< Source clock divided by 4. */ +#define CLK_SYSCLK_DIV8 3 /**< Source clock divided by 8. */ +#define CLK_SYSCLK_DIV16 4 /**< Source clock divided by 16. */ +#define CLK_SYSCLK_DIV32 5 /**< Source clock divided by 32. */ +#define CLK_SYSCLK_DIV64 6 /**< Source clock divided by 64. */ +#define CLK_SYSCLK_DIV128 7 /**< Source clock divided by 128. */ + +#define CLK_RTCSEL_HSI 1 /**< HSI RTC clock selector. */ +#define CLK_RTCSEL_LSI 2 /**< LSI RTC clock selector. */ +#define CLK_RTCSEL_HSE 4 /**< HSE RTC clock selector. */ +#define CLK_RTCSEL_LSE 8 /**< LSE RTC clock selector. */ + +#define CLK_RTCCLK_DIV1 0 /**< Source clock divided by 1. */ +#define CLK_RTCCLK_DIV2 1 /**< Source clock divided by 2. */ +#define CLK_RTCCLK_DIV4 2 /**< Source clock divided by 4. */ +#define CLK_RTCCLK_DIV8 3 /**< Source clock divided by 8. */ +#define CLK_RTCCLK_DIV16 4 /**< Source clock divided by 16. */ +#define CLK_RTCCLK_DIV32 5 /**< Source clock divided by 32. */ +#define CLK_RTCCLK_DIV64 6 /**< Source clock divided by 64. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Disables the clock initialization in the HAL. + */ +#if !defined(STM8L_NO_CLOCK_INIT) || defined(__DOXYGEN__) +#define STM8L_NO_CLOCK_INIT FALSE +#endif + +/** + * @brief Enables or disables the HSI clock source. + */ +#if !defined(STM8L_HSI_ENABLED) || defined(__DOXYGEN__) +#define STM8L_HSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM8L_LSI_ENABLED) || defined(__DOXYGEN__) +#define STM8L_LSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the HSE clock source. + */ +#if !defined(STM8L_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM8L_HSE_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the LSE clock source. + */ +#if !defined(STM8L_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM8L_LSE_ENABLED FALSE +#endif + +/** + * @brief System clock source selection. + */ +#if !defined(STM8L_SYSCLK_SOURCE) || defined(__DOXYGEN__) +#define STM8L_SYSCLK_SOURCE CLK_SYSSEL_HSI +#endif + +/** + * @brief System clock divider. + */ +#if !defined(STM8L_SYSCLK_DIVIDER) || defined(__DOXYGEN__) +#define STM8L_SYSCLK_DIVIDER CLK_SYSCLK_DIV1 +#endif + +/** + * @brief RTC clock source selection. + */ +#if !defined(STM8L_RTCCLK_SOURCE) || defined(__DOXYGEN__) +#define STM8L_RTCCLK_SOURCE CLK_RTCSEL_HSI +#endif + +/** + * @brief RTC clock divider. + */ +#if !defined(STM8L_RTCCLK_DIVIDER) || defined(__DOXYGEN__) +#define STM8L_RTCCLK_DIVIDER CLK_RTCCLK_DIV1 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV1) && \ + (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV2) && \ + (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV4) && \ + (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV8) && \ + (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV16) && \ + (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV32) && \ + (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV64) && \ + (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV128) +#error "specified invalid SYSCLK divider" +#endif + +#if (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV1) && \ + (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV2) && \ + (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV4) && \ + (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV8) && \ + (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV16) && \ + (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV32) && \ + (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV64) +#error "specified invalid RTCCLK divider" +#endif + +#if STM8L_HSE_ENABLED && (HSECLK == 0) +#error "impossible to activate HSE" +#endif + +#if STM8L_LSE_ENABLED && (LSECLK == 0) +#error "impossible to activate LSE" +#endif + +#if !STM8L_HSI_ENABLED && ((STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSI) || \ + (STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSI)) +#error "requested HSI clock is not enabled" +#endif + +#if !STM8L_LSI_ENABLED && ((STM8L_SYSCLK_SOURCE == CLK_SYSSEL_LSI) || \ + (STM8L_RTCCLK_SOURCE == CLK_RTCSEL_LSI)) +#error "requested LSI clock is not enabled" +#endif + +#if !STM8L_HSE_ENABLED && ((STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSE) || \ + (STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSE)) +#error "requested HSE clock is not enabled" +#endif + +#if !STM8L_LSE_ENABLED && ((STM8L_SYSCLK_SOURCE == CLK_SYSSEL_LSE) || \ + (STM8L_RTCCLK_SOURCE == CLK_RTCSEL_LSE)) +#error "requested LSE clock is not enabled" +#endif + +/** + * @brief System clock. + */ +#if STM8L_NO_CLOCK_INIT || defined(__DOXYGEN__) +#define SYSCLK (HSICLK / 8) +#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSI +#define SYSCLK (HSICLK / (1 << STM8L_SYSCLK_DIVIDER)) +#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_LSI +#define SYSCLK (LSICLK / (1 << STM8L_SYSCLK_DIVIDER)) +#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSE +#define SYSCLK (HSECLK / (1 << STM8L_SYSCLK_DIVIDER)) +#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_LSE +#define SYSCLK (LSECLK / (1 << STM8L_SYSCLK_DIVIDER)) +#else +#error "specified invalid SYSCLK source" +#endif + +/** + * @brief RTC clock. + */ +#if STM8L_NO_CLOCK_INIT || defined(__DOXYGEN__) +#define RTCCLK 0 +#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSI +#define RTCCLK (HSICLK / (1 << STM8L_RTCCLK_DIVIDER)) +#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_LSI +#define RTCCLK (LSICLK / (1 << STM8L_RTCCLK_DIVIDER)) +#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSE +#define RTCCLK (HSECLK / (1 << STM8L_RTCCLK_DIVIDER)) +#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_LSE +#define RTCCLK (LSECLK / (1 << STM8L_RTCCLK_DIVIDER)) +#else +#error "specified invalid RTCCLK source" +#endif + +/** + * @brief CPU clock. + * @details On the STM8L the CPU clock is always equal to the system clock. + */ +#define CPUCLK SYSCLK + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM8L/hal_lld_stm8l_hd.h b/Project/os/hal/platforms/STM8L/hal_lld_stm8l_hd.h new file mode 100644 index 0000000..7255e47 --- /dev/null +++ b/Project/os/hal/platforms/STM8L/hal_lld_stm8l_hd.h @@ -0,0 +1,89 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup STM8L_HD_HAL STM8L High Density sub-family + * + * @ingroup HAL + */ + +/** + * @file STM8L/hal_lld_stm8l_hd.h + * @brief STM8L High Density sub-family capabilities descriptor. + * + * @addtogroup STM8L_HD_HAL + * @{ + */ + +#ifndef _HAL_LLD_STM8L_HD_H_ +#define _HAL_LLD_STM8L_HD_H_ + +/*===========================================================================*/ +/* Sub-family capabilities. */ +/*===========================================================================*/ + +#define STM8L_HAS_ADC1 TRUE + +#define STM8L_HAS_BEEP TRUE + +#define STM8L_HAS_COMP1 TRUE +#define STM8L_HAS_COMP2 TRUE + +#define STM8L_HAS_DAC1 TRUE + +#define STM8L_HAS_DMA1 TRUE + +#define STM8L_HAS_GPIOA TRUE +#define STM8L_HAS_GPIOB TRUE +#define STM8L_HAS_GPIOC TRUE +#define STM8L_HAS_GPIOD TRUE +#define STM8L_HAS_GPIOE TRUE +#define STM8L_HAS_GPIOF TRUE +#define STM8L_HAS_GPIOG TRUE +#define STM8L_HAS_GPIOH TRUE +#define STM8L_HAS_GPIOI TRUE + +#define STM8L_HAS_I2C1 TRUE + +#define STM8L_HAS_LCD TRUE + +#define STM8L_HAS_SPI1 TRUE +#define STM8L_HAS_SPI2 TRUE + +#define STM8L_HAS_TIM1 TRUE +#define STM8L_HAS_TIM2 TRUE +#define STM8L_HAS_TIM3 TRUE +#define STM8L_HAS_TIM4 TRUE +#define STM8L_HAS_TIM5 TRUE + +#define STM8L_HAS_USART1 TRUE +#define STM8L_HAS_USART2 TRUE +#define STM8L_HAS_USART3 TRUE + +#endif /* _HAL_LLD_STM8L_HD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM8L/hal_lld_stm8l_md.h b/Project/os/hal/platforms/STM8L/hal_lld_stm8l_md.h new file mode 100644 index 0000000..d2cbe71 --- /dev/null +++ b/Project/os/hal/platforms/STM8L/hal_lld_stm8l_md.h @@ -0,0 +1,89 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup STM8L_MD_HAL STM8L Medium Density sub-family + * + * @ingroup HAL + */ + +/** + * @file STM8L/hal_lld_stm8l_md.h + * @brief STM8L Medium Density sub-family capabilities descriptor. + * + * @addtogroup STM8L_MD_HAL + * @{ + */ + +#ifndef _HAL_LLD_STM8L_MD_H_ +#define _HAL_LLD_STM8L_MD_H_ + +/*===========================================================================*/ +/* Sub-family capabilities. */ +/*===========================================================================*/ + +#define STM8L_HAS_ADC1 TRUE + +#define STM8L_HAS_BEEP TRUE + +#define STM8L_HAS_COMP1 TRUE +#define STM8L_HAS_COMP2 TRUE + +#define STM8L_HAS_DAC1 TRUE + +#define STM8L_HAS_DMA1 TRUE + +#define STM8L_HAS_GPIOA TRUE +#define STM8L_HAS_GPIOB TRUE +#define STM8L_HAS_GPIOC TRUE +#define STM8L_HAS_GPIOD TRUE +#define STM8L_HAS_GPIOE TRUE +#define STM8L_HAS_GPIOF TRUE +#define STM8L_HAS_GPIOG FALSE +#define STM8L_HAS_GPIOH FALSE +#define STM8L_HAS_GPIOI FALSE + +#define STM8L_HAS_I2C1 TRUE + +#define STM8L_HAS_LCD TRUE + +#define STM8L_HAS_SPI1 TRUE +#define STM8L_HAS_SPI2 FALSE + +#define STM8L_HAS_TIM1 TRUE +#define STM8L_HAS_TIM2 TRUE +#define STM8L_HAS_TIM3 TRUE +#define STM8L_HAS_TIM4 TRUE +#define STM8L_HAS_TIM5 FALSE + +#define STM8L_HAS_USART1 TRUE +#define STM8L_HAS_USART2 FALSE +#define STM8L_HAS_USART3 FALSE + +#endif /* _HAL_LLD_STM8L_MD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM8L/hal_lld_stm8l_mdp.h b/Project/os/hal/platforms/STM8L/hal_lld_stm8l_mdp.h new file mode 100644 index 0000000..ca65330 --- /dev/null +++ b/Project/os/hal/platforms/STM8L/hal_lld_stm8l_mdp.h @@ -0,0 +1,89 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup STM8L_MDP_HAL STM8L Medium Density Plus sub-family + * + * @ingroup HAL + */ + +/** + * @file STM8L/hal_lld_stm8l_mdp.h + * @brief STM8L Medium Density Plus sub-family capabilities descriptor. + * + * @addtogroup STM8L_MDP_HAL + * @{ + */ + +#ifndef _HAL_LLD_STM8L_MDP_H_ +#define _HAL_LLD_STM8L_MDP_H_ + +/*===========================================================================*/ +/* Sub-family capabilities. */ +/*===========================================================================*/ + +#define STM8L_HAS_ADC1 TRUE + +#define STM8L_HAS_BEEP TRUE + +#define STM8L_HAS_COMP1 TRUE +#define STM8L_HAS_COMP2 TRUE + +#define STM8L_HAS_DAC1 TRUE + +#define STM8L_HAS_DMA1 TRUE + +#define STM8L_HAS_GPIOA TRUE +#define STM8L_HAS_GPIOB TRUE +#define STM8L_HAS_GPIOC TRUE +#define STM8L_HAS_GPIOD TRUE +#define STM8L_HAS_GPIOE TRUE +#define STM8L_HAS_GPIOF TRUE +#define STM8L_HAS_GPIOG TRUE +#define STM8L_HAS_GPIOH TRUE +#define STM8L_HAS_GPIOI TRUE + +#define STM8L_HAS_I2C1 TRUE + +#define STM8L_HAS_LCD TRUE + +#define STM8L_HAS_SPI1 TRUE +#define STM8L_HAS_SPI2 TRUE + +#define STM8L_HAS_TIM1 TRUE +#define STM8L_HAS_TIM2 TRUE +#define STM8L_HAS_TIM3 TRUE +#define STM8L_HAS_TIM4 TRUE +#define STM8L_HAS_TIM5 TRUE + +#define STM8L_HAS_USART1 TRUE +#define STM8L_HAS_USART2 TRUE +#define STM8L_HAS_USART3 TRUE + +#endif /* _HAL_LLD_STM8L_MDP_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM8L/pal_lld.c b/Project/os/hal/platforms/STM8L/pal_lld.c new file mode 100644 index 0000000..c118bbb --- /dev/null +++ b/Project/os/hal/platforms/STM8L/pal_lld.c @@ -0,0 +1,116 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM8L/pal_lld.c + * @brief STM8L GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT_PULLUP: + port->DDR &= ~mask; + port->CR1 |= mask; + port->CR2 &= ~mask; + break; + case PAL_MODE_INPUT: + case PAL_MODE_INPUT_ANALOG: + port->DDR &= ~mask; + port->CR1 &= ~mask; + port->CR2 &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + case PAL_MODE_OUTPUT_PUSHPULL_SLOW: + port->DDR |= mask; + port->CR1 |= mask; + port->CR2 &= ~mask; + break; + case PAL_MODE_OUTPUT_PUSHPULL: + port->DDR |= mask; + port->CR1 |= mask; + port->CR2 |= mask; + break; + case PAL_MODE_OUTPUT_OPENDRAIN_SLOW: + port->DDR |= mask; + port->CR1 &= ~mask; + port->CR2 &= ~mask; + break; + case PAL_MODE_OUTPUT_OPENDRAIN: + port->DDR |= mask; + port->CR1 &= ~mask; + port->CR2 |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM8L/pal_lld.h b/Project/os/hal/platforms/STM8L/pal_lld.h new file mode 100644 index 0000000..8d8ae15 --- /dev/null +++ b/Project/os/hal/platforms/STM8L/pal_lld.h @@ -0,0 +1,255 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM8L/pal_lld.h + * @brief STM8L GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLDOWN + +/** + * @brief STM8L specific alternate push-pull slow output mode. + */ +#define PAL_MODE_OUTPUT_PUSHPULL_SLOW 16 + +/** + * @brief STM8L specific alternate open-drain slow output mode. + */ +#define PAL_MODE_OUTPUT_OPENDRAIN_SLOW 17 + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief Generic I/O ports static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { +#if STM8L_HAS_GPIOI || defined(__DOXYGEN__) + GPIO_TypeDef P[9]; +#elif STM8L_HAS_GPIOH || defined(__DOXYGEN__) + GPIO_TypeDef P[8]; +#elif STM8L_HAS_GPIOG || defined(__DOXYGEN__) + GPIO_TypeDef P[7]; +#else + GPIO_TypeDef P[6]; +#endif +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 8 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint8_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint8_t iomode_t; + +/** + * @brief Port Identifier. + */ +typedef GPIO_TypeDef *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief GPIO ports as a whole. + */ +#define IOPORTS ((PALConfig *)0x5000) + +#if STM8L_HAS_GPIOA || defined(__DOXYGEN__) +/** + * @brief GPIO port A identifier. + */ +#define IOPORT1 GPIOA +#endif + +#if STM8L_HAS_GPIOB || defined(__DOXYGEN__) +/** + * @brief GPIO port B identifier. + */ +#define IOPORT2 GPIOB +#endif + +#if STM8L_HAS_GPIOC || defined(__DOXYGEN__) +/** + * @brief GPIO port C identifier. + */ +#define IOPORT3 GPIOC +#endif + +#if STM8L_HAS_GPIOD || defined(__DOXYGEN__) +/** + * @brief GPIO port D identifier. + */ +#define IOPORT4 GPIOD +#endif + +#if STM8L_HAS_GPIOE || defined(__DOXYGEN__) +/** + * @brief GPIO port E identifier. + */ +#define IOPORT5 GPIOE +#endif + +#if STM8L_HAS_GPIOF || defined(__DOXYGEN__) +/** + * @brief GPIO port F identifier. + */ +#define IOPORT6 GPIOF +#endif + +#if STM8L_HAS_GPIOG || defined(__DOXYGEN__) +/** + * @brief GPIO port G identifier. + */ +#define IOPORT7 GPIOG +#endif + +#if STM8L_HAS_GPIOH || defined(__DOXYGEN__) +/** + * @brief GPIO port H identifier. + */ +#define IOPORT8 GPIOH +#endif + +#if STM8L_HAS_GPIOI || defined(__DOXYGEN__) +/** + * @brief GPIO port I identifier. + */ +#define IOPORT9 GPIOI +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) (*IOPORTS = *(config)) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->IDR) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->ODR) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->ODR = (bits)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +extern ROMCONST PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM8L/platform.dox b/Project/os/hal/platforms/STM8L/platform.dox new file mode 100644 index 0000000..00e3be6 --- /dev/null +++ b/Project/os/hal/platforms/STM8L/platform.dox @@ -0,0 +1,110 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup STM8L_DRIVERS STM8L Drivers + * @details This section describes all the supported drivers on the STM8L + * and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup STM8L_HAL STM8L Initialization Support + * @details The STM8L HAL support is responsible for system initialization. + * + * @section stm8l_hal_1 Supported HW resources + * - CLK. + * . + * @section stm8l_hal_2 STM8L HAL driver implementation features + * - Board related initializations. + * - Clock tree initialization. + * - Clock source selection. + * . + * @ingroup STM8L_DRIVERS + */ + +/** + * @defgroup STM8L_PAL STM8L PAL Support + * @details The STM8L PAL driver uses the GPIO peripherals. + * + * @section stm8l_pal_1 Supported HW resources + * - GPIOA. + * - GPIOB. + * - GPIOC. + * - GPIOD. + * - GPIOE. + * - GPIOF. + * - GPIOG. + * - GPIOH (where present). + * - GPIOI (where present). + * . + * @section stm8l_pal_2 STM8L PAL driver implementation features + * The PAL driver implementation fully supports the following hardware + * capabilities: + * - 8 bits wide ports. + * - Atomic set/reset/toggle functions because special STM8L instruction set. + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section stm8l_pal_3 Supported PAL setup modes + * The STM8L PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_PULLUP. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * - @p PAL_MODE_OUTPUT_OPENDRAIN. + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section stm8l_pal_4 Suboptimal behavior + * The STM8L GPIO is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Bus/group writing is not atomic. + * - Pad/group mode setup is not atomic. + * . + * @ingroup STM8L_DRIVERS + */ + +/** + * @defgroup STM8L_SERIAL STM8L Serial Support + * @details The STM8L Serial driver uses the USART1 peripheral in a + * buffered, interrupt driven, implementation. + * + * @section stm8l_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - USART1. + * - USART2 (where present). + * - USART3 (where present). + * . + * @section stm8l_serial_2 STM8L Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Fully interrupt driven. + * . + * @ingroup STM8L_DRIVERS + */ diff --git a/Project/os/hal/platforms/STM8L/serial_lld.c b/Project/os/hal/platforms/STM8L/serial_lld.c new file mode 100644 index 0000000..3e4d3f6 --- /dev/null +++ b/Project/os/hal/platforms/STM8L/serial_lld.c @@ -0,0 +1,220 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM8L/serial_lld.c + * @brief STM8L low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief USART1 serial driver identifier. + */ +#if STM8L_SERIAL_USE_USART1 || defined(__DOXYGEN__) +SerialDriver SD1; +#endif + +/** + * @brief USART2 serial driver identifier. + */ +#if STM8L_SERIAL_USE_USART2 || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/** + * @brief USART3 serial driver identifier. + */ +#if STM8L_SERIAL_USE_USART3 || defined(__DOXYGEN__) +SerialDriver SD3; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** + * @brief Driver default configuration. + */ +static ROMCONST SerialConfig default_config = { + BRR(SERIAL_DEFAULT_BITRATE), + SD_MODE_PARITY_NONE | SD_MODE_STOP_1 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +#if STM8L_SERIAL_USE_USART1 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + USART1->CR2 |= USART_CR2_TIEN; +} +#endif /* STM8L_SERIAL_USE_USART1 */ + +#if STM8L_SERIAL_USE_USART2 || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + USART2->CR2 |= USART_CR2_TIEN; +} +#endif /* STM8L_SERIAL_USE_USART1 */ + +#if STM8L_SERIAL_USE_USART3 || defined(__DOXYGEN__) +static void notify3(GenericQueue *qp) { + + (void)qp; + USART3->CR2 |= USART_CR2_TIEN; +} +#endif /* STM8L_SERIAL_USE_USART3 */ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/* See in serial_lld.h.*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Error handling routine. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] sr USART SR register value + * + * @notapi + */ +void sd_lld_set_error(SerialDriver *sdp, uint8_t sr) { + ioflags_t sts = 0; + + if (sr & USART_SR_OR) + sts |= SD_OVERRUN_ERROR; + if (sr & USART_SR_NF) + sts |= SD_NOISE_ERROR; + if (sr & USART_SR_FE) + sts |= SD_FRAMING_ERROR; + if (sr & USART_SR_PE) + sts |= SD_PARITY_ERROR; + chSysLockFromIsr(); + chIOAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if STM8L_SERIAL_USE_USART1 + sdObjectInit(&SD1, NULL, notify1); + CLK->PCKENR1 |= CLK_PCKENR1_USART1; /* PCKEN12, clock source. */ + USART1->CR1 = USART_CR1_USARTD; /* USARTD (low power). */ + SD1.usart = USART1; +#endif + +#if STM8L_SERIAL_USE_USART2 + sdObjectInit(&SD2, NULL, notify2); + CLK->PCKENR3 |= CLK_PCKENR3_USART2; /* PCKEN13, clock source. */ + USART2->CR1 = USART_CR1_USARTD; /* USARTD (low power). */ + SD2.usart = USART2; +#endif + +#if STM8L_SERIAL_USE_USART3 + sdObjectInit(&SD3, NULL, notify3); + CLK->PCKENR3 |= CLK_PCKENR3_USART3; /* PCKEN13, clock source. */ + USART3->CR1 = USART_CR1_USARTD; /* USARTD (low power). */ + SD3.usart = USART3; +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + USART_TypeDef *u = sdp->usart; + + if (config == NULL) + config = &default_config; + + u->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) | + ((uint8_t)config->sc_brr & (uint8_t)0x0F)); + u->BRR1 = (uint8_t)(config->sc_brr >> 4); + u->CR1 = (uint8_t)(config->sc_mode & SD_MODE_PARITY); + u->CR2 = USART_CR2_RIEN | USART_CR2_TEN | USART_CR2_REN; + u->CR3 = (uint8_t)(config->sc_mode & SD_MODE_STOP); + u->CR4 = 0; + u->CR5 = 0; + u->PSCR = 1; + (void)u->SR; + (void)u->DR; +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + USART_TypeDef *u = sdp->usart; + + u->CR1 = USART_CR1_USARTD; + u->CR2 = 0; + u->CR3 = 0; + u->CR4 = 0; + u->CR5 = 0; + u->PSCR = 0; +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM8L/serial_lld.h b/Project/os/hal/platforms/STM8L/serial_lld.h new file mode 100644 index 0000000..8d523fe --- /dev/null +++ b/Project/os/hal/platforms/STM8L/serial_lld.h @@ -0,0 +1,281 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM8L/serial_lld.h + * @brief STM8L low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define SD_MODE_PARITY 0x07 /**< @brief Parity field mask. */ +#define SD_MODE_PARITY_NONE 0x00 /**< @brief No parity. */ +#define SD_MODE_PARITY_EVEN 0x05 /**< @brief Even parity. */ +#define SD_MODE_PARITY_ODD 0x07 /**< @brief Odd parity. */ + +#define SD_MODE_STOP 0x30 /**< @brief Stop bits mask. */ +#define SD_MODE_STOP_1 0x00 /**< @brief One stop bit. */ +#define SD_MODE_STOP_2 0x20 /**< @brief Two stop bits. */ +#define SD_MODE_STOP_1P5 0x30 /**< @brief 1.5 stop bits. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief USART1 driver enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM8L_SERIAL_USE_USART1) || defined(__DOXYGEN__) +#define STM8L_SERIAL_USE_USART1 TRUE +#endif + +/** + * @brief USART2 driver enable switch. + * @details If set to @p TRUE the support for USART3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM8L_SERIAL_USE_USART2) || defined(__DOXYGEN__) +#define STM8L_SERIAL_USE_USART2 TRUE +#endif + +/** + * @brief USART3 driver enable switch. + * @details If set to @p TRUE the support for USART3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM8L_SERIAL_USE_USART3) || defined(__DOXYGEN__) +#define STM8L_SERIAL_USE_USART3 TRUE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM8L_SERIAL_USE_USART1 && !STM8L_HAS_USART1 +#error "USART1 not present in the selected device" +#endif + +#if STM8L_SERIAL_USE_USART2 && !STM8L_HAS_USART2 +#error "USART2 not present in the selected device" +#endif + +#if STM8L_SERIAL_USE_USART3 && !STM8L_HAS_USART3 +#error "USART3 not present in the selected device" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Generic Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct { + /** + * @brief Bit rate register. + */ + uint16_t sc_brr; + /** + * @brief Mode flags. + */ + uint8_t sc_mode; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + USART_TypeDef *usart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Macro for baud rate computation. + * @note Make sure the final baud rate is within tolerance. + */ +#define BRR(b) (SYSCLK / (b)) + +#if STM8L_SERIAL_USE_USART1 || defined(__DOXYGEN__) +/** + * @brief USART1 RX interrupt handler segment. + */ +#define _USART1_RECEIVE_ISR() { \ + uint8_t sr = USART1->SR; \ + if (sr & (USART_SR_RXNE | USART_SR_OR | USART_SR_NF | \ + USART_SR_FE | USART_SR_PE)) { \ + if (sr & (USART_SR_OR | USART_SR_NF | USART_SR_FE | USART_SR_PE)) \ + sd_lld_set_error(&SD1, sr); \ + chSysLockFromIsr(); \ + sdIncomingDataI(&SD1, USART1->DR); \ + chSysUnlockFromIsr(); \ + } \ +} + +/** + * @brief USART1 TX interrupt handler segment. + */ +#define _USART1_TRANSMIT_ISR() { \ + if (USART1->SR & USART_SR_TXE) { \ + msg_t b; \ + chSysLockFromIsr(); \ + b = sdRequestDataI(&SD1); \ + chSysUnlockFromIsr(); \ + if (b < Q_OK) \ + USART1->CR2 &= (uint8_t)~USART_CR2_TIEN; \ + else \ + USART1->DR = (uint8_t)b; \ + } \ +} +#endif /* STM8L_SERIAL_USE_USART1 */ + +#if STM8L_SERIAL_USE_USART2 || defined(__DOXYGEN__) +/** + * @brief USART2 RX interrupt handler segment. + */ +#define _USART2_RECEIVE_ISR() { \ + uint8_t sr = USART2->SR; \ + if (sr & (USART_SR_RXNE | USART_SR_OR | USART_SR_NF | \ + USART_SR_FE | USART_SR_PE)) { \ + if (sr & (USART_SR_OR | USART_SR_NF | USART_SR_FE | USART_SR_PE)) \ + sd_lld_set_error(&SD2, sr); \ + chSysLockFromIsr(); \ + sdIncomingDataI(&SD2, USART2->DR); \ + chSysUnlockFromIsr(); \ + } \ +} + +/** + * @brief USART2 TX interrupt handler segment. + */ +#define _USART2_TRANSMIT_ISR() { \ + if (USART2->SR & USART_SR_TXE) { \ + msg_t b; \ + chSysLockFromIsr(); \ + b = sdRequestDataI(&SD2); \ + chSysUnlockFromIsr(); \ + if (b < Q_OK) \ + USART2->CR2 &= (uint8_t)~USART_CR2_TIEN; \ + else \ + USART2->DR = (uint8_t)b; \ + } \ +} +#endif /* STM8L_SERIAL_USE_USART2 */ + +#if STM8L_SERIAL_USE_USART3 || defined(__DOXYGEN__) +/** + * @brief USART3 RX interrupt handler segment. + */ +#define _USART3_RECEIVE_ISR() { \ + uint8_t sr = USART3->SR; \ + if (sr & (USART_SR_RXNE | USART_SR_OR | USART_SR_NF | \ + USART_SR_FE | USART_SR_PE)) { \ + if (sr & (USART_SR_OR | USART_SR_NF | USART_SR_FE | USART_SR_PE)) \ + sd_lld_set_error(&SD3, sr); \ + chSysLockFromIsr(); \ + sdIncomingDataI(&SD3, USART3->DR); \ + chSysUnlockFromIsr(); \ + } \ +} + +/** + * @brief USART3 TX interrupt handler segment. + */ +#define _USART3_TRANSMIT_ISR() { \ + if (USART3->SR & USART_SR_TXE) { \ + msg_t b; \ + chSysLockFromIsr(); \ + b = sdRequestDataI(&SD3); \ + chSysUnlockFromIsr(); \ + if (b < Q_OK) \ + USART3->CR2 &= (uint8_t)~USART_CR2_TIEN; \ + else \ + USART3->DR = (uint8_t)b; \ + } \ +} +#endif /* STM8L_SERIAL_USE_USART3 */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM8L_SERIAL_USE_USART1 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if STM8L_SERIAL_USE_USART2 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif +#if STM8L_SERIAL_USE_USART3 && !defined(__DOXYGEN__) +extern SerialDriver SD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); + void sd_lld_set_error(SerialDriver *sdp, uint8_t sr); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM8L/shared_isr.c b/Project/os/hal/platforms/STM8L/shared_isr.c new file mode 100644 index 0000000..7c6bfb9 --- /dev/null +++ b/Project/os/hal/platforms/STM8L/shared_isr.c @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM8L/shared_isr.c + * @brief STM8L shared interrupt code source. + * @details The STM8L shares some interrupt handlers among several sources. + * This module includes all the interrupt handlers that are + * used by more than one peripheral. + * @note Only the interrupt handlers that are used by the HAL are defined + * in this module. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/* This inclusion allows user ISR to be added to the HAL.*/ +#if defined(_USER_ISR_) +#include "user_isr.h" +#endif + +#if defined(_TIM2_UPDATE_ISR) || defined(_USART2_TRANSMIT_ISR) || \ + defined(__DOXYGEN__) +/** + * @brief IRQ 19 service routine. + * @details This handler is shared between the following sources: + * - TIM2 update/overflow/trigger/break. + * - USART2 transmit. + * . + * + * @isr + */ +CH_IRQ_HANDLER(19) { + CH_IRQ_PROLOGUE(); + +#if defined(_TIM2_UPDATE_ISR) + _TIM2_UPDATE_ISR(); +#endif +#if defined(_USART2_TRANSMIT_ISR) + _USART2_TRANSMIT_ISR(); +#endif + + CH_IRQ_EPILOGUE(); +} +#endif /* defined(_TIM2_UPDATE_ISR) || defined(_USART2_TRANSMIT_ISR) */ + +#if defined(_TIM2_COMPARE_ISR) || defined(_USART2_RECEIVE_ISR) || \ + defined(__DOXYGEN__) +/** + * @brief IRQ 20 service routine. + * @details This handler is shared between the following sources: + * - TIM2 compare/capture + * - USART2 receive. + * . + * + * @isr + */ +CH_IRQ_HANDLER(20) { + CH_IRQ_PROLOGUE(); + +#if defined(_TIM2_COMPARE_ISR) + _TIM2_COMPARE_ISR(); +#endif +#if defined(_USART2_RECEIVE_ISR) + _USART2_RECEIVE_ISR(); +#endif + + CH_IRQ_EPILOGUE(); +} +#endif /* defined(_TIM2_COMPARE_ISR) || defined(_USART2_RECEIVE_ISR) */ + +#if defined(_TIM3_UPDATE_ISR) || defined(_USART3_TRANSMIT_ISR) || \ + defined(__DOXYGEN__) +/** + * @brief IRQ 21 service routine. + * @details This handler is shared between the following sources: + * - TIM3 update/overflow/trigger/break. + * - USART3 transmit. + * . + * + * @isr + */ +CH_IRQ_HANDLER(21) { + CH_IRQ_PROLOGUE(); + +#if defined(_TIM3_UPDATE_ISR) + _TIM3_UPDATE_ISR(); +#endif +#if defined(_USART3_TRANSMIT_ISR) + _USART3_TRANSMIT_ISR(); +#endif + + CH_IRQ_EPILOGUE(); +} +#endif /* defined(_TIM3_UPDATE_ISR) || defined(_USART3_TRANSMIT_ISR) */ + +#if defined(_TIM3_COMPARE_ISR) || defined(_USART3_RECEIVE_ISR) || \ + defined(__DOXYGEN__) +/** + * @brief IRQ 22 service routine. + * @details This handler is shared between the following sources: + * - TIM3 compare/capture + * - USART3 receive. + * . + * + * @isr + */ +CH_IRQ_HANDLER(22) { + CH_IRQ_PROLOGUE(); + +#if defined(_TIM3_COMPARE_ISR) + _TIM3_COMPARE_ISR(); +#endif +#if defined(_USART3_RECEIVE_ISR) + _USART3_RECEIVE_ISR(); +#endif + + CH_IRQ_EPILOGUE(); +} +#endif /* defined(_TIM3_COMPARE_ISR) || defined(_USART3_RECEIVE_ISR) */ + +#if defined(_TIM5_UPDATE_ISR) || defined(_USART1_TRANSMIT_ISR) || \ + defined(__DOXYGEN__) +/** + * @brief IRQ 27 service routine. + * @details This handler is shared between the following sources: + * - TIM5 update/overflow/trigger/break. + * - USART1 transmit. + * . + * + * @isr + */ +CH_IRQ_HANDLER(27) { + CH_IRQ_PROLOGUE(); + +#if defined(_TIM5_UPDATE_ISR) + _TIM5_UPDATE_ISR(); +#endif +#if defined(_USART1_TRANSMIT_ISR) + _USART1_TRANSMIT_ISR(); +#endif + + CH_IRQ_EPILOGUE(); +} +#endif /* defined(_TIM5_UPDATE_ISR) || defined(_USART1_TRANSMIT_ISR) */ + +#if defined(_TIM5_COMPARE_ISR) || defined(_USART1_RECEIVE_ISR) || \ + defined(__DOXYGEN__) +/** + * @brief IRQ 28 service routine. + * @details This handler is shared between the following sources: + * - TIM5 compare/capture + * - USART1 receive. + * . + * + * @isr + */ +CH_IRQ_HANDLER(28) { + CH_IRQ_PROLOGUE(); + +#if defined(_TIM5_COMPARE_ISR) + _TIM5_COMPARE_ISR(); +#endif +#if defined(_USART1_RECEIVE_ISR) + _USART1_RECEIVE_ISR(); +#endif + + CH_IRQ_EPILOGUE(); +} +#endif /* defined(_TIM5_COMPARE_ISR) || defined(_USART1_RECEIVE_ISR) */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM8L/stm8l15x.h b/Project/os/hal/platforms/STM8L/stm8l15x.h new file mode 100644 index 0000000..aaea076 --- /dev/null +++ b/Project/os/hal/platforms/STM8L/stm8l15x.h @@ -0,0 +1,2866 @@ +/** + ****************************************************************************** + * @file stm8l15x.h + * @author MCD Application Team + * @version V1.4.0 + * @date 09/24/2010 + * @brief This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM8L15x devices. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM8L15x_H + #define __STM8L15x_H + +/** @addtogroup STM8L15x_StdPeriph_Driver + * @{ + */ +/* Uncomment the line below according to the target STM8L device used in your + application + */ +/* #define STM8L15X_MD */ /*!< STM8L15X_MD: STM8L15x Medium density devices */ +/* #define STM8L15X_MDP */ /*!< STM8L15X_MDP: STM8L15x Medium density plus devices */ +/* #define STM8L15X_HD */ /*!< STM8L15X_HD: STM8L15x/16x High density devices */ + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + + - Medium density STM8L15x devices are STM8L151C4, STM8L151C6, STM8L152C4, + STM8L152C6, STM8L151K4, STM8L151K6, STM8L152K4, STM8L152K6, STM8L151G4, + STM8L151G6, STM8L152G4 and STM8L152G6 microcontrollers where the Flash memory + density ranges between 16 and 32 Kbytes. + - Medium density Plus devices are STM8L151R6, STM8L152R6 microcontrollers where + the Flash memory density is fixed and equal to 32 Kbytes and a wider range of + peripheral than the medium density devices. + - High density STM8L15x devices are STM8L151x8, STM8L152x8, STM8L162R8 and STM8L162M8 + microcontrollers where the Flash memory density is fixed and equal to 64 Kbytes with + the same peripheral set than Medium Density Plus devices. + + */ + +#if !defined (STM8L15X_MD) && !defined (STM8L15X_MDP) && !defined (STM8L15X_HD) + #error "Please select first the target STM8L device used in your application (in stm8l15x.h file)" +#endif + +/******************************************************************************/ +/* Library configuration section */ +/******************************************************************************/ +/* Check the used compiler */ +#if defined(__CSMC__) + #define _COSMIC_ +#elif defined(__RCST7__) + #define _RAISONANCE_ +#elif defined(__ICCSTM8__) + #define _IAR_ +#else + #error "Unsupported Compiler!" /* Compiler defines not found */ +#endif + +#if !defined USE_STDPERIPH_DRIVER +/* Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will be + based on direct access to peripherals registers */ +/* #define USE_STDPERIPH_DRIVER*/ +#endif + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined HSE_Value + #define HSE_VALUE ((uint32_t)16000000) /*!< Typical Value of the HSE in Hz */ +#endif /* HSE_Value */ + +/** + * @brief Definition of External Low Speed oscillator (LSE) frequency + */ +#define LSE_VALUE ((uint32_t)32768) /*!< Typical Value of the LSE in Hz */ + +/** + * @brief Definition of Device on-chip RC oscillator frequencies + */ +#define HSI_VALUE ((uint32_t)16000000) /*!< Typical Value of the HSI in Hz */ +#define LSI_VALUE ((uint32_t)38000) /*!< Typical Value of the LSI in Hz */ + +#ifdef _COSMIC_ + #define FAR @far + #define NEAR @near + #define TINY @tiny + #define EEPROM @eeprom + #define __CONST const + #define IN_RAM +#elif defined (_RAISONANCE_) /* __RCST7__ */ + #define FAR far + #define NEAR data + #define TINY page0 + #define EEPROM eeprom + #define __CONST code + #define IN_RAM inram + #if defined (STM8L15X_MD) || defined (STM8L15X_MDP) + /*!< Used with memory Models for code less than 64K */ + #define MEMCPY memcpy + #else /* STM8L15X_HD */ + /*!< Used with memory Models for code higher than 64K */ + #define MEMCPY fmemcpy + #endif /* STM8L15X_MD or STM8L15X_MDP */ +#else /*_IAR_*/ + #define FAR __far + #define NEAR __near + #define TINY __tiny + #define EEPROM __eeprom + #define __CONST const + #define IN_RAM +#endif /* __CSMC__ */ + +#if defined (STM8L15X_MD) || defined (STM8L15X_MDP) +/*!< Used with memory Models for code smaller than 64K */ + #define PointerAttr NEAR +#else /* STM8L15X_HD */ +/*!< Used with memory Models for code higher than 64K */ + #define PointerAttr FAR +#endif /* STM8L15X_MD or STM8L15X_MDP */ + +/* Uncomment the line below to enable the FLASH functions execution from RAM */ +#if defined(_COSMIC_) + #if !defined (COSMIC_RAM_EXECUTION) + /* #define COSMIC_RAM_EXECUTION (1) */ + #endif + +/* Uncomment the line below to enable the FLASH functions execution from RAM */ +#elif defined (_RAISONANCE_) /* __RCST7__ */ + #if !defined (RAISONANCE_RAM_EXECUTION) + /* #define RAISONANCE_RAM_EXECUTION (1) */ + #endif +/* Uncomment the line below to enable the FLASH functions execution from RAM */ +#elif defined (_IAR_) /* __RCST7__ */ + #if !defined (IAR_RAM_EXECUTION) + /* #define IAR_RAM_EXECUTION (1) */ + #endif +#endif /* __CSMC__ */ + +/*!< [31:16] STM8L15x Standard Peripheral Library main version */ +#define __STM8L15X_STDPERIPH_VERSION_MAIN ((uint8_t)0x01) +/*!< [15:8] STM8L15x Standard Peripheral Library sub1 version */ +#define __STM8L15X_STDPERIPH_VERSION_SUB1 ((uint8_t)0x04) +/*!< [7:0] STM8L15x Standard Peripheral Library sub2 version */ +#define __STM8L15X_STDPERIPH_VERSION_SUB2 ((uint8_t)0x00) +/*!< STM8L15x Standard Peripheral Library version number */ +#define __STM8L15X_STDPERIPH_VERSION ((uint32_t)(__STM8L15X_STDPERIPH_VERSION_MAIN <<(uint32_t)16)\ + | (__STM8L15X_STDPERIPH_VERSION_SUB1 <<(uint32_t) 8)\ + | __STM8L15X_STDPERIPH_VERSION_SUB2) + +/******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ + +/* Exported types and constants-----------------------------------------------*/ + +/** @addtogroup Exported_types + * @{ + */ + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ +#define __I volatile const /*!< defines 'read only' permissions */ +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/* Stupid thing to do...*/ +#if 0 +/*!< Signed integer types */ +typedef signed char int8_t; +typedef signed short int16_t; +typedef signed long int32_t; + +/*!< Unsigned integer types */ +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned long uint32_t; +#endif + +/*!< STM8Lx Standard Peripheral Library old types (maintained for legacy purpose) */ + +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + + +typedef enum {FALSE = 0, TRUE = !FALSE} bool; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#define U8_MAX (255) +#define S8_MAX (127) +#define S8_MIN (-128) +#define U16_MAX (65535u) +#define S16_MAX (32767) +#define S16_MIN (-32768) +#define U32_MAX (4294967295uL) +#define S32_MAX (2147483647) +#define S32_MIN (-2147483648uL) + +/** + * @} + */ + +/** @addtogroup MAP_FILE_Exported_Types_and_Constants + * @{ + */ + +/******************************************************************************/ +/* IP registers structures */ +/******************************************************************************/ + +/*----------------------------------------------------------------------------*/ +/** + * @brief General Purpose I/Os (GPIO) + */ +typedef struct GPIO_struct +{ + __IO uint8_t ODR; /*!< Output Data Register */ + __IO uint8_t IDR; /*!< Input Data Register */ + __IO uint8_t DDR; /*!< Data Direction Register */ + __IO uint8_t CR1; /*!< Configuration Register 1 */ + __IO uint8_t CR2; /*!< Configuration Register 2 */ +} +GPIO_TypeDef; + +/** @addtogroup GPIO_Registers_Reset_Value + * @{ + */ +#define GPIO_ODR_RESET_VALUE ((uint8_t)0x00) +#define GPIO_DDR_RESET_VALUE ((uint8_t)0x00) +#define GPIO_CR1_RESET_VALUE ((uint8_t)0x00) +#define GPIO_CR2_RESET_VALUE ((uint8_t)0x00) +/** + * @} + */ +/*----------------------------------------------------------------------------*/ + +/** + * @brief Real-Time Clock (RTC) peripheral registers. + */ +typedef struct RTC_struct +{ + __IO uint8_t TR1; /*!< Time Register 1*/ + __IO uint8_t TR2; /*!< Time Register 2*/ + __IO uint8_t TR3; /*!< Time Register 3*/ + + __IO uint8_t RESERVED0; + + __IO uint8_t DR1; /*!< Date Register 1*/ + __IO uint8_t DR2; /*!< Date Register 2*/ + __IO uint8_t DR3; /*!< Date Register 3*/ + + __IO uint8_t RESERVED1; + + __IO uint8_t CR1; /*!< Control Register 1*/ + __IO uint8_t CR2; /*!< Control Register 2*/ + __IO uint8_t CR3; /*!< Control Register 3*/ + + __IO uint8_t RESERVED2; + + __IO uint8_t ISR1; /*!< Initialisation and Status Register 1 */ + __IO uint8_t ISR2; /*!< Initialisation and Status Register 2 */ + + __IO uint8_t RESERVED3; + __IO uint8_t RESERVED4; + + __IO uint8_t SPRERH; /*!< Synchronous Prediv high Register */ + __IO uint8_t SPRERL; /*!< Synchronous Prediv Low Register */ + __IO uint8_t APRER; /*!< Asynchronous Prediv Register */ + + __IO uint8_t RESERVED5; + + __IO uint8_t WUTRH; /*!< Wake-Up Timer High Register */ + __IO uint8_t WUTRL; /*!< Wake-Up Timer Low Register */ + + __IO uint8_t RESERVED6; + + __IO uint8_t SSRH; /*!< Sub Second High Register */ + __IO uint8_t SSRL; /*!< Sub Second Low Register */ + + __IO uint8_t WPR; /*!< Write Protection Register */ + + __IO uint8_t SHIFTRH; /*!< Shift control High Register */ + __IO uint8_t SHIFTRL; /*!< Shift control Low Register */ + + __IO uint8_t ALRMAR1; /*!< ALARM A Register 1 */ + __IO uint8_t ALRMAR2; /*!< ALARM A Register 2 */ + __IO uint8_t ALRMAR3; /*!< ALARM A Register 3 */ + __IO uint8_t ALRMAR4; /*!< ALARM A Register 4 */ + + __IO uint8_t RESERVED7[4]; + + __IO uint8_t ALRMASSRH; /*!< ALARM A Subsecond Register High */ + __IO uint8_t ALRMASSRL; /*!< ALARM A Subsecond Register Low */ + __IO uint8_t ALRMASSMSKR; /*!< ALARM A Subsecond Mask Register */ + + __IO uint8_t RESERVED8[3]; + + __IO uint8_t CALRH; /*!< Calibration register high */ + __IO uint8_t CALRL; /*!< Calibration register low */ + + __IO uint8_t TCR1; /*!< Tamper control register 1 */ + __IO uint8_t TCR2; /*!< Tamper control register 2 */ +} +RTC_TypeDef; + +/** @addtogroup RTC_Registers_Reset_Value + * @{ + */ +#define RTC_TR1_RESET_VALUE ((uint8_t)0x00) +#define RTC_TR2_RESET_VALUE ((uint8_t)0x00) +#define RTC_TR3_RESET_VALUE ((uint8_t)0x00) + +#define RTC_DR1_RESET_VALUE ((uint8_t)0x01) +#define RTC_DR2_RESET_VALUE ((uint8_t)0x21) +#define RTC_DR3_RESET_VALUE ((uint8_t)0x00) + +#define RTC_CR1_RESET_VALUE ((uint8_t)0x00) +#define RTC_CR2_RESET_VALUE ((uint8_t)0x00) +#define RTC_CR3_RESET_VALUE ((uint8_t)0x00) + +#define RTC_ISR1_RESET_VALUE ((uint8_t)0x07) +#define RTC_ISR2_RESET_VALUE ((uint8_t)0x00) + +#define RTC_SPRERH_RESET_VALUE ((uint8_t)0x00) +#define RTC_SPRERL_RESET_VALUE ((uint8_t)0xFF) +#define RTC_APRER_RESET_VALUE ((uint8_t)0x7F) + +#define RTC_WUTRH_RESET_VALUE ((uint8_t)0xFF) +#define RTC_WUTRL_RESET_VALUE ((uint8_t)0xFF) + +#define RTC_WPR_RESET_VALUE ((uint8_t)0x00) + +#define RTC_ALRMAR1_RESET_VALUE ((uint8_t)0x00) +#define RTC_ALRMAR2_RESET_VALUE ((uint8_t)0x00) +#define RTC_ALRMAR3_RESET_VALUE ((uint8_t)0x00) +#define RTC_ALRMAR4_RESET_VALUE ((uint8_t)0x00) + +#define RTC_SHIFTRH_RESET_VALUE ((uint8_t)0x00) +#define RTC_SHIFTRL_RESET_VALUE ((uint8_t)0x00) + +#define RTC_ALRMASSRH_RESET_VALUE ((uint8_t)0x00) +#define RTC_ALRMASSRL_RESET_VALUE ((uint8_t)0x00) +#define RTC_ALRMASSMSKR_RESET_VALUE ((uint8_t)0x00) + +#define RTC_CALRH_RESET_VALUE ((uint8_t)0x00) +#define RTC_CALRL_RESET_VALUE ((uint8_t)0x00) + +#define RTC_TCR1_RESET_VALUE ((uint8_t)0x00) +#define RTC_TCR2_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup RTC_Registers_Bits_Definition + * @{ + */ + +/* Bits definition for RTC_TR1 register*/ +#define RTC_TR1_ST ((uint8_t)0x70) +#define RTC_TR1_SU ((uint8_t)0x0F) + +/* Bits definition for RTC_TR2 register*/ +#define RTC_TR2_MNT ((uint8_t)0x70) +#define RTC_TR2_MNU ((uint8_t)0x0F) + +/* Bits definition for RTC_TR3 register*/ +#define RTC_TR3_PM ((uint8_t)0x40) +#define RTC_TR3_HT ((uint8_t)0x30) +#define RTC_TR3_HU ((uint8_t)0x0F) + +/* Bits definition for RTC_DR1 register*/ +#define RTC_DR1_DT ((uint8_t)0x30) +#define RTC_DR1_DU ((uint8_t)0x0F) + +/* Bits definition for RTC_DR2 register*/ +#define RTC_DR2_WDU ((uint8_t)0xE0) +#define RTC_DR2_MT ((uint8_t)0x10) +#define RTC_DR2_MU ((uint8_t)0x0F) + +/* Bits definition for RTC_DR3 register*/ +#define RTC_DR3_YT ((uint8_t)0xF0) +#define RTC_DR3_YU ((uint8_t)0x0F) + +/* Bits definition for RTC_CR1 register*/ +#define RTC_CR1_FMT ((uint8_t)0x40) +#define RTC_CR1_RATIO ((uint8_t)0x20) +#define RTC_CR1_WUCKSEL ((uint8_t)0x07) +#define RTC_CR1_BYPSHAD ((uint8_t)0x10) + + +/* Bits definition for RTC_CR2 register*/ +#define RTC_CR2_WUTIE ((uint8_t)0x40) +#define RTC_CR2_ALRAIE ((uint8_t)0x10) +#define RTC_CR2_WUTE ((uint8_t)0x04) +#define RTC_CR2_ALRAE ((uint8_t)0x01) +#define RTC_CR2_ALRIE ((uint8_t)0x20) + + + +/* Bits definition for RTC_CR3 register*/ +#define RTC_CR3_COE ((uint8_t)0x80) +#define RTC_CR3_OSEL ((uint8_t)0x60) +#define RTC_CR3_POL ((uint8_t)0x10) +#define RTC_CR3_COSEL ((uint8_t)0x08) +#define RTC_CR3_BCK ((uint8_t)0x04) +#define RTC_CR3_SUB1H ((uint8_t)0x02) +#define RTC_CR3_ADD1H ((uint8_t)0x01) + + +/* Bits definition for RTC_ISR1 register*/ +#define RTC_ISR1_INIT ((uint8_t)0x80) +#define RTC_ISR1_INITF ((uint8_t)0x40) +#define RTC_ISR1_RSF ((uint8_t)0x20) +#define RTC_ISR1_INITS ((uint8_t)0x10) +#define RTC_ISR1_SHPF ((uint8_t)0x08) +#define RTC_ISR1_WUTWF ((uint8_t)0x04) +#define RTC_ISR1_RECALPF ((uint8_t)0x02) +#define RTC_ISR1_ALRAWF ((uint8_t)0x01) + + +/* Bits definition for RTC_ISR2 register*/ +#define RTC_ISR2_WUTF ((uint8_t)0x04) +#define RTC_ISR2_ALRAF ((uint8_t)0x01) +#define RTC_ISR2_TAMP3F ((uint8_t)0x80) +#define RTC_ISR2_TAMP2F ((uint8_t)0x40) +#define RTC_ISR2_TAMP1F ((uint8_t)0x20) + +/* Bits definition for RTC_SHIFTRH register*/ +#define RTC_SHIFTRH_ADD1S ((uint8_t)0x80) +#define RTC_SHIFTRH_SUBFS ((uint8_t)0x7F) + +/* Bits definition for RTC_SHIFTRL register*/ +#define RTC_SHIFTRL_SUBFS ((uint8_t)0xFF) + + +/* Bits definition for RTC_ALRMAR1 register*/ +#define RTC_ALRMAR1_MSK1 ((uint8_t)0x80) +#define RTC_ALRMAR1_ST ((uint8_t)0x70) +#define RTC_ALRMAR1_SU ((uint8_t)0x0F) + +/* Bits definition for RTC_ALRMAR2 register*/ +#define RTC_ALRMAR2_MSK2 ((uint8_t)0x80) +#define RTC_ALRMAR2_MNT ((uint8_t)0x70) +#define RTC_ALRMAR2_MNU ((uint8_t)0x0F) + +/* Bits definition for RTC_ALRMAR3 register*/ +#define RTC_ALRMAR3_MSK3 ((uint8_t)0x80) +#define RTC_ALRMAR3_PM ((uint8_t)0x40) +#define RTC_ALRMAR3_HT ((uint8_t)0x30) +#define RTC_ALRMAR3_HU ((uint8_t)0x0F) + +/* Bits definition for RTC_ALRMAR4 register*/ +#define RTC_ALRMAR4_MSK4 ((uint8_t)0x80) +#define RTC_ALRMAR4_WDSEL ((uint8_t)0x40) +#define RTC_ALRMAR4_DT ((uint8_t)0x30) +#define RTC_ALRMAR4_DU ((uint8_t)0x0F) + +/* Bits definition for RTC_ALRMASSRH register*/ +#define RTC_ALRMASSRH_ALSS ((uint8_t)0x7F) + +/* Bits definition for RTC_ALRMASSRL register*/ +#define RTC_ALRMASSRL_ALSS ((uint8_t)0xFF) + +/* Bits definition for RTC_ALRMASSMSKR register*/ +#define RTC_ALRMASSMSKR_MASKSS ((uint8_t)0x1F) + + +/* Bits definition for RTC_CALRH register*/ +#define RTC_CALRH_CALP ((uint8_t)0x80) +#define RTC_CALRH_CALW8 ((uint8_t)0x40) +#define RTC_CALRH_CALW16 ((uint8_t)0x20) +#define RTC_CALRH_CALWx ((uint8_t)0x60) +#define RTC_CALRH_CALM ((uint8_t)0x01) + +/* Bits definition for RTC_CALRL register*/ +#define RTC_CALRL_CALM ((uint8_t)0xFF) + +/* Bits definition for RTC_TCR1 register*/ +#define RTC_TCR1_TAMP3LEVEL ((uint8_t)0x40) +#define RTC_TCR1_TAMP3E ((uint8_t)0x20) +#define RTC_TCR1_TAMP2LEVEL ((uint8_t)0x10) +#define RTC_TCR1_TAMP2E ((uint8_t)0x08) +#define RTC_TCR1_TAMP1LEVEL ((uint8_t)0x04) +#define RTC_TCR1_TAMP1E ((uint8_t)0x02) +#define RTC_TCR1_TAMPIE ((uint8_t)0x01) + +/* Bits definition for RTC_TCR2 register*/ +#define RTC_TCR2_TAMPPUDIS ((uint8_t)0x80) +#define RTC_TCR2_TAMPPRCH ((uint8_t)0x60) +#define RTC_TCR2_TAMPFLT ((uint8_t)0x18) +#define RTC_TCR2_TAMPFREQ ((uint8_t)0x07) + + +/*RTC special defines */ +#define RTC_WPR_EnableKey ((uint8_t)0xFF) +#define RTC_WPR_DisableKey1 ((uint8_t)0xCA) +#define RTC_WPR_DisableKey2 ((uint8_t)0x53) + +/** + * @} + */ + +/** + * @brief CSS on LSE registers. + */ +typedef struct CSSLSE_struct +{ + __IO uint8_t CSR; /*!< Control and Status Register*/ +} +CSSLSE_TypeDef; + +/** @addtogroup CSSLSE_Registers_Reset_Value + * @{ + */ +#define CSSLSE_CSR_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup CSSLSE_Registers_Bits_Definition + * @{ + */ + +/* Bits definition for CSSLSE_CSR register*/ +#define CSSLSE_CSR_SWITCHF ((uint8_t)0x10) +#define CSSLSE_CSR_CSSF ((uint8_t)0x08) +#define CSSLSE_CSR_CSSIE ((uint8_t)0x04) +#define CSSLSE_CSR_SWITCHEN ((uint8_t)0x02) +#define CSSLSE_CSR_CSSEN ((uint8_t)0x01) + +/** + * @} + */ +/*----------------------------------------------------------------------------*/ +/** + * @brief Beeper (BEEP) peripheral registers. + */ + +typedef struct BEEP_struct +{ + __IO uint8_t CSR1; /*!< BEEP Control status register1 */ + uint8_t RSERVED1; + uint8_t RESERVED2; + __IO uint8_t CSR2; /*!< BEEP Control status register2 */ +} +BEEP_TypeDef; + +/** @addtogroup BEEP_Registers_Reset_Value + * @{ + */ +#define BEEP_CSR1_RESET_VALUE ((uint8_t)0x00) +#define BEEP_CSR2_RESET_VALUE ((uint8_t)0x1F) + +/** + * @} + */ + +/** @addtogroup BEEP_Registers_Bits_Definition + * @{ + */ + +#define BEEP_CSR1_MSR ((uint8_t)0x01) /*!< Measurement enable mask */ + +#define BEEP_CSR2_BEEPSEL ((uint8_t)0xC0) /*!< Beeper frequency selection mask */ +#define BEEP_CSR2_BEEPEN ((uint8_t)0x20) /*!< Beeper enable mask */ +#define BEEP_CSR2_BEEPDIV ((uint8_t)0x1F) /*!< Beeper Divider prescalar mask */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------ok*/ + +/** + * @brief Configuration Registers (CFG) + */ + +typedef struct CFG_struct +{ + __IO uint8_t GCR; /*!< Global Configuration register */ +} +CFG_TypeDef; + +/** @addtogroup CFG_Registers_Reset_Value + * @{ + */ + +#define CFG_GCR_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup CFG_Registers_Bits_Definition + * @{ + */ + +#define CFG_GCR_SWD ((uint8_t)0x01) /*!< Swim disable bit mask */ +#define CFG_GCR_AL ((uint8_t)0x02) /*!< Activation Level bit mask */ + +/** + * @} + */ +/*----------------------------------------------------------------------------ok*/ + +/** + * @brief SYSCFG + */ + +typedef struct SYSCFG_struct +{ + __IO uint8_t RMPCR3; /*!< Remap control register 3 */ + __IO uint8_t RMPCR1; /*!< Remap control register 1 */ + __IO uint8_t RMPCR2; /*!< Remap control register 2 */ +} +SYSCFG_TypeDef; + +/** @addtogroup SYSCFG_Registers_Reset_Value + * @{ + */ +#define SYSCFG_RMPCR1_RESET_VALUE ((uint8_t)0x0C) +#define SYSCFG_RMPCR2_RESET_VALUE ((uint8_t)0x00) +#define SYSCFG_RMPCR3_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup SYSCFG_Registers_Bits_Definition + * @{ + */ + +/* For DMA Channel Mapping*/ +#define SYSCFG_RMPCR1_ADC1DMA_REMAP ((uint8_t)0x03) /*!< ADC1 DMA channel remapping */ +#define SYSCFG_RMPCR1_TIM4DMA_REMAP ((uint8_t)0x0C) /*!< TIM4 DMA channel remapping */ + + +/* For GPIO Reapping*/ +#define SYSCFG_RMPCR1_USART1TR_REMAP ((uint8_t)0x30) /*!< USART1_TX and USART1_RX remapping */ +#define SYSCFG_RMPCR1_USART1CK_REMAP ((uint8_t)0x40) /*!< USART1_CK remapping */ +#define SYSCFG_RMPCR1_SPI1_REMAP ((uint8_t)0x80) /*!< SPI1 remapping */ + +#define SYSCFG_RMPCR2_ADC1TRIG_REMAP ((uint8_t)0x01) /*!< ADC1 External Trigger remap */ +#define SYSCFG_RMPCR2_TIM2TRIG_REMAP ((uint8_t)0x02) /*!< TIM2 Trigger remap */ +#define SYSCFG_RMPCR2_TIM3TRIG_REMAP1 ((uint8_t)0x04) /*!< TIM3 Trigger remap 1 */ +#define SYSCFG_RMPCR2_TIM2TRIG_LSE ((uint8_t)0x08) /*!< TIM2 Trigger remap to LSE */ +#define SYSCFG_RMPCR2_TIM3TRIG_LSE ((uint8_t)0x10) /*!< TIM3 Trigger remap to LSE */ +#define SYSCFG_RMPCR2_SPI2_REMAP ((uint8_t)0x20) /*!< SPI2 remapping */ +#define SYSCFG_RMPCR2_TIM3TRIG_REMAP2 ((uint8_t)0x40) /*!< TIM3 Trigger remap 2 */ +#define SYSCFG_RMPCR2_TIM23BKIN_REMAP ((uint8_t)0x80) /*!< TIM2 & TIM3 Break input remap */ + +#define SYSCFG_RMPCR3_SPI1_REMAP ((uint8_t)0x01) /*!< SPI1 remapping */ +#define SYSCFG_RMPCR3_USART3TR_REMAP ((uint8_t)0x02) /*!< USART3_TX and USART3_RX remapping */ +#define SYSCFG_RMPCR3_USART3CK_REMAP ((uint8_t)0x04) /*!< USART3_CK remapping */ +#define SYSCFG_RMPCR3_TIM3CH1_REMAP ((uint8_t)0x08) /*!< TIM3 channel 1 remapping */ +#define SYSCFG_RMPCR3_TIM3CH2_REMAP ((uint8_t)0x10) /*!< TIM3 channel 2 remapping */ +#define SYSCFG_RMPCR3_CCO_REMAP ((uint8_t)0x20) /*!< CCO remapping */ + +/** + * @} + */ +/*----------------------------------------------------------------------------ok*/ + +/** + * @brief Clock Controller (CLK) + */ +typedef struct CLK_struct +{ + __IO uint8_t CKDIVR; /*!< Clock Master Divider Register */ + __IO uint8_t CRTCR; /*!< RTC Clock selection Register */ + __IO uint8_t ICKCR; /*!< Internal Clocks Control Register */ + __IO uint8_t PCKENR1; /*!< Peripheral Clock Gating Register 1 */ + __IO uint8_t PCKENR2; /*!< Peripheral Clock Gating Register 2 */ + __IO uint8_t CCOR; /*!< Configurable Clock Output Register */ + __IO uint8_t ECKCR; /*!< External Clocks Control Register */ + __IO uint8_t SCSR; /*!< System clock status Register */ + __IO uint8_t SWR; /*!< System clock Switch Register */ + __IO uint8_t SWCR; /*!< Switch Control Register */ + __IO uint8_t CSSR; /*!< Clock Security Sytem Register */ + __IO uint8_t CBEEPR; /*!< Clock BEEP Register */ + __IO uint8_t HSICALR; /*!< HSI Calibration Register */ + __IO uint8_t HSITRIMR; /*!< HSI clock Calibration Trimmer Register */ + __IO uint8_t HSIUNLCKR; /*!< HSI Unlock Register */ + __IO uint8_t REGCSR; /*!< Main regulator control status register */ + __IO uint8_t PCKENR3; /*!< Peripheral Clock Gating Register 3 */ +} +CLK_TypeDef; + +/** @addtogroup CLK_Registers_Reset_Value + * @{ + */ +#define CLK_CKDIVR_RESET_VALUE ((uint8_t)0x03) +#define CLK_CRTCR_RESET_VALUE ((uint8_t)0x00) +#define CLK_ICKCR_RESET_VALUE ((uint8_t)0x11) +#define CLK_PCKENR1_RESET_VALUE ((uint8_t)0x00) +#define CLK_PCKENR2_RESET_VALUE ((uint8_t)0x80) +#define CLK_PCKENR3_RESET_VALUE ((uint8_t)0x00) +#define CLK_CCOR_RESET_VALUE ((uint8_t)0x00) +#define CLK_ECKCR_RESET_VALUE ((uint8_t)0x00) +#define CLK_SCSR_RESET_VALUE ((uint8_t)0x01) +#define CLK_SWR_RESET_VALUE ((uint8_t)0x01) +#define CLK_SWCR_RESET_VALUE ((uint8_t)0x00) +#define CLK_CSSR_RESET_VALUE ((uint8_t)0x00) +#define CLK_CBEEPR_RESET_VALUE ((uint8_t)0x00) +#define CLK_HSICALR_RESET_VALUE ((uint8_t)0x00) +#define CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00) +#define CLK_HSIUNLCKR_RESET_VALUE ((uint8_t)0x00) +#define CLK_REGCSR_RESET_VALUE ((uint8_t)0xB9) +/** + * @} + */ + +/** @addtogroup CLK_Registers_Bits_Definition + * @{ + */ + +#define CLK_CKDIVR_CKM ((uint8_t)0x07) /*!< System clock prescaler mask */ + +#define CLK_CRTCR_RTCDIV ((uint8_t)0xE0) /*!< RTC clock prescaler mask*/ +#define CLK_CRTCR_RTCSEL ((uint8_t)0x1E) /*!< RTC clock output selection mask */ +#define CLK_CRTCR_RTCSWBSY ((uint8_t)0x01) /*!< RTC clock switch busy */ + +#define CLK_ICKCR_BEEPAHALT ((uint8_t)0x40) /*!< BEEP clock Active Halt/Halt mode */ +#define CLK_ICKCR_FHWU ((uint8_t)0x20) /*!< Fast Wake-up from Active Halt/Halt mode */ +#define CLK_ICKCR_SAHALT ((uint8_t)0x10) /*!< Slow Active-halt mode */ +#define CLK_ICKCR_LSIRDY ((uint8_t)0x08) /*!< Low speed internal RC oscillator ready */ +#define CLK_ICKCR_LSION ((uint8_t)0x04) /*!< Low speed internal RC oscillator enable */ +#define CLK_ICKCR_HSIRDY ((uint8_t)0x02) /*!< High speed internal RC oscillator ready */ +#define CLK_ICKCR_HSION ((uint8_t)0x01) /*!< High speed internal RC oscillator enable */ + +#define CLK_PCKENR1_TIM2 ((uint8_t)0x01) /*!< Timer 2 clock enable */ +#define CLK_PCKENR1_TIM3 ((uint8_t)0x02) /*!< Timer 3 clock enable */ +#define CLK_PCKENR1_TIM4 ((uint8_t)0x04) /*!< Timer 4 clock enable */ +#define CLK_PCKENR1_I2C1 ((uint8_t)0x08) /*!< I2C1 clock enable */ +#define CLK_PCKENR1_SPI1 ((uint8_t)0x10) /*!< SPI1 clock enable */ +#define CLK_PCKENR1_USART1 ((uint8_t)0x20) /*!< USART1 clock enable */ +#define CLK_PCKENR1_BEEP ((uint8_t)0x40) /*!< BEEP clock enable */ +#define CLK_PCKENR1_DAC ((uint8_t)0x80) /*!< DAC clock enable */ + +#define CLK_PCKENR2_ADC1 ((uint8_t)0x01) /*!< ADC1 clock enable */ +#define CLK_PCKENR2_TIM1 ((uint8_t)0x02) /*!< TIM1 clock enable */ +#define CLK_PCKENR2_RTC ((uint8_t)0x04) /*!< RTC clock enable */ +#define CLK_PCKENR2_LCD ((uint8_t)0x08) /*!< LCD clock enable */ +#define CLK_PCKENR2_DMA1 ((uint8_t)0x10) /*!< DMA1 clock enable */ +#define CLK_PCKENR2_COMP ((uint8_t)0x20) /*!< Comparator clock enable */ +#define CLK_PCKENR2_BOOTROM ((uint8_t)0x80) /*!< Boot ROM clock enable */ + +#define CLK_PCKENR3_AES ((uint8_t)0x01) /*!< AES clock enable */ +#define CLK_PCKENR3_TIM5 ((uint8_t)0x02) /*!< Timer 5 clock enable */ +#define CLK_PCKENR3_SPI2 ((uint8_t)0x04) /*!< SPI2 clock enable */ +#define CLK_PCKENR3_UASRT2 ((uint8_t)0x08) /*!< USART2 clock enable */ +#define CLK_PCKENR3_USART3 ((uint8_t)0x10) /*!< USART3 clock enable */ + +#define CLK_CCOR_CCODIV ((uint8_t)0xE0) /*!< Configurable Clock output prescaler */ +#define CLK_CCOR_CCOSEL ((uint8_t)0x1E) /*!< Configurable clock output selection */ +#define CLK_CCOR_CCOSWBSY ((uint8_t)0x01) /*!< Configurable clock output switch busy flag */ + +#define CLK_ECKCR_LSEBYP ((uint8_t)0x20) /*!< Low speed external clock bypass */ +#define CLK_ECKCR_HSEBYP ((uint8_t)0x10) /*!< High speed external clock bypass */ +#define CLK_ECKCR_LSERDY ((uint8_t)0x08) /*!< Low speed external crystal oscillator ready */ +#define CLK_ECKCR_LSEON ((uint8_t)0x04) /*!< Low speed external crystal oscillator enable */ +#define CLK_ECKCR_HSERDY ((uint8_t)0x02) /*!< High speed external crystal oscillator ready */ +#define CLK_ECKCR_HSEON ((uint8_t)0x01) /*!< High speed external crystal oscillator enable */ + +#define CLK_SCSR_CKM ((uint8_t)0x0F) /*!< System clock status bits */ + +#define CLK_SWR_SWI ((uint8_t)0x0F) /*!< System clock selection bits */ + +#define CLK_SWCR_SWIF ((uint8_t)0x08) /*!< Clock switch interrupt flag */ +#define CLK_SWCR_SWIEN ((uint8_t)0x04) /*!< Clock switch interrupt enable */ +#define CLK_SWCR_SWEN ((uint8_t)0x02) /*!< Switch start/stop */ +#define CLK_SWCR_SWBSY ((uint8_t)0x01) /*!< Switch busy */ + +#define CLK_CSSR_CSSDGON ((uint8_t)0x10) /*!< Clock security sytem deglitcher system */ +#define CLK_CSSR_CSSD ((uint8_t)0x08) /*!< Clock security sytem detection */ +#define CLK_CSSR_CSSDIE ((uint8_t)0x04) /*!< Clock security system detection interrupt enable */ +#define CLK_CSSR_AUX ((uint8_t)0x02) /*!< Auxiliary oscillator connected to master clock */ +#define CLK_CSSR_CSSEN ((uint8_t)0x01) /*!< Clock security system enable */ + +#define CLK_CBEEPR_CLKBEEPSEL ((uint8_t)0x06) /*!< Configurable BEEP clock source selection */ +#define CLK_CBEEPR_BEEPSWBSY ((uint8_t)0x01) /*!< BEEP clock busy in switch */ + +#define CLK_HSICALR_HSICAL ((uint8_t)0xFF) /*!< Copy of otpion byte trimming HSI oscillator */ + +#define CLK_HSITRIMR_HSITRIM ((uint8_t)0xFF) /*!< High speed internal oscillator trimmer */ + +#define CLK_HSIUNLCKR_HSIUNLCK ((uint8_t)0xFF) /*!< High speed internal oscillator trimmer unlock */ + +#define CLK_REGCSR_EEREADY ((uint8_t)0x80) /*!< Flash program memory and Data EEPROM ready */ +#define CLK_REGCSR_EEBUSY ((uint8_t)0x40) /*!< Flash program memory and Data EEPROM busy */ +#define CLK_REGCSR_LSEPD ((uint8_t)0x20) /*!< LSE power-down */ +#define CLK_REGCSR_HSEPD ((uint8_t)0x10) /*!< HSE power-down */ +#define CLK_REGCSR_LSIPD ((uint8_t)0x08) /*!< LSI power-down */ +#define CLK_REGCSR_HSIPD ((uint8_t)0x04) /*!< HSI power-down */ +#define CLK_REGCSR_REGOFF ((uint8_t)0x02) /*!< Main regulator OFF */ +#define CLK_REGCSR_REGREADY ((uint8_t)0x01) /*!< Main regulator ready */ + +/** + * @} + */ +/*----------------------------------------------------------------------------ok*/ + +/** + * @brief Comparator interface (COMP) + */ + +typedef struct COMP_struct +{ + __IO uint8_t CSR1; /*!< Control status register 1 */ + __IO uint8_t CSR2; /*!< Control status register 2 */ + __IO uint8_t CSR3; /*!< Control status register 3 */ + __IO uint8_t CSR4; /*!< Control status register 4 */ + __IO uint8_t CSR5; /*!< Control status register 5 */ +} +COMP_TypeDef; + + +/** @addtogroup COMP_Registers_Reset_Value + * @{ + */ +#define COMP_CSR1_RESET_VALUE ((uint8_t)0x00) +#define COMP_CSR2_RESET_VALUE ((uint8_t)0x00) +#define COMP_CSR3_RESET_VALUE ((uint8_t)0xC0) +#define COMP_CSR4_RESET_VALUE ((uint8_t)0x00) +#define COMP_CSR5_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup COMP_Registers_Bits_Definition + * @{ + */ + +/* CSR1 */ +#define COMP_CSR1_IE1 ((uint8_t)0x20) /*!< Comparator 1 Interrupt Enable Mask. */ +#define COMP_CSR1_EF1 ((uint8_t)0x10) /*!< Comparator 1 Event Flag Mask. */ +#define COMP_CSR1_CMP1OUT ((uint8_t)0x08) /*!< Comparator 1 Ouptput Mask. */ +#define COMP_CSR1_STE ((uint8_t)0x04) /*!< Schmitt trigger enable Mask. */ +#define COMP_CSR1_CMP1 ((uint8_t)0x03) /*!< Comparator 1 Configuration Mask. */ + +/* CSR2 */ +#define COMP_CSR2_IE2 ((uint8_t)0x20) /*!< Comparator 2 Interrupt Enable Mask. */ +#define COMP_CSR2_EF2 ((uint8_t)0x10) /*!< Comparator 2 Event Flag Mask. */ +#define COMP_CSR2_CMP2OUT ((uint8_t)0x08) /*!< Comparator 2 Ouptput Mask. */ +#define COMP_CSR2_SPEED ((uint8_t)0x04) /*!< Comparator 2 speed modeMask. */ +#define COMP_CSR2_CMP2 ((uint8_t)0x03) /*!< Comparator 2 Configuration Mask. */ + +/* CSR3 */ +#define COMP_CSR3_OUTSEL ((uint8_t)0xC0) /*!< Comparator 2 output selection Mask. */ +#define COMP_CSR3_INSEL ((uint8_t)0x38) /*!< Inversion input selection Mask. */ +#define COMP_CSR3_VREFEN ((uint8_t)0x04) /*!< Internal reference voltage Enable Mask. */ +#define COMP_CSR3_WNDWE ((uint8_t)0x02) /*!< Window Mode Enable Mask. */ +#define COMP_CSR3_VREFOUTEN ((uint8_t)0x01) /*!< VREF Output Enable Mask. */ + +/* CSR4 */ +#define COMP_CSR4_NINVTRIG ((uint8_t)0x38) /*!< COMP2 non-inverting input Mask. */ +#define COMP_CSR4_INVTRIG ((uint8_t)0x07) /*!< COMP2 inverting input Mask. */ + +/* CSR5 */ +#define COMP_CSR5_DACTRIG ((uint8_t)0x38) /*!< DAC outputs Mask. */ +#define COMP_CSR5_VREFTRIG ((uint8_t)0x07) /*!< VREF outputs Mask. */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------ok*/ + +/** + * @brief External Interrupt Controller (EXTI) + */ +typedef struct EXTI_struct +{ + __IO uint8_t CR1; /*!< The four LSB EXTI pin sensitivity */ + __IO uint8_t CR2; /*!< The four MSB EXTI pin sensitivity */ + __IO uint8_t CR3; /*!< EXTI port B & port D sensitivity */ + __IO uint8_t SR1; /*!< Pins Status flag register 1 */ + __IO uint8_t SR2; /*!< Ports Status flage register 2 */ + __IO uint8_t CONF1; /*!< Port interrupt selector */ + __IO uint8_t RESERVED[4]; /*!< reserved area */ + __IO uint8_t CR4; /*!< EXTI port G & port H sensitivity */ + __IO uint8_t CONF2; /*!< Port interrupt selector */ +} +EXTI_TypeDef; + +/** @addtogroup EXTI_Registers_Reset_Value + * @{ + */ + +#define EXTI_CR1_RESET_VALUE ((uint8_t)0x00) +#define EXTI_CR2_RESET_VALUE ((uint8_t)0x00) +#define EXTI_CR3_RESET_VALUE ((uint8_t)0x00) +#define EXTI_CONF1_RESET_VALUE ((uint8_t)0x00) +#define EXTI_SR1_RESET_VALUE ((uint8_t)0x00) +#define EXTI_SR2_RESET_VALUE ((uint8_t)0x00) +#define EXTI_CR4_RESET_VALUE ((uint8_t)0x00) +#define EXTI_CONF2_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup EXTI_Registers_Bits_Definition + * @{ + */ +/* CR1 */ +#define EXTI_CR1_P3IS ((uint8_t)0xC0) /*!< EXTI Pin 3 external interrupt sensitivity bit Mask */ +#define EXTI_CR1_P2IS ((uint8_t)0x30) /*!< EXTI Pin 2 external interrupt sensitivity bit Mask */ +#define EXTI_CR1_P1IS ((uint8_t)0x0C) /*!< EXTI Pin 1 external interrupt sensitivity bit Mask */ +#define EXTI_CR1_P0IS ((uint8_t)0x03) /*!< EXTI Pin 0 external interrupt sensitivity bit Mask */ + +/* CR2 */ +#define EXTI_CR2_P7IS ((uint8_t)0xC0) /*!< EXTI Pin 7 external interrupt sensitivity bit Mask */ +#define EXTI_CR2_P6IS ((uint8_t)0x30) /*!< EXTI Pin 6 external interrupt sensitivity bit Mask */ +#define EXTI_CR2_P5IS ((uint8_t)0x0C) /*!< EXTI Pin 5 external interrupt sensitivity bit Mask */ +#define EXTI_CR2_P4IS ((uint8_t)0x03) /*!< EXTI Pin 4 external interrupt sensitivity bit Mask */ + +/* CR3 */ +#define EXTI_CR3_PBIS ((uint8_t)0x03) /*!< EXTI PORTB external interrupt sensitivity bits Mask */ +#define EXTI_CR3_PDIS ((uint8_t)0x0C) /*!< EXTI PORTD external interrupt sensitivity bits Mask */ +#define EXTI_CR3_PEIS ((uint8_t)0x30) /*!< EXTI PORTE external interrupt sensitivity bits Mask */ +#define EXTI_CR3_PFIS ((uint8_t)0xC0) /*!< EXTI PORTF external interrupt sensitivity bits Mask */ + +/* CONF1 */ +#define EXTI_CONF1_PBLIS ((uint8_t)0x01) /*!< EXTI PORTB low interrupt selector bit Mask */ +#define EXTI_CONF1_PBHIS ((uint8_t)0x02) /*!< EXTI PORTB high interrupt selector bit Mask */ +#define EXTI_CONF1_PDLIS ((uint8_t)0x04) /*!< EXTI PORTD low interrupt selector bit Mask */ +#define EXTI_CONF1_PDHIS ((uint8_t)0x08) /*!< EXTI PORTD high interrupt selector bit Mask */ +#define EXTI_CONF1_PELIS ((uint8_t)0x10) /*!< EXTI PORTE low interrupt selector bit Mask */ +#define EXTI_CONF1_PEHIS ((uint8_t)0x20) /*!< EXTI PORTE high interrupt selector bit Mask */ +#define EXTI_CONF1_PFLIS ((uint8_t)0x40) /*!< EXTI PORTF low interrupt selector bit Mask */ +#define EXTI_CONF1_PFES ((uint8_t)0x80) /*!< EXTI PORTF or PORTE interrupt selector bit Mask */ + +/* CR4 */ +#define EXTI_CR4_PGIS ((uint8_t)0x03) /*!< EXTI PORTG external interrupt sensitivity bits Mask */ +#define EXTI_CR4_PHIS ((uint8_t)0x0C) /*!< EXTI PORTH external interrupt sensitivity bits Mask */ + +/* CONF2 */ +#define EXTI_CONF2_PFHIS ((uint8_t)0x01) /*!< EXTI PORTF high interrupt selector bit Mask */ +#define EXTI_CONF2_PGLIS ((uint8_t)0x02) /*!< EXTI PORTG low interrupt selector bit Mask */ +#define EXTI_CONF2_PGHIS ((uint8_t)0x04) /*!< EXTI PORTG high interrupt selector bit Mask */ +#define EXTI_CONF2_PHLIS ((uint8_t)0x08) /*!< EXTI PORTH low interrupt selector bit Mask */ +#define EXTI_CONF2_PHHIS ((uint8_t)0x10) /*!< EXTI PORTH high interrupt selector bit Mask */ +#define EXTI_CONF2_PGBS ((uint8_t)0x20) /*!< EXTI PORTB or PORTG interrupt selector bit Mask */ +#define EXTI_CONF2_PHDS ((uint8_t)0x40) /*!< EXTI PORTD or PORTH interrupt selector bit Mask */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------ok*/ + +/** + * @brief FLASH and Data EEPROM + */ +typedef struct FLASH_struct +{ + __IO uint8_t CR1; /*!< Flash control register 1 */ + __IO uint8_t CR2; /*!< Flash control register 2 */ + __IO uint8_t PUKR; /*!< Flash program memory unprotection register */ + __IO uint8_t DUKR; /*!< Data EEPROM unprotection register */ + __IO uint8_t IAPSR; /*!< Flash in-application programming status register */ +} +FLASH_TypeDef; + +/** @addtogroup FLASH_Registers_Reset_Value + * @{ + */ +#define FLASH_CR1_RESET_VALUE ((uint8_t)0x00) +#define FLASH_CR2_RESET_VALUE ((uint8_t)0x00) +#define FLASH_PUKR_RESET_VALUE ((uint8_t)0xAE) +#define FLASH_DUKR_RESET_VALUE ((uint8_t)0x56) +#define FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40) + + +/** + * @} + */ + +/** @addtogroup FLASH_Registers_Bits_Definition + * @{ + */ +#define FLASH_CR1_EEPM ((uint8_t)0x08) /*!< Flash low power selection during Run and Low power run mode Mask */ +#define FLASH_CR1_WAITM ((uint8_t)0x04) /*!< Flash low power selection during Wait and Low power wait mode Mask */ +#define FLASH_CR1_IE ((uint8_t)0x02) /*!< Flash Interrupt enable Mask */ +#define FLASH_CR1_FIX ((uint8_t)0x01) /*!< Fix programming time Mask */ + +#define FLASH_CR2_OPT ((uint8_t)0x80) /*!< Enable write access to option bytes*/ +#define FLASH_CR2_WPRG ((uint8_t)0x40) /*!< Word write once Mask */ +#define FLASH_CR2_ERASE ((uint8_t)0x20) /*!< Erase block Mask */ +#define FLASH_CR2_FPRG ((uint8_t)0x10) /*!< Fast programming mode Mask */ +#define FLASH_CR2_PRG ((uint8_t)0x01) /*!< Program block Mask */ + +#define FLASH_IAPSR_HVOFF ((uint8_t)0x40) /*!< End of high voltage flag Mask */ +#define FLASH_IAPSR_DUL ((uint8_t)0x08) /*!< Data EEPROM unlocked flag Mask */ +#define FLASH_IAPSR_EOP ((uint8_t)0x04) /*!< End of operation flag Mask */ +#define FLASH_IAPSR_PUL ((uint8_t)0x02) /*!< Program memory unlocked flag Mask */ +#define FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01) /*!< Write attempted to protected page Mask */ + +#define FLASH_PUKR_PUK ((uint8_t)0xFF) /*!< Flash Program memory unprotection mask */ + +#define FLASH_DUKR_DUK ((uint8_t)0xFF) /*!< Data EEPROM unprotection mask */ + + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ + +/** + * @brief Inter-Integrated Circuit (I2C) + */ +typedef struct I2C_struct +{ + __IO uint8_t CR1; /*!< I2C control register 1 */ + __IO uint8_t CR2; /*!< I2C control register 2 */ + __IO uint8_t FREQR; /*!< I2C frequency register */ + __IO uint8_t OARL; /*!< I2C own address register 1 LSB */ + __IO uint8_t OARH; /*!< I2C own address register 1 MSB */ + __IO uint8_t OAR2; /*!< I2C own address register 2 */ + __IO uint8_t DR; /*!< I2C data register */ + __IO uint8_t SR1; /*!< I2C status register 1 */ + __IO uint8_t SR2; /*!< I2C status register 2 */ + __IO uint8_t SR3; /*!< I2C status register 3 */ + __IO uint8_t ITR; /*!< I2C interrupt & DMA register */ + __IO uint8_t CCRL; /*!< I2C clock control register low */ + __IO uint8_t CCRH; /*!< I2C clock control register high */ + __IO uint8_t TRISER; /*!< I2C maximum rise time register */ + __IO uint8_t PECR; /*!< I2CPacket Error Checking register */ +} +I2C_TypeDef; + +/** @addtogroup I2C_Registers_Reset_Value + * @{ + */ +#define I2C_CR1_RESET_VALUE ((uint8_t)0x00) +#define I2C_CR2_RESET_VALUE ((uint8_t)0x00) +#define I2C_FREQR_RESET_VALUE ((uint8_t)0x00) +#define I2C_OARL_RESET_VALUE ((uint8_t)0x00) +#define I2C_OARH_RESET_VALUE ((uint8_t)0x00) +#define I2C_OAR2_RESET_VALUE ((uint8_t)0x00) +#define I2C_DR_RESET_VALUE ((uint8_t)0x00) +#define I2C_SR1_RESET_VALUE ((uint8_t)0x00) +#define I2C_SR2_RESET_VALUE ((uint8_t)0x00) +#define I2C_SR3_RESET_VALUE ((uint8_t)0x00) +#define I2C_ITR_RESET_VALUE ((uint8_t)0x00) +#define I2C_CCRL_RESET_VALUE ((uint8_t)0x00) +#define I2C_CCRH_RESET_VALUE ((uint8_t)0x00) +#define I2C_TRISER_RESET_VALUE ((uint8_t)0x02) +#define I2C_PECR_RESET_VALUE ((uint8_t)0x00) + +/** + * @} + */ + +/** @addtogroup I2C_Registers_Bits_Definition + * @{ + */ + +#define I2C_CR1_NOSTRETCH ((uint8_t)0x80) /*!< Clock Stretching Disable (Slave mode) */ +#define I2C_CR1_ENGC ((uint8_t)0x40) /*!< General Call Enable */ +#define I2C_CR1_ENPEC ((uint8_t)0x20) /*!< PEC Enable */ +#define I2C_CR1_ARP ((uint8_t)0x10) /*!< ARP Enable */ +#define I2C_CR1_SMBTYPE ((uint8_t)0x08) /*!< SMBus type */ +#define I2C_CR1_SMBUS ((uint8_t)0x02) /*!< SMBus mode */ +#define I2C_CR1_PE ((uint8_t)0x01) /*!< Peripheral Enable */ + +#define I2C_CR2_SWRST ((uint8_t)0x80) /*!< Software Reset */ +#define I2C_CR2_ALERT ((uint8_t)0x20) /*!< SMBus Alert*/ +#define I2C_CR2_PEC ((uint8_t)0x10) /*!< Packet Error Checking */ +#define I2C_CR2_POS ((uint8_t)0x08) /*!< Acknowledge */ +#define I2C_CR2_ACK ((uint8_t)0x04) /*!< Acknowledge Enable */ +#define I2C_CR2_STOP ((uint8_t)0x02) /*!< Stop Generation */ +#define I2C_CR2_START ((uint8_t)0x01) /*!< Start Generation */ + +#define I2C_FREQR_FREQ ((uint8_t)0x3F) /*!< Peripheral Clock Frequency */ + +#define I2C_OARL_ADD ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */ +#define I2C_OARL_ADD0 ((uint8_t)0x01) /*!< Interface Address bit0 */ + +#define I2C_OARH_ADDMODE ((uint8_t)0x80) /*!< Addressing Mode (Slave mode) */ +#define I2C_OARH_ADDCONF ((uint8_t)0x40) /*!< Address mode configuration */ +#define I2C_OARH_ADD ((uint8_t)0x06) /*!< Interface Address bits [9..8] */ + +#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */ +#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */ + +#define I2C_DR_DR ((uint8_t)0xFF) /*!< Data Register */ + +#define I2C_SR1_TXE ((uint8_t)0x80) /*!< Data Register Empty (transmitters) */ +#define I2C_SR1_RXNE ((uint8_t)0x40) /*!< Data Register not Empty (receivers) */ +#define I2C_SR1_STOPF ((uint8_t)0x10) /*!< Stop detection (Slave mode) */ +#define I2C_SR1_ADD10 ((uint8_t)0x08) /*!< 10-bit header sent (Master mode) */ +#define I2C_SR1_BTF ((uint8_t)0x04) /*!< Byte Transfer Finished */ +#define I2C_SR1_ADDR ((uint8_t)0x02) /*!< Address sent (master mode)/matched (slave mode) */ +#define I2C_SR1_SB ((uint8_t)0x01) /*!< Start Bit (Master mode) */ + +#define I2C_SR2_SMBALERT ((uint8_t)0x80) /*!< SMBus Alert */ +#define I2C_SR2_TIMEOUT ((uint8_t)0x40) /*!< Time out or TLow error */ +#define I2C_SR2_WUFH ((uint8_t)0x20) /*!< Wake-up from Halt */ +#define I2C_SR2_PECERR ((uint8_t)0x10) /*!< PEC error in reception */ +#define I2C_SR2_OVR ((uint8_t)0x08) /*!< Overrun/Underrun */ +#define I2C_SR2_AF ((uint8_t)0x04) /*!< Acknowledge Failure */ +#define I2C_SR2_ARLO ((uint8_t)0x02) /*!< Arbitration Lost (master mode) */ +#define I2C_SR2_BERR ((uint8_t)0x01) /*!< Bus Error */ + +#define I2C_SR3_DUALF ((uint8_t)0x80) /*!< Dual flag (Slave mode) */ +#define I2C_SR3_SMBHOST ((uint8_t)0x40) /*!< SMBus Host Header (Slave mode) */ +#define I2C_SR3_SMBDEFAULT ((uint8_t)0x20) /*!< SMBus Default Header (Slave mode) */ +#define I2C_SR3_GENCALL ((uint8_t)0x10) /*!< General Call Header (Slave mode) */ +#define I2C_SR3_TRA ((uint8_t)0x04) /*!< Transmitter/Receiver */ +#define I2C_SR3_BUSY ((uint8_t)0x02) /*!< Bus Busy */ +#define I2C_SR3_MSL ((uint8_t)0x01) /*!< Master/Slave */ + +#define I2C_ITR_LAST ((uint8_t)0x10) /*!< DMA Last transfer */ +#define I2C_ITR_DMAEN ((uint8_t)0x08) /*!< DMA request Enable */ +#define I2C_ITR_ITBUFEN ((uint8_t)0x04) /*!< Buffer Interrupt Enable */ +#define I2C_ITR_ITEVTEN ((uint8_t)0x02) /*!< Event Interrupt Enable */ +#define I2C_ITR_ITERREN ((uint8_t)0x01) /*!< Error Interrupt Enable */ + +#define I2C_CCRL_CCR ((uint8_t)0xFF) /*!< Clock Control Register (Master mode) */ + +#define I2C_CCRH_FS ((uint8_t)0x80) /*!< Master Mode Selection */ +#define I2C_CCRH_DUTY ((uint8_t)0x40) /*!< Fast Mode Duty Cycle */ +#define I2C_CCRH_CCR ((uint8_t)0x0F) /*!< Clock Control Register in Fast/Standard mode (Master mode) bits [11..8] */ + +#define I2C_TRISER_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ + +#define I2C_PECR_PEC ((uint8_t)0xFF) /*!< Packet error checking */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ + +/** + * @brief IR digital interface (IRTIM) + */ +typedef struct IRTIM_struct +{ + __IO uint8_t CR; /*!< control register */ +} +IRTIM_TypeDef; +/** @addtogroup IRTIM_Registers_Reset_Value + * @{ + */ +#define IRTIM_CR_RESET_VALUE ((uint8_t)0x00) + + +/** +* @} +*/ + +/** @addtogroup IRTIM_Registers_Bits_Definition + * @{ + */ +/* CR*/ +#define IRTIM_CR_EN ((uint8_t)0x01) /*!< IRTIM_OUT enable Mask. */ +#define IRTIM_CR_HSEN ((uint8_t)0x02) /*!< High sink open drain buffer enable Mask */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ + +/** + * @brief Interrupt Controller (ITC) + */ +typedef struct ITC_struct +{ + __IO uint8_t ISPR1; /*!< Interrupt Software Priority register 1 */ + __IO uint8_t ISPR2; /*!< Interrupt Software Priority register 2 */ + __IO uint8_t ISPR3; /*!< Interrupt Software Priority register 3 */ + __IO uint8_t ISPR4; /*!< Interrupt Software Priority register 4 */ + __IO uint8_t ISPR5; /*!< Interrupt Software Priority register 5 */ + __IO uint8_t ISPR6; /*!< Interrupt Software Priority register 6 */ + __IO uint8_t ISPR7; /*!< Interrupt Software Priority register 7 */ + __IO uint8_t ISPR8; /*!< Interrupt Software Priority register 8 */ +} +ITC_TypeDef; + +/** @addtogroup ITC_Registers_Reset_Value + * @{ + */ +#define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF) /*!< Reset value of Software Priority registers 0 to 7 */ +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ + +/** + * @brief Internal Low Speed Watchdog (IWDG) + */ +typedef struct IWDG_struct +{ + __IO uint8_t KR; /*!< Low Speed Watchdog Key Register */ + __IO uint8_t PR; /*!< Low Speed Watchdog Prescaler Register */ + __IO uint8_t RLR; /*!< Low Speed Watchdog Reload Register */ +} +IWDG_TypeDef; + +/** @addtogroup IWDG_Registers_Reset_Value + * @{ + */ +#define IWDG_RLR_RESET_VALUE ((uint8_t)0xFF) /*! + #define enableInterrupts() _rim_() /*! + #define enableInterrupts() {asm("rim\n");} /* enable interrupts */ + #define disableInterrupts() {asm("sim\n");} /* disable interrupts */ + #define rim() {asm("rim\n");} /* enable interrupts */ + #define sim() {asm("sim\n");} /* disable interrupts */ + #define nop() {asm("nop\n");} /* No Operation */ + #define trap() {asm("trap\n");} /* Trap (soft IT) */ + #define wfi() {asm("wfi\n");} /* Wait For Interrupt */ + #define wfe() {asm("wfe\n");} /* Wait for event */ + #define halt() {asm("halt\n");} /* Halt */ +#endif + +/*============================== Interrupt vector Handling ========================*/ + +#ifdef _COSMIC_ + #define INTERRUPT_HANDLER(a,b) @far @interrupt void a(void) + #define INTERRUPT_HANDLER_TRAP(a) void @far @interrupt a(void) +#endif /* _COSMIC_ */ + +#ifdef _RAISONANCE_ + #define INTERRUPT_HANDLER(a,b) void a(void) interrupt b + #define INTERRUPT_HANDLER_TRAP(a) void a(void) trap +#endif /* _RAISONANCE_ */ + +#ifdef _IAR_ + #define STRINGVECTOR(x) #x + #define VECTOR_ID(x) STRINGVECTOR( vector = (x) ) + #define INTERRUPT_HANDLER( a, b ) \ + _Pragma( VECTOR_ID( (b)+2 ) ) \ + __interrupt void (a)( void ) + #define INTERRUPT_HANDLER_TRAP(a) \ + _Pragma( VECTOR_ID( 1 ) ) \ + __interrupt void (a) (void) +#endif /* _IAR_ */ + +/*============================== Interrupt Handler declaration ========================*/ +#ifdef _COSMIC_ + #define INTERRUPT @far @interrupt +#elif defined(_IAR_) + #define INTERRUPT __interrupt +#endif /* _COSMIC_ */ + +/*============================== Handling bits ====================================*/ +/*----------------------------------------------------------------------------- +Method : I +Description : Handle the bit from the character variables. +Comments : The different parameters of commands are + - VAR : Name of the character variable where the bit is located. + - Place : Bit position in the variable (7 6 5 4 3 2 1 0) + - Value : Can be 0 (reset bit) or not 0 (set bit) + The "MskBit" command allows to select some bits in a source + variables and copy it in a destination var (return the value). + The "ValBit" command returns the value of a bit in a char + variable: the bit is reseted if it returns 0 else the bit is set. + This method generates not an optimised code yet. +-----------------------------------------------------------------------------*/ +#define SetBit(VAR,Place) ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) ) +#define ClrBit(VAR,Place) ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) ) + +#define ChgBit(VAR,Place) ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) ) +#define AffBit(VAR,Place,Value) ((Value) ? \ + ((VAR) |= ((uint8_t)1<<(Place))) : \ + ((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255))) +#define MskBit(Dest,Msk,Src) ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) ) + +#define ValBit(VAR,Place) ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place))) + +#define BYTE_0(n) ((uint8_t)((n) & (uint8_t)0xFF)) /*!< Returns the low byte of the 32-bit value */ +#define BYTE_1(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)8))) /*!< Returns the second byte of the 32-bit value */ +#define BYTE_2(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)16))) /*!< Returns the third byte of the 32-bit value */ +#define BYTE_3(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)24))) /*!< Returns the high byte of the 32-bit value */ + +/*============================== Assert Macros ====================================*/ +#define IS_STATE_VALUE(STATE) \ + (((STATE) == SET) || \ + ((STATE) == RESET)) + +/*----------------------------------------------------------------------------- +Method : II +Description : Handle directly the bit. +Comments : The idea is to handle directly with the bit name. For that, it is + necessary to have RAM area descriptions (example: HW register...) + and the following command line for each area. + This method generates the most optimized code. +-----------------------------------------------------------------------------*/ + +#define AREA 0x00 /* The area of bits begins at address 0x10. */ + +#define BitClr(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) ) +#define BitSet(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) ) +#define BitVal(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) ) + + +#endif /* __STM8L15x_H */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Project/os/hal/platforms/STM8S/hal_lld.c b/Project/os/hal/platforms/STM8S/hal_lld.c new file mode 100644 index 0000000..0706c9e --- /dev/null +++ b/Project/os/hal/platforms/STM8S/hal_lld.c @@ -0,0 +1,118 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM8S/hal_lld.c + * @brief STM8S HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * @details Clock sources initialization, HSI is assumed to be already + * started after reset. + * @note If the @p STM8S_CLOCK_INIT option is set to @p FALSE then the + * initialization is not performed and is left to the application. + * + * @notapi + */ +void hal_lld_init(void) { + +#if !STM8S_NO_CLOCK_INIT + /* Makes sure that HSI is stable before proceeding.*/ + CLK->ICKR |= CLK_ICKR_HSIEN; + while ((CLK->ICKR & CLK_ICKR_HSIRDY) == 0) + ; + + /* LSI startup and stabilization if required.*/ +#if STM8S_LSI_ENABLED + CLK->ICKR |= CLK_ICKR_LSIEN; + while ((CLK->ICKR & CLK_ICKR_LSIRDY) == 0) + ; +#endif + + /* HSE startup and stabilization if required.*/ +#if STM8S_HSE_ENABLED + CLK->ECKR |= CLK_ECKR_HSEEN; + while ((CLK->ECKR & CLK_ECKR_HSERDY) == 0) + ; +#endif + + /* Setting up clock dividers.*/ + CLK->CKDIVR = (STM8S_HSI_DIVIDER << 3) | (STM8S_CPU_DIVIDER << 0); + + /* SYSCLK switch to the selected source, not necessary if it is HSI.*/ +#if STM8S_SYSCLK_SOURCE != CLK_SYSSEL_HSI + /* Switching clock (manual switch mode).*/ + CLK->SWR = STM8S_SYSCLK_SOURCE; + while ((CLK->SWCR & CLK_SWCR_SWIF) == 0) + ; + CLK->SWCR = CLK_SWCR_SWEN; +#endif + + /* Clocks initially all disabled.*/ + CLK->PCKENR1 = 0; + CLK->PCKENR2 = 0; + + /* Other clock related initializations.*/ + CLK->CSSR = 0; + CLK->CCOR = 0; + CLK->CANCCR = STM8S_CAN_DIVIDER_VALUE; + + /* HSI disabled if it is no more required.*/ +#if !STM8S_HSI_ENABLED + CLK->ICKR &= ~CLK_ICKR_HSIEN; +#endif +#endif /* !STM8S_NO_CLOCK_INIT */ +} + +/** @} */ diff --git a/Project/os/hal/platforms/STM8S/hal_lld.h b/Project/os/hal/platforms/STM8S/hal_lld.h new file mode 100644 index 0000000..59e570a --- /dev/null +++ b/Project/os/hal/platforms/STM8S/hal_lld.h @@ -0,0 +1,244 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM8S/hal_lld.h + * @brief STM8S HAL subsystem low level driver source. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - HSECLK (@p 0 if disabled or frequency in Hertz). + * . + * One of the following macros must also be defined: + * - STM8S103. + * - STM8S105. + * - STM8S207. + * - STM8S208. + * - STM8S903. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#undef FALSE +#undef TRUE + +#if defined(STM8S208) || defined(STM8S207) || defined(STM8S105) || \ + defined(STM8S103) || defined(STM8S903) +#include "stm8s.h" +#else +#error "unsupported or invalid STM8 platform" +#endif + +#define FALSE 0 +#define TRUE (!FALSE) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "STM8S" + +#define LSICLK 128000 /**< Low speed internal clock. */ +#define HSICLK 16000000 /**< High speed internal clock. */ + +#define CLK_SYSSEL_HSI 0xE1 /**< HSI clock selector. */ +#define CLK_SYSSEL_LSI 0xD2 /**< LSI clock selector. */ +#define CLK_SYSSEL_HSE 0xB4 /**< HSE clock selector. */ + +#define CLK_HSI_DIV1 0 /**< HSI clock divided by 1. */ +#define CLK_HSI_DIV2 1 /**< HSI clock divided by 2. */ +#define CLK_HSI_DIV4 2 /**< HSI clock divided by 4. */ +#define CLK_HSI_DIV8 3 /**< HSI clock divided by 8. */ + +#define CLK_CPU_DIV1 0 /**< CPU clock divided by 1. */ +#define CLK_CPU_DIV2 1 /**< CPU clock divided by 2. */ +#define CLK_CPU_DIV4 2 /**< CPU clock divided by 4. */ +#define CLK_CPU_DIV8 3 /**< CPU clock divided by 8. */ +#define CLK_CPU_DIV16 4 /**< CPU clock divided by 16. */ +#define CLK_CPU_DIV32 5 /**< CPU clock divided by 32. */ +#define CLK_CPU_DIV64 6 /**< CPU clock divided by 64. */ +#define CLK_CPU_DIV128 7 /**< CPU clock divided by 128. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Disables the clock initialization in the HAL. + */ +#if !defined(STM8S_NO_CLOCK_INIT) || defined(__DOXYGEN__) +#define STM8S_NO_CLOCK_INIT FALSE +#endif + +/** + * @brief Enables or disables the HSI clock source. + */ +#if !defined(STM8S_HSI_ENABLED) || defined(__DOXYGEN__) +#define STM8S_HSI_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM8S_LSI_ENABLED) || defined(__DOXYGEN__) +#define STM8S_LSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the HSE clock source. + */ +#if !defined(STM8S_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM8S_HSE_ENABLED TRUE +#endif + +/** + * @brief Clock source setting. + */ +#if !defined(STM8S_SYSCLK_SOURCE) || defined(__DOXYGEN__) +#define STM8S_SYSCLK_SOURCE CLK_SYSSEL_HSE +#endif + +/** + * @brief HSI clock divider. + */ +#if !defined(STM8S_HSI_DIVIDER) || defined(__DOXYGEN__) +#define STM8S_HSI_DIVIDER CLK_HSI_DIV8 +#endif + +/** + * @brief CPU clock divider. + */ +#if !defined(STM8S_CPU_DIVIDER) || defined(__DOXYGEN__) +#define STM8S_CPU_DIVIDER CLK_CPU_DIV1 +#endif + +/** + * @brief bxCAN divider value. + */ +#if !defined(STM8S_CAN_DIVIDER_VALUE) || defined(__DOXYGEN__) +#define STM8S_CAN_DIVIDER_VALUE 1 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (STM8S_HSI_DIVIDER != CLK_HSI_DIV1) && \ + (STM8S_HSI_DIVIDER != CLK_HSI_DIV2) && \ + (STM8S_HSI_DIVIDER != CLK_HSI_DIV4) && \ + (STM8S_HSI_DIVIDER != CLK_HSI_DIV8) +#error "specified invalid HSI divider" +#endif + +#if (STM8S_CPU_DIVIDER != CLK_CPU_DIV1) && \ + (STM8S_CPU_DIVIDER != CLK_CPU_DIV2) && \ + (STM8S_CPU_DIVIDER != CLK_CPU_DIV4) && \ + (STM8S_CPU_DIVIDER != CLK_CPU_DIV8) && \ + (STM8S_CPU_DIVIDER != CLK_CPU_DIV16) && \ + (STM8S_CPU_DIVIDER != CLK_CPU_DIV32) && \ + (STM8S_CPU_DIVIDER != CLK_CPU_DIV64) && \ + (STM8S_CPU_DIVIDER != CLK_CPU_DIV128) +#error "specified invalid CPU divider" +#endif + +#if (STM8S_CAN_DIVIDER_VALUE < 1) || (STM8S_CAN_DIVIDER_VALUE > 8) +#error "specified invalid CAN divider value" +#endif + +#if STM8S_HSE_ENABLED && (HSECLK == 0) +#error "impossible to activate HSE" +#endif + +#if !STM8S_HSI_ENABLED && (STM8S_SYSCLK_SOURCE == CLK_SYSSEL_HSI) +#error "requested HSI clock is not enabled" +#endif + +#if !STM8S_LSI_ENABLED && (STM8S_SYSCLK_SOURCE == CLK_SYSSEL_LSI) +#error "requested LSI clock is not enabled" +#endif + +#if !STM8S_HSE_ENABLED && (STM8S_SYSCLK_SOURCE == CLK_SYSSEL_HSE) +#error "requested HSE clock is not enabled" +#endif + +/** + * @brief System clock. + */ +#if STM8SL_NO_CLOCK_INIT || defined(__DOXYGEN__) +#define SYSCLK (HSICLK / 8) +#elif STM8S_SYSCLK_SOURCE == CLK_SYSSEL_HSI +#define SYSCLK (HSICLK / (1 << STM8S_HSI_DIVIDER)) +#elif STM8S_SYSCLK_SOURCE == CLK_SYSSEL_LSI +#define SYSCLK LSICLK +#elif STM8S_SYSCLK_SOURCE == CLK_SYSSEL_HSE +#define SYSCLK HSECLK +#else +#error "specified invalid clock source" +#endif + +/** + * @brief CPU clock. + * @details On the STM8SS the CPU clock can be programmed to be a fraction of + * the system clock. + */ +#define CPUCLK (SYSCLK / (1 << STM8S_CPU_DIVIDER)) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM8S/pal_lld.c b/Project/os/hal/platforms/STM8S/pal_lld.c new file mode 100644 index 0000000..3bfec4e --- /dev/null +++ b/Project/os/hal/platforms/STM8S/pal_lld.c @@ -0,0 +1,116 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM8S/pal_lld.c + * @brief STM8S GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT_PULLUP: + port->DDR &= ~mask; + port->CR1 |= mask; + port->CR2 &= ~mask; + break; + case PAL_MODE_INPUT: + case PAL_MODE_INPUT_ANALOG: + port->DDR &= ~mask; + port->CR1 &= ~mask; + port->CR2 &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + case PAL_MODE_OUTPUT_PUSHPULL_SLOW: + port->DDR |= mask; + port->CR1 |= mask; + port->CR2 &= ~mask; + break; + case PAL_MODE_OUTPUT_PUSHPULL: + port->DDR |= mask; + port->CR1 |= mask; + port->CR2 |= mask; + break; + case PAL_MODE_OUTPUT_OPENDRAIN_SLOW: + port->DDR |= mask; + port->CR1 &= ~mask; + port->CR2 &= ~mask; + break; + case PAL_MODE_OUTPUT_OPENDRAIN: + port->DDR |= mask; + port->CR1 &= ~mask; + port->CR2 |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM8S/pal_lld.h b/Project/os/hal/platforms/STM8S/pal_lld.h new file mode 100644 index 0000000..1134543 --- /dev/null +++ b/Project/os/hal/platforms/STM8S/pal_lld.h @@ -0,0 +1,240 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM8S/pal_lld.h + * @brief STM8S GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLDOWN + +/** + * @brief STM8S specific alternate push-pull slow output mode. + */ +#define PAL_MODE_OUTPUT_PUSHPULL_SLOW 16 + +/** + * @brief STM8S specific alternate open-drain slow output mode. + */ +#define PAL_MODE_OUTPUT_OPENDRAIN_SLOW 17 + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief Generic I/O ports static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { +#if defined(STM8S105) || defined(__DOXYGEN__) + GPIO_TypeDef P[7]; +#elif defined(STM8S207) || defined(STM8S208) + GPIO_TypeDef P[9]; +#else + GPIO_TypeDef P[6]; +#endif +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 8 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint8_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint8_t iomode_t; + +/** + * @brief Port Identifier. + */ +typedef GPIO_TypeDef *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief GPIO ports as a whole. + */ +#define IOPORTS ((PALConfig *)0x5000) + +/** + * @brief GPIO port A identifier. + */ +#define IOPORT1 GPIOA + +/** + * @brief GPIO port B identifier. + */ +#define IOPORT2 GPIOB + +/** + * @brief GPIO port C identifier. + */ +#define IOPORT3 GPIOC + +/** + * @brief GPIO port D identifier. + */ +#define IOPORT4 GPIOD + +/** + * @brief GPIO port E identifier. + */ +#define IOPORT5 GPIOE + +/** + * @brief GPIO port F identifier. + */ +#define IOPORT6 GPIOF + +#if defined(STM8S207) || defined(STM8S208) || defined(STM8S105) || \ + defined(__DOXYGEN__) +/** + * @brief GPIO port G identifier. + */ +#define IOPORT7 GPIOG +#endif + +#if defined(STM8S207) || defined(STM8S208) || defined(__DOXYGEN__) +/** + * @brief GPIO port H identifier. + */ +#define IOPORT8 GPIOH + +/** + * @brief GPIO port I identifier. + */ +#define IOPORT9 GPIOI +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) (*IOPORTS = *(config)) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->IDR) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->ODR) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->ODR = (bits)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +extern ROMCONST PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM8S/platform.dox b/Project/os/hal/platforms/STM8S/platform.dox new file mode 100644 index 0000000..8e2ef88 --- /dev/null +++ b/Project/os/hal/platforms/STM8S/platform.dox @@ -0,0 +1,130 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup STM8S STM8S Drivers + * @details This section describes all the supported drivers on the STM8S + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup STM8S_HAL STM8S Initialization Support + * @details The STM8S HAL support is responsible for system initialization. + * + * @section stm8s_hal_1 Supported HW resources + * - CLK. + * . + * @section stm8s_hal_2 STM8S HAL driver implementation features + * - Clock tree initialization. + * - Clock source selection. + * . + * @ingroup STM8S + */ + +/** + * @defgroup STM8S_PAL STM8S PAL Support + * @details The STM8S PAL driver uses the GPIO peripherals. + * + * @section stm8s_pal_1 Supported HW resources + * - GPIOA. + * - GPIOB. + * - GPIOC. + * - GPIOD. + * - GPIOE. + * - GPIOF. + * - GPIOG (where present). + * - GPIOH (where present). + * - GPIOI (where present). + * . + * @section stm8s_pal_2 STM8S PAL driver implementation features + * The PAL driver implementation fully supports the following hardware + * capabilities: + * - 8 bits wide ports. + * - Atomic set/reset/toggle functions because special STM8S instruction set. + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section stm8s_pal_3 Supported PAL setup modes + * The STM8S PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_PULLUP. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * - @p PAL_MODE_OUTPUT_OPENDRAIN. + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section stm8s_pal_4 Suboptimal behavior + * The STM8S GPIO is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Bus/group writing is not atomic. + * - Pad/group mode setup is not atomic. + * . + * @ingroup STM8S + */ + +/** + * @defgroup STM8S_SERIAL STM8S Serial Support + * @details The STM8S Serial driver uses the UART peripherals in a + * buffered, interrupt driven, implementation. + * + * @section stm8s_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - UART1. + * - UART2 (where present). + * - UART3 (where present). + * . + * @section stm8s_serial_2 STM8S Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * . + * @ingroup STM8S + */ + +/** + * @defgroup STM8S_SPI STM8S SPI Support + * @details The SPI driver supports the STM8S SPI peripheral in an interrupt + * driven implementation. + * @note Being the SPI a fast peripheral, much care must be taken to + * not saturate the CPU bandwidth with an excessive IRQ rate. The + * maximum transfer bit rate is likely limited by the IRQ + * handling. + * + * @section stm8s_spi_1 Supported HW resources + * - SPI. + * . + * @section stm8s_spi_2 STM8S SPI driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Fully interrupt driven. + * . + * @ingroup STM8S + */ diff --git a/Project/os/hal/platforms/STM8S/serial_lld.c b/Project/os/hal/platforms/STM8S/serial_lld.c new file mode 100644 index 0000000..106a8ef --- /dev/null +++ b/Project/os/hal/platforms/STM8S/serial_lld.c @@ -0,0 +1,457 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM8S/serial_lld.c + * @brief STM8S low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief UART1 serial driver identifier. + */ +#if STM8S_SERIAL_USE_UART1 || defined(__DOXYGEN__) +SerialDriver SD1; +#endif + +/** + * @brief UART2 serial driver identifier. + */ +#if STM8S_SERIAL_USE_UART2 || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/** + * @brief UART3 serial driver identifier. + */ +#if STM8S_SERIAL_USE_UART3 || defined(__DOXYGEN__) +SerialDriver SD3; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** + * @brief Driver default configuration. + */ +static ROMCONST SerialConfig default_config = { + BRR(SERIAL_DEFAULT_BITRATE), + SD_MODE_PARITY_NONE | SD_MODE_STOP_1 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void set_error(SerialDriver *sdp, uint8_t sr) { + ioflags_t sts = 0; + + /* Note, SR register bit definitions are equal for all UARTs so using + the UART1 definitions is fine.*/ + if (sr & UART1_SR_OR) + sts |= SD_OVERRUN_ERROR; + if (sr & UART1_SR_NF) + sts |= SD_NOISE_ERROR; + if (sr & UART1_SR_FE) + sts |= SD_FRAMING_ERROR; + if (sr & UART1_SR_PE) + sts |= SD_PARITY_ERROR; + chSysLockFromIsr(); + chIOAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +#if STM8S_SERIAL_USE_UART1 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + UART1->CR2 |= UART1_CR2_TIEN; +} + +/** + * @brief UART1 initialization. + * + * @param[in] config architecture-dependent serial driver configuration + */ +static void uart1_init(const SerialConfig *config) { + + UART1->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) | + ((uint8_t)config->sc_brr & (uint8_t)0x0F)); + UART1->BRR1 = (uint8_t)(config->sc_brr >> 4); + UART1->CR1 = (uint8_t)(config->sc_mode & + SD_MODE_PARITY); /* PIEN included. */ + UART1->CR2 = UART1_CR2_RIEN | UART1_CR2_TEN | UART1_CR2_REN; + UART1->CR3 = (uint8_t)(config->sc_mode & SD_MODE_STOP); + UART1->CR4 = 0; + UART1->CR5 = 0; + UART1->PSCR = 1; + (void)UART1->SR; + (void)UART1->DR; +} + +/** + * @brief UART1 de-initialization. + */ +static void uart1_deinit(void) { + + UART1->CR1 = UART1_CR1_UARTD; + UART1->CR2 = 0; + UART1->CR3 = 0; + UART1->CR4 = 0; + UART1->CR5 = 0; + UART1->PSCR = 0; +} +#endif /* STM8S_SERIAL_USE_UART1 */ + +#if STM8S_SERIAL_USE_UART2 || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + UART2->CR2 |= UART2_CR2_TIEN; +} + +/** + * @brief UART2 initialization. + * + * @param[in] config architecture-dependent serial driver configuration + */ +static void uart2_init(const SerialConfig *config) { + + UART2->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) | + ((uint8_t)config->sc_brr & (uint8_t)0x0F)); + UART2->BRR1 = (uint8_t)(config->sc_brr >> 4); + UART2->CR1 = (uint8_t)(config->sc_mode & + SD_MODE_PARITY); /* PIEN included. */ + UART2->CR2 = UART2_CR2_RIEN | UART2_CR2_TEN | UART2_CR2_REN; + UART2->CR3 = (uint8_t)(config->sc_mode & SD_MODE_STOP); + UART2->CR4 = 0; + UART2->CR5 = 0; + UART2->CR6 = 0; + UART2->PSCR = 1; + (void)UART2->SR; + (void)UART2->DR; +} + +/** + * @brief UART1 de-initialization. + */ +static void uart2_deinit(void) { + + UART2->CR1 = UART2_CR1_UARTD; + UART2->CR2 = 0; + UART2->CR3 = 0; + UART2->CR4 = 0; + UART2->CR5 = 0; + UART2->CR6 = 0; + UART2->PSCR = 0; +} +#endif /* STM8S_SERIAL_USE_UART1 */ + +#if STM8S_SERIAL_USE_UART3 || defined(__DOXYGEN__) +static void notify3(GenericQueue *qp) { + + (void)qp; + UART3->CR2 |= UART3_CR2_TIEN; +} + +/** + * @brief UART3 initialization. + * + * @param[in] config architecture-dependent serial driver configuration + */ +static void uart3_init(const SerialConfig *config) { + + UART3->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) | + ((uint8_t)config->sc_brr & (uint8_t)0x0F)); + UART3->BRR1 = (uint8_t)(config->sc_brr >> 4); + UART3->CR1 = (uint8_t)(config->sc_mode & + SD_MODE_PARITY); /* PIEN included. */ + UART3->CR2 = UART3_CR2_RIEN | UART3_CR2_TEN | UART3_CR2_REN; + UART3->CR3 = (uint8_t)(config->sc_mode & SD_MODE_STOP); + UART3->CR4 = 0; + UART3->CR6 = 0; + (void)UART3->SR; + (void)UART3->DR; +} + +/** + * @brief UART3 de-initialization. + */ +static void uart3_deinit(void) { + + UART3->CR1 = UART3_CR1_UARTD; + UART3->CR2 = 0; + UART3->CR3 = 0; + UART3->CR4 = 0; + UART3->CR6 = 0; +} +#endif /* STM8S_SERIAL_USE_UART3 */ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM8S_SERIAL_USE_UART1 || defined(__DOXYGEN__) +/** + * @brief IRQ 17 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(17) { + msg_t b; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + b = sdRequestDataI(&SD1); + chSysUnlockFromIsr(); + if (b < Q_OK) + UART1->CR2 &= (uint8_t)~UART1_CR2_TIEN; + else + UART1->DR = (uint8_t)b; + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief IRQ 18 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(18) { + uint8_t sr = UART1->SR; + + CH_IRQ_PROLOGUE(); + + if ((sr = UART1->SR) & (UART1_SR_OR | UART1_SR_NF | + UART1_SR_FE | UART1_SR_PE)) + set_error(&SD1, sr); + chSysLockFromIsr(); + sdIncomingDataI(&SD1, UART1->DR); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM8S_SERIAL_USE_UART1 */ + +#if STM8S_SERIAL_USE_UART2 || defined(__DOXYGEN__) +/** + * @brief IRQ 20 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(20) { + msg_t b; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + b = sdRequestDataI(&SD2); + chSysUnlockFromIsr(); + if (b < Q_OK) + UART2->CR2 &= (uint8_t)~UART2_CR2_TIEN; + else + UART2->DR = (uint8_t)b; + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief IRQ 21 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(21) { + uint8_t sr = UART2->SR; + + CH_IRQ_PROLOGUE(); + + if ((sr = UART2->SR) & (UART2_SR_OR | UART2_SR_NF | + UART2_SR_FE | UART2_SR_PE)) + set_error(&SD2, sr); + chSysLockFromIsr(); + sdIncomingDataI(&SD2, UART2->DR); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM8S_SERIAL_USE_UART2 */ + +#if STM8S_SERIAL_USE_UART3 || defined(__DOXYGEN__) +/** + * @brief IRQ 20 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(20) { + msg_t b; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + b = sdRequestDataI(&SD3); + chSysUnlockFromIsr(); + if (b < Q_OK) + UART3->CR2 &= (uint8_t)~UART3_CR2_TIEN; + else + UART3->DR = (uint8_t)b; + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief IRQ 21 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(21) { + uint8_t sr = UART3->SR; + + CH_IRQ_PROLOGUE(); + + if ((sr = UART3->SR) & (UART3_SR_OR | UART3_SR_NF | + UART3_SR_FE | UART3_SR_PE)) + set_error(&SD3, sr); + chSysLockFromIsr(); + sdIncomingDataI(&SD3, UART3->DR); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM8S_SERIAL_USE_UART3 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if STM8S_SERIAL_USE_UART1 + sdObjectInit(&SD1, NULL, notify1); + CLK->PCKENR1 |= CLK_PCKENR1_UART1; /* PCKEN12, clock source. */ + UART1->CR1 = UART1_CR1_UARTD; /* UARTD (low power). */ +#endif + +#if STM8S_SERIAL_USE_UART2 + sdObjectInit(&SD2, NULL, notify2); + CLK->PCKENR1 |= CLK_PCKENR1_UART2; /* PCKEN13, clock source. */ + UART2->CR1 = UART2_CR1_UARTD; /* UARTD (low power). */ +#endif + +#if STM8S_SERIAL_USE_UART3 + sdObjectInit(&SD3, NULL, notify3); + CLK->PCKENR1 |= CLK_PCKENR1_UART3; /* PCKEN13, clock source. */ + UART3->CR1 = UART3_CR1_UARTD; /* UARTD (low power). */ +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + +#if STM8S_SERIAL_USE_UART1 + if (&SD1 == sdp) { + uart1_init(config); + return; + } +#endif +#if STM8S_SERIAL_USE_UART2 + if (&SD2 == sdp) { + uart2_init(config); + return; + } +#endif +#if STM8S_SERIAL_USE_UART3 + if (&SD3 == sdp) { + uart3_init(config); + return; + } +#endif +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + +#if STM8S_SERIAL_USE_UART1 + if (&SD1 == sdp) { + uart1_deinit(); + return; + } +#endif +#if STM8S_SERIAL_USE_UART2 + if (&SD2 == sdp) { + uart2_deinit(); + return; + } +#endif +#if STM8S_SERIAL_USE_UART3 + if (&SD3 == sdp) { + uart3_deinit(); + return; + } +#endif +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM8S/serial_lld.h b/Project/os/hal/platforms/STM8S/serial_lld.h new file mode 100644 index 0000000..81d470e --- /dev/null +++ b/Project/os/hal/platforms/STM8S/serial_lld.h @@ -0,0 +1,172 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM8S/serial_lld.h + * @brief STM8S low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define SD_MODE_PARITY 0x07 /**< @brief Parity field mask. */ +#define SD_MODE_PARITY_NONE 0x00 /**< @brief No parity. */ +#define SD_MODE_PARITY_EVEN 0x05 /**< @brief Even parity. */ +#define SD_MODE_PARITY_ODD 0x07 /**< @brief Odd parity. */ + +#define SD_MODE_STOP 0x30 /**< @brief Stop bits mask. */ +#define SD_MODE_STOP_1 0x00 /**< @brief One stop bit. */ +#define SD_MODE_STOP_2 0x20 /**< @brief Two stop bits. */ +#define SD_MODE_STOP_1P5 0x30 /**< @brief 1.5 stop bits. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief UART1 driver enable switch. + * @details If set to @p TRUE the support for UART1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM8S_SERIAL_USE_UART1) || defined(__DOXYGEN__) +#define STM8S_SERIAL_USE_UART1 TRUE +#endif + +/** + * @brief UART2 driver enable switch. + * @details If set to @p TRUE the support for UART3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM8S_SERIAL_USE_UART2) || defined(__DOXYGEN__) +#define STM8S_SERIAL_USE_UART2 TRUE +#endif + +/** + * @brief UART3 driver enable switch. + * @details If set to @p TRUE the support for UART3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM8S_SERIAL_USE_UART3) || defined(__DOXYGEN__) +#define STM8S_SERIAL_USE_UART3 TRUE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM8S_SERIAL_USE_UART2 && STM8S_SERIAL_USE_UART3 +#error "STM8S UART2 and UART3 cannot be used together" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Generic Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct { + /** + * @brief Bit rate register. + */ + uint16_t sc_brr; + /** + * @brief Mode flags. + */ + uint8_t sc_mode; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Macro for baud rate computation. + * @note Make sure the final baud rate is within tolerance. + */ +#define BRR(b) (SYSCLK / (b)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM8S_SERIAL_USE_UART1 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if STM8S_SERIAL_USE_UART2 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif +#if STM8S_SERIAL_USE_UART3 && !defined(__DOXYGEN__) +extern SerialDriver SD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM8S/spi_lld.c b/Project/os/hal/platforms/STM8S/spi_lld.c new file mode 100644 index 0000000..83c879b --- /dev/null +++ b/Project/os/hal/platforms/STM8S/spi_lld.c @@ -0,0 +1,300 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM8S/spi_lld.c + * @brief STM8S low level SPI driver code. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if STM8S_SPI_USE_SPI || defined(__DOXYGEN__) +/** @brief SPI1 driver identifier.*/ +SPIDriver SPID1; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM8S_SPI_USE_SPI || defined(__DOXYGEN__) +/** + * @brief IRQ 10 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(10) { + + CH_IRQ_PROLOGUE(); + + if ((SPI->SR & SPI_SR_OVR) != 0) { + /* The overflow condition should never happen because priority is given + to receive but a hook macro is provided anyway...*/ + STM8S_SPI_ERROR_HOOK(&SPID1); + } + /* Handling the DR register like it is a FIFO with depth>1 in order to + handle the case where a frame arrives immediately after reading the + DR register.*/ + while ((SPI->SR & SPI_SR_RXNE) != 0) { + if (SPID1.rxptr != NULL) + *SPID1.rxptr++ = SPI->DR; + else + (void)SPI->DR; + if (--SPID1.rxcnt == 0) { + chDbgAssert(SPID1.txcnt == 0, + "IRQ10, #1", "counter out of synch"); + /* Stops all the IRQ sources.*/ + SPI->ICR = 0; + /* Portable SPI ISR code defined in the high level driver, note, it + is a macro.*/ + _spi_isr_code(&SPID1); + /* Goto because it is mandatory to go through the epilogue, cannot + just return.*/ + goto exit_isr; + } + } + /* Loading the DR register.*/ + if ((SPI->SR & SPI_SR_TXE) != 0) { + if (SPID1.txptr != NULL) + SPI->DR = *SPID1.txptr++; + else + SPI->DR = 0xFF; + } + +exit_isr: + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +#if STM8S_SPI_USE_SPI + spiObjectInit(&SPID1); +#endif /* STM8S_SPI_USE_SPI */ +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + /* Clock activation.*/ + CLK->PCKENR1 |= CLK_PCKENR1_SPI; /* PCKEN11, clock source. */ + + /* Configuration.*/ + SPI->CR1 = 0; + SPI->CR1 = spip->config->cr1 | SPI_CR1_MSTR; + SPI->CR2 = SPI_CR2_SSI | SPI_CR2_SSM; + SPI->CR1 |= SPI_CR1_SPE; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + (void)spip; + + /* Reset state.*/ + SPI->CR1 = 0; + SPI->CR2 = 0; + SPI->ICR = 0; + + /* Clock de-activation.*/ + CLK->PCKENR1 &= (uint8_t)~CLK_PCKENR1_SPI; /* PCKEN11, clock source. */ +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This function transmits a series of idle words on the SPI bus and + * ignores the received data. This function can be invoked even + * when a slave select signal has not been yet asserted. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + spip->rxptr = NULL; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + SPI->ICR = SPI_ICR_TXEI | SPI_ICR_RXEI | SPI_ICR_ERRIE; +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + SPI->ICR = SPI_ICR_TXEI | SPI_ICR_RXEI | SPI_ICR_ERRIE; +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + spip->rxptr = NULL; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + SPI->ICR = SPI_ICR_TXEI | SPI_ICR_RXEI | SPI_ICR_ERRIE; +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + SPI->ICR = SPI_ICR_TXEI | SPI_ICR_RXEI | SPI_ICR_ERRIE; +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame) { + + (void)spip; + + SPI->DR = (uint32_t)frame; + while ((SPI->SR & SPI_SR_RXNE) == 0) + ; + return (uint16_t)SPI->DR; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM8S/spi_lld.h b/Project/os/hal/platforms/STM8S/spi_lld.h new file mode 100644 index 0000000..e129af5 --- /dev/null +++ b/Project/os/hal/platforms/STM8S/spi_lld.h @@ -0,0 +1,198 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file STM8S/spi_lld.h + * @brief STM8S low level SPI driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for device SSP0 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM8S_SPI_USE_SPI) || defined(__DOXYGEN__) +#define STM8S_SPI_USE_SPI TRUE +#endif + +/** + * @brief Overflow error hook. + * @details The default action is to stop the system. + */ +#if !defined(STM8S_SPI_SPI_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM8S_SPI_ERROR_HOOK(spip) chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM8S_SPI_USE_SPI +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief SPI initialization data. + */ + uint8_t cr1; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Number of bytes yet to be received. + */ + uint16_t rxcnt; + /** + * @brief Receive pointer or @p NULL. + */ + uint8_t *rxptr; + /** + * @brief Number of bytes yet to be transmitted. + */ + uint16_t txcnt; + /** + * @brief Transmit pointer or @p NULL. + */ + const uint8_t *txptr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM8S_SPI_USE_SPI && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/STM8S/stm8s.h b/Project/os/hal/platforms/STM8S/stm8s.h new file mode 100644 index 0000000..c210092 --- /dev/null +++ b/Project/os/hal/platforms/STM8S/stm8s.h @@ -0,0 +1,2567 @@ +/** + ****************************************************************************** + * @file stm8s.h + * @brief This file contains all HW registers definitions and memory mapping. + * @author STMicroelectronics - MCD Application Team + * @version V1.1.1 + * @date 06/05/2009 + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ * @image html logo.bmp + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM8S_H +#define __STM8S_H + +/******************************************************************************/ +/* Library configuration section */ +/******************************************************************************/ +/* Check the used compiler */ +#if defined(__CSMC__) + #undef _RAISONANCE_ + #define _COSMIC_ +#elif defined(__RCST7__) + #undef _COSMIC_ + #define _RAISONANCE_ +#else + #error "Unsupported Compiler!" /* Compiler defines not found */ +#endif + +/* Uncomment the line below according to the target STM8S device used in your + application. + Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. */ +#if !defined (STM8S208) && !defined (STM8S207) && !defined (STM8S105) && !defined (STM8S103) && !defined (STM8S903) + #define STM8S208 + /* #define STM8S207 */ + /* #define STM8S105 */ + /* #define STM8S103 */ + /* #define STM8S903 */ +#endif + + +#if !defined USE_STDPERIPH_DRIVER +/* Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will be + based on direct access to peripherals registers */ +/* #define USE_STDPERIPH_DRIVER*/ +#endif + +/* For FLASH routines, select whether pointer will be declared as near (2 bytes, handle + code smaller than 64KB) or far (3 bytes, handle code larger than 64K) */ +/*#define PointerAttr_Near 1 */ /*!< Used with memory Models for code smaller than 64K */ +#define PointerAttr_Far 2 /*!< Used with memory Models for code larger than 64K */ + +#ifdef _COSMIC_ + #define FAR @far + #define NEAR @near + #define TINY @tiny + #define __CONST const +#else /* __RCST7__ */ + #define FAR far + #define NEAR data + #define TINY page0 + #define __CONST code +#endif /* __CSMC__ */ + +#ifdef PointerAttr_Far + #define PointerAttr FAR +#else /* PointerAttr_Near */ + #define PointerAttr NEAR +#endif /* PointerAttr_Far */ + + +/* Uncomment the line below to use the cosmic section */ +#if defined(_COSMIC_) +/* #define USE_COSMIC_SECTIONS (1)*/ +#endif + +/******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm8s_type.h" + +/* Exported types and constants-----------------------------------------------*/ +/** @addtogroup MAP_FILE_Exported_Types_and_Constants + * @{ + */ + +/******************************************************************************/ +/* IP registers structures */ +/******************************************************************************/ +/*----------------------------------------------------------------------------*/ +/** + * @brief General Purpose I/Os (GPIO) + */ + +typedef struct GPIO_struct +{ + vu8 ODR; /*!< Output Data Register */ + vu8 IDR; /*!< Input Data Register */ + vu8 DDR; /*!< Data Direction Register */ + vu8 CR1; /*!< Configuration Register 1 */ + vu8 CR2; /*!< Configuration Register 2 */ +} +GPIO_TypeDef; + +/** @addtogroup GPIO_Registers_Reset_Value + * @{ + */ + +#define GPIO_ODR_RESET_VALUE ((u8)0x00) +#define GPIO_DDR_RESET_VALUE ((u8)0x00) +#define GPIO_CR1_RESET_VALUE ((u8)0x00) +#define GPIO_CR2_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +#if defined(STM8S105) || defined(STM8S103) || defined(STM8S903) +/** + * @brief Analog to Digital Converter (ADC1) + */ +typedef struct ADC1_struct +{ + vu8 DB0RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB0RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB1RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB1RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB2RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB2RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB3RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB3RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB4RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB4RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB5RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB5RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB6RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB6RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB7RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB7RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB8RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB8RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB9RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB9RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 RESERVED[12]; /*!< Reserved byte */ + vu8 CSR; /*!< ADC1 control status register */ + vu8 CR1; /*!< ADC1 configuration register 1 */ + vu8 CR2; /*!< ADC1 configuration register 2 */ + vu8 CR3; /*!< ADC1 configuration register 3 */ + vu8 DRH; /*!< ADC1 Data high */ + vu8 DRL; /*!< ADC1 Data low */ + vu8 TDRH; /*!< ADC1 Schmitt trigger disable register high */ + vu8 TDRL; /*!< ADC1 Schmitt trigger disable register low */ + vu8 HTRH; /*!< ADC1 high threshold register High*/ + vu8 HTRL; /*!< ADC1 high threshold register Low*/ + vu8 LTRH; /*!< ADC1 low threshold register high */ + vu8 LTRL; /*!< ADC1 low threshold register low */ + vu8 AWSRH; /*!< ADC1 watchdog status register high */ + vu8 AWSRL; /*!< ADC1 watchdog status register low */ + vu8 AWCRH; /*!< ADC1 watchdog control register high */ + vu8 AWCRL; /*!< ADC1 watchdog control register low */ +} +ADC1_TypeDef; + +/** @addtogroup ADC1_Registers_Reset_Value + * @{ + */ + +#define ADC1_CSR_RESET_VALUE ((u8)0x00) +#define ADC1_CR1_RESET_VALUE ((u8)0x00) +#define ADC1_CR2_RESET_VALUE ((u8)0x00) +#define ADC1_CR3_RESET_VALUE ((u8)0x00) +#define ADC1_TDRL_RESET_VALUE ((u8)0x00) +#define ADC1_TDRH_RESET_VALUE ((u8)0x00) +#define ADC1_HTRL_RESET_VALUE ((u8)0x03) +#define ADC1_HTRH_RESET_VALUE ((u8)0xFF) +#define ADC1_LTRH_RESET_VALUE ((u8)0x00) +#define ADC1_LTRL_RESET_VALUE ((u8)0x00) +#define ADC1_AWCRH_RESET_VALUE ((u8)0x00) +#define ADC1_AWCRL_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup ADC1_Registers_Bits_Definition + * @{ + */ + +#define ADC1_CSR_EOC ((u8)0x80) /*!< End of Conversion mask */ +#define ADC1_CSR_AWD ((u8)0x40) /*!< Analog Watch Dog Status mask */ +#define ADC1_CSR_EOCIE ((u8)0x20) /*!< Interrupt Enable for EOC mask */ +#define ADC1_CSR_AWDIE ((u8)0x10) /*!< Analog Watchdog interrupt enable mask */ +#define ADC1_CSR_CH ((u8)0x0F) /*!< Channel selection bits mask */ + +#define ADC1_CR1_SPSEL ((u8)0x70) /*!< Prescaler selectiont mask */ +#define ADC1_CR1_CONT ((u8)0x02) /*!< Continuous conversion mask */ +#define ADC1_CR1_ADON ((u8)0x01) /*!< A/D Converter on/off mask */ + +#define ADC1_CR2_EXTTRIG ((u8)0x40) /*!< External trigger enable mask */ +#define ADC1_CR2_EXTSEL ((u8)0x30) /*!< External event selection mask */ +#define ADC1_CR2_ALIGN ((u8)0x08) /*!< Data Alignment mask */ +#define ADC1_CR2_SCAN ((u8)0x02) /*!< Scan mode mask */ + +#define ADC1_CR3_DBUF ((u8)0x80) /*!< Data Buffer Enable mask */ +#define ADC1_CR3_OVR ((u8)0x40) /*!< Overrun Status Flag mask */ + +#endif /* (STM8S105) ||(STM8S103) || (STM8S903) */ +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief Analog to Digital Converter (ADC2) + */ +#if defined(STM8S208) || defined(STM8S207) +typedef struct ADC2_struct +{ + vu8 CSR; /*!< ADC2 control status register */ + vu8 CR1; /*!< ADC2 configuration register 1 */ + vu8 CR2; /*!< ADC2 configuration register 2 */ + vu8 RESERVED; /*!< Reserved byte */ + vu8 DRH; /*!< ADC2 Data high */ + vu8 DRL; /*!< ADC2 Data low */ + vu8 TDRH; /*!< ADC2 Schmitt trigger disable register high */ + vu8 TDRL; /*!< ADC2 Schmitt trigger disable register low */ +} +ADC2_TypeDef; + +/** @addtogroup ADC2_Registers_Reset_Value + * @{ + */ + +#define ADC2_CSR_RESET_VALUE ((u8)0x00) +#define ADC2_CR1_RESET_VALUE ((u8)0x00) +#define ADC2_CR2_RESET_VALUE ((u8)0x00) +#define ADC2_TDRL_RESET_VALUE ((u8)0x00) +#define ADC2_TDRH_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup ADC2_Registers_Bits_Definition + * @{ + */ + +#define ADC2_CSR_EOC ((u8)0x80) /*!< End of Conversion mask */ +#define ADC2_CSR_EOCIE ((u8)0x20) /*!< Interrupt Enable for EOC mask */ +#define ADC2_CSR_CH ((u8)0x0F) /*!< Channel selection bits mask */ + +#define ADC2_CR1_SPSEL ((u8)0x70) /*!< Prescaler selectiont mask */ +#define ADC2_CR1_CONT ((u8)0x02) /*!< Continuous conversion mask */ +#define ADC2_CR1_ADON ((u8)0x01) /*!< A/D Converter on/off mask */ + +#define ADC2_CR2_EXTTRIG ((u8)0x40) /*!< External trigger enable mask */ +#define ADC2_CR2_EXTSEL ((u8)0x30) /*!< External event selection mask */ +#define ADC2_CR2_ALIGN ((u8)0x08) /*!< Data Alignment mask */ + +#endif /* (STM8S208) ||(STM8S207) */ +/** + * @} + */ +/*----------------------------------------------------------------------------*/ +/** + * @brief Auto Wake Up (AWU) peripheral registers. + */ + +typedef struct AWU_struct +{ + vu8 CSR; /*!< AWU Control status register */ + vu8 APR; /*!< AWU Asynchronous prescalar buffer */ + vu8 TBR; /*!< AWU Time base selection register */ +} +AWU_TypeDef; + +/** @addtogroup AWU_Registers_Reset_Value + * @{ + */ + +#define AWU_CSR_RESET_VALUE ((u8)0x00) +#define AWU_APR_RESET_VALUE ((u8)0x3F) +#define AWU_TBR_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup AWU_Registers_Bits_Definition + * @{ + */ + +#define AWU_CSR_AWUF ((u8)0x20) /*!< Interrupt flag mask */ +#define AWU_CSR_AWUEN ((u8)0x10) /*!< Auto Wake-up enable mask */ +#define AWU_CSR_MR ((u8)0x02) /*!< Master Reset mask */ +#define AWU_CSR_MSR ((u8)0x01) /*!< Measurement enable mask */ + +#define AWU_APR_APR ((u8)0x3F) /*!< Asynchronous Prescaler divider mask */ + +#define AWU_TBR_AWUTB ((u8)0x0F) /*!< Timebase selection mask */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief Beeper (BEEP) peripheral registers. + */ + +typedef struct BEEP_struct +{ + vu8 CSR; /*!< BEEP Control status register */ +} +BEEP_TypeDef; + +/** @addtogroup BEEP_Registers_Reset_Value + * @{ + */ + +#define BEEP_CSR_RESET_VALUE ((u8)0x1F) + +/** + * @} + */ + +/** @addtogroup BEEP_Registers_Bits_Definition + * @{ + */ + +#define BEEP_CSR_BEEPSEL ((u8)0xC0) /*!< Beeper frequency selection mask */ +#define BEEP_CSR_BEEPEN ((u8)0x20) /*!< Beeper enable mask */ +#define BEEP_CSR_BEEPDIV ((u8)0x1F) /*!< Beeper Divider prescalar mask */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief Clock Controller (CLK) + */ + +typedef struct CLK_struct +{ + vu8 ICKR; /*!< Internal Clocks Control Register */ + vu8 ECKR; /*!< External Clocks Control Register */ + u8 RESERVED; /*!< Reserved byte */ + vu8 CMSR; /*!< Clock Master Status Register */ + vu8 SWR; /*!< Clock Master Switch Register */ + vu8 SWCR; /*!< Switch Control Register */ + vu8 CKDIVR; /*!< Clock Divider Register */ + vu8 PCKENR1; /*!< Peripheral Clock Gating Register 1 */ + vu8 CSSR; /*!< Clock Security Sytem Register */ + vu8 CCOR; /*!< Configurable Clock Output Register */ + vu8 PCKENR2; /*!< Peripheral Clock Gating Register 2 */ + vu8 CANCCR; /*!< CAN external clock control Register (exist only in STM8S208 otherwise it is reserved) */ + vu8 HSITRIMR; /*!< HSI Calibration Trimmer Register */ + vu8 SWIMCCR; /*!< SWIM clock control register */ +} +CLK_TypeDef; + +/** @addtogroup CLK_Registers_Reset_Value + * @{ + */ + +#define CLK_ICKR_RESET_VALUE ((u8)0x01) +#define CLK_ECKR_RESET_VALUE ((u8)0x00) +#define CLK_CMSR_RESET_VALUE ((u8)0xE1) +#define CLK_SWR_RESET_VALUE ((u8)0xE1) +#define CLK_SWCR_RESET_VALUE ((u8)0x00) +#define CLK_CKDIVR_RESET_VALUE ((u8)0x18) +#define CLK_PCKENR1_RESET_VALUE ((u8)0xFF) +#define CLK_PCKENR2_RESET_VALUE ((u8)0xFF) +#define CLK_CSSR_RESET_VALUE ((u8)0x00) +#define CLK_CCOR_RESET_VALUE ((u8)0x00) +#define CLK_CANCCR_RESET_VALUE ((u8)0x00) +#define CLK_HSITRIMR_RESET_VALUE ((u8)0x00) +#define CLK_SWIMCCR_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup CLK_Registers_Bits_Definition + * @{ + */ + +#define CLK_ICKR_SWUAH ((u8)0x20) /*!< Slow Wake-up from Active Halt/Halt modes */ +#define CLK_ICKR_LSIRDY ((u8)0x10) /*!< Low speed internal oscillator ready */ +#define CLK_ICKR_LSIEN ((u8)0x08) /*!< Low speed internal RC oscillator enable */ +#define CLK_ICKR_FHWU ((u8)0x04) /*!< Fast Wake-up from Active Halt/Halt mode */ +#define CLK_ICKR_HSIRDY ((u8)0x02) /*!< High speed internal RC oscillator ready */ +#define CLK_ICKR_HSIEN ((u8)0x01) /*!< High speed internal RC oscillator enable */ + +#define CLK_ECKR_HSERDY ((u8)0x02) /*!< High speed external crystal oscillator ready */ +#define CLK_ECKR_HSEEN ((u8)0x01) /*!< High speed external crystal oscillator enable */ + +#define CLK_CMSR_CKM ((u8)0xFF) /*!< Clock master status bits */ + +#define CLK_SWR_SWI ((u8)0xFF) /*!< Clock master selection bits */ + +#define CLK_SWCR_SWIF ((u8)0x08) /*!< Clock switch interrupt flag */ +#define CLK_SWCR_SWIEN ((u8)0x04) /*!< Clock switch interrupt enable */ +#define CLK_SWCR_SWEN ((u8)0x02) /*!< Switch start/stop */ +#define CLK_SWCR_SWBSY ((u8)0x01) /*!< Switch busy */ + +#define CLK_CKDIVR_HSIDIV ((u8)0x18) /*!< High speed internal clock prescaler */ +#define CLK_CKDIVR_CPUDIV ((u8)0x07) /*!< CPU clock prescaler */ + +#define CLK_PCKENR1_TIM1 ((u8)0x80) /*!< Timer 1 clock enable */ +#define CLK_PCKENR1_TIM3 ((u8)0x40) /*!< Timer 3 clock enable */ +#define CLK_PCKENR1_TIM2 ((u8)0x20) /*!< Timer 2 clock enable */ +#define CLK_PCKENR1_TIM5 ((u8)0x20) /*!< Timer 5 clock enable */ +#define CLK_PCKENR1_TIM4 ((u8)0x10) /*!< Timer 4 clock enable */ +#define CLK_PCKENR1_TIM6 ((u8)0x10) /*!< Timer 6 clock enable */ +#define CLK_PCKENR1_UART3 ((u8)0x08) /*!< UART3 clock enable */ +#define CLK_PCKENR1_UART2 ((u8)0x08) /*!< UART2 clock enable */ +#define CLK_PCKENR1_UART1 ((u8)0x04) /*!< UART1 clock enable */ +#define CLK_PCKENR1_SPI ((u8)0x02) /*!< SPI clock enable */ +#define CLK_PCKENR1_I2C ((u8)0x01) /*!< I2C clock enable */ + +#define CLK_PCKENR2_CAN ((u8)0x80) /*!< CAN clock enable */ +#define CLK_PCKENR2_ADC ((u8)0x08) /*!< ADC clock enable */ +#define CLK_PCKENR2_AWU ((u8)0x04) /*!< AWU clock enable */ + +#define CLK_CSSR_CSSD ((u8)0x08) /*!< Clock security sytem detection */ +#define CLK_CSSR_CSSDIE ((u8)0x04) /*!< Clock security system detection interrupt enable */ +#define CLK_CSSR_AUX ((u8)0x02) /*!< Auxiliary oscillator connected to master clock */ +#define CLK_CSSR_CSSEN ((u8)0x01) /*!< Clock security system enable */ + +#define CLK_CCOR_CCOBSY ((u8)0x40) /*!< Configurable clock output busy */ +#define CLK_CCOR_CCORDY ((u8)0x20) /*!< Configurable clock output ready */ +#define CLK_CCOR_CCOSEL ((u8)0x1E) /*!< Configurable clock output selection */ +#define CLK_CCOR_CCOEN ((u8)0x01) /*!< Configurable clock output enable */ + +#define CLK_CANCCR_CANDIV ((u8)0x07) /*!< External CAN clock divider */ + +#define CLK_HSITRIMR_HSITRIM ((u8)0x07) /*!< High speed internal oscillator trimmer */ + +#define CLK_SWIMCCR_SWIMDIV ((u8)0x01) /*!< SWIM Clock Dividing Factor */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief 16-bit timer with complementary PWM outputs (TIM1) + */ + +typedef struct TIM1_struct +{ + vu8 CR1; /*!< control register 1 */ + vu8 CR2; /*!< control register 2 */ + vu8 SMCR; /*!< Synchro mode control register */ + vu8 ETR; /*!< external trigger register */ + vu8 IER; /*!< interrupt enable register*/ + vu8 SR1; /*!< status register 1 */ + vu8 SR2; /*!< status register 2 */ + vu8 EGR; /*!< event generation register */ + vu8 CCMR1; /*!< CC mode register 1 */ + vu8 CCMR2; /*!< CC mode register 2 */ + vu8 CCMR3; /*!< CC mode register 3 */ + vu8 CCMR4; /*!< CC mode register 4 */ + vu8 CCER1; /*!< CC enable register 1 */ + vu8 CCER2; /*!< CC enable register 2 */ + vu8 CNTRH; /*!< counter high */ + vu8 CNTRL; /*!< counter low */ + vu8 PSCRH; /*!< prescaler high */ + vu8 PSCRL; /*!< prescaler low */ + vu8 ARRH; /*!< auto-reload register high */ + vu8 ARRL; /*!< auto-reload register low */ + vu8 RCR; /*!< Repetition Counter register */ + vu8 CCR1H; /*!< capture/compare register 1 high */ + vu8 CCR1L; /*!< capture/compare register 1 low */ + vu8 CCR2H; /*!< capture/compare register 2 high */ + vu8 CCR2L; /*!< capture/compare register 2 low */ + vu8 CCR3H; /*!< capture/compare register 3 high */ + vu8 CCR3L; /*!< capture/compare register 3 low */ + vu8 CCR4H; /*!< capture/compare register 3 high */ + vu8 CCR4L; /*!< capture/compare register 3 low */ + vu8 BKR; /*!< Break Register */ + vu8 DTR; /*!< dead-time register */ + vu8 OISR; /*!< Output idle register */ +} +TIM1_TypeDef; + +/** @addtogroup TIM1_Registers_Reset_Value + * @{ + */ + +#define TIM1_CR1_RESET_VALUE ((u8)0x00) +#define TIM1_CR2_RESET_VALUE ((u8)0x00) +#define TIM1_SMCR_RESET_VALUE ((u8)0x00) +#define TIM1_ETR_RESET_VALUE ((u8)0x00) +#define TIM1_IER_RESET_VALUE ((u8)0x00) +#define TIM1_SR1_RESET_VALUE ((u8)0x00) +#define TIM1_SR2_RESET_VALUE ((u8)0x00) +#define TIM1_EGR_RESET_VALUE ((u8)0x00) +#define TIM1_CCMR1_RESET_VALUE ((u8)0x00) +#define TIM1_CCMR2_RESET_VALUE ((u8)0x00) +#define TIM1_CCMR3_RESET_VALUE ((u8)0x00) +#define TIM1_CCMR4_RESET_VALUE ((u8)0x00) +#define TIM1_CCER1_RESET_VALUE ((u8)0x00) +#define TIM1_CCER2_RESET_VALUE ((u8)0x00) +#define TIM1_CNTRH_RESET_VALUE ((u8)0x00) +#define TIM1_CNTRL_RESET_VALUE ((u8)0x00) +#define TIM1_PSCRH_RESET_VALUE ((u8)0x00) +#define TIM1_PSCRL_RESET_VALUE ((u8)0x00) +#define TIM1_ARRH_RESET_VALUE ((u8)0xFF) +#define TIM1_ARRL_RESET_VALUE ((u8)0xFF) +#define TIM1_RCR_RESET_VALUE ((u8)0x00) +#define TIM1_CCR1H_RESET_VALUE ((u8)0x00) +#define TIM1_CCR1L_RESET_VALUE ((u8)0x00) +#define TIM1_CCR2H_RESET_VALUE ((u8)0x00) +#define TIM1_CCR2L_RESET_VALUE ((u8)0x00) +#define TIM1_CCR3H_RESET_VALUE ((u8)0x00) +#define TIM1_CCR3L_RESET_VALUE ((u8)0x00) +#define TIM1_CCR4H_RESET_VALUE ((u8)0x00) +#define TIM1_CCR4L_RESET_VALUE ((u8)0x00) +#define TIM1_BKR_RESET_VALUE ((u8)0x00) +#define TIM1_DTR_RESET_VALUE ((u8)0x00) +#define TIM1_OISR_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup TIM1_Registers_Bits_Definition + * @{ + */ +/* CR1*/ +#define TIM1_CR1_ARPE ((u8)0x80) /*!< Auto-Reload Preload Enable mask. */ +#define TIM1_CR1_CMS ((u8)0x60) /*!< Center-aligned Mode Selection mask. */ +#define TIM1_CR1_DIR ((u8)0x10) /*!< Direction mask. */ +#define TIM1_CR1_OPM ((u8)0x08) /*!< One Pulse Mode mask. */ +#define TIM1_CR1_URS ((u8)0x04) /*!< Update Request Source mask. */ +#define TIM1_CR1_UDIS ((u8)0x02) /*!< Update DIsable mask. */ +#define TIM1_CR1_CEN ((u8)0x01) /*!< Counter Enable mask. */ +/* CR2*/ +#define TIM1_CR2_TI1S ((u8)0x80) /*!< TI1S Selection mask. */ +#define TIM1_CR2_MMS ((u8)0x70) /*!< MMS Selection mask. */ +#define TIM1_CR2_COMS ((u8)0x04) /*!< Capture/Compare Control Update Selection mask. */ +#define TIM1_CR2_CCPC ((u8)0x01) /*!< Capture/Compare Preloaded Control mask. */ +/* SMCR*/ +#define TIM1_SMCR_MSM ((u8)0x80) /*!< Master/Slave Mode mask. */ +#define TIM1_SMCR_TS ((u8)0x70) /*!< Trigger Selection mask. */ +#define TIM1_SMCR_SMS ((u8)0x07) /*!< Slave Mode Selection mask. */ +/*ETR*/ +#define TIM1_ETR_ETP ((u8)0x80) /*!< External Trigger Polarity mask. */ +#define TIM1_ETR_ECE ((u8)0x40)/*!< External Clock mask. */ +#define TIM1_ETR_ETPS ((u8)0x30) /*!< External Trigger Prescaler mask. */ +#define TIM1_ETR_ETF ((u8)0x0F) /*!< External Trigger Filter mask. */ +/*IER*/ +#define TIM1_IER_BIE ((u8)0x80) /*!< Break Interrupt Enable mask. */ +#define TIM1_IER_TIE ((u8)0x40) /*!< Trigger Interrupt Enable mask. */ +#define TIM1_IER_COMIE ((u8)0x20) /*!< Commutation Interrupt Enable mask.*/ +#define TIM1_IER_CC4IE ((u8)0x10) /*!< Capture/Compare 4 Interrupt Enable mask. */ +#define TIM1_IER_CC3IE ((u8)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */ +#define TIM1_IER_CC2IE ((u8)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ +#define TIM1_IER_CC1IE ((u8)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ +#define TIM1_IER_UIE ((u8)0x01) /*!< Update Interrupt Enable mask. */ +/*SR1*/ +#define TIM1_SR1_BIF ((u8)0x80) /*!< Break Interrupt Flag mask. */ +#define TIM1_SR1_TIF ((u8)0x40) /*!< Trigger Interrupt Flag mask. */ +#define TIM1_SR1_COMIF ((u8)0x20) /*!< Commutation Interrupt Flag mask. */ +#define TIM1_SR1_CC4IF ((u8)0x10) /*!< Capture/Compare 4 Interrupt Flag mask. */ +#define TIM1_SR1_CC3IF ((u8)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */ +#define TIM1_SR1_CC2IF ((u8)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ +#define TIM1_SR1_CC1IF ((u8)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ +#define TIM1_SR1_UIF ((u8)0x01) /*!< Update Interrupt Flag mask. */ +/*SR2*/ +#define TIM1_SR2_CC4OF ((u8)0x10) /*!< Capture/Compare 4 Overcapture Flag mask. */ +#define TIM1_SR2_CC3OF ((u8)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */ +#define TIM1_SR2_CC2OF ((u8)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ +#define TIM1_SR2_CC1OF ((u8)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ +/*EGR*/ +#define TIM1_EGR_BG ((u8)0x80) /*!< Break Generation mask. */ +#define TIM1_EGR_TG ((u8)0x40) /*!< Trigger Generation mask. */ +#define TIM1_EGR_COMG ((u8)0x20) /*!< Capture/Compare Control Update Generation mask. */ +#define TIM1_EGR_CC4G ((u8)0x10) /*!< Capture/Compare 4 Generation mask. */ +#define TIM1_EGR_CC3G ((u8)0x08) /*!< Capture/Compare 3 Generation mask. */ +#define TIM1_EGR_CC2G ((u8)0x04) /*!< Capture/Compare 2 Generation mask. */ +#define TIM1_EGR_CC1G ((u8)0x02) /*!< Capture/Compare 1 Generation mask. */ +#define TIM1_EGR_UG ((u8)0x01) /*!< Update Generation mask. */ +/*CCMR*/ +#define TIM1_CCMR_ICxPSC ((u8)0x0C) /*!< Input Capture x Prescaler mask. */ +#define TIM1_CCMR_ICxF ((u8)0xF0) /*!< Input Capture x Filter mask. */ +#define TIM1_CCMR_OCM ((u8)0x70) /*!< Output Compare x Mode mask. */ +#define TIM1_CCMR_OCxPE ((u8)0x08) /*!< Output Compare x Preload Enable mask. */ +#define TIM1_CCMR_OCxFE ((u8)0x04) /*!< Output Compare x Fast Enable mask. */ +#define TIM1_CCMR_CCxS ((u8)0x03) /*!< Capture/Compare x Selection mask. */ + +#define CCMR_TIxDirect_Set ((u8)0x01) +/*CCER1*/ +#define TIM1_CCER1_CC2NP ((u8)0x80) /*!< Capture/Compare 2 Complementary output Polarity mask. */ +#define TIM1_CCER1_CC2NE ((u8)0x40) /*!< Capture/Compare 2 Complementary output enable mask. */ +#define TIM1_CCER1_CC2P ((u8)0x20) /*!< Capture/Compare 2 output Polarity mask. */ +#define TIM1_CCER1_CC2E ((u8)0x10) /*!< Capture/Compare 2 output enable mask. */ +#define TIM1_CCER1_CC1NP ((u8)0x08) /*!< Capture/Compare 1 Complementary output Polarity mask. */ +#define TIM1_CCER1_CC1NE ((u8)0x04) /*!< Capture/Compare 1 Complementary output enable mask. */ +#define TIM1_CCER1_CC1P ((u8)0x02) /*!< Capture/Compare 1 output Polarity mask. */ +#define TIM1_CCER1_CC1E ((u8)0x01) /*!< Capture/Compare 1 output enable mask. */ +/*CCER2*/ +#define TIM1_CCER2_CC4P ((u8)0x20) /*!< Capture/Compare 4 output Polarity mask. */ +#define TIM1_CCER2_CC4E ((u8)0x10) /*!< Capture/Compare 4 output enable mask. */ +#define TIM1_CCER2_CC3NP ((u8)0x08) /*!< Capture/Compare 3 Complementary output Polarity mask. */ +#define TIM1_CCER2_CC3NE ((u8)0x04) /*!< Capture/Compare 3 Complementary output enable mask. */ +#define TIM1_CCER2_CC3P ((u8)0x02) /*!< Capture/Compare 3 output Polarity mask. */ +#define TIM1_CCER2_CC3E ((u8)0x01) /*!< Capture/Compare 3 output enable mask. */ +/*CNTRH*/ +#define TIM1_CNTRH_CNT ((u8)0xFF) /*!< Counter Value (MSB) mask. */ +/*CNTRL*/ +#define TIM1_CNTRL_CNT ((u8)0xFF) /*!< Counter Value (LSB) mask. */ +/*PSCH*/ +#define TIM1_PSCH_PSC ((u8)0xFF) /*!< Prescaler Value (MSB) mask. */ +/*PSCL*/ +#define TIM1_PSCL_PSC ((u8)0xFF) /*!< Prescaler Value (LSB) mask. */ +/*ARR*/ +#define TIM1_ARRH_ARR ((u8)0xFF) /*!< Autoreload Value (MSB) mask. */ +#define TIM1_ARRL_ARR ((u8)0xFF) /*!< Autoreload Value (LSB) mask. */ +/*RCR*/ +#define TIM1_RCR_REP ((u8)0xFF) /*!< Repetition Counter Value mask. */ +/*CCR1*/ +#define TIM1_CCR1H_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ +#define TIM1_CCR1L_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ +/*CCR2*/ +#define TIM1_CCR2H_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ +#define TIM1_CCR2L_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ +/*CCR3*/ +#define TIM1_CCR3H_CCR3 ((u8)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */ +#define TIM1_CCR3L_CCR3 ((u8)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */ +/*CCR4*/ +#define TIM1_CCR4H_CCR4 ((u8)0xFF) /*!< Capture/Compare 4 Value (MSB) mask. */ +#define TIM1_CCR4L_CCR4 ((u8)0xFF) /*!< Capture/Compare 4 Value (LSB) mask. */ +/*BKR*/ +#define TIM1_BKR_MOE ((u8)0x80) /*!< Main Output Enable mask. */ +#define TIM1_BKR_AOE ((u8)0x40) /*!< Automatic Output Enable mask. */ +#define TIM1_BKR_BKP ((u8)0x20) /*!< Break Polarity mask. */ +#define TIM1_BKR_BKE ((u8)0x10) /*!< Break Enable mask. */ +#define TIM1_BKR_OSSR ((u8)0x08) /*!< Off-State Selection for Run mode mask. */ +#define TIM1_BKR_OSSI ((u8)0x04) /*!< Off-State Selection for Idle mode mask. */ +#define TIM1_BKR_LOCK ((u8)0x03) /*!< Lock Configuration mask. */ +/*DTR*/ +#define TIM1_DTR_DTG ((u8)0xFF) /*!< Dead-Time Generator set-up mask. */ +/*OISR*/ +#define TIM1_OISR_OIS4 ((u8)0x40) /*!< Output Idle state 4 (OC4 output) mask. */ +#define TIM1_OISR_OIS3N ((u8)0x20) /*!< Output Idle state 3 (OC3N output) mask. */ +#define TIM1_OISR_OIS3 ((u8)0x10) /*!< Output Idle state 3 (OC3 output) mask. */ +#define TIM1_OISR_OIS2N ((u8)0x08) /*!< Output Idle state 2 (OC2N output) mask. */ +#define TIM1_OISR_OIS2 ((u8)0x04) /*!< Output Idle state 2 (OC2 output) mask. */ +#define TIM1_OISR_OIS1N ((u8)0x02) /*!< Output Idle state 1 (OC1N output) mask. */ +#define TIM1_OISR_OIS1 ((u8)0x01) /*!< Output Idle state 1 (OC1 output) mask. */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief 16-bit timer (TIM2) + */ + +typedef struct TIM2_struct +{ + vu8 CR1; /*!< control register 1 */ +#if defined STM8S103 + vu8 RESERVED1; /*!< Reserved register */ + vu8 RESERVED2; /*!< Reserved register */ +#endif + vu8 IER; /*!< interrupt enable register */ + vu8 SR1; /*!< status register 1 */ + vu8 SR2; /*!< status register 2 */ + vu8 EGR; /*!< event generation register */ + vu8 CCMR1; /*!< CC mode register 1 */ + vu8 CCMR2; /*!< CC mode register 2 */ + vu8 CCMR3; /*!< CC mode register 3 */ + vu8 CCER1; /*!< CC enable register 1 */ + vu8 CCER2; /*!< CC enable register 2 */ + vu8 CNTRH; /*!< counter high */ + vu8 CNTRL; /*!< counter low */ + vu8 PSCR; /*!< prescaler register */ + vu8 ARRH; /*!< auto-reload register high */ + vu8 ARRL; /*!< auto-reload register low */ + vu8 CCR1H; /*!< capture/compare register 1 high */ + vu8 CCR1L; /*!< capture/compare register 1 low */ + vu8 CCR2H; /*!< capture/compare register 2 high */ + vu8 CCR2L; /*!< capture/compare register 2 low */ + vu8 CCR3H; /*!< capture/compare register 3 high */ + vu8 CCR3L; /*!< capture/compare register 3 low */ +} +TIM2_TypeDef; + +/** @addtogroup TIM2_Registers_Reset_Value + * @{ + */ + +#define TIM2_CR1_RESET_VALUE ((u8)0x00) +#define TIM2_IER_RESET_VALUE ((u8)0x00) +#define TIM2_SR1_RESET_VALUE ((u8)0x00) +#define TIM2_SR2_RESET_VALUE ((u8)0x00) +#define TIM2_EGR_RESET_VALUE ((u8)0x00) +#define TIM2_CCMR1_RESET_VALUE ((u8)0x00) +#define TIM2_CCMR2_RESET_VALUE ((u8)0x00) +#define TIM2_CCMR3_RESET_VALUE ((u8)0x00) +#define TIM2_CCER1_RESET_VALUE ((u8)0x00) +#define TIM2_CCER2_RESET_VALUE ((u8)0x00) +#define TIM2_CNTRH_RESET_VALUE ((u8)0x00) +#define TIM2_CNTRL_RESET_VALUE ((u8)0x00) +#define TIM2_PSCR_RESET_VALUE ((u8)0x00) +#define TIM2_ARRH_RESET_VALUE ((u8)0xFF) +#define TIM2_ARRL_RESET_VALUE ((u8)0xFF) +#define TIM2_CCR1H_RESET_VALUE ((u8)0x00) +#define TIM2_CCR1L_RESET_VALUE ((u8)0x00) +#define TIM2_CCR2H_RESET_VALUE ((u8)0x00) +#define TIM2_CCR2L_RESET_VALUE ((u8)0x00) +#define TIM2_CCR3H_RESET_VALUE ((u8)0x00) +#define TIM2_CCR3L_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup TIM2_Registers_Bits_Definition + * @{ + */ +/*CR1*/ +#define TIM2_CR1_ARPE ((u8)0x80) /*!< Auto-Reload Preload Enable mask. */ +#define TIM2_CR1_OPM ((u8)0x08) /*!< One Pulse Mode mask. */ +#define TIM2_CR1_URS ((u8)0x04) /*!< Update Request Source mask. */ +#define TIM2_CR1_UDIS ((u8)0x02) /*!< Update DIsable mask. */ +#define TIM2_CR1_CEN ((u8)0x01) /*!< Counter Enable mask. */ +/*IER*/ +#define TIM2_IER_CC3IE ((u8)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */ +#define TIM2_IER_CC2IE ((u8)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ +#define TIM2_IER_CC1IE ((u8)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ +#define TIM2_IER_UIE ((u8)0x01) /*!< Update Interrupt Enable mask. */ +/*SR1*/ +#define TIM2_SR1_CC3IF ((u8)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */ +#define TIM2_SR1_CC2IF ((u8)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ +#define TIM2_SR1_CC1IF ((u8)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ +#define TIM2_SR1_UIF ((u8)0x01) /*!< Update Interrupt Flag mask. */ +/*SR2*/ +#define TIM2_SR2_CC3OF ((u8)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */ +#define TIM2_SR2_CC2OF ((u8)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ +#define TIM2_SR2_CC1OF ((u8)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ +/*EGR*/ +#define TIM2_EGR_CC3G ((u8)0x08) /*!< Capture/Compare 3 Generation mask. */ +#define TIM2_EGR_CC2G ((u8)0x04) /*!< Capture/Compare 2 Generation mask. */ +#define TIM2_EGR_CC1G ((u8)0x02) /*!< Capture/Compare 1 Generation mask. */ +#define TIM2_EGR_UG ((u8)0x01) /*!< Update Generation mask. */ +/*CCMR*/ +#define TIM2_CCMR_ICxPSC ((u8)0x0C) /*!< Input Capture x Prescaler mask. */ +#define TIM2_CCMR_ICxF ((u8)0xF0) /*!< Input Capture x Filter mask. */ +#define TIM2_CCMR_OCM ((u8)0x70) /*!< Output Compare x Mode mask. */ +#define TIM2_CCMR_OCxPE ((u8)0x08) /*!< Output Compare x Preload Enable mask. */ +#define TIM2_CCMR_CCxS ((u8)0x03) /*!< Capture/Compare x Selection mask. */ +/*CCER1*/ +#define TIM2_CCER1_CC2P ((u8)0x20) /*!< Capture/Compare 2 output Polarity mask. */ +#define TIM2_CCER1_CC2E ((u8)0x10) /*!< Capture/Compare 2 output enable mask. */ +#define TIM2_CCER1_CC1P ((u8)0x02) /*!< Capture/Compare 1 output Polarity mask. */ +#define TIM2_CCER1_CC1E ((u8)0x01) /*!< Capture/Compare 1 output enable mask. */ +/*CCER2*/ +#define TIM2_CCER2_CC3P ((u8)0x02) /*!< Capture/Compare 3 output Polarity mask. */ +#define TIM2_CCER2_CC3E ((u8)0x01) /*!< Capture/Compare 3 output enable mask. */ +/*CNTR*/ +#define TIM2_CNTRH_CNT ((u8)0xFF) /*!< Counter Value (MSB) mask. */ +#define TIM2_CNTRL_CNT ((u8)0xFF) /*!< Counter Value (LSB) mask. */ +/*PSCR*/ +#define TIM2_PSCR_PSC ((u8)0xFF) /*!< Prescaler Value (MSB) mask. */ +/*ARR*/ +#define TIM2_ARRH_ARR ((u8)0xFF) /*!< Autoreload Value (MSB) mask. */ +#define TIM2_ARRL_ARR ((u8)0xFF) /*!< Autoreload Value (LSB) mask. */ +/*CCR1*/ +#define TIM2_CCR1H_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ +#define TIM2_CCR1L_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ +/*CCR2*/ +#define TIM2_CCR2H_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ +#define TIM2_CCR2L_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ +/*CCR3*/ +#define TIM2_CCR3H_CCR3 ((u8)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */ +#define TIM2_CCR3L_CCR3 ((u8)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief 16-bit timer (TIM3) + */ +typedef struct TIM3_struct +{ + vu8 CR1; /*!< control register 1 */ + vu8 IER; /*!< interrupt enable register */ + vu8 SR1; /*!< status register 1 */ + vu8 SR2; /*!< status register 2 */ + vu8 EGR; /*!< event generation register */ + vu8 CCMR1; /*!< CC mode register 1 */ + vu8 CCMR2; /*!< CC mode register 2 */ + vu8 CCER1; /*!< CC enable register 1 */ + vu8 CNTRH; /*!< counter high */ + vu8 CNTRL; /*!< counter low */ + vu8 PSCR; /*!< prescaler register */ + vu8 ARRH; /*!< auto-reload register high */ + vu8 ARRL; /*!< auto-reload register low */ + vu8 CCR1H; /*!< capture/compare register 1 high */ + vu8 CCR1L; /*!< capture/compare register 1 low */ + vu8 CCR2H; /*!< capture/compare register 2 high */ + vu8 CCR2L; /*!< capture/compare register 2 low */ +} +TIM3_TypeDef; + +/** @addtogroup TIM3_Registers_Reset_Value + * @{ + */ + +#define TIM3_CR1_RESET_VALUE ((u8)0x00) +#define TIM3_IER_RESET_VALUE ((u8)0x00) +#define TIM3_SR1_RESET_VALUE ((u8)0x00) +#define TIM3_SR2_RESET_VALUE ((u8)0x00) +#define TIM3_EGR_RESET_VALUE ((u8)0x00) +#define TIM3_CCMR1_RESET_VALUE ((u8)0x00) +#define TIM3_CCMR2_RESET_VALUE ((u8)0x00) +#define TIM3_CCER1_RESET_VALUE ((u8)0x00) +#define TIM3_CNTRH_RESET_VALUE ((u8)0x00) +#define TIM3_CNTRL_RESET_VALUE ((u8)0x00) +#define TIM3_PSCR_RESET_VALUE ((u8)0x00) +#define TIM3_ARRH_RESET_VALUE ((u8)0xFF) +#define TIM3_ARRL_RESET_VALUE ((u8)0xFF) +#define TIM3_CCR1H_RESET_VALUE ((u8)0x00) +#define TIM3_CCR1L_RESET_VALUE ((u8)0x00) +#define TIM3_CCR2H_RESET_VALUE ((u8)0x00) +#define TIM3_CCR2L_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup TIM3_Registers_Bits_Definition + * @{ + */ +/*CR1*/ +#define TIM3_CR1_ARPE ((u8)0x80) /*!< Auto-Reload Preload Enable mask. */ +#define TIM3_CR1_OPM ((u8)0x08) /*!< One Pulse Mode mask. */ +#define TIM3_CR1_URS ((u8)0x04) /*!< Update Request Source mask. */ +#define TIM3_CR1_UDIS ((u8)0x02) /*!< Update DIsable mask. */ +#define TIM3_CR1_CEN ((u8)0x01) /*!< Counter Enable mask. */ +/*IER*/ +#define TIM3_IER_CC2IE ((u8)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ +#define TIM3_IER_CC1IE ((u8)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ +#define TIM3_IER_UIE ((u8)0x01) /*!< Update Interrupt Enable mask. */ +/*SR1*/ +#define TIM3_SR1_CC2IF ((u8)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ +#define TIM3_SR1_CC1IF ((u8)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ +#define TIM3_SR1_UIF ((u8)0x01) /*!< Update Interrupt Flag mask. */ +/*SR2*/ +#define TIM3_SR2_CC2OF ((u8)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ +#define TIM3_SR2_CC1OF ((u8)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ +/*EGR*/ +#define TIM3_EGR_CC2G ((u8)0x04) /*!< Capture/Compare 2 Generation mask. */ +#define TIM3_EGR_CC1G ((u8)0x02) /*!< Capture/Compare 1 Generation mask. */ +#define TIM3_EGR_UG ((u8)0x01) /*!< Update Generation mask. */ +/*CCMR*/ +#define TIM3_CCMR_ICxPSC ((u8)0x0C) /*!< Input Capture x Prescaler mask. */ +#define TIM3_CCMR_ICxF ((u8)0xF0) /*!< Input Capture x Filter mask. */ +#define TIM3_CCMR_OCM ((u8)0x70) /*!< Output Compare x Mode mask. */ +#define TIM3_CCMR_OCxPE ((u8)0x08) /*!< Output Compare x Preload Enable mask. */ +#define TIM3_CCMR_CCxS ((u8)0x03) /*!< Capture/Compare x Selection mask. */ +/*CCER1*/ +#define TIM3_CCER1_CC2P ((u8)0x20) /*!< Capture/Compare 2 output Polarity mask. */ +#define TIM3_CCER1_CC2E ((u8)0x10) /*!< Capture/Compare 2 output enable mask. */ +#define TIM3_CCER1_CC1P ((u8)0x02) /*!< Capture/Compare 1 output Polarity mask. */ +#define TIM3_CCER1_CC1E ((u8)0x01) /*!< Capture/Compare 1 output enable mask. */ +/*CNTR*/ +#define TIM3_CNTRH_CNT ((u8)0xFF) /*!< Counter Value (MSB) mask. */ +#define TIM3_CNTRL_CNT ((u8)0xFF) /*!< Counter Value (LSB) mask. */ +/*PSCR*/ +#define TIM3_PSCR_PSC ((u8)0xFF) /*!< Prescaler Value (MSB) mask. */ +/*ARR*/ +#define TIM3_ARRH_ARR ((u8)0xFF) /*!< Autoreload Value (MSB) mask. */ +#define TIM3_ARRL_ARR ((u8)0xFF) /*!< Autoreload Value (LSB) mask. */ +/*CCR1*/ +#define TIM3_CCR1H_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ +#define TIM3_CCR1L_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ +/*CCR2*/ +#define TIM3_CCR2H_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ +#define TIM3_CCR2L_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief 8-bit system timer (TIM4) + */ + +typedef struct TIM4_struct +{ + vu8 CR1; /*!< control register 1 */ +#if defined STM8S103 + vu8 RESERVED1; /*!< Reserved register */ + vu8 RESERVED2; /*!< Reserved register */ +#endif + vu8 IER; /*!< interrupt enable register */ + vu8 SR1; /*!< status register 1 */ + vu8 EGR; /*!< event generation register */ + vu8 CNTR; /*!< counter register */ + vu8 PSCR; /*!< prescaler register */ + vu8 ARR; /*!< auto-reload register */ +} +TIM4_TypeDef; + +/** @addtogroup TIM4_Registers_Reset_Value + * @{ + */ + +#define TIM4_CR1_RESET_VALUE ((u8)0x00) +#define TIM4_IER_RESET_VALUE ((u8)0x00) +#define TIM4_SR1_RESET_VALUE ((u8)0x00) +#define TIM4_EGR_RESET_VALUE ((u8)0x00) +#define TIM4_CNTR_RESET_VALUE ((u8)0x00) +#define TIM4_PSCR_RESET_VALUE ((u8)0x00) +#define TIM4_ARR_RESET_VALUE ((u8)0xFF) + +/** + * @} + */ + +/** @addtogroup TIM4_Registers_Bits_Definition + * @{ + */ +/*CR1*/ +#define TIM4_CR1_ARPE ((u8)0x80) /*!< Auto-Reload Preload Enable mask. */ +#define TIM4_CR1_OPM ((u8)0x08) /*!< One Pulse Mode mask. */ +#define TIM4_CR1_URS ((u8)0x04) /*!< Update Request Source mask. */ +#define TIM4_CR1_UDIS ((u8)0x02) /*!< Update DIsable mask. */ +#define TIM4_CR1_CEN ((u8)0x01) /*!< Counter Enable mask. */ +/*IER*/ +#define TIM4_IER_UIE ((u8)0x01) /*!< Update Interrupt Enable mask. */ +/*SR1*/ +#define TIM4_SR1_UIF ((u8)0x01) /*!< Update Interrupt Flag mask. */ +/*EGR*/ +#define TIM4_EGR_UG ((u8)0x01) /*!< Update Generation mask. */ +/*CNTR*/ +#define TIM4_CNTR_CNT ((u8)0xFF) /*!< Counter Value (LSB) mask. */ +/*PSCR*/ +#define TIM4_PSCR_PSC ((u8)0x07) /*!< Prescaler Value mask. */ +/*ARR*/ +#define TIM4_ARR_ARR ((u8)0xFF) /*!< Autoreload Value mask. */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief 16-bit timer with synchro module (TIM5) + */ + +typedef struct TIM5_struct +{ + vu8 CR1; /*! + #define enableInterrupts() _rim_() /* enable interrupts */ + #define disableInterrupts() _sim_() /* disable interrupts */ + #define rim() _rim_() /* enable interrupts */ + #define sim() _sim_() /* disable interrupts */ + #define nop() _nop_() /* No Operation */ + #define trap() _trap_() /* Trap (soft IT) */ + #define wfi() _wfi_() /* Wait For Interrupt */ + #define halt() _halt_() /* Halt */ +#else /* COSMIC */ + #define enableInterrupts() {_asm("rim\n");} /* enable interrupts */ + #define disableInterrupts() {_asm("sim\n");} /* disable interrupts */ + #define rim() {_asm("rim\n");} /* enable interrupts */ + #define sim() {_asm("sim\n");} /* disable interrupts */ + #define nop() {_asm("nop\n");} /* No Operation */ + #define trap() {_asm("trap\n");} /* Trap (soft IT) */ + #define wfi() {_asm("wfi\n");} /* Wait For Interrupt */ + #define halt() {_asm("halt\n");} /* Halt */ +#endif + +/*============================== Handling bits ====================================*/ +/*----------------------------------------------------------------------------- +Method : I +Description : Handle the bit from the character variables. +Comments : The different parameters of commands are + - VAR : Name of the character variable where the bit is located. + - Place : Bit position in the variable (7 6 5 4 3 2 1 0) + - Value : Can be 0 (reset bit) or not 0 (set bit) + The "MskBit" command allows to select some bits in a source + variables and copy it in a destination var (return the value). + The "ValBit" command returns the value of a bit in a char + variable: the bit is reseted if it returns 0 else the bit is set. + This method generates not an optimised code yet. +-----------------------------------------------------------------------------*/ +#define SetBit(VAR,Place) ( (VAR) |= (u8)((u8)1<<(u8)(Place)) ) +#define ClrBit(VAR,Place) ( (VAR) &= (u8)((u8)((u8)1<<(u8)(Place))^(u8)255) ) + +#define ChgBit(VAR,Place) ( (VAR) ^= (u8)((u8)1<<(u8)(Place)) ) +#define AffBit(VAR,Place,Value) ((Value) ? \ + ((VAR) |= ((u8)1<<(Place))) : \ + ((VAR) &= (((u8)1<<(Place))^(u8)255))) +#define MskBit(Dest,Msk,Src) ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) ) + +#define ValBit(VAR,Place) ((u8)(VAR) & (u8)((u8)1<<(u8)(Place))) + +#define BYTE_0(n) ((u8)((n) & (u8)0xFF)) /*!< Returns the low byte of the 32-bit value */ +#define BYTE_1(n) ((u8)(BYTE_0((n) >> (u8)8))) /*!< Returns the second byte of the 32-bit value */ +#define BYTE_2(n) ((u8)(BYTE_0((n) >> (u8)16))) /*!< Returns the third byte of the 32-bit value */ +#define BYTE_3(n) ((u8)(BYTE_0((n) >> (u8)24))) /*!< Returns the high byte of the 32-bit value */ + +/*============================== Assert Macros ====================================*/ +#define IS_STATE_VALUE_OK(SensitivityValue) \ + (((SensitivityValue) == ENABLE) || \ + ((SensitivityValue) == DISABLE)) + +/*----------------------------------------------------------------------------- +Method : II +Description : Handle directly the bit. +Comments : The idea is to handle directly with the bit name. For that, it is + necessary to have RAM area descriptions (example: HW register...) + and the following command line for each area. + This method generates the most optimized code. +-----------------------------------------------------------------------------*/ + +#define AREA 0x00 /* The area of bits begins at address 0x10. */ + +#define BitClr(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) ) +#define BitSet(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) ) +#define BitVal(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) ) + +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM8S_H */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/Project/os/hal/platforms/STM8S/stm8s_type.h b/Project/os/hal/platforms/STM8S/stm8s_type.h new file mode 100644 index 0000000..5c80f66 --- /dev/null +++ b/Project/os/hal/platforms/STM8S/stm8s_type.h @@ -0,0 +1,103 @@ +/** + ****************************************************************************** + * @file stm8s_type.h + * @brief This file contains all common data types. + * @author STMicroelectronics - MCD Application Team + * @version V1.1.1 + * @date 06/05/2009 + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ * @image html logo.bmp + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM8S_TYPE_H +#define __STM8S_TYPE_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +typedef signed long s32; +typedef signed short s16; +typedef signed char s8; + +typedef signed long const sc32; /* Read Only */ +typedef signed short const sc16; /* Read Only */ +typedef signed char const sc8; /* Read Only */ + +typedef volatile signed long vs32; +typedef volatile signed short vs16; +typedef volatile signed char vs8; + +typedef volatile signed long const vsc32; /* Read Only */ +typedef volatile signed short const vsc16; /* Read Only */ +typedef volatile signed char const vsc8; /* Read Only */ + +typedef unsigned long u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef unsigned long const uc32; /* Read Only */ +typedef unsigned short const uc16; /* Read Only */ +typedef unsigned char const uc8; /* Read Only */ + +typedef volatile unsigned long vu32; +typedef volatile unsigned short vu16; +typedef volatile unsigned char vu8; + +typedef volatile unsigned long const vuc32; /* Read Only */ +typedef volatile unsigned short const vuc16; /* Read Only */ +typedef volatile unsigned char const vuc8; /* Read Only */ + +typedef enum +{ + FALSE = 0, + TRUE = !FALSE +} +bool; + +typedef enum { + RESET = 0, + SET = !RESET +} +FlagStatus, ITStatus, BitStatus; + +typedef enum { + DISABLE = 0, + ENABLE = !DISABLE +} +FunctionalState; + +#define IS_FUNCTIONALSTATE_OK(VALUE) ( (VALUE == ENABLE) || (VALUE == DISABLE) ) + +typedef enum { + ERROR = 0, + SUCCESS = !ERROR +} +ErrorStatus; + +#define U8_MAX ((u8)255) +#define S8_MAX ((s8)127) +#define S8_MIN ((s8)-128) +#define U16_MAX ((u16)65535u) +#define S16_MAX ((s16)32767) +#define S16_MIN ((s16)-32768) +#define U32_MAX ((u32)4294967295uL) +#define S32_MAX ((s32)2147483647) +#define S32_MIN ((s32)-2147483648) + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM8S_TYPE_H */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/Project/os/hal/platforms/Win32/console.c b/Project/os/hal/platforms/Win32/console.c new file mode 100644 index 0000000..cac93d9 --- /dev/null +++ b/Project/os/hal/platforms/Win32/console.c @@ -0,0 +1,134 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file console.c + * @brief Simulator console driver code. + * @{ + */ + +#include + +#include "ch.h" +#include "console.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief Console driver 1. + */ +BaseChannel CD1; + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + + +static size_t writes(void *ip, const uint8_t *bp, size_t n) { + size_t ret; + + (void)ip; + ret = fwrite(bp, 1, n, stdout); + fflush(stdout); + return ret; +} + +static size_t reads(void *ip, uint8_t *bp, size_t n) { + + (void)ip; + return fread(bp, 1, n, stdin); +} + +static bool_t putwouldblock(void *ip) { + + (void)ip; + return FALSE; +} + +static bool_t getwouldblock(void *ip) { + + (void)ip; + return TRUE; +} + +static msg_t putt(void *ip, uint8_t b, systime_t time) { + + (void)ip; + (void)time; + fputc(b, stdout); + fflush(stdout); + return RDY_OK; +} + +static msg_t gett(void *ip, systime_t time) { + + (void)ip; + (void)time; + return fgetc(stdin); +} + +static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t time) { + size_t ret; + + (void)ip; + (void)time; + ret = fwrite(bp, 1, n, stdout); + fflush(stdout); + return ret; +} + +static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t time) { + + (void)ip; + (void)time; + return fread(bp, 1, n, stdin); +} + +static const struct BaseChannelVMT vmt = { + writes, reads, putwouldblock, getwouldblock, putt, gett, writet, readt +}; + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +void conInit(void) { + + CD1.vmt = &vmt; +} + +/** @} */ diff --git a/Project/os/hal/platforms/Win32/console.h b/Project/os/hal/platforms/Win32/console.h new file mode 100644 index 0000000..49d2710 --- /dev/null +++ b/Project/os/hal/platforms/Win32/console.h @@ -0,0 +1,73 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file console.h + * @brief Simulator console driver header. + * @{ + */ + +#ifndef _CONSOLE_H_ +#define _CONSOLE_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern BaseChannel CD1; + +#ifdef __cplusplus +extern "C" { +#endif + void conInit(void); +#ifdef __cplusplus +} +#endif + +#endif /* _CONSOLE_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/Win32/hal_lld.c b/Project/os/hal/platforms/Win32/hal_lld.c new file mode 100644 index 0000000..bbdce05 --- /dev/null +++ b/Project/os/hal/platforms/Win32/hal_lld.c @@ -0,0 +1,121 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file Win32/hal_lld.c + * @brief Win32 HAL subsystem low level driver code. + * @addtogroup WIN32_HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +static LARGE_INTEGER nextcnt; +static LARGE_INTEGER slice; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + */ +void hal_lld_init(void) { + WSADATA wsaData; + + /* Initialization.*/ + if (WSAStartup(2, &wsaData) != 0) { + printf("Unable to locate a winsock DLL\n"); + exit(1); + } + + printf("ChibiOS/RT simulator (Win32)\n"); + if (!QueryPerformanceFrequency(&slice)) { + printf("QueryPerformanceFrequency() error"); + exit(1); + } + slice.QuadPart /= CH_FREQUENCY; + QueryPerformanceCounter(&nextcnt); + nextcnt.QuadPart += slice.QuadPart; + + fflush(stdout); +} + +/** + * @brief Interrupt simulation. + */ +void ChkIntSources(void) { + LARGE_INTEGER n; + +#if HAL_USE_SERIAL + if (sd_lld_interrupt_pending()) { + dbg_check_lock(); + if (chSchIsPreemptionRequired()) + chSchDoReschedule(); + dbg_check_unlock(); + return; + } +#endif + + /* Interrupt Timer simulation (10ms interval).*/ + QueryPerformanceCounter(&n); + if (n.QuadPart > nextcnt.QuadPart) { + nextcnt.QuadPart += slice.QuadPart; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); + + dbg_check_lock(); + if (chSchIsPreemptionRequired()) + chSchDoReschedule(); + dbg_check_unlock(); + } +} + +/** @} */ diff --git a/Project/os/hal/platforms/Win32/hal_lld.h b/Project/os/hal/platforms/Win32/hal_lld.h new file mode 100644 index 0000000..45a4bb6 --- /dev/null +++ b/Project/os/hal/platforms/Win32/hal_lld.h @@ -0,0 +1,83 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file Win32/hal_lld.h + * @brief WIN32 simulator HAL subsystem low level driver header. + * + * @addtogroup WIN32_HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include +#include + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "Win32" + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void ChkIntSources(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/Win32/pal_lld.c b/Project/os/hal/platforms/Win32/pal_lld.c new file mode 100644 index 0000000..baacb3f --- /dev/null +++ b/Project/os/hal/platforms/Win32/pal_lld.c @@ -0,0 +1,106 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file Win32/pal_lld.c + * @brief Win32 low level simulated PAL driver code. + * + * @addtogroup WIN32_PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief VIO1 simulated port. + */ +sim_vio_port_t vio_port_1; + +/** + * @brief VIO2 simulated port. + */ +sim_vio_port_t vio_port_2; + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @note This function is not meant to be invoked directly by the application + * code. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with high + * state. + * @note This function does not alter the @p PINSELx registers. Alternate + * functions setup must be handled by device-specific code. + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + port->dir &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + port->latch |= mask; + case PAL_MODE_OUTPUT_PUSHPULL: + port->dir |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/Win32/pal_lld.h b/Project/os/hal/platforms/Win32/pal_lld.h new file mode 100644 index 0000000..3d9a87e --- /dev/null +++ b/Project/os/hal/platforms/Win32/pal_lld.h @@ -0,0 +1,217 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file Win32/pal_lld.h + * @brief Win32 low level simulated PAL driver header. + * + * @addtogroup WIN32_PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_OUTPUT_OPENDRAIN +#undef PAL_MODE_INPUT_ANALOG + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief VIO port structure. + */ +typedef struct { + /** + * @brief VIO_LATCH register. + * @details This register represents the output latch of the VIO port. + */ + uint32_t latch; + /** + * @brief VIO_PIN register. + * @details This register represents the logical level at the VIO port + * pin level. + */ + uint32_t pin; + /** + * @brief VIO_DIR register. + * @details Direction of the VIO port bits, 0=input, 1=output. + */ + uint32_t dir; +} sim_vio_port_t; + +/** + * @brief Virtual I/O ports static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { + /** + * @brief Virtual port 1 setup data. + */ + sim_vio_port_t VP1Data; + /** + * @brief Virtual port 2 setup data. + */ + sim_vio_port_t VP2Data; +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 32 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + */ +typedef sim_vio_port_t *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief VIO port 1 identifier. + */ +#define IOPORT1 (&vio_port_1) + +/** + * @brief VIO port 2 identifier. + */ +#define IOPORT2 (&vio_port_2) + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) \ + (vio_port_1 = (config)->VP1Data, \ + vio_port_2 = (config)->VP2Data) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->pin) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->latch) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->latch = (bits)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +#if !defined(__DOXYGEN__) +extern sim_vio_port_t vio_port_1; +extern sim_vio_port_t vio_port_2; +extern const PALConfig pal_default_config; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/Win32/platform.mk b/Project/os/hal/platforms/Win32/platform.mk new file mode 100644 index 0000000..0887c1a --- /dev/null +++ b/Project/os/hal/platforms/Win32/platform.mk @@ -0,0 +1,7 @@ +# List of all the Win32 platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/Win32/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/Win32/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/Win32/serial_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/Win32 diff --git a/Project/os/hal/platforms/Win32/serial_lld.c b/Project/os/hal/platforms/Win32/serial_lld.c new file mode 100644 index 0000000..88b0afb --- /dev/null +++ b/Project/os/hal/platforms/Win32/serial_lld.c @@ -0,0 +1,289 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file Win32/serial_lld.c + * @brief Win32 low level simulated serial driver code. + * @addtogroup WIN32_SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief Serial driver 1 identifier.*/ +#if USE_WIN32_SERIAL1 || defined(__DOXYGEN__) +SerialDriver SD1; +#endif +/** @brief Serial driver 2 identifier.*/ +#if USE_WIN32_SERIAL2 || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = { +}; + +static u_long nb = 1; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void init(SerialDriver *sdp, uint16_t port) { + struct sockaddr_in sad; + struct protoent *prtp; + + if ((prtp = getprotobyname("tcp")) == NULL) { + printf("%s: Error mapping protocol name to protocol number\n", sdp->com_name); + goto abort; + } + + sdp->com_listen = socket(PF_INET, SOCK_STREAM, prtp->p_proto); + if (sdp->com_listen == INVALID_SOCKET) { + printf("%s: Error creating simulator socket\n", sdp->com_name); + goto abort; + } + + if (ioctlsocket(sdp->com_listen, FIONBIO, &nb) != 0) { + printf("%s: Unable to setup non blocking mode on socket\n", sdp->com_name); + goto abort; + } + + memset(&sad, 0, sizeof(sad)); + sad.sin_family = AF_INET; + sad.sin_addr.s_addr = INADDR_ANY; + sad.sin_port = htons(port); + if (bind(sdp->com_listen, (struct sockaddr *)&sad, sizeof(sad))) { + printf("%s: Error binding socket\n", sdp->com_name); + goto abort; + } + + if (listen(sdp->com_listen, 1) != 0) { + printf("%s: Error listening socket\n", sdp->com_name); + goto abort; + } + printf("Full Duplex Channel %s listening on port %d\n", sdp->com_name, port); + return; + +abort: + if (sdp->com_listen != INVALID_SOCKET) + closesocket(sdp->com_listen); + WSACleanup(); + exit(1); +} + +static bool_t connint(SerialDriver *sdp) { + + if (sdp->com_data == INVALID_SOCKET) { + struct sockaddr addr; + int addrlen = sizeof(addr); + + if ((sdp->com_data = accept(sdp->com_listen, &addr, &addrlen)) == INVALID_SOCKET) + return FALSE; + + if (ioctlsocket(sdp->com_data, FIONBIO, &nb) != 0) { + printf("%s: Unable to setup non blocking mode on data socket\n", sdp->com_name); + goto abort; + } + chSysLockFromIsr(); + chIOAddFlagsI(sdp, IO_CONNECTED); + chSysUnlockFromIsr(); + return TRUE; + } + return FALSE; +abort: + if (sdp->com_listen != INVALID_SOCKET) + closesocket(sdp->com_listen); + if (sdp->com_data != INVALID_SOCKET) + closesocket(sdp->com_data); + WSACleanup(); + exit(1); +} + +static bool_t inint(SerialDriver *sdp) { + + if (sdp->com_data != INVALID_SOCKET) { + int i; + uint8_t data[32]; + + /* + * Input. + */ + int n = recv(sdp->com_data, data, sizeof(data), 0); + switch (n) { + case 0: + closesocket(sdp->com_data); + sdp->com_data = INVALID_SOCKET; + chSysLockFromIsr(); + chIOAddFlagsI(sdp, IO_DISCONNECTED); + chSysUnlockFromIsr(); + return FALSE; + case SOCKET_ERROR: + if (WSAGetLastError() == WSAEWOULDBLOCK) + return FALSE; + closesocket(sdp->com_data); + sdp->com_data = INVALID_SOCKET; + return FALSE; + } + for (i = 0; i < n; i++) { + chSysLockFromIsr(); + sdIncomingDataI(sdp, data[i]); + chSysUnlockFromIsr(); + } + return TRUE; + } + return FALSE; +} + +static bool_t outint(SerialDriver *sdp) { + + if (sdp->com_data != INVALID_SOCKET) { + int n; + uint8_t data[1]; + + /* + * Input. + */ + chSysLockFromIsr(); + n = sdRequestDataI(sdp); + chSysUnlockFromIsr(); + if (n < 0) + return FALSE; + data[0] = (uint8_t)n; + n = send(sdp->com_data, data, sizeof(data), 0); + switch (n) { + case 0: + closesocket(sdp->com_data); + sdp->com_data = INVALID_SOCKET; + chSysLockFromIsr(); + chIOAddFlagsI(sdp, IO_DISCONNECTED); + chSysUnlockFromIsr(); + return FALSE; + case SOCKET_ERROR: + if (WSAGetLastError() == WSAEWOULDBLOCK) + return FALSE; + closesocket(sdp->com_data); + sdp->com_data = INVALID_SOCKET; + return FALSE; + } + return TRUE; + } + return FALSE; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * Low level serial driver initialization. + */ +void sd_lld_init(void) { + +#if USE_WIN32_SERIAL1 + sdObjectInit(&SD1, NULL, NULL); + SD1.com_listen = INVALID_SOCKET; + SD1.com_data = INVALID_SOCKET; + SD1.com_name = "SD1"; +#endif + +#if USE_WIN32_SERIAL1 + sdObjectInit(&SD2, NULL, NULL); + SD2.com_listen = INVALID_SOCKET; + SD2.com_data = INVALID_SOCKET; + SD2.com_name = "SD2"; +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + +#if USE_WIN32_SERIAL1 + if (sdp == &SD1) + init(&SD1, SD1_PORT); +#endif + +#if USE_WIN32_SERIAL1 + if (sdp == &SD2) + init(&SD2, SD2_PORT); +#endif +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + */ +void sd_lld_stop(SerialDriver *sdp) { + + (void)sdp; +} + +bool_t sd_lld_interrupt_pending(void) { + bool_t b; + + CH_IRQ_PROLOGUE(); + + b = connint(&SD1) || connint(&SD2) || + inint(&SD1) || inint(&SD2) || + outint(&SD1) || outint(&SD2); + + CH_IRQ_EPILOGUE(); + + return b; +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/Project/os/hal/platforms/Win32/serial_lld.h b/Project/os/hal/platforms/Win32/serial_lld.h new file mode 100644 index 0000000..aca87b6 --- /dev/null +++ b/Project/os/hal/platforms/Win32/serial_lld.h @@ -0,0 +1,154 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file Win32/serial_lld.h + * @brief Win32 low level simulated serial driver header. + * + * @addtogroup WIN32_SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 1024 +#endif + +/** + * @brief SD1 driver enable switch. + * @details If set to @p TRUE the support for SD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_WIN32_SERIAL1) || defined(__DOXYGEN__) +#define USE_WIN32_SERIAL1 TRUE +#endif + +/** + * @brief SD2 driver enable switch. + * @details If set to @p TRUE the support for SD2 is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_WIN32_SERIAL2) || defined(__DOXYGEN__) +#define USE_WIN32_SERIAL2 TRUE +#endif + +/** + * @brief Listen port for SD1. + */ +#if !defined(SD1_PORT) || defined(__DOXYGEN__) +#define SD1_PORT 29001 +#endif + +/** + * @brief Listen port for SD2. + */ +#if !defined(SD2_PORT) || defined(__DOXYGEN__) +#define SD2_PORT 29002 +#endif + +/*===========================================================================*/ +/* Unsupported event flags and custom events. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Generic Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct { +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Listen socket for simulated serial port.*/ \ + SOCKET com_listen; \ + /* Data socket for simulated serial port.*/ \ + SOCKET com_data; \ + /* Port readable name.*/ \ + const char *com_name; + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if USE_WIN32_SERIAL1 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if USE_WIN32_SERIAL2 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); + bool_t sd_lld_interrupt_pending(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/platforms/platforms.dox b/Project/os/hal/platforms/platforms.dox new file mode 100644 index 0000000..3ba56d5 --- /dev/null +++ b/Project/os/hal/platforms/platforms.dox @@ -0,0 +1,35 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup platforms Platforms + * @brief Supported platforms. + * @details The implementation of the device drivers can be slightly different + * on the various platforms because architectural constrains. This section + * describes the implementation of the various device drivers on the various + * supported platforms. + */ diff --git a/Project/os/hal/src/adc.c b/Project/os/hal/src/adc.c new file mode 100644 index 0000000..8f396ca --- /dev/null +++ b/Project/os/hal/src/adc.c @@ -0,0 +1,350 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file adc.c + * @brief ADC Driver code. + * + * @addtogroup ADC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief ADC Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void adcInit(void) { + + adc_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p ADCDriver structure. + * + * @param[out] adcp pointer to the @p ADCDriver object + * + * @init + */ +void adcObjectInit(ADCDriver *adcp) { + + adcp->state = ADC_STOP; + adcp->config = NULL; + adcp->samples = NULL; + adcp->depth = 0; + adcp->grpp = NULL; +#if ADC_USE_WAIT + adcp->thread = NULL; +#endif /* ADC_USE_WAIT */ +#if ADC_USE_MUTUAL_EXCLUSION +#if CH_USE_MUTEXES + chMtxInit(&adcp->mutex); +#else + chSemInit(&adcp->semaphore, 1); +#endif +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_INIT_HOOK) + ADC_DRIVER_EXT_INIT_HOOK(adcp); +#endif +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] config pointer to the @p ADCConfig object. Depending on + * the implementation the value can be @p NULL. + * + * @api + */ +void adcStart(ADCDriver *adcp, const ADCConfig *config) { + + chDbgCheck(adcp != NULL, "adcStart"); + + chSysLock(); + chDbgAssert((adcp->state == ADC_STOP) || (adcp->state == ADC_READY), + "adcStart(), #1", "invalid state"); + adcp->config = config; + adc_lld_start(adcp); + adcp->state = ADC_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @api + */ +void adcStop(ADCDriver *adcp) { + + chDbgCheck(adcp != NULL, "adcStop"); + + chSysLock(); + chDbgAssert((adcp->state == ADC_STOP) || (adcp->state == ADC_READY), + "adcStop(), #1", "invalid state"); + adc_lld_stop(adcp); + adcp->state = ADC_STOP; + chSysUnlock(); +} + +/** + * @brief Starts an ADC conversion. + * @details Starts an asynchronous conversion operation. + * @note The buffer is organized as a matrix of M*N elements where M is the + * channels number configured into the conversion group and N is the + * buffer depth. The samples are sequentially written into the buffer + * with no gaps. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] grpp pointer to a @p ADCConversionGroup object + * @param[out] samples pointer to the samples buffer + * @param[in] depth buffer depth (matrix rows number). The buffer depth + * must be one or an even number. + * + * @api + */ +void adcStartConversion(ADCDriver *adcp, + const ADCConversionGroup *grpp, + adcsample_t *samples, + size_t depth) { + + chSysLock(); + adcStartConversionI(adcp, grpp, samples, depth); + chSysUnlock(); +} + +/** + * @brief Starts an ADC conversion. + * @details Starts an asynchronous conversion operation. + * @post The callbacks associated to the conversion group will be invoked + * on buffer fill and error events. + * @note The buffer is organized as a matrix of M*N elements where M is the + * channels number configured into the conversion group and N is the + * buffer depth. The samples are sequentially written into the buffer + * with no gaps. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] grpp pointer to a @p ADCConversionGroup object + * @param[out] samples pointer to the samples buffer + * @param[in] depth buffer depth (matrix rows number). The buffer depth + * must be one or an even number. + * + * @iclass + */ +void adcStartConversionI(ADCDriver *adcp, + const ADCConversionGroup *grpp, + adcsample_t *samples, + size_t depth) { + + chDbgCheckClassI(); + chDbgCheck((adcp != NULL) && (grpp != NULL) && (samples != NULL) && + ((depth == 1) || ((depth & 1) == 0)), + "adcStartConversionI"); + chDbgAssert((adcp->state == ADC_READY) || + (adcp->state == ADC_COMPLETE) || + (adcp->state == ADC_ERROR), + "adcStartConversionI(), #1", "not ready"); + + adcp->samples = samples; + adcp->depth = depth; + adcp->grpp = grpp; + adcp->state = ADC_ACTIVE; + adc_lld_start_conversion(adcp); +} + +/** + * @brief Stops an ongoing conversion. + * @details This function stops the currently ongoing conversion and returns + * the driver in the @p ADC_READY state. If there was no conversion + * being processed then the function does nothing. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @api + */ +void adcStopConversion(ADCDriver *adcp) { + + chDbgCheck(adcp != NULL, "adcStopConversion"); + + chSysLock(); + chDbgAssert((adcp->state == ADC_READY) || + (adcp->state == ADC_ACTIVE), + "adcStopConversion(), #1", "invalid state"); + if (adcp->state != ADC_READY) { + adc_lld_stop_conversion(adcp); + adcp->grpp = NULL; + adcp->state = ADC_READY; + _adc_reset_s(adcp); + } + chSysUnlock(); +} + +/** + * @brief Stops an ongoing conversion. + * @details This function stops the currently ongoing conversion and returns + * the driver in the @p ADC_READY state. If there was no conversion + * being processed then the function does nothing. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @iclass + */ +void adcStopConversionI(ADCDriver *adcp) { + + chDbgCheckClassI(); + chDbgCheck(adcp != NULL, "adcStopConversionI"); + chDbgAssert((adcp->state == ADC_READY) || + (adcp->state == ADC_ACTIVE) || + (adcp->state == ADC_COMPLETE), + "adcStopConversionI(), #1", "invalid state"); + + if (adcp->state != ADC_READY) { + adc_lld_stop_conversion(adcp); + adcp->grpp = NULL; + adcp->state = ADC_READY; + _adc_reset_i(adcp); + } +} + +#if ADC_USE_WAIT || defined(__DOXYGEN__) +/** + * @brief Performs an ADC conversion. + * @details Performs a synchronous conversion operation. + * @note The buffer is organized as a matrix of M*N elements where M is the + * channels number configured into the conversion group and N is the + * buffer depth. The samples are sequentially written into the buffer + * with no gaps. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] grpp pointer to a @p ADCConversionGroup object + * @param[out] samples pointer to the samples buffer + * @param[in] depth buffer depth (matrix rows number). The buffer depth + * must be one or an even number. + * @return The operation result. + * @retval RDY_OK Conversion finished. + * @retval RDY_RESET The conversion has been stopped using + * @p acdStopConversion() or @p acdStopConversionI(), + * the result buffer may contain incorrect data. + * @retval RDY_TIMEOUT The conversion has been stopped because an hardware + * error. + * + * @api + */ +msg_t adcConvert(ADCDriver *adcp, + const ADCConversionGroup *grpp, + adcsample_t *samples, + size_t depth) { + msg_t msg; + + chSysLock(); + chDbgAssert(adcp->thread == NULL, "adcConvert(), #1", "already waiting"); + adcStartConversionI(adcp, grpp, samples, depth); + (adcp)->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + msg = chThdSelf()->p_u.rdymsg; + chSysUnlock(); + return msg; +} +#endif /* ADC_USE_WAIT */ + +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +/** + * @brief Gains exclusive access to the ADC peripheral. + * @details This function tries to gain ownership to the ADC bus, if the bus + * is already being used then the invoking thread is queued. + * @pre In order to use this function the option + * @p ADC_USE_MUTUAL_EXCLUSION must be enabled. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @api + */ +void adcAcquireBus(ADCDriver *adcp) { + + chDbgCheck(adcp != NULL, "adcAcquireBus"); + +#if CH_USE_MUTEXES + chMtxLock(&adcp->mutex); +#elif CH_USE_SEMAPHORES + chSemWait(&adcp->semaphore); +#endif +} + +/** + * @brief Releases exclusive access to the ADC peripheral. + * @pre In order to use this function the option + * @p ADC_USE_MUTUAL_EXCLUSION must be enabled. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @api + */ +void adcReleaseBus(ADCDriver *adcp) { + + chDbgCheck(adcp != NULL, "adcReleaseBus"); + +#if CH_USE_MUTEXES + (void)adcp; + chMtxUnlock(); +#elif CH_USE_SEMAPHORES + chSemSignal(&adcp->semaphore); +#endif +} +#endif /* ADC_USE_MUTUAL_EXCLUSION */ + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/Project/os/hal/src/can.c b/Project/os/hal/src/can.c new file mode 100644 index 0000000..4f969a8 --- /dev/null +++ b/Project/os/hal/src/can.c @@ -0,0 +1,302 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file can.c + * @brief CAN Driver code. + * + * @addtogroup CAN + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_CAN || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief CAN Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void canInit(void) { + + can_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p CANDriver structure. + * + * @param[out] canp pointer to the @p CANDriver object + * + * @init + */ +void canObjectInit(CANDriver *canp) { + + canp->state = CAN_STOP; + canp->config = NULL; + chSemInit(&canp->txsem, 0); + chSemInit(&canp->rxsem, 0); + chEvtInit(&canp->rxfull_event); + chEvtInit(&canp->txempty_event); + chEvtInit(&canp->error_event); + canp->status = 0; +#if CAN_USE_SLEEP_MODE + chEvtInit(&canp->sleep_event); + chEvtInit(&canp->wakeup_event); +#endif /* CAN_USE_SLEEP_MODE */ +} + +/** + * @brief Configures and activates the CAN peripheral. + * @note Activating the CAN bus can be a slow operation this this function + * is not atomic, it waits internally for the initialization to + * complete. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] config pointer to the @p CANConfig object. Depending on + * the implementation the value can be @p NULL. + * + * @api + */ +void canStart(CANDriver *canp, const CANConfig *config) { + + chDbgCheck(canp != NULL, "canStart"); + + chSysLock(); + chDbgAssert((canp->state == CAN_STOP) || + (canp->state == CAN_STARTING) || + (canp->state == CAN_READY), + "canStart(), #1", "invalid state"); + while (canp->state == CAN_STARTING) + chThdSleepS(1); + if (canp->state == CAN_STOP) { + canp->config = config; + can_lld_start(canp); + canp->state = CAN_READY; + } + chSysUnlock(); +} + +/** + * @brief Deactivates the CAN peripheral. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @api + */ +void canStop(CANDriver *canp) { + + chDbgCheck(canp != NULL, "canStop"); + + chSysLock(); + chDbgAssert((canp->state == CAN_STOP) || (canp->state == CAN_READY), + "canStop(), #1", "invalid state"); + can_lld_stop(canp); + chSemResetI(&canp->rxsem, 0); + chSemResetI(&canp->txsem, 0); + chSchRescheduleS(); + canp->state = CAN_STOP; + canp->status = 0; + chSysUnlock(); +} + +/** + * @brief Can frame transmission. + * @details The specified frame is queued for transmission, if the hardware + * queue is full then the invoking thread is queued. + * @note Trying to transmit while in sleep mode simply enqueues the thread. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] ctfp pointer to the CAN frame to be transmitted + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation result. + * @retval RDY_OK the frame has been queued for transmission. + * @retval RDY_TIMEOUT The operation has timed out. + * @retval RDY_RESET The driver has been stopped while waiting. + * + * @api + */ +msg_t canTransmit(CANDriver *canp, const CANTxFrame *ctfp, systime_t timeout) { + + chDbgCheck((canp != NULL) && (ctfp != NULL), "canTransmit"); + + chSysLock(); + chDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP), + "canTransmit(), #1", "invalid state"); + while ((canp->state == CAN_SLEEP) || !can_lld_can_transmit(canp)) { + msg_t msg = chSemWaitTimeoutS(&canp->txsem, timeout); + if (msg != RDY_OK) { + chSysUnlock(); + return msg; + } + } + can_lld_transmit(canp, ctfp); + chSysUnlock(); + return RDY_OK; +} + +/** + * @brief Can frame receive. + * @details The function waits until a frame is received. + * @note Trying to receive while in sleep mode simply enqueues the thread. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[out] crfp pointer to the buffer where the CAN frame is copied + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout (useful in an + * event driven scenario where a thread never blocks + * for I/O). + * - @a TIME_INFINITE no timeout. + * . + * @return The operation result. + * @retval RDY_OK a frame has been received and placed in the buffer. + * @retval RDY_TIMEOUT The operation has timed out. + * @retval RDY_RESET The driver has been stopped while waiting. + * + * @api + */ +msg_t canReceive(CANDriver *canp, CANRxFrame *crfp, systime_t timeout) { + + chDbgCheck((canp != NULL) && (crfp != NULL), "canReceive"); + + chSysLock(); + chDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP), + "canReceive(), #1", "invalid state"); + while ((canp->state == CAN_SLEEP) || !can_lld_can_receive(canp)) { + msg_t msg = chSemWaitTimeoutS(&canp->rxsem, timeout); + if (msg != RDY_OK) { + chSysUnlock(); + return msg; + } + } + can_lld_receive(canp, crfp); + chSysUnlock(); + return RDY_OK; +} + +/** + * @brief Returns the current status mask and clears it. + * + * @param[in] canp pointer to the @p CANDriver object + * @return The status flags mask. + * + * @api + */ +canstatus_t canGetAndClearFlags(CANDriver *canp) { + canstatus_t status; + + chSysLock(); + status = canp->status; + canp->status = 0; + chSysUnlock(); + return status; +} + +#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__) +/** + * @brief Enters the sleep mode. + * @details This function puts the CAN driver in sleep mode and broadcasts + * the @p sleep_event event source. + * @pre In order to use this function the option @p CAN_USE_SLEEP_MODE must + * be enabled and the @p CAN_SUPPORTS_SLEEP mode must be supported + * by the low level driver. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @api + */ +void canSleep(CANDriver *canp) { + + chDbgCheck(canp != NULL, "canSleep"); + + chSysLock(); + chDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP), + "canSleep(), #1", "invalid state"); + if (canp->state == CAN_READY) { + can_lld_sleep(canp); + canp->state = CAN_SLEEP; + chEvtBroadcastI(&canp->sleep_event); + chSchRescheduleS(); + } + chSysUnlock(); +} + +/** + * @brief Enforces leaving the sleep mode. + * @note The sleep mode is supposed to be usually exited automatically by + * an hardware event. + * + * @param[in] canp pointer to the @p CANDriver object + */ +void canWakeup(CANDriver *canp) { + + chDbgCheck(canp != NULL, "canWakeup"); + + chSysLock(); + chDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP), + "canWakeup(), #1", "invalid state"); + if (canp->state == CAN_SLEEP) { + can_lld_wakeup(canp); + canp->state = CAN_READY; + chEvtBroadcastI(&canp->wakeup_event); + chSchRescheduleS(); + } + chSysUnlock(); +} +#endif /* CAN_USE_SLEEP_MODE */ + +#endif /* HAL_USE_CAN */ + +/** @} */ diff --git a/Project/os/hal/src/ext.c b/Project/os/hal/src/ext.c new file mode 100644 index 0000000..7b4a1b3 --- /dev/null +++ b/Project/os/hal/src/ext.c @@ -0,0 +1,174 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file ext.c + * @brief EXT Driver code. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief EXT Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void extInit(void) { + + ext_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p EXTDriver structure. + * + * @param[out] extp pointer to the @p EXTDriver object + * + * @init + */ +void extObjectInit(EXTDriver *extp) { + + extp->state = EXT_STOP; + extp->config = NULL; +} + +/** + * @brief Configures and activates the EXT peripheral. + * @post After activation all EXT channels are in the disabled state, + * use @p extChannelEnable() in order to activate them. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] config pointer to the @p EXTConfig object + * + * @api + */ +void extStart(EXTDriver *extp, const EXTConfig *config) { + + chDbgCheck((extp != NULL) && (config != NULL), "extStart"); + + chSysLock(); + chDbgAssert((extp->state == EXT_STOP) || (extp->state == EXT_ACTIVE), + "extStart(), #1", "invalid state"); + extp->config = config; + ext_lld_start(extp); + extp->state = EXT_ACTIVE; + chSysUnlock(); +} + +/** + * @brief Deactivates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @api + */ +void extStop(EXTDriver *extp) { + + chDbgCheck(extp != NULL, "extStop"); + + chSysLock(); + chDbgAssert((extp->state == EXT_STOP) || (extp->state == EXT_ACTIVE), + "extStop(), #1", "invalid state"); + ext_lld_stop(extp); + extp->state = EXT_STOP; + chSysUnlock(); +} + +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @api + */ +void extChannelEnable(EXTDriver *extp, expchannel_t channel) { + + chDbgCheck((extp != NULL) && + (channel < EXT_MAX_CHANNELS) && + (extp->config->channels[channel].mode != EXT_CH_MODE_DISABLED), + "extChannelEnable"); + + chSysLock(); + chDbgAssert(extp->state == EXT_ACTIVE, + "extChannelEnable(), #1", "invalid state"); + extChannelEnableI(extp, channel); + chSysUnlock(); +} + +/** + * @brief Disables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be disabled + * + * @api + */ +void extChannelDisable(EXTDriver *extp, expchannel_t channel) { + + chDbgCheck((extp != NULL) && + (channel < EXT_MAX_CHANNELS) && + (extp->config->channels[channel].mode != EXT_CH_MODE_DISABLED), + "extChannelDisable"); + + chSysLock(); + chDbgAssert(extp->state == EXT_ACTIVE, + "extChannelDisable(), #1", "invalid state"); + extChannelDisableI(extp, channel); + chSysUnlock(); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/Project/os/hal/src/gpt.c b/Project/os/hal/src/gpt.c new file mode 100644 index 0000000..83958c6 --- /dev/null +++ b/Project/os/hal/src/gpt.c @@ -0,0 +1,251 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file gpt.c + * @brief GPT Driver code. + * + * @addtogroup GPT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief GPT Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void gptInit(void) { + + gpt_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p GPTDriver structure. + * + * @param[out] gptp pointer to the @p GPTDriver object + * + * @init + */ +void gptObjectInit(GPTDriver *gptp) { + + gptp->state = GPT_STOP; + gptp->config = NULL; +} + +/** + * @brief Configures and activates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] config pointer to the @p GPTConfig object + * + * @api + */ +void gptStart(GPTDriver *gptp, const GPTConfig *config) { + + chDbgCheck((gptp != NULL) && (config != NULL), "ptStart"); + + chSysLock(); + chDbgAssert((gptp->state == GPT_STOP) || (gptp->state == GPT_READY), + "gptStart(), #1", "invalid state"); + gptp->config = config; + gpt_lld_start(gptp); + gptp->state = GPT_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @api + */ +void gptStop(GPTDriver *gptp) { + + chDbgCheck(gptp != NULL, "gptStop"); + + chSysLock(); + chDbgAssert((gptp->state == GPT_STOP) || (gptp->state == GPT_READY), + "gptStop(), #1", "invalid state"); + gpt_lld_stop(gptp); + gptp->state = GPT_STOP; + chSysUnlock(); +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @api + */ +void gptStartContinuous(GPTDriver *gptp, gptcnt_t interval) { + + chSysLock(); + gptStartContinuousI(gptp, interval); + chSysUnlock(); +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @iclass + */ +void gptStartContinuousI(GPTDriver *gptp, gptcnt_t interval) { + + chDbgCheckClassI(); + chDbgCheck(gptp != NULL, "gptStartContinuousI"); + chDbgAssert(gptp->state == GPT_READY, + "gptStartContinuousI(), #1", "invalid state"); + + gptp->state = GPT_CONTINUOUS; + gpt_lld_start_timer(gptp, interval); +} + +/** + * @brief Starts the timer in one shot mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @api + */ +void gptStartOneShot(GPTDriver *gptp, gptcnt_t interval) { + + chSysLock(); + gptStartOneShotI(gptp, interval); + chSysUnlock(); +} + +/** + * @brief Starts the timer in one shot mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @api + */ +void gptStartOneShotI(GPTDriver *gptp, gptcnt_t interval) { + + chDbgCheckClassI(); + chDbgCheck(gptp != NULL, "gptStartOneShotI"); + chDbgAssert(gptp->state == GPT_READY, + "gptStartOneShotI(), #1", "invalid state"); + + gptp->state = GPT_ONESHOT; + gpt_lld_start_timer(gptp, interval); +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @api + */ +void gptStopTimer(GPTDriver *gptp) { + + chSysLock(); + gptStopTimerI(gptp); + chSysUnlock(); +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @api + */ +void gptStopTimerI(GPTDriver *gptp) { + + chDbgCheckClassI(); + chDbgCheck(gptp != NULL, "gptStopTimerI"); + chDbgAssert((gptp->state == GPT_READY) || (gptp->state == GPT_CONTINUOUS) || + (gptp->state == GPT_ONESHOT), + "gptStopTimerI(), #1", "invalid state"); + + gptp->state = GPT_READY; + gpt_lld_stop_timer(gptp); +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * @note The configured callback is not invoked when using this function. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @api + */ +void gptPolledDelay(GPTDriver *gptp, gptcnt_t interval) { + + chDbgAssert(gptp->state == GPT_READY, + "gptPolledDelay(), #1", "invalid state"); + + gptp->state = GPT_ONESHOT; + gpt_lld_polled_delay(gptp, interval); + gptp->state = GPT_READY; +} + +#endif /* HAL_USE_GPT */ + +/** @} */ diff --git a/Project/os/hal/src/hal.c b/Project/os/hal/src/hal.c new file mode 100644 index 0000000..a46bdbb --- /dev/null +++ b/Project/os/hal/src/hal.c @@ -0,0 +1,201 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file hal.c + * @brief HAL subsystem code. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief HAL initialization. + * @details This function invokes the low level initialization code then + * initializes all the drivers enabled in the HAL. Finally the + * board-specific initialization is performed by invoking + * @p boardInit() (usually defined in @p board.c). + * + * @init + */ +void halInit(void) { + + hal_lld_init(); + +#if HAL_USE_TM || defined(__DOXYGEN__) + tmInit(); +#endif +#if HAL_USE_PAL || defined(__DOXYGEN__) + palInit(&pal_default_config); +#endif +#if HAL_USE_ADC || defined(__DOXYGEN__) + adcInit(); +#endif +#if HAL_USE_CAN || defined(__DOXYGEN__) + canInit(); +#endif +#if HAL_USE_EXT || defined(__DOXYGEN__) + extInit(); +#endif +#if HAL_USE_GPT || defined(__DOXYGEN__) + gptInit(); +#endif +#if HAL_USE_I2C || defined(__DOXYGEN__) + i2cInit(); +#endif +#if HAL_USE_ICU || defined(__DOXYGEN__) + icuInit(); +#endif +#if HAL_USE_MAC || defined(__DOXYGEN__) + macInit(); +#endif +#if HAL_USE_PWM || defined(__DOXYGEN__) + pwmInit(); +#endif +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + sdInit(); +#endif +#if HAL_USE_SDC || defined(__DOXYGEN__) + sdcInit(); +#endif +#if HAL_USE_SPI || defined(__DOXYGEN__) + spiInit(); +#endif +#if HAL_USE_UART || defined(__DOXYGEN__) + uartInit(); +#endif +#if HAL_USE_USB || defined(__DOXYGEN__) + usbInit(); +#endif +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) + mmcInit(); +#endif +#if HAL_USE_SERIAL_USB || defined(__DOXYGEN__) + sduInit(); +#endif +#if HAL_USE_RTC || defined(__DOXYGEN__) + rtcInit(); +#endif + /* Board specific initialization.*/ + boardInit(); +} + +#if HAL_IMPLEMENTS_COUNTERS || defined(__DOXYGEN__) +/** + * @brief Realtime window test. + * @details This function verifies if the current realtime counter value + * lies within the specified range or not. The test takes care + * of the realtime counter wrapping to zero on overflow. + * @note When start==end then the function returns always true because the + * whole time range is specified. + * @note This is an optional service that could not be implemented in + * all HAL implementations. + * @note This function can be called from any context. + * + * @par Example 1 + * Example of a guarded loop using the realtime counter. The loop implements + * a timeout after one second. + * @code + * halrtcnt_t start = halGetCounterValue(); + * halrtcnt_t timeout = start + S2RTT(1); + * while (my_condition) { + * if (!halIsCounterWithin(start, timeout) + * return TIMEOUT; + * // Do something. + * } + * // Continue. + * @endcode + * + * @par Example 2 + * Example of a loop that lasts exactly 50 microseconds. + * @code + * halrtcnt_t start = halGetCounterValue(); + * halrtcnt_t timeout = start + US2RTT(50); + * while (halIsCounterWithin(start, timeout)) { + * // Do something. + * } + * // Continue. + * @endcode + * + * @param[in] start the start of the time window (inclusive) + * @param[in] end the end of the time window (non inclusive) + * @retval TRUE current time within the specified time window. + * @retval FALSE current time not within the specified time window. + * + * @special + */ +bool_t halIsCounterWithin(halrtcnt_t start, halrtcnt_t end) { + halrtcnt_t now = halGetCounterValue(); + + return end > start ? (now >= start) && (now < end) : + (now >= start) || (now < end); +} + +/** + * @brief Polled delay. + * @note The real delays is always few cycles in excess of the specified + * value. + * @note This is an optional service that could not be implemented in + * all HAL implementations. + * @note This function can be called from any context. + * + * @param[in] ticks number of ticks + * + * @special + */ +void halPolledDelay(halrtcnt_t ticks) { + halrtcnt_t start = halGetCounterValue(); + halrtcnt_t timeout = start + (ticks); + while (halIsCounterWithin(start, timeout)) + ; +} +#endif /* HAL_IMPLEMENTS_COUNTERS */ + +/** @} */ diff --git a/Project/os/hal/src/i2c.c b/Project/os/hal/src/i2c.c new file mode 100644 index 0000000..22b39e2 --- /dev/null +++ b/Project/os/hal/src/i2c.c @@ -0,0 +1,310 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file i2c.c + * @brief I2C Driver code. + * + * @addtogroup I2C + * @{ + */ +#include "ch.h" +#include "hal.h" + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief I2C Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void i2cInit(void) { + i2c_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p I2CDriver structure. + * + * @param[out] i2cp pointer to the @p I2CDriver object + * + * @init + */ +void i2cObjectInit(I2CDriver *i2cp) { + + i2cp->state = I2C_STOP; + i2cp->config = NULL; + +#if I2C_USE_MUTUAL_EXCLUSION +#if CH_USE_MUTEXES + chMtxInit(&i2cp->mutex); +#else + chSemInit(&i2cp->semaphore, 1); +#endif /* CH_USE_MUTEXES */ +#endif /* I2C_USE_MUTUAL_EXCLUSION */ + +#if defined(I2C_DRIVER_EXT_INIT_HOOK) + I2C_DRIVER_EXT_INIT_HOOK(i2cp); +#endif +} + +/** + * @brief Configures and activates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] config pointer to the @p I2CConfig object + * + * @api + */ +void i2cStart(I2CDriver *i2cp, const I2CConfig *config) { + + chDbgCheck((i2cp != NULL) && (config != NULL), "i2cStart"); + chDbgAssert((i2cp->state == I2C_STOP) || (i2cp->state == I2C_READY) || + (i2cp->state == I2C_LOCKED), + "i2cStart(), #1", + "invalid state"); + + chSysLock(); + i2cp->config = config; + i2c_lld_start(i2cp); + i2cp->state = I2C_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @api + */ +void i2cStop(I2CDriver *i2cp) { + + chDbgCheck(i2cp != NULL, "i2cStop"); + chDbgAssert((i2cp->state == I2C_STOP) || (i2cp->state == I2C_READY) || + (i2cp->state == I2C_LOCKED), + "i2cStop(), #1", + "invalid state"); + + chSysLock(); + i2c_lld_stop(i2cp); + i2cp->state = I2C_STOP; + chSysUnlock(); +} + +/** + * @brief Returns the errors mask associated to the previous operation. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @return The errors mask. + * + * @api + */ +i2cflags_t i2cGetErrors(I2CDriver *i2cp) { + + chDbgCheck(i2cp != NULL, "i2cGetErrors"); + + return i2c_lld_get_errors(i2cp); +} + +/** + * @brief Sends data via the I2C bus. + * @details Function designed to realize "read-through-write" transfer + * paradigm. If you want transmit data without any further read, + * than set @b rxbytes field to 0. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address (7 bits) without R/W bit + * @param[in] txbuf pointer to transmit buffer + * @param[in] txbytes number of bytes to be transmitted + * @param[out] rxbuf pointer to receive buffer + * @param[in] rxbytes number of bytes to be received, set it to 0 if + * you want transmit only + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval RDY_TIMEOUT if a timeout occurred before operation end. + * + * @api + */ +msg_t i2cMasterTransmitTimeout(I2CDriver *i2cp, + i2caddr_t addr, + const uint8_t *txbuf, + size_t txbytes, + uint8_t *rxbuf, + size_t rxbytes, + systime_t timeout) { + msg_t rdymsg; + + chDbgCheck((i2cp != NULL) && (addr != 0) && + (txbytes > 0) && (txbuf != NULL) && + ((rxbytes == 0) || ((rxbytes > 0) && (rxbuf != NULL))) && + (timeout != TIME_IMMEDIATE), + "i2cMasterTransmitTimeout"); + + chDbgAssert(i2cp->state == I2C_READY, + "i2cMasterTransmitTimeout(), #1", "not ready"); + + chSysLock(); + i2cp->errors = I2CD_NO_ERROR; + i2cp->state = I2C_ACTIVE_TX; + rdymsg = i2c_lld_master_transmit_timeout(i2cp, addr, txbuf, txbytes, + rxbuf, rxbytes, timeout); + if (rdymsg == RDY_TIMEOUT) + i2cp->state = I2C_LOCKED; + else + i2cp->state = I2C_READY; + chSysUnlock(); + return rdymsg; +} + +/** + * @brief Receives data from the I2C bus. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address (7 bits) without R/W bit + * @param[out] rxbuf pointer to receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval RDY_TIMEOUT if a timeout occurred before operation end. + * + * @api + */ +msg_t i2cMasterReceiveTimeout(I2CDriver *i2cp, + i2caddr_t addr, + uint8_t *rxbuf, + size_t rxbytes, + systime_t timeout){ + + msg_t rdymsg; + + chDbgCheck((i2cp != NULL) && (addr != 0) && + (rxbytes > 0) && (rxbuf != NULL) && + (timeout != TIME_IMMEDIATE), + "i2cMasterReceiveTimeout"); + + chDbgAssert(i2cp->state == I2C_READY, + "i2cMasterReceive(), #1", "not ready"); + + chSysLock(); + i2cp->errors = I2CD_NO_ERROR; + i2cp->state = I2C_ACTIVE_RX; + rdymsg = i2c_lld_master_receive_timeout(i2cp, addr, rxbuf, rxbytes, timeout); + if (rdymsg == RDY_TIMEOUT) + i2cp->state = I2C_LOCKED; + else + i2cp->state = I2C_READY; + chSysUnlock(); + return rdymsg; +} + +#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +/** + * @brief Gains exclusive access to the I2C bus. + * @details This function tries to gain ownership to the SPI bus, if the bus + * is already being used then the invoking thread is queued. + * @pre In order to use this function the option @p I2C_USE_MUTUAL_EXCLUSION + * must be enabled. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @api + */ +void i2cAcquireBus(I2CDriver *i2cp) { + + chDbgCheck(i2cp != NULL, "i2cAcquireBus"); + +#if CH_USE_MUTEXES + chMtxLock(&i2cp->mutex); +#elif CH_USE_SEMAPHORES + chSemWait(&i2cp->semaphore); +#endif +} + +/** + * @brief Releases exclusive access to the I2C bus. + * @pre In order to use this function the option @p I2C_USE_MUTUAL_EXCLUSION + * must be enabled. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @api + */ +void i2cReleaseBus(I2CDriver *i2cp) { + + chDbgCheck(i2cp != NULL, "i2cReleaseBus"); + +#if CH_USE_MUTEXES + chMtxUnlock(); +#elif CH_USE_SEMAPHORES + chSemSignal(&i2cp->semaphore); +#endif +} +#endif /* I2C_USE_MUTUAL_EXCLUSION */ + +#endif /* HAL_USE_I2C */ + +/** @} */ diff --git a/Project/os/hal/src/icu.c b/Project/os/hal/src/icu.c new file mode 100644 index 0000000..3d0c25c --- /dev/null +++ b/Project/os/hal/src/icu.c @@ -0,0 +1,166 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file icu.c + * @brief ICU Driver code. + * + * @addtogroup ICU + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief ICU Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void icuInit(void) { + + icu_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p ICUDriver structure. + * + * @param[out] icup pointer to the @p ICUDriver object + * + * @init + */ +void icuObjectInit(ICUDriver *icup) { + + icup->state = ICU_STOP; + icup->config = NULL; +} + +/** + * @brief Configures and activates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * @param[in] config pointer to the @p ICUConfig object + * + * @api + */ +void icuStart(ICUDriver *icup, const ICUConfig *config) { + + chDbgCheck((icup != NULL) && (config != NULL), "icuStart"); + + chSysLock(); + chDbgAssert((icup->state == ICU_STOP) || (icup->state == ICU_READY), + "icuStart(), #1", "invalid state"); + icup->config = config; + icu_lld_start(icup); + icup->state = ICU_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @api + */ +void icuStop(ICUDriver *icup) { + + chDbgCheck(icup != NULL, "icuStop"); + + chSysLock(); + chDbgAssert((icup->state == ICU_STOP) || (icup->state == ICU_READY), + "icuStop(), #1", "invalid state"); + icu_lld_stop(icup); + icup->state = ICU_STOP; + chSysUnlock(); +} + +/** + * @brief Enables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @api + */ +void icuEnable(ICUDriver *icup) { + + chDbgCheck(icup != NULL, "icuEnable"); + + chSysLock(); + chDbgAssert(icup->state == ICU_READY, "icuEnable(), #1", "invalid state"); + icu_lld_enable(icup); + icup->state = ICU_WAITING; + chSysUnlock(); +} + +/** + * @brief Disables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @api + */ +void icuDisable(ICUDriver *icup) { + + chDbgCheck(icup != NULL, "icuDisable"); + + chSysLock(); + chDbgAssert((icup->state == ICU_READY) || (icup->state == ICU_WAITING) || + (icup->state == ICU_ACTIVE) || (icup->state == ICU_IDLE), + "icuDisable(), #1", "invalid state"); + icu_lld_disable(icup); + icup->state = ICU_READY; + chSysUnlock(); +} + +#endif /* HAL_USE_ICU */ + +/** @} */ diff --git a/Project/os/hal/src/mac.c b/Project/os/hal/src/mac.c new file mode 100644 index 0000000..ec54848 --- /dev/null +++ b/Project/os/hal/src/mac.c @@ -0,0 +1,275 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file mac.c + * @brief MAC Driver code. + * + * @addtogroup MAC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief MAC Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void macInit(void) { + + mac_lld_init(); +} + +/** + * @brief Initialize the standard part of a @p MACDriver structure. + * + * @param[out] macp pointer to the @p MACDriver object + * + * @init + */ +void macObjectInit(MACDriver *macp) { + + macp->state = MAC_STOP; + macp->config = NULL; + chSemInit(&macp->tdsem, 0); + chSemInit(&macp->rdsem, 0); +#if MAC_USE_EVENTS + chEvtInit(&macp->rdevent); +#endif +} + +/** + * @brief Configures and activates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[in] config pointer to the @p MACConfig object + * + * @api + */ +void macStart(MACDriver *macp, const MACConfig *config) { + + chDbgCheck((macp != NULL) && (config != NULL), "macStart"); + + chSysLock(); + chDbgAssert(macp->state == MAC_STOP, + "macStart(), #1", "invalid state"); + macp->config = config; + mac_lld_start(macp); + macp->state = MAC_ACTIVE; + chSysUnlock(); +} + +/** + * @brief Deactivates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @api + */ +void macStop(MACDriver *macp) { + + chDbgCheck(macp != NULL, "macStop"); + + chSysLock(); + chDbgAssert((macp->state == MAC_STOP) || (macp->state == MAC_ACTIVE), + "macStop(), #1", "invalid state"); + mac_lld_stop(macp); + macp->state = MAC_STOP; + chSysUnlock(); +} + +/** + * @brief Allocates a transmission descriptor. + * @details One of the available transmission descriptors is locked and + * returned. If a descriptor is not currently available then the + * invoking thread is queued until one is freed. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK the descriptor was obtained. + * @retval RDY_TIMEOUT the operation timed out, descriptor not initialized. + * + * @api + */ +msg_t macWaitTransmitDescriptor(MACDriver *macp, + MACTransmitDescriptor *tdp, + systime_t time) { + msg_t msg; + systime_t now; + + chDbgCheck((macp != NULL) && (tdp != NULL), "macWaitTransmitDescriptor"); + chDbgAssert(macp->state == MAC_ACTIVE, "macWaitTransmitDescriptor(), #1", + "not active"); + + while (((msg = mac_lld_get_transmit_descriptor(macp, tdp)) != RDY_OK) && + (time > 0)) { + chSysLock(); + now = chTimeNow(); + if ((msg = chSemWaitTimeoutS(&macp->tdsem, time)) == RDY_TIMEOUT) { + chSysUnlock(); + break; + } + if (time != TIME_INFINITE) + time -= (chTimeNow() - now); + chSysUnlock(); + } + return msg; +} + +/** + * @brief Releases a transmit descriptor and starts the transmission of the + * enqueued data as a single frame. + * + * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure + * + * @api + */ +void macReleaseTransmitDescriptor(MACTransmitDescriptor *tdp) { + + chDbgCheck((tdp != NULL), "macReleaseTransmitDescriptor"); + + mac_lld_release_transmit_descriptor(tdp); +} + +/** + * @brief Waits for a received frame. + * @details Stops until a frame is received and buffered. If a frame is + * not immediately available then the invoking thread is queued + * until one is received. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] rdp pointer to a @p MACReceiveDescriptor structure + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK the descriptor was obtained. + * @retval RDY_TIMEOUT the operation timed out, descriptor not initialized. + * + * @api + */ +msg_t macWaitReceiveDescriptor(MACDriver *macp, + MACReceiveDescriptor *rdp, + systime_t time) { + msg_t msg; + systime_t now; + + chDbgCheck((macp != NULL) && (rdp != NULL), "macWaitReceiveDescriptor"); + chDbgAssert(macp->state == MAC_ACTIVE, "macWaitReceiveDescriptor(), #1", + "not active"); + + while (((msg = mac_lld_get_receive_descriptor(macp, rdp)) != RDY_OK) && + (time > 0)) { + chSysLock(); + now = chTimeNow(); + if ((msg = chSemWaitTimeoutS(&macp->rdsem, time)) == RDY_TIMEOUT) { + chSysUnlock(); + break; + } + if (time != TIME_INFINITE) + time -= (chTimeNow() - now); + chSysUnlock(); + } + return msg; +} + +/** + * @brief Releases a receive descriptor. + * @details The descriptor and its buffer are made available for more incoming + * frames. + * + * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure + * + * @api + */ +void macReleaseReceiveDescriptor(MACReceiveDescriptor *rdp) { + + chDbgCheck((rdp != NULL), "macReleaseReceiveDescriptor"); + + mac_lld_release_receive_descriptor(rdp); +} + +/** + * @brief Updates and returns the link status. + * + * @param[in] macp pointer to the @p MACDriver object + * @return The link status. + * @retval TRUE if the link is active. + * @retval FALSE if the link is down. + * + * @api + */ +bool_t macPollLinkStatus(MACDriver *macp) { + + chDbgCheck((macp != NULL), "macPollLinkStatus"); + chDbgAssert(macp->state == MAC_ACTIVE, "macPollLinkStatus(), #1", + "not active"); + + return mac_lld_poll_link_status(macp); +} + +#endif /* HAL_USE_MAC */ + +/** @} */ diff --git a/Project/os/hal/src/mmc_spi.c b/Project/os/hal/src/mmc_spi.c new file mode 100644 index 0000000..0a1c310 --- /dev/null +++ b/Project/os/hal/src/mmc_spi.c @@ -0,0 +1,769 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ +/* + Parts of this file have been contributed by Matthias Blaicher. + */ + +/** + * @file mmc_spi.c + * @brief MMC over SPI driver code. + * + * @addtogroup MMC_SPI + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** + * @brief Lookup table for CRC-7 ( based on polynomial x^7 + x^3 + 1). + */ +static const uint8_t crc7_lookup_table[256] = { + 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f, 0x48, 0x41, 0x5a, 0x53, + 0x6c, 0x65, 0x7e, 0x77, 0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26, + 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e, 0x32, 0x3b, 0x20, 0x29, + 0x16, 0x1f, 0x04, 0x0d, 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45, + 0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14, 0x63, 0x6a, 0x71, 0x78, + 0x47, 0x4e, 0x55, 0x5c, 0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b, + 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13, 0x7d, 0x74, 0x6f, 0x66, + 0x59, 0x50, 0x4b, 0x42, 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a, + 0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69, 0x1e, 0x17, 0x0c, 0x05, + 0x3a, 0x33, 0x28, 0x21, 0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70, + 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38, 0x41, 0x48, 0x53, 0x5a, + 0x65, 0x6c, 0x77, 0x7e, 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36, + 0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67, 0x10, 0x19, 0x02, 0x0b, + 0x34, 0x3d, 0x26, 0x2f, 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c, + 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04, 0x6a, 0x63, 0x78, 0x71, + 0x4e, 0x47, 0x5c, 0x55, 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d, + 0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a, 0x6d, 0x64, 0x7f, 0x76, + 0x49, 0x40, 0x5b, 0x52, 0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03, + 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b, 0x17, 0x1e, 0x05, 0x0c, + 0x33, 0x3a, 0x21, 0x28, 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60, + 0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31, 0x46, 0x4f, 0x54, 0x5d, + 0x62, 0x6b, 0x70, 0x79 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Calculate the MMC standard CRC-7 based on a lookup table. + * + * @param[in] crc start value for CRC + * @param[in] buffer pointer to data buffer + * @param[in] len length of data + * @return Calculated CRC + */ +static uint8_t crc7(uint8_t crc, const uint8_t *buffer, size_t len) { + + while (len--) + crc = crc7_lookup_table[(crc << 1) ^ (*buffer++)]; + return crc; +} + +/** + * @brief Insertion monitor timer callback function. + * + * @param[in] p pointer to the @p MMCDriver object + * + * @notapi + */ +static void tmrfunc(void *p) { + MMCDriver *mmcp = p; + + if (mmcp->cnt > 0) { + if (mmcp->is_inserted()) { + if (--mmcp->cnt == 0) { + mmcp->state = MMC_INSERTED; + chEvtBroadcastI(&mmcp->inserted_event); + } + } + else + mmcp->cnt = MMC_POLLING_INTERVAL; + } + else { + if (!mmcp->is_inserted()) { + mmcp->state = MMC_WAIT; + mmcp->cnt = MMC_POLLING_INTERVAL; + chEvtBroadcastI(&mmcp->removed_event); + } + } + chVTSetI(&mmcp->vt, MS2ST(MMC_POLLING_DELAY), tmrfunc, mmcp); +} + +/** + * @brief Waits an idle condition. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * + * @notapi + */ +static void wait(MMCDriver *mmcp) { + int i; + uint8_t buf[4]; + + for (i = 0; i < 16; i++) { + spiReceive(mmcp->spip, 1, buf); + if (buf[0] == 0xFF) + return; + } + /* Looks like it is a long wait.*/ + while (TRUE) { + spiReceive(mmcp->spip, 1, buf); + if (buf[0] == 0xFF) + break; +#ifdef MMC_NICE_WAITING + /* Trying to be nice with the other threads.*/ + chThdSleep(1); +#endif + } +} + +/** + * @brief Sends a command header. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[in] cmd the command id + * @param[in] arg the command argument + * + * @notapi + */ +static void send_hdr(MMCDriver *mmcp, uint8_t cmd, uint32_t arg) { + uint8_t buf[6]; + + /* Wait for the bus to become idle if a write operation was in progress.*/ + wait(mmcp); + + buf[0] = 0x40 | cmd; + buf[1] = arg >> 24; + buf[2] = arg >> 16; + buf[3] = arg >> 8; + buf[4] = arg; + /* Calculate CRC for command header, shift to right position, add stop bit.*/ + buf[5] = ((crc7(0, buf, 5) & 0x7F) << 1) | 0x01; + + spiSend(mmcp->spip, 6, buf); +} + +/** + * @brief Receives a single byte response. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @return The response as an @p uint8_t value. + * @retval 0xFF timed out. + * + * @notapi + */ +static uint8_t recvr1(MMCDriver *mmcp) { + int i; + uint8_t r1[1]; + + for (i = 0; i < 9; i++) { + spiReceive(mmcp->spip, 1, r1); + if (r1[0] != 0xFF) + return r1[0]; + } + return 0xFF; +} + +/** + * @brief Receives a three byte response. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[out] buffer pointer to four bytes wide buffer + * @return First response byte as an @p uint8_t value. + * @retval 0xFF timed out. + * + * @notapi + */ +static uint8_t recvr3(MMCDriver *mmcp, uint8_t* buffer) { + uint8_t r1; + + r1 = recvr1(mmcp); + spiReceive(mmcp->spip, 4, buffer); + + return r1; +} + +/** + * @brief Sends a command an returns a single byte response. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[in] cmd the command id + * @param[in] arg the command argument + * @return The response as an @p uint8_t value. + * @retval 0xFF timed out. + * + * @notapi + */ +static uint8_t send_command_R1(MMCDriver *mmcp, uint8_t cmd, uint32_t arg) { + uint8_t r1; + + spiSelect(mmcp->spip); + send_hdr(mmcp, cmd, arg); + r1 = recvr1(mmcp); + spiUnselect(mmcp->spip); + return r1; +} + +/** + * @brief Sends a command which returns a five bytes response (R3). + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[in] cmd the command id + * @param[in] arg the command argument + * @param[out] response pointer to four bytes wide uint8_t buffer + * @return The first byte of the response (R1) as an @p + * uint8_t value. + * @retval 0xFF timed out. + * + * @notapi + */ +static uint8_t send_command_R3(MMCDriver *mmcp, uint8_t cmd, uint32_t arg, + uint8_t *response) { + uint8_t r1; + + spiSelect(mmcp->spip); + send_hdr(mmcp, cmd, arg); + r1 = recvr3(mmcp, response); + spiUnselect(mmcp->spip); + return r1; +} + +/** + * @brief Waits that the card reaches an idle state. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * + * @notapi + */ +static void sync(MMCDriver *mmcp) { + uint8_t buf[1]; + + spiSelect(mmcp->spip); + while (TRUE) { + spiReceive(mmcp->spip, 1, buf); + if (buf[0] == 0xFF) + break; +#ifdef MMC_NICE_WAITING + chThdSleep(1); /* Trying to be nice with the other threads.*/ +#endif + } + spiUnselect(mmcp->spip); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief MMC over SPI driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void mmcInit(void) { + +} + +/** + * @brief Initializes an instance. + * + * @param[out] mmcp pointer to the @p MMCDriver object + * @param[in] spip pointer to the SPI driver to be used as interface + * @param[in] lscfg low speed configuration for the SPI driver + * @param[in] hscfg high speed configuration for the SPI driver + * @param[in] is_protected function that returns the card write protection + * setting + * @param[in] is_inserted function that returns the card insertion sensor + * status + * + * @init + */ +void mmcObjectInit(MMCDriver *mmcp, SPIDriver *spip, + const SPIConfig *lscfg, const SPIConfig *hscfg, + mmcquery_t is_protected, mmcquery_t is_inserted) { + + mmcp->state = MMC_STOP; + mmcp->config = NULL; + mmcp->spip = spip; + mmcp->lscfg = lscfg; + mmcp->hscfg = hscfg; + mmcp->is_protected = is_protected; + mmcp->is_inserted = is_inserted; + mmcp->block_addresses = FALSE; + chEvtInit(&mmcp->inserted_event); + chEvtInit(&mmcp->removed_event); +} + +/** + * @brief Configures and activates the MMC peripheral. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[in] config pointer to the @p MMCConfig object. Must be @p NULL. + * + * @api + */ +void mmcStart(MMCDriver *mmcp, const MMCConfig *config) { + + chDbgCheck((mmcp != NULL) && (config == NULL), "mmcStart"); + + chSysLock(); + chDbgAssert(mmcp->state == MMC_STOP, "mmcStart(), #1", "invalid state"); + mmcp->config = config; + mmcp->state = MMC_WAIT; + mmcp->cnt = MMC_POLLING_INTERVAL; + chVTSetI(&mmcp->vt, MS2ST(MMC_POLLING_DELAY), tmrfunc, mmcp); + chSysUnlock(); +} + +/** + * @brief Disables the MMC peripheral. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * + * @api + */ +void mmcStop(MMCDriver *mmcp) { + + chDbgCheck(mmcp != NULL, "mmcStop"); + + chSysLock(); + chDbgAssert((mmcp->state != MMC_UNINIT) && + (mmcp->state != MMC_READING) && + (mmcp->state != MMC_WRITING), + "mmcStop(), #1", "invalid state"); + if (mmcp->state != MMC_STOP) { + mmcp->state = MMC_STOP; + chVTResetI(&mmcp->vt); + } + chSysUnlock(); + spiStop(mmcp->spip); +} + +/** + * @brief Performs the initialization procedure on the inserted card. + * @details This function should be invoked when a card is inserted and + * brings the driver in the @p MMC_READY state where it is possible + * to perform read and write operations. + * @note It is possible to invoke this function from the insertion event + * handler. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @return The operation status. + * @retval FALSE the operation succeeded and the driver is now + * in the @p MMC_READY state. + * @retval TRUE the operation failed. + * + * @api + */ +bool_t mmcConnect(MMCDriver *mmcp) { + unsigned i; + bool_t result; + uint8_t r3[4]; + + chDbgCheck(mmcp != NULL, "mmcConnect"); + + chDbgAssert((mmcp->state != MMC_UNINIT) && (mmcp->state != MMC_STOP), + "mmcConnect(), #1", "invalid state"); + + if (mmcp->state == MMC_INSERTED) { + /* Slow clock mode and 128 clock pulses.*/ + spiStart(mmcp->spip, mmcp->lscfg); + spiIgnore(mmcp->spip, 16); + + /* SPI mode selection.*/ + i = 0; + while (TRUE) { + if (send_command_R1(mmcp, MMC_CMDGOIDLE, 0) == 0x01) + break; + if (++i >= MMC_CMD0_RETRY) + return TRUE; + chThdSleepMilliseconds(10); + } + + /* Try to detect if this is a high capacity card and switch to block + * addresses if possible. + * + * This method is based on "How to support SDC Ver2 and high capacity cards" + * by ElmChan. + * + * */ + if(send_command_R3(mmcp, MMC_CMDINTERFACE_CONDITION, 0x01AA, r3) != 0x05) { + + /* Switch to SDHC mode.*/ + i = 0; + while (TRUE) { + if ((send_command_R1(mmcp, MMC_CMDAPP, 0) == 0x01) && + (send_command_R3(mmcp, MMC_ACMDOPCONDITION, 0x400001aa, r3) == 0x00)) + break; + + if (++i >= MMC_ACMD41_RETRY) + return TRUE; + chThdSleepMilliseconds(10); + } + + /* Execute dedicated read on OCR register */ + send_command_R3(mmcp, MMC_CMDREADOCR, 0, r3); + + /* Check if CCS is set in response. Card operates in block mode if set */ + if(r3[0] & 0x40) + mmcp->block_addresses = TRUE; + } + + /* Initialization. */ + i = 0; + while (TRUE) { + uint8_t b = send_command_R1(mmcp, MMC_CMDINIT, 0); + if (b == 0x00) + break; + if (b != 0x01) + return TRUE; + if (++i >= MMC_CMD1_RETRY) + return TRUE; + chThdSleepMilliseconds(10); + } + + /* Initialization complete, full speed. */ + spiStart(mmcp->spip, mmcp->hscfg); + + /* Setting block size.*/ + if (send_command_R1(mmcp, MMC_CMDSETBLOCKLEN, MMC_SECTOR_SIZE) != 0x00) + return TRUE; + + /* Transition to MMC_READY state (if not extracted).*/ + chSysLock(); + if (mmcp->state == MMC_INSERTED) { + mmcp->state = MMC_READY; + result = FALSE; + } + else + result = TRUE; + chSysUnlock(); + return result; + } + if (mmcp->state == MMC_READY) + return FALSE; + /* Any other state is invalid.*/ + return TRUE; +} + +/** + * @brief Brings the driver in a state safe for card removal. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @return The operation status. + * @retval FALSE the operation succeeded and the driver is now + * in the @p MMC_INSERTED state. + * @retval TRUE the operation failed. + * + * @api + */ +bool_t mmcDisconnect(MMCDriver *mmcp) { + bool_t status; + + chDbgCheck(mmcp != NULL, "mmcDisconnect"); + + chDbgAssert((mmcp->state != MMC_UNINIT) && (mmcp->state != MMC_STOP), + "mmcDisconnect(), #1", "invalid state"); + switch (mmcp->state) { + case MMC_READY: + /* Wait for the pending write operations to complete.*/ + sync(mmcp); + chSysLock(); + if (mmcp->state == MMC_READY) + mmcp->state = MMC_INSERTED; + chSysUnlock(); + case MMC_INSERTED: + status = FALSE; + default: + status = TRUE; + } + spiStop(mmcp->spip); + return status; +} + +/** + * @brief Starts a sequential read. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[in] startblk first block to read + * @return The operation status. + * @retval FALSE the operation succeeded. + * @retval TRUE the operation failed. + * + * @api + */ +bool_t mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk) { + + chDbgCheck(mmcp != NULL, "mmcStartSequentialRead"); + + chSysLock(); + if (mmcp->state != MMC_READY) { + chSysUnlock(); + return TRUE; + } + mmcp->state = MMC_READING; + chSysUnlock(); + + spiStart(mmcp->spip, mmcp->hscfg); + spiSelect(mmcp->spip); + + if(mmcp->block_addresses) + send_hdr(mmcp, MMC_CMDREADMULTIPLE, startblk); + else + send_hdr(mmcp, MMC_CMDREADMULTIPLE, startblk * MMC_SECTOR_SIZE); + + if (recvr1(mmcp) != 0x00) { + spiUnselect(mmcp->spip); + chSysLock(); + if (mmcp->state == MMC_READING) + mmcp->state = MMC_READY; + chSysUnlock(); + return TRUE; + } + return FALSE; +} + +/** + * @brief Reads a block within a sequential read operation. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[out] buffer pointer to the read buffer + * @return The operation status. + * @retval FALSE the operation succeeded. + * @retval TRUE the operation failed. + * + * @api + */ +bool_t mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer) { + int i; + + chDbgCheck((mmcp != NULL) && (buffer != NULL), "mmcSequentialRead"); + + chSysLock(); + if (mmcp->state != MMC_READING) { + chSysUnlock(); + return TRUE; + } + chSysUnlock(); + + for (i = 0; i < MMC_WAIT_DATA; i++) { + spiReceive(mmcp->spip, 1, buffer); + if (buffer[0] == 0xFE) { + spiReceive(mmcp->spip, MMC_SECTOR_SIZE, buffer); + /* CRC ignored. */ + spiIgnore(mmcp->spip, 2); + return FALSE; + } + } + /* Timeout.*/ + spiUnselect(mmcp->spip); + chSysLock(); + if (mmcp->state == MMC_READING) + mmcp->state = MMC_READY; + chSysUnlock(); + return TRUE; +} + +/** + * @brief Stops a sequential read gracefully. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @return The operation status. + * @retval FALSE the operation succeeded. + * @retval TRUE the operation failed. + * + * @api + */ +bool_t mmcStopSequentialRead(MMCDriver *mmcp) { + static const uint8_t stopcmd[] = {0x40 | MMC_CMDSTOP, 0, 0, 0, 0, 1, 0xFF}; + bool_t result; + + chDbgCheck(mmcp != NULL, "mmcStopSequentialRead"); + + chSysLock(); + if (mmcp->state != MMC_READING) { + chSysUnlock(); + return TRUE; + } + chSysUnlock(); + + spiSend(mmcp->spip, sizeof(stopcmd), stopcmd); +/* result = recvr1(mmcp) != 0x00;*/ + /* Note, ignored r1 response, it can be not zero, unknown issue.*/ + recvr1(mmcp); + result = FALSE; + spiUnselect(mmcp->spip); + + chSysLock(); + if (mmcp->state == MMC_READING) + mmcp->state = MMC_READY; + chSysUnlock(); + return result; +} + +/** + * @brief Starts a sequential write. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[in] startblk first block to write + * @return The operation status. + * @retval FALSE the operation succeeded. + * @retval TRUE the operation failed. + * + * @api + */ +bool_t mmcStartSequentialWrite(MMCDriver *mmcp, uint32_t startblk) { + + chDbgCheck(mmcp != NULL, "mmcStartSequentialWrite"); + + chSysLock(); + if (mmcp->state != MMC_READY) { + chSysUnlock(); + return TRUE; + } + mmcp->state = MMC_WRITING; + chSysUnlock(); + + spiStart(mmcp->spip, mmcp->hscfg); + spiSelect(mmcp->spip); + if(mmcp->block_addresses) + send_hdr(mmcp, MMC_CMDWRITEMULTIPLE, startblk); + else + send_hdr(mmcp, MMC_CMDWRITEMULTIPLE, startblk * MMC_SECTOR_SIZE); + + + if (recvr1(mmcp) != 0x00) { + spiUnselect(mmcp->spip); + chSysLock(); + if (mmcp->state == MMC_WRITING) + mmcp->state = MMC_READY; + chSysUnlock(); + return TRUE; + } + return FALSE; +} + +/** + * @brief Writes a block within a sequential write operation. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @param[out] buffer pointer to the write buffer + * @return The operation status. + * @retval FALSE the operation succeeded. + * @retval TRUE the operation failed. + * + * @api + */ +bool_t mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer) { + static const uint8_t start[] = {0xFF, 0xFC}; + uint8_t b[1]; + + chDbgCheck((mmcp != NULL) && (buffer != NULL), "mmcSequentialWrite"); + + chSysLock(); + if (mmcp->state != MMC_WRITING) { + chSysUnlock(); + return TRUE; + } + chSysUnlock(); + + spiSend(mmcp->spip, sizeof(start), start); /* Data prologue. */ + spiSend(mmcp->spip, MMC_SECTOR_SIZE, buffer); /* Data. */ + spiIgnore(mmcp->spip, 2); /* CRC ignored. */ + spiReceive(mmcp->spip, 1, b); + if ((b[0] & 0x1F) == 0x05) { + wait(mmcp); + return FALSE; + } + + /* Error.*/ + spiUnselect(mmcp->spip); + chSysLock(); + if (mmcp->state == MMC_WRITING) + mmcp->state = MMC_READY; + chSysUnlock(); + return TRUE; +} + +/** + * @brief Stops a sequential write gracefully. + * + * @param[in] mmcp pointer to the @p MMCDriver object + * @return The operation status. + * @retval FALSE the operation succeeded. + * @retval TRUE the operation failed. + * + * @api + */ +bool_t mmcStopSequentialWrite(MMCDriver *mmcp) { + static const uint8_t stop[] = {0xFD, 0xFF}; + + chDbgCheck(mmcp != NULL, "mmcStopSequentialWrite"); + + chSysLock(); + if (mmcp->state != MMC_WRITING) { + chSysUnlock(); + return TRUE; + } + chSysUnlock(); + + spiSend(mmcp->spip, sizeof(stop), stop); + spiUnselect(mmcp->spip); + + chSysLock(); + if (mmcp->state == MMC_WRITING) { + mmcp->state = MMC_READY; + chSysUnlock(); + return FALSE; + } + chSysUnlock(); + return TRUE; +} + +#endif /* HAL_USE_MMC_SPI */ + +/** @} */ diff --git a/Project/os/hal/src/pal.c b/Project/os/hal/src/pal.c new file mode 100644 index 0000000..3f8c91f --- /dev/null +++ b/Project/os/hal/src/pal.c @@ -0,0 +1,134 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file pal.c + * @brief I/O Ports Abstraction Layer code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Read from an I/O bus. + * @note The operation is not guaranteed to be atomic on all the + * architectures, for atomicity and/or portability reasons you may + * need to enclose port I/O operations between @p chSysLock() and + * @p chSysUnlock(). + * @note The function internally uses the @p palReadGroup() macro. The use + * of this function is preferred when you value code size, readability + * and error checking over speed. + * + * @param[in] bus the I/O bus, pointer to a @p IOBus structure + * @return The bus logical states. + * + * @api + */ +ioportmask_t palReadBus(IOBus *bus) { + + chDbgCheck((bus != NULL) && + (bus->offset < PAL_IOPORTS_WIDTH), "palReadBus"); + + return palReadGroup(bus->portid, bus->mask, bus->offset); +} + +/** + * @brief Write to an I/O bus. + * @note The operation is not guaranteed to be atomic on all the + * architectures, for atomicity and/or portability reasons you may + * need to enclose port I/O operations between @p chSysLock() and + * @p chSysUnlock(). + * @note The default implementation is non atomic and not necessarily + * optimal. Low level drivers may optimize the function by using + * specific hardware or coding. + * + * @param[in] bus the I/O bus, pointer to a @p IOBus structure + * @param[in] bits the bits to be written on the I/O bus. Values exceeding + * the bus width are masked so most significant bits are + * lost. + * + * @api + */ +void palWriteBus(IOBus *bus, ioportmask_t bits) { + + chDbgCheck((bus != NULL) && + (bus->offset < PAL_IOPORTS_WIDTH), "palWriteBus"); + + palWriteGroup(bus->portid, bus->mask, bus->offset, bits); +} + +/** + * @brief Programs a bus with the specified mode. + * @note The operation is not guaranteed to be atomic on all the + * architectures, for atomicity and/or portability reasons you may + * need to enclose port I/O operations between @p chSysLock() and + * @p chSysUnlock(). + * @note The default implementation is non atomic and not necessarily + * optimal. Low level drivers may optimize the function by using + * specific hardware or coding. + * + * @param[in] bus the I/O bus, pointer to a @p IOBus structure + * @param[in] mode the mode + * + * @api + */ +void palSetBusMode(IOBus *bus, iomode_t mode) { + + chDbgCheck((bus != NULL) && + (bus->offset < PAL_IOPORTS_WIDTH), "palSetBusMode"); + + palSetGroupMode(bus->portid, bus->mask, bus->offset, mode); +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/Project/os/hal/src/pwm.c b/Project/os/hal/src/pwm.c new file mode 100644 index 0000000..e121731 --- /dev/null +++ b/Project/os/hal/src/pwm.c @@ -0,0 +1,214 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file pwm.c + * @brief PWM Driver code. + * + * @addtogroup PWM + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief PWM Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void pwmInit(void) { + + pwm_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p PWMDriver structure. + * + * @param[out] pwmp pointer to a @p PWMDriver object + * + * @init + */ +void pwmObjectInit(PWMDriver *pwmp) { + + pwmp->state = PWM_STOP; + pwmp->config = NULL; +#if defined(PWM_DRIVER_EXT_INIT_HOOK) + PWM_DRIVER_EXT_INIT_HOOK(pwmp); +#endif +} + +/** + * @brief Configures and activates the PWM peripheral. + * @note Starting a driver that is already in the @p PWM_READY state + * disables all the active channels. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] config pointer to a @p PWMConfig object + * + * @api + */ +void pwmStart(PWMDriver *pwmp, const PWMConfig *config) { + + chDbgCheck((pwmp != NULL) && (config != NULL), "pwmStart"); + + chSysLock(); + chDbgAssert((pwmp->state == PWM_STOP) || (pwmp->state == PWM_READY), + "pwmStart(), #1", "invalid state"); + pwmp->config = config; + pwmp->period = config->period; + pwm_lld_start(pwmp); + pwmp->state = PWM_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the PWM peripheral. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @api + */ +void pwmStop(PWMDriver *pwmp) { + + chDbgCheck(pwmp != NULL, "pwmStop"); + + chSysLock(); + chDbgAssert((pwmp->state == PWM_STOP) || (pwmp->state == PWM_READY), + "pwmStop(), #1", "invalid state"); + pwm_lld_stop(pwmp); + pwmp->state = PWM_STOP; + chSysUnlock(); +} + +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @api + */ +void pwmChangePeriod(PWMDriver *pwmp, pwmcnt_t period) { + + chDbgCheck(pwmp != NULL, "pwmChangePeriod"); + + chSysLock(); + chDbgAssert(pwmp->state == PWM_READY, + "pwmChangePeriod(), #1", "invalid state"); + pwmChangePeriodI(pwmp, period); + chSysUnlock(); +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note Depending on the hardware implementation this function has + * effect starting on the next cycle (recommended implementation) + * or immediately (fallback implementation). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @api + */ +void pwmEnableChannel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width) { + + chDbgCheck((pwmp != NULL) && (channel < PWM_CHANNELS), + "pwmEnableChannel"); + + chSysLock(); + chDbgAssert(pwmp->state == PWM_READY, + "pwmEnableChannel(), #1", "not ready"); + pwm_lld_enable_channel(pwmp, channel, width); + chSysUnlock(); +} + +/** + * @brief Disables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note Depending on the hardware implementation this function has + * effect starting on the next cycle (recommended implementation) + * or immediately (fallback implementation). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * + * @api + */ +void pwmDisableChannel(PWMDriver *pwmp, pwmchannel_t channel) { + + chDbgCheck((pwmp != NULL) && (channel < PWM_CHANNELS), + "pwmEnableChannel"); + + chSysLock(); + chDbgAssert(pwmp->state == PWM_READY, + "pwmDisableChannel(), #1", "not ready"); + pwm_lld_disable_channel(pwmp, channel); + chSysUnlock(); +} + +#endif /* HAL_USE_PWM */ + +/** @} */ diff --git a/Project/os/hal/src/rtc.c b/Project/os/hal/src/rtc.c new file mode 100644 index 0000000..c96634e --- /dev/null +++ b/Project/os/hal/src/rtc.c @@ -0,0 +1,179 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file rtc.c + * @brief RTC Driver code. + * + * @addtogroup RTC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief RTC Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void rtcInit(void) { + + rtc_lld_init(); +} + +/** + * @brief Set current time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] timespec pointer to a @p RTCTime structure + * + * @api + */ +void rtcSetTime(RTCDriver *rtcp, const RTCTime *timespec) { + + chDbgCheck((rtcp != NULL) && (timespec != NULL), "rtcSetTime"); + + chSysLock(); + rtcSetTimeI(rtcp, timespec); + chSysUnlock(); +} + +/** + * @brief Get current time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[out] timespec pointer to a @p RTCTime structure + * + * @api + */ +void rtcGetTime(RTCDriver *rtcp, RTCTime *timespec) { + + chDbgCheck((rtcp != NULL) && (timespec != NULL), "rtcGetTime"); + + chSysLock(); + rtcGetTimeI(rtcp, timespec); + chSysUnlock(); +} + +#if (RTC_ALARMS > 0) || defined(__DOXYGEN__) +/** + * @brief Set alarm time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[in] alarmspec pointer to a @p RTCAlarm structure or @p NULL + * + * @api + */ +void rtcSetAlarm(RTCDriver *rtcp, + rtcalarm_t alarm, + const RTCAlarm *alarmspec) { + + chDbgCheck((rtcp != NULL) && (alarm < RTC_ALARMS), "rtcSetAlarm"); + + chSysLock(); + rtcSetAlarmI(rtcp, alarm, alarmspec); + chSysUnlock(); +} + +/** + * @brief Get current alarm. + * @note If an alarm has not been set then the returned alarm specification + * is not meaningful. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[out] alarmspec pointer to a @p RTCAlarm structure + * + * @api + */ +void rtcGetAlarm(RTCDriver *rtcp, + rtcalarm_t alarm, + RTCAlarm *alarmspec) { + + chDbgCheck((rtcp != NULL) && (alarm < RTC_ALARMS) && (alarmspec != NULL), + "rtcGetAlarm"); + + chSysLock(); + rtcGetAlarmI(rtcp, alarm, alarmspec); + chSysUnlock(); +} +#endif /* RTC_ALARMS > 0 */ + +#if RTC_SUPPORTS_CALLBACKS || defined(__DOXYGEN__) +/** + * @brief Enables or disables RTC callbacks. + * @details This function enables or disables the callback, use a @p NULL + * pointer in order to disable it. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] callback callback function pointer or @p NULL + * + * @api + */ +void rtcSetCallback(RTCDriver *rtcp, rtccb_t callback) { + + chDbgCheck((rtcp != NULL), "rtcSetCallback"); + + chSysLock(); + rtcSetCallbackI(rtcp, callback); + chSysUnlock(); +} +#endif /* RTC_SUPPORTS_CALLBACKS */ + +#endif /* HAL_USE_RTC */ + +/** @} */ diff --git a/Project/os/hal/src/sdc.c b/Project/os/hal/src/sdc.c new file mode 100644 index 0000000..1cf8419 --- /dev/null +++ b/Project/os/hal/src/sdc.c @@ -0,0 +1,404 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file sdc.c + * @brief SDC Driver code. + * + * @addtogroup SDC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SDC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Wait for the card to complete pending operations. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @return The operation status. + * @retval FALSE the card is now in transfer state. + * @retval TRUE an error occurred while waiting or the card is in an + * unexpected state. + * + * @notapi + */ +bool_t _sdc_wait_for_transfer_state(SDCDriver *sdcp) { + uint32_t resp[1]; + + while (TRUE) { + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_SEND_STATUS, + sdcp->rca, resp) || + SDC_R1_ERROR(resp[0])) + return TRUE; + switch (SDC_R1_STS(resp[0])) { + case SDC_STS_TRAN: + return FALSE; + case SDC_STS_DATA: + case SDC_STS_RCV: + case SDC_STS_PRG: +#if SDC_NICE_WAITING + chThdSleepMilliseconds(1); +#endif + continue; + default: + /* The card should have been initialized so any other state is not + valid and is reported as an error.*/ + return TRUE; + } + } +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief SDC Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void sdcInit(void) { + + sdc_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p SDCDriver structure. + * + * @param[out] sdcp pointer to the @p SDCDriver object + * + * @init + */ +void sdcObjectInit(SDCDriver *sdcp) { + + sdcp->state = SDC_STOP; + sdcp->config = NULL; +} + +/** + * @brief Configures and activates the SDC peripheral. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] config pointer to the @p SDCConfig object, can be @p NULL if + * the driver supports a default configuration or + * requires no configuration + * + * @api + */ +void sdcStart(SDCDriver *sdcp, const SDCConfig *config) { + + chDbgCheck(sdcp != NULL, "sdcStart"); + + chSysLock(); + chDbgAssert((sdcp->state == SDC_STOP) || (sdcp->state == SDC_READY), + "sdcStart(), #1", "invalid state"); + sdcp->config = config; + sdc_lld_start(sdcp); + sdcp->state = SDC_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the SDC peripheral. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @api + */ +void sdcStop(SDCDriver *sdcp) { + + chDbgCheck(sdcp != NULL, "sdcStop"); + + chSysLock(); + chDbgAssert((sdcp->state == SDC_STOP) || (sdcp->state == SDC_READY), + "sdcStop(), #1", "invalid state"); + sdc_lld_stop(sdcp); + sdcp->state = SDC_STOP; + chSysUnlock(); +} + +/** + * @brief Performs the initialization procedure on the inserted card. + * @details This function should be invoked when a card is inserted and + * brings the driver in the @p SDC_ACTIVE state where it is possible + * to perform read and write operations. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @return The operation status. + * @retval FALSE operation succeeded, the driver is now + * in the @p SDC_ACTIVE state. + * @retval TRUE operation failed. + * + * @api + */ +bool_t sdcConnect(SDCDriver *sdcp) { + uint32_t resp[1]; + + chDbgCheck(sdcp != NULL, "sdcConnect"); + + chSysLock(); + chDbgAssert((sdcp->state == SDC_READY) || (sdcp->state == SDC_ACTIVE), + "mmcConnect(), #1", "invalid state"); + sdcp->state = SDC_CONNECTING; + chSysUnlock(); + + /* Card clock initialization.*/ + sdc_lld_start_clk(sdcp); + + /* Enforces the initial card state.*/ + sdc_lld_send_cmd_none(sdcp, SDC_CMD_GO_IDLE_STATE, 0); + + /* V2.0 cards detection.*/ + if (!sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_SEND_IF_COND, + SDC_CMD8_PATTERN, resp)) { + sdcp->cardmode = SDC_MODE_CARDTYPE_SDV20; + /* Voltage verification.*/ + if (((resp[0] >> 8) & 0xF) != 1) + goto failed; + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_APP_CMD, 0, resp) || + SDC_R1_ERROR(resp[0])) + goto failed; + } + else { +#if SDC_MMC_SUPPORT + /* MMC or SD V1.1 detection.*/ + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_APP_CMD, 0, resp) || + SDC_R1_ERROR(resp[0])) + sdcp->cardmode = SDC_MODE_CARDTYPE_MMC; + else +#endif /* SDC_MMC_SUPPORT */ + sdcp->cardmode = SDC_MODE_CARDTYPE_SDV11; + } + +#if SDC_MMC_SUPPORT + if ((sdcp->cardmode & SDC_MODE_CARDTYPE_MASK) == SDC_MODE_CARDTYPE_MMC) { + /* TODO: MMC initialization.*/ + return TRUE; + } + else +#endif /* SDC_MMC_SUPPORT */ + { + unsigned i; + uint32_t ocr; + + /* SD initialization.*/ + if ((sdcp->cardmode & SDC_MODE_CARDTYPE_MASK) == SDC_MODE_CARDTYPE_SDV20) + ocr = 0xC0100000; + else + ocr = 0x80100000; + + /* SD-type initialization. */ + i = 0; + while (TRUE) { + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_APP_CMD, 0, resp) || + SDC_R1_ERROR(resp[0])) + goto failed; + if (sdc_lld_send_cmd_short(sdcp, SDC_CMD_APP_OP_COND, ocr, resp)) + goto failed; + if ((resp[0] & 0x80000000) != 0) { + if (resp[0] & 0x40000000) + sdcp->cardmode |= SDC_MODE_HIGH_CAPACITY; + break; + } + if (++i >= SDC_INIT_RETRY) + goto failed; + chThdSleepMilliseconds(10); + } + } + + /* Reads CID.*/ + if (sdc_lld_send_cmd_long_crc(sdcp, SDC_CMD_ALL_SEND_CID, 0, sdcp->cid)) + goto failed; + + /* Asks for the RCA.*/ + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_SEND_RELATIVE_ADDR, + 0, &sdcp->rca)) + goto failed; + + /* Reads CSD.*/ + if (sdc_lld_send_cmd_long_crc(sdcp, SDC_CMD_SEND_CSD, sdcp->rca, sdcp->csd)) + goto failed; + + /* Switches to high speed.*/ + sdc_lld_set_data_clk(sdcp); + + /* Selects the card for operations.*/ + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_SEL_DESEL_CARD, + sdcp->rca, resp)) + goto failed; + + /* Block length fixed at 512 bytes.*/ + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_SET_BLOCKLEN, + SDC_BLOCK_SIZE, resp) || + SDC_R1_ERROR(resp[0])) + goto failed; + + /* Switches to wide bus mode.*/ + switch (sdcp->cardmode & SDC_MODE_CARDTYPE_MASK) { + case SDC_MODE_CARDTYPE_SDV11: + case SDC_MODE_CARDTYPE_SDV20: + sdc_lld_set_bus_mode(sdcp, SDC_MODE_4BIT); + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_APP_CMD, sdcp->rca, resp) || + SDC_R1_ERROR(resp[0])) + goto failed; + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_SET_BUS_WIDTH, 2, resp) || + SDC_R1_ERROR(resp[0])) + goto failed; + } + + sdcp->state = SDC_ACTIVE; + return FALSE; +failed: + sdc_lld_stop_clk(sdcp); + sdcp->state = SDC_READY; + return TRUE; +} + +/** + * @brief Brings the driver in a state safe for card removal. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @return The operation status. + * @retval FALSE the operation succeeded and the driver is now + * in the @p SDC_READY state. + * @retval TRUE the operation failed. + * + * @api + */ +bool_t sdcDisconnect(SDCDriver *sdcp) { + + chDbgCheck(sdcp != NULL, "sdcDisconnect"); + + chSysLock(); + chDbgAssert(sdcp->state == SDC_ACTIVE, + "sdcDisconnect(), #1", "invalid state"); + if (sdcp->state == SDC_READY) { + chSysUnlock(); + return FALSE; + } + sdcp->state = SDC_DISCONNECTING; + chSysUnlock(); + + /* Waits for eventual pending operations completion.*/ + if (_sdc_wait_for_transfer_state(sdcp)) + return TRUE; + + /* Card clock stopped.*/ + sdc_lld_stop_clk(sdcp); + + sdcp->state = SDC_READY; + return FALSE; +} + +/** + * @brief Reads one or more blocks. + * @pre The driver must be in the @p SDC_ACTIVE state after a successful + * sdcConnect() invocation. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to read + * @param[out] buf pointer to the read buffer + * @param[in] n number of blocks to read + * @return The operation status. + * @retval FALSE operation succeeded, the requested blocks have been + * read. + * @retval TRUE operation failed, the state of the buffer is uncertain. + * + * @api + */ +bool_t sdcRead(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf, uint32_t n) { + bool_t err; + + chDbgCheck((sdcp != NULL) && (buf != NULL) && (n > 0), "sdcRead"); + + chSysLock(); + chDbgAssert(sdcp->state == SDC_ACTIVE, "sdcRead(), #1", "invalid state"); + sdcp->state = SDC_READING; + chSysUnlock(); + + err = sdc_lld_read(sdcp, startblk, buf, n); + sdcp->state = SDC_ACTIVE; + return err; +} + +/** + * @brief Writes one or more blocks. + * @pre The driver must be in the @p SDC_ACTIVE state after a successful + * sdcConnect() invocation. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to write + * @param[out] buf pointer to the write buffer + * @param[in] n number of blocks to write + * @return The operation status. + * @retval FALSE operation succeeded, the requested blocks have been + * written. + * @retval TRUE operation failed. + * + * @api + */ +bool_t sdcWrite(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf, uint32_t n) { + bool_t err; + + chDbgCheck((sdcp != NULL) && (buf != NULL) && (n > 0), "sdcWrite"); + + chSysLock(); + chDbgAssert(sdcp->state == SDC_ACTIVE, "sdcWrite(), #1", "invalid state"); + sdcp->state = SDC_WRITING; + chSysUnlock(); + + err = sdc_lld_write(sdcp, startblk, buf, n); + sdcp->state = SDC_ACTIVE; + return err; +} + +#endif /* HAL_USE_SDC */ + +/** @} */ diff --git a/Project/os/hal/src/serial.c b/Project/os/hal/src/serial.c new file mode 100644 index 0000000..aaa345a --- /dev/null +++ b/Project/os/hal/src/serial.c @@ -0,0 +1,259 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file serial.c + * @brief Serial Driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/* + * Interface implementation, the following functions just invoke the equivalent + * queue-level function or macro. + */ + +static size_t writes(void *ip, const uint8_t *bp, size_t n) { + + return chOQWriteTimeout(&((SerialDriver *)ip)->oqueue, bp, + n, TIME_INFINITE); +} + +static size_t reads(void *ip, uint8_t *bp, size_t n) { + + return chIQReadTimeout(&((SerialDriver *)ip)->iqueue, bp, + n, TIME_INFINITE); +} + +static bool_t putwouldblock(void *ip) { + + return chOQIsFullI(&((SerialDriver *)ip)->oqueue); +} + +static bool_t getwouldblock(void *ip) { + + return chIQIsEmptyI(&((SerialDriver *)ip)->iqueue); +} + +static msg_t putt(void *ip, uint8_t b, systime_t timeout) { + + return chOQPutTimeout(&((SerialDriver *)ip)->oqueue, b, timeout); +} + +static msg_t gett(void *ip, systime_t timeout) { + + return chIQGetTimeout(&((SerialDriver *)ip)->iqueue, timeout); +} + +static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t time) { + + return chOQWriteTimeout(&((SerialDriver *)ip)->oqueue, bp, n, time); +} + +static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t time) { + + return chIQReadTimeout(&((SerialDriver *)ip)->iqueue, bp, n, time); +} + +static ioflags_t getflags(void *ip) { + _ch_get_and_clear_flags_impl(ip); +} + +static const struct SerialDriverVMT vmt = { + writes, reads, putwouldblock, getwouldblock, + putt, gett, writet, readt, + getflags +}; + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Serial Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void sdInit(void) { + + sd_lld_init(); +} + +/** + * @brief Initializes a generic full duplex driver object. + * @details The HW dependent part of the initialization has to be performed + * outside, usually in the hardware initialization code. + * + * @param[out] sdp pointer to a @p SerialDriver structure + * @param[in] inotify pointer to a callback function that is invoked when + * some data is read from the Queue. The value can be + * @p NULL. + * @param[in] onotify pointer to a callback function that is invoked when + * some data is written in the Queue. The value can be + * @p NULL. + * + * @init + */ +void sdObjectInit(SerialDriver *sdp, qnotify_t inotify, qnotify_t onotify) { + + sdp->vmt = &vmt; + chEvtInit(&sdp->event); + sdp->flags = IO_NO_ERROR; + sdp->state = SD_STOP; + chIQInit(&sdp->iqueue, sdp->ib, SERIAL_BUFFERS_SIZE, inotify); + chOQInit(&sdp->oqueue, sdp->ob, SERIAL_BUFFERS_SIZE, onotify); +} + +/** + * @brief Configures and starts the driver. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @api + */ +void sdStart(SerialDriver *sdp, const SerialConfig *config) { + + chDbgCheck(sdp != NULL, "sdStart"); + + chSysLock(); + chDbgAssert((sdp->state == SD_STOP) || (sdp->state == SD_READY), + "sdStart(), #1", + "invalid state"); + sd_lld_start(sdp, config); + sdp->state = SD_READY; + chSysUnlock(); +} + +/** + * @brief Stops the driver. + * @details Any thread waiting on the driver's queues will be awakened with + * the message @p Q_RESET. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @api + */ +void sdStop(SerialDriver *sdp) { + + chDbgCheck(sdp != NULL, "sdStop"); + + chSysLock(); + chDbgAssert((sdp->state == SD_STOP) || (sdp->state == SD_READY), + "sdStop(), #1", + "invalid state"); + sd_lld_stop(sdp); + sdp->state = SD_STOP; + chOQResetI(&sdp->oqueue); + chIQResetI(&sdp->iqueue); + chSchRescheduleS(); + chSysUnlock(); +} + +/** + * @brief Handles incoming data. + * @details This function must be called from the input interrupt service + * routine in order to enqueue incoming data and generate the + * related events. + * @note The incoming data event is only generated when the input queue + * becomes non-empty. + * @note In order to gain some performance it is suggested to not use + * this function directly but copy this code directly into the + * interrupt service routine. + * + * @param[in] sdp pointer to a @p SerialDriver structure + * @param[in] b the byte to be written in the driver's Input Queue + * + * @iclass + */ +void sdIncomingDataI(SerialDriver *sdp, uint8_t b) { + + chDbgCheckClassI(); + chDbgCheck(sdp != NULL, "sdIncomingDataI"); + + if (chIQIsEmptyI(&sdp->iqueue)) + chIOAddFlagsI(sdp, IO_INPUT_AVAILABLE); + if (chIQPutI(&sdp->iqueue, b) < Q_OK) + chIOAddFlagsI(sdp, SD_OVERRUN_ERROR); +} + +/** + * @brief Handles outgoing data. + * @details Must be called from the output interrupt service routine in order + * to get the next byte to be transmitted. + * @note In order to gain some performance it is suggested to not use + * this function directly but copy this code directly into the + * interrupt service routine. + * + * @param[in] sdp pointer to a @p SerialDriver structure + * @return The byte value read from the driver's output queue. + * @retval Q_EMPTY if the queue is empty (the lower driver usually + * disables the interrupt source when this happens). + * + * @iclass + */ +msg_t sdRequestDataI(SerialDriver *sdp) { + msg_t b; + + chDbgCheckClassI(); + chDbgCheck(sdp != NULL, "sdRequestDataI"); + + b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) + chIOAddFlagsI(sdp, IO_OUTPUT_EMPTY); + return b; +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/Project/os/hal/src/serial_usb.c b/Project/os/hal/src/serial_usb.c new file mode 100644 index 0000000..4527eea --- /dev/null +++ b/Project/os/hal/src/serial_usb.c @@ -0,0 +1,383 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file serial_usb.c + * @brief Serial over USB Driver code. + * + * @addtogroup SERIAL_USB + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#include "usb_cdc.h" + +#if HAL_USE_SERIAL_USB || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/* + * Current Line Coding. + */ +static cdc_linecoding_t linecoding = { + {0x00, 0x96, 0x00, 0x00}, /* 38400. */ + LC_STOP_1, LC_PARITY_NONE, 8 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/* + * Interface implementation. + */ + +static size_t writes(void *ip, const uint8_t *bp, size_t n) { + + return chOQWriteTimeout(&((SerialUSBDriver *)ip)->oqueue, bp, + n, TIME_INFINITE); +} + +static size_t reads(void *ip, uint8_t *bp, size_t n) { + + return chIQReadTimeout(&((SerialUSBDriver *)ip)->iqueue, bp, + n, TIME_INFINITE); +} + +static bool_t putwouldblock(void *ip) { + + return chOQIsFullI(&((SerialUSBDriver *)ip)->oqueue); +} + +static bool_t getwouldblock(void *ip) { + + return chIQIsEmptyI(&((SerialUSBDriver *)ip)->iqueue); +} + +static msg_t putt(void *ip, uint8_t b, systime_t timeout) { + + return chOQPutTimeout(&((SerialUSBDriver *)ip)->oqueue, b, timeout); +} + +static msg_t gett(void *ip, systime_t timeout) { + + return chIQGetTimeout(&((SerialUSBDriver *)ip)->iqueue, timeout); +} + +static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t time) { + + return chOQWriteTimeout(&((SerialUSBDriver *)ip)->oqueue, bp, n, time); +} + +static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t time) { + + return chIQReadTimeout(&((SerialUSBDriver *)ip)->iqueue, bp, n, time); +} + +static ioflags_t getflags(void *ip) { + _ch_get_and_clear_flags_impl(ip); +} + +static const struct SerialUSBDriverVMT vmt = { + writes, reads, putwouldblock, getwouldblock, + putt, gett, writet, readt, + getflags +}; + +/** + * @brief Notification of data removed from the input queue. + */ +static void inotify(GenericQueue *qp) { + SerialUSBDriver *sdup = (SerialUSBDriver *)qp->q_wrptr; + + /* Writes to the input queue can only happen when the queue has been + emptied, then a whole packet is loaded in the queue.*/ + if (!usbGetReceiveStatusI(sdup->config->usbp, USB_CDC_DATA_AVAILABLE_EP) && + chIQIsEmptyI(&sdup->iqueue)) { + chSysUnlock(); + + /* Unlocked to make the potentially long read operation preemptable.*/ + size_t n = usbReadPacketBuffer(sdup->config->usbp, + USB_CDC_DATA_AVAILABLE_EP, + sdup->iqueue.q_buffer, + SERIAL_USB_BUFFERS_SIZE); + + chSysLock(); + usbStartReceiveI(sdup->config->usbp, USB_CDC_DATA_AVAILABLE_EP); + chIOAddFlagsI(sdup, IO_INPUT_AVAILABLE); + sdup->iqueue.q_rdptr = sdup->iqueue.q_buffer; + sdup->iqueue.q_counter = n; + while (notempty(&sdup->iqueue.q_waiting)) + chSchReadyI(fifo_remove(&sdup->iqueue.q_waiting))->p_u.rdymsg = Q_OK; + } +} + +/** + * @brief Notification of data inserted into the output queue. + */ +static void onotify(GenericQueue *qp) { + SerialUSBDriver *sdup = (SerialUSBDriver *)qp->q_rdptr; + size_t n; + + /* If there is any data in the output queue then it is sent within a + single packet and the queue is emptied.*/ + n = chOQGetFullI(&sdup->oqueue); + if (!usbGetTransmitStatusI(sdup->config->usbp, USB_CDC_DATA_REQUEST_EP)) { + chSysUnlock(); + + /* Unlocked to make the potentially long write operation preemptable.*/ + usbWritePacketBuffer(sdup->config->usbp, USB_CDC_DATA_REQUEST_EP, + sdup->oqueue.q_buffer, n); + + chSysLock(); + usbStartTransmitI(sdup->config->usbp, USB_CDC_DATA_REQUEST_EP); + chIOAddFlagsI(sdup, IO_OUTPUT_EMPTY); + sdup->oqueue.q_wrptr = sdup->oqueue.q_buffer; + sdup->oqueue.q_counter = chQSizeI(&sdup->oqueue); + while (notempty(&sdup->oqueue.q_waiting)) + chSchReadyI(fifo_remove(&sdup->oqueue.q_waiting))->p_u.rdymsg = Q_OK; + } +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Serial Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void sduInit(void) { +} + +/** + * @brief Initializes a generic full duplex driver object. + * @details The HW dependent part of the initialization has to be performed + * outside, usually in the hardware initialization code. + * + * @param[out] sdup pointer to a @p SerialUSBDriver structure + * + * @init + */ +void sduObjectInit(SerialUSBDriver *sdup) { + + sdup->vmt = &vmt; + chEvtInit(&sdup->event); + sdup->flags = IO_NO_ERROR; + sdup->state = SDU_STOP; + chIQInit(&sdup->iqueue, sdup->ib, SERIAL_USB_BUFFERS_SIZE, inotify); + chOQInit(&sdup->oqueue, sdup->ob, SERIAL_USB_BUFFERS_SIZE, onotify); + /* This is a dirty trick but those pointers are never used because queues + are accessed in block mode from the low level.*/ + sdup->iqueue.q_wrptr = (uint8_t *)sdup; + sdup->oqueue.q_rdptr = (uint8_t *)sdup; +} + +/** + * @brief Configures and starts the driver. + * + * @param[in] sdup pointer to a @p SerialUSBDriver object + * @param[in] config the serial over USB driver configuration + * + * @api + */ +void sduStart(SerialUSBDriver *sdup, const SerialUSBConfig *config) { + + chDbgCheck(sdup != NULL, "sduStart"); + + chSysLock(); + chDbgAssert((sdup->state == SDU_STOP) || (sdup->state == SDU_READY), + "sduStart(), #1", + "invalid state"); + sdup->config = config; + config->usbp->param = sdup; + sdup->state = SDU_READY; + chSysUnlock(); + usbStart(config->usbp, &config->usb_config); +} + +/** + * @brief Stops the driver. + * @details Any thread waiting on the driver's queues will be awakened with + * the message @p Q_RESET. + * + * @param[in] sdup pointer to a @p SerialUSBDriver object + * + * @api + */ +void sduStop(SerialUSBDriver *sdup) { + + chDbgCheck(sdup != NULL, "sdStop"); + + chSysLock(); + chDbgAssert((sdup->state == SDU_STOP) || (sdup->state == SDU_READY), + "sduStop(), #1", + "invalid state"); + sdup->state = SDU_STOP; + chSysUnlock(); + usbStop(sdup->config->usbp); +} + +/** + * @brief Default requests hook. + * @details Applications wanting to use the Serial over USB driver can use + * this function as requests hook in the USB configuration. + * The following requests are emulated: + * - CDC_GET_LINE_CODING. + * - CDC_SET_LINE_CODING. + * - CDC_SET_CONTROL_LINE_STATE. + * . + * + * @param[in] usbp pointer to the @p USBDriver object + * @return The hook status. + * @retval TRUE Message handled internally. + * @retval FALSE Message not handled. + */ +bool_t sduRequestsHook(USBDriver *usbp) { + + if ((usbp->setup[0] & USB_RTYPE_TYPE_MASK) == USB_RTYPE_TYPE_CLASS) { + switch (usbp->setup[1]) { + case CDC_GET_LINE_CODING: + usbSetupTransfer(usbp, (uint8_t *)&linecoding, sizeof(linecoding), NULL); + return TRUE; + case CDC_SET_LINE_CODING: + usbSetupTransfer(usbp, (uint8_t *)&linecoding, sizeof(linecoding), NULL); + return TRUE; + case CDC_SET_CONTROL_LINE_STATE: + /* Nothing to do, there are no control lines.*/ + usbSetupTransfer(usbp, NULL, 0, NULL); + return TRUE; + default: + return FALSE; + } + } + return FALSE; +} + +/** + * @brief Default data transmitted callback. + * @details The application must use this function as callback for the IN + * data endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + */ +void sduDataTransmitted(USBDriver *usbp, usbep_t ep) { + SerialUSBDriver *sdup = usbp->param; + size_t n; + + chSysLockFromIsr(); + /* If there is any data in the output queue then it is sent within a + single packet and the queue is emptied.*/ + n = chOQGetFullI(&sdup->oqueue); + if (n > 0) { + /* The endpoint cannot be busy, we are in the context of the callback, + so it is safe to transmit without a check.*/ + chSysUnlockFromIsr(); + + /* Unlocked to make the potentially long write operation preemptable.*/ + usbWritePacketBuffer(usbp, ep, sdup->oqueue.q_buffer, n); + + chSysLockFromIsr(); + usbStartTransmitI(usbp, ep); + chIOAddFlagsI(sdup, IO_OUTPUT_EMPTY); + sdup->oqueue.q_wrptr = sdup->oqueue.q_buffer; + sdup->oqueue.q_counter = chQSizeI(&sdup->oqueue); + while (notempty(&sdup->oqueue.q_waiting)) + chSchReadyI(fifo_remove(&sdup->oqueue.q_waiting))->p_u.rdymsg = Q_OK; + } + chSysUnlockFromIsr(); +} + +/** + * @brief Default data received callback. + * @details The application must use this function as callback for the OUT + * data endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + */ +void sduDataReceived(USBDriver *usbp, usbep_t ep) { + SerialUSBDriver *sdup = usbp->param; + + chSysLockFromIsr(); + /* Writes to the input queue can only happen when the queue has been + emptied, then a whole packet is loaded in the queue.*/ + if (chIQIsEmptyI(&sdup->iqueue)) { + /* The endpoint cannot be busy, we are in the context of the callback, + so a packet is in the buffer for sure.*/ + size_t n; + + chSysUnlockFromIsr(); + + /* Unlocked to make the potentially long write operation preemptable.*/ + n = usbReadPacketBuffer(usbp, ep, sdup->iqueue.q_buffer, + SERIAL_USB_BUFFERS_SIZE); + + chSysLockFromIsr(); + usbStartReceiveI(usbp, ep); + chIOAddFlagsI(sdup, IO_INPUT_AVAILABLE); + sdup->iqueue.q_rdptr = sdup->iqueue.q_buffer; + sdup->iqueue.q_counter = n; + while (notempty(&sdup->iqueue.q_waiting)) + chSchReadyI(fifo_remove(&sdup->iqueue.q_waiting))->p_u.rdymsg = Q_OK; + } + chSysUnlockFromIsr(); +} + +/** + * @brief Default data received callback. + * @details The application must use this function as callback for the IN + * interrupt endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + */ +void sduInterruptTransmitted(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + (void)ep; +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/Project/os/hal/src/spi.c b/Project/os/hal/src/spi.c new file mode 100644 index 0000000..08d4171 --- /dev/null +++ b/Project/os/hal/src/spi.c @@ -0,0 +1,447 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file spi.c + * @brief SPI Driver code. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief SPI Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void spiInit(void) { + + spi_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p SPIDriver structure. + * + * @param[out] spip pointer to the @p SPIDriver object + * + * @init + */ +void spiObjectInit(SPIDriver *spip) { + + spip->state = SPI_STOP; + spip->config = NULL; +#if SPI_USE_WAIT + spip->thread = NULL; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION +#if CH_USE_MUTEXES + chMtxInit(&spip->mutex); +#else + chSemInit(&spip->semaphore, 1); +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_INIT_HOOK) + SPI_DRIVER_EXT_INIT_HOOK(spip); +#endif +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] config pointer to the @p SPIConfig object + * + * @api + */ +void spiStart(SPIDriver *spip, const SPIConfig *config) { + + chDbgCheck((spip != NULL) && (config != NULL), "spiStart"); + + chSysLock(); + chDbgAssert((spip->state == SPI_STOP) || (spip->state == SPI_READY), + "spiStart(), #1", "invalid state"); + spip->config = config; + spi_lld_start(spip); + spip->state = SPI_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the SPI peripheral. + * @note Deactivating the peripheral also enforces a release of the slave + * select line. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @api + */ +void spiStop(SPIDriver *spip) { + + chDbgCheck(spip != NULL, "spiStop"); + + chSysLock(); + chDbgAssert((spip->state == SPI_STOP) || (spip->state == SPI_READY), + "spiStop(), #1", "invalid state"); + spi_lld_unselect(spip); + spi_lld_stop(spip); + spip->state = SPI_STOP; + chSysUnlock(); +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @api + */ +void spiSelect(SPIDriver *spip) { + + chDbgCheck(spip != NULL, "spiSelect"); + + chSysLock(); + chDbgAssert(spip->state == SPI_READY, "spiSelect(), #1", "not ready"); + spiSelectI(spip); + chSysUnlock(); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @api + */ +void spiUnselect(SPIDriver *spip) { + + chDbgCheck(spip != NULL, "spiUnselect"); + + chSysLock(); + chDbgAssert(spip->state == SPI_READY, "spiUnselect(), #1", "not ready"); + spiUnselectI(spip); + chSysUnlock(); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This asynchronous function starts the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @pre A slave must have been selected using @p spiSelect() or + * @p spiSelectI(). + * @post At the end of the operation the configured callback is invoked. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @api + */ +void spiStartIgnore(SPIDriver *spip, size_t n) { + + chDbgCheck((spip != NULL) && (n > 0), "spiStartIgnore"); + + chSysLock(); + chDbgAssert(spip->state == SPI_READY, "spiStartIgnore(), #1", "not ready"); + spiStartIgnoreI(spip, n); + chSysUnlock(); +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @pre A slave must have been selected using @p spiSelect() or + * @p spiSelectI(). + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @api + */ +void spiStartExchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL) && (txbuf != NULL), + "spiStartExchange"); + + chSysLock(); + chDbgAssert(spip->state == SPI_READY, "spiStartExchange(), #1", "not ready"); + spiStartExchangeI(spip, n, txbuf, rxbuf); + chSysUnlock(); +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @pre A slave must have been selected using @p spiSelect() or + * @p spiSelectI(). + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @api + */ +void spiStartSend(SPIDriver *spip, size_t n, const void *txbuf) { + + chDbgCheck((spip != NULL) && (n > 0) && (txbuf != NULL), + "spiStartSend"); + + chSysLock(); + chDbgAssert(spip->state == SPI_READY, "spiStartSend(), #1", "not ready"); + spiStartSendI(spip, n, txbuf); + chSysUnlock(); +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @pre A slave must have been selected using @p spiSelect() or + * @p spiSelectI(). + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @api + */ +void spiStartReceive(SPIDriver *spip, size_t n, void *rxbuf) { + + chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL), + "spiStartReceive"); + + chSysLock(); + chDbgAssert(spip->state == SPI_READY, "spiStartReceive(), #1", "not ready"); + spiStartReceiveI(spip, n, rxbuf); + chSysUnlock(); +} + +#if SPI_USE_WAIT || defined(__DOXYGEN__) +/** + * @brief Ignores data on the SPI bus. + * @details This synchronous function performs the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @pre In order to use this function the option @p SPI_USE_WAIT must be + * enabled. + * @pre In order to use this function the driver must have been configured + * without callbacks (@p end_cb = @p NULL). + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @api + */ +void spiIgnore(SPIDriver *spip, size_t n) { + + chDbgCheck((spip != NULL) && (n > 0), "spiIgnoreWait"); + + chSysLock(); + chDbgAssert(spip->state == SPI_READY, "spiIgnore(), #1", "not ready"); + chDbgAssert(spip->config->end_cb == NULL, "spiIgnore(), #2", "has callback"); + spiStartIgnoreI(spip, n); + _spi_wait_s(spip); + chSysUnlock(); +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This synchronous function performs a simultaneous transmit/receive + * operation. + * @pre In order to use this function the option @p SPI_USE_WAIT must be + * enabled. + * @pre In order to use this function the driver must have been configured + * without callbacks (@p end_cb = @p NULL). + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @api + */ +void spiExchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL) && (txbuf != NULL), + "spiExchange"); + + chSysLock(); + chDbgAssert(spip->state == SPI_READY, "spiExchange(), #1", "not ready"); + chDbgAssert(spip->config->end_cb == NULL, + "spiExchange(), #2", "has callback"); + spiStartExchangeI(spip, n, txbuf, rxbuf); + _spi_wait_s(spip); + chSysUnlock(); +} + +/** + * @brief Sends data over the SPI bus. + * @details This synchronous function performs a transmit operation. + * @pre In order to use this function the option @p SPI_USE_WAIT must be + * enabled. + * @pre In order to use this function the driver must have been configured + * without callbacks (@p end_cb = @p NULL). + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @api + */ +void spiSend(SPIDriver *spip, size_t n, const void *txbuf) { + + chDbgCheck((spip != NULL) && (n > 0) && (txbuf != NULL), "spiSend"); + + chSysLock(); + chDbgAssert(spip->state == SPI_READY, "spiSend(), #1", "not ready"); + chDbgAssert(spip->config->end_cb == NULL, "spiSend(), #2", "has callback"); + spiStartSendI(spip, n, txbuf); + _spi_wait_s(spip); + chSysUnlock(); +} + +/** + * @brief Receives data from the SPI bus. + * @details This synchronous function performs a receive operation. + * @pre In order to use this function the option @p SPI_USE_WAIT must be + * enabled. + * @pre In order to use this function the driver must have been configured + * without callbacks (@p end_cb = @p NULL). + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @api + */ +void spiReceive(SPIDriver *spip, size_t n, void *rxbuf) { + + chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL), + "spiReceive"); + + chSysLock(); + chDbgAssert(spip->state == SPI_READY, "spiReceive(), #1", "not ready"); + chDbgAssert(spip->config->end_cb == NULL, + "spiReceive(), #2", "has callback"); + spiStartReceiveI(spip, n, rxbuf); + _spi_wait_s(spip); + chSysUnlock(); +} +#endif /* SPI_USE_WAIT */ + +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +/** + * @brief Gains exclusive access to the SPI bus. + * @details This function tries to gain ownership to the SPI bus, if the bus + * is already being used then the invoking thread is queued. + * @pre In order to use this function the option @p SPI_USE_MUTUAL_EXCLUSION + * must be enabled. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @api + */ +void spiAcquireBus(SPIDriver *spip) { + + chDbgCheck(spip != NULL, "spiAcquireBus"); + +#if CH_USE_MUTEXES + chMtxLock(&spip->mutex); +#elif CH_USE_SEMAPHORES + chSemWait(&spip->semaphore); +#endif +} + +/** + * @brief Releases exclusive access to the SPI bus. + * @pre In order to use this function the option @p SPI_USE_MUTUAL_EXCLUSION + * must be enabled. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @api + */ +void spiReleaseBus(SPIDriver *spip) { + + chDbgCheck(spip != NULL, "spiReleaseBus"); + +#if CH_USE_MUTEXES + (void)spip; + chMtxUnlock(); +#elif CH_USE_SEMAPHORES + chSemSignal(&spip->semaphore); +#endif +} +#endif /* SPI_USE_MUTUAL_EXCLUSION */ + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/Project/os/hal/src/tm.c b/Project/os/hal/src/tm.c new file mode 100644 index 0000000..a03b9d3 --- /dev/null +++ b/Project/os/hal/src/tm.c @@ -0,0 +1,135 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file tm.c + * @brief Time Measurement driver code. + * + * @addtogroup TM + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_TM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** + * @brief Subsystem calibration value. + */ +static halrtcnt_t measurement_offset; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Starts a measurement. + * + * @param[in,out] tmp pointer to a @p TimeMeasurement structure + * + * @notapi + */ +static void tm_start(TimeMeasurement *tmp) { + + tmp->last = halGetCounterValue(); +} + +/** + * @brief Stops a measurement. + * + * @param[in,out] tmp pointer to a @p TimeMeasurement structure + * + * @notapi + */ +static void tm_stop(TimeMeasurement *tmp) { + + halrtcnt_t now = halGetCounterValue(); + tmp->last = now - tmp->last - measurement_offset; + if (tmp->last > tmp->worst) + tmp->worst = tmp->last; + else if (tmp->last < tmp->best) + tmp->best = tmp->last; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the Time Measurement unit. + * + * @init + */ +void tmInit(void) { + TimeMeasurement tm; + + /* Time Measurement subsystem calibration, it does a null measurement + and calculates the call overhead which is subtracted to real + measurements.*/ + measurement_offset = 0; + tmObjectInit(&tm); + tmStartMeasurement(&tm); + tmStopMeasurement(&tm); + measurement_offset = tm.last; +} + +/** + * @brief Initializes a @p TimeMeasurement object. + * + * @param[out] tmp pointer to a @p TimeMeasurement structure + * + * @init + */ +void tmObjectInit(TimeMeasurement *tmp) { + + tmp->start = tm_start; + tmp->stop = tm_stop; + tmp->last = (halrtcnt_t)0; + tmp->worst = (halrtcnt_t)0; + tmp->best = (halrtcnt_t)-1; +} + +#endif /* HAL_USE_TM */ + +/** @} */ diff --git a/Project/os/hal/src/uart.c b/Project/os/hal/src/uart.c new file mode 100644 index 0000000..c873429 --- /dev/null +++ b/Project/os/hal/src/uart.c @@ -0,0 +1,353 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file uart.c + * @brief UART Driver code. + * + * @addtogroup UART + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief UART Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void uartInit(void) { + + uart_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p UARTDriver structure. + * + * @param[out] uartp pointer to the @p UARTDriver object + * + * @init + */ +void uartObjectInit(UARTDriver *uartp) { + + uartp->state = UART_STOP; + uartp->txstate = UART_TX_IDLE; + uartp->rxstate = UART_RX_IDLE; + uartp->config = NULL; + /* Optional, user-defined initializer.*/ +#if defined(UART_DRIVER_EXT_INIT_HOOK) + UART_DRIVER_EXT_INIT_HOOK(uartp); +#endif +} + +/** + * @brief Configures and activates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] config pointer to the @p UARTConfig object + * + * @api + */ +void uartStart(UARTDriver *uartp, const UARTConfig *config) { + + chDbgCheck((uartp != NULL) && (config != NULL), "uartStart"); + + chSysLock(); + chDbgAssert((uartp->state == UART_STOP) || (uartp->state == UART_READY), + "uartStart(), #1", "invalid state"); + + uartp->config = config; + uart_lld_start(uartp); + uartp->state = UART_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @api + */ +void uartStop(UARTDriver *uartp) { + + chDbgCheck(uartp != NULL, "uartStop"); + + chSysLock(); + chDbgAssert((uartp->state == UART_STOP) || (uartp->state == UART_READY), + "uartStop(), #1", "invalid state"); + + uart_lld_stop(uartp); + uartp->state = UART_STOP; + uartp->txstate = UART_TX_IDLE; + uartp->rxstate = UART_RX_IDLE; + chSysUnlock(); +} + +/** + * @brief Starts a transmission on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @api + */ +void uartStartSend(UARTDriver *uartp, size_t n, const void *txbuf) { + + chDbgCheck((uartp != NULL) && (n > 0) && (txbuf != NULL), + "uartStartSend"); + + chSysLock(); + chDbgAssert((uartp->state == UART_READY) && (uartp->txstate == UART_TX_IDLE), + "uartStartSend(), #1", "not active"); + + uart_lld_start_send(uartp, n, txbuf); + uartp->txstate = UART_TX_ACTIVE; + chSysUnlock(); +} + +/** + * @brief Starts a transmission on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * @note This function has to be invoked from a lock zone. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @iclass + */ +void uartStartSendI(UARTDriver *uartp, size_t n, const void *txbuf) { + + chDbgCheckClassI(); + chDbgCheck((uartp != NULL) && (n > 0) && (txbuf != NULL), + "uartStartSendI"); + chDbgAssert((uartp->state == UART_READY) && + (uartp->txstate != UART_TX_ACTIVE), + "uartStartSendI(), #1", "not active"); + + uart_lld_start_send(uartp, n, txbuf); + uartp->txstate = UART_TX_ACTIVE; +} + +/** + * @brief Stops any ongoing transmission. + * @note Stopping a transmission also suppresses the transmission callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not transmitted by the + * stopped transmit operation. + * @retval 0 There was no transmit operation in progress. + * + * @api + */ +size_t uartStopSend(UARTDriver *uartp) { + size_t n; + + chDbgCheck(uartp != NULL, "uartStopSend"); + + chSysLock(); + chDbgAssert(uartp->state == UART_READY, "uartStopSend(), #1", "not active"); + + if (uartp->txstate == UART_TX_ACTIVE) { + n = uart_lld_stop_send(uartp); + uartp->txstate = UART_TX_IDLE; + } + else + n = 0; + chSysUnlock(); + return n; +} + +/** + * @brief Stops any ongoing transmission. + * @note Stopping a transmission also suppresses the transmission callbacks. + * @note This function has to be invoked from a lock zone. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not transmitted by the + * stopped transmit operation. + * @retval 0 There was no transmit operation in progress. + * + * @iclass + */ +size_t uartStopSendI(UARTDriver *uartp) { + + chDbgCheckClassI(); + chDbgCheck(uartp != NULL, "uartStopSendI"); + chDbgAssert(uartp->state == UART_READY, "uartStopSendI(), #1", "not active"); + + if (uartp->txstate == UART_TX_ACTIVE) { + size_t n = uart_lld_stop_send(uartp); + uartp->txstate = UART_TX_IDLE; + return n; + } + return 0; +} + +/** + * @brief Starts a receive operation on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[in] rxbuf the pointer to the receive buffer + * + * @api + */ +void uartStartReceive(UARTDriver *uartp, size_t n, void *rxbuf) { + + chDbgCheck((uartp != NULL) && (n > 0) && (rxbuf != NULL), + "uartStartReceive"); + + chSysLock(); + chDbgAssert((uartp->state == UART_READY) && (uartp->rxstate == UART_RX_IDLE), + "uartStartReceive(), #1", "not active"); + + uart_lld_start_receive(uartp, n, rxbuf); + uartp->rxstate = UART_RX_ACTIVE; + chSysUnlock(); +} + +/** + * @brief Starts a receive operation on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * @note This function has to be invoked from a lock zone. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[out] rxbuf the pointer to the receive buffer + * + * @iclass + */ +void uartStartReceiveI(UARTDriver *uartp, size_t n, void *rxbuf) { + + chDbgCheckClassI(); + chDbgCheck((uartp != NULL) && (n > 0) && (rxbuf != NULL), + "uartStartReceiveI"); + chDbgAssert((uartp->state == UART_READY) && (uartp->rxstate == UART_RX_IDLE), + "uartStartReceiveI(), #1", "not active"); + + uart_lld_start_receive(uartp, n, rxbuf); + uartp->rxstate = UART_RX_ACTIVE; +} + +/** + * @brief Stops any ongoing receive operation. + * @note Stopping a receive operation also suppresses the receive callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not received by the + * stopped receive operation. + * @retval 0 There was no receive operation in progress. + * + * @api + */ +size_t uartStopReceive(UARTDriver *uartp) { + size_t n; + + chDbgCheck(uartp != NULL, "uartStopReceive"); + + chSysLock(); + chDbgAssert(uartp->state == UART_READY, + "uartStopReceive(), #1", "not active"); + + if (uartp->rxstate == UART_RX_ACTIVE) { + n = uart_lld_stop_receive(uartp); + uartp->rxstate = UART_RX_IDLE; + } + else + n = 0; + chSysUnlock(); + return n; +} + +/** + * @brief Stops any ongoing receive operation. + * @note Stopping a receive operation also suppresses the receive callbacks. + * @note This function has to be invoked from a lock zone. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not received by the + * stopped receive operation. + * @retval 0 There was no receive operation in progress. + * + * @iclass + */ +size_t uartStopReceiveI(UARTDriver *uartp) { + + chDbgCheckClassI(); + chDbgCheck(uartp != NULL, "uartStopReceiveI"); + chDbgAssert(uartp->state == UART_READY, + "uartStopReceiveI(), #1", "not active"); + + if (uartp->rxstate == UART_RX_ACTIVE) { + size_t n = uart_lld_stop_receive(uartp); + uartp->rxstate = UART_RX_IDLE; + return n; + } + return 0; +} + +#endif /* HAL_USE_UART */ + +/** @} */ diff --git a/Project/os/hal/src/usb.c b/Project/os/hal/src/usb.c new file mode 100644 index 0000000..9e5f6e3 --- /dev/null +++ b/Project/os/hal/src/usb.c @@ -0,0 +1,658 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file usb.c + * @brief USB Driver code. + * + * @addtogroup USB + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" +#include "usb.h" + +#if HAL_USE_USB || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +static const uint8_t zero_status[] = {0x00, 0x00}; +static const uint8_t active_status[] ={0x00, 0x00}; +static const uint8_t halted_status[] = {0x01, 0x00}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief SET ADDRESS transaction callback. + * + * @param[in] usbp pointer to the @p USBDriver object + */ +static void set_address(USBDriver *usbp) { + + usbp->address = usbp->setup[2]; + usb_lld_set_address(usbp); + _usb_isr_invoke_event_cb(usbp, USB_EVENT_ADDRESS); + usbp->state = USB_SELECTED; +} + +/** + * @brief Standard requests handler. + * @details This is the standard requests default handler, most standard + * requests are handled here, the user can override the standard + * handling using the @p requests_hook_cb hook in the + * @p USBConfig structure. + * + * @param[in] usbp pointer to the @p USBDriver object + * @return The request handling exit code. + * @retval FALSE Request not recognized by the handler or error. + * @retval TRUE Request handled. + */ +static bool_t default_handler(USBDriver *usbp) { + const USBDescriptor *dp; + + /* Decoding the request.*/ + switch (((usbp->setup[0] & (USB_RTYPE_RECIPIENT_MASK | + USB_RTYPE_TYPE_MASK)) | + (usbp->setup[1] << 8))) { + case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_GET_STATUS << 8): + /* Just returns the current status word.*/ + usbSetupTransfer(usbp, (uint8_t *)&usbp->status, 2, NULL); + return TRUE; + case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_CLEAR_FEATURE << 8): + /* Only the DEVICE_REMOTE_WAKEUP is handled here, any other feature + number is handled as an error.*/ + if (usbp->setup[2] == USB_FEATURE_DEVICE_REMOTE_WAKEUP) { + usbp->status &= ~2; + usbSetupTransfer(usbp, NULL, 0, NULL); + return TRUE; + } + return FALSE; + case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_SET_FEATURE << 8): + /* Only the DEVICE_REMOTE_WAKEUP is handled here, any other feature + number is handled as an error.*/ + if (usbp->setup[2] == USB_FEATURE_DEVICE_REMOTE_WAKEUP) { + usbp->status |= 2; + usbSetupTransfer(usbp, NULL, 0, NULL); + return TRUE; + } + return FALSE; + case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_SET_ADDRESS << 8): + /* The SET_ADDRESS handling can be performed here or postponed after + the status packed depending on the USB_SET_ADDRESS_MODE low + driver setting.*/ +#if USB_SET_ADDRESS_MODE == USB_EARLY_SET_ADDRESS + if ((usbp->setup[0] == USB_RTYPE_RECIPIENT_DEVICE) && + (usbp->setup[1] == USB_REQ_SET_ADDRESS)) + set_address(usbp); + usbSetupTransfer(usbp, NULL, 0, NULL); +#else + usbSetupTransfer(usbp, NULL, 0, set_address); +#endif + return TRUE; + case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_GET_DESCRIPTOR << 8): + /* Handling descriptor requests from the host.*/ + dp = usbp->config->get_descriptor_cb( + usbp, usbp->setup[3], usbp->setup[2], + usb_lld_fetch_word(&usbp->setup[4])); + if (dp == NULL) + return FALSE; + usbSetupTransfer(usbp, (uint8_t *)dp->ud_string, dp->ud_size, NULL); + return TRUE; + case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_GET_CONFIGURATION << 8): + /* Returning the last selected configuration.*/ + usbSetupTransfer(usbp, &usbp->configuration, 1, NULL); + return TRUE; + case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_SET_CONFIGURATION << 8): + /* Handling configuration selection from the host.*/ + usbp->configuration = usbp->setup[2]; + if (usbp->configuration == 0) + usbp->state = USB_SELECTED; + else + usbp->state = USB_ACTIVE; + _usb_isr_invoke_event_cb(usbp, USB_EVENT_CONFIGURED); + usbSetupTransfer(usbp, NULL, 0, NULL); + return TRUE; + case USB_RTYPE_RECIPIENT_INTERFACE | (USB_REQ_GET_STATUS << 8): + case USB_RTYPE_RECIPIENT_ENDPOINT | (USB_REQ_SYNCH_FRAME << 8): + /* Just sending two zero bytes, the application can change the behavior + using a hook..*/ + usbSetupTransfer(usbp, (uint8_t *)zero_status, 2, NULL); + return TRUE; + case USB_RTYPE_RECIPIENT_ENDPOINT | (USB_REQ_GET_STATUS << 8): + /* Sending the EP status.*/ + if (usbp->setup[4] & 0x80) { + switch (usb_lld_get_status_in(usbp, usbp->setup[4] & 0x0F)) { + case EP_STATUS_STALLED: + usbSetupTransfer(usbp, (uint8_t *)halted_status, 2, NULL); + return TRUE; + case EP_STATUS_ACTIVE: + usbSetupTransfer(usbp, (uint8_t *)active_status, 2, NULL); + return TRUE; + default: + return FALSE; + } + } + else { + switch (usb_lld_get_status_out(usbp, usbp->setup[4] & 0x0F)) { + case EP_STATUS_STALLED: + usbSetupTransfer(usbp, (uint8_t *)halted_status, 2, NULL); + return TRUE; + case EP_STATUS_ACTIVE: + usbSetupTransfer(usbp, (uint8_t *)active_status, 2, NULL); + return TRUE; + default: + return FALSE; + } + } + case USB_RTYPE_RECIPIENT_ENDPOINT | (USB_REQ_CLEAR_FEATURE << 8): + /* Only ENDPOINT_HALT is handled as feature.*/ + if (usbp->setup[2] != USB_FEATURE_ENDPOINT_HALT) + return FALSE; + /* Clearing the EP status, not valid for EP0, it is ignored in that case.*/ + if ((usbp->setup[4] & 0x0F) > 0) { + if (usbp->setup[4] & 0x80) + usb_lld_clear_in(usbp, usbp->setup[4] & 0x0F); + else + usb_lld_clear_out(usbp, usbp->setup[4] & 0x0F); + } + usbSetupTransfer(usbp, NULL, 0, NULL); + return TRUE; + case USB_RTYPE_RECIPIENT_ENDPOINT | (USB_REQ_SET_FEATURE << 8): + /* Only ENDPOINT_HALT is handled as feature.*/ + if (usbp->setup[2] != USB_FEATURE_ENDPOINT_HALT) + return FALSE; + /* Stalling the EP, not valid for EP0, it is ignored in that case.*/ + if ((usbp->setup[4] & 0x0F) > 0) { + if (usbp->setup[4] & 0x80) + usb_lld_stall_in(usbp, usbp->setup[4] & 0x0F); + else + usb_lld_stall_out(usbp, usbp->setup[4] & 0x0F); + } + usbSetupTransfer(usbp, NULL, 0, NULL); + return TRUE; + case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_SET_DESCRIPTOR << 8): + case USB_RTYPE_RECIPIENT_INTERFACE | (USB_REQ_CLEAR_FEATURE << 8): + case USB_RTYPE_RECIPIENT_INTERFACE | (USB_REQ_SET_FEATURE << 8): + case USB_RTYPE_RECIPIENT_INTERFACE | (USB_REQ_GET_INTERFACE << 8): + case USB_RTYPE_RECIPIENT_INTERFACE | (USB_REQ_SET_INTERFACE << 8): + /* All the above requests are not handled here, if you need them then + use the hook mechanism and provide handling.*/ + default: + return FALSE; + } +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief USB Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void usbInit(void) { + + usb_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p USBDriver structure. + * + * @param[out] usbp pointer to the @p USBDriver object + * + * @init + */ +void usbObjectInit(USBDriver *usbp) { + + usbp->state = USB_STOP; + usbp->config = NULL; + usbp->param = NULL; + usbp->transmitting = 0; + usbp->receiving = 0; +} + +/** + * @brief Configures and activates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] config pointer to the @p USBConfig object + * + * @api + */ +void usbStart(USBDriver *usbp, const USBConfig *config) { + unsigned i; + + chDbgCheck((usbp != NULL) && (config != NULL), "usbStart"); + + chSysLock(); + chDbgAssert((usbp->state == USB_STOP) || (usbp->state == USB_READY), + "usbStart(), #1", "invalid state"); + usbp->config = config; + for (i = 0; i <= USB_MAX_ENDPOINTS; i++) + usbp->epc[i] = NULL; + usb_lld_start(usbp); + usbp->state = USB_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @api + */ +void usbStop(USBDriver *usbp) { + + chDbgCheck(usbp != NULL, "usbStop"); + + chSysLock(); + chDbgAssert((usbp->state == USB_STOP) || (usbp->state == USB_READY), + "usbStop(), #1", "invalid state"); + usb_lld_stop(usbp); + usbp->state = USB_STOP; + chSysUnlock(); +} + +/** + * @brief Enables an endpoint. + * @details This function enables an endpoint, both IN and/or OUT directions + * depending on the configuration structure. + * @note This function must be invoked in response of a SET_CONFIGURATION + * or SET_INTERFACE message. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[in] epcp the endpoint configuration + * + * @iclass + */ +void usbInitEndpointI(USBDriver *usbp, usbep_t ep, + const USBEndpointConfig *epcp) { + + chDbgCheckClassI(); + chDbgCheck((usbp != NULL) && (epcp != NULL), "usbInitEndpointI"); + chDbgAssert(usbp->state == USB_ACTIVE, + "usbEnableEndpointI(), #1", "invalid state"); + chDbgAssert(usbp->epc[ep] == NULL, + "usbEnableEndpointI(), #2", "already initialized"); + + /* Logically enabling the endpoint in the USBDriver structure.*/ + if (!(epcp->ep_mode & USB_EP_MODE_PACKET)) { + memset(epcp->in_state, 0, sizeof(USBInEndpointState)); + memset(epcp->out_state, 0, sizeof(USBOutEndpointState)); + } + usbp->epc[ep] = epcp; + + /* Low level endpoint activation.*/ + usb_lld_init_endpoint(usbp, ep); +} + +/** + * @brief Disables all the active endpoints. + * @details This function disables all the active endpoints except the + * endpoint zero. + * @note This function must be invoked in response of a SET_CONFIGURATION + * message with configuration number zero. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @iclass + */ +void usbDisableEndpointsI(USBDriver *usbp) { + unsigned i; + + chDbgCheckClassI(); + chDbgCheck(usbp != NULL, "usbDisableEndpointsI"); + chDbgAssert(usbp->state == USB_SELECTED, + "usbDisableEndpointsI(), #1", "invalid state"); + + usbp->transmitting &= ~1; + usbp->receiving &= ~1; + for (i = 1; i <= USB_MAX_ENDPOINTS; i++) + usbp->epc[i] = NULL; + + /* Low level endpoints deactivation.*/ + usb_lld_disable_endpoints(usbp); +} + +/** + * @brief Starts a receive transaction on an OUT endpoint. + * @post The endpoint callback is invoked when the transfer has been + * completed. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The operation status. + * @retval FALSE Operation started successfully. + * @retval TRUE Endpoint busy, operation not started. + * + * @iclass + */ +bool_t usbStartReceiveI(USBDriver *usbp, usbep_t ep) { + + chDbgCheckClassI(); + chDbgCheck(usbp != NULL, "usbStartReceiveI"); + + if (usbGetReceiveStatusI(usbp, ep)) + return TRUE; + + usbp->receiving |= (1 << ep); + usb_lld_start_out(usbp, ep); + return FALSE; +} + +/** + * @brief Starts a transmit transaction on an IN endpoint. + * @post The endpoint callback is invoked when the transfer has been + * completed. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The operation status. + * @retval FALSE Operation started successfully. + * @retval TRUE Endpoint busy, operation not started. + * + * @iclass + */ +bool_t usbStartTransmitI(USBDriver *usbp, usbep_t ep) { + + chDbgCheckClassI(); + chDbgCheck(usbp != NULL, "usbStartTransmitI"); + + if (usbGetTransmitStatusI(usbp, ep)) + return TRUE; + + usbp->transmitting |= (1 << ep); + usb_lld_start_in(usbp, ep); + return FALSE; +} + +/** + * @brief Stalls an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The operation status. + * @retval FALSE Endpoint stalled. + * @retval TRUE Endpoint busy, not stalled. + * + * @iclass + */ +bool_t usbStallReceiveI(USBDriver *usbp, usbep_t ep) { + + chDbgCheckClassI(); + chDbgCheck(usbp != NULL, "usbStallReceiveI"); + + if (usbGetReceiveStatusI(usbp, ep)) + return TRUE; + + usb_lld_stall_out(usbp, ep); + return FALSE; +} + +/** + * @brief Stalls an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The operation status. + * @retval FALSE Endpoint stalled. + * @retval TRUE Endpoint busy, not stalled. + * + * @iclass + */ +bool_t usbStallTransmitI(USBDriver *usbp, usbep_t ep) { + + chDbgCheckClassI(); + chDbgCheck(usbp != NULL, "usbStallTransmitI"); + + if (usbGetTransmitStatusI(usbp, ep)) + return TRUE; + + usb_lld_stall_in(usbp, ep); + return FALSE; +} + +/** + * @brief USB reset routine. + * @details This function must be invoked when an USB bus reset condition is + * detected. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void _usb_reset(USBDriver *usbp) { + unsigned i; + + usbp->state = USB_READY; + usbp->status = 0; + usbp->address = 0; + usbp->configuration = 0; + usbp->transmitting = 0; + usbp->receiving = 0; + + /* Invalidates all endpoints into the USBDriver structure.*/ + for (i = 0; i <= USB_MAX_ENDPOINTS; i++) + usbp->epc[i] = NULL; + + /* EP0 state machine initialization.*/ + usbp->ep0state = USB_EP0_WAITING_SETUP; + + /* Low level reset.*/ + usb_lld_reset(usbp); +} + +/** + * @brief Default EP0 SETUP callback. + * @details This function is used by the low level driver as default handler + * for EP0 SETUP events. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number, always zero + * + * @notapi + */ +void _usb_ep0setup(USBDriver *usbp, usbep_t ep) { + size_t max; + + usbp->ep0state = USB_EP0_WAITING_SETUP; + usbReadSetup(usbp, ep, usbp->setup); + + /* First verify if the application has an handler installed for this + request.*/ + if (!(usbp->config->requests_hook_cb) || + !(usbp->config->requests_hook_cb(usbp))) { + /* Invoking the default handler, if this fails then stalls the + endpoint zero as error.*/ + if (((usbp->setup[0] & USB_RTYPE_TYPE_MASK) != USB_RTYPE_TYPE_STD) || + !default_handler(usbp)) { + /* Error response, the state machine goes into an error state, the low + level layer will have to reset it to USB_EP0_WAITING_SETUP after + receiving a SETUP packet.*/ + usb_lld_stall_in(usbp, 0); + usb_lld_stall_out(usbp, 0); + _usb_isr_invoke_event_cb(usbp, USB_EVENT_STALLED); + usbp->ep0state = USB_EP0_ERROR; + return; + } + } + + /* Transfer preparation. The request handler must have populated + correctly the fields ep0next, ep0n and ep0endcb using the macro + usbSetupTransfer().*/ + max = usb_lld_fetch_word(&usbp->setup[6]); + /* The transfer size cannot exceed the specified amount.*/ + if (usbp->ep0n > max) + usbp->ep0n = max; + if ((usbp->setup[0] & USB_RTYPE_DIR_MASK) == USB_RTYPE_DIR_DEV2HOST) { + /* IN phase.*/ + if (usbp->ep0n > 0) { + /* Starts the transmit phase.*/ + usbp->ep0state = USB_EP0_TX; + usb_lld_prepare_transmit(usbp, 0, usbp->ep0next, usbp->ep0n); + usb_lld_start_in(usbp, 0); + } + else { + /* No transmission phase, directly receiving the zero sized status + packet.*/ + usbp->ep0state = USB_EP0_WAITING_STS; + usb_lld_prepare_receive(usbp, 0, NULL, 0); + usb_lld_start_out(usbp, 0); + } + } + else { + /* OUT phase.*/ + if (usbp->ep0n > 0) { + /* Starts the receive phase.*/ + usbp->ep0state = USB_EP0_RX; + usb_lld_prepare_receive(usbp, 0, usbp->ep0next, usbp->ep0n); + usb_lld_start_out(usbp, 0); + } + else { + /* No receive phase, directly sending the zero sized status + packet.*/ + usbp->ep0state = USB_EP0_SENDING_STS; + usb_lld_prepare_transmit(usbp, 0, NULL, 0); + usb_lld_start_in(usbp, 0); + } + } +} + +/** + * @brief Default EP0 IN callback. + * @details This function is used by the low level driver as default handler + * for EP0 IN events. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number, always zero + * + * @notapi + */ +void _usb_ep0in(USBDriver *usbp, usbep_t ep) { + size_t max; + + (void)ep; + switch (usbp->ep0state) { + case USB_EP0_TX: + max = usb_lld_fetch_word(&usbp->setup[6]); + /* If the transmitted size is less than the requested size and it is a + multiple of the maximum packet size then a zero size packet must be + transmitted.*/ + if ((usbp->ep0n < max) && + ((usbp->ep0n % usbp->epc[0]->in_maxsize) == 0)) { + usb_lld_prepare_transmit(usbp, 0, NULL, 0); + usb_lld_start_in(usbp, 0); + return; + } + + /* Transmit phase over, receiving the zero sized status packet.*/ + usbp->ep0state = USB_EP0_WAITING_STS; + usb_lld_prepare_receive(usbp, 0, NULL, 0); + usb_lld_start_out(usbp, 0); + return; + case USB_EP0_SENDING_STS: + /* Status packet sent, invoking the callback if defined.*/ + if (usbp->ep0endcb != NULL) + usbp->ep0endcb(usbp); + usbp->ep0state = USB_EP0_WAITING_SETUP; + return; + default: + ; + } + /* Error response, the state machine goes into an error state, the low + level layer will have to reset it to USB_EP0_WAITING_SETUP after + receiving a SETUP packet.*/ + usb_lld_stall_in(usbp, 0); + usb_lld_stall_out(usbp, 0); + _usb_isr_invoke_event_cb(usbp, USB_EVENT_STALLED); + usbp->ep0state = USB_EP0_ERROR; +} + +/** + * @brief Default EP0 OUT callback. + * @details This function is used by the low level driver as default handler + * for EP0 OUT events. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number, always zero + * + * @notapi + */ +void _usb_ep0out(USBDriver *usbp, usbep_t ep) { + + (void)ep; + switch (usbp->ep0state) { + case USB_EP0_RX: + /* Receive phase over, sending the zero sized status packet.*/ + usbp->ep0state = USB_EP0_SENDING_STS; + usb_lld_prepare_transmit(usbp, 0, NULL, 0); + usb_lld_start_in(usbp, 0); + return; + case USB_EP0_WAITING_STS: + /* Status packet received, it must be zero sized, invoking the callback + if defined.*/ + if (usbGetReceiveTransactionSizeI(usbp, 0) != 0) + break; + if (usbp->ep0endcb != NULL) + usbp->ep0endcb(usbp); + usbp->ep0state = USB_EP0_WAITING_SETUP; + return; + default: + ; + } + /* Error response, the state machine goes into an error state, the low + level layer will have to reset it to USB_EP0_WAITING_SETUP after + receiving a SETUP packet.*/ + usb_lld_stall_in(usbp, 0); + usb_lld_stall_out(usbp, 0); + _usb_isr_invoke_event_cb(usbp, USB_EVENT_STALLED); + usbp->ep0state = USB_EP0_ERROR; +} + +#endif /* HAL_USE_USB */ + +/** @} */ diff --git a/Project/os/hal/templates/adc_lld.c b/Project/os/hal/templates/adc_lld.c new file mode 100644 index 0000000..42b8831 --- /dev/null +++ b/Project/os/hal/templates/adc_lld.c @@ -0,0 +1,128 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/adc_lld.c + * @brief ADC Driver subsystem low level driver source template. + * + * @addtogroup ADC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + if (adcp->adc_state == ADC_STOP) { + /* Clock activation.*/ + } + /* Configuration.*/ +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + if (adcp->state == ADC_READY) { + /* Clock de-activation.*/ + + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/Project/os/hal/templates/adc_lld.h b/Project/os/hal/templates/adc_lld.h new file mode 100644 index 0000000..d6d9ebb --- /dev/null +++ b/Project/os/hal/templates/adc_lld.h @@ -0,0 +1,191 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/adc_lld.h + * @brief ADC Driver subsystem low level driver header template. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !CH_USE_SEMAPHORES +#error "the ADC driver requires CH_USE_SEMAPHORES" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool_t circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /* End of the mandatory fields.*/ +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + * @note It could be empty on some architectures. + */ +typedef struct { + +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/templates/can_lld.c b/Project/os/hal/templates/can_lld.c new file mode 100644 index 0000000..366fa23 --- /dev/null +++ b/Project/os/hal/templates/can_lld.c @@ -0,0 +1,181 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/can_lld.c + * @brief CAN Driver subsystem low level driver source template. + * + * @addtogroup CAN + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_CAN || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level CAN driver initialization. + * + * @notapi + */ +void can_lld_init(void) { + +} + +/** + * @brief Configures and activates the CAN peripheral. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_start(CANDriver *canp) { + +} + +/** + * @brief Deactivates the CAN peripheral. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_stop(CANDriver *canp) { + + /* If in ready state then disables the CAN peripheral.*/ + if (canp->state == CAN_READY) { + + } +} + + +/** + * @brief Determines whether a frame can be transmitted. + * + * @param[in] canp pointer to the @p CANDriver object + * @return The queue space availability. + * @retval FALSE no space in the transmit queue. + * @retval TRUE transmit slot available. + * + * @notapi + */ +bool_t can_lld_can_transmit(CANDriver *canp) { + + return FALSE; +} + +/** + * @brief Inserts a frame into the transmit queue. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] ctfp pointer to the CAN frame to be transmitted + * + * @notapi + */ +void can_lld_transmit(CANDriver *canp, const CANTxFrame *ctfp) { + +} + +/** + * @brief Determines whether a frame has been received. + * + * @param[in] canp pointer to the @p CANDriver object + * @return The queue space availability. + * @retval FALSE no space in the transmit queue. + * @retval TRUE transmit slot available. + * + * @notapi + */ +bool_t can_lld_can_receive(CANDriver *canp) { + + return FALSE; +} + +/** + * @brief Receives a frame from the input queue. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[out] crfp pointer to the buffer where the CAN frame is copied + * + * @notapi + */ +void can_lld_receive(CANDriver *canp, CANRxFrame *crfp) { + +} + +#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__) +/** + * @brief Enters the sleep mode. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_sleep(CANDriver *canp) { + +} + +/** + * @brief Enforces leaving the sleep mode. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_wakeup(CANDriver *canp) { + +} +#endif /* CAN_USE_SLEEP_MODE */ + +#endif /* HAL_USE_CAN */ + +/** @} */ diff --git a/Project/os/hal/templates/can_lld.h b/Project/os/hal/templates/can_lld.h new file mode 100644 index 0000000..57b6300 --- /dev/null +++ b/Project/os/hal/templates/can_lld.h @@ -0,0 +1,231 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/can_lld.h + * @brief CAN Driver subsystem low level driver header template. + * + * @addtogroup CAN + * @{ + */ + +#ifndef _CAN_LLD_H_ +#define _CAN_LLD_H_ + +#if HAL_USE_CAN || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief This switch defines whether the driver implementation supports + * a low power switch mode with automatic an wakeup feature. + */ +#define CAN_SUPPORTS_SLEEP TRUE + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP +#error "CAN sleep mode not supported in this architecture" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief CAN status flags. + */ +typedef uint32_t canstatus_t; + +/** + * @brief CAN transmission frame. + * @note Accessing the frame data as word16 or word32 is not portable + * because machine data endianness, it can be still useful for a + * quick filling. + */ +typedef struct { + struct { + uint8_t DLC:4; /**< @brief Data length. */ + uint8_t RTR:1; /**< @brief Frame type. */ + uint8_t IDE:1; /**< @brief Identifier type. */ + }; + union { + struct { + uint32_t SID:11; /**< @brief Standard identifier.*/ + }; + struct { + uint32_t EID:29; /**< @brief Extended identifier.*/ + }; + }; + union { + uint8_t data8[8]; /**< @brief Frame data. */ + uint16_t data16[4]; /**< @brief Frame data. */ + uint32_t data32[2]; /**< @brief Frame data. */ + }; +} CANTxFrame; + +/** + * @brief CAN received frame. + * @note Accessing the frame data as word16 or word32 is not portable + * because machine data endianness, it can be still useful for a + * quick filling. + */ +typedef struct { + struct { + uint8_t DLC:4; /**< @brief Data length. */ + uint8_t RTR:1; /**< @brief Frame type. */ + uint8_t IDE:1; /**< @brief Identifier type. */ + }; + union { + struct { + uint32_t SID:11; /**< @brief Standard identifier.*/ + }; + struct { + uint32_t EID:29; /**< @brief Extended identifier.*/ + }; + }; + union { + uint8_t data8[8]; /**< @brief Frame data. */ + uint16_t data16[4]; /**< @brief Frame data. */ + uint32_t data32[2]; /**< @brief Frame data. */ + }; +} CANRxFrame; + +/** + * @brief CAN filter. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + * @note It could not be present on some architectures. + */ +typedef struct { +} CANFilter; + +/** + * @brief Driver configuration structure. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + * @note It could be empty on some architectures. + */ +typedef struct { +} CANConfig; + +/** + * @brief Structure representing an CAN driver. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + /** + * @brief Driver state. + */ + canstate_t state; + /** + * @brief Current configuration data. + */ + const CANConfig *config; + /** + * @brief Transmission queue semaphore. + */ + Semaphore txsem; + /** + * @brief Receive queue semaphore. + */ + Semaphore rxsem; + /** + * @brief One or more frames become available. + * @note After broadcasting this event it will not be broadcasted again + * until the received frames queue has been completely emptied. It + * is not broadcasted for each received frame. It is + * responsibility of the application to empty the queue by repeatedly + * invoking @p chReceive() when listening to this event. This behavior + * minimizes the interrupt served by the system because CAN traffic. + */ + EventSource rxfull_event; + /** + * @brief One or more transmission slots become available. + */ + EventSource txempty_event; + /** + * @brief A CAN bus error happened. + */ + EventSource error_event; + /** + * @brief Error flags set when an error event is broadcasted. + */ + canstatus_t status; +#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__) + /** + * @brief Entering sleep state event. + */ + EventSource sleep_event; + /** + * @brief Exiting sleep state event. + */ + EventSource wakeup_event; +#endif /* CAN_USE_SLEEP_MODE */ + /* End of the mandatory fields.*/ +} CANDriver; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void can_lld_init(void); + void can_lld_start(CANDriver *canp); + void can_lld_stop(CANDriver *canp); + bool_t can_lld_can_transmit(CANDriver *canp); + void can_lld_transmit(CANDriver *canp, const CANTxFrame *crfp); + bool_t can_lld_can_receive(CANDriver *canp); + void can_lld_receive(CANDriver *canp, CANRxFrame *ctfp); +#if CAN_USE_SLEEP_MODE + void can_lld_sleep(CANDriver *canp); + void can_lld_wakeup(CANDriver *canp); +#endif /* CAN_USE_SLEEP_MODE */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_CAN */ + +#endif /* _CAN_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/templates/ext_lld.c b/Project/os/hal/templates/ext_lld.c new file mode 100644 index 0000000..4056b13 --- /dev/null +++ b/Project/os/hal/templates/ext_lld.c @@ -0,0 +1,137 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/ext_lld.c + * @brief EXT Driver subsystem low level driver source template. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EXTD1 driver identifier. + */ +EXTDriver EXTD1; + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level EXT driver initialization. + * + * @notapi + */ +void ext_lld_init(void) { + + /* Driver initialization.*/ + extObjectInit(&EXTD1); +} + +/** + * @brief Configures and activates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_start(EXTDriver *extp) { + + if (extp->state == EXT_STOP) { + /* Clock activation.*/ + } + /* Configuration.*/ +} + +/** + * @brief Deactivates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_stop(EXTDriver *extp) { + + if (extp->state == EXT_ACTIVE) { + /* Clock deactivation.*/ + + } +} + +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @notapi + */ +void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { + +} + +/** + * @brief Disables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be disabled + * + * @notapi + */ +void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) { + +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/Project/os/hal/templates/ext_lld.h b/Project/os/hal/templates/ext_lld.h new file mode 100644 index 0000000..5d03b0a --- /dev/null +++ b/Project/os/hal/templates/ext_lld.h @@ -0,0 +1,147 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/ext_lld.h + * @brief EXT Driver subsystem low level driver header template. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_H_ +#define _EXT_LLD_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Available number of EXT channels. + */ +#define EXT_MAX_CHANNELS 20 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief EXT channel identifier. + */ +typedef uint32_t expchannel_t; + +/** + * @brief Type of an EXT generic notification callback. + * + * @param[in] extp pointer to the @p EXPDriver object triggering the + * callback + */ +typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); + +/** + * @brief Channel configuration structure. + */ +typedef struct { + /** + * @brief Channel mode. + */ + uint32_t mode; + /** + * @brief Channel callback. + * @details In the STM32 implementation a @p NULL callback pointer is + * valid and configures the channel as an event sources instead + * of an interrupt source. + */ + extcallback_t cb; +} EXTChannelConfig; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Channel configurations. + */ + EXTChannelConfig channels[EXT_MAX_CHANNELS]; + /* End of the mandatory fields.*/ +} EXTConfig; + +/** + * @brief Structure representing an EXT driver. + */ +struct EXTDriver { + /** + * @brief Driver state. + */ + extstate_t state; + /** + * @brief Current configuration data. + */ + const EXTConfig *config; + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern EXTDriver EXTD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_init(void); + void ext_lld_start(EXTDriver *extp); + void ext_lld_stop(EXTDriver *extp); + void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); + void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/templates/gpt_lld.c b/Project/os/hal/templates/gpt_lld.c new file mode 100644 index 0000000..4d99e08 --- /dev/null +++ b/Project/os/hal/templates/gpt_lld.c @@ -0,0 +1,146 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/gpt_lld.c + * @brief GPT Driver subsystem low level driver source template. + * + * @addtogroup GPT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level GPT driver initialization. + * + * @notapi + */ +void gpt_lld_init(void) { + +} + +/** + * @brief Configures and activates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_start(GPTDriver *gptp) { + uint16_t psc; + + if (gptp->state == GPT_STOP) { + /* Clock activation.*/ + + } + /* Configuration.*/ +} + +/** + * @brief Deactivates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop(GPTDriver *gptp) { + + if (gptp->state == GPT_READY) { + /* Clock de-activation.*/ + + } +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] period period in ticks + * + * @notapi + */ +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period) { + +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop_timer(GPTDriver *gptp) { + +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @notapi + */ +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { + +} + +#endif /* HAL_USE_GPT */ + +/** @} */ diff --git a/Project/os/hal/templates/gpt_lld.h b/Project/os/hal/templates/gpt_lld.h new file mode 100644 index 0000000..bdd649f --- /dev/null +++ b/Project/os/hal/templates/gpt_lld.h @@ -0,0 +1,141 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/gpt_lld.h + * @brief GPT Driver subsystem low level driver header template. + * + * @addtogroup GPT + * @{ + */ + +#ifndef _GPT_LLD_H_ +#define _GPT_LLD_H_ + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPT frequency type. + */ +typedef uint32_t gptfreq_t; + +/** + * @brief GPT counter type. + */ +typedef uint16_t gptcnt_t; + +/** + * @brief Type of a structure representing a GPT driver. + */ +typedef struct GPTDriver GPTDriver; + +/** + * @brief GPT notification callback type. + * + * @param[in] gptp pointer to a @p GPTDriver object + */ +typedef void (*gptcallback_t)(GPTDriver *gptp); + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + gptfreq_t frequency; + /** + * @brief Timer callback pointer. + * @note This callback is invoked on GPT counter events. + */ + gptcallback_t callback; + /* End of the mandatory fields.*/ +} GPTConfig; + +/** + * @brief Structure representing a GPT driver. + */ +struct GPTDriver { + /** + * @brief Driver state. + */ + gptstate_t state; + /** + * @brief Current configuration data. + */ + const GPTConfig *config; +#if defined(GPT_DRIVER_EXT_FIELDS) + GPT_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void gpt_lld_init(void); + void gpt_lld_start(GPTDriver *gptp); + void gpt_lld_stop(GPTDriver *gptp); + void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval); + void gpt_lld_stop_timer(GPTDriver *gptp); + void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT */ + +#endif /* _GPT_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/templates/hal_lld.c b/Project/os/hal/templates/hal_lld.c new file mode 100644 index 0000000..c93e968 --- /dev/null +++ b/Project/os/hal/templates/hal_lld.c @@ -0,0 +1,72 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/hal_lld.c + * @brief HAL Driver subsystem low level driver source template. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + +} + +/** @} */ diff --git a/Project/os/hal/templates/hal_lld.h b/Project/os/hal/templates/hal_lld.h new file mode 100644 index 0000000..62235e7 --- /dev/null +++ b/Project/os/hal/templates/hal_lld.h @@ -0,0 +1,78 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/hal_lld.h + * @brief HAL subsystem low level driver header template. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "" + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/templates/halconf.h b/Project/os/hal/templates/halconf.h new file mode 100644 index 0000000..b528f65 --- /dev/null +++ b/Project/os/hal/templates/halconf.h @@ -0,0 +1,401 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @name Drivers enable switches + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN TRUE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC TRUE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI TRUE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART TRUE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name ADC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name CAN driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name I2C driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MAC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name MMC_SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SDC driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SERIAL_USB driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif +/** @} */ + +/*===========================================================================*/ +/** + * @name SPI driver related setting + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif +/** @} */ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/Project/os/hal/templates/i2c_lld.c b/Project/os/hal/templates/i2c_lld.c new file mode 100644 index 0000000..071e737 --- /dev/null +++ b/Project/os/hal/templates/i2c_lld.c @@ -0,0 +1,166 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/i2c_lld.c + * @brief I2C Driver subsystem low level driver source template. + * + * @addtogroup I2C + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level I2C driver initialization. + * + * @notapi + */ +void i2c_lld_init(void) { + +} + +/** + * @brief Configures and activates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_start(I2CDriver *i2cp) { + + if (i2cp->i2c_state == I2C_STOP) { + /* Clock activation.*/ + } + /* Configuration.*/ +} + +/** + * @brief Deactivates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_stop(I2CDriver *i2cp) { + +} + +/** + * @brief Initiates a master bus transaction. + * @details This function sends a start bit followed by an one or two bytes + * header. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] header transaction header + * + * @notapi + */ +void i2c_lld_master_start(I2CDriver *i2cp, uint16_t header) { + +} + +/** + * @brief Terminates a master bus transaction. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_master_stop(I2CDriver *i2cp) { + +} + +/** + * @brief Sends a restart bit. + * @details Restart bits are required by some types of I2C transactions. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_master_restart(I2CDriver *i2cp) { + +} + +/** + * @brief Master transmission. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] n number of bytes to be transmitted + * @param[in] txbuf transmit data buffer pointer + * + * @notapi + */ +void i2c_lld_master_transmit(I2CDriver *i2cp, size_t n, + const uint8_t *txbuf) { + +} + +/** + * @brief Master receive. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] n number of bytes to be transmitted + * @param[in] rxbuf receive data buffer pointer + * + * @notapi + */ +void i2c_lld_master_receive(I2CDriver *i2cp, size_t n, uint8_t *rxbuf) { + +} + +#endif /* HAL_USE_I2C */ + +/** @} */ diff --git a/Project/os/hal/templates/i2c_lld.h b/Project/os/hal/templates/i2c_lld.h new file mode 100644 index 0000000..7675893 --- /dev/null +++ b/Project/os/hal/templates/i2c_lld.h @@ -0,0 +1,128 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/i2c_lld.h + * @brief I2C Driver subsystem low level driver header template. + * + * @addtogroup I2C + * @{ + */ + +#ifndef _I2C_LLD_H_ +#define _I2C_LLD_H_ + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + + +/** + * @brief Type of a structure representing an I2C driver. + */ +typedef struct I2CDriver I2CDriver; + +/** + * @brief I2C completion callback type. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] sts operation status + */ +typedef void (*i2ccallback_t)(I2CDriver *i2cp, i2cstatus_t sts); + +/** + * @brief Driver configuration structure. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + /** @brief I2C bus bit rate.*/ + uint32_t ic_speed; + /* End of the mandatory fields.*/ +} I2CConfig; + +/** + * @brief Structure representing an I2C driver. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +struct I2CDriver { + /** @brief Driver state.*/ + i2cstate_t id_state; + /** @brief Current configuration data.*/ + const I2CConfig *id_config; + /** @brief Current callback.*/ + i2ccallback_t id_callback; +#if defined(I2C_DRIVER_EXT_FIELDS) + I2C_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void i2c_lld_init(void); + void i2c_lld_start(I2CDriver *i2cp); + void i2c_lld_stop(I2CDriver *i2cp); + void i2c_lld_master_start(I2CDriver *i2cp, uint16_t header); + void i2c_lld_master_stop(I2CDriver *i2cp); + void i2c_lld_master_restart(I2CDriver *i2cp); + void i2c_lld_master_transmit(I2CDriver *i2cp, size_t n, + const uint8_t *txbuf); + void i2c_lld_master_receive(I2CDriver *i2cp, size_t n, uint8_t *rxbuf); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_I2C */ + +#endif /* _I2C_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/templates/icu_lld.c b/Project/os/hal/templates/icu_lld.c new file mode 100644 index 0000000..b4afb18 --- /dev/null +++ b/Project/os/hal/templates/icu_lld.c @@ -0,0 +1,156 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/icu_lld.c + * @brief ICU Driver subsystem low level driver source template. + * + * @addtogroup ICU + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ICU driver initialization. + * + * @notapi + */ +void icu_lld_init(void) { + +} + +/** + * @brief Configures and activates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_start(ICUDriver *icup) { + + if (icup->state == ICU_STOP) { + /* Clock activation.*/ + } + /* Configuration.*/ +} + +/** + * @brief Deactivates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_stop(ICUDriver *icup) { + + if (icup->state == ICU_READY) { + /* Clock deactivation.*/ + + } +} + +/** + * @brief Enables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_enable(ICUDriver *icup) { + +} + +/** + * @brief Disables the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_disable(ICUDriver *icup) { + +} + +/** + * @brief Returns the width of the latest pulse. + * @details The pulse width is defined as number of ticks between the start + * edge and the stop edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @notapi + */ +icucnt_t icu_lld_get_width(ICUDriver *icup) { + +} + +/** + * @brief Returns the width of the latest cycle. + * @details The cycle width is defined as number of ticks between a start + * edge and the next start edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @notapi + */ +icucnt_t icu_lld_get_period(ICUDriver *icup) { + +} + +#endif /* HAL_USE_ICU */ + +/** @} */ diff --git a/Project/os/hal/templates/icu_lld.h b/Project/os/hal/templates/icu_lld.h new file mode 100644 index 0000000..c3cb0df --- /dev/null +++ b/Project/os/hal/templates/icu_lld.h @@ -0,0 +1,145 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/icu_lld.h + * @brief ICU Driver subsystem low level driver header template. + * + * @addtogroup ICU + * @{ + */ + +#ifndef _ICU_LLD_H_ +#define _ICU_LLD_H_ + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ICU driver mode. + */ +typedef enum { + ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge. */ + ICU_INPUT_ACTIVE_LOW = 1, /**< Trigger on falling edge. */ +} icumode_t; + +/** + * @brief ICU frequency type. + */ +typedef uint32_t icufreq_t; + +/** + * @brief ICU counter type. + */ +typedef uint16_t icucnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Driver mode. + */ + icumode_t mode; + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + icufreq_t frequency; + /** + * @brief Callback for pulse width measurement. + */ + icucallback_t width_cb; + /** + * @brief Callback for cycle period measurement. + */ + icucallback_t period_cb; + /* End of the mandatory fields.*/ +} ICUConfig; + +/** + * @brief Structure representing an ICU driver. + */ +struct ICUDriver { + /** + * @brief Driver state. + */ + icustate_t state; + /** + * @brief Current configuration data. + */ + const ICUConfig *config; +#if defined(ICU_DRIVER_EXT_FIELDS) + ICU_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void icu_lld_init(void); + void icu_lld_start(ICUDriver *icup); + void icu_lld_stop(ICUDriver *icup); + void icu_lld_enable(ICUDriver *icup); + void icu_lld_disable(ICUDriver *icup); + icucnt_t icu_lld_get_width(ICUDriver *icup); + icucnt_t icu_lld_get_period(ICUDriver *icup); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ICU */ + +#endif /* _ICU_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/templates/mac_lld.c b/Project/os/hal/templates/mac_lld.c new file mode 100644 index 0000000..cbfc245 --- /dev/null +++ b/Project/os/hal/templates/mac_lld.c @@ -0,0 +1,219 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/mac_lld.c + * @brief MAC Driver subsystem low level driver source template. + * + * @addtogroup MAC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief Ethernet driver 1. + */ +MACDriver ETH1; + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level MAC initialization. + * + * @notapi + */ +void mac_lld_init(void) { + +} + +/** + * @brief Configures and activates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_start(MACDriver *macp) { + +} + +/** + * @brief Deactivates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_stop(MACDriver *macp) { + +} + +/** + * @brief Returns a transmission descriptor. + * @details One of the available transmission descriptors is locked and + * returned. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] tdp pointer to a @p MACTransmitDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp) { + + return RDY_OK; +} + +/** + * @brief Writes to a transmit descriptor's stream. + * + * @param[in] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] buf pointer to the buffer containing the data to be + * written + * @param[in] size number of bytes to be written + * @return The number of bytes written into the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if the maximum + * frame size is reached. + * + * @notapi + */ +size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size) { + + return 0; +} + +/** + * @brief Releases a transmit descriptor and starts the transmission of the + * enqueued data as a single frame. + * + * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure + * + * @notapi + */ +void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) { + +} + +/** + * @brief Returns a receive descriptor. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] rdp pointer to a @p MACReceiveDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t mac_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp) { + + return RDY_TIMEOUT; +} + +/** + * @brief Reads from a receive descriptor's stream. + * + * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[in] buf pointer to the buffer that will receive the read data + * @param[in] size number of bytes to be read + * @return The number of bytes read from the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if there are + * no more bytes to read. + * + * @notapi + */ +size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size) { + + return 0; +} + +/** + * @brief Releases a receive descriptor. + * @details The descriptor and its buffer are made available for more incoming + * frames. + * + * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure + * + * @notapi + */ +void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) { + +} + +/** + * @brief Updates and returns the link status. + * + * @param[in] macp pointer to the @p MACDriver object + * @return The link status. + * @retval TRUE if the link is active. + * @retval FALSE if the link is down. + * + * @notapi + */ +bool_t mac_lld_poll_link_status(MACDriver *macp) { + +} + +#endif /* HAL_USE_MAC */ + +/** @} */ diff --git a/Project/os/hal/templates/mac_lld.h b/Project/os/hal/templates/mac_lld.h new file mode 100644 index 0000000..6cd2e9b --- /dev/null +++ b/Project/os/hal/templates/mac_lld.h @@ -0,0 +1,166 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/mac_lld.h + * @brief MAC Driver subsystem low level driver header template. + * + * @addtogroup MAC + * @{ + */ + +#ifndef _MAC_LLD_H_ +#define _MAC_LLD_H_ + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief MAC address. + */ + uint8_t *mac_address; + /* End of the mandatory fields.*/ +} MACConfig; + +/** + * @brief Structure representing a MAC driver. + */ +struct MACDriver { + /** + * @brief Driver state. + */ + macstate_t state; + /** + * @brief Current configuration data. + */ + const MACConfig *config; + /** + * @brief Transmit semaphore. + */ + Semaphore tdsem; + /** + * @brief Receive semaphore. + */ + Semaphore rdsem; +#if MAC_USE_EVENTS || defined(__DOXYGEN__) + /** + * @brief Receive event. + */ + EventSource rdevent; +#endif + /* End of the mandatory fields.*/ +}; + +/** + * @brief Structure representing a transmit descriptor. + */ +typedef struct { + /** + * @brief Current write offset. + */ + size_t offset; + /** + * @brief Available space size. + */ + size_t size; + /* End of the mandatory fields.*/ +} MACTransmitDescriptor; + +/** + * @brief Structure representing a receive descriptor. + */ +typedef struct { + /** + * @brief Current read offset. + */ + size_t offset; + /** + * @brief Available data size. + */ + size_t size; + /* End of the mandatory fields.*/ +} MACReceiveDescriptor; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern MACDriver ETH1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void mac_lld_init(void); + void mac_lld_start(MACDriver *macp); + void mac_lld_stop(MACDriver *macp); + msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp); + size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size); + void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp); + msg_t mac_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp); + size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size); + void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp); + bool_t mac_lld_poll_link_status(MACDriver *macp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_MAC */ + +#endif /* _MAC_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/templates/meta/driver.c b/Project/os/hal/templates/meta/driver.c new file mode 100644 index 0000000..b014a81 --- /dev/null +++ b/Project/os/hal/templates/meta/driver.c @@ -0,0 +1,128 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file xxx.c + * @brief XXX Driver code. + * + * @addtogroup XXX + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_XXX || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief XXX Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void xxxInit(void) { + + xxx_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p XXXDriver structure. + * + * @param[out] xxxp pointer to the @p XXXDriver object + * + * @init + */ +void xxxObjectInit(XXXDriver *xxxp) { + + xxxp->state = XXX_STOP; + xxxp->config = NULL; +} + +/** + * @brief Configures and activates the XXX peripheral. + * + * @param[in] xxxp pointer to the @p XXXDriver object + * @param[in] config pointer to the @p XXXConfig object + * + * @api + */ +void xxxStart(XXXDriver *xxxp, const XXXConfig *config) { + + chDbgCheck((xxxp != NULL) && (config != NULL), "xxxStart"); + + chSysLock(); + chDbgAssert((xxxp->state == XXX_STOP) || (xxxp->state == XXX_READY), + "xxxStart(), #1", "invalid state"); + xxxp->config = config; + xxx_lld_start(xxxp); + xxxp->state = XXX_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the XXX peripheral. + * + * @param[in] xxxp pointer to the @p XXXDriver object + * + * @api + */ +void xxxStop(XXXDriver *xxxp) { + + chDbgCheck(xxxp != NULL, "xxxStop"); + + chSysLock(); + chDbgAssert((xxxp->state == XXX_STOP) || (xxxp->state == XXX_READY), + "xxxStop(), #1", "invalid state"); + xxx_lld_stop(xxxp); + xxxp->state = XXX_STOP; + chSysUnlock(); +} + +#endif /* HAL_USE_XXX */ + +/** @} */ diff --git a/Project/os/hal/templates/meta/driver.h b/Project/os/hal/templates/meta/driver.h new file mode 100644 index 0000000..886e9a4 --- /dev/null +++ b/Project/os/hal/templates/meta/driver.h @@ -0,0 +1,96 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file xxx.h + * @brief XXX Driver macros and structures. + * + * @addtogroup XXX + * @{ + */ + +#ifndef _XXX_H_ +#define _XXX_H_ + +#if HAL_USE_XXX || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + XXX_UNINIT = 0, /**< Not initialized. */ + XXX_STOP = 1, /**< Stopped. */ + XXX_READY = 2, /**< Ready. */ +} xxxstate_t; + +/** + * @brief Type of a structure representing a XXX driver. + */ +typedef struct XXXDriver XXXDriver; + +#include "xxx_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void xxxInit(void); + void xxxObjectInit(XXXDriver *xxxp); + void xxxStart(XXXDriver *xxxp, const XXXConfig *config); + void xxxStop(XXXDriver *xxxp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_XXX */ + +#endif /* _XXX_H_ */ + +/** @} */ diff --git a/Project/os/hal/templates/meta/driver_lld.c b/Project/os/hal/templates/meta/driver_lld.c new file mode 100644 index 0000000..7dcb604 --- /dev/null +++ b/Project/os/hal/templates/meta/driver_lld.c @@ -0,0 +1,106 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/xxx_lld.c + * @brief XXX Driver subsystem low level driver source template. + * + * @addtogroup XXX + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_XXX || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level XXX driver initialization. + * + * @notapi + */ +void xxx_lld_init(void) { + +} + +/** + * @brief Configures and activates the XXX peripheral. + * + * @param[in] xxxp pointer to the @p XXXDriver object + * + * @notapi + */ +void xxx_lld_start(XXXDriver *xxxp) { + + if (xxxp->state == XXX_STOP) { + /* Clock activation.*/ + } + /* Configuration.*/ +} + +/** + * @brief Deactivates the XXX peripheral. + * + * @param[in] xxxp pointer to the @p XXXDriver object + * + * @notapi + */ +void xxx_lld_stop(XXXDriver *xxxp) { + + if (xxxp->state == XXX_READY) { + /* Clock deactivation.*/ + + } +} + +#endif /* HAL_USE_XXX */ + +/** @} */ diff --git a/Project/os/hal/templates/meta/driver_lld.h b/Project/os/hal/templates/meta/driver_lld.h new file mode 100644 index 0000000..20d9233 --- /dev/null +++ b/Project/os/hal/templates/meta/driver_lld.h @@ -0,0 +1,107 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/xxx_lld.h + * @brief XXX Driver subsystem low level driver header template. + * + * @addtogroup XXX + * @{ + */ + +#ifndef _XXX_LLD_H_ +#define _XXX_LLD_H_ + +#if HAL_USE_XXX || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an XXX driver. + */ +typedef struct XXXDriver XXXDriver; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + +} XXXConfig; + +/** + * @brief Structure representing an XXX driver. + */ +struct XXXDriver { + /** + * @brief Driver state. + */ + xxxstate_t state; + /** + * @brief Current configuration data. + */ + const XXXConfig *config; + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void xxx_lld_init(void); + void xxx_lld_start(XXXDriver *xxxp); + void xxx_lld_stop(XXXDriver *xxxp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_XXX */ + +#endif /* _XXX_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/templates/pal_lld.c b/Project/os/hal/templates/pal_lld.c new file mode 100644 index 0000000..dd39a4b --- /dev/null +++ b/Project/os/hal/templates/pal_lld.c @@ -0,0 +1,67 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/pal_lld.c + * @brief PAL subsystem low level driver template. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/Project/os/hal/templates/pal_lld.h b/Project/os/hal/templates/pal_lld.h new file mode 100644 index 0000000..dd3bb75 --- /dev/null +++ b/Project/os/hal/templates/pal_lld.h @@ -0,0 +1,326 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/pal_lld.h + * @brief PAL subsystem low level driver header template. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief Generic I/O ports static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 32 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef uint32_t ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief First I/O port identifier. + * @details Low level drivers can define multiple ports, it is suggested to + * use this naming convention. + */ +#define IOPORT1 0 + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) + +/** + * @brief Sets a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) + +/** + * @brief Clears a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) + +/** + * @brief Toggles a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be XORed on the specified port + * + * @notapi + */ +#define pal_lld_toggleport(port, bits) + +/** + * @brief Reads a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @notapi + */ +#define pal_lld_readgroup(port, mask, offset) + +/** + * @brief Writes a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Reads a logical state from an I/O pad. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @return The logical state. + * @retval PAL_LOW low logical state. + * @retval PAL_HIGH high logical state. + * + * @notapi + */ +#define pal_lld_readpad(port, pad) + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) + +/** + * @brief Toggles a pad logical state. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_togglepad(port, pad) + +/** + * @brief Pad mode setup. + * @details This function programs a pad with the specified mode. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad mode + * + * @notapi + */ +#define pal_lld_setpadmode(port, pad, mode) + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/templates/pwm_lld.c b/Project/os/hal/templates/pwm_lld.c new file mode 100644 index 0000000..13b82f3 --- /dev/null +++ b/Project/os/hal/templates/pwm_lld.c @@ -0,0 +1,160 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/pwm_lld.c + * @brief PWM Driver subsystem low level driver source template. + * + * @addtogroup PWM + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level PWM driver initialization. + * + * @notapi + */ +void pwm_lld_init(void) { + +} + +/** + * @brief Configures and activates the PWM peripheral. + * + * @param[in] pwmp pointer to the @p PWMDriver object + * + * @notapi + */ +void pwm_lld_start(PWMDriver *pwmp) { + + if (pwmp->state == PWM_STOP) { + /* Clock activation.*/ + } + /* Configuration.*/ +} + +/** + * @brief Deactivates the PWM peripheral. + * + * @param[in] pwmp pointer to the @p PWMDriver object + * + * @notapi + */ +void pwm_lld_stop(PWMDriver *pwmp) { + +} + +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note The function has effect at the next cycle start. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @notapi + */ +void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) { + +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note Depending on the hardware implementation this function has + * effect starting on the next cycle (recommended implementation) + * or immediately (fallback implementation). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @notapi + */ +void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width) { + +} + +/** + * @brief Disables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note Depending on the hardware implementation this function has + * effect starting on the next cycle (recommended implementation) + * or immediately (fallback implementation). + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) + * + * @notapi + */ +void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { + +} + +#endif /* HAL_USE_PWM */ + +/** @} */ diff --git a/Project/os/hal/templates/pwm_lld.h b/Project/os/hal/templates/pwm_lld.h new file mode 100644 index 0000000..4035576 --- /dev/null +++ b/Project/os/hal/templates/pwm_lld.h @@ -0,0 +1,180 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/pwm_lld.h + * @brief PWM Driver subsystem low level driver header template. + * + * @addtogroup PWM + * @{ + */ + +#ifndef _PWM_LLD_H_ +#define _PWM_LLD_H_ + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Number of PWM channels per PWM driver. + */ +#if !defined(PWM_CHANNELS) || defined(__DOXYGEN__) +#define PWM_CHANNELS 1 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief PWM mode type. + */ +typedef uint32_t pwmmode_t; + +/** + * @brief PWM channel type. + */ +typedef uint8_t pwmchannel_t; + +/** + * @brief PWM counter type. + */ +typedef uint16_t pwmcnt_t; + +/** + * @brief PWM driver channel configuration structure. + * @note Some architectures may not be able to support the channel mode + * or the callback, in this case the fields are ignored. + */ +typedef struct { + /** + * @brief Channel active logic level. + */ + pwmmode_t mode; + /** + * @brief Channel callback pointer. + * @note This callback is invoked on the channel compare event. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /* End of the mandatory fields.*/ +} PWMChannelConfig; + +/** + * @brief Driver configuration structure. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + uint32_t frequency; + /** + * @brief PWM period in ticks. + * @note The low level can use assertions in order to catch invalid + * period specifications. + */ + pwmcnt_t period; + /** + * @brief Periodic callback pointer. + * @note This callback is invoked on PWM counter reset. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /** + * @brief Channels configurations. + */ + PWMChannelConfig channels[PWM_CHANNELS]; + /* End of the mandatory fields.*/ +} PWMConfig; + +/** + * @brief Structure representing an PWM driver. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +struct PWMDriver { + /** + * @brief Driver state. + */ + pwmstate_t state; + /** + * @brief Current configuration data. + */ + const PWMConfig *config; + /** + * @brief Current PWM period in ticks. + */ + pwmcnt_t period; +#if defined(PWM_DRIVER_EXT_FIELDS) + PWM_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void pwm_lld_init(void); + void pwm_lld_start(PWMDriver *pwmp); + void pwm_lld_stop(PWMDriver *pwmp); + void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period); + void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width); + void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PWM */ + +#endif /* _PWM_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/templates/serial_lld.c b/Project/os/hal/templates/serial_lld.c new file mode 100644 index 0000000..edf7c88 --- /dev/null +++ b/Project/os/hal/templates/serial_lld.c @@ -0,0 +1,112 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/serial_lld.c + * @brief Serial Driver subsystem low level driver source template. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** + * @brief Driver default configuration. + */ +static const SerialConfig default_config = { +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/Project/os/hal/templates/serial_lld.h b/Project/os/hal/templates/serial_lld.h new file mode 100644 index 0000000..a2702fb --- /dev/null +++ b/Project/os/hal/templates/serial_lld.h @@ -0,0 +1,107 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/serial_lld.h + * @brief Serial Driver subsystem low level driver header template. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Generic Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/templates/spi_lld.c b/Project/os/hal/templates/spi_lld.c new file mode 100644 index 0000000..9d62b62 --- /dev/null +++ b/Project/os/hal/templates/spi_lld.c @@ -0,0 +1,210 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/spi_lld.c + * @brief SPI Driver subsystem low level driver source template. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + if (spip->state == SPI_STOP) { + /* Clock activation.*/ + } + /* Configuration.*/ +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + +} + +/** + * @brief Ignores data on the SPI bus. + * @details This asynchronous function starts the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @post At the end of the operation the configured callback is invoked. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/Project/os/hal/templates/spi_lld.h b/Project/os/hal/templates/spi_lld.h new file mode 100644 index 0000000..6c365d3 --- /dev/null +++ b/Project/os/hal/templates/spi_lld.h @@ -0,0 +1,149 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/spi_lld.h + * @brief SPI Driver subsystem low level driver header template. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + /** + * @brief Operation complete callback. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ +} SPIConfig; + +/** + * @brief Structure representing an SPI driver. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/templates/uart_lld.c b/Project/os/hal/templates/uart_lld.c new file mode 100644 index 0000000..d18670f --- /dev/null +++ b/Project/os/hal/templates/uart_lld.c @@ -0,0 +1,162 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/uart_lld.c + * @brief UART Driver subsystem low level driver source template. + * + * @addtogroup UART + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level UART driver initialization. + * + * @notapi + */ +void uart_lld_init(void) { + +} + +/** + * @brief Configures and activates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_start(UARTDriver *uartp) { + + if (uartp->uart_state == UART_STOP) { + /* Clock activation.*/ + } + /* Configuration.*/ +} + +/** + * @brief Deactivates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_stop(UARTDriver *uartp) { + +} + +/** + * @brief Starts a transmission on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { + +} + +/** + * @brief Stops any ongoing transmission. + * @note Stopping a transmission also suppresses the transmission callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not transmitted by the + * stopped transmit operation. + * + * @notapi + */ +size_t uart_lld_stop_send(UARTDriver *uartp) { + +} + +/** + * @brief Starts a receive operation on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { + +} + +/** + * @brief Stops any ongoing receive operation. + * @note Stopping a receive operation also suppresses the receive callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not received by the + * stopped receive operation. + * + * @notapi + */ +size_t uart_lld_stop_receive(UARTDriver *uartp) { + +} + +#endif /* HAL_USE_UART */ + +/** @} */ diff --git a/Project/os/hal/templates/uart_lld.h b/Project/os/hal/templates/uart_lld.h new file mode 100644 index 0000000..9688661 --- /dev/null +++ b/Project/os/hal/templates/uart_lld.h @@ -0,0 +1,175 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/uart_lld.h + * @brief UART Driver subsystem low level driver header template. + * + * @addtogroup UART + * @{ + */ + +#ifndef _UART_LLD_H_ +#define _UART_LLD_H_ + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief UART driver condition flags type. + */ +typedef uint32_t uartflags_t; + +/** + * @brief Type of structure representing an UART driver. + */ +typedef struct UARTDriver UARTDriver; + +/** + * @brief Generic UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +typedef void (*uartcb_t)(UARTDriver *uartp); + +/** + * @brief Character received UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object triggering the + * callback + * @param[in] c received character + */ +typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); + +/** + * @brief Receive error UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object triggering the + * callback + * @param[in] e receive error mask + */ +typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); + +/** + * @brief Driver configuration structure. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + /** + * @brief End of transmission buffer callback. + */ + uartcb_t txend1_cb; + /** + * @brief Physical end of transmission callback. + */ + uartcb_t txend2_cb; + /** + * @brief Receive buffer filled callback. + */ + uartcb_t rxend_cb; + /** + * @brief Character received while out if the @p UART_RECEIVE state. + */ + uartccb_t rxchar_cb; + /** + * @brief Receive error callback. + */ + uartecb_t rxerr_cb; + /* End of the mandatory fields.*/ +} UARTConfig; + +/** + * @brief Structure representing an UART driver. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +struct UARTDriver { + /** + * @brief Driver state. + */ + uartstate_t state; + /** + * @brief Transmitter state. + */ + uarttxstate_t txstate; + /** + * @brief Receiver state. + */ + uartrxstate_t rxstate; + /** + * @brief Current configuration data. + */ + const UARTConfig *config; +#if defined(UART_DRIVER_EXT_FIELDS) + UART_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void uart_lld_init(void); + void uart_lld_start(UARTDriver *uartp); + void uart_lld_stop(UARTDriver *uartp); + void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf); + size_t uart_lld_stop_send(UARTDriver *uartp); + void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf); + size_t uart_lld_stop_receive(UARTDriver *uartp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_UART */ + +#endif /* _UART_LLD_H_ */ + +/** @} */ diff --git a/Project/os/hal/templates/usb_lld.c b/Project/os/hal/templates/usb_lld.c new file mode 100644 index 0000000..8c1ee53 --- /dev/null +++ b/Project/os/hal/templates/usb_lld.c @@ -0,0 +1,357 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/usb_lld.c + * @brief USB Driver subsystem low level driver source template. + * + * @addtogroup USB + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_USB || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EP0 state. + * @note It is an union because IN and OUT endpoints are never used at the + * same time for EP0. + */ +static union { + /** + * @brief IN EP0 state. + */ + USBInEndpointState in; + /** + * @brief OUT EP0 state. + */ + USBOutEndpointState out; +} ep0_state; + +/** + * @brief EP0 initialization structure. + */ +static const USBEndpointConfig ep0config = { + USB_EP_MODE_TYPE_CTRL | USB_EP_MODE_TRANSACTION, + _usb_ep0in, + _usb_ep0out, + 0x40, + 0x40, + &ep0_state.in, + &ep0_state.out +}; + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level USB driver initialization. + * + * @notapi + */ +void usb_lld_init(void) { + +} + +/** + * @brief Configures and activates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_start(USBDriver *usbp) { + + if (usbp->state == USB_STOP) { + /* Clock activation.*/ + + /* Reset procedure enforced on driver start.*/ + _usb_reset(usbp); + } + /* Configuration.*/ +} + +/** + * @brief Deactivates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_stop(USBDriver *usbp) { + + /* If in ready state then disables the USB clock.*/ + if (usbp->state == USB_STOP) { + + } +} + +/** + * @brief USB low level reset routine. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_reset(USBDriver *usbp) { + + /* Post reset initialization.*/ + + /* EP0 initialization.*/ + usbp->epc[0] = &ep0config; + usb_lld_init_endpoint(usbp, 0); +} + +/** + * @brief Sets the USB address. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_set_address(USBDriver *usbp) { + +} + +/** + * @brief Enables an endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { + +} + +/** + * @brief Disables all the active endpoints except the endpoint zero. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_disable_endpoints(USBDriver *usbp) { + +} + +/** + * @brief Returns the status of an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The endpoint status. + * @retval EP_STATUS_DISABLED The endpoint is not active. + * @retval EP_STATUS_STALLED The endpoint is stalled. + * @retval EP_STATUS_ACTIVE The endpoint is active. + * + * @notapi + */ +usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) { + +} + +/** + * @brief Returns the status of an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The endpoint status. + * @retval EP_STATUS_DISABLED The endpoint is not active. + * @retval EP_STATUS_STALLED The endpoint is stalled. + * @retval EP_STATUS_ACTIVE The endpoint is active. + * + * @notapi + */ +usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) { + +} + +/** + * @brief Reads a setup packet from the dedicated packet buffer. + * @details This function must be invoked in the context of the @p setup_cb + * callback in order to read the received setup packet. + * @pre In order to use this function the endpoint must have been + * initialized as a control endpoint. + * @post The endpoint is ready to accept another packet. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the packet data + * + * @notapi + */ +void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { + +} + +/** + * @brief Reads a packet from the dedicated packet buffer. + * @pre In order to use this function he endpoint must have been + * initialized in packet mode. + * @post The endpoint is ready to accept another packet. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the packet data + * @param[in] n maximum number of bytes to copy. This value must + * not exceed the maximum packet size for this endpoint. + * @return The received packet size regardless the specified + * @p n parameter. + * @retval 0 Zero size packet received. + * + * @notapi + */ +size_t usb_lld_read_packet(USBDriver *usbp, usbep_t ep, + uint8_t *buf, size_t n) { + +} + +/** + * @brief Writes a packet to the dedicated packet buffer. + * @pre In order to use this function he endpoint must have been + * initialized in packet mode. + * @post The endpoint is ready to transmit the packet. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[in] buf buffer where to fetch the packet data + * @param[in] n maximum number of bytes to copy. This value must + * not exceed the maximum packet size for this endpoint. + * + * @notapi + */ +void usb_lld_write_packet(USBDriver *usbp, usbep_t ep, + const uint8_t *buf, size_t n) { + +} + +/** + * @brief Starts a receive operation on an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the endpoint data + * @param[in] n maximum number of bytes to copy in the buffer + * + * @notapi + */ +void usb_lld_start_out(USBDriver *usbp, usbep_t ep, + uint8_t *buf, size_t n) { + +} + +/** + * @brief Starts a transmit operation on an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[in] buf buffer where to fetch the endpoint data + * @param[in] n maximum number of bytes to copy + * + * @notapi + */ +void usb_lld_start_in(USBDriver *usbp, usbep_t ep, + const uint8_t *buf, size_t n) { + +} + +/** + * @brief Brings an OUT endpoint in the stalled state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) { + +} + +/** + * @brief Brings an IN endpoint in the stalled state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) { + +} + +/** + * @brief Brings an OUT endpoint in the active state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) { + +} + +/** + * @brief Brings an IN endpoint in the active state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) { + +} + +#endif /* HAL_USE_USB */ + +/** @} */ diff --git a/Project/os/hal/templates/usb_lld.h b/Project/os/hal/templates/usb_lld.h new file mode 100644 index 0000000..7bc1005 --- /dev/null +++ b/Project/os/hal/templates/usb_lld.h @@ -0,0 +1,317 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/usb_lld.h + * @brief USB Driver subsystem low level driver header template. + * + * @addtogroup USB + * @{ + */ + +#ifndef _USB_LLD_H_ +#define _USB_LLD_H_ + +#if HAL_USE_USB || defined(__DOXYGEN__) + +#include "stm32_usb.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Maximum endpoint address. + */ +#define USB_MAX_ENDPOINTS 4 + +/** + * @brief This device requires the address change after the status packet. + */ +#define USB_SET_ADDRESS_MODE USB_LATE_SET_ADDRESS + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an IN endpoint state structure. + */ +typedef struct { + +} USBInEndpointState; + +/** + * @brief Type of an OUT endpoint state structure. + */ +typedef struct { + +} USBOutEndpointState; + +/** + * @brief Type of an USB endpoint configuration structure. + * @note Platform specific restrictions may apply to endpoints. + */ +typedef struct { + /** + * @brief Type and mode of the endpoint. + */ + uint32_t ep_mode; + /** + * @brief IN endpoint notification callback. + * @details This field must be set to @p NULL if the IN endpoint is not + * used. + */ + usbepcallback_t in_cb; + /** + * @brief OUT endpoint notification callback. + * @details This field must be set to @p NULL if the OUT endpoint is not + * used. + */ + usbepcallback_t out_cb; + /** + * @brief IN endpoint maximum packet size. + * @details This field must be set to zero if the IN endpoint is not + * used. + */ + uint16_t in_maxsize; + /** + * @brief OUT endpoint maximum packet size. + * @details This field must be set to zero if the OUT endpoint is not + * used. + */ + uint16_t out_maxsize; + /** + * @brief @p USBEndpointState associated to the IN endpoint. + * @details This structure maintains the state of the IN endpoint when + * the endpoint is not in packet mode. Endpoints configured in + * packet mode must set this field to @p NULL. + */ + USBInEndpointState *in_state; + /** + * @brief @p USBEndpointState associated to the OUT endpoint. + * @details This structure maintains the state of the OUT endpoint when + * the endpoint is not in packet mode. Endpoints configured in + * packet mode must set this field to @p NULL. + */ + USBOutEndpointState *out_state; + /* End of the mandatory fields.*/ +} USBEndpointConfig; + +/** + * @brief Type of an USB driver configuration structure. + */ +typedef struct { + /** + * @brief USB events callback. + * @details This callback is invoked when an USB driver event is registered. + */ + usbeventcb_t event_cb; + /** + * @brief Device GET_DESCRIPTOR request callback. + * @note This callback is mandatory and cannot be set to @p NULL. + */ + usbgetdescriptor_t get_descriptor_cb; + /** + * @brief Requests hook callback. + * @details This hook allows to be notified of standard requests or to + * handle non standard requests. + */ + usbreqhandler_t requests_hook_cb; + /** + * @brief Start Of Frame callback. + */ + usbcallback_t sof_cb; + /* End of the mandatory fields.*/ +} USBConfig; + +/** + * @brief Structure representing an USB driver. + */ +struct USBDriver { + /** + * @brief Driver state. + */ + usbstate_t state; + /** + * @brief Current configuration data. + */ + const USBConfig *config; + /** + * @brief Field available to user, it can be used to associate an + * application-defined handler to the USB driver. + */ + void *param; + /** + * @brief Bit map of the transmitting IN endpoints. + */ + uint16_t transmitting; + /** + * @brief Bit map of the receiving OUT endpoints. + */ + uint16_t receiving; + /** + * @brief Active endpoints configurations. + */ + const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1]; + /** + * @brief Endpoint 0 state. + */ + usbep0state_t ep0state; + /** + * @brief Next position in the buffer to be transferred through endpoint 0. + */ + uint8_t *ep0next; + /** + * @brief Number of bytes yet to be transferred through endpoint 0. + */ + size_t ep0n; + /** + * @brief Endpoint 0 end transaction callback. + */ + usbcallback_t ep0endcb; + /** + * @brief Setup packet buffer. + */ + uint8_t setup[8]; + /** + * @brief Current USB device status. + */ + uint16_t status; + /** + * @brief Assigned USB address. + */ + uint8_t address; + /** + * @brief Current USB device configuration. + */ + uint8_t configuration; +#if defined(USB_DRIVER_EXT_FIELDS) + USB_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Fetches a 16 bits word value from an USB message. + * + * @param[in] p pointer to the 16 bits word + * + * @notapi + */ +#define usb_lld_fetch_word(p) (*(uint16_t *)(p)) + +/** + * @brief Returns the current frame number. + * + * @param[in] usbp pointer to the @p USBDriver object + * @return The current frame number. + * + * @notapi + */ +#define usb_lld_get_frame_number(usbp) + +/** + * @brief Returns the exact size of a receive transaction. + * @details The received size can be different from the size specified in + * @p usbStartReceiveI() because the last packet could have a size + * different from the expected one. + * @pre The OUT endpoint must have been configured in transaction mode + * in order to use this function. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return Received data size. + * + * @notapi + */ +#define usb_lld_get_transaction_size(usbp, ep) + +/** + * @brief Returns the exact size of a received packet. + * @pre The OUT endpoint must have been configured in packet mode + * in order to use this function. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return Received data size. + * + * @notapi + */ +#define usb_lld_get_packet_size(usbp, ep) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void usb_lld_init(void); + void usb_lld_start(USBDriver *usbp); + void usb_lld_stop(USBDriver *usbp); + void usb_lld_reset(USBDriver *usbp); + void usb_lld_set_address(USBDriver *usbp); + void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep); + void usb_lld_disable_endpoints(USBDriver *usbp); + usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep); + usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep); + void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf); + size_t usb_lld_read_packet(USBDriver *usbp, usbep_t ep, + uint8_t *buf, size_t n); + void usb_lld_write_packet(USBDriver *usbp, usbep_t ep, + const uint8_t *buf, size_t n); + void usb_lld_start_out(USBDriver *usbp, usbep_t ep, + uint8_t *buf, size_t n); + void usb_lld_start_in(USBDriver *usbp, usbep_t ep, + const uint8_t *buf, size_t n); + void usb_lld_stall_in(USBDriver *usbp, usbep_t ep); + void usb_lld_stall_out(USBDriver *usbp, usbep_t ep); + void usb_lld_clear_out(USBDriver *usbp, usbep_t ep); + void usb_lld_clear_in(USBDriver *usbp, usbep_t ep); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_USB */ + +#endif /* _USB_LLD_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/ch.h b/Project/os/kernel/include/ch.h new file mode 100644 index 0000000..ea395dd --- /dev/null +++ b/Project/os/kernel/include/ch.h @@ -0,0 +1,123 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file ch.h + * @brief ChibiOS/RT main include file. + * @details This header includes all the required kernel headers so it is the + * only kernel header you usually want to include in your application. + * + * @addtogroup kernel_info + * @details Kernel related info. + * @{ + */ + +#ifndef _CH_H_ +#define _CH_H_ + +/** + * @brief ChibiOS/RT identification macro. + */ +#define _CHIBIOS_RT_ + +/** + * @brief Kernel version string. + */ +#define CH_KERNEL_VERSION "2.4.4" + +/** + * @name Kernel version + * @{ + */ +/** + * @brief Kernel version major number. + */ +#define CH_KERNEL_MAJOR 2 + +/** + * @brief Kernel version minor number. + */ +#define CH_KERNEL_MINOR 4 + +/** + * @brief Kernel version patch number. + */ +#define CH_KERNEL_PATCH 4 +/** @} */ + +/* + * Common values. + */ +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE (!FALSE) +#endif + +#include "chconf.h" +#include "chtypes.h" +#include "chlists.h" +#include "chcore.h" +#include "chsys.h" +#include "chvt.h" +#include "chschd.h" +#include "chsem.h" +#include "chbsem.h" +#include "chmtx.h" +#include "chcond.h" +#include "chevents.h" +#include "chmsg.h" +#include "chmboxes.h" +#include "chmemcore.h" +#include "chheap.h" +#include "chmempools.h" +#include "chthreads.h" +#include "chdynamic.h" +#include "chregistry.h" +#include "chinline.h" +#include "chqueues.h" +#include "chstreams.h" +#include "chioch.h" +#include "chfiles.h" +#include "chdebug.h" + +#if !defined(__DOXYGEN__) +extern WORKING_AREA(_idle_thread_wa, PORT_IDLE_THREAD_STACK_SIZE); +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _idle_thread(void *p); +#ifdef __cplusplus +} +#endif + +#endif /* _CH_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chbsem.h b/Project/os/kernel/include/chbsem.h new file mode 100644 index 0000000..18122af --- /dev/null +++ b/Project/os/kernel/include/chbsem.h @@ -0,0 +1,258 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chbsem.h + * @brief Binary semaphores structures and macros. + * + * @addtogroup binary_semaphores + * @details Binary semaphores related APIs and services. + * + *

Operation mode

+ * Binary semaphores are implemented as a set of macros that use the + * existing counting semaphores primitives. The difference between + * counting and binary semaphores is that the counter of binary + * semaphores is not allowed to grow above the value 1. Repeated + * signal operation are ignored. A binary semaphore can thus have + * only two defined states: + * - Taken, when its counter has a value of zero or lower + * than zero. A negative number represent the number of threads + * queued on the binary semaphore. + * - Not taken, when its counter has a value of one. + * . + * Binary semaphores are different from mutexes because there is no + * the concept of ownership, a binary semaphore can be taken by a + * thread and signaled by another thread or an interrupt handler, + * mutexes can only be taken and released by the same thread. Another + * difference is that binary semaphores, unlike mutexes, do not + * implement the priority inheritance protocol.
+ * In order to use the binary semaphores APIs the @p CH_USE_SEMAPHORES + * option must be enabled in @p chconf.h. + * @{ + */ + +#ifndef _CHBSEM_H_ +#define _CHBSEM_H_ + +#if CH_USE_SEMAPHORES || defined(__DOXYGEN__) + +/** + * @extends Semaphore + * + * @brief Binary semaphore type. + */ +typedef struct { + Semaphore bs_sem; +} BinarySemaphore; + +/** + * @brief Data part of a static semaphore initializer. + * @details This macro should be used when statically initializing a semaphore + * that is part of a bigger structure. + * + * @param[in] name the name of the semaphore variable + * @param[in] taken the semaphore initial state + */ +#define _BSEMAPHORE_DATA(name, taken) \ + {_SEMAPHORE_DATA(name.bs_sem, ((taken) ? 0 : 1))} + +/** + * @brief Static semaphore initializer. + * @details Statically initialized semaphores require no explicit + * initialization using @p chSemInit(). + * + * @param[in] name the name of the semaphore variable + * @param[in] taken the semaphore initial state + */ +#define BSEMAPHORE_DECL(name, taken) \ + BinarySemaphore name = _BSEMAPHORE_DATA(name, taken) + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Initializes a binary semaphore. + * + * @param[out] bsp pointer to a @p BinarySemaphore structure + * @param[in] taken initial state of the binary semaphore: + * - @a FALSE, the initial state is not taken. + * - @a TRUE, the initial state is taken. + * . + * + * @init + */ +#define chBSemInit(bsp, taken) chSemInit(&(bsp)->bs_sem, (taken) ? 0 : 1) + +/** + * @brief Wait operation on the binary semaphore. + * + * @param[in] bsp pointer to a @p BinarySemaphore structure + * @return A message specifying how the invoking thread has been + * released from the semaphore. + * @retval RDY_OK if the binary semaphore has been successfully taken. + * @retval RDY_RESET if the binary semaphore has been reset using + * @p bsemReset(). + * + * @api + */ +#define chBSemWait(bsp) chSemWait(&(bsp)->bs_sem) + +/** + * @brief Wait operation on the binary semaphore. + * + * @param[in] bsp pointer to a @p BinarySemaphore structure + * @return A message specifying how the invoking thread has been + * released from the semaphore. + * @retval RDY_OK if the binary semaphore has been successfully taken. + * @retval RDY_RESET if the binary semaphore has been reset using + * @p bsemReset(). + * + * @sclass + */ +#define chBSemWaitS(bsp) chSemWaitS(&(bsp)->bs_sem) + +/** + * @brief Wait operation on the binary semaphore. + * + * @param[in] bsp pointer to a @p BinarySemaphore structure + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return A message specifying how the invoking thread has been + * released from the semaphore. + * @retval RDY_OK if the binary semaphore has been successfully taken. + * @retval RDY_RESET if the binary semaphore has been reset using + * @p bsemReset(). + * @retval RDY_TIMEOUT if the binary semaphore has not been signaled or reset + * within the specified timeout. + * + * @api + */ +#define chBSemWaitTimeout(bsp, time) chSemWaitTimeout(&(bsp)->bs_sem, (time)) + +/** + * @brief Wait operation on the binary semaphore. + * + * @param[in] bsp pointer to a @p BinarySemaphore structure + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return A message specifying how the invoking thread has been + * released from the semaphore. + * @retval RDY_OK if the binary semaphore has been successfully taken. + * @retval RDY_RESET if the binary semaphore has been reset using + * @p bsemReset(). + * @retval RDY_TIMEOUT if the binary semaphore has not been signaled or reset + * within the specified timeout. + * + * @sclass + */ +#define chBSemWaitTimeoutS(bsp, time) chSemWaitTimeoutS(&(bsp)->bs_sem, (time)) + +/** + * @brief Reset operation on the binary semaphore. + * @note The released threads can recognize they were waked up by a reset + * rather than a signal because the @p bsemWait() will return + * @p RDY_RESET instead of @p RDY_OK. + * + * @param[in] bsp pointer to a @p BinarySemaphore structure + * @param[in] taken new state of the binary semaphore + * - @a FALSE, the new state is not taken. + * - @a TRUE, the new state is taken. + * . + * + * @api + */ +#define chBSemReset(bsp, taken) chSemReset(&(bsp)->bs_sem, (taken) ? 0 : 1) + +/** + * @brief Reset operation on the binary semaphore. + * @note The released threads can recognize they were waked up by a reset + * rather than a signal because the @p bsemWait() will return + * @p RDY_RESET instead of @p RDY_OK. + * @note This function does not reschedule. + * + * @param[in] bsp pointer to a @p BinarySemaphore structure + * @param[in] taken new state of the binary semaphore + * - @a FALSE, the new state is not taken. + * - @a TRUE, the new state is taken. + * . + * + * @iclass + */ +#define chBSemResetI(bsp, taken) chSemResetI(&(bsp)->bs_sem, (taken) ? 0 : 1) + +/** + * @brief Performs a signal operation on a binary semaphore. + * + * @param[in] bsp pointer to a @p BinarySemaphore structure + * + * @api + */ +#define chBSemSignal(bsp) { \ + chSysLock(); \ + chBSemSignalI((bsp)); \ + chSchRescheduleS(); \ + chSysUnlock(); \ +} + +/** + * @brief Performs a signal operation on a binary semaphore. + * @note This function does not reschedule. + * + * @param[in] bsp pointer to a @p BinarySemaphore structure + * + * @iclass + */ +#define chBSemSignalI(bsp) { \ + if ((bsp)->bs_sem.s_cnt < 1) \ + chSemSignalI(&(bsp)->bs_sem); \ +} + +/** + * @brief Returns the binary semaphore current state. + * + * @param[in] bsp pointer to a @p BinarySemaphore structure + * @return The binary semaphore current state. + * @retval FALSE if the binary semaphore is not taken. + * @retval TRUE if the binary semaphore is taken. + * + * @iclass + */ +#define chBSemGetStateI(bsp) ((bsp)->bs_sem.s_cnt > 0 ? FALSE : TRUE) +/** @} */ + +#endif /* CH_USE_SEMAPHORES */ + +#endif /* _CHBSEM_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chcond.h b/Project/os/kernel/include/chcond.h new file mode 100644 index 0000000..d8422d1 --- /dev/null +++ b/Project/os/kernel/include/chcond.h @@ -0,0 +1,98 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ +/* + Concepts and parts of this file have been contributed by Leon Woestenberg. + */ + +/** + * @file chcond.h + * @brief Condition Variables macros and structures. + * + * @addtogroup condvars + * @{ + */ + +#ifndef _CHCOND_H_ +#define _CHCOND_H_ + +#if CH_USE_CONDVARS || defined(__DOXYGEN__) + +/* + * Module dependencies check. + */ +#if !CH_USE_MUTEXES +#error "CH_USE_CONDVARS requires CH_USE_MUTEXES" +#endif + +/** + * @brief CondVar structure. + */ +typedef struct CondVar { + ThreadsQueue c_queue; /**< @brief CondVar threads queue.*/ +} CondVar; + +#ifdef __cplusplus +extern "C" { +#endif + void chCondInit(CondVar *cp); + void chCondSignal(CondVar *cp); + void chCondSignalI(CondVar *cp); + void chCondBroadcast(CondVar *cp); + void chCondBroadcastI(CondVar *cp); + msg_t chCondWait(CondVar *cp); + msg_t chCondWaitS(CondVar *cp); +#if CH_USE_CONDVARS_TIMEOUT + msg_t chCondWaitTimeout(CondVar *cp, systime_t time); + msg_t chCondWaitTimeoutS(CondVar *cp, systime_t time); +#endif +#ifdef __cplusplus +} +#endif + +/** + * @brief Data part of a static condition variable initializer. + * @details This macro should be used when statically initializing a condition + * variable that is part of a bigger structure. + * + * @param[in] name the name of the condition variable + */ +#define _CONDVAR_DATA(name) {_THREADSQUEUE_DATA(name.c_queue)} + +/** + * @brief Static condition variable initializer. + * @details Statically initialized condition variables require no explicit + * initialization using @p chCondInit(). + * + * @param[in] name the name of the condition variable + */ +#define CONDVAR_DECL(name) CondVar name = _CONDVAR_DATA(name) + +#endif /* CH_USE_CONDVARS */ + +#endif /* _CHCOND_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chdebug.h b/Project/os/kernel/include/chdebug.h new file mode 100644 index 0000000..1154981 --- /dev/null +++ b/Project/os/kernel/include/chdebug.h @@ -0,0 +1,248 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chdebug.h + * @brief Debug macros and structures. + * + * @addtogroup debug + * @{ + */ + +#ifndef _CHDEBUG_H_ +#define _CHDEBUG_H_ + +#if CH_DBG_ENABLE_ASSERTS || CH_DBG_ENABLE_CHECKS || \ + CH_DBG_ENABLE_STACK_CHECK || CH_DBG_SYSTEM_STATE_CHECK +#define CH_DBG_ENABLED TRUE +#else +#define CH_DBG_ENABLED FALSE +#endif + +#define __QUOTE_THIS(p) #p + +/*===========================================================================*/ +/** + * @name Debug related settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Trace buffer entries. + */ +#ifndef CH_TRACE_BUFFER_SIZE +#define CH_TRACE_BUFFER_SIZE 64 +#endif + +/** + * @brief Fill value for thread stack area in debug mode. + */ +#ifndef CH_STACK_FILL_VALUE +#define CH_STACK_FILL_VALUE 0x55 +#endif + +/** + * @brief Fill value for thread area in debug mode. + * @note The chosen default value is 0xFF in order to make evident which + * thread fields were not initialized when inspecting the memory with + * a debugger. A uninitialized field is not an error in itself but it + * better to know it. + */ +#ifndef CH_THREAD_FILL_VALUE +#define CH_THREAD_FILL_VALUE 0xFF +#endif + +/** @} */ + +/*===========================================================================*/ +/* System state checker related code and variables. */ +/*===========================================================================*/ + +#if !CH_DBG_SYSTEM_STATE_CHECK +#define dbg_check_disable() +#define dbg_check_suspend() +#define dbg_check_enable() +#define dbg_check_lock() +#define dbg_check_unlock() +#define dbg_check_lock_from_isr() +#define dbg_check_unlock_from_isr() +#define dbg_check_enter_isr() +#define dbg_check_leave_isr() +#define chDbgCheckClassI(); +#define chDbgCheckClassS(); +#endif + +/*===========================================================================*/ +/* Trace related structures and macros. */ +/*===========================================================================*/ + +#if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__) +/** + * @brief Trace buffer record. + */ +typedef struct { + systime_t se_time; /**< @brief Time of the switch event. */ + Thread *se_tp; /**< @brief Switched in thread. */ + void *se_wtobjp; /**< @brief Object where going to sleep.*/ + uint8_t se_state; /**< @brief Switched out thread state. */ +} ch_swc_event_t; + +/** + * @brief Trace buffer header. + */ +typedef struct { + unsigned tb_size; /**< @brief Trace buffer size (entries).*/ + ch_swc_event_t *tb_ptr; /**< @brief Pointer to the buffer front.*/ + /** @brief Ring buffer.*/ + ch_swc_event_t tb_buffer[CH_TRACE_BUFFER_SIZE]; +} ch_trace_buffer_t; + +#if !defined(__DOXYGEN__) +extern ch_trace_buffer_t dbg_trace_buffer; +#endif + +#endif /* CH_DBG_ENABLE_TRACE */ + +#if !CH_DBG_ENABLE_TRACE +/* When the trace feature is disabled this function is replaced by an empty + macro.*/ +#define dbg_trace(otp) +#endif + +/*===========================================================================*/ +/* Parameters checking related macros. */ +/*===========================================================================*/ + +#if CH_DBG_ENABLE_CHECKS || defined(__DOXYGEN__) +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Function parameter check. + * @details If the condition check fails then the kernel panics and halts. + * @note The condition is tested only if the @p CH_DBG_ENABLE_CHECKS switch + * is specified in @p chconf.h else the macro does nothing. + * + * @param[in] c the condition to be verified to be true + * @param[in] func the undecorated function name + * + * @api + */ +#if !defined(chDbgCheck) +#define chDbgCheck(c, func) { \ + if (!(c)) \ + chDbgPanic(__QUOTE_THIS(func)"()"); \ +} +#endif /* !defined(chDbgCheck) */ +/** @} */ +#else /* !CH_DBG_ENABLE_CHECKS */ +#define chDbgCheck(c, func) { \ + (void)(c), (void)__QUOTE_THIS(func)"()"; \ +} +#endif /* !CH_DBG_ENABLE_CHECKS */ + +/*===========================================================================*/ +/* Assertions related macros. */ +/*===========================================================================*/ + +#if CH_DBG_ENABLE_ASSERTS || defined(__DOXYGEN__) +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Condition assertion. + * @details If the condition check fails then the kernel panics with the + * specified message and halts. + * @note The condition is tested only if the @p CH_DBG_ENABLE_ASSERTS switch + * is specified in @p chconf.h else the macro does nothing. + * @note The convention for the message is the following:
+ * @(), #@ + * @note The remark string is not currently used except for putting a + * comment in the code about the assertion. + * + * @param[in] c the condition to be verified to be true + * @param[in] m the text message + * @param[in] r a remark string + * + * @api + */ +#if !defined(chDbgAssert) +#define chDbgAssert(c, m, r) { \ + if (!(c)) \ + chDbgPanic(m); \ +} +#endif /* !defined(chDbgAssert) */ +/** @} */ +#else /* !CH_DBG_ENABLE_ASSERTS */ +#define chDbgAssert(c, m, r) {(void)(c);} +#endif /* !CH_DBG_ENABLE_ASSERTS */ + +extern char *dbg_panic_msg; + +/*===========================================================================*/ +/* Panic related macros. */ +/*===========================================================================*/ + +#if !CH_DBG_ENABLED +/* When the debug features are disabled this function is replaced by an empty + macro.*/ +#define chDbgPanic(msg) {} +#endif + +#ifdef __cplusplus +extern "C" { +#endif +#if CH_DBG_SYSTEM_STATE_CHECK + void dbg_check_disable(void); + void dbg_check_suspend(void); + void dbg_check_enable(void); + void dbg_check_lock(void); + void dbg_check_unlock(void); + void dbg_check_lock_from_isr(void); + void dbg_check_unlock_from_isr(void); + void dbg_check_enter_isr(void); + void dbg_check_leave_isr(void); + void chDbgCheckClassI(void); + void chDbgCheckClassS(void); +#endif +#if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__) + void _trace_init(void); + void dbg_trace(Thread *otp); +#endif +#if CH_DBG_ENABLED + void chDbgPanic(char *msg); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _CHDEBUG_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chdynamic.h b/Project/os/kernel/include/chdynamic.h new file mode 100644 index 0000000..3c3b8ef --- /dev/null +++ b/Project/os/kernel/include/chdynamic.h @@ -0,0 +1,75 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chdynamic.h + * @brief Dynamic threads macros and structures. + * + * @addtogroup dynamic_threads + * @{ + */ + +#ifndef _CHDYNAMIC_H_ +#define _CHDYNAMIC_H_ + +#if CH_USE_DYNAMIC || defined(__DOXYGEN__) + +/* + * Module dependencies check. + */ +#if CH_USE_DYNAMIC && !CH_USE_WAITEXIT +#error "CH_USE_DYNAMIC requires CH_USE_WAITEXIT" +#endif +#if CH_USE_DYNAMIC && !CH_USE_HEAP && !CH_USE_MEMPOOLS +#error "CH_USE_DYNAMIC requires CH_USE_HEAP and/or CH_USE_MEMPOOLS" +#endif + +/* + * Dynamic threads APIs. + */ +#ifdef __cplusplus +extern "C" { +#endif + Thread *chThdAddRef(Thread *tp); + void chThdRelease(Thread *tp); +#if CH_USE_HEAP + Thread *chThdCreateFromHeap(MemoryHeap *heapp, size_t size, + tprio_t prio, tfunc_t pf, void *arg); +#endif +#if CH_USE_MEMPOOLS + Thread *chThdCreateFromMemoryPool(MemoryPool *mp, tprio_t prio, + tfunc_t pf, void *arg); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* CH_USE_DYNAMIC */ + +#endif /* _CHDYNAMIC_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chevents.h b/Project/os/kernel/include/chevents.h new file mode 100644 index 0000000..38c1c17 --- /dev/null +++ b/Project/os/kernel/include/chevents.h @@ -0,0 +1,205 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chevents.h + * @brief Events macros and structures. + * + * @addtogroup events + * @{ + */ + +#ifndef _CHEVENTS_H_ +#define _CHEVENTS_H_ + +#if CH_USE_EVENTS || defined(__DOXYGEN__) + +typedef struct EventListener EventListener; + +/** + * @brief Event Listener structure. + */ +struct EventListener { + EventListener *el_next; /**< @brief Next Event Listener + registered on the Event + Source. */ + Thread *el_listener; /**< @brief Thread interested in the + Event Source. */ + eventmask_t el_mask; /**< @brief Event flags mask associated + by the thread to the Event + Source. */ +}; + +/** + * @brief Event Source structure. + */ +typedef struct EventSource { + EventListener *es_next; /**< @brief First Event Listener + registered on the Event + Source. */ +} EventSource; + +/** + * @brief Event Handler callback function. + */ +typedef void (*evhandler_t)(eventid_t); + +/** + * @brief Data part of a static event source initializer. + * @details This macro should be used when statically initializing an event + * source that is part of a bigger structure. + * @param name the name of the event source variable + */ +#define _EVENTSOURCE_DATA(name) {(void *)(&name)} + +/** + * @brief Static event source initializer. + * @details Statically initialized event sources require no explicit + * initialization using @p chEvtInit(). + * + * @param name the name of the event source variable + */ +#define EVENTSOURCE_DECL(name) EventSource name = _EVENTSOURCE_DATA(name) + +/** + * @brief All events allowed mask. + */ +#define ALL_EVENTS ((eventmask_t)-1) + +/** + * @brief Returns an event mask from an event identifier. + */ +#define EVENT_MASK(eid) ((eventmask_t)(1 << (eid))) + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Registers an Event Listener on an Event Source. + * @note Multiple Event Listeners can use the same event identifier, the + * listener will share the callback function. + * + * @param[in] esp pointer to the @p EventSource structure + * @param[out] elp pointer to the @p EventListener structure + * @param[in] eid numeric identifier assigned to the Event Listener. The + * identifier is used as index for the event callback + * function. + * The value must range between zero and the size, in bit, + * of the @p eventid_t type minus one. + * + * @api + */ +#define chEvtRegister(esp, elp, eid) \ + chEvtRegisterMask(esp, elp, EVENT_MASK(eid)) + +/** + * @brief Initializes an Event Source. + * @note This function can be invoked before the kernel is initialized + * because it just prepares a @p EventSource structure. + * + * @param[in] esp pointer to the @p EventSource structure + * + * @init + */ +#define chEvtInit(esp) \ + ((esp)->es_next = (EventListener *)(void *)(esp)) + +/** + * @brief Verifies if there is at least one @p EventListener registered. + * + * @param[in] esp pointer to the @p EventSource structure + * + * @iclass + */ +#define chEvtIsListeningI(esp) \ + ((void *)(esp) != (void *)(esp)->es_next) + +/** + * @brief Signals all the Event Listeners registered on the specified Event + * Source. + * + * @param[in] esp pointer to the @p EventSource structure + * + * @api + */ +#define chEvtBroadcast(esp) chEvtBroadcastFlags(esp, 0) + +/** + * @brief Signals all the Event Listeners registered on the specified Event + * Source. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note that + * interrupt handlers always reschedule on exit so an explicit + * reschedule must not be performed in ISRs. + * + * @param[in] esp pointer to the @p EventSource structure + * + * @iclass + */ +#define chEvtBroadcastI(esp) chEvtBroadcastFlagsI(esp, 0) +/** @} */ + +#ifdef __cplusplus +extern "C" { +#endif + void chEvtRegisterMask(EventSource *esp, + EventListener *elp, + eventmask_t mask); + void chEvtUnregister(EventSource *esp, EventListener *elp); + eventmask_t chEvtClearFlags(eventmask_t mask); + eventmask_t chEvtAddFlags(eventmask_t mask); + void chEvtSignalFlags(Thread *tp, eventmask_t mask); + void chEvtSignalFlagsI(Thread *tp, eventmask_t mask); + void chEvtBroadcastFlags(EventSource *esp, eventmask_t mask); + void chEvtBroadcastFlagsI(EventSource *esp, eventmask_t mask); + void chEvtDispatch(const evhandler_t *handlers, eventmask_t mask); +#if CH_OPTIMIZE_SPEED || !CH_USE_EVENTS_TIMEOUT + eventmask_t chEvtWaitOne(eventmask_t mask); + eventmask_t chEvtWaitAny(eventmask_t mask); + eventmask_t chEvtWaitAll(eventmask_t mask); +#endif +#if CH_USE_EVENTS_TIMEOUT + eventmask_t chEvtWaitOneTimeout(eventmask_t mask, systime_t time); + eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t time); + eventmask_t chEvtWaitAllTimeout(eventmask_t mask, systime_t time); +#endif +#ifdef __cplusplus +} +#endif + +#if !CH_OPTIMIZE_SPEED && CH_USE_EVENTS_TIMEOUT +#define chEvtWaitOne(mask) chEvtWaitOneTimeout(mask, TIME_INFINITE) +#define chEvtWaitAny(mask) chEvtWaitAnyTimeout(mask, TIME_INFINITE) +#define chEvtWaitAll(mask) chEvtWaitAllTimeout(mask, TIME_INFINITE) +#endif + +#endif /* CH_USE_EVENTS */ + +#endif /* _CHEVENTS_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chfiles.h b/Project/os/kernel/include/chfiles.h new file mode 100644 index 0000000..0a1e84e --- /dev/null +++ b/Project/os/kernel/include/chfiles.h @@ -0,0 +1,172 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chfiles.h + * @brief Data files. + * @details This header defines abstract interfaces useful to access generic + * data files in a standardized way. + * + * @addtogroup data_files + * @details This module define an abstract interface for generic data files by + * extending the @p BaseSequentialStream interface. Note that no code + * is present, data files are just abstract interface-like structures, + * you should look at the systems as to a set of abstract C++ classes + * (even if written in C). This system has the advantage to make the + * access to streams independent from the implementation logic.
+ * The data files interface can be used as base class for high level + * object types such as an API for a File System implementation. + * @{ + */ + +#ifndef _CHFILES_H_ +#define _CHFILES_H_ + +/** + * @brief No error return code. + */ +#define FILE_OK 0 + +/** + * @brief Error code from the file stream methods. + */ +#define FILE_ERROR 0xFFFFFFFFUL + +/** + * @brief File offset type. + */ +typedef uint32_t fileoffset_t; + +/** + * @brief BaseFileStream specific methods. + */ +#define _base_file_stream_methods \ + _base_sequential_stream_methods \ + /* File close method.*/ \ + uint32_t (*close)(void *instance); \ + /* Get last error code method.*/ \ + int (*geterror)(void *instance); \ + /* File get size method.*/ \ + fileoffset_t (*getsize)(void *instance); \ + /* File get current position method.*/ \ + fileoffset_t (*getposition)(void *instance); \ + /* File seek method.*/ \ + uint32_t (*lseek)(void *instance, fileoffset_t offset); + +/** + * @brief @p BaseFileStream specific data. + * @note It is empty because @p BaseFileStream is only an interface + * without implementation. + */ +#define _base_file_stream_data \ + _base_sequential_stream_data + +/** + * @extends BaseSequentialStreamVMT + * + * @brief @p BaseFileStream virtual methods table. + */ +struct BaseFileStreamVMT { + _base_file_stream_methods +}; + +/** + * @extends BaseSequentialStream + * + * @brief Base file stream class. + * @details This class represents a generic file data stream. + */ +typedef struct { + /** @brief Virtual Methods Table.*/ + const struct BaseFileStreamVMT *vmt; + _base_file_stream_data +} BaseFileStream; + +/** + * @name Macro Functions (BaseFileStream) + * @{ + */ +/** + * @brief Base file Stream close. + * @details The function closes a file stream. + * + * @param[in] ip pointer to a @p BaseFileStream or derived class + * @return The operation status. + * @retval FILE_OK no error. + * @retval FILE_ERROR operation failed. + * + * @api + */ +#define chFileStreamClose(ip) ((ip)->vmt->close(ip)) + +/** + * @brief Returns an implementation dependent error code. + * + * @param[in] ip pointer to a @p BaseFileStream or derived class + * @return Implementation dependent error code. + * + * @api + */ +#define chFileStreamGetError(ip) ((ip)->vmt->geterror(ip)) + +/** + * @brief Returns the current file size. + * + * @param[in] ip pointer to a @p BaseFileStream or derived class + * @return The file size. + * + * @api + */ +#define chFileStreamGetSize(ip) ((ip)->vmt->getsize(ip)) + +/** + * @brief Returns the current file pointer position. + * + * @param[in] ip pointer to a @p BaseFileStream or derived class + * @return The current position inside the file. + * + * @api + */ +#define chFileStreamGetPosition(ip) ((ip)->vmt->getposition(ip)) + +/** + * @brief Moves the file current pointer to an absolute position. + * + * @param[in] ip pointer to a @p BaseFileStream or derived class + * @param[in] offset new absolute position + * @return The operation status. + * @retval FILE_OK no error. + * @retval FILE_ERROR operation failed. + * + * @api + */ +#define chFileStreamSeek(ip, offset) ((ip)->vmt->lseek(ip, offset)) +/** @} */ + +#endif /* _CHFILES_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chheap.h b/Project/os/kernel/include/chheap.h new file mode 100644 index 0000000..65b3125 --- /dev/null +++ b/Project/os/kernel/include/chheap.h @@ -0,0 +1,101 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chheap.h + * @brief Heaps macros and structures. + * + * @addtogroup heaps + * @{ + */ + +#ifndef _CHHEAP_H_ +#define _CHHEAP_H_ + +#if CH_USE_HEAP || defined(__DOXYGEN__) + +/* + * Module dependencies check. + */ +#if !CH_USE_MEMCORE && !CH_USE_MALLOC_HEAP +#error "CH_USE_HEAP requires CH_USE_MEMCORE or CH_USE_MALLOC_HEAP" +#endif + +#if !CH_USE_MUTEXES && !CH_USE_SEMAPHORES +#error "CH_USE_HEAP requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES" +#endif + +typedef struct memory_heap MemoryHeap; + +/** + * @brief Memory heap block header. + */ +union heap_header { + stkalign_t align; + struct { + union { + union heap_header *next; /**< @brief Next block in free list. */ + MemoryHeap *heap; /**< @brief Block owner heap. */ + } u; /**< @brief Overlapped fields. */ + size_t size; /**< @brief Size of the memory block. */ + } h; +}; + +/** + * @brief Structure describing a memory heap. + */ +struct memory_heap { + memgetfunc_t h_provider; /**< @brief Memory blocks provider for + this heap. */ + union heap_header h_free; /**< @brief Free blocks list header. */ +#if CH_USE_MUTEXES + Mutex h_mtx; /**< @brief Heap access mutex. */ +#else + Semaphore h_sem; /**< @brief Heap access semaphore. */ +#endif +}; + +#ifdef __cplusplus +extern "C" { +#endif + void _heap_init(void); +#if !CH_USE_MALLOC_HEAP + void chHeapInit(MemoryHeap *heapp, void *buf, size_t size); +#endif + void *chHeapAlloc(MemoryHeap *heapp, size_t size); + void chHeapFree(void *p); + size_t chHeapStatus(MemoryHeap *heapp, size_t *sizep); + void chHeapMaxMinFraq(MemoryHeap *heapp, size_t *min, size_t *max); +#ifdef __cplusplus +} +#endif + +#endif /* CH_USE_HEAP */ + +#endif /* _CHHEAP_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chinline.h b/Project/os/kernel/include/chinline.h new file mode 100644 index 0000000..3bbd1b3 --- /dev/null +++ b/Project/os/kernel/include/chinline.h @@ -0,0 +1,94 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chinline.h + * @brief Kernel inlined functions. + * @details In this file there are a set of inlined functions if the + * @p CH_OPTIMIZE_SPEED is enabled. + */ + +#ifndef _CHINLINE_H_ +#define _CHINLINE_H_ + +/* If the performance code path has been chosen then all the following + functions are inlined into the various kernel modules.*/ +#if CH_OPTIMIZE_SPEED +static INLINE void prio_insert(Thread *tp, ThreadsQueue *tqp) { + + Thread *cp = (Thread *)tqp; + do { + cp = cp->p_next; + } while ((cp != (Thread *)tqp) && (cp->p_prio >= tp->p_prio)); + tp->p_next = cp; + tp->p_prev = cp->p_prev; + tp->p_prev->p_next = cp->p_prev = tp; +} + +static INLINE void queue_insert(Thread *tp, ThreadsQueue *tqp) { + + tp->p_next = (Thread *)tqp; + tp->p_prev = tqp->p_prev; + tp->p_prev->p_next = tqp->p_prev = tp; +} + +static INLINE Thread *fifo_remove(ThreadsQueue *tqp) { + Thread *tp = tqp->p_next; + + (tqp->p_next = tp->p_next)->p_prev = (Thread *)tqp; + return tp; +} + +static INLINE Thread *lifo_remove(ThreadsQueue *tqp) { + Thread *tp = tqp->p_prev; + + (tqp->p_prev = tp->p_prev)->p_next = (Thread *)tqp; + return tp; +} + +static INLINE Thread *dequeue(Thread *tp) { + + tp->p_prev->p_next = tp->p_next; + tp->p_next->p_prev = tp->p_prev; + return tp; +} + +static INLINE void list_insert(Thread *tp, ThreadsList *tlp) { + + tp->p_next = tlp->p_next; + tlp->p_next = tp; +} + +static INLINE Thread *list_remove(ThreadsList *tlp) { + + Thread *tp = tlp->p_next; + tlp->p_next = tp->p_next; + return tp; +} +#endif /* CH_OPTIMIZE_SPEED */ + +#endif /* _CHINLINE_H_ */ diff --git a/Project/os/kernel/include/chioch.h b/Project/os/kernel/include/chioch.h new file mode 100644 index 0000000..c1804e8 --- /dev/null +++ b/Project/os/kernel/include/chioch.h @@ -0,0 +1,377 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chioch.h + * @brief I/O channels. + * @details This header defines abstract interfaces useful to access generic + * I/O resources in a standardized way. + * + * @addtogroup io_channels + * @details This module defines an abstract interface for I/O channels by + * extending the @p BaseSequentialStream interface. Note that no code + * is present, I/O channels are just abstract interface like + * structures, you should look at the systems as to a set of abstract + * C++ classes (even if written in C). Specific device drivers can + * use/extend the interface and implement them.
+ * This system has the advantage to make the access to channels + * independent from the implementation logic. + * @{ + */ + +#ifndef _CHIOCH_H_ +#define _CHIOCH_H_ + +/** + * @brief @p BaseChannel specific methods. + */ +#define _base_channel_methods \ + _base_sequential_stream_methods \ + /* Channel output check.*/ \ + bool_t (*putwouldblock)(void *instance); \ + /* Channel input check.*/ \ + bool_t (*getwouldblock)(void *instance); \ + /* Channel put method with timeout specification.*/ \ + msg_t (*put)(void *instance, uint8_t b, systime_t time); \ + /* Channel get method with timeout specification.*/ \ + msg_t (*get)(void *instance, systime_t time); \ + /* Channel write method with timeout specification.*/ \ + size_t (*writet)(void *instance, const uint8_t *bp, \ + size_t n, systime_t time); \ + /* Channel read method with timeout specification.*/ \ + size_t (*readt)(void *instance, uint8_t *bp, size_t n, systime_t time); + +/** + * @brief @p BaseChannel specific data. + * @note It is empty because @p BaseChannel is only an interface without + * implementation. + */ +#define _base_channel_data \ + _base_sequential_stream_data + +/** + * @extends BaseSequentialStreamVMT + * + * @brief @p BaseChannel virtual methods table. + */ +struct BaseChannelVMT { \ + _base_channel_methods \ +}; + +/** + * @extends BaseSequentialStream + * + * @brief Base channel class. + * @details This class represents a generic, byte-wide, I/O channel. This class + * introduces generic I/O primitives with timeout specification. + */ +typedef struct { + /** @brief Virtual Methods Table.*/ + const struct BaseChannelVMT *vmt; + _base_channel_data +} BaseChannel; + +/** + * @name Macro Functions (BaseChannel) + * @{ + */ +/** + * @brief Channel output check. + * @details This function verifies if a subsequent put/write operation would + * block. + * + * @param[in] ip pointer to a @p BaseChannel or derived class + * @return The output queue status. + * @retval FALSE if the output queue has space and would not block a + * write operation. + * @retval TRUE if the output queue is full and would block a write + * operation. + * + * @api + */ +#define chIOPutWouldBlock(ip) ((ip)->vmt->putwouldblock(ip)) + +/** + * @brief Channel input check. + * @details This function verifies if a subsequent get/read operation would + * block. + * + * @param[in] ip pointer to a @p BaseChannel or derived class + * @return The input queue status. + * @retval FALSE if the input queue contains data and would not block a + * read operation. + * @retval TRUE if the input queue is empty and would block a read + * operation. + * + * @api + */ +#define chIOGetWouldBlock(ip) ((ip)->vmt->getwouldblock(ip)) + +/** + * @brief Channel blocking byte write. + * @details This function writes a byte value to a channel. If the channel + * is not ready to accept data then the calling thread is suspended. + * + * @param[in] ip pointer to a @p BaseChannel or derived class + * @param[in] b the byte value to be written to the channel + * @return The operation status. + * @retval Q_OK if the operation succeeded. + * @retval Q_RESET if the channel associated queue (if any) was reset. + * + * @api + */ +#define chIOPut(ip, b) ((ip)->vmt->put(ip, b, TIME_INFINITE)) + +/** + * @brief Channel blocking byte write with timeout. + * @details This function writes a byte value to a channel. If the channel + * is not ready to accept data then the calling thread is suspended. + * + * @param[in] ip pointer to a @p BaseChannel or derived class + * @param[in] b the byte value to be written to the channel + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval Q_OK if the operation succeeded. + * @retval Q_TIMEOUT if the specified time expired. + * @retval Q_RESET if the channel associated queue (if any) was reset. + * + * @api + */ +#define chIOPutTimeout(ip, b, time) ((ip)->vmt->put(ip, b, time)) + +/** + * @brief Channel blocking byte read. + * @details This function reads a byte value from a channel. If the data + * is not available then the calling thread is suspended. + * + * @param[in] ip pointer to a @p BaseChannel or derived class + * @return A byte value from the queue. + * @retval Q_RESET if the channel associated queue (if any) has been + * reset. + * + * @api + */ +#define chIOGet(ip) ((ip)->vmt->get(ip, TIME_INFINITE)) + +/** + * @brief Channel blocking byte read with timeout. + * @details This function reads a byte value from a channel. If the data + * is not available then the calling thread is suspended. + * + * @param[in] ip pointer to a @p BaseChannel or derived class + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return A byte value from the queue. + * @retval Q_TIMEOUT if the specified time expired. + * @retval Q_RESET if the channel associated queue (if any) has been + * reset. + * + * @api + */ +#define chIOGetTimeout(ip, time) ((ip)->vmt->get(ip, time)) + +/** + * @brief Channel blocking write with timeout. + * @details The function writes data from a buffer to a channel. If the channel + * is not ready to accept data then the calling thread is suspended. + * + * @param[in] ip pointer to a @p BaseChannel or derived class + * @param[out] bp pointer to the data buffer + * @param[in] n the maximum amount of data to be transferred + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The number of bytes transferred. + * + * @api + */ +#define chIOWriteTimeout(ip, bp, n, time) \ + ((ip)->vmt->writet(ip, bp, n, time)) + +/** + * @brief Channel blocking read with timeout. + * @details The function reads data from a channel into a buffer. If the data + * is not available then the calling thread is suspended. + * + * @param[in] ip pointer to a @p BaseChannel or derived class + * @param[in] bp pointer to the data buffer + * @param[in] n the maximum amount of data to be transferred + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The number of bytes transferred. + * + * @api + */ +#define chIOReadTimeout(ip, bp, n, time) \ + ((ip)->vmt->readt(ip, bp, n, time)) +/** @} */ + +#if CH_USE_EVENTS || defined(__DOXYGEN__) +/** + * @name I/O status flags + * @{ + */ +/** @brief No pending conditions.*/ +#define IO_NO_ERROR 0 +/** @brief Connection happened.*/ +#define IO_CONNECTED 1 +/** @brief Disconnection happened.*/ +#define IO_DISCONNECTED 2 +/** @brief Data available in the input queue.*/ +#define IO_INPUT_AVAILABLE 4 +/** @brief Output queue empty.*/ +#define IO_OUTPUT_EMPTY 8 +/** @brief Transmission end.*/ +#define IO_TRANSMISSION_END 16 +/** @} */ + +/** + * @brief Type of an I/O condition flags mask. + */ +typedef uint_fast16_t ioflags_t; + +/** + * @brief @p BaseAsynchronousChannel specific methods. + */ +#define _base_asynchronous_channel_methods \ + _base_channel_methods \ + /* Channel read method with timeout specification.*/ \ + ioflags_t (*getflags)(void *instance); + +/** + * @brief @p BaseAsynchronousChannel specific data. + */ +#define _base_asynchronous_channel_data \ + _base_channel_data \ + /* I/O condition event source.*/ \ + EventSource event; \ + /* I/O condition flags.*/ \ + ioflags_t flags; + +/** + * @extends BaseChannelVMT + * + * @brief @p BaseAsynchronousChannel virtual methods table. + */ +struct BaseAsynchronousChannelVMT { + _base_asynchronous_channel_methods +}; + +/** + * @extends BaseChannel + * + * @brief Base asynchronous channel class. + * @details This class extends @p BaseChannel by adding event sources fields + * for asynchronous I/O for use in an event-driven environment. + */ +typedef struct { + /** @brief Virtual Methods Table.*/ + const struct BaseAsynchronousChannelVMT *vmt; + _base_asynchronous_channel_data +} BaseAsynchronousChannel; + +/** + * @name Macro Functions (BaseAsynchronousChannel) + * @{ + */ +/** + * @brief Returns the I/O condition event source. + * @details The event source is broadcasted when an I/O condition happens. + * + * @param[in] ip pointer to a @p BaseAsynchronousChannel or derived + * class + * @return A pointer to an @p EventSource object. + * + * @api + */ +#define chIOGetEventSource(ip) (&((ip)->event)) + +/** + * @brief Adds status flags to the channel's mask. + * @details This function is usually called from the I/O ISRs in order to + * notify I/O conditions such as data events, errors, signal + * changes etc. + * + * @param[in] ip pointer to a @p BaseAsynchronousChannel or derived + * class + * @param[in] mask condition flags to be added to the mask + * + * @iclass + */ +#define chIOAddFlagsI(ip, mask) { \ + (ip)->flags |= (mask); \ + chEvtBroadcastI(&(ip)->event); \ +} + +/** + * @brief Returns and clears the status flags associated to the channel. + * + * @param[in] ip pointer to a @p BaseAsynchronousChannel or derived + * class + * @return The condition flags modified since last time this + * function was invoked. + * + * @api + */ +#define chIOGetAndClearFlags(ip) ((ip)->vmt->getflags(ip)) +/** @} */ + +/** + * @brief Default implementation of the @p getflags virtual method. + * + * @param[in] ip pointer to a @p BaseAsynchronousChannel or derived + * class + * @return The condition flags modified since last time this + * function was invoked. + * + * @notapi + */ +#define _ch_get_and_clear_flags_impl(ip) \ + ioflags_t mask; \ + chSysLock(); \ + mask = ((BaseAsynchronousChannel *)(ip))->flags; \ + ((BaseAsynchronousChannel *)(ip))->flags = IO_NO_ERROR; \ + chSysUnlock(); \ + return mask + +#endif /* CH_USE_EVENTS */ + +#endif /* _CHIOCH_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chlists.h b/Project/os/kernel/include/chlists.h new file mode 100644 index 0000000..70aade8 --- /dev/null +++ b/Project/os/kernel/include/chlists.h @@ -0,0 +1,134 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chlists.h + * @brief Thread queues/lists macros and structures. + * @note All the macros present in this module, while public, are not + * an OS API and should not be directly used in the user applications + * code. + * + * @addtogroup internals + * @{ + */ + +#ifndef _CHLISTS_H_ +#define _CHLISTS_H_ + +typedef struct Thread Thread; + +/** + * @brief Threads queue initialization. + * + * @notapi + */ +#define queue_init(tqp) ((tqp)->p_next = (tqp)->p_prev = (Thread *)(tqp)); + +/** + * @brief Threads list initialization. + * + * @notapi + */ +#define list_init(tlp) ((tlp)->p_next = (Thread *)(tlp)) + +/** + * @brief Evaluates to @p TRUE if the specified threads queue or list is + * empty. + * + * @notapi + */ +#define isempty(p) ((p)->p_next == (Thread *)(p)) + +/** + * @brief Evaluates to @p TRUE if the specified threads queue or list is + * not empty. + * + * @notapi + */ +#define notempty(p) ((p)->p_next != (Thread *)(p)) + +/** + * @brief Data part of a static threads queue initializer. + * @details This macro should be used when statically initializing a threads + * queue that is part of a bigger structure. + * + * @param[in] name the name of the threads queue variable + */ +#define _THREADSQUEUE_DATA(name) {(Thread *)&name, (Thread *)&name} + +/** + * @brief Static threads queue initializer. + * @details Statically initialized threads queues require no explicit + * initialization using @p queue_init(). + * + * @param[in] name the name of the threads queue variable + */ +#define THREADSQUEUE_DECL(name) ThreadsQueue name = _THREADSQUEUE_DATA(name) + +/** + * @extends ThreadsList + * + * @brief Generic threads bidirectional linked list header and element. + */ +typedef struct { + Thread *p_next; /**< First @p Thread in the queue, or + @p ThreadQueue when empty. */ + Thread *p_prev; /**< Last @p Thread in the queue, or + @p ThreadQueue when empty. */ +} ThreadsQueue; + +/** + * @brief Generic threads single link list, it works like a stack. + */ +typedef struct { + + Thread *p_next; /**< Last pushed @p Thread on the stack + list, or pointer to itself if + empty. */ +} ThreadsList; + +#if !CH_OPTIMIZE_SPEED + +#ifdef __cplusplus +extern "C" { +#endif + void prio_insert(Thread *tp, ThreadsQueue *tqp); + void queue_insert(Thread *tp, ThreadsQueue *tqp); + Thread *fifo_remove(ThreadsQueue *tqp); + Thread *lifo_remove(ThreadsQueue *tqp); + Thread *dequeue(Thread *tp); + void list_insert(Thread *tp, ThreadsList *tlp); + Thread *list_remove(ThreadsList *tlp); +#ifdef __cplusplus +} +#endif + +#endif /* !CH_OPTIMIZE_SPEED */ + +#endif /* _CHLISTS_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chmboxes.h b/Project/os/kernel/include/chmboxes.h new file mode 100644 index 0000000..87fb655 --- /dev/null +++ b/Project/os/kernel/include/chmboxes.h @@ -0,0 +1,170 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chmboxes.h + * @brief Mailboxes macros and structures. + * + * @addtogroup mailboxes + * @{ + */ + +#ifndef _CHMBOXES_H_ +#define _CHMBOXES_H_ + +#if CH_USE_MAILBOXES || defined(__DOXYGEN__) + +/* + * Module dependencies check. + */ +#if !CH_USE_SEMAPHORES +#error "CH_USE_MAILBOXES requires CH_USE_SEMAPHORES" +#endif + +/** + * @brief Structure representing a mailbox object. + */ +typedef struct { + msg_t *mb_buffer; /**< @brief Pointer to the mailbox + buffer. */ + msg_t *mb_top; /**< @brief Pointer to the location + after the buffer. */ + msg_t *mb_wrptr; /**< @brief Write pointer. */ + msg_t *mb_rdptr; /**< @brief Read pointer. */ + Semaphore mb_fullsem; /**< @brief Full counter + @p Semaphore. */ + Semaphore mb_emptysem; /**< @brief Empty counter + @p Semaphore. */ +} Mailbox; + +#ifdef __cplusplus +extern "C" { +#endif + void chMBInit(Mailbox *mbp, msg_t *buf, cnt_t n); + void chMBReset(Mailbox *mbp); + msg_t chMBPost(Mailbox *mbp, msg_t msg, systime_t timeout); + msg_t chMBPostS(Mailbox *mbp, msg_t msg, systime_t timeout); + msg_t chMBPostI(Mailbox *mbp, msg_t msg); + msg_t chMBPostAhead(Mailbox *mbp, msg_t msg, systime_t timeout); + msg_t chMBPostAheadS(Mailbox *mbp, msg_t msg, systime_t timeout); + msg_t chMBPostAheadI(Mailbox *mbp, msg_t msg); + msg_t chMBFetch(Mailbox *mbp, msg_t *msgp, systime_t timeout); + msg_t chMBFetchS(Mailbox *mbp, msg_t *msgp, systime_t timeout); + msg_t chMBFetchI(Mailbox *mbp, msg_t *msgp); +#ifdef __cplusplus +} +#endif + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns the mailbox buffer size. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * + * @iclass + */ +#define chMBSizeI(mbp) \ + ((mbp)->mb_top - (mbp)->mb_buffer) + +/** + * @brief Returns the number of free message slots into a mailbox. + * @note Can be invoked in any system state but if invoked out of a locked + * state then the returned value may change after reading. + * @note The returned value can be less than zero when there are waiting + * threads on the internal semaphore. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @return The number of empty message slots. + * + * @iclass + */ +#define chMBGetFreeCountI(mbp) chSemGetCounterI(&(mbp)->mb_emptysem) + +/** + * @brief Returns the number of used message slots into a mailbox. + * @note Can be invoked in any system state but if invoked out of a locked + * state then the returned value may change after reading. + * @note The returned value can be less than zero when there are waiting + * threads on the internal semaphore. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @return The number of queued messages. + * + * @iclass + */ +#define chMBGetUsedCountI(mbp) chSemGetCounterI(&(mbp)->mb_fullsem) + +/** + * @brief Returns the next message in the queue without removing it. + * @pre A message must be waiting in the queue for this function to work + * or it would return garbage. The correct way to use this macro is + * to use @p chMBGetFullCountI() and then use this macro, all within + * a lock state. + * + * @iclass + */ +#define chMBPeekI(mbp) (*(mbp)->mb_rdptr) +/** @} */ + +/** + * @brief Data part of a static mailbox initializer. + * @details This macro should be used when statically initializing a + * mailbox that is part of a bigger structure. + * + * @param[in] name the name of the mailbox variable + * @param[in] buffer pointer to the mailbox buffer area + * @param[in] size size of the mailbox buffer area + */ +#define _MAILBOX_DATA(name, buffer, size) { \ + (msg_t *)(buffer), \ + (msg_t *)(buffer) + size, \ + (msg_t *)(buffer), \ + (msg_t *)(buffer), \ + _SEMAPHORE_DATA(name.mb_fullsem, 0), \ + _SEMAPHORE_DATA(name.mb_emptysem, size), \ +} + +/** + * @brief Static mailbox initializer. + * @details Statically initialized mailboxes require no explicit + * initialization using @p chMBInit(). + * + * @param[in] name the name of the mailbox variable + * @param[in] buffer pointer to the mailbox buffer area + * @param[in] size size of the mailbox buffer area + */ +#define MAILBOX_DECL(name, buffer, size) \ + Mailbox name = _MAILBOX_DATA(name, buffer, size) + +#endif /* CH_USE_MAILBOXES */ + +#endif /* _CHMBOXES_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chmemcore.h b/Project/os/kernel/include/chmemcore.h new file mode 100644 index 0000000..ffb57d7 --- /dev/null +++ b/Project/os/kernel/include/chmemcore.h @@ -0,0 +1,93 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chmemcore.h + * @brief Core memory manager macros and structures. + * + * @addtogroup memcore + * @{ + */ + +#ifndef _CHMEMCORE_H_ +#define _CHMEMCORE_H_ + +/** + * @brief Memory get function. + * @note This type must be assignment compatible with the @p chMemAlloc() + * function. + */ +typedef void *(*memgetfunc_t)(size_t size); + +/** + * @name Alignment support macros + */ +/** + * @brief Alignment size constant. + */ +#define MEM_ALIGN_SIZE sizeof(stkalign_t) + +/** + * @brief Alignment mask constant. + */ +#define MEM_ALIGN_MASK (MEM_ALIGN_SIZE - 1) + +/** + * @brief Alignment helper macro. + */ +#define MEM_ALIGN_PREV(p) ((size_t)(p) & ~MEM_ALIGN_MASK) + +/** + * @brief Alignment helper macro. + */ +#define MEM_ALIGN_NEXT(p) MEM_ALIGN_PREV((size_t)(p) + MEM_ALIGN_MASK) + +/** + * @brief Returns whatever a pointer or memory size is aligned to + * the type @p align_t. + */ +#define MEM_IS_ALIGNED(p) (((size_t)(p) & MEM_ALIGN_MASK) == 0) +/** @} */ + +#if CH_USE_MEMCORE || defined(__DOXYGEN__) + +#ifdef __cplusplus +extern "C" { +#endif + void _core_init(void); + void *chCoreAlloc(size_t size); + void *chCoreAllocI(size_t size); + size_t chCoreStatus(void); +#ifdef __cplusplus +} +#endif + +#endif /* CH_USE_MEMCORE */ + +#endif /* _CHMEMCORE_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chmempools.h b/Project/os/kernel/include/chmempools.h new file mode 100644 index 0000000..b4963a6 --- /dev/null +++ b/Project/os/kernel/include/chmempools.h @@ -0,0 +1,101 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chmempools.h + * @brief Memory Pools macros and structures. + * + * @addtogroup pools + * @{ + */ + +#ifndef _CHMEMPOOLS_H_ +#define _CHMEMPOOLS_H_ + +#if CH_USE_MEMPOOLS || defined(__DOXYGEN__) + +/** + * @brief Memory pool free object header. + */ +struct pool_header { + struct pool_header *ph_next; /**< @brief Pointer to the next pool + header in the list. */ +}; + +/** + * @brief Memory pool descriptor. + */ +typedef struct { + struct pool_header *mp_next; /**< @brief Pointer to the header. */ + size_t mp_object_size; /**< @brief Memory pool objects + size. */ + memgetfunc_t mp_provider; /**< @brief Memory blocks provider for + this pool. */ +} MemoryPool; + +/** + * @brief Data part of a static memory pool initializer. + * @details This macro should be used when statically initializing a + * memory pool that is part of a bigger structure. + * + * @param[in] name the name of the memory pool variable + * @param[in] size size of the memory pool contained objects + * @param[in] provider memory provider function for the memory pool + */ +#define _MEMORYPOOL_DATA(name, size, provider) \ + {NULL, MEM_ALIGN_NEXT(size), provider} + +/** + * @brief Static memory pool initializer in hungry mode. + * @details Statically initialized memory pools require no explicit + * initialization using @p chPoolInit(). + * + * @param[in] name the name of the memory pool variable + * @param[in] size size of the memory pool contained objects + * @param[in] provider memory provider function for the memory pool or @p NULL + * if the pool is not allowed to grow automatically + */ +#define MEMORYPOOL_DECL(name, size, provider) \ + MemoryPool name = _MEMORYPOOL_DATA(name, size, provider) + +#ifdef __cplusplus +extern "C" { +#endif + void chPoolInit(MemoryPool *mp, size_t size, memgetfunc_t provider); + void *chPoolAllocI(MemoryPool *mp); + void *chPoolAlloc(MemoryPool *mp); + void chPoolFreeI(MemoryPool *mp, void *objp); + void chPoolFree(MemoryPool *mp, void *objp); +#ifdef __cplusplus +} +#endif + +#endif /* CH_USE_MEMPOOLS */ + +#endif /* _CHMEMPOOLS_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chmsg.h b/Project/os/kernel/include/chmsg.h new file mode 100644 index 0000000..39d8883 --- /dev/null +++ b/Project/os/kernel/include/chmsg.h @@ -0,0 +1,104 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chmsg.h + * @brief Messages macros and structures. + * + * @addtogroup messages + * @{ + */ + +#ifndef _CHMSG_H_ +#define _CHMSG_H_ + +#if CH_USE_MESSAGES || defined(__DOXYGEN__) + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Evaluates to TRUE if the thread has pending messages. + * + * @iclass + */ +#define chMsgIsPendingI(tp) \ + ((tp)->p_msgqueue.p_next != (Thread *)&(tp)->p_msgqueue) + +/** + * @brief Returns the message carried by the specified thread. + * @pre This function must be invoked immediately after exiting a call + * to @p chMsgWait(). + * + * @param[in] tp pointer to the thread + * @return The message carried by the sender. + * + * @api + */ +#define chMsgGet(tp) ((tp)->p_msg) + +/** + * @brief Returns the message carried by the specified thread. + * @pre This function must be invoked immediately after exiting a call + * to @p chMsgWait(). + * + * @param[in] tp pointer to the thread + * @return The message carried by the sender. + * + * @sclass + */ +#define chMsgGetS(tp) ((tp)->p_msg) + +/** + * @brief Releases the thread waiting on top of the messages queue. + * @pre Invoke this function only after a message has been received + * using @p chMsgWait(). + * + * @param[in] tp pointer to the thread + * @param[in] msg message to be returned to the sender + * + * @sclass + */ +#define chMsgReleaseS(tp, msg) chSchWakeupS(tp, msg) +/** @} */ + +#ifdef __cplusplus +extern "C" { +#endif + msg_t chMsgSend(Thread *tp, msg_t msg); + Thread * chMsgWait(void); + void chMsgRelease(Thread *tp, msg_t msg); +#ifdef __cplusplus +} +#endif + +#endif /* CH_USE_MESSAGES */ + +#endif /* _CHMSG_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chmtx.h b/Project/os/kernel/include/chmtx.h new file mode 100644 index 0000000..d1477c1 --- /dev/null +++ b/Project/os/kernel/include/chmtx.h @@ -0,0 +1,103 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chmtx.h + * @brief Mutexes macros and structures. + * + * @addtogroup mutexes + * @{ + */ + +#ifndef _CHMTX_H_ +#define _CHMTX_H_ + +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + +/** + * @brief Mutex structure. + */ +typedef struct Mutex { + ThreadsQueue m_queue; /**< @brief Queue of the threads sleeping + on this Mutex. */ + Thread *m_owner; /**< @brief Owner @p Thread pointer or + @p NULL. */ + struct Mutex *m_next; /**< @brief Next @p Mutex into an + owner-list or @p NULL. */ +} Mutex; + +#ifdef __cplusplus +extern "C" { +#endif + void chMtxInit(Mutex *mp); + void chMtxLock(Mutex *mp); + void chMtxLockS(Mutex *mp); + bool_t chMtxTryLock(Mutex *mp); + bool_t chMtxTryLockS(Mutex *mp); + Mutex *chMtxUnlock(void); + Mutex *chMtxUnlockS(void); + void chMtxUnlockAll(void); +#ifdef __cplusplus +} +#endif + +/** + * @brief Data part of a static mutex initializer. + * @details This macro should be used when statically initializing a mutex + * that is part of a bigger structure. + * + * @param[in] name the name of the mutex variable + */ +#define _MUTEX_DATA(name) {_THREADSQUEUE_DATA(name.m_queue), NULL, NULL} + +/** + * @brief Static mutex initializer. + * @details Statically initialized mutexes require no explicit initialization + * using @p chMtxInit(). + * + * @param[in] name the name of the mutex variable + */ +#define MUTEX_DECL(name) Mutex name = _MUTEX_DATA(name) + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns @p TRUE if the mutex queue contains at least a waiting + * thread. + * + * @sclass + */ +#define chMtxQueueNotEmptyS(mp) notempty(&(mp)->m_queue) +/** @} */ + +#endif /* CH_USE_MUTEXES */ + +#endif /* _CHMTX_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chqueues.h b/Project/os/kernel/include/chqueues.h new file mode 100644 index 0000000..e131a82 --- /dev/null +++ b/Project/os/kernel/include/chqueues.h @@ -0,0 +1,356 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chqueues.h + * @brief I/O Queues macros and structures. + * + * @addtogroup io_queues + * @{ + */ + +#ifndef _CHQUEUES_H_ +#define _CHQUEUES_H_ + +#if CH_USE_QUEUES || defined(__DOXYGEN__) + +/** + * @name Queue functions returned status value + * @{ + */ +#define Q_OK RDY_OK /**< @brief Operation successful. */ +#define Q_TIMEOUT RDY_TIMEOUT /**< @brief Timeout condition. */ +#define Q_RESET RDY_RESET /**< @brief Queue has been reset. */ +#define Q_EMPTY -3 /**< @brief Queue empty. */ +#define Q_FULL -4 /**< @brief Queue full, */ +/** @} */ + +/** + * @brief Type of a generic I/O queue structure. + */ +typedef struct GenericQueue GenericQueue; + +/** @brief Queue notification callback type.*/ +typedef void (*qnotify_t)(GenericQueue *qp); + +/** + * @brief Generic I/O queue structure. + * @details This structure represents a generic Input or Output asymmetrical + * queue. The queue is asymmetrical because one end is meant to be + * accessed from a thread context, and thus can be blocking, the other + * end is accessible from interrupt handlers or from within a kernel + * lock zone (see I-Locked and S-Locked states in + * @ref system_states) and is non-blocking. + */ +struct GenericQueue { + ThreadsQueue q_waiting; /**< @brief Queue of waiting threads. */ + size_t q_counter; /**< @brief Resources counter. */ + uint8_t *q_buffer; /**< @brief Pointer to the queue buffer.*/ + uint8_t *q_top; /**< @brief Pointer to the first location + after the buffer. */ + uint8_t *q_wrptr; /**< @brief Write pointer. */ + uint8_t *q_rdptr; /**< @brief Read pointer. */ + qnotify_t q_notify; /**< @brief Data notification callback. */ +}; + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns the queue's buffer size. + * + * @param[in] qp pointer to a @p GenericQueue structure. + * @return The buffer size. + * + * @iclass + */ +#define chQSizeI(qp) ((size_t)((qp)->q_top - (qp)->q_buffer)) + +/** + * @brief Queue space. + * @details Returns the used space if used on an input queue or the empty + * space if used on an output queue. + * + * @param[in] qp pointer to a @p GenericQueue structure. + * @return The buffer space. + * + * @iclass + */ +#define chQSpaceI(qp) ((qp)->q_counter) +/** @} */ + +/** + * @extends GenericQueue + * + * @brief Type of an input queue structure. + * @details This structure represents a generic asymmetrical input queue. + * Writing to the queue is non-blocking and can be performed from + * interrupt handlers or from within a kernel lock zone (see + * I-Locked and S-Locked states in @ref system_states). + * Reading the queue can be a blocking operation and is supposed to + * be performed by a system thread. + */ +typedef GenericQueue InputQueue; + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns the filled space into an input queue. + * + * @param[in] iqp pointer to an @p InputQueue structure + * @return The number of full bytes in the queue. + * @retval 0 if the queue is empty. + * + * @iclass + */ +#define chIQGetFullI(iqp) chQSpaceI(iqp) + +/** + * @brief Returns the empty space into an input queue. + * + * @param[in] iqp pointer to an @p InputQueue structure + * @return The number of empty bytes in the queue. + * @retval 0 if the queue is full. + * + * @iclass + */ +#define chIQGetEmptyI(iqp) (chQSizeI(iqp) - chQSpaceI(iqp)) + +/** + * @brief Evaluates to @p TRUE if the specified input queue is empty. + * + * @param[in] iqp pointer to an @p InputQueue structure. + * @return The queue status. + * @retval FALSE The queue is not empty. + * @retval TRUE The queue is empty. + * + * @iclass + */ +#define chIQIsEmptyI(iqp) ((bool_t)(chQSpaceI(iqp) <= 0)) + +/** + * @brief Evaluates to @p TRUE if the specified input queue is full. + * + * @param[in] iqp pointer to an @p InputQueue structure. + * @return The queue status. + * @retval FALSE The queue is not full. + * @retval TRUE The queue is full. + * + * @iclass + */ +#define chIQIsFullI(iqp) ((bool_t)(((iqp)->q_wrptr == (iqp)->q_rdptr) && \ + ((iqp)->q_counter != 0))) + +/** + * @brief Input queue read. + * @details This function reads a byte value from an input queue. If the queue + * is empty then the calling thread is suspended until a byte arrives + * in the queue. + * + * @param[in] iqp pointer to an @p InputQueue structure + * @return A byte value from the queue. + * @retval Q_RESET if the queue has been reset. + * + * @api + */ +#define chIQGet(iqp) chIQGetTimeout(iqp, TIME_INFINITE) +/** @} */ + +/** + * @brief Data part of a static input queue initializer. + * @details This macro should be used when statically initializing an + * input queue that is part of a bigger structure. + * + * @param[in] name the name of the input queue variable + * @param[in] buffer pointer to the queue buffer area + * @param[in] size size of the queue buffer area + * @param[in] inotify input notification callback pointer + */ +#define _INPUTQUEUE_DATA(name, buffer, size, inotify) { \ + _THREADSQUEUE_DATA(name), \ + 0, \ + (uint8_t *)(buffer), \ + (uint8_t *)(buffer) + (size), \ + (uint8_t *)(buffer), \ + (uint8_t *)(buffer), \ + inotify \ +} + +/** + * @brief Static input queue initializer. + * @details Statically initialized input queues require no explicit + * initialization using @p chIQInit(). + * + * @param[in] name the name of the input queue variable + * @param[in] buffer pointer to the queue buffer area + * @param[in] size size of the queue buffer area + * @param[in] inotify input notification callback pointer + */ +#define INPUTQUEUE_DECL(name, buffer, size, inotify) \ + InputQueue name = _INPUTQUEUE_DATA(name, buffer, size, inotify) + +/** + * @extends GenericQueue + * + * @brief Type of an output queue structure. + * @details This structure represents a generic asymmetrical output queue. + * Reading from the queue is non-blocking and can be performed from + * interrupt handlers or from within a kernel lock zone (see + * I-Locked and S-Locked states in @ref system_states). + * Writing the queue can be a blocking operation and is supposed to + * be performed by a system thread. + */ +typedef GenericQueue OutputQueue; + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns the filled space into an output queue. + * + * @param[in] oqp pointer to an @p OutputQueue structure + * @return The number of full bytes in the queue. + * @retval 0 if the queue is empty. + * + * @iclass + */ +#define chOQGetFullI(oqp) (chQSizeI(oqp) - chQSpaceI(oqp)) + +/** + * @brief Returns the empty space into an output queue. + * + * @param[in] oqp pointer to an @p OutputQueue structure + * @return The number of empty bytes in the queue. + * @retval 0 if the queue is full. + * + * @iclass + */ +#define chOQGetEmptyI(oqp) chQSpaceI(oqp) + +/** + * @brief Evaluates to @p TRUE if the specified output queue is empty. + * + * @param[in] oqp pointer to an @p OutputQueue structure. + * @return The queue status. + * @retval FALSE The queue is not empty. + * @retval TRUE The queue is empty. + * + * @iclass + */ +#define chOQIsEmptyI(oqp) ((bool_t)(((oqp)->q_wrptr == (oqp)->q_rdptr) && \ + ((oqp)->q_counter != 0))) + +/** + * @brief Evaluates to @p TRUE if the specified output queue is full. + * + * @param[in] oqp pointer to an @p OutputQueue structure. + * @return The queue status. + * @retval FALSE The queue is not full. + * @retval TRUE The queue is full. + * + * @iclass + */ +#define chOQIsFullI(oqp) ((bool_t)(chQSpaceI(oqp) <= 0)) + +/** + * @brief Output queue write. + * @details This function writes a byte value to an output queue. If the queue + * is full then the calling thread is suspended until there is space + * in the queue. + * + * @param[in] oqp pointer to an @p OutputQueue structure + * @param[in] b the byte value to be written in the queue + * @return The operation status. + * @retval Q_OK if the operation succeeded. + * @retval Q_RESET if the queue has been reset. + * + * @api + */ +#define chOQPut(oqp, b) chOQPutTimeout(oqp, b, TIME_INFINITE) + /** @} */ + +/** + * @brief Data part of a static output queue initializer. + * @details This macro should be used when statically initializing an + * output queue that is part of a bigger structure. + * + * @param[in] name the name of the output queue variable + * @param[in] buffer pointer to the queue buffer area + * @param[in] size size of the queue buffer area + * @param[in] onotify output notification callback pointer + */ +#define _OUTPUTQUEUE_DATA(name, buffer, size, onotify) { \ + _THREADSQUEUE_DATA(name), \ + (size), \ + (uint8_t *)(buffer), \ + (uint8_t *)(buffer) + (size), \ + (uint8_t *)(buffer), \ + (uint8_t *)(buffer), \ + onotify \ +} + +/** + * @brief Static output queue initializer. + * @details Statically initialized output queues require no explicit + * initialization using @p chOQInit(). + * + * @param[in] name the name of the output queue variable + * @param[in] buffer pointer to the queue buffer area + * @param[in] size size of the queue buffer area + * @param[in] onotify output notification callback pointer + */ +#define OUTPUTQUEUE_DECL(name, buffer, size, onotify) \ + OutputQueue name = _OUTPUTQUEUE_DATA(name, buffer, size, onotify) + +#ifdef __cplusplus +extern "C" { +#endif + void chIQInit(InputQueue *iqp, uint8_t *bp, size_t size, qnotify_t infy); + void chIQResetI(InputQueue *iqp); + msg_t chIQPutI(InputQueue *iqp, uint8_t b); + msg_t chIQGetTimeout(InputQueue *iqp, systime_t time); + size_t chIQReadTimeout(InputQueue *iqp, uint8_t *bp, + size_t n, systime_t time); + + void chOQInit(OutputQueue *oqp, uint8_t *bp, size_t size, qnotify_t onfy); + void chOQResetI(OutputQueue *oqp); + msg_t chOQPutTimeout(OutputQueue *oqp, uint8_t b, systime_t time); + msg_t chOQGetI(OutputQueue *oqp); + size_t chOQWriteTimeout(OutputQueue *oqp, const uint8_t *bp, + size_t n, systime_t time); +#ifdef __cplusplus +} +#endif +#endif /* CH_USE_QUEUES */ + +#endif /* _CHQUEUES_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chregistry.h b/Project/os/kernel/include/chregistry.h new file mode 100644 index 0000000..182624a --- /dev/null +++ b/Project/os/kernel/include/chregistry.h @@ -0,0 +1,137 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chregistry.h + * @brief Threads registry macros and structures. + * + * @addtogroup registry + * @{ + */ + +#ifndef _CHREGISTRY_H_ +#define _CHREGISTRY_H_ + +#if CH_USE_REGISTRY || defined(__DOXYGEN__) + +/** + * @brief ChibiOS/RT memory signature record. + */ +typedef struct { + char ch_identifier[4]; /**< @brief Always set to "main". */ + uint8_t ch_zero; /**< @brief Must be zero. */ + uint8_t ch_size; /**< @brief Size of this structure. */ + uint16_t ch_version; /**< @brief Encoded ChibiOS/RT version. */ + uint8_t ch_ptrsize; /**< @brief Size of a pointer. */ + uint8_t ch_timesize; /**< @brief Size of a @p systime_t. */ + uint8_t ch_threadsize; /**< @brief Size of a @p Thread struct. */ + uint8_t cf_off_prio; /**< @brief Offset of @p p_prio field. */ + uint8_t cf_off_ctx; /**< @brief Offset of @p p_ctx field. */ + uint8_t cf_off_newer; /**< @brief Offset of @p p_newer field. */ + uint8_t cf_off_older; /**< @brief Offset of @p p_older field. */ + uint8_t cf_off_name; /**< @brief Offset of @p p_name field. */ + uint8_t cf_off_stklimit; /**< @brief Offset of @p p_stklimit + field. */ + uint8_t cf_off_state; /**< @brief Offset of @p p_state field. */ + uint8_t cf_off_flags; /**< @brief Offset of @p p_flags field. */ + uint8_t cf_off_refs; /**< @brief Offset of @p p_refs field. */ + uint8_t cf_off_preempt; /**< @brief Offset of @p p_preempt + field. */ + uint8_t cf_off_time; /**< @brief Offset of @p p_time field. */ +} chdebug_t; + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Sets the current thread name. + * @pre This function only stores the pointer to the name if the option + * @p CH_USE_REGISTRY is enabled else no action is performed. + * + * @param[in] p thread name as a zero terminated string + * + * @api + */ +#define chRegSetThreadName(p) (currp->p_name = (p)) + +/** + * @brief Returns the name of the specified thread. + * @pre This function only returns the pointer to the name if the option + * @p CH_USE_REGISTRY is enabled else @p NULL is returned. + * + * @param[in] tp pointer to the thread + * + * @return Thread name as a zero terminated string. + * @retval NULL if the thread name has not been set. + */ +#define chRegGetThreadName(tp) ((tp)->p_name) +/** @} */ +#else /* !CH_USE_REGISTRY */ +#define chRegSetThreadName(p) +#define chRegGetThreadName(tp) NULL +#endif /* !CH_USE_REGISTRY */ + +#if CH_USE_REGISTRY || defined(__DOXYGEN__) +/** + * @brief Removes a thread from the registry list. + * @note This macro is not meant for use in application code. + * + * @param[in] tp thread to remove from the registry + */ +#define REG_REMOVE(tp) { \ + (tp)->p_older->p_newer = (tp)->p_newer; \ + (tp)->p_newer->p_older = (tp)->p_older; \ +} + +/** + * @brief Adds a thread to the registry list. + * @note This macro is not meant for use in application code. + * + * @param[in] tp thread to add to the registry + */ +#define REG_INSERT(tp) { \ + (tp)->p_newer = (Thread *)&rlist; \ + (tp)->p_older = rlist.r_older; \ + (tp)->p_older->p_newer = rlist.r_older = (tp); \ +} + +#ifdef __cplusplus +extern "C" { +#endif + extern ROMCONST chdebug_t ch_debug; + Thread *chRegFirstThread(void); + Thread *chRegNextThread(Thread *tp); +#ifdef __cplusplus +} +#endif + +#endif /* CH_USE_REGISTRY */ + +#endif /* _CHREGISTRY_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chschd.h b/Project/os/kernel/include/chschd.h new file mode 100644 index 0000000..083b6ba --- /dev/null +++ b/Project/os/kernel/include/chschd.h @@ -0,0 +1,241 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chschd.h + * @brief Scheduler macros and structures. + * + * @addtogroup scheduler + * @{ + */ + +#ifndef _CHSCHD_H_ +#define _CHSCHD_H_ + +/** + * @name Wakeup status codes + * @{ + */ +#define RDY_OK 0 /**< @brief Normal wakeup message. */ +#define RDY_TIMEOUT -1 /**< @brief Wakeup caused by a timeout + condition. */ +#define RDY_RESET -2 /**< @brief Wakeup caused by a reset + condition. */ +/** @} */ + +/** + * @name Priority constants + * @{ + */ +#define NOPRIO 0 /**< @brief Ready list header priority. */ +#define IDLEPRIO 1 /**< @brief Idle thread priority. */ +#define LOWPRIO 2 /**< @brief Lowest user priority. */ +#define NORMALPRIO 64 /**< @brief Normal user priority. */ +#define HIGHPRIO 127 /**< @brief Highest user priority. */ +#define ABSPRIO 255 /**< @brief Greatest possible priority. */ +/** @} */ + +/** + * @name Special time constants + * @{ + */ +/** + * @brief Zero time specification for some functions with a timeout + * specification. + * @note Not all functions accept @p TIME_IMMEDIATE as timeout parameter, + * see the specific function documentation. + */ +#define TIME_IMMEDIATE ((systime_t)0) + +/** + * @brief Infinite time specification for all functions with a timeout + * specification. + */ +#define TIME_INFINITE ((systime_t)-1) +/** @} */ + +/** + * @brief Returns the priority of the first thread on the given ready list. + * + * @notapi + */ +#define firstprio(rlp) ((rlp)->p_next->p_prio) + +/** + * @extends ThreadsQueue + * + * @brief Ready list header. + */ +#if !defined(PORT_OPTIMIZED_READYLIST_STRUCT) || defined(__DOXYGEN__) +typedef struct { + ThreadsQueue r_queue; /**< @brief Threads queue. */ + tprio_t r_prio; /**< @brief This field must be + initialized to zero. */ + struct context r_ctx; /**< @brief Not used, present because + offsets. */ +#if CH_USE_REGISTRY || defined(__DOXYGEN__) + Thread *r_newer; /**< @brief Newer registry element. */ + Thread *r_older; /**< @brief Older registry element. */ +#endif + /* End of the fields shared with the Thread structure.*/ +#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__) + cnt_t r_preempt; /**< @brief Round robin counter. */ +#endif + Thread *r_current; /**< @brief The currently running + thread. */ +} ReadyList; +#endif /* !defined(PORT_OPTIMIZED_READYLIST_STRUCT) */ + +#if !defined(PORT_OPTIMIZED_RLIST_EXT) && !defined(__DOXYGEN__) +extern ReadyList rlist; +#endif /* !defined(PORT_OPTIMIZED_RLIST_EXT) */ + +/** + * @brief Current thread pointer access macro. + * @note This macro is not meant to be used in the application code but + * only from within the kernel, use the @p chThdSelf() API instead. + * @note It is forbidden to use this macro in order to change the pointer + * (currp = something), use @p setcurrp() instead. + */ +#if !defined(PORT_OPTIMIZED_CURRP) || defined(__DOXYGEN__) +#define currp rlist.r_current +#endif /* !defined(PORT_OPTIMIZED_CURRP) */ + +/** + * @brief Current thread pointer change macro. + * @note This macro is not meant to be used in the application code but + * only from within the kernel. + * + * @notapi + */ +#if !defined(PORT_OPTIMIZED_SETCURRP) || defined(__DOXYGEN__) +#define setcurrp(tp) (currp = (tp)) +#endif /* !defined(PORT_OPTIMIZED_SETCURRP) */ + +/* + * Scheduler APIs. + */ +#ifdef __cplusplus +extern "C" { +#endif + void _scheduler_init(void); +#if !defined(PORT_OPTIMIZED_READYI) + Thread *chSchReadyI(Thread *tp); +#endif +#if !defined(PORT_OPTIMIZED_GOSLEEPS) + void chSchGoSleepS(tstate_t newstate); +#endif +#if !defined(PORT_OPTIMIZED_GOSLEEPTIMEOUTS) + msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t time); +#endif +#if !defined(PORT_OPTIMIZED_WAKEUPS) + void chSchWakeupS(Thread *tp, msg_t msg); +#endif +#if !defined(PORT_OPTIMIZED_RESCHEDULES) + void chSchRescheduleS(void); +#endif +#if !defined(PORT_OPTIMIZED_ISPREEMPTIONREQUIRED) + bool_t chSchIsPreemptionRequired(void); +#endif +#if !defined(PORT_OPTIMIZED_DORESCHEDULE) + void chSchDoReschedule(void); +#endif +#ifdef __cplusplus +} +#endif + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Determines if the current thread must reschedule. + * @details This function returns @p TRUE if there is a ready thread with + * higher priority. + * + * @iclass + */ +#if !defined(PORT_OPTIMIZED_ISRESCHREQUIREDI) || defined(__DOXYGEN__) +#define chSchIsRescRequiredI() (firstprio(&rlist.r_queue) > currp->p_prio) +#endif /* !defined(PORT_OPTIMIZED_ISRESCHREQUIREDI) */ + +/** + * @brief Determines if yielding is possible. + * @details This function returns @p TRUE if there is a ready thread with + * equal or higher priority. + * + * @sclass + */ +#if !defined(PORT_OPTIMIZED_CANYIELDS) || defined(__DOXYGEN__) +#define chSchCanYieldS() (firstprio(&rlist.r_queue) >= currp->p_prio) +#endif /* !defined(PORT_OPTIMIZED_CANYIELDS) */ + +/** + * @brief Yields the time slot. + * @details Yields the CPU control to the next thread in the ready list with + * equal or higher priority, if any. + * + * @sclass + */ +#if !defined(PORT_OPTIMIZED_DOYIELDS) || defined(__DOXYGEN__) +#define chSchDoYieldS() { \ + if (chSchCanYieldS()) \ + chSchDoReschedule(); \ +} +#endif /* !defined(PORT_OPTIMIZED_DOYIELDS) */ + +/** + * @brief Inline-able preemption code. + * @details This is the common preemption code, this function must be invoked + * exclusively from the port layer. + * + * @special + */ +#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__) +#define chSchPreemption() { \ + tprio_t p1 = firstprio(&rlist.r_queue); \ + tprio_t p2 = currp->p_prio; \ + if (rlist.r_preempt) { \ + if (p1 > p2) \ + chSchDoReschedule(); \ + } \ + else { \ + if (p1 >= p2) \ + chSchDoReschedule(); \ + } \ +} +#else /* CH_TIME_QUANTUM == 0 */ +#define chSchPreemption() { \ + if (p1 >= p2) \ + chSchDoReschedule(); \ +} +#endif /* CH_TIME_QUANTUM == 0 */ +/** @} */ + +#endif /* _CHSCHD_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chsem.h b/Project/os/kernel/include/chsem.h new file mode 100644 index 0000000..9f46c42 --- /dev/null +++ b/Project/os/kernel/include/chsem.h @@ -0,0 +1,125 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chsem.h + * @brief Semaphores macros and structures. + * + * @addtogroup semaphores + * @{ + */ + +#ifndef _CHSEM_H_ +#define _CHSEM_H_ + +#if CH_USE_SEMAPHORES || defined(__DOXYGEN__) + +/** + * @brief Semaphore structure. + */ +typedef struct Semaphore { + ThreadsQueue s_queue; /**< @brief Queue of the threads sleeping + on this semaphore. */ + cnt_t s_cnt; /**< @brief The semaphore counter. */ +} Semaphore; + +#ifdef __cplusplus +extern "C" { +#endif + void chSemInit(Semaphore *sp, cnt_t n); + void chSemReset(Semaphore *sp, cnt_t n); + void chSemResetI(Semaphore *sp, cnt_t n); + msg_t chSemWait(Semaphore *sp); + msg_t chSemWaitS(Semaphore *sp); + msg_t chSemWaitTimeout(Semaphore *sp, systime_t time); + msg_t chSemWaitTimeoutS(Semaphore *sp, systime_t time); + void chSemSignal(Semaphore *sp); + void chSemSignalI(Semaphore *sp); + void chSemAddCounterI(Semaphore *sp, cnt_t n); +#if CH_USE_SEMSW + msg_t chSemSignalWait(Semaphore *sps, Semaphore *spw); +#endif +#ifdef __cplusplus +} +#endif + +/** + * @brief Data part of a static semaphore initializer. + * @details This macro should be used when statically initializing a semaphore + * that is part of a bigger structure. + * + * @param[in] name the name of the semaphore variable + * @param[in] n the counter initial value, this value must be + * non-negative + */ +#define _SEMAPHORE_DATA(name, n) {_THREADSQUEUE_DATA(name.s_queue), n} + +/** + * @brief Static semaphore initializer. + * @details Statically initialized semaphores require no explicit + * initialization using @p chSemInit(). + * + * @param[in] name the name of the semaphore variable + * @param[in] n the counter initial value, this value must be + * non-negative + */ +#define SEMAPHORE_DECL(name, n) Semaphore name = _SEMAPHORE_DATA(name, n) + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Decreases the semaphore counter. + * @details This macro can be used when the counter is known to be positive. + * + * @iclass + */ +#define chSemFastWaitI(sp) ((sp)->s_cnt--) + +/** + * @brief Increases the semaphore counter. + * @details This macro can be used when the counter is known to be not + * negative. + * + * @iclass + */ +#define chSemFastSignalI(sp) ((sp)->s_cnt++) + +/** + * @brief Returns the semaphore counter current value. + * + * @iclass + */ +#define chSemGetCounterI(sp) ((sp)->s_cnt) +/** @} */ + +#endif /* CH_USE_SEMAPHORES */ + +#endif /* _CHSEM_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chstreams.h b/Project/os/kernel/include/chstreams.h new file mode 100644 index 0000000..4470a64 --- /dev/null +++ b/Project/os/kernel/include/chstreams.h @@ -0,0 +1,121 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chstreams.h + * @brief Data streams. + * @details This header defines abstract interfaces useful to access generic + * data streams in a standardized way. + * + * @addtogroup data_streams + * @details This module define an abstract interface for generic data streams. + * Note that no code is present, streams are just abstract interfaces + * like structures, you should look at the systems as to a set of + * abstract C++ classes (even if written in C). This system has the + * advantage to make the access to streams independent from the + * implementation logic.
+ * The stream interface can be used as base class for high level + * object types such as files, sockets, serial ports, pipes etc. + * @{ + */ + +#ifndef _CHSTREAMS_H_ +#define _CHSTREAMS_H_ + +/** + * @brief BaseSequentialStream specific methods. + */ +#define _base_sequential_stream_methods \ + /* Stream write buffer method.*/ \ + size_t (*write)(void *instance, const uint8_t *bp, size_t n); \ + /* Stream read buffer method.*/ \ + size_t (*read)(void *instance, uint8_t *bp, size_t n); + +/** + * @brief @p BaseSequentialStream specific data. + * @note It is empty because @p BaseSequentialStream is only an interface + * without implementation. + */ +#define _base_sequential_stream_data + +/** + * @brief @p BaseSequentialStream virtual methods table. + */ +struct BaseSequentialStreamVMT { + _base_sequential_stream_methods +}; + +/** + * @brief Base stream class. + * @details This class represents a generic blocking unbuffered sequential + * data stream. + */ +typedef struct { + /** @brief Virtual Methods Table.*/ + const struct BaseSequentialStreamVMT *vmt; + _base_sequential_stream_data +} BaseSequentialStream; + +/** + * @name Macro Functions (BaseSequentialStream) + * @{ + */ +/** + * @brief Sequential Stream write. + * @details The function writes data from a buffer to a stream. + * + * @param[in] ip pointer to a @p BaseSequentialStream or derived class + * @param[in] bp pointer to the data buffer + * @param[in] n the maximum amount of data to be transferred + * @return The number of bytes transferred. The return value can + * be less than the specified number of bytes if the + * stream reaches a physical end of file and cannot be + * extended. + * + * @api + */ +#define chSequentialStreamWrite(ip, bp, n) ((ip)->vmt->write(ip, bp, n)) + +/** + * @brief Sequential Stream read. + * @details The function reads data from a stream into a buffer. + * + * @param[in] ip pointer to a @p BaseSequentialStream or derived class + * @param[out] bp pointer to the data buffer + * @param[in] n the maximum amount of data to be transferred + * @return The number of bytes transferred. The return value can + * be less than the specified number of bytes if the + * stream reaches the end of the available data. + * + * @api + */ +#define chSequentialStreamRead(ip, bp, n) ((ip)->vmt->read(ip, bp, n)) +/** @} */ + +#endif /* _CHSTREAMS_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chsys.h b/Project/os/kernel/include/chsys.h new file mode 100644 index 0000000..ac3fcb6 --- /dev/null +++ b/Project/os/kernel/include/chsys.h @@ -0,0 +1,254 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chsys.h + * @brief System related macros and structures. + * + * @addtogroup system + * @{ + */ + +#ifndef _CHSYS_H_ +#define _CHSYS_H_ + +/** + * @name Macro Functions + * @{ + */ +#if !CH_NO_IDLE_THREAD || defined(__DOXYGEN__) +/** + * @brief Returns a pointer to the idle thread. + * @pre In order to use this function the option @p CH_NO_IDLE_THREAD + * must be disabled. + * @note The reference counter of the idle thread is not incremented but + * it is not strictly required being the idle thread a static + * object. + * + * @return Pointer to the idle thread. + * + * @api + */ +#define chSysGetIdleThread() ((Thread *)_idle_thread_wa) +#endif + +/** + * @brief Halts the system. + * @details This function is invoked by the operating system when an + * unrecoverable error is detected, for example because a programming + * error in the application code that triggers an assertion while + * in debug mode. + * @note Can be invoked from any system state. + * + * @special + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define chSysHalt() port_halt() +#else +#define chSysHalt() { \ + SYSTEM_HALT_HOOK(); \ + port_halt(); \ +} +#endif + +/** + * @brief Performs a context switch. + * @note Not a user function, it is meant to be invoked by the scheduler + * itself or from within the port layer. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + * + * @special + */ +#define chSysSwitch(ntp, otp) { \ + dbg_trace(otp); \ + THREAD_CONTEXT_SWITCH_HOOK(ntp, otp); \ + port_switch(ntp, otp); \ +} + +/** + * @brief Raises the system interrupt priority mask to the maximum level. + * @details All the maskable interrupt sources are disabled regardless their + * hardware priority. + * @note Do not invoke this API from within a kernel lock. + * + * @special + */ +#define chSysDisable() { \ + port_disable(); \ + dbg_check_disable(); \ +} + +/** + * @brief Raises the system interrupt priority mask to system level. + * @details The interrupt sources that should not be able to preempt the kernel + * are disabled, interrupt sources with higher priority are still + * enabled. + * @note Do not invoke this API from within a kernel lock. + * @note This API is no replacement for @p chSysLock(), the @p chSysLock() + * could do more than just disable the interrupts. + * + * @special + */ +#define chSysSuspend() { \ + port_suspend(); \ + dbg_check_suspend(); \ +} + +/** + * @brief Lowers the system interrupt priority mask to user level. + * @details All the interrupt sources are enabled. + * @note Do not invoke this API from within a kernel lock. + * @note This API is no replacement for @p chSysUnlock(), the + * @p chSysUnlock() could do more than just enable the interrupts. + * + * @special + */ +#define chSysEnable() { \ + dbg_check_enable(); \ + port_enable(); \ +} + +/** + * @brief Enters the kernel lock mode. + * + * @special + */ +#define chSysLock() { \ + port_lock(); \ + dbg_check_lock(); \ +} + +/** + * @brief Leaves the kernel lock mode. + * + * @special + */ +#define chSysUnlock() { \ + dbg_check_unlock(); \ + port_unlock(); \ +} + +/** + * @brief Enters the kernel lock mode from within an interrupt handler. + * @note This API may do nothing on some architectures, it is required + * because on ports that support preemptable interrupt handlers + * it is required to raise the interrupt mask to the same level of + * the system mutual exclusion zone.
+ * It is good practice to invoke this API before invoking any I-class + * syscall from an interrupt handler. + * @note This API must be invoked exclusively from interrupt handlers. + * + * @special + */ +#define chSysLockFromIsr() { \ + port_lock_from_isr(); \ + dbg_check_lock_from_isr(); \ +} + +/** + * @brief Leaves the kernel lock mode from within an interrupt handler. + * + * @note This API may do nothing on some architectures, it is required + * because on ports that support preemptable interrupt handlers + * it is required to raise the interrupt mask to the same level of + * the system mutual exclusion zone.
+ * It is good practice to invoke this API after invoking any I-class + * syscall from an interrupt handler. + * @note This API must be invoked exclusively from interrupt handlers. + * + * @special + */ +#define chSysUnlockFromIsr() { \ + dbg_check_unlock_from_isr(); \ + port_unlock_from_isr(); \ +} +/** @} */ + +/** + * @name ISRs abstraction macros + */ +/** + * @brief IRQ handler enter code. + * @note Usually IRQ handlers functions are also declared naked. + * @note On some architectures this macro can be empty. + * + * @special + */ +#define CH_IRQ_PROLOGUE() \ + PORT_IRQ_PROLOGUE(); \ + dbg_check_enter_isr(); + +/** + * @brief IRQ handler exit code. + * @note Usually IRQ handlers function are also declared naked. + * @note This macro usually performs the final reschedule by using + * @p chSchIsPreemptionRequired() and @p chSchDoReschedule(). + * + * @special + */ +#define CH_IRQ_EPILOGUE() \ + dbg_check_leave_isr(); \ + PORT_IRQ_EPILOGUE(); + +/** + * @brief Standard normal IRQ handler declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + * + * @special + */ +#define CH_IRQ_HANDLER(id) PORT_IRQ_HANDLER(id) +/** @} */ + +/** + * @name Fast ISRs abstraction macros + */ +/** + * @brief Standard fast IRQ handler declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + * @note Not all architectures support fast interrupts. + * + * @special + */ +#define CH_FAST_IRQ_HANDLER(id) PORT_FAST_IRQ_HANDLER(id) +/** @} */ + +#ifdef __cplusplus +extern "C" { +#endif + void chSysInit(void); + void chSysTimerHandlerI(void); +#ifdef __cplusplus +} +#endif + +#endif /* _CHSYS_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chthreads.h b/Project/os/kernel/include/chthreads.h new file mode 100644 index 0000000..b49c365 --- /dev/null +++ b/Project/os/kernel/include/chthreads.h @@ -0,0 +1,375 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chthreads.h + * @brief Threads macros and structures. + * + * @addtogroup threads + * @{ + */ + +#ifndef _CHTHREADS_H_ +#define _CHTHREADS_H_ + +/** + * @name Thread states + * @{ + */ +#define THD_STATE_READY 0 /**< @brief Waiting on the ready list. */ +#define THD_STATE_CURRENT 1 /**< @brief Currently running. */ +#define THD_STATE_SUSPENDED 2 /**< @brief Created in suspended state. */ +#define THD_STATE_WTSEM 3 /**< @brief Waiting on a semaphore. */ +#define THD_STATE_WTMTX 4 /**< @brief Waiting on a mutex. */ +#define THD_STATE_WTCOND 5 /**< @brief Waiting on a condition + variable. */ +#define THD_STATE_SLEEPING 6 /**< @brief Waiting in @p chThdSleep() + or @p chThdSleepUntil(). */ +#define THD_STATE_WTEXIT 7 /**< @brief Waiting in @p chThdWait(). */ +#define THD_STATE_WTOREVT 8 /**< @brief Waiting for an event. */ +#define THD_STATE_WTANDEVT 9 /**< @brief Waiting for several events. */ +#define THD_STATE_SNDMSGQ 10 /**< @brief Sending a message, in queue.*/ +#define THD_STATE_SNDMSG 11 /**< @brief Sent a message, waiting + answer. */ +#define THD_STATE_WTMSG 12 /**< @brief Waiting for a message. */ +#define THD_STATE_WTQUEUE 13 /**< @brief Waiting on an I/O queue. */ +#define THD_STATE_FINAL 14 /**< @brief Thread terminated. */ + +/** + * @brief Thread states as array of strings. + * @details Each element in an array initialized with this macro can be + * indexed using the numeric thread state values. + */ +#define THD_STATE_NAMES \ + "READY", "CURRENT", "SUSPENDED", "WTSEM", "WTMTX", "WTCOND", "SLEEPING", \ + "WTEXIT", "WTOREVT", "WTANDEVT", "SNDMSGQ", "SNDMSG", "WTMSG", "WTQUEUE", \ + "FINAL" +/** @} */ + +/** + * @name Thread flags and attributes + * @{ + */ +#define THD_MEM_MODE_MASK 3 /**< @brief Thread memory mode mask. */ +#define THD_MEM_MODE_STATIC 0 /**< @brief Static thread. */ +#define THD_MEM_MODE_HEAP 1 /**< @brief Thread allocated from a + Memory Heap. */ +#define THD_MEM_MODE_MEMPOOL 2 /**< @brief Thread allocated from a + Memory Pool. */ +#define THD_TERMINATE 4 /**< @brief Termination requested flag. */ +/** @} */ + +/** + * @extends ThreadsQueue + * + * @brief Structure representing a thread. + * @note Not all the listed fields are always needed, by switching off some + * not needed ChibiOS/RT subsystems it is possible to save RAM space + * by shrinking the @p Thread structure. + */ +struct Thread { + Thread *p_next; /**< @brief Next in the list/queue. */ + /* End of the fields shared with the ThreadsList structure. */ + Thread *p_prev; /**< @brief Previous in the queue. */ + /* End of the fields shared with the ThreadsQueue structure. */ + tprio_t p_prio; /**< @brief Thread priority. */ + struct context p_ctx; /**< @brief Processor context. */ +#if CH_USE_REGISTRY || defined(__DOXYGEN__) + Thread *p_newer; /**< @brief Newer registry element. */ + Thread *p_older; /**< @brief Older registry element. */ +#endif + /* End of the fields shared with the ReadyList structure. */ +#if CH_USE_REGISTRY || defined(__DOXYGEN__) + /** + * @brief Thread name or @p NULL. + */ + const char *p_name; +#endif +#if CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) + /** + * @brief Thread stack boundary. + */ + stkalign_t *p_stklimit; +#endif + /** + * @brief Current thread state. + */ + tstate_t p_state; + /** + * @brief Various thread flags. + */ + tmode_t p_flags; +#if CH_USE_DYNAMIC || defined(__DOXYGEN__) + /** + * @brief References to this thread. + */ + trefs_t p_refs; +#endif +#if CH_DBG_THREADS_PROFILING || defined(__DOXYGEN__) + /** + * @brief Thread consumed time in ticks. + * @note This field can overflow. + */ + volatile systime_t p_time; +#endif + /** + * @brief State-specific fields. + * @note All the fields declared in this union are only valid in the + * specified state or condition and are thus volatile. + */ + union { + /** + * @brief Thread wakeup code. + * @note This field contains the low level message sent to the thread + * by the waking thread or interrupt handler. The value is valid + * after exiting the @p chSchWakeupS() function. + */ + msg_t rdymsg; + /** + * @brief Thread exit code. + * @note The thread termination code is stored in this field in order + * to be retrieved by the thread performing a @p chThdWait() on + * this thread. + */ + msg_t exitcode; + /** + * @brief Pointer to a generic "wait" object. + * @note This field is used to get a generic pointer to a synchronization + * object and is valid when the thread is in one of the wait + * states. + */ + void *wtobjp; +#if CH_USE_EVENTS || defined(__DOXYGEN__) + /** + * @brief Enabled events mask. + * @note This field is only valid while the thread is in the + * @p THD_STATE_WTOREVT or @p THD_STATE_WTANDEVT states. + */ + eventmask_t ewmask; +#endif + } p_u; +#if CH_USE_WAITEXIT || defined(__DOXYGEN__) + /** + * @brief Termination waiting list. + */ + ThreadsList p_waiting; +#endif +#if CH_USE_MESSAGES || defined(__DOXYGEN__) + /** + * @brief Messages queue. + */ + ThreadsQueue p_msgqueue; + /** + * @brief Thread message. + */ + msg_t p_msg; +#endif +#if CH_USE_EVENTS || defined(__DOXYGEN__) + /** + * @brief Pending events mask. + */ + eventmask_t p_epending; +#endif +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief List of the mutexes owned by this thread. + * @note The list is terminated by a @p NULL in this field. + */ + Mutex *p_mtxlist; + /** + * @brief Thread's own, non-inherited, priority. + */ + tprio_t p_realprio; +#endif +#if (CH_USE_DYNAMIC && CH_USE_MEMPOOLS) || defined(__DOXYGEN__) + /** + * @brief Memory Pool where the thread workspace is returned. + */ + void *p_mpool; +#endif +#if defined(THREAD_EXT_FIELDS) + /* Extra fields defined in chconf.h.*/ + THREAD_EXT_FIELDS +#endif +}; + +/** + * @brief Thread function. + */ +typedef msg_t (*tfunc_t)(void *); + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Returns a pointer to the current @p Thread. + * + * @api + */ +#define chThdSelf() currp + +/** + * @brief Returns the current thread priority. + * + * @api + */ +#define chThdGetPriority() (currp->p_prio) + +/** + * @brief Returns the number of ticks consumed by the specified thread. + * @note This function is only available when the + * @p CH_DBG_THREADS_PROFILING configuration option is enabled. + * + * @param[in] tp pointer to the thread + * + * @api + */ +#define chThdGetTicks(tp) ((tp)->p_time) + +/** + * @brief Returns the pointer to the @p Thread local storage area, if any. + * + * @api + */ +#define chThdLS() (void *)(currp + 1) + +/** + * @brief Verifies if the specified thread is in the @p THD_STATE_FINAL state. + * + * @param[in] tp pointer to the thread + * @retval TRUE thread terminated. + * @retval FALSE thread not terminated. + * + * @api + */ +#define chThdTerminated(tp) ((tp)->p_state == THD_STATE_FINAL) + +/** + * @brief Verifies if the current thread has a termination request pending. + * + * @retval TRUE termination request pended. + * @retval FALSE termination request not pended. + * + * @api + */ +#define chThdShouldTerminate() (currp->p_flags & THD_TERMINATE) + +/** + * @brief Resumes a thread created with @p chThdCreateI(). + * + * @param[in] tp pointer to the thread + * + * @iclass + */ +#define chThdResumeI(tp) chSchReadyI(tp) + +/** + * @brief Suspends the invoking thread for the specified time. + * + * @param[in] time the delay in system ticks, the special values are + * handled as follow: + * - @a TIME_INFINITE the thread enters an infinite sleep + * state. + * - @a TIME_IMMEDIATE this value is not allowed. + * . + * + * @sclass + */ +#define chThdSleepS(time) chSchGoSleepTimeoutS(THD_STATE_SLEEPING, time) + +/** + * @brief Delays the invoking thread for the specified number of seconds. + * @note The specified time is rounded up to a value allowed by the real + * system clock. + * @note The maximum specified value is implementation dependent. + * + * @param[in] sec time in seconds, must be different from zero + * + * @api + */ +#define chThdSleepSeconds(sec) chThdSleep(S2ST(sec)) + +/** + * @brief Delays the invoking thread for the specified number of + * milliseconds. + * @note The specified time is rounded up to a value allowed by the real + * system clock. + * @note The maximum specified value is implementation dependent. + * + * @param[in] msec time in milliseconds, must be different from zero + * + * @api + */ +#define chThdSleepMilliseconds(msec) chThdSleep(MS2ST(msec)) + +/** + * @brief Delays the invoking thread for the specified number of + * microseconds. + * @note The specified time is rounded up to a value allowed by the real + * system clock. + * @note The maximum specified value is implementation dependent. + * + * @param[in] usec time in microseconds, must be different from zero + * + * @api + */ +#define chThdSleepMicroseconds(usec) chThdSleep(US2ST(usec)) +/** @} */ + +/* + * Threads APIs. + */ +#ifdef __cplusplus +extern "C" { +#endif + Thread *_thread_init(Thread *tp, tprio_t prio); +#if CH_DBG_FILL_THREADS + void _thread_memfill(uint8_t *startp, uint8_t *endp, uint8_t v); +#endif + Thread *chThdCreateI(void *wsp, size_t size, + tprio_t prio, tfunc_t pf, void *arg); + Thread *chThdCreateStatic(void *wsp, size_t size, + tprio_t prio, tfunc_t pf, void *arg); + tprio_t chThdSetPriority(tprio_t newprio); + Thread *chThdResume(Thread *tp); + void chThdTerminate(Thread *tp); + void chThdSleep(systime_t time); + void chThdSleepUntil(systime_t time); + void chThdYield(void); + void chThdExit(msg_t msg); + void chThdExitS(msg_t msg); +#if CH_USE_WAITEXIT + msg_t chThdWait(Thread *tp); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _CHTHREADS_H_ */ + +/** @} */ diff --git a/Project/os/kernel/include/chvt.h b/Project/os/kernel/include/chvt.h new file mode 100644 index 0000000..c127c5a --- /dev/null +++ b/Project/os/kernel/include/chvt.h @@ -0,0 +1,200 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chvt.h + * @brief Time macros and structures. + * + * @addtogroup time + * @{ + */ + +#ifndef _CHVT_H_ +#define _CHVT_H_ + +/** + * @name Time conversion utilities + * @{ + */ +/** + * @brief Seconds to system ticks. + * @details Converts from seconds to system ticks number. + * @note The result is rounded upward to the next tick boundary. + * + * @param[in] sec number of seconds + * @return The number of ticks. + * + * @api + */ +#define S2ST(sec) ((systime_t)((sec) * CH_FREQUENCY)) + +/** + * @brief Milliseconds to system ticks. + * @details Converts from milliseconds to system ticks number. + * @note The result is rounded upward to the next tick boundary. + * + * @param[in] msec number of milliseconds + * @return The number of ticks. + * + * @api + */ +#define MS2ST(msec) ((systime_t)(((((msec) - 1L) * CH_FREQUENCY) / 1000L) + 1L)) + +/** + * @brief Microseconds to system ticks. + * @details Converts from microseconds to system ticks number. + * @note The result is rounded upward to the next tick boundary. + * + * @param[in] usec number of microseconds + * @return The number of ticks. + * + * @api + */ +#define US2ST(usec) ((systime_t)(((((usec) - 1L) * CH_FREQUENCY) / 1000000L) + 1L)) + +/** + * @brief System ticks to Milliseconds. + * @details Converts from system ticks to milliseconds number. + * @note The result is rounded upward to the next ms boundary. + * + * @param[in] ticks The number of ticks. + * @return number of milliseconds + * + * @api + */ +#define ST2MS(ticks) ((uint32_t)(((((ticks) - 1L) * 1000L) / CH_FREQUENCY) + 1L)) + + +/** @} */ + +/** + * @brief Virtual Timer callback function. + */ +typedef void (*vtfunc_t)(void *); + +/** + * @brief Virtual Timer structure type. + */ +typedef struct VirtualTimer VirtualTimer; + +/** + * @extends DeltaList + * + * @brief Virtual Timer descriptor structure. + */ +struct VirtualTimer { + VirtualTimer *vt_next; /**< @brief Next timer in the delta + list. */ + VirtualTimer *vt_prev; /**< @brief Previous timer in the delta + list. */ + systime_t vt_time; /**< @brief Time delta before timeout. */ + vtfunc_t vt_func; /**< @brief Timer callback function + pointer. */ + void *vt_par; /**< @brief Timer callback function + parameter. */ +}; + +/** + * @brief Virtual timers list header. + * @note The delta list is implemented as a double link bidirectional list + * in order to make the unlink time constant, the reset of a virtual + * timer is often used in the code. + */ +typedef struct { + VirtualTimer *vt_next; /**< @brief Next timer in the delta + list. */ + VirtualTimer *vt_prev; /**< @brief Last timer in the delta + list. */ + systime_t vt_time; /**< @brief Must be initialized to -1. */ + volatile systime_t vt_systime; /**< @brief System Time counter. */ +} VTList; + +extern VTList vtlist; + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Virtual timers ticker. + * + * @iclass + */ +#define chVTDoTickI() { \ + vtlist.vt_systime++; \ + if (&vtlist != (VTList *)vtlist.vt_next) { \ + VirtualTimer *vtp; \ + \ + --vtlist.vt_next->vt_time; \ + while (!(vtp = vtlist.vt_next)->vt_time) { \ + vtfunc_t fn = vtp->vt_func; \ + vtp->vt_func = (vtfunc_t)NULL; \ + vtp->vt_next->vt_prev = (void *)&vtlist; \ + (&vtlist)->vt_next = vtp->vt_next; \ + fn(vtp->vt_par); \ + } \ + } \ +} + +/** + * @brief Returns TRUE if the specified timer is armed. + * + * @iclass + */ +#define chVTIsArmedI(vtp) ((vtp)->vt_func != NULL) + +/** + * @brief Current system time. + * @details Returns the number of system ticks since the @p chSysInit() + * invocation. + * @note The counter can reach its maximum and then restart from zero. + * @note This function is designed to work with the @p chThdSleepUntil(). + * + * @return The system time in ticks.r + * + * @api + */ +#define chTimeNow() (vtlist.vt_systime) +/** @} */ + +/* + * Virtual Timers APIs. + */ +#ifdef __cplusplus +extern "C" { +#endif + void _vt_init(void); + void chVTSetI(VirtualTimer *vtp, systime_t time, vtfunc_t vtfunc, void *par); + void chVTResetI(VirtualTimer *vtp); + bool_t chTimeIsWithin(systime_t start, systime_t end); +#ifdef __cplusplus +} +#endif + +#endif /* _CHVT_H_ */ + +/** @} */ diff --git a/Project/os/kernel/kernel.dox b/Project/os/kernel/kernel.dox new file mode 100644 index 0000000..adb2e3e --- /dev/null +++ b/Project/os/kernel/kernel.dox @@ -0,0 +1,185 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup kernel Kernel + * @details The kernel is the portable part of ChibiOS/RT, this section + * documents the various kernel subsystems. + */ + +/** + * @defgroup kernel_info Version Numbers and Identification + * @ingroup kernel + */ + +/** + * @defgroup config Configuration + * @ingroup kernel + */ + +/** + * @defgroup types Types + * @details The system types are defined into the port layer, please refer to + * the core port implementation section. + * @ingroup kernel + */ + +/** + * @defgroup base Base Kernel Services + * @details Base kernel services, the base subsystems are always included in + * the OS builds. + * @ingroup kernel + */ + +/** + * @defgroup system System Management + * @ingroup base + */ + +/** + * @defgroup scheduler Scheduler + * @ingroup base + */ + +/** + * @defgroup threads Threads + * @ingroup base + */ + +/** + * @defgroup time Time and Virtual Timers + * @ingroup base + */ + +/** + * @defgroup synchronization Synchronization + * @details Synchronization services. + * @ingroup kernel + */ + +/** + * @defgroup semaphores Counting Semaphores + * @ingroup synchronization + */ + +/** + * @defgroup binary_semaphores Binary Semaphores + * @ingroup synchronization + */ + +/** + * @defgroup mutexes Mutexes + * @ingroup synchronization + */ + +/** + * @defgroup condvars Condition Variables + * @ingroup synchronization + */ + +/** + * @defgroup events Event Flags + * @ingroup synchronization + */ + +/** + * @defgroup messages Synchronous Messages + * @ingroup synchronization + */ + +/** + * @defgroup mailboxes Mailboxes + * @ingroup synchronization + */ + +/** + * @defgroup memory Memory Management + * @details Memory Management services. + * @ingroup kernel + */ + +/** + * @defgroup memcore Core Memory Manager + * @ingroup memory + */ + +/** + * @defgroup heaps Heaps + * @ingroup memory + */ + +/** + * @defgroup pools Memory Pools + * @ingroup memory + */ + +/** + * @defgroup dynamic_threads Dynamic Threads + * @ingroup memory + */ + + /** + * @defgroup io_support I/O Support + * @details I/O related services. + * @ingroup kernel + */ + +/** + * @defgroup data_streams Abstract Sequential Streams + * @ingroup io_support + */ + +/** + * @defgroup data_files Abstract File Streams + * @ingroup io_support + */ + +/** + * @defgroup io_channels Abstract I/O Channels + * @ingroup io_support + */ + +/** + * @defgroup io_queues I/O Queues + * @ingroup io_support + */ + +/** + * @defgroup registry Registry + * @ingroup kernel + */ + +/** + * @defgroup debug Debug + * @ingroup kernel + */ + +/** + * @defgroup internals Internals + * @ingroup kernel + */ + diff --git a/Project/os/kernel/kernel.mk b/Project/os/kernel/kernel.mk new file mode 100644 index 0000000..3ebf2ed --- /dev/null +++ b/Project/os/kernel/kernel.mk @@ -0,0 +1,23 @@ +# List of all the ChibiOS/RT kernel files, there is no need to remove the files +# from this list, you can disable parts of the kernel by editing chconf.h. +KERNSRC = ${CHIBIOS}/os/kernel/src/chsys.c \ + ${CHIBIOS}/os/kernel/src/chdebug.c \ + ${CHIBIOS}/os/kernel/src/chlists.c \ + ${CHIBIOS}/os/kernel/src/chvt.c \ + ${CHIBIOS}/os/kernel/src/chschd.c \ + ${CHIBIOS}/os/kernel/src/chthreads.c \ + ${CHIBIOS}/os/kernel/src/chdynamic.c \ + ${CHIBIOS}/os/kernel/src/chregistry.c \ + ${CHIBIOS}/os/kernel/src/chsem.c \ + ${CHIBIOS}/os/kernel/src/chmtx.c \ + ${CHIBIOS}/os/kernel/src/chcond.c \ + ${CHIBIOS}/os/kernel/src/chevents.c \ + ${CHIBIOS}/os/kernel/src/chmsg.c \ + ${CHIBIOS}/os/kernel/src/chmboxes.c \ + ${CHIBIOS}/os/kernel/src/chqueues.c \ + ${CHIBIOS}/os/kernel/src/chmemcore.c \ + ${CHIBIOS}/os/kernel/src/chheap.c \ + ${CHIBIOS}/os/kernel/src/chmempools.c + +# Required include directories +KERNINC = ${CHIBIOS}/os/kernel/include diff --git a/Project/os/kernel/src/chcond.c b/Project/os/kernel/src/chcond.c new file mode 100644 index 0000000..fd593f9 --- /dev/null +++ b/Project/os/kernel/src/chcond.c @@ -0,0 +1,292 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ +/* + Concepts and parts of this file have been contributed by Leon Woestenberg. + */ + +/** + * @file chcond.c + * @brief Condition Variables code. + * + * @addtogroup condvars Condition Variables + * @details This module implements the Condition Variables mechanism. Condition + * variables are an extensions to the Mutex subsystem and cannot + * work alone. + *

Operation mode

+ * The condition variable is a synchronization object meant to be + * used inside a zone protected by a @p Mutex. Mutexes and CondVars + * together can implement a Monitor construct. + * @pre In order to use the condition variable APIs the @p CH_USE_CONDVARS + * option must be enabled in @p chconf.h. + * @{ + */ + +#include "ch.h" + +#if (CH_USE_CONDVARS && CH_USE_MUTEXES) || defined(__DOXYGEN__) + +/** + * @brief Initializes s @p CondVar structure. + * + * @param[out] cp pointer to a @p CondVar structure + * + * @init + */ +void chCondInit(CondVar *cp) { + + chDbgCheck(cp != NULL, "chCondInit"); + + queue_init(&cp->c_queue); +} + +/** + * @brief Signals one thread that is waiting on the condition variable. + * + * @param[in] cp pointer to the @p CondVar structure + * + * @api + */ +void chCondSignal(CondVar *cp) { + + chDbgCheck(cp != NULL, "chCondSignal"); + + chSysLock(); + if (notempty(&cp->c_queue)) + chSchWakeupS(fifo_remove(&cp->c_queue), RDY_OK); + chSysUnlock(); +} + +/** + * @brief Signals one thread that is waiting on the condition variable. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note that + * interrupt handlers always reschedule on exit so an explicit + * reschedule must not be performed in ISRs. + * + * @param[in] cp pointer to the @p CondVar structure + * + * @iclass + */ +void chCondSignalI(CondVar *cp) { + + chDbgCheckClassI(); + chDbgCheck(cp != NULL, "chCondSignalI"); + + if (notempty(&cp->c_queue)) + chSchReadyI(fifo_remove(&cp->c_queue))->p_u.rdymsg = RDY_OK; +} + +/** + * @brief Signals all threads that are waiting on the condition variable. + * + * @param[in] cp pointer to the @p CondVar structure + * + * @api + */ +void chCondBroadcast(CondVar *cp) { + + chSysLock(); + chCondBroadcastI(cp); + chSchRescheduleS(); + chSysUnlock(); +} + +/** + * @brief Signals all threads that are waiting on the condition variable. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note that + * interrupt handlers always reschedule on exit so an explicit + * reschedule must not be performed in ISRs. + * + * @param[in] cp pointer to the @p CondVar structure + * + * @iclass + */ +void chCondBroadcastI(CondVar *cp) { + + chDbgCheckClassI(); + chDbgCheck(cp != NULL, "chCondBroadcastI"); + + /* Empties the condition variable queue and inserts all the Threads into the + ready list in FIFO order. The wakeup message is set to @p RDY_RESET in + order to make a chCondBroadcast() detectable from a chCondSignal().*/ + while (cp->c_queue.p_next != (void *)&cp->c_queue) + chSchReadyI(fifo_remove(&cp->c_queue))->p_u.rdymsg = RDY_RESET; +} + +/** + * @brief Waits on the condition variable releasing the mutex lock. + * @details Releases the currently owned mutex, waits on the condition + * variable, and finally acquires the mutex again. All the sequence + * is performed atomically. + * @pre The invoking thread must have at least one owned mutex. + * + * @param[in] cp pointer to the @p CondVar structure + * @return A message specifying how the invoking thread has been + * released from the condition variable. + * @retval RDY_OK if the condvar has been signaled using + * @p chCondSignal(). + * @retval RDY_RESET if the condvar has been signaled using + * @p chCondBroadcast(). + * + * @api + */ +msg_t chCondWait(CondVar *cp) { + msg_t msg; + + chSysLock(); + msg = chCondWaitS(cp); + chSysUnlock(); + return msg; +} + +/** + * @brief Waits on the condition variable releasing the mutex lock. + * @details Releases the currently owned mutex, waits on the condition + * variable, and finally acquires the mutex again. All the sequence + * is performed atomically. + * @pre The invoking thread must have at least one owned mutex. + * + * @param[in] cp pointer to the @p CondVar structure + * @return A message specifying how the invoking thread has been + * released from the condition variable. + * @retval RDY_OK if the condvar has been signaled using + * @p chCondSignal(). + * @retval RDY_RESET if the condvar has been signaled using + * @p chCondBroadcast(). + * + * @sclass + */ +msg_t chCondWaitS(CondVar *cp) { + Thread *ctp = currp; + Mutex *mp; + msg_t msg; + + chDbgCheckClassS(); + chDbgCheck(cp != NULL, "chCondWaitS"); + chDbgAssert(ctp->p_mtxlist != NULL, + "chCondWaitS(), #1", + "not owning a mutex"); + + mp = chMtxUnlockS(); + ctp->p_u.wtobjp = cp; + prio_insert(ctp, &cp->c_queue); + chSchGoSleepS(THD_STATE_WTCOND); + msg = ctp->p_u.rdymsg; + chMtxLockS(mp); + return msg; +} + +#if CH_USE_CONDVARS_TIMEOUT || defined(__DOXYGEN__) +/** + * @brief Waits on the condition variable releasing the mutex lock. + * @details Releases the currently owned mutex, waits on the condition + * variable, and finally acquires the mutex again. All the sequence + * is performed atomically. + * @pre The invoking thread must have at least one owned mutex. + * @pre The configuration option @p CH_USE_CONDVARS_TIMEOUT must be enabled + * in order to use this function. + * @post Exiting the function because a timeout does not re-acquire the + * mutex, the mutex ownership is lost. + * + * @param[in] cp pointer to the @p CondVar structure + * @param[in] time the number of ticks before the operation timeouts, the + * special values are handled as follow: + * - @a TIME_INFINITE no timeout. + * - @a TIME_IMMEDIATE this value is not allowed. + * . + * @return A message specifying how the invoking thread has been + * released from the condition variable. + * @retval RDY_OK if the condvar has been signaled using + * @p chCondSignal(). + * @retval RDY_RESET if the condvar has been signaled using + * @p chCondBroadcast(). + * @retval RDY_TIMEOUT if the condvar has not been signaled within the + * specified timeout. + * + * @api + */ +msg_t chCondWaitTimeout(CondVar *cp, systime_t time) { + msg_t msg; + + chSysLock(); + msg = chCondWaitTimeoutS(cp, time); + chSysUnlock(); + return msg; +} + +/** + * @brief Waits on the condition variable releasing the mutex lock. + * @details Releases the currently owned mutex, waits on the condition + * variable, and finally acquires the mutex again. All the sequence + * is performed atomically. + * @pre The invoking thread must have at least one owned mutex. + * @pre The configuration option @p CH_USE_CONDVARS_TIMEOUT must be enabled + * in order to use this function. + * @post Exiting the function because a timeout does not re-acquire the + * mutex, the mutex ownership is lost. + * + * @param[in] cp pointer to the @p CondVar structure + * @param[in] time the number of ticks before the operation timeouts, the + * special values are handled as follow: + * - @a TIME_INFINITE no timeout. + * - @a TIME_IMMEDIATE this value is not allowed. + * . + * @return A message specifying how the invoking thread has been + * released from the condition variable. + * @retval RDY_OK if the condvar has been signaled using + * @p chCondSignal(). + * @retval RDY_RESET if the condvar has been signaled using + * @p chCondBroadcast(). + * @retval RDY_TIMEOUT if the condvar has not been signaled within the + * specified timeout. + * + * @sclass + */ +msg_t chCondWaitTimeoutS(CondVar *cp, systime_t time) { + Mutex *mp; + msg_t msg; + + chDbgCheckClassS(); + chDbgCheck((cp != NULL) && (time != TIME_IMMEDIATE), "chCondWaitTimeoutS"); + chDbgAssert(currp->p_mtxlist != NULL, + "chCondWaitTimeoutS(), #1", + "not owning a mutex"); + + mp = chMtxUnlockS(); + currp->p_u.wtobjp = cp; + prio_insert(currp, &cp->c_queue); + msg = chSchGoSleepTimeoutS(THD_STATE_WTCOND, time); + if (msg != RDY_TIMEOUT) + chMtxLockS(mp); + return msg; +} +#endif /* CH_USE_CONDVARS_TIMEOUT */ + +#endif /* CH_USE_CONDVARS && CH_USE_MUTEXES */ + +/** @} */ diff --git a/Project/os/kernel/src/chdebug.c b/Project/os/kernel/src/chdebug.c new file mode 100644 index 0000000..6dcc748 --- /dev/null +++ b/Project/os/kernel/src/chdebug.c @@ -0,0 +1,280 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chdebug.c + * @brief ChibiOS/RT Debug code. + * + * @addtogroup debug + * @details Debug APIs and services: + * - Runtime system state and call protocol check. The following + * panic messages can be generated: + * - SV#1, misplaced @p chSysDisable(). + * - SV#2, misplaced @p chSysSuspend() + * - SV#3, misplaced @p chSysEnable(). + * - SV#4, misplaced @p chSysLock(). + * - SV#5, misplaced @p chSysUnlock(). + * - SV#6, misplaced @p chSysLockFromIsr(). + * - SV#7, misplaced @p chSysUnlockFromIsr(). + * - SV#8, misplaced @p CH_IRQ_PROLOGUE(). + * - SV#9, misplaced @p CH_IRQ_EPILOGUE(). + * - SV#10, misplaced I-class function. + * - SV#11, misplaced S-class function. + * . + * - Trace buffer. + * - Parameters check. + * - Kernel assertions. + * - Kernel panics. + * . + * @note Stack checks are not implemented in this module but in the port + * layer in an architecture-dependent way. + * @{ + */ + +#include "libwismart.h" +#include "ch.h" + +/*===========================================================================*/ +/* System state checker related code and variables. */ +/*===========================================================================*/ + +#if CH_DBG_SYSTEM_STATE_CHECK || defined(__DOXYGEN__) + +/** + * @brief ISR nesting level. + */ +cnt_t dbg_isr_cnt=0; + +/** + * @brief Lock nesting level. + */ +cnt_t dbg_lock_cnt=0; + +/** + * @brief Guard code for @p chSysDisable(). + * + * @notapi + */ +void dbg_check_disable(void) { + + if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0)) + chDbgPanic("SV#1"); +} + +/** + * @brief Guard code for @p chSysSuspend(). + * + * @notapi + */ +void dbg_check_suspend(void) { + + if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0)) + chDbgPanic("SV#2"); +} + +/** + * @brief Guard code for @p chSysEnable(). + * + * @notapi + */ +void dbg_check_enable(void) { + + if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0)) + chDbgPanic("SV#3"); +} + +/** + * @brief Guard code for @p chSysLock(). + * + * @notapi + */ +void dbg_check_lock(void) { + + if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0)) + chDbgPanic("SV#4"); + dbg_lock_cnt = 1; +} + +/** + * @brief Guard code for @p chSysUnlock(). + * + * @notapi + */ +void dbg_check_unlock(void) { + + if ((dbg_isr_cnt != 0) || (dbg_lock_cnt <= 0)) + chDbgPanic("SV#5"); + dbg_lock_cnt = 0; +} + +/** + * @brief Guard code for @p chSysLockFromIsr(). + * + * @notapi + */ +void dbg_check_lock_from_isr(void) { + + if ((dbg_isr_cnt <= 0) || (dbg_lock_cnt != 0)) + chDbgPanic("SV#6"); + dbg_lock_cnt = 1; +} + +/** + * @brief Guard code for @p chSysUnlockFromIsr(). + * + * @notapi + */ +void dbg_check_unlock_from_isr(void) { + + if ((dbg_isr_cnt <= 0) || (dbg_lock_cnt <= 0)) + chDbgPanic("SV#7"); + dbg_lock_cnt = 0; +} + +/** + * @brief Guard code for @p CH_IRQ_PROLOGUE(). + * + * @notapi + */ +void dbg_check_enter_isr(void) { + + port_lock_from_isr(); + if ((dbg_isr_cnt < 0) || (dbg_lock_cnt != 0)) + chDbgPanic("SV#8"); + dbg_isr_cnt++; + port_unlock_from_isr(); +} + +/** + * @brief Guard code for @p CH_IRQ_EPILOGUE(). + * + * @notapi + */ +void dbg_check_leave_isr(void) { + + port_lock_from_isr(); + if ((dbg_isr_cnt <= 0) || (dbg_lock_cnt != 0)) + chDbgPanic("SV#9"); + dbg_isr_cnt--; + port_unlock_from_isr(); +} + +/** + * @brief I-class functions context check. + * @details Verifies that the system is in an appropriate state for invoking + * an I-class API function. A panic is generated if the state is + * not compatible. + * + * @api + */ +void chDbgCheckClassI(void) { + + if ((dbg_isr_cnt < 0) || (dbg_lock_cnt <= 0)) + chDbgPanic("SV#10"); +} + +/** + * @brief S-class functions context check. + * @details Verifies that the system is in an appropriate state for invoking + * an S-class API function. A panic is generated if the state is + * not compatible. + * + * @api + */ +void chDbgCheckClassS(void) { + + if ((dbg_isr_cnt != 0) || (dbg_lock_cnt <= 0)) + chDbgPanic("SV#11"); +} + +#endif /* CH_DBG_SYSTEM_STATE_CHECK */ + +/*===========================================================================*/ +/* Trace related code and variables. */ +/*===========================================================================*/ + +#if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__) +/** + * @brief Public trace buffer. + */ +ch_trace_buffer_t dbg_trace_buffer; + +/** + * @brief Trace circular buffer subsystem initialization. + * @note Internal use only. + */ +void _trace_init(void) { + + dbg_trace_buffer.tb_size = CH_TRACE_BUFFER_SIZE; + dbg_trace_buffer.tb_ptr = &dbg_trace_buffer.tb_buffer[0]; +} + +/** + * @brief Inserts in the circular debug trace buffer a context switch record. + * + * @param[in] otp the thread being switched out + * + * @notapi + */ +void dbg_trace(Thread *otp) { + + dbg_trace_buffer.tb_ptr->se_time = chTimeNow(); + dbg_trace_buffer.tb_ptr->se_tp = currp; + dbg_trace_buffer.tb_ptr->se_wtobjp = otp->p_u.wtobjp; + dbg_trace_buffer.tb_ptr->se_state = (uint8_t)otp->p_state; + if (++dbg_trace_buffer.tb_ptr >= + &dbg_trace_buffer.tb_buffer[CH_TRACE_BUFFER_SIZE]) + dbg_trace_buffer.tb_ptr = &dbg_trace_buffer.tb_buffer[0]; +} +#endif /* CH_DBG_ENABLE_TRACE */ + +/*===========================================================================*/ +/* Panic related code and variables. */ +/*===========================================================================*/ + +#if CH_DBG_ENABLED || defined(__DOXYGEN__) +/** + * @brief Pointer to the panic message. + * @details This pointer is meant to be accessed through the debugger, it is + * written once and then the system is halted. + */ +char *dbg_panic_msg; + +/** + * @brief Prints a panic message on the console and then halts the system. + * + * @param[in] msg the pointer to the panic message string + */ +void chDbgPanic(char *msg) { + + dbg_panic_msg = msg; + printI(">> %s\r\n",msg); + chSysHalt(); +} +#endif /* CH_DBG_ENABLED */ + +/** @} */ diff --git a/Project/os/kernel/src/chdynamic.c b/Project/os/kernel/src/chdynamic.c new file mode 100644 index 0000000..083c144 --- /dev/null +++ b/Project/os/kernel/src/chdynamic.c @@ -0,0 +1,211 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chdynamic.c + * @brief Dynamic threads code. + * + * @addtogroup dynamic_threads + * @details Dynamic threads related APIs and services. + * @{ + */ + +#include "ch.h" + +#if CH_USE_DYNAMIC || defined(__DOXYGEN__) + +/** + * @brief Adds a reference to a thread object. + * @pre The configuration option @p CH_USE_DYNAMIC must be enabled in order + * to use this function. + * + * @param[in] tp pointer to the thread + * @return The same thread pointer passed as parameter + * representing the new reference. + * + * @api + */ +Thread *chThdAddRef(Thread *tp) { + + chSysLock(); + chDbgAssert(tp->p_refs < 255, "chThdAddRef(), #1", "too many references"); + tp->p_refs++; + chSysUnlock(); + return tp; +} + +/** + * @brief Releases a reference to a thread object. + * @details If the references counter reaches zero and the thread + * is in the @p THD_STATE_FINAL state then the thread's memory is + * returned to the proper allocator. + * @pre The configuration option @p CH_USE_DYNAMIC must be enabled in order + * to use this function. + * @note Static threads are not affected. + * + * @param[in] tp pointer to the thread + * + * @api + */ +void chThdRelease(Thread *tp) { + trefs_t refs; + + chSysLock(); + chDbgAssert(tp->p_refs > 0, "chThdRelease(), #1", "not referenced"); + refs = --tp->p_refs; + chSysUnlock(); + + /* If the references counter reaches zero and the thread is in its + terminated state then the memory can be returned to the proper + allocator. Of course static threads are not affected.*/ + if ((refs == 0) && (tp->p_state == THD_STATE_FINAL)) { + switch (tp->p_flags & THD_MEM_MODE_MASK) { +#if CH_USE_HEAP + case THD_MEM_MODE_HEAP: +#if CH_USE_REGISTRY + REG_REMOVE(tp); +#endif + chHeapFree(tp); + break; +#endif +#if CH_USE_MEMPOOLS + case THD_MEM_MODE_MEMPOOL: +#if CH_USE_REGISTRY + REG_REMOVE(tp); +#endif + chPoolFree(tp->p_mpool, tp); + break; +#endif + } + } +} + +#if CH_USE_HEAP || defined(__DOXYGEN__) +/** + * @brief Creates a new thread allocating the memory from the heap. + * @pre The configuration options @p CH_USE_DYNAMIC and @p CH_USE_HEAP + * must be enabled in order to use this function. + * @note A thread can terminate by calling @p chThdExit() or by simply + * returning from its main function. + * @note The memory allocated for the thread is not released when the thread + * terminates but when a @p chThdWait() is performed. + * + * @param[in] heapp heap from which allocate the memory or @p NULL for the + * default heap + * @param[in] size size of the working area to be allocated + * @param[in] prio the priority level for the new thread + * @param[in] pf the thread function + * @param[in] arg an argument passed to the thread function. It can be + * @p NULL. + * @return The pointer to the @p Thread structure allocated for + * the thread into the working space area. + * @retval NULL if the memory cannot be allocated. + * + * @api + */ +Thread *chThdCreateFromHeap(MemoryHeap *heapp, size_t size, + tprio_t prio, tfunc_t pf, void *arg) { + void *wsp; + Thread *tp; + + wsp = chHeapAlloc(heapp, size); + if (wsp == NULL) + return NULL; + +#if CH_DBG_FILL_THREADS + _thread_memfill((uint8_t *)wsp, + (uint8_t *)wsp + sizeof(Thread), + CH_THREAD_FILL_VALUE); + _thread_memfill((uint8_t *)wsp + sizeof(Thread), + (uint8_t *)wsp + size, + CH_STACK_FILL_VALUE); +#endif + + chSysLock(); + tp = chThdCreateI(wsp, size, prio, pf, arg); + tp->p_flags = THD_MEM_MODE_HEAP; + chSchWakeupS(tp, RDY_OK); + chSysUnlock(); + return tp; +} +#endif /* CH_USE_HEAP */ + +#if CH_USE_MEMPOOLS || defined(__DOXYGEN__) +/** + * @brief Creates a new thread allocating the memory from the specified + * memory pool. + * @pre The configuration options @p CH_USE_DYNAMIC and @p CH_USE_MEMPOOLS + * must be enabled in order to use this function. + * @note A thread can terminate by calling @p chThdExit() or by simply + * returning from its main function. + * @note The memory allocated for the thread is not released when the thread + * terminates but when a @p chThdWait() is performed. + * + * @param[in] mp pointer to the memory pool object + * @param[in] prio the priority level for the new thread + * @param[in] pf the thread function + * @param[in] arg an argument passed to the thread function. It can be + * @p NULL. + * @return The pointer to the @p Thread structure allocated for + * the thread into the working space area. + * @retval NULL if the memory pool is empty. + * + * @api + */ +Thread *chThdCreateFromMemoryPool(MemoryPool *mp, tprio_t prio, + tfunc_t pf, void *arg) { + void *wsp; + Thread *tp; + + chDbgCheck(mp != NULL, "chThdCreateFromMemoryPool"); + + wsp = chPoolAlloc(mp); + if (wsp == NULL) + return NULL; + +#if CH_DBG_FILL_THREADS + _thread_memfill((uint8_t *)wsp, + (uint8_t *)wsp + sizeof(Thread), + CH_THREAD_FILL_VALUE); + _thread_memfill((uint8_t *)wsp + sizeof(Thread), + (uint8_t *)wsp + mp->mp_object_size, + CH_STACK_FILL_VALUE); +#endif + + chSysLock(); + tp = chThdCreateI(wsp, mp->mp_object_size, prio, pf, arg); + tp->p_flags = THD_MEM_MODE_MEMPOOL; + tp->p_mpool = mp; + chSchWakeupS(tp, RDY_OK); + chSysUnlock(); + return tp; +} +#endif /* CH_USE_MEMPOOLS */ + +#endif /* CH_USE_DYNAMIC */ + +/** @} */ diff --git a/Project/os/kernel/src/chevents.c b/Project/os/kernel/src/chevents.c new file mode 100644 index 0000000..fe00e7e --- /dev/null +++ b/Project/os/kernel/src/chevents.c @@ -0,0 +1,507 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chevents.c + * @brief Events code. + * + * @addtogroup events + * @details Event Flags, Event Sources and Event Listeners. + *

Operation mode

+ * Each thread has a mask of pending event flags inside its @p Thread + * structure. + * Operations defined for event flags: + * - Wait, the invoking thread goes to sleep until a certain + * AND/OR combination of event flags becomes pending. + * - Clear, a mask of event flags is cleared from the pending + * events mask, the cleared event flags mask is returned (only the + * flags that were actually pending and then cleared). + * - Signal, an event mask is directly ORed to the mask of the + * signaled thread. + * - Broadcast, each thread registered on an Event Source is + * signaled with the event flags specified in its Event Listener. + * - Dispatch, an events mask is scanned and for each bit set + * to one an associated handler function is invoked. Bit masks are + * scanned from bit zero upward. + * . + * An Event Source is a special object that can be "broadcasted" by + * a thread or an interrupt service routine. Broadcasting an Event + * Source has the effect that all the threads registered on the + * Event Source will be signaled with an events mask.
+ * An unlimited number of Event Sources can exists in a system and + * each thread can be listening on an unlimited number of + * them. + * @pre In order to use the Events APIs the @p CH_USE_EVENTS option must be + * enabled in @p chconf.h. + * @post Enabling events requires 1-4 (depending on the architecture) + * extra bytes in the @p Thread structure. + * @{ + */ + +#include "ch.h" + +#if CH_USE_EVENTS || defined(__DOXYGEN__) +/** + * @brief Registers an Event Listener on an Event Source. + * @details Once a thread has registered as listener on an event source it + * will be notified of all events broadcasted there. + * @note Multiple Event Listeners can specify the same bits to be ORed to + * different threads. + * + * @param[in] esp pointer to the @p EventSource structure + * @param[in] elp pointer to the @p EventListener structure + * @param[in] mask the mask of event flags to be ORed to the thread when + * the event source is broadcasted + * + * @api + */ +void chEvtRegisterMask(EventSource *esp, EventListener *elp, eventmask_t mask) { + + chDbgCheck((esp != NULL) && (elp != NULL), "chEvtRegisterMask"); + + chSysLock(); + elp->el_next = esp->es_next; + esp->es_next = elp; + elp->el_listener = currp; + elp->el_mask = mask; + chSysUnlock(); +} + +/** + * @brief Unregisters an Event Listener from its Event Source. + * @note If the event listener is not registered on the specified event + * source then the function does nothing. + * @note For optimal performance it is better to perform the unregister + * operations in inverse order of the register operations (elements + * are found on top of the list). + * + * @param[in] esp pointer to the @p EventSource structure + * @param[in] elp pointer to the @p EventListener structure + * + * @api + */ +void chEvtUnregister(EventSource *esp, EventListener *elp) { + EventListener *p; + + chDbgCheck((esp != NULL) && (elp != NULL), "chEvtUnregister"); + + p = (EventListener *)esp; + chSysLock(); + while (p->el_next != (EventListener *)esp) { + if (p->el_next == elp) { + p->el_next = elp->el_next; + break; + } + p = p->el_next; + } + chSysUnlock(); +} + +/** + * @brief Clears the pending events specified in the mask. + * + * @param[in] mask the events to be cleared + * @return The pending events that were cleared. + * + * @api + */ +eventmask_t chEvtClearFlags(eventmask_t mask) { + eventmask_t m; + + chSysLock(); + + m = currp->p_epending & mask; + currp->p_epending &= ~mask; + + chSysUnlock(); + return m; +} + +/** + * @brief Adds (OR) a set of event flags on the current thread, this is + * @b much faster than using @p chEvtBroadcast() or @p chEvtSignal(). + * + * @param[in] mask the event flags to be ORed + * @return The current pending events mask. + * + * @api + */ +eventmask_t chEvtAddFlags(eventmask_t mask) { + + chSysLock(); + + mask = (currp->p_epending |= mask); + + chSysUnlock(); + return mask; +} + +/** + * @brief Adds (OR) a set of event flags on the specified @p Thread. + * + * @param[in] tp the thread to be signaled + * @param[in] mask the event flags set to be ORed + * + * @api + */ +void chEvtSignalFlags(Thread *tp, eventmask_t mask) { + + chDbgCheck(tp != NULL, "chEvtSignal"); + + chSysLock(); + chEvtSignalFlagsI(tp, mask); + chSchRescheduleS(); + chSysUnlock(); +} + +/** + * @brief Adds (OR) a set of event flags on the specified @p Thread. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note that + * interrupt handlers always reschedule on exit so an explicit + * reschedule must not be performed in ISRs. + * + * @param[in] tp the thread to be signaled + * @param[in] mask the event flags set to be ORed + * + * @iclass + */ +void chEvtSignalFlagsI(Thread *tp, eventmask_t mask) { + + chDbgCheckClassI(); + chDbgCheck(tp != NULL, "chEvtSignalI"); + + tp->p_epending |= mask; + /* Test on the AND/OR conditions wait states.*/ + if (((tp->p_state == THD_STATE_WTOREVT) && + ((tp->p_epending & tp->p_u.ewmask) != 0)) || + ((tp->p_state == THD_STATE_WTANDEVT) && + ((tp->p_epending & tp->p_u.ewmask) == tp->p_u.ewmask))) + chSchReadyI(tp)->p_u.rdymsg = RDY_OK; +} + +/** + * @brief Signals all the Event Listeners registered on the specified Event + * Source. + * @details This function variants ORs the specified event flags to all the + * threads registered on the @p EventSource in addition to the event + * flags specified by the threads themselves in the + * @p EventListener objects. + * + * @param[in] esp pointer to the @p EventSource structure + * @param[in] mask the event flags set to be ORed + * + * @api + */ +void chEvtBroadcastFlags(EventSource *esp, eventmask_t mask) { + + chSysLock(); + chEvtBroadcastFlagsI(esp, mask); + chSchRescheduleS(); + chSysUnlock(); +} + +/** + * @brief Signals all the Event Listeners registered on the specified Event + * Source. + * @details This function variants ORs the specified event flags to all the + * threads registered on the @p EventSource in addition to the event + * flags specified by the threads themselves in the + * @p EventListener objects. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note that + * interrupt handlers always reschedule on exit so an explicit + * reschedule must not be performed in ISRs. + * + * @param[in] esp pointer to the @p EventSource structure + * @param[in] mask the event flags set to be ORed + * + * @iclass + */ +void chEvtBroadcastFlagsI(EventSource *esp, eventmask_t mask) { + EventListener *elp; + + chDbgCheckClassI(); + chDbgCheck(esp != NULL, "chEvtBroadcastMaskI"); + + elp = esp->es_next; + while (elp != (EventListener *)esp) { + chEvtSignalFlagsI(elp->el_listener, elp->el_mask | mask); + elp = elp->el_next; + } +} + +/** + * @brief Invokes the event handlers associated to an event flags mask. + * + * @param[in] mask mask of the event flags to be dispatched + * @param[in] handlers an array of @p evhandler_t. The array must have size + * equal to the number of bits in eventmask_t. + * + * @api + */ +void chEvtDispatch(const evhandler_t *handlers, eventmask_t mask) { + eventid_t eid; + + chDbgCheck(handlers != NULL, "chEvtDispatch"); + + eid = 0; + while (mask) { + if (mask & EVENT_MASK(eid)) { + chDbgAssert(handlers[eid] != NULL, + "chEvtDispatch(), #1", + "null handler"); + mask &= ~EVENT_MASK(eid); + handlers[eid](eid); + } + eid++; + } +} + +#if CH_OPTIMIZE_SPEED || !CH_USE_EVENTS_TIMEOUT || defined(__DOXYGEN__) +/** + * @brief Waits for exactly one of the specified events. + * @details The function waits for one event among those specified in + * @p mask to become pending then the event is cleared and returned. + * @note One and only one event is served in the function, the one with the + * lowest event id. The function is meant to be invoked into a loop in + * order to serve all the pending events.
+ * This means that Event Listeners with a lower event identifier have + * an higher priority. + * + * @param[in] mask mask of the event flags that the function should wait + * for, @p ALL_EVENTS enables all the events + * @return The mask of the lowest id served and cleared event. + * + * @api + */ +eventmask_t chEvtWaitOne(eventmask_t mask) { + Thread *ctp = currp; + eventmask_t m; + + chSysLock(); + + if ((m = (ctp->p_epending & mask)) == 0) { + ctp->p_u.ewmask = mask; + chSchGoSleepS(THD_STATE_WTOREVT); + m = ctp->p_epending & mask; + } + m &= -m; + ctp->p_epending &= ~m; + + chSysUnlock(); + return m; +} + +/** + * @brief Waits for any of the specified events. + * @details The function waits for any event among those specified in + * @p mask to become pending then the events are cleared and returned. + * + * @param[in] mask mask of the event flags that the function should wait + * for, @p ALL_EVENTS enables all the events + * @return The mask of the served and cleared events. + * + * @api + */ +eventmask_t chEvtWaitAny(eventmask_t mask) { + Thread *ctp = currp; + eventmask_t m; + + chSysLock(); + + if ((m = (ctp->p_epending & mask)) == 0) { + ctp->p_u.ewmask = mask; + chSchGoSleepS(THD_STATE_WTOREVT); + m = ctp->p_epending & mask; + } + ctp->p_epending &= ~m; + + chSysUnlock(); + return m; +} + +/** + * @brief Waits for all the specified events. + * @details The function waits for all the events specified in @p mask to + * become pending then the events are cleared and returned. + * + * @param[in] mask mask of the event flags that the function should wait + * for, @p ALL_EVENTS requires all the events + * @return The mask of the served and cleared events. + * + * @api + */ +eventmask_t chEvtWaitAll(eventmask_t mask) { + Thread *ctp = currp; + + chSysLock(); + + if ((ctp->p_epending & mask) != mask) { + ctp->p_u.ewmask = mask; + chSchGoSleepS(THD_STATE_WTANDEVT); + } + ctp->p_epending &= ~mask; + + chSysUnlock(); + return mask; +} +#endif /* CH_OPTIMIZE_SPEED || !CH_USE_EVENTS_TIMEOUT */ + +#if CH_USE_EVENTS_TIMEOUT || defined(__DOXYGEN__) +/** + * @brief Waits for exactly one of the specified events. + * @details The function waits for one event among those specified in + * @p mask to become pending then the event is cleared and returned. + * @note One and only one event is served in the function, the one with the + * lowest event id. The function is meant to be invoked into a loop in + * order to serve all the pending events.
+ * This means that Event Listeners with a lower event identifier have + * an higher priority. + * + * @param[in] mask mask of the event flags that the function should wait + * for, @p ALL_EVENTS enables all the events + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The mask of the lowest id served and cleared event. + * @retval 0 if the operation has timed out. + * + * @api + */ +eventmask_t chEvtWaitOneTimeout(eventmask_t mask, systime_t time) { + Thread *ctp = currp; + eventmask_t m; + + chSysLock(); + + if ((m = (ctp->p_epending & mask)) == 0) { + if (TIME_IMMEDIATE == time) { + chSysUnlock(); + return (eventmask_t)0; + } + ctp->p_u.ewmask = mask; + if (chSchGoSleepTimeoutS(THD_STATE_WTOREVT, time) < RDY_OK) { + chSysUnlock(); + return (eventmask_t)0; + } + m = ctp->p_epending & mask; + } + m &= -m; + ctp->p_epending &= ~m; + + chSysUnlock(); + return m; +} + +/** + * @brief Waits for any of the specified events. + * @details The function waits for any event among those specified in + * @p mask to become pending then the events are cleared and + * returned. + * + * @param[in] mask mask of the event flags that the function should wait + * for, @p ALL_EVENTS enables all the events + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The mask of the served and cleared events. + * @retval 0 if the operation has timed out. + * + * @api + */ +eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t time) { + Thread *ctp = currp; + eventmask_t m; + + chSysLock(); + + if ((m = (ctp->p_epending & mask)) == 0) { + if (TIME_IMMEDIATE == time) { + chSysUnlock(); + return (eventmask_t)0; + } + ctp->p_u.ewmask = mask; + if (chSchGoSleepTimeoutS(THD_STATE_WTOREVT, time) < RDY_OK) { + chSysUnlock(); + return (eventmask_t)0; + } + m = ctp->p_epending & mask; + } + ctp->p_epending &= ~m; + + chSysUnlock(); + return m; +} + +/** + * @brief Waits for all the specified events. + * @details The function waits for all the events specified in @p mask to + * become pending then the events are cleared and returned. + * + * @param[in] mask mask of the event flags that the function should wait + * for, @p ALL_EVENTS requires all the events + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The mask of the served and cleared events. + * @retval 0 if the operation has timed out. + * + * @api + */ +eventmask_t chEvtWaitAllTimeout(eventmask_t mask, systime_t time) { + Thread *ctp = currp; + + chSysLock(); + + if ((ctp->p_epending & mask) != mask) { + if (TIME_IMMEDIATE == time) { + chSysUnlock(); + return (eventmask_t)0; + } + ctp->p_u.ewmask = mask; + if (chSchGoSleepTimeoutS(THD_STATE_WTANDEVT, time) < RDY_OK) { + chSysUnlock(); + return (eventmask_t)0; + } + } + ctp->p_epending &= ~mask; + + chSysUnlock(); + return mask; +} +#endif /* CH_USE_EVENTS_TIMEOUT */ + +#endif /* CH_USE_EVENTS */ + +/** @} */ diff --git a/Project/os/kernel/src/chheap.c b/Project/os/kernel/src/chheap.c new file mode 100644 index 0000000..8256ec5 --- /dev/null +++ b/Project/os/kernel/src/chheap.c @@ -0,0 +1,360 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chheap.c + * @brief Heaps code. + * + * @addtogroup heaps + * @details Heap Allocator related APIs. + *

Operation mode

+ * The heap allocator implements a first-fit strategy and its APIs + * are functionally equivalent to the usual @p malloc() and @p free() + * library functions. The main difference is that the OS heap APIs + * are guaranteed to be thread safe.
+ * By enabling the @p CH_USE_MALLOC_HEAP option the heap manager + * will use the runtime-provided @p malloc() and @p free() as + * back end for the heap APIs instead of the system provided + * allocator. + * @pre In order to use the heap APIs the @p CH_USE_HEAP option must + * be enabled in @p chconf.h. + * @{ + */ + +#include "ch.h" + +#if CH_USE_HEAP || defined(__DOXYGEN__) + +#if !CH_USE_MALLOC_HEAP || defined(__DOXYGEN__) + +/* + * Defaults on the best synchronization mechanism available. + */ +#if CH_USE_MUTEXES || defined(__DOXYGEN__) +#define H_LOCK(h) chMtxLock(&(h)->h_mtx) +#define H_UNLOCK(h) chMtxUnlock() +#else +#define H_LOCK(h) chSemWait(&(h)->h_sem) +#define H_UNLOCK(h) chSemSignal(&(h)->h_sem) +#endif + +/** + * @brief Default heap descriptor. + */ +static MemoryHeap default_heap; + +/** + * @brief Initializes the default heap. + * + * @notapi + */ +void _heap_init(void) { + default_heap.h_provider = chCoreAlloc; + default_heap.h_free.h.u.next = (union heap_header *)NULL; + default_heap.h_free.h.size = 0; +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + chMtxInit(&default_heap.h_mtx); +#else + chSemInit(&default_heap.h_sem, 1); +#endif +} + +/** + * @brief Initializes a memory heap from a static memory area. + * @pre Both the heap buffer base and the heap size must be aligned to + * the @p stkalign_t type size. + * @pre In order to use this function the option @p CH_USE_MALLOC_HEAP + * must be disabled. + * + * @param[out] heapp pointer to the memory heap descriptor to be initialized + * @param[in] buf heap buffer base + * @param[in] size heap size + * + * @init + */ +void chHeapInit(MemoryHeap *heapp, void *buf, size_t size) { + union heap_header *hp; + + chDbgCheck(MEM_IS_ALIGNED(buf) && MEM_IS_ALIGNED(size), "chHeapInit"); + + heapp->h_provider = (memgetfunc_t)NULL; + heapp->h_free.h.u.next = hp = buf; + heapp->h_free.h.size = 0; + hp->h.u.next = NULL; + hp->h.size = size - sizeof(union heap_header); +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + chMtxInit(&heapp->h_mtx); +#else + chSemInit(&heapp->h_sem, 1); +#endif +} + +/** + * @brief Allocates a block of memory from the heap by using the first-fit + * algorithm. + * @details The allocated block is guaranteed to be properly aligned for a + * pointer data type (@p stkalign_t). + * + * @param[in] heapp pointer to a heap descriptor or @p NULL in order to + * access the default heap. + * @param[in] size the size of the block to be allocated. Note that the + * allocated block may be a bit bigger than the requested + * size for alignment and fragmentation reasons. + * @return A pointer to the allocated block. + * @retval NULL if the block cannot be allocated. + * + * @api + */ +void *chHeapAlloc(MemoryHeap *heapp, size_t size) { + union heap_header *qp, *hp, *fp; + + if (heapp == NULL) + heapp = &default_heap; + + size = MEM_ALIGN_NEXT(size); + qp = &heapp->h_free; + H_LOCK(heapp); + + while (qp->h.u.next != NULL) { + hp = qp->h.u.next; + if (hp->h.size >= size) { + if (hp->h.size < size + sizeof(union heap_header)) { + /* Gets the whole block even if it is slightly bigger than the + requested size because the fragment would be too small to be + useful.*/ + qp->h.u.next = hp->h.u.next; + } + else { + /* Block bigger enough, must split it.*/ + fp = (void *)((uint8_t *)(hp) + sizeof(union heap_header) + size); + fp->h.u.next = hp->h.u.next; + fp->h.size = hp->h.size - sizeof(union heap_header) - size; + qp->h.u.next = fp; + hp->h.size = size; + } + hp->h.u.heap = heapp; + + H_UNLOCK(heapp); + return (void *)(hp + 1); + } + qp = hp; + } + + H_UNLOCK(heapp); + + /* More memory is required, tries to get it from the associated provider + else fails.*/ + if (heapp->h_provider) { + hp = heapp->h_provider(size + sizeof(union heap_header)); + if (hp != NULL) { + hp->h.u.heap = heapp; + hp->h.size = size; + hp++; + return (void *)hp; + } + } + return NULL; +} + +#define LIMIT(p) (union heap_header *)((uint8_t *)(p) + \ + sizeof(union heap_header) + \ + (p)->h.size) + +/** + * @brief Frees a previously allocated memory block. + * + * @param[in] p pointer to the memory block to be freed + * + * @api + */ +void chHeapFree(void *p) { + union heap_header *qp, *hp; + MemoryHeap *heapp; + + chDbgCheck(p != NULL, "chHeapFree"); + + hp = (union heap_header *)p - 1; + heapp = hp->h.u.heap; + qp = &heapp->h_free; + H_LOCK(heapp); + + while (TRUE) { + chDbgAssert((hp < qp) || (hp >= LIMIT(qp)), + "chHeapFree(), #1", + "within free block"); + + if (((qp == &heapp->h_free) || (hp > qp)) && + ((qp->h.u.next == NULL) || (hp < qp->h.u.next))) { + /* Insertion after qp.*/ + hp->h.u.next = qp->h.u.next; + qp->h.u.next = hp; + /* Verifies if the newly inserted block should be merged.*/ + if (LIMIT(hp) == hp->h.u.next) { + /* Merge with the next block.*/ + hp->h.size += hp->h.u.next->h.size + sizeof(union heap_header); + hp->h.u.next = hp->h.u.next->h.u.next; + } + if ((LIMIT(qp) == hp)) { + /* Merge with the previous block.*/ + qp->h.size += hp->h.size + sizeof(union heap_header); + qp->h.u.next = hp->h.u.next; + } + break; + } + qp = qp->h.u.next; + } + + H_UNLOCK(heapp); + return; +} + +/** + * @brief Reports the heap status. + * @note This function is meant to be used in the test suite, it should + * not be really useful for the application code. + * @note This function is not implemented when the @p CH_USE_MALLOC_HEAP + * configuration option is used (it always returns zero). + * + * @param[in] heapp pointer to a heap descriptor or @p NULL in order to + * access the default heap. + * @param[in] sizep pointer to a variable that will receive the total + * fragmented free space + * @return The number of fragments in the heap. + * + * @api + */ +size_t chHeapStatus(MemoryHeap *heapp, size_t *sizep) { + union heap_header *qp; + size_t n, sz; + + if (heapp == NULL) + heapp = &default_heap; + + H_LOCK(heapp); + + sz = 0; + for (n = 0, qp = &heapp->h_free; qp->h.u.next; n++, qp = qp->h.u.next) + sz += qp->h.u.next->h.size; + if (sizep) + *sizep = sz; + + H_UNLOCK(heapp); + return n; +} + +/** + * @brief Reports the min/max size of fragments on heap. + * @note This function is not implemented when the @p CH_USE_MALLOC_HEAP + * configuration option is used (it always returns zero). + * + * @param[in] heapp pointer to a heap descriptor or @p NULL in order to + * access the default heap. + * @param[in] min pointer to a variable that will receive the min free fragmented size + * @param[in] max pointer to a variable that will receive the max free fragmented size + * @return The number of fragments in the heap. + * + * @api + */ +void chHeapMaxMinFraq(MemoryHeap *heapp, size_t *min, size_t *max) { + union heap_header *qp; + size_t n, sz; + *min = 0; + *max = 0; + + if (heapp == NULL) + heapp = &default_heap; + + H_LOCK(heapp); + + for (n = 0, qp = &heapp->h_free; qp->h.u.next; n++, qp = qp->h.u.next){ + sz = qp->h.u.next->h.size; + if(*min>sz) + *min = sz; + if(*max + +#if CH_USE_MUTEXES +#define H_LOCK() chMtxLock(&hmtx) +#define H_UNLOCK() chMtxUnlock() +static Mutex hmtx; +#elif CH_USE_SEMAPHORES +#define H_LOCK() chSemWait(&hsem) +#define H_UNLOCK() chSemSignal(&hsem) +static Semaphore hsem; +#endif + +void _heap_init(void) { + +#if CH_USE_MUTEXES + chMtxInit(&hmtx); +#else + chSemInit(&hsem, 1); +#endif +} + +void *chHeapAlloc(MemoryHeap *heapp, size_t size) { + void *p; + + chDbgCheck(heapp == NULL, "chHeapAlloc"); + + H_LOCK(); + p = malloc(size); + H_UNLOCK(); + return p; +} + +void chHeapFree(void *p) { + + chDbgCheck(p != NULL, "chHeapFree"); + + H_LOCK(); + free(p); + H_UNLOCK(); +} + +size_t chHeapStatus(MemoryHeap *heapp, size_t *sizep) { + + chDbgCheck(heapp == NULL, "chHeapStatus"); + + if (sizep) + *sizep = 0; + return 0; +} + +#endif /* CH_USE_MALLOC_HEAP */ + +#endif /* CH_USE_HEAP */ + +/** @} */ diff --git a/Project/os/kernel/src/chlists.c b/Project/os/kernel/src/chlists.c new file mode 100644 index 0000000..a21d408 --- /dev/null +++ b/Project/os/kernel/src/chlists.c @@ -0,0 +1,163 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chlists.c + * @brief Thread queues/lists code. + * + * @addtogroup internals + * @details All the functions present in this module, while public, are not + * OS APIs and should not be directly used in the user applications + * code. + * @{ + */ +#include "ch.h" + +#if !CH_OPTIMIZE_SPEED || defined(__DOXYGEN__) +/** + * @brief Inserts a thread into a priority ordered queue. + * @note The insertion is done by scanning the list from the highest + * priority toward the lowest. + * + * @param[in] tp the pointer to the thread to be inserted in the list + * @param[in] tqp the pointer to the threads list header + * + * @notapi + */ +void prio_insert(Thread *tp, ThreadsQueue *tqp) { + + /* cp iterates over the queue.*/ + Thread *cp = (Thread *)tqp; + do { + /* Iterate to next thread in queue.*/ + cp = cp->p_next; + /* Not end of queue? and cp has equal or higher priority than tp?.*/ + } while ((cp != (Thread *)tqp) && (cp->p_prio >= tp->p_prio)); + /* Insertion on p_prev.*/ + tp->p_next = cp; + tp->p_prev = cp->p_prev; + tp->p_prev->p_next = cp->p_prev = tp; +} + +/** + * @brief Inserts a Thread into a queue. + * + * @param[in] tp the pointer to the thread to be inserted in the list + * @param[in] tqp the pointer to the threads list header + * + * @notapi + */ +void queue_insert(Thread *tp, ThreadsQueue *tqp) { + + tp->p_next = (Thread *)tqp; + tp->p_prev = tqp->p_prev; + tp->p_prev->p_next = tqp->p_prev = tp; +} + +/** + * @brief Removes the first-out Thread from a queue and returns it. + * @note If the queue is priority ordered then this function returns the + * thread with the highest priority. + * + * @param[in] tqp the pointer to the threads list header + * @return The removed thread pointer. + * + * @notapi + */ +Thread *fifo_remove(ThreadsQueue *tqp) { + Thread *tp = tqp->p_next; + + (tqp->p_next = tp->p_next)->p_prev = (Thread *)tqp; + return tp; +} + +/** + * @brief Removes the last-out Thread from a queue and returns it. + * @note If the queue is priority ordered then this function returns the + * thread with the lowest priority. + * + * @param[in] tqp the pointer to the threads list header + * @return The removed thread pointer. + * + * @notapi + */ +Thread *lifo_remove(ThreadsQueue *tqp) { + Thread *tp = tqp->p_prev; + + (tqp->p_prev = tp->p_prev)->p_next = (Thread *)tqp; + return tp; +} + +/** + * @brief Removes a Thread from a queue and returns it. + * @details The thread is removed from the queue regardless of its relative + * position and regardless the used insertion method. + * + * @param[in] tp the pointer to the thread to be removed from the queue + * @return The removed thread pointer. + * + * @notapi + */ +Thread *dequeue(Thread *tp) { + + tp->p_prev->p_next = tp->p_next; + tp->p_next->p_prev = tp->p_prev; + return tp; +} + +/** + * @brief Pushes a Thread on top of a stack list. + * + * @param[in] tp the pointer to the thread to be inserted in the list + * @param[in] tlp the pointer to the threads list header + * + * @notapi + */ +void list_insert(Thread *tp, ThreadsList *tlp) { + + tp->p_next = tlp->p_next; + tlp->p_next = tp; +} + +/** + * @brief Pops a Thread from the top of a stack list and returns it. + * @pre The list must be non-empty before calling this function. + * + * @param[in] tlp the pointer to the threads list header + * @return The removed thread pointer. + * + * @notapi + */ +Thread *list_remove(ThreadsList *tlp) { + + Thread *tp = tlp->p_next; + tlp->p_next = tp->p_next; + return tp; +} +#endif /* CH_OPTIMIZE_SPEED */ + +/** @} */ diff --git a/Project/os/kernel/src/chmboxes.c b/Project/os/kernel/src/chmboxes.c new file mode 100644 index 0000000..94a1c98 --- /dev/null +++ b/Project/os/kernel/src/chmboxes.c @@ -0,0 +1,383 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chmboxes.c + * @brief Mailboxes code. + * + * @addtogroup mailboxes + * @details Asynchronous messages. + *

Operation mode

+ * A mailbox is an asynchronous communication mechanism.
+ * Operations defined for mailboxes: + * - Post: Posts a message on the mailbox in FIFO order. + * - Post Ahead: Posts a message on the mailbox with urgent + * priority. + * - Fetch: A message is fetched from the mailbox and removed + * from the queue. + * - Reset: The mailbox is emptied and all the stored messages + * are lost. + * . + * A message is a variable of type msg_t that is guaranteed to have + * the same size of and be compatible with (data) pointers (anyway an + * explicit cast is needed). + * If larger messages need to be exchanged then a pointer to a + * structure can be posted in the mailbox but the posting side has + * no predefined way to know when the message has been processed. A + * possible approach is to allocate memory (from a memory pool as + * example) from the posting side and free it on the fetching side. + * Another approach is to set a "done" flag into the structure pointed + * by the message. + * @pre In order to use the mailboxes APIs the @p CH_USE_MAILBOXES option + * must be enabled in @p chconf.h. + * @{ + */ + +#include "ch.h" + +#if CH_USE_MAILBOXES || defined(__DOXYGEN__) +/** + * @brief Initializes a Mailbox object. + * + * @param[out] mbp the pointer to the Mailbox structure to be initialized + * @param[in] buf the circular messages buffer + * @param[in] n the buffer size as number of @p msg_t + * + * @init + */ +void chMBInit(Mailbox *mbp, msg_t *buf, cnt_t n) { + + chDbgCheck((mbp != NULL) && (buf != NULL) && (n > 0), "chMBInit"); + + mbp->mb_buffer = mbp->mb_wrptr = mbp->mb_rdptr = buf; + mbp->mb_top = &buf[n]; + chSemInit(&mbp->mb_emptysem, n); + chSemInit(&mbp->mb_fullsem, 0); +} + +/** + * @brief Resets a Mailbox object. + * @details All the waiting threads are resumed with status @p RDY_RESET and + * the queued messages are lost. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * + * @api + */ +void chMBReset(Mailbox *mbp) { + + chDbgCheck(mbp != NULL, "chMBReset"); + + chSysLock(); + mbp->mb_wrptr = mbp->mb_rdptr = mbp->mb_buffer; + chSemResetI(&mbp->mb_emptysem, mbp->mb_top - mbp->mb_buffer); + chSemResetI(&mbp->mb_fullsem, 0); + chSchRescheduleS(); + chSysUnlock(); +} + +/** + * @brief Posts a message into a mailbox. + * @details The invoking thread waits until a empty slot in the mailbox becomes + * available or the specified time runs out. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @param[in] msg the message to be posted on the mailbox + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if a message has been correctly posted. + * @retval RDY_RESET if the mailbox has been reset while waiting. + * @retval RDY_TIMEOUT if the operation has timed out. + * + * @api + */ +msg_t chMBPost(Mailbox *mbp, msg_t msg, systime_t time) { + msg_t rdymsg; + + chSysLock(); + rdymsg = chMBPostS(mbp, msg, time); + chSysUnlock(); + return rdymsg; +} + +/** + * @brief Posts a message into a mailbox. + * @details The invoking thread waits until a empty slot in the mailbox becomes + * available or the specified time runs out. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @param[in] msg the message to be posted on the mailbox + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if a message has been correctly posted. + * @retval RDY_RESET if the mailbox has been reset while waiting. + * @retval RDY_TIMEOUT if the operation has timed out. + * + * @sclass + */ +msg_t chMBPostS(Mailbox *mbp, msg_t msg, systime_t time) { + msg_t rdymsg; + + chDbgCheckClassS(); + chDbgCheck(mbp != NULL, "chMBPostS"); + + rdymsg = chSemWaitTimeoutS(&mbp->mb_emptysem, time); + if (rdymsg == RDY_OK) { + *mbp->mb_wrptr++ = msg; + if (mbp->mb_wrptr >= mbp->mb_top) + mbp->mb_wrptr = mbp->mb_buffer; + chSemSignalI(&mbp->mb_fullsem); + chSchRescheduleS(); + } + return rdymsg; +} + +/** + * @brief Posts a message into a mailbox. + * @details This variant is non-blocking, the function returns a timeout + * condition if the queue is full. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @param[in] msg the message to be posted on the mailbox + * @return The operation status. + * @retval RDY_OK if a message has been correctly posted. + * @retval RDY_TIMEOUT if the mailbox is full and the message cannot be + * posted. + * + * @iclass + */ +msg_t chMBPostI(Mailbox *mbp, msg_t msg) { + + chDbgCheckClassI(); + chDbgCheck(mbp != NULL, "chMBPostI"); + + if (chSemGetCounterI(&mbp->mb_emptysem) <= 0) + return RDY_TIMEOUT; + chSemFastWaitI(&mbp->mb_emptysem); + *mbp->mb_wrptr++ = msg; + if (mbp->mb_wrptr >= mbp->mb_top) + mbp->mb_wrptr = mbp->mb_buffer; + chSemSignalI(&mbp->mb_fullsem); + return RDY_OK; +} + +/** + * @brief Posts an high priority message into a mailbox. + * @details The invoking thread waits until a empty slot in the mailbox becomes + * available or the specified time runs out. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @param[in] msg the message to be posted on the mailbox + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if a message has been correctly posted. + * @retval RDY_RESET if the mailbox has been reset while waiting. + * @retval RDY_TIMEOUT if the operation has timed out. + * + * @api + */ +msg_t chMBPostAhead(Mailbox *mbp, msg_t msg, systime_t time) { + msg_t rdymsg; + + chSysLock(); + rdymsg = chMBPostAheadS(mbp, msg, time); + chSysUnlock(); + return rdymsg; +} + +/** + * @brief Posts an high priority message into a mailbox. + * @details The invoking thread waits until a empty slot in the mailbox becomes + * available or the specified time runs out. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @param[in] msg the message to be posted on the mailbox + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if a message has been correctly posted. + * @retval RDY_RESET if the mailbox has been reset while waiting. + * @retval RDY_TIMEOUT if the operation has timed out. + * + * @sclass + */ +msg_t chMBPostAheadS(Mailbox *mbp, msg_t msg, systime_t time) { + msg_t rdymsg; + + chDbgCheckClassS(); + chDbgCheck(mbp != NULL, "chMBPostAheadS"); + + rdymsg = chSemWaitTimeoutS(&mbp->mb_emptysem, time); + if (rdymsg == RDY_OK) { + if (--mbp->mb_rdptr < mbp->mb_buffer) + mbp->mb_rdptr = mbp->mb_top - 1; + *mbp->mb_rdptr = msg; + chSemSignalI(&mbp->mb_fullsem); + chSchRescheduleS(); + } + return rdymsg; +} + +/** + * @brief Posts an high priority message into a mailbox. + * @details This variant is non-blocking, the function returns a timeout + * condition if the queue is full. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @param[in] msg the message to be posted on the mailbox + * @return The operation status. + * @retval RDY_OK if a message has been correctly posted. + * @retval RDY_TIMEOUT if the mailbox is full and the message cannot be + * posted. + * + * @iclass + */ +msg_t chMBPostAheadI(Mailbox *mbp, msg_t msg) { + + chDbgCheckClassI(); + chDbgCheck(mbp != NULL, "chMBPostAheadI"); + + if (chSemGetCounterI(&mbp->mb_emptysem) <= 0) + return RDY_TIMEOUT; + chSemFastWaitI(&mbp->mb_emptysem); + if (--mbp->mb_rdptr < mbp->mb_buffer) + mbp->mb_rdptr = mbp->mb_top - 1; + *mbp->mb_rdptr = msg; + chSemSignalI(&mbp->mb_fullsem); + return RDY_OK; +} + +/** + * @brief Retrieves a message from a mailbox. + * @details The invoking thread waits until a message is posted in the mailbox + * or the specified time runs out. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @param[out] msgp pointer to a message variable for the received message + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if a message has been correctly fetched. + * @retval RDY_RESET if the mailbox has been reset while waiting. + * @retval RDY_TIMEOUT if the operation has timed out. + * + * @api + */ +msg_t chMBFetch(Mailbox *mbp, msg_t *msgp, systime_t time) { + msg_t rdymsg; + + chSysLock(); + rdymsg = chMBFetchS(mbp, msgp, time); + chSysUnlock(); + return rdymsg; +} + +/** + * @brief Retrieves a message from a mailbox. + * @details The invoking thread waits until a message is posted in the mailbox + * or the specified time runs out. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @param[out] msgp pointer to a message variable for the received message + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if a message has been correctly fetched. + * @retval RDY_RESET if the mailbox has been reset while waiting. + * @retval RDY_TIMEOUT if the operation has timed out. + * + * @sclass + */ +msg_t chMBFetchS(Mailbox *mbp, msg_t *msgp, systime_t time) { + msg_t rdymsg; + + chDbgCheckClassS(); + chDbgCheck((mbp != NULL) && (msgp != NULL), "chMBFetchS"); + + rdymsg = chSemWaitTimeoutS(&mbp->mb_fullsem, time); + if (rdymsg == RDY_OK) { + *msgp = *mbp->mb_rdptr++; + if (mbp->mb_rdptr >= mbp->mb_top) + mbp->mb_rdptr = mbp->mb_buffer; + chSemSignalI(&mbp->mb_emptysem); + chSchRescheduleS(); + } + return rdymsg; +} + +/** + * @brief Retrieves a message from a mailbox. + * @details This variant is non-blocking, the function returns a timeout + * condition if the queue is full. + * + * @param[in] mbp the pointer to an initialized Mailbox object + * @param[out] msgp pointer to a message variable for the received message + * @return The operation status. + * @retval RDY_OK if a message has been correctly fetched. + * @retval RDY_TIMEOUT if the mailbox is empty and a message cannot be + * fetched. + * + * @iclass + */ +msg_t chMBFetchI(Mailbox *mbp, msg_t *msgp) { + + chDbgCheckClassI(); + chDbgCheck((mbp != NULL) && (msgp != NULL), "chMBFetchI"); + + if (chSemGetCounterI(&mbp->mb_fullsem) <= 0) + return RDY_TIMEOUT; + chSemFastWaitI(&mbp->mb_fullsem); + *msgp = *mbp->mb_rdptr++; + if (mbp->mb_rdptr >= mbp->mb_top) + mbp->mb_rdptr = mbp->mb_buffer; + chSemSignalI(&mbp->mb_emptysem); + return RDY_OK; +} +#endif /* CH_USE_MAILBOXES */ + +/** @} */ diff --git a/Project/os/kernel/src/chmemcore.c b/Project/os/kernel/src/chmemcore.c new file mode 100644 index 0000000..cf5f50b --- /dev/null +++ b/Project/os/kernel/src/chmemcore.c @@ -0,0 +1,138 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chmemcore.c + * @brief Core memory manager code. + * + * @addtogroup memcore + * @details Core Memory Manager related APIs and services. + *

Operation mode

+ * The core memory manager is a simplified allocator that only + * allows to allocate memory blocks without the possibility to + * free them.
+ * This allocator is meant as a memory blocks provider for the + * other allocators such as: + * - C-Runtime allocator (through a compiler specific adapter module). + * - Heap allocator (see @ref heaps). + * - Memory pools allocator (see @ref pools). + * . + * By having a centralized memory provider the various allocators + * can coexist and share the main memory.
+ * This allocator, alone, is also useful for very simple + * applications that just require a simple way to get memory + * blocks. + * @pre In order to use the core memory manager APIs the @p CH_USE_MEMCORE + * option must be enabled in @p chconf.h. + * @{ + */ + +#include "ch.h" + +#if CH_USE_MEMCORE || defined(__DOXYGEN__) + +static uint8_t *nextmem; +static uint8_t *endmem; + +/** + * @brief Low level memory manager initialization. + * + * @notapi + */ +void _core_init(void) { +#if CH_MEMCORE_SIZE == 0 + extern uint8_t __heap_base__[]; + extern uint8_t __heap_end__[]; + nextmem = (uint8_t *)MEM_ALIGN_NEXT(__heap_base__); + endmem = (uint8_t *)MEM_ALIGN_PREV(__heap_end__); +#else + static stkalign_t buffer[MEM_ALIGN_NEXT(CH_MEMCORE_SIZE)/MEM_ALIGN_SIZE]; + nextmem = (uint8_t *)&buffer[0]; + endmem = (uint8_t *)&buffer[MEM_ALIGN_NEXT(CH_MEMCORE_SIZE)/MEM_ALIGN_SIZE]; +#endif +} + +/** + * @brief Allocates a memory block. + * @details The size of the returned block is aligned to the alignment + * type so it is not possible to allocate less + * than MEM_ALIGN_SIZE. + * + * @param[in] size the size of the block to be allocated + * @return A pointer to the allocated memory block. + * @retval NULL allocation failed, core memory exhausted. + * + * @api + */ +void *chCoreAlloc(size_t size) { + void *p; + + chSysLock(); + p = chCoreAllocI(size); + chSysUnlock(); + return p; +} + +/** + * @brief Allocates a memory block. + * @details The size of the returned block is aligned to the alignment + * type so it is not possible to allocate less than + * MEM_ALIGN_SIZE. + * + * @param[in] size the size of the block to be allocated. + * @return A pointer to the allocated memory block. + * @retval NULL allocation failed, core memory exhausted. + * + * @iclass + */ +void *chCoreAllocI(size_t size) { + void *p; + + chDbgCheckClassI(); + + size = MEM_ALIGN_NEXT(size); + if ((size_t)(endmem - nextmem) < size) + return NULL; + p = nextmem; + nextmem += size; + return p; +} + +/** + * @brief Core memory status. + * + * @return The size, in bytes, of the free core memory. + * + * @api + */ +size_t chCoreStatus(void) { + + return (size_t)(endmem - nextmem); +} +#endif /* CH_USE_MEMCORE */ + +/** @} */ diff --git a/Project/os/kernel/src/chmempools.c b/Project/os/kernel/src/chmempools.c new file mode 100644 index 0000000..0d49904 --- /dev/null +++ b/Project/os/kernel/src/chmempools.c @@ -0,0 +1,153 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chmempools.c + * @brief Memory Pools code. + * + * @addtogroup pools + * @details Memory Pools related APIs and services. + *

Operation mode

+ * The Memory Pools APIs allow to allocate/free fixed size objects in + * constant time and reliably without memory fragmentation + * problems. + * @pre In order to use the memory pools APIs the @p CH_USE_MEMPOOLS option + * must be enabled in @p chconf.h. + * @{ + */ + +#include "ch.h" + +#if CH_USE_MEMPOOLS || defined(__DOXYGEN__) +/** + * @brief Initializes an empty memory pool. + * @note The size is internally aligned to be a multiple of the + * @p stkalign_t type size. + * + * @param[out] mp pointer to a @p MemoryPool structure + * @param[in] size the size of the objects contained in this memory pool, + * the minimum accepted size is the size of a pointer to + * void. + * @param[in] provider memory provider function for the memory pool or + * @p NULL if the pool is not allowed to grow + * automatically + * + * @init + */ +void chPoolInit(MemoryPool *mp, size_t size, memgetfunc_t provider) { + + chDbgCheck((mp != NULL) && (size >= sizeof(void *)), "chPoolInit"); + + mp->mp_next = NULL; + mp->mp_object_size = MEM_ALIGN_NEXT(size); + mp->mp_provider = provider; +} + +/** + * @brief Allocates an object from a memory pool. + * + * @param[in] mp pointer to a @p MemoryPool structure + * @return The pointer to the allocated object. + * @retval NULL if pool is empty. + * + * @iclass + */ +void *chPoolAllocI(MemoryPool *mp) { + void *objp; + + chDbgCheckClassI(); + chDbgCheck(mp != NULL, "chPoolAllocI"); + + if ((objp = mp->mp_next) != NULL) + mp->mp_next = mp->mp_next->ph_next; + else if (mp->mp_provider != NULL) + objp = mp->mp_provider(mp->mp_object_size); + return objp; +} + +/** + * @brief Allocates an object from a memory pool. + * + * @param[in] mp pointer to a @p MemoryPool structure + * @return The pointer to the allocated object. + * @retval NULL if pool is empty. + * + * @api + */ +void *chPoolAlloc(MemoryPool *mp) { + void *objp; + + chSysLock(); + objp = chPoolAllocI(mp); + chSysUnlock(); + return objp; +} + +/** + * @brief Releases (or adds) an object into (to) a memory pool. + * @pre The freed object must be of the right size for the specified + * memory pool. + * @pre The freed object must be memory aligned to the size of + * @p stkalign_t type. + * + * @param[in] mp pointer to a @p MemoryPool structure + * @param[in] objp the pointer to the object to be released or added + * + * @iclass + */ +void chPoolFreeI(MemoryPool *mp, void *objp) { + struct pool_header *php = objp; + + chDbgCheckClassI(); + chDbgCheck((mp != NULL) && (objp != NULL) && MEM_IS_ALIGNED(objp), + "chPoolFreeI"); + + php->ph_next = mp->mp_next; + mp->mp_next = php; +} + +/** + * @brief Releases (or adds) an object into (to) a memory pool. + * @pre The freed object must be of the right size for the specified + * memory pool. + * @pre The freed object must be memory aligned to the size of + * @p stkalign_t type. + * + * @param[in] mp pointer to a @p MemoryPool structure + * @param[in] objp the pointer to the object to be released or added + * + * @api + */ +void chPoolFree(MemoryPool *mp, void *objp) { + + chSysLock(); + chPoolFreeI(mp, objp); + chSysUnlock(); +} +#endif /* CH_USE_MEMPOOLS */ + +/** @} */ diff --git a/Project/os/kernel/src/chmsg.c b/Project/os/kernel/src/chmsg.c new file mode 100644 index 0000000..c0aff4e --- /dev/null +++ b/Project/os/kernel/src/chmsg.c @@ -0,0 +1,139 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chmsg.c + * @brief Messages code. + * + * @addtogroup messages + * @details Synchronous inter-thread messages APIs and services. + *

Operation Mode

+ * Synchronous messages are an easy to use and fast IPC mechanism, + * threads can both act as message servers and/or message clients, + * the mechanism allows data to be carried in both directions. Note + * that messages are not copied between the client and server threads + * but just a pointer passed so the exchange is very time + * efficient.
+ * Messages are scalar data types of type @p msg_t that are guaranteed + * to be size compatible with data pointers. Note that on some + * architectures function pointers can be larger that @p msg_t.
+ * Messages are usually processed in FIFO order but it is possible to + * process them in priority order by enabling the + * @p CH_USE_MESSAGES_PRIORITY option in @p chconf.h.
+ * @pre In order to use the message APIs the @p CH_USE_MESSAGES option + * must be enabled in @p chconf.h. + * @post Enabling messages requires 6-12 (depending on the architecture) + * extra bytes in the @p Thread structure. + * @{ + */ + +#include "ch.h" + +#if CH_USE_MESSAGES || defined(__DOXYGEN__) + +#if CH_USE_MESSAGES_PRIORITY +#define msg_insert(tp, qp) prio_insert(tp, qp) +#else +#define msg_insert(tp, qp) queue_insert(tp, qp) +#endif + +/** + * @brief Sends a message to the specified thread. + * @details The sender is stopped until the receiver executes a + * @p chMsgRelease()after receiving the message. + * + * @param[in] tp the pointer to the thread + * @param[in] msg the message + * @return The answer message from @p chMsgRelease(). + * + * @api + */ +msg_t chMsgSend(Thread *tp, msg_t msg) { + Thread *ctp = currp; + + chDbgCheck(tp != NULL, "chMsgSend"); + + chSysLock(); + ctp->p_msg = msg; + ctp->p_u.wtobjp = &tp->p_msgqueue; + msg_insert(ctp, &tp->p_msgqueue); + if (tp->p_state == THD_STATE_WTMSG) + chSchReadyI(tp); + chSchGoSleepS(THD_STATE_SNDMSGQ); + msg = ctp->p_u.rdymsg; + chSysUnlock(); + return msg; +} + +/** + * @brief Suspends the thread and waits for an incoming message. + * @post After receiving a message the function @p chMsgGet() must be + * called in order to retrieve the message and then @p chMsgRelease() + * must be invoked in order to acknowledge the reception and send + * the answer. + * @note If the message is a pointer then you can assume that the data + * pointed by the message is stable until you invoke @p chMsgRelease() + * because the sending thread is suspended until then. + * + * @return A reference to the thread carrying the message. + * + * @api + */ +Thread *chMsgWait(void) { + Thread *tp; + + chSysLock(); + if (!chMsgIsPendingI(currp)) + chSchGoSleepS(THD_STATE_WTMSG); + tp = fifo_remove(&currp->p_msgqueue); + tp->p_state = THD_STATE_SNDMSG; + chSysUnlock(); + return tp; +} + +/** + * @brief Releases a sender thread specifying a response message. + * @pre Invoke this function only after a message has been received + * using @p chMsgWait(). + * + * @param[in] tp pointer to the thread + * @param[in] msg message to be returned to the sender + * + * @api + */ +void chMsgRelease(Thread *tp, msg_t msg) { + + chSysLock(); + chDbgAssert(tp->p_state == THD_STATE_SNDMSG, + "chMsgRelease(), #1", "invalid state"); + chMsgReleaseS(tp, msg); + chSysUnlock(); +} + +#endif /* CH_USE_MESSAGES */ + +/** @} */ diff --git a/Project/os/kernel/src/chmtx.c b/Project/os/kernel/src/chmtx.c new file mode 100644 index 0000000..2c31071 --- /dev/null +++ b/Project/os/kernel/src/chmtx.c @@ -0,0 +1,400 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chmtx.c + * @brief Mutexes code. + * + * @addtogroup mutexes + * @details Mutexes related APIs and services. + * + *

Operation mode

+ * A mutex is a threads synchronization object that can be in two + * distinct states: + * - Not owned (unlocked). + * - Owned by a thread (locked). + * . + * Operations defined for mutexes: + * - Lock: The mutex is checked, if the mutex is not owned by + * some other thread then it is associated to the locking thread + * else the thread is queued on the mutex in a list ordered by + * priority. + * - Unlock: The mutex is released by the owner and the highest + * priority thread waiting in the queue, if any, is resumed and made + * owner of the mutex. + * . + *

Constraints

+ * In ChibiOS/RT the Unlock operations are always performed in + * lock-reverse order. The unlock API does not even have a parameter, + * the mutex to unlock is selected from an internal, per-thread, stack + * of owned mutexes. This both improves the performance and is + * required for an efficient implementation of the priority + * inheritance mechanism. + * + *

The priority inversion problem

+ * The mutexes in ChibiOS/RT implements the full priority + * inheritance mechanism in order handle the priority inversion + * problem.
+ * When a thread is queued on a mutex, any thread, directly or + * indirectly, holding the mutex gains the same priority of the + * waiting thread (if their priority was not already equal or higher). + * The mechanism works with any number of nested mutexes and any + * number of involved threads. The algorithm complexity (worst case) + * is N with N equal to the number of nested mutexes. + * @pre In order to use the mutex APIs the @p CH_USE_MUTEXES option + * must be enabled in @p chconf.h. + * @post Enabling mutexes requires 5-12 (depending on the architecture) + * extra bytes in the @p Thread structure. + * @{ + */ + +#include "ch.h" + +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + +/** + * @brief Initializes s @p Mutex structure. + * + * @param[out] mp pointer to a @p Mutex structure + * + * @init + */ +void chMtxInit(Mutex *mp) { + + chDbgCheck(mp != NULL, "chMtxInit"); + + queue_init(&mp->m_queue); + mp->m_owner = NULL; +} + +/** + * @brief Locks the specified mutex. + * @post The mutex is locked and inserted in the per-thread stack of owned + * mutexes. + * + * @param[in] mp pointer to the @p Mutex structure + * + * @api + */ +void chMtxLock(Mutex *mp) { + + chSysLock(); + + chMtxLockS(mp); + + chSysUnlock(); +} + +/** + * @brief Locks the specified mutex. + * @post The mutex is locked and inserted in the per-thread stack of owned + * mutexes. + * + * @param[in] mp pointer to the @p Mutex structure + * + * @sclass + */ +void chMtxLockS(Mutex *mp) { + Thread *ctp = currp; + + chDbgCheckClassS(); + chDbgCheck(mp != NULL, "chMtxLockS"); + + /* Is the mutex already locked? */ + if (mp->m_owner != NULL) { + /* Priority inheritance protocol; explores the thread-mutex dependencies + boosting the priority of all the affected threads to equal the priority + of the running thread requesting the mutex.*/ + Thread *tp = mp->m_owner; + /* Does the running thread have higher priority than the mutex + owning thread? */ + while (tp->p_prio < ctp->p_prio) { + /* Make priority of thread tp match the running thread's priority.*/ + tp->p_prio = ctp->p_prio; + /* The following states need priority queues reordering.*/ + switch (tp->p_state) { + case THD_STATE_WTMTX: + /* Re-enqueues the mutex owner with its new priority.*/ + prio_insert(dequeue(tp), (ThreadsQueue *)tp->p_u.wtobjp); + tp = ((Mutex *)tp->p_u.wtobjp)->m_owner; + continue; +#if CH_USE_CONDVARS | \ + (CH_USE_SEMAPHORES && CH_USE_SEMAPHORES_PRIORITY) | \ + (CH_USE_MESSAGES && CH_USE_MESSAGES_PRIORITY) +#if CH_USE_CONDVARS + case THD_STATE_WTCOND: +#endif +#if CH_USE_SEMAPHORES && CH_USE_SEMAPHORES_PRIORITY + case THD_STATE_WTSEM: +#endif +#if CH_USE_MESSAGES && CH_USE_MESSAGES_PRIORITY + case THD_STATE_SNDMSGQ: +#endif + /* Re-enqueues tp with its new priority on the queue.*/ + prio_insert(dequeue(tp), (ThreadsQueue *)tp->p_u.wtobjp); + break; +#endif + case THD_STATE_READY: +#if CH_DBG_ENABLE_ASSERTS + /* Prevents an assertion in chSchReadyI().*/ + tp->p_state = THD_STATE_CURRENT; +#endif + /* Re-enqueues tp with its new priority on the ready list.*/ + chSchReadyI(dequeue(tp)); + break; + } + break; + } + /* Sleep on the mutex.*/ + prio_insert(ctp, &mp->m_queue); + ctp->p_u.wtobjp = mp; + chSchGoSleepS(THD_STATE_WTMTX); + /* It is assumed that the thread performing the unlock operation assigns + the mutex to this thread.*/ + chDbgAssert(mp->m_owner == ctp, "chMtxLockS(), #1", "not owner"); + chDbgAssert(ctp->p_mtxlist == mp, "chMtxLockS(), #2", "not owned"); + } + else { + /* It was not owned, inserted in the owned mutexes list.*/ + mp->m_owner = ctp; + mp->m_next = ctp->p_mtxlist; + ctp->p_mtxlist = mp; + } +} + +/** + * @brief Tries to lock a mutex. + * @details This function attempts to lock a mutex, if the mutex is already + * locked by another thread then the function exits without waiting. + * @post The mutex is locked and inserted in the per-thread stack of owned + * mutexes. + * @note This function does not have any overhead related to the + * priority inheritance mechanism because it does not try to + * enter a sleep state. + * + * @param[in] mp pointer to the @p Mutex structure + * @return The operation status. + * @retval TRUE if the mutex has been successfully acquired + * @retval FALSE if the lock attempt failed. + * + * @api + */ +bool_t chMtxTryLock(Mutex *mp) { + bool_t b; + + chSysLock(); + + b = chMtxTryLockS(mp); + + chSysUnlock(); + return b; +} + +/** + * @brief Tries to lock a mutex. + * @details This function attempts to lock a mutex, if the mutex is already + * taken by another thread then the function exits without waiting. + * @post The mutex is locked and inserted in the per-thread stack of owned + * mutexes. + * @note This function does not have any overhead related to the + * priority inheritance mechanism because it does not try to + * enter a sleep state. + * + * @param[in] mp pointer to the @p Mutex structure + * @return The operation status. + * @retval TRUE if the mutex has been successfully acquired + * @retval FALSE if the lock attempt failed. + * + * @sclass + */ +bool_t chMtxTryLockS(Mutex *mp) { + + chDbgCheckClassS(); + chDbgCheck(mp != NULL, "chMtxTryLockS"); + + if (mp->m_owner != NULL) + return FALSE; + mp->m_owner = currp; + mp->m_next = currp->p_mtxlist; + currp->p_mtxlist = mp; + return TRUE; +} + +/** + * @brief Unlocks the next owned mutex in reverse lock order. + * @pre The invoking thread must have at least one owned mutex. + * @post The mutex is unlocked and removed from the per-thread stack of + * owned mutexes. + * + * @return A pointer to the unlocked mutex. + * + * @api + */ +Mutex *chMtxUnlock(void) { + Thread *ctp = currp; + Mutex *ump, *mp; + + chSysLock(); + chDbgAssert(ctp->p_mtxlist != NULL, + "chMtxUnlock(), #1", + "owned mutexes list empty"); + chDbgAssert(ctp->p_mtxlist->m_owner == ctp, + "chMtxUnlock(), #2", + "ownership failure"); + /* Removes the top Mutex from the Thread's owned mutexes list and mark it + as not owned.*/ + ump = ctp->p_mtxlist; + ctp->p_mtxlist = ump->m_next; + /* If a thread is waiting on the mutex then the fun part begins.*/ + if (chMtxQueueNotEmptyS(ump)) { + Thread *tp; + + /* Recalculates the optimal thread priority by scanning the owned + mutexes list.*/ + tprio_t newprio = ctp->p_realprio; + mp = ctp->p_mtxlist; + while (mp != NULL) { + /* If the highest priority thread waiting in the mutexes list has a + greater priority than the current thread base priority then the final + priority will have at least that priority.*/ + if (chMtxQueueNotEmptyS(mp) && (mp->m_queue.p_next->p_prio > newprio)) + newprio = mp->m_queue.p_next->p_prio; + mp = mp->m_next; + } + /* Assigns to the current thread the highest priority among all the + waiting threads.*/ + ctp->p_prio = newprio; + /* Awakens the highest priority thread waiting for the unlocked mutex and + assigns the mutex to it.*/ + tp = fifo_remove(&ump->m_queue); + ump->m_owner = tp; + ump->m_next = tp->p_mtxlist; + tp->p_mtxlist = ump; + chSchWakeupS(tp, RDY_OK); + } + else + ump->m_owner = NULL; + chSysUnlock(); + return ump; +} + +/** + * @brief Unlocks the next owned mutex in reverse lock order. + * @pre The invoking thread must have at least one owned mutex. + * @post The mutex is unlocked and removed from the per-thread stack of + * owned mutexes. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. + * + * @return A pointer to the unlocked mutex. + * + * @sclass + */ +Mutex *chMtxUnlockS(void) { + Thread *ctp = currp; + Mutex *ump, *mp; + + chDbgCheckClassS(); + chDbgAssert(ctp->p_mtxlist != NULL, + "chMtxUnlockS(), #1", + "owned mutexes list empty"); + chDbgAssert(ctp->p_mtxlist->m_owner == ctp, + "chMtxUnlockS(), #2", + "ownership failure"); + + /* Removes the top Mutex from the owned mutexes list and marks it as not + owned.*/ + ump = ctp->p_mtxlist; + ctp->p_mtxlist = ump->m_next; + /* If a thread is waiting on the mutex then the fun part begins.*/ + if (chMtxQueueNotEmptyS(ump)) { + Thread *tp; + + /* Recalculates the optimal thread priority by scanning the owned + mutexes list.*/ + tprio_t newprio = ctp->p_realprio; + mp = ctp->p_mtxlist; + while (mp != NULL) { + /* If the highest priority thread waiting in the mutexes list has a + greater priority than the current thread base priority then the final + priority will have at least that priority.*/ + if (chMtxQueueNotEmptyS(mp) && (mp->m_queue.p_next->p_prio > newprio)) + newprio = mp->m_queue.p_next->p_prio; + mp = mp->m_next; + } + ctp->p_prio = newprio; + /* Awakens the highest priority thread waiting for the unlocked mutex and + assigns the mutex to it.*/ + tp = fifo_remove(&ump->m_queue); + ump->m_owner = tp; + ump->m_next = tp->p_mtxlist; + tp->p_mtxlist = ump; + chSchReadyI(tp); + } + else + ump->m_owner = NULL; + return ump; +} + +/** + * @brief Unlocks all the mutexes owned by the invoking thread. + * @post The stack of owned mutexes is emptied and all the found + * mutexes are unlocked. + * @note This function is MUCH MORE efficient than releasing the + * mutexes one by one and not just because the call overhead, + * this function does not have any overhead related to the priority + * inheritance mechanism. + * + * @api + */ +void chMtxUnlockAll(void) { + Thread *ctp = currp; + + chSysLock(); + if (ctp->p_mtxlist != NULL) { + do { + Mutex *ump = ctp->p_mtxlist; + ctp->p_mtxlist = ump->m_next; + if (chMtxQueueNotEmptyS(ump)) { + Thread *tp = fifo_remove(&ump->m_queue); + ump->m_owner = tp; + ump->m_next = tp->p_mtxlist; + tp->p_mtxlist = ump; + chSchReadyI(tp); + } + else + ump->m_owner = NULL; + } while (ctp->p_mtxlist != NULL); + ctp->p_prio = ctp->p_realprio; + chSchRescheduleS(); + } + chSysUnlock(); +} + +#endif /* CH_USE_MUTEXES */ + +/** @} */ diff --git a/Project/os/kernel/src/chqueues.c b/Project/os/kernel/src/chqueues.c new file mode 100644 index 0000000..ea467c4 --- /dev/null +++ b/Project/os/kernel/src/chqueues.c @@ -0,0 +1,434 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chqueues.c + * @brief I/O Queues code. + * + * @addtogroup io_queues + * @details ChibiOS/RT queues are mostly used in serial-like device drivers. + * The device drivers are usually designed to have a lower side + * (lower driver, it is usually an interrupt service routine) and an + * upper side (upper driver, accessed by the application threads).
+ * There are several kind of queues:
+ * - Input queue, unidirectional queue where the writer is the + * lower side and the reader is the upper side. + * - Output queue, unidirectional queue where the writer is the + * upper side and the reader is the lower side. + * - Full duplex queue, bidirectional queue. Full duplex queues + * are implemented by pairing an input queue and an output queue + * together. + * . + * I/O queues are usually used as an implementation layer for the I/O + * channels interface, also see @ref io_channels. + * @pre In order to use the I/O queues the @p CH_USE_QUEUES option must + * be enabled in @p chconf.h. + * @{ + */ + +#include "ch.h" + +#if CH_USE_QUEUES || defined(__DOXYGEN__) + +/** + * @brief Puts the invoking thread into the queue's threads queue. + * + * @param[out] qp pointer to an @p GenericQueue structure + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return A message specifying how the invoking thread has been + * released from threads queue. + * @retval Q_OK is the normal exit, thread signaled. + * @retval Q_RESET if the queue has been reset. + * @retval Q_TIMEOUT if the queue operation timed out. + */ +static msg_t qwait(GenericQueue *qp, systime_t time) { + + if (TIME_IMMEDIATE == time) + return Q_TIMEOUT; + currp->p_u.wtobjp = qp; + queue_insert(currp, &qp->q_waiting); + return chSchGoSleepTimeoutS(THD_STATE_WTQUEUE, time); +} + +/** + * @brief Initializes an input queue. + * @details A Semaphore is internally initialized and works as a counter of + * the bytes contained in the queue. + * @note The callback is invoked from within the S-Locked system state, + * see @ref system_states. + * + * @param[out] iqp pointer to an @p InputQueue structure + * @param[in] bp pointer to a memory area allocated as queue buffer + * @param[in] size size of the queue buffer + * @param[in] infy pointer to a callback function that is invoked when + * data is read from the queue. The value can be @p NULL. + * + * @init + */ +void chIQInit(InputQueue *iqp, uint8_t *bp, size_t size, qnotify_t infy) { + + queue_init(&iqp->q_waiting); + iqp->q_counter = 0; + iqp->q_buffer = iqp->q_rdptr = iqp->q_wrptr = bp; + iqp->q_top = bp + size; + iqp->q_notify = infy; +} + +/** + * @brief Resets an input queue. + * @details All the data in the input queue is erased and lost, any waiting + * thread is resumed with status @p Q_RESET. + * @note A reset operation can be used by a low level driver in order to + * obtain immediate attention from the high level layers. + * + * @param[in] iqp pointer to an @p InputQueue structure + * + * @iclass + */ +void chIQResetI(InputQueue *iqp) { + + chDbgCheckClassI(); + + iqp->q_rdptr = iqp->q_wrptr = iqp->q_buffer; + iqp->q_counter = 0; + while (notempty(&iqp->q_waiting)) + chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_RESET; +} + +/** + * @brief Input queue write. + * @details A byte value is written into the low end of an input queue. + * + * @param[in] iqp pointer to an @p InputQueue structure + * @param[in] b the byte value to be written in the queue + * @return The operation status. + * @retval Q_OK if the operation has been completed with success. + * @retval Q_FULL if the queue is full and the operation cannot be + * completed. + * + * @iclass + */ +msg_t chIQPutI(InputQueue *iqp, uint8_t b) { + + chDbgCheckClassI(); + + if (chIQIsFullI(iqp)) + return Q_FULL; + + iqp->q_counter++; + *iqp->q_wrptr++ = b; + if (iqp->q_wrptr >= iqp->q_top) + iqp->q_wrptr = iqp->q_buffer; + + if (notempty(&iqp->q_waiting)) + chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_OK; + + return Q_OK; +} + +/** + * @brief Input queue read with timeout. + * @details This function reads a byte value from an input queue. If the queue + * is empty then the calling thread is suspended until a byte arrives + * in the queue or a timeout occurs. + * @note The callback is invoked before reading the character from the + * buffer or before entering the state @p THD_STATE_WTQUEUE. + * + * @param[in] iqp pointer to an @p InputQueue structure + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return A byte value from the queue. + * @retval Q_TIMEOUT if the specified time expired. + * @retval Q_RESET if the queue has been reset. + * + * @api + */ +msg_t chIQGetTimeout(InputQueue *iqp, systime_t time) { + uint8_t b; + + chSysLock(); + if (iqp->q_notify) + iqp->q_notify(iqp); + + while (chIQIsEmptyI(iqp)) { + msg_t msg; + if ((msg = qwait((GenericQueue *)iqp, time)) < Q_OK) { + chSysUnlock(); + return msg; + } + } + + iqp->q_counter--; + b = *iqp->q_rdptr++; + if (iqp->q_rdptr >= iqp->q_top) + iqp->q_rdptr = iqp->q_buffer; + + chSysUnlock(); + return b; +} + +/** + * @brief Input queue read with timeout. + * @details The function reads data from an input queue into a buffer. The + * operation completes when the specified amount of data has been + * transferred or after the specified timeout or if the queue has + * been reset. + * @note The function is not atomic, if you need atomicity it is suggested + * to use a semaphore or a mutex for mutual exclusion. + * @note The callback is invoked before reading each character from the + * buffer or before entering the state @p THD_STATE_WTQUEUE. + * + * @param[in] iqp pointer to an @p InputQueue structure + * @param[out] bp pointer to the data buffer + * @param[in] n the maximum amount of data to be transferred, the + * value 0 is reserved + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The number of bytes effectively transferred. + * + * @api + */ +size_t chIQReadTimeout(InputQueue *iqp, uint8_t *bp, + size_t n, systime_t time) { + qnotify_t nfy = iqp->q_notify; + size_t r = 0; + + chDbgCheck(n > 0, "chIQReadTimeout"); + + chSysLock(); + while (TRUE) { + if (nfy) + nfy(iqp); + + while (chIQIsEmptyI(iqp)) { + if (qwait((GenericQueue *)iqp, time) != Q_OK) { + chSysUnlock(); + return r; + } + } + + iqp->q_counter--; + *bp++ = *iqp->q_rdptr++; + if (iqp->q_rdptr >= iqp->q_top) + iqp->q_rdptr = iqp->q_buffer; + + chSysUnlock(); /* Gives a preemption chance in a controlled point.*/ + r++; + if (--n == 0) + return r; + + chSysLock(); + } +} + +/** + * @brief Initializes an output queue. + * @details A Semaphore is internally initialized and works as a counter of + * the free bytes in the queue. + * @note The callback is invoked from within the S-Locked system state, + * see @ref system_states. + * + * @param[out] oqp pointer to an @p OutputQueue structure + * @param[in] bp pointer to a memory area allocated as queue buffer + * @param[in] size size of the queue buffer + * @param[in] onfy pointer to a callback function that is invoked when + * data is written to the queue. The value can be @p NULL. + * + * @init + */ +void chOQInit(OutputQueue *oqp, uint8_t *bp, size_t size, qnotify_t onfy) { + + queue_init(&oqp->q_waiting); + oqp->q_counter = size; + oqp->q_buffer = oqp->q_rdptr = oqp->q_wrptr = bp; + oqp->q_top = bp + size; + oqp->q_notify = onfy; +} + +/** + * @brief Resets an output queue. + * @details All the data in the output queue is erased and lost, any waiting + * thread is resumed with status @p Q_RESET. + * @note A reset operation can be used by a low level driver in order to + * obtain immediate attention from the high level layers. + * + * @param[in] oqp pointer to an @p OutputQueue structure + * + * @iclass + */ +void chOQResetI(OutputQueue *oqp) { + + chDbgCheckClassI(); + + oqp->q_rdptr = oqp->q_wrptr = oqp->q_buffer; + oqp->q_counter = chQSizeI(oqp); + while (notempty(&oqp->q_waiting)) + chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_RESET; +} + +/** + * @brief Output queue write with timeout. + * @details This function writes a byte value to an output queue. If the queue + * is full then the calling thread is suspended until there is space + * in the queue or a timeout occurs. + * @note The callback is invoked after writing the character into the + * buffer. + * + * @param[in] oqp pointer to an @p OutputQueue structure + * @param[in] b the byte value to be written in the queue + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval Q_OK if the operation succeeded. + * @retval Q_TIMEOUT if the specified time expired. + * @retval Q_RESET if the queue has been reset. + * + * @api + */ +msg_t chOQPutTimeout(OutputQueue *oqp, uint8_t b, systime_t time) { + + chSysLock(); + while (chOQIsFullI(oqp)) { + msg_t msg; + + if ((msg = qwait((GenericQueue *)oqp, time)) < Q_OK) { + chSysUnlock(); + return msg; + } + } + + oqp->q_counter--; + *oqp->q_wrptr++ = b; + if (oqp->q_wrptr >= oqp->q_top) + oqp->q_wrptr = oqp->q_buffer; + + if (oqp->q_notify) + oqp->q_notify(oqp); + + chSysUnlock(); + return Q_OK; +} + +/** + * @brief Output queue read. + * @details A byte value is read from the low end of an output queue. + * + * @param[in] oqp pointer to an @p OutputQueue structure + * @return The byte value from the queue. + * @retval Q_EMPTY if the queue is empty. + * + * @iclass + */ +msg_t chOQGetI(OutputQueue *oqp) { + uint8_t b; + + chDbgCheckClassI(); + + if (chOQIsEmptyI(oqp)) + return Q_EMPTY; + + oqp->q_counter++; + b = *oqp->q_rdptr++; + if (oqp->q_rdptr >= oqp->q_top) + oqp->q_rdptr = oqp->q_buffer; + + if (notempty(&oqp->q_waiting)) + chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_OK; + + return b; +} + +/** + * @brief Output queue write with timeout. + * @details The function writes data from a buffer to an output queue. The + * operation completes when the specified amount of data has been + * transferred or after the specified timeout or if the queue has + * been reset. + * @note The function is not atomic, if you need atomicity it is suggested + * to use a semaphore or a mutex for mutual exclusion. + * @note The callback is invoked after writing each character into the + * buffer. + * + * @param[in] oqp pointer to an @p OutputQueue structure + * @param[out] bp pointer to the data buffer + * @param[in] n the maximum amount of data to be transferred, the + * value 0 is reserved + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return The number of bytes effectively transferred. + * + * @api + */ +size_t chOQWriteTimeout(OutputQueue *oqp, const uint8_t *bp, + size_t n, systime_t time) { + qnotify_t nfy = oqp->q_notify; + size_t w = 0; + + chDbgCheck(n > 0, "chOQWriteTimeout"); + + chSysLock(); + while (TRUE) { + while (chOQIsFullI(oqp)) { + if (qwait((GenericQueue *)oqp, time) != Q_OK) { + chSysUnlock(); + return w; + } + } + oqp->q_counter--; + *oqp->q_wrptr++ = *bp++; + if (oqp->q_wrptr >= oqp->q_top) + oqp->q_wrptr = oqp->q_buffer; + + if (nfy) + nfy(oqp); + + chSysUnlock(); /* Gives a preemption chance in a controlled point.*/ + w++; + if (--n == 0) + return w; + chSysLock(); + } +} +#endif /* CH_USE_QUEUES */ + +/** @} */ diff --git a/Project/os/kernel/src/chregistry.c b/Project/os/kernel/src/chregistry.c new file mode 100644 index 0000000..4bfa694 --- /dev/null +++ b/Project/os/kernel/src/chregistry.c @@ -0,0 +1,159 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chregistry.c + * @brief Threads registry code. + * + * @addtogroup registry + * @details Threads Registry related APIs and services. + * + *

Operation mode

+ * The Threads Registry is a double linked list that holds all the + * active threads in the system.
+ * Operations defined for the registry: + * - First, returns the first, in creation order, active thread + * in the system. + * - Next, returns the next, in creation order, active thread + * in the system. + * . + * The registry is meant to be mainly a debug feature, for example, + * using the registry a debugger can enumerate the active threads + * in any given moment or the shell can print the active threads + * and their state.
+ * Another possible use is for centralized threads memory management, + * terminating threads can pulse an event source and an event handler + * can perform a scansion of the registry in order to recover the + * memory. + * @pre In order to use the threads registry the @p CH_USE_REGISTRY option + * must be enabled in @p chconf.h. + * @{ + */ +#include "ch.h" + +#if CH_USE_REGISTRY || defined(__DOXYGEN__) + +#define _offsetof(st, m) \ + ((size_t)((char *)&((st *)0)->m - (char *)0)) + +/* + * OS signature in ROM plus debug-related information. + */ +ROMCONST chdebug_t ch_debug = { + "main", + (uint8_t)0, + (uint8_t)sizeof (chdebug_t), + (uint16_t)((CH_KERNEL_MAJOR << 11) | + (CH_KERNEL_MINOR << 6) | + (CH_KERNEL_PATCH) << 0), + (uint8_t)sizeof (void *), + (uint8_t)sizeof (systime_t), + (uint8_t)sizeof (Thread), + (uint8_t)_offsetof(Thread, p_prio), + (uint8_t)_offsetof(Thread, p_ctx), + (uint8_t)_offsetof(Thread, p_newer), + (uint8_t)_offsetof(Thread, p_older), + (uint8_t)_offsetof(Thread, p_name), +#if CH_DBG_ENABLE_STACK_CHECK + (uint8_t)_offsetof(Thread, p_stklimit), +#else + (uint8_t)0, +#endif + (uint8_t)_offsetof(Thread, p_state), + (uint8_t)_offsetof(Thread, p_flags), +#if CH_USE_DYNAMIC + (uint8_t)_offsetof(Thread, p_refs), +#else + (uint8_t)0, +#endif + (uint8_t)0, /* Not used in 2.4.x.*/ +#if CH_DBG_THREADS_PROFILING + (uint8_t)_offsetof(Thread, p_time) +#else + (uint8_t)0 +#endif +}; + +/** + * @brief Returns the first thread in the system. + * @details Returns the most ancient thread in the system, usually this is + * the main thread unless it terminated. A reference is added to the + * returned thread in order to make sure its status is not lost. + * @note This function cannot return @p NULL because there is always at + * least one thread in the system. + * + * @return A reference to the most ancient thread. + * + * @api + */ +Thread *chRegFirstThread(void) { + Thread *tp; + + chSysLock(); + tp = rlist.r_newer; +#if CH_USE_DYNAMIC + tp->p_refs++; +#endif + chSysUnlock(); + return tp; +} + +/** + * @brief Returns the thread next to the specified one. + * @details The reference counter of the specified thread is decremented and + * the reference counter of the returned thread is incremented. + * + * @param[in] tp pointer to the thread + * @return A reference to the next thread. + * @retval NULL if there is no next thread. + * + * @api + */ +Thread *chRegNextThread(Thread *tp) { + Thread *ntp; + + chSysLock(); + ntp = tp->p_newer; + if (ntp == (Thread *)&rlist) + ntp = NULL; +#if CH_USE_DYNAMIC + else { + chDbgAssert(ntp->p_refs < 255, "chRegNextThread(), #1", + "too many references"); + ntp->p_refs++; + } +#endif + chSysUnlock(); +#if CH_USE_DYNAMIC + chThdRelease(tp); +#endif + return ntp; +} + +#endif /* CH_USE_REGISTRY */ + +/** @} */ diff --git a/Project/os/kernel/src/chschd.c b/Project/os/kernel/src/chschd.c new file mode 100644 index 0000000..b87397a --- /dev/null +++ b/Project/os/kernel/src/chschd.c @@ -0,0 +1,313 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chschd.c + * @brief Scheduler code. + * + * @addtogroup scheduler + * @details This module provides the default portable scheduler code, + * scheduler functions can be individually captured by the port + * layer in order to provide architecture optimized equivalents. + * When a function is captured its default code is not built into + * the OS image, the optimized version is included instead. + * @{ + */ + +#include "ch.h" + +/** + * @brief Ready list header. + */ +#if !defined(PORT_OPTIMIZED_RLIST_VAR) || defined(__DOXYGEN__) +ReadyList rlist; +#endif /* !defined(PORT_OPTIMIZED_RLIST_VAR) */ + +/** + * @brief Scheduler initialization. + * + * @notapi + */ +void _scheduler_init(void) { + + queue_init(&rlist.r_queue); + rlist.r_prio = NOPRIO; +#if CH_TIME_QUANTUM > 0 + rlist.r_preempt = CH_TIME_QUANTUM; +#endif +#if CH_USE_REGISTRY + rlist.r_newer = rlist.r_older = (Thread *)&rlist; +#endif +} + +/** + * @brief Inserts a thread in the Ready List. + * @pre The thread must not be already inserted in any list through its + * @p p_next and @p p_prev or list corruption would occur. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note that + * interrupt handlers always reschedule on exit so an explicit + * reschedule must not be performed in ISRs. + * + * @param[in] tp the thread to be made ready + * @return The thread pointer. + * + * @iclass + */ +#if !defined(PORT_OPTIMIZED_READYI) || defined(__DOXYGEN__) +Thread *chSchReadyI(Thread *tp) { + Thread *cp; + + /* Integrity checks.*/ + chDbgAssert((tp->p_state != THD_STATE_READY) && + (tp->p_state != THD_STATE_FINAL), + "chSchReadyI(), #1", + "invalid state"); + + tp->p_state = THD_STATE_READY; + cp = (Thread *)&rlist.r_queue; + do { + cp = cp->p_next; + } while (cp->p_prio >= tp->p_prio); + /* Insertion on p_prev.*/ + tp->p_next = cp; + tp->p_prev = cp->p_prev; + tp->p_prev->p_next = cp->p_prev = tp; + return tp; +} +#endif /* !defined(PORT_OPTIMIZED_READYI) */ + +/** + * @brief Puts the current thread to sleep into the specified state. + * @details The thread goes into a sleeping state. The possible + * @ref thread_states are defined into @p threads.h. + * + * @param[in] newstate the new thread state + * + * @sclass + */ +#if !defined(PORT_OPTIMIZED_GOSLEEPS) || defined(__DOXYGEN__) +void chSchGoSleepS(tstate_t newstate) { + Thread *otp; + + chDbgCheckClassS(); + + (otp = currp)->p_state = newstate; +#if CH_TIME_QUANTUM > 0 + rlist.r_preempt = CH_TIME_QUANTUM; +#endif + setcurrp(fifo_remove(&rlist.r_queue)); + currp->p_state = THD_STATE_CURRENT; + chSysSwitch(currp, otp); +} +#endif /* !defined(PORT_OPTIMIZED_GOSLEEPS) */ + +#if !defined(PORT_OPTIMIZED_GOSLEEPTIMEOUTS) || defined(__DOXYGEN__) +/* + * Timeout wakeup callback. + */ +static void wakeup(void *p) { + Thread *tp = (Thread *)p; + + switch (tp->p_state) { + case THD_STATE_READY: + /* Handling the special case where the thread has been made ready by + another thread with higher priority.*/ + return; +#if CH_USE_SEMAPHORES || CH_USE_QUEUES || \ + (CH_USE_CONDVARS && CH_USE_CONDVARS_TIMEOUT) +#if CH_USE_SEMAPHORES + case THD_STATE_WTSEM: + chSemFastSignalI((Semaphore *)tp->p_u.wtobjp); + /* Falls into, intentional. */ +#endif +#if CH_USE_QUEUES + case THD_STATE_WTQUEUE: +#endif +#if CH_USE_CONDVARS && CH_USE_CONDVARS_TIMEOUT + case THD_STATE_WTCOND: +#endif + /* States requiring dequeuing.*/ + dequeue(tp); +#endif + } + tp->p_u.rdymsg = RDY_TIMEOUT; + chSchReadyI(tp); +} + +/** + * @brief Puts the current thread to sleep into the specified state with + * timeout specification. + * @details The thread goes into a sleeping state, if it is not awakened + * explicitly within the specified timeout then it is forcibly + * awakened with a @p RDY_TIMEOUT low level message. The possible + * @ref thread_states are defined into @p threads.h. + * + * @param[in] newstate the new thread state + * @param[in] time the number of ticks before the operation timeouts, the + * special values are handled as follow: + * - @a TIME_INFINITE the thread enters an infinite sleep + * state, this is equivalent to invoking + * @p chSchGoSleepS() but, of course, less efficient. + * - @a TIME_IMMEDIATE this value is not allowed. + * . + * @return The wakeup message. + * @retval RDY_TIMEOUT if a timeout occurs. + * + * @sclass + */ +msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t time) { + + chDbgCheckClassS(); + + if (TIME_INFINITE != time) { + VirtualTimer vt; + + chVTSetI(&vt, time, wakeup, currp); + chSchGoSleepS(newstate); + if (chVTIsArmedI(&vt)) + chVTResetI(&vt); + } + else + chSchGoSleepS(newstate); + return currp->p_u.rdymsg; +} +#endif /* !defined(PORT_OPTIMIZED_GOSLEEPTIMEOUTS) */ + +/** + * @brief Wakes up a thread. + * @details The thread is inserted into the ready list or immediately made + * running depending on its relative priority compared to the current + * thread. + * @pre The thread must not be already inserted in any list through its + * @p p_next and @p p_prev or list corruption would occur. + * @note It is equivalent to a @p chSchReadyI() followed by a + * @p chSchRescheduleS() but much more efficient. + * @note The function assumes that the current thread has the highest + * priority. + * + * @param[in] ntp the Thread to be made ready + * @param[in] msg message to the awakened thread + * + * @sclass + */ +#if !defined(PORT_OPTIMIZED_WAKEUPS) || defined(__DOXYGEN__) +void chSchWakeupS(Thread *ntp, msg_t msg) { + + chDbgCheckClassS(); + + ntp->p_u.rdymsg = msg; + /* If the waken thread has a not-greater priority than the current + one then it is just inserted in the ready list else it made + running immediately and the invoking thread goes in the ready + list instead.*/ + if (ntp->p_prio <= currp->p_prio) + chSchReadyI(ntp); + else { + Thread *otp = chSchReadyI(currp); +#if CH_TIME_QUANTUM > 0 + rlist.r_preempt = CH_TIME_QUANTUM; +#endif + setcurrp(ntp); + ntp->p_state = THD_STATE_CURRENT; + chSysSwitch(ntp, otp); + } +} +#endif /* !defined(PORT_OPTIMIZED_WAKEUPS) */ + +/** + * @brief Performs a reschedule if a higher priority thread is runnable. + * @details If a thread with a higher priority than the current thread is in + * the ready list then make the higher priority thread running. + * + * @sclass + */ +#if !defined(PORT_OPTIMIZED_RESCHEDULES) || defined(__DOXYGEN__) +void chSchRescheduleS(void) { + + chDbgCheckClassS(); + + if (chSchIsRescRequiredI()) + chSchDoReschedule(); +} +#endif /* !defined(PORT_OPTIMIZED_RESCHEDULES) */ + +/** + * @brief Evaluates if preemption is required. + * @details The decision is taken by comparing the relative priorities and + * depending on the state of the round robin timeout counter. + * @note Not a user function, it is meant to be invoked by the scheduler + * itself or from within the port layer. + * + * @retval TRUE if there is a thread that must go in running state + * immediately. + * @retval FALSE if preemption is not required. + * + * @special + */ +#if !defined(PORT_OPTIMIZED_ISPREEMPTIONREQUIRED) || defined(__DOXYGEN__) +bool_t chSchIsPreemptionRequired(void) { + tprio_t p1 = firstprio(&rlist.r_queue); + tprio_t p2 = currp->p_prio; +#if CH_TIME_QUANTUM > 0 + /* If the running thread has not reached its time quantum, reschedule only + if the first thread on the ready queue has a higher priority. + Otherwise, if the running thread has used up its time quantum, reschedule + if the first thread on the ready queue has equal or higher priority.*/ + return rlist.r_preempt ? p1 > p2 : p1 >= p2; +#else + /* If the round robin preemption feature is not enabled then performs a + simpler comparison.*/ + return p1 > p2; +#endif +} +#endif /* !defined(PORT_OPTIMIZED_ISPREEMPTIONREQUIRED) */ + +/** + * @brief Switches to the first thread on the runnable queue. + * @note Not a user function, it is meant to be invoked by the scheduler + * itself or from within the port layer. + * + * @special + */ +#if !defined(PORT_OPTIMIZED_DORESCHEDULE) || defined(__DOXYGEN__) +void chSchDoReschedule(void) { + Thread *otp; + +#if CH_TIME_QUANTUM > 0 + rlist.r_preempt = CH_TIME_QUANTUM; +#endif + otp = currp; + /* Picks the first thread from the ready queue and makes it current.*/ + setcurrp(fifo_remove(&rlist.r_queue)); + currp->p_state = THD_STATE_CURRENT; + chSchReadyI(otp); + chSysSwitch(currp, otp); +} +#endif /* !defined(PORT_OPTIMIZED_DORESCHEDULE) */ + +/** @} */ diff --git a/Project/os/kernel/src/chsem.c b/Project/os/kernel/src/chsem.c new file mode 100644 index 0000000..d557080 --- /dev/null +++ b/Project/os/kernel/src/chsem.c @@ -0,0 +1,402 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chsem.c + * @brief Semaphores code. + * + * @addtogroup semaphores + * @details Semaphores related APIs and services. + * + *

Operation mode

+ * Semaphores are a flexible synchronization primitive, ChibiOS/RT + * implements semaphores in their "counting semaphores" variant as + * defined by Edsger Dijkstra plus several enhancements like: + * - Wait operation with timeout. + * - Reset operation. + * - Atomic wait+signal operation. + * - Return message from the wait operation (OK, RESET, TIMEOUT). + * . + * The binary semaphores variant can be easily implemented using + * counting semaphores.
+ * Operations defined for semaphores: + * - Signal: The semaphore counter is increased and if the + * result is non-positive then a waiting thread is removed from + * the semaphore queue and made ready for execution. + * - Wait: The semaphore counter is decreased and if the result + * becomes negative the thread is queued in the semaphore and + * suspended. + * - Reset: The semaphore counter is reset to a non-negative + * value and all the threads in the queue are released. + * . + * Semaphores can be used as guards for mutual exclusion zones + * (note that mutexes are recommended for this kind of use) but + * also have other uses, queues guards and counters for example.
+ * Semaphores usually use a FIFO queuing strategy but it is possible + * to make them order threads by priority by enabling + * @p CH_USE_SEMAPHORES_PRIORITY in @p chconf.h. + * @pre In order to use the semaphore APIs the @p CH_USE_SEMAPHORES + * option must be enabled in @p chconf.h. + * @{ + */ + +#include "ch.h" + +#if CH_USE_SEMAPHORES || defined(__DOXYGEN__) + +#if CH_USE_SEMAPHORES_PRIORITY +#define sem_insert(tp, qp) prio_insert(tp, qp) +#else +#define sem_insert(tp, qp) queue_insert(tp, qp) +#endif + +/** + * @brief Initializes a semaphore with the specified counter value. + * + * @param[out] sp pointer to a @p Semaphore structure + * @param[in] n initial value of the semaphore counter. Must be + * non-negative. + * + * @init + */ +void chSemInit(Semaphore *sp, cnt_t n) { + + chDbgCheck((sp != NULL) && (n >= 0), "chSemInit"); + + queue_init(&sp->s_queue); + sp->s_cnt = n; +} + +/** + * @brief Performs a reset operation on the semaphore. + * @post After invoking this function all the threads waiting on the + * semaphore, if any, are released and the semaphore counter is set + * to the specified, non negative, value. + * @note The released threads can recognize they were waked up by a reset + * rather than a signal because the @p chSemWait() will return + * @p RDY_RESET instead of @p RDY_OK. + * + * @param[in] sp pointer to a @p Semaphore structure + * @param[in] n the new value of the semaphore counter. The value must + * be non-negative. + * + * @api + */ +void chSemReset(Semaphore *sp, cnt_t n) { + + chSysLock(); + chSemResetI(sp, n); + chSchRescheduleS(); + chSysUnlock(); +} + +/** + * @brief Performs a reset operation on the semaphore. + * @post After invoking this function all the threads waiting on the + * semaphore, if any, are released and the semaphore counter is set + * to the specified, non negative, value. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note that + * interrupt handlers always reschedule on exit so an explicit + * reschedule must not be performed in ISRs. + * @note The released threads can recognize they were waked up by a reset + * rather than a signal because the @p chSemWait() will return + * @p RDY_RESET instead of @p RDY_OK. + * + * @param[in] sp pointer to a @p Semaphore structure + * @param[in] n the new value of the semaphore counter. The value must + * be non-negative. + * + * @iclass + */ +void chSemResetI(Semaphore *sp, cnt_t n) { + cnt_t cnt; + + chDbgCheckClassI(); + chDbgCheck((sp != NULL) && (n >= 0), "chSemResetI"); + chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) || + ((sp->s_cnt < 0) && notempty(&sp->s_queue)), + "chSemResetI(), #1", + "inconsistent semaphore"); + + cnt = sp->s_cnt; + sp->s_cnt = n; + while (++cnt <= 0) + chSchReadyI(lifo_remove(&sp->s_queue))->p_u.rdymsg = RDY_RESET; +} + +/** + * @brief Performs a wait operation on a semaphore. + * + * @param[in] sp pointer to a @p Semaphore structure + * @return A message specifying how the invoking thread has been + * released from the semaphore. + * @retval RDY_OK if the thread has not stopped on the semaphore or the + * semaphore has been signaled. + * @retval RDY_RESET if the semaphore has been reset using @p chSemReset(). + * + * @api + */ +msg_t chSemWait(Semaphore *sp) { + msg_t msg; + + chSysLock(); + msg = chSemWaitS(sp); + chSysUnlock(); + return msg; +} + +/** + * @brief Performs a wait operation on a semaphore. + * + * @param[in] sp pointer to a @p Semaphore structure + * @return A message specifying how the invoking thread has been + * released from the semaphore. + * @retval RDY_OK if the thread has not stopped on the semaphore or the + * semaphore has been signaled. + * @retval RDY_RESET if the semaphore has been reset using @p chSemReset(). + * + * @sclass + */ +msg_t chSemWaitS(Semaphore *sp) { + + chDbgCheckClassS(); + chDbgCheck(sp != NULL, "chSemWaitS"); + chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) || + ((sp->s_cnt < 0) && notempty(&sp->s_queue)), + "chSemWaitS(), #1", + "inconsistent semaphore"); + + if (--sp->s_cnt < 0) { + currp->p_u.wtobjp = sp; + sem_insert(currp, &sp->s_queue); + chSchGoSleepS(THD_STATE_WTSEM); + return currp->p_u.rdymsg; + } + return RDY_OK; +} + +/** + * @brief Performs a wait operation on a semaphore with timeout specification. + * + * @param[in] sp pointer to a @p Semaphore structure + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return A message specifying how the invoking thread has been + * released from the semaphore. + * @retval RDY_OK if the thread has not stopped on the semaphore or the + * semaphore has been signaled. + * @retval RDY_RESET if the semaphore has been reset using @p chSemReset(). + * @retval RDY_TIMEOUT if the semaphore has not been signaled or reset within + * the specified timeout. + * + * @api + */ +msg_t chSemWaitTimeout(Semaphore *sp, systime_t time) { + msg_t msg; + + chSysLock(); + msg = chSemWaitTimeoutS(sp, time); + chSysUnlock(); + return msg; +} + +/** + * @brief Performs a wait operation on a semaphore with timeout specification. + * + * @param[in] sp pointer to a @p Semaphore structure + * @param[in] time the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_IMMEDIATE immediate timeout. + * - @a TIME_INFINITE no timeout. + * . + * @return A message specifying how the invoking thread has been + * released from the semaphore. + * @retval RDY_OK if the thread has not stopped on the semaphore or the + * semaphore has been signaled. + * @retval RDY_RESET if the semaphore has been reset using @p chSemReset(). + * @retval RDY_TIMEOUT if the semaphore has not been signaled or reset within + * the specified timeout. + * + * @sclass + */ +msg_t chSemWaitTimeoutS(Semaphore *sp, systime_t time) { + + chDbgCheckClassS(); + chDbgCheck(sp != NULL, "chSemWaitTimeoutS"); + chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) || + ((sp->s_cnt < 0) && notempty(&sp->s_queue)), + "chSemWaitTimeoutS(), #1", + "inconsistent semaphore"); + + if (--sp->s_cnt < 0) { + if (TIME_IMMEDIATE == time) { + sp->s_cnt++; + return RDY_TIMEOUT; + } + currp->p_u.wtobjp = sp; + sem_insert(currp, &sp->s_queue); + return chSchGoSleepTimeoutS(THD_STATE_WTSEM, time); + } + return RDY_OK; +} + +/** + * @brief Performs a signal operation on a semaphore. + * + * @param[in] sp pointer to a @p Semaphore structure + * + * @api + */ +void chSemSignal(Semaphore *sp) { + + chDbgCheck(sp != NULL, "chSemSignal"); + + chSysLock(); + + chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) || + ((sp->s_cnt < 0) && notempty(&sp->s_queue)), + "chSemSignalI(), #1", + "inconsistent semaphore"); + + if (++sp->s_cnt <= 0) + chSchWakeupS(fifo_remove(&sp->s_queue), RDY_OK); + chSysUnlock(); +} + +/** + * @brief Performs a signal operation on a semaphore. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note that + * interrupt handlers always reschedule on exit so an explicit + * reschedule must not be performed in ISRs. + * + * @param[in] sp pointer to a @p Semaphore structure + * + * @iclass + */ +void chSemSignalI(Semaphore *sp) { + + chDbgCheckClassI(); + chDbgCheck(sp != NULL, "chSemSignalI"); + chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) || + ((sp->s_cnt < 0) && notempty(&sp->s_queue)), + "chSemSignalI(), #1", + "inconsistent semaphore"); + + if (++sp->s_cnt <= 0) { + /* note, it is done this way in order to allow a tail call on + chSchReadyI().*/ + Thread *tp = fifo_remove(&sp->s_queue); + tp->p_u.rdymsg = RDY_OK; + chSchReadyI(tp); + } +} + +/** + * @brief Adds the specified value to the semaphore counter. + * @post This function does not reschedule so a call to a rescheduling + * function must be performed before unlocking the kernel. Note that + * interrupt handlers always reschedule on exit so an explicit + * reschedule must not be performed in ISRs. + * + * @param[in] sp pointer to a @p Semaphore structure + * @param[in] n value to be added to the semaphore counter. The value + * must be positive. + * + * @iclass + */ +void chSemAddCounterI(Semaphore *sp, cnt_t n) { + + chDbgCheckClassI(); + chDbgCheck((sp != NULL) && (n > 0), "chSemAddCounterI"); + chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) || + ((sp->s_cnt < 0) && notempty(&sp->s_queue)), + "chSemAddCounterI(), #1", + "inconsistent semaphore"); + + while (n > 0) { + if (++sp->s_cnt <= 0) + chSchReadyI(fifo_remove(&sp->s_queue))->p_u.rdymsg = RDY_OK; + n--; + } +} + +#if CH_USE_SEMSW +/** + * @brief Performs atomic signal and wait operations on two semaphores. + * @pre The configuration option @p CH_USE_SEMSW must be enabled in order + * to use this function. + * + * @param[in] sps pointer to a @p Semaphore structure to be signaled + * @param[in] spw pointer to a @p Semaphore structure to be wait on + * @return A message specifying how the invoking thread has been + * released from the semaphore. + * @retval RDY_OK if the thread has not stopped on the semaphore or the + * semaphore has been signaled. + * @retval RDY_RESET if the semaphore has been reset using @p chSemReset(). + * + * @api + */ +msg_t chSemSignalWait(Semaphore *sps, Semaphore *spw) { + msg_t msg; + + chDbgCheck((sps != NULL) && (spw != NULL), "chSemSignalWait"); + chDbgAssert(((sps->s_cnt >= 0) && isempty(&sps->s_queue)) || + ((sps->s_cnt < 0) && notempty(&sps->s_queue)), + "chSemSignalWait(), #1", + "inconsistent semaphore"); + chDbgAssert(((spw->s_cnt >= 0) && isempty(&spw->s_queue)) || + ((spw->s_cnt < 0) && notempty(&spw->s_queue)), + "chSemSignalWait(), #2", + "inconsistent semaphore"); + + chSysLock(); + if (++sps->s_cnt <= 0) + chSchReadyI(fifo_remove(&sps->s_queue))->p_u.rdymsg = RDY_OK; + if (--spw->s_cnt < 0) { + Thread *ctp = currp; + sem_insert(ctp, &spw->s_queue); + ctp->p_u.wtobjp = spw; + chSchGoSleepS(THD_STATE_WTSEM); + msg = ctp->p_u.rdymsg; + } + else { + chSchRescheduleS(); + msg = RDY_OK; + } + chSysUnlock(); + return msg; +} +#endif /* CH_USE_SEMSW */ + +#endif /* CH_USE_SEMAPHORES */ + +/** @} */ diff --git a/Project/os/kernel/src/chsys.c b/Project/os/kernel/src/chsys.c new file mode 100644 index 0000000..2314d78 --- /dev/null +++ b/Project/os/kernel/src/chsys.c @@ -0,0 +1,156 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chsys.c + * @brief System related code. + * + * @addtogroup system + * @details System related APIs and services: + * - Initialization. + * - Locks. + * - Interrupt Handling. + * - Power Management. + * - Abnormal Termination. + * . + * @{ + */ + +#include "ch.h" + +#if !CH_NO_IDLE_THREAD || defined(__DOXYGEN__) +/** + * @brief Idle thread working area. + */ +WORKING_AREA(_idle_thread_wa, PORT_IDLE_THREAD_STACK_SIZE); + +/** + * @brief This function implements the idle thread infinite loop. + * @details The function puts the processor in the lowest power mode capable + * to serve interrupts.
+ * The priority is internally set to the minimum system value so + * that this thread is executed only if there are no other ready + * threads in the system. + * + * @param[in] p the thread parameter, unused in this scenario + */ +void _idle_thread(void *p) { + + (void)p; + chRegSetThreadName("idle"); + while (TRUE) { + port_wait_for_interrupt(); + IDLE_LOOP_HOOK(); + } +} +#endif /* CH_NO_IDLE_THREAD */ + +/** + * @brief ChibiOS/RT initialization. + * @details After executing this function the current instructions stream + * becomes the main thread. + * @pre Interrupts must be still disabled when @p chSysInit() is invoked + * and are internally enabled. + * @post The main thread is created with priority @p NORMALPRIO. + * @note This function has special, architecture-dependent, requirements, + * see the notes into the various port reference manuals. + * + * @special + */ +void chSysInit(void) { + static Thread mainthread; +#if CH_DBG_ENABLE_STACK_CHECK + extern stkalign_t __main_thread_stack_base__; +#endif + + port_init(); + _scheduler_init(); + _vt_init(); +#if CH_USE_MEMCORE + _core_init(); +#endif +#if CH_USE_HEAP + _heap_init(); +#endif +#if CH_DBG_ENABLE_TRACE + _trace_init(); +#endif + + /* Now this instructions flow becomes the main thread.*/ + setcurrp(_thread_init(&mainthread, NORMALPRIO)); + currp->p_state = THD_STATE_CURRENT; +#if CH_DBG_ENABLE_STACK_CHECK + /* This is a special case because the main thread Thread structure is not + adjacent to its stack area.*/ + currp->p_stklimit = &__main_thread_stack_base__; +#endif + chSysEnable(); + + /* Note, &ch_debug points to the string "main" if the registry is + active, else the parameter is ignored.*/ + chRegSetThreadName((const char *)&ch_debug); + +#if !CH_NO_IDLE_THREAD + /* This thread has the lowest priority in the system, its role is just to + serve interrupts in its context while keeping the lowest energy saving + mode compatible with the system status.*/ + chThdCreateStatic(_idle_thread_wa, sizeof(_idle_thread_wa), IDLEPRIO, + (tfunc_t)_idle_thread, NULL); +#endif +} + +/** + * @brief Handles time ticks for round robin preemption and timer increments. + * @details Decrements the remaining time quantum of the running thread + * and preempts it when the quantum is used up. Increments system + * time and manages the timers. + * @note The frequency of the timer determines the system tick granularity + * and, together with the @p CH_TIME_QUANTUM macro, the round robin + * interval. + * + * @iclass + */ +void chSysTimerHandlerI(void) { + + chDbgCheckClassI(); + +#if CH_TIME_QUANTUM > 0 + /* Running thread has not used up quantum yet? */ + if (rlist.r_preempt > 0) + /* Decrement remaining quantum.*/ + rlist.r_preempt--; +#endif +#if CH_DBG_THREADS_PROFILING + currp->p_time++; +#endif + chVTDoTickI(); +#if defined(SYSTEM_TICK_EVENT_HOOK) + SYSTEM_TICK_EVENT_HOOK(); +#endif +} + +/** @} */ diff --git a/Project/os/kernel/src/chthreads.c b/Project/os/kernel/src/chthreads.c new file mode 100644 index 0000000..fa63d75 --- /dev/null +++ b/Project/os/kernel/src/chthreads.c @@ -0,0 +1,440 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chthreads.c + * @brief Threads code. + * + * @addtogroup threads + * @details Threads related APIs and services. + * + *

Operation mode

+ * A thread is an abstraction of an independent instructions flow. + * In ChibiOS/RT a thread is represented by a "C" function owning + * a processor context, state informations and a dedicated stack + * area. In this scenario static variables are shared among all + * threads while automatic variables are local to the thread.
+ * Operations defined for threads: + * - Create, a thread is started on the specified thread + * function. This operation is available in multiple variants, + * both static and dynamic. + * - Exit, a thread terminates by returning from its top + * level function or invoking a specific API, the thread can + * return a value that can be retrieved by other threads. + * - Wait, a thread waits for the termination of another + * thread and retrieves its return value. + * - Resume, a thread created in suspended state is started. + * - Sleep, the execution of a thread is suspended for the + * specified amount of time or the specified future absolute time + * is reached. + * - SetPriority, a thread changes its own priority level. + * - Yield, a thread voluntarily renounces to its time slot. + * . + * The threads subsystem is implicitly included in kernel however + * some of its part may be excluded by disabling them in @p chconf.h, + * see the @p CH_USE_WAITEXIT and @p CH_USE_DYNAMIC configuration + * options. + * @{ + */ + +#include "ch.h" + +/** + * @brief Initializes a thread structure. + * @note This is an internal functions, do not use it in application code. + * + * @param[in] tp pointer to the thread + * @param[in] prio the priority level for the new thread + * @return The same thread pointer passed as parameter. + * + * @notapi + */ +Thread *_thread_init(Thread *tp, tprio_t prio) { + + tp->p_prio = prio; + tp->p_state = THD_STATE_SUSPENDED; + tp->p_flags = THD_MEM_MODE_STATIC; +#if CH_USE_MUTEXES + tp->p_realprio = prio; + tp->p_mtxlist = NULL; +#endif +#if CH_USE_EVENTS + tp->p_epending = 0; +#endif +#if CH_DBG_THREADS_PROFILING + tp->p_time = 0; +#endif +#if CH_USE_DYNAMIC + tp->p_refs = 1; +#endif +#if CH_USE_REGISTRY + tp->p_name = NULL; + REG_INSERT(tp); +#endif +#if CH_USE_WAITEXIT + list_init(&tp->p_waiting); +#endif +#if CH_USE_MESSAGES + queue_init(&tp->p_msgqueue); +#endif +#if CH_DBG_ENABLE_STACK_CHECK + tp->p_stklimit = (stkalign_t *)(tp + 1); +#endif +#if defined(THREAD_EXT_INIT_HOOK) + THREAD_EXT_INIT_HOOK(tp); +#endif + return tp; +} + +#if CH_DBG_FILL_THREADS || defined(__DOXYGEN__) +/** + * @brief Memory fill utility. + * + * @param[in] startp first address to fill + * @param[in] endp last address to fill +1 + * @param[in] v filler value + * + * @notapi + */ +void _thread_memfill(uint8_t *startp, uint8_t *endp, uint8_t v) { + + while (startp < endp) + *startp++ = v; +} +#endif /* CH_DBG_FILL_THREADS */ + +/** + * @brief Creates a new thread into a static memory area. + * @details The new thread is initialized but not inserted in the ready list, + * the initial state is @p THD_STATE_SUSPENDED. + * @post The initialized thread can be subsequently started by invoking + * @p chThdResume(), @p chThdResumeI() or @p chSchWakeupS() + * depending on the execution context. + * @note A thread can terminate by calling @p chThdExit() or by simply + * returning from its main function. + * @note Threads created using this function do not obey to the + * @p CH_DBG_FILL_THREADS debug option because it would keep + * the kernel locked for too much time. + * + * @param[out] wsp pointer to a working area dedicated to the thread stack + * @param[in] size size of the working area + * @param[in] prio the priority level for the new thread + * @param[in] pf the thread function + * @param[in] arg an argument passed to the thread function. It can be + * @p NULL. + * @return The pointer to the @p Thread structure allocated for + * the thread into the working space area. + * + * @iclass + */ +Thread *chThdCreateI(void *wsp, size_t size, + tprio_t prio, tfunc_t pf, void *arg) { + /* Thread structure is laid out in the lower part of the thread workspace.*/ + Thread *tp = wsp; + + chDbgCheckClassI(); + + chDbgCheck((wsp != NULL) && (size >= THD_WA_SIZE(0)) && + (prio <= HIGHPRIO) && (pf != NULL), + "chThdCreateI"); + SETUP_CONTEXT(wsp, size, pf, arg); + return _thread_init(tp, prio); +} + +/** + * @brief Creates a new thread into a static memory area. + * @note A thread can terminate by calling @p chThdExit() or by simply + * returning from its main function. + * + * @param[out] wsp pointer to a working area dedicated to the thread stack + * @param[in] size size of the working area + * @param[in] prio the priority level for the new thread + * @param[in] pf the thread function + * @param[in] arg an argument passed to the thread function. It can be + * @p NULL. + * @return The pointer to the @p Thread structure allocated for + * the thread into the working space area. + * + * @api + */ +Thread *chThdCreateStatic(void *wsp, size_t size, + tprio_t prio, tfunc_t pf, void *arg) { + Thread *tp; + +#if CH_DBG_FILL_THREADS + _thread_memfill((uint8_t *)wsp, + (uint8_t *)wsp + sizeof(Thread), + CH_THREAD_FILL_VALUE); + _thread_memfill((uint8_t *)wsp + sizeof(Thread), + (uint8_t *)wsp + size, + CH_STACK_FILL_VALUE); +#endif + chSysLock(); + chSchWakeupS(tp = chThdCreateI(wsp, size, prio, pf, arg), RDY_OK); + chSysUnlock(); + return tp; +} + +/** + * @brief Changes the running thread priority level then reschedules if + * necessary. + * @note The function returns the real thread priority regardless of the + * current priority that could be higher than the real priority + * because the priority inheritance mechanism. + * + * @param[in] newprio the new priority level of the running thread + * @return The old priority level. + * + * @api + */ +tprio_t chThdSetPriority(tprio_t newprio) { + tprio_t oldprio; + + chDbgCheck(newprio <= ABSPRIO, "chThdSetPriority"); + + chSysLock(); +#if CH_USE_MUTEXES + oldprio = currp->p_realprio; + if ((currp->p_prio == currp->p_realprio) || (newprio > currp->p_prio)) + currp->p_prio = newprio; + currp->p_realprio = newprio; +#else + oldprio = currp->p_prio; + currp->p_prio = newprio; +#endif + chSchRescheduleS(); + chSysUnlock(); + return oldprio; +} + +/** + * @brief Resumes a suspended thread. + * @pre The specified thread pointer must refer to an initialized thread + * in the @p THD_STATE_SUSPENDED state. + * @post The specified thread is immediately started or put in the ready + * list depending on the relative priority levels. + * @note Use this function to start threads created with @p chThdInit(). + * + * @param[in] tp pointer to the thread + * @return The pointer to the thread. + * + * @api + */ +Thread *chThdResume(Thread *tp) { + + chSysLock(); + chDbgAssert(tp->p_state == THD_STATE_SUSPENDED, + "chThdResume(), #1", + "thread not in THD_STATE_SUSPENDED state"); + chSchWakeupS(tp, RDY_OK); + chSysUnlock(); + return tp; +} + +/** + * @brief Requests a thread termination. + * @pre The target thread must be written to invoke periodically + * @p chThdShouldTerminate() and terminate cleanly if it returns + * @p TRUE. + * @post The specified thread will terminate after detecting the termination + * condition. + * + * @param[in] tp pointer to the thread + * + * @api + */ +void chThdTerminate(Thread *tp) { + + chSysLock(); + tp->p_flags |= THD_TERMINATE; + chSysUnlock(); +} + +/** + * @brief Suspends the invoking thread for the specified time. + * + * @param[in] time the delay in system ticks, the special values are + * handled as follow: + * - @a TIME_INFINITE the thread enters an infinite sleep + * state. + * - @a TIME_IMMEDIATE this value is not allowed. + * . + * + * @api + */ +void chThdSleep(systime_t time) { + + chDbgCheck(time != TIME_IMMEDIATE, "chThdSleep"); + + chSysLock(); + chThdSleepS(time); + chSysUnlock(); +} + +/** + * @brief Suspends the invoking thread until the system time arrives to the + * specified value. + * + * @param[in] time absolute system time + * + * @api + */ +void chThdSleepUntil(systime_t time) { + + chSysLock(); + if ((time -= chTimeNow()) > 0) + chThdSleepS(time); + chSysUnlock(); +} + +/** + * @brief Yields the time slot. + * @details Yields the CPU control to the next thread in the ready list with + * equal priority, if any. + * + * @api + */ +void chThdYield(void) { + + chSysLock(); + chSchDoYieldS(); + chSysUnlock(); +} + +/** + * @brief Terminates the current thread. + * @details The thread goes in the @p THD_STATE_FINAL state holding the + * specified exit status code, other threads can retrieve the + * exit status code by invoking the function @p chThdWait(). + * @post Eventual code after this function will never be executed, + * this function never returns. The compiler has no way to + * know this so do not assume that the compiler would remove + * the dead code. + * + * @param[in] msg thread exit code + * + * @api + */ +void chThdExit(msg_t msg) { + + chSysLock(); + chThdExitS(msg); + /* The thread never returns here.*/ +} + +/** + * @brief Terminates the current thread. + * @details The thread goes in the @p THD_STATE_FINAL state holding the + * specified exit status code, other threads can retrieve the + * exit status code by invoking the function @p chThdWait(). + * @post Eventual code after this function will never be executed, + * this function never returns. The compiler has no way to + * know this so do not assume that the compiler would remove + * the dead code. + * + * @param[in] msg thread exit code + * + * @sclass + */ +void chThdExitS(msg_t msg) { + Thread *tp = currp; + + tp->p_u.exitcode = msg; +#if defined(THREAD_EXT_EXIT_HOOK) + THREAD_EXT_EXIT_HOOK(tp); +#endif +#if CH_USE_WAITEXIT + while (notempty(&tp->p_waiting)) + chSchReadyI(list_remove(&tp->p_waiting)); +#endif +#if CH_USE_REGISTRY + /* Static threads are immediately removed from the registry because + there is no memory to recover.*/ + if ((tp->p_flags & THD_MEM_MODE_MASK) == THD_MEM_MODE_STATIC) + REG_REMOVE(tp); +#endif + chSchGoSleepS(THD_STATE_FINAL); + /* The thread never returns here.*/ + chDbgAssert(FALSE, "chThdExitS(), #1", "zombies apocalypse"); +} + +#if CH_USE_WAITEXIT || defined(__DOXYGEN__) +/** + * @brief Blocks the execution of the invoking thread until the specified + * thread terminates then the exit code is returned. + * @details This function waits for the specified thread to terminate then + * decrements its reference counter, if the counter reaches zero then + * the thread working area is returned to the proper allocator.
+ * The memory used by the exited thread is handled in different ways + * depending on the API that spawned the thread: + * - If the thread was spawned by @p chThdCreateStatic() or by + * @p chThdInit() then nothing happens and the thread working area + * is not released or modified in any way. This is the default, + * totally static, behavior. + * - If the thread was spawned by @p chThdCreateFromHeap() then + * the working area is returned to the system heap. + * - If the thread was spawned by @p chThdCreateFromMemoryPool() + * then the working area is returned to the owning memory pool. + * . + * @pre The configuration option @p CH_USE_WAITEXIT must be enabled in + * order to use this function. + * @post Enabling @p chThdWait() requires 2-4 (depending on the + * architecture) extra bytes in the @p Thread structure. + * @post After invoking @p chThdWait() the thread pointer becomes invalid + * and must not be used as parameter for further system calls. + * @note If @p CH_USE_DYNAMIC is not specified this function just waits for + * the thread termination, no memory allocators are involved. + * + * @param[in] tp pointer to the thread + * @return The exit code from the terminated thread. + * + * @api + */ +msg_t chThdWait(Thread *tp) { + msg_t msg; + + chDbgCheck(tp != NULL, "chThdWait"); + + chSysLock(); + chDbgAssert(tp != currp, "chThdWait(), #1", "waiting self"); +#if CH_USE_DYNAMIC + chDbgAssert(tp->p_refs > 0, "chThdWait(), #2", "not referenced"); +#endif + if (tp->p_state != THD_STATE_FINAL) { + list_insert(currp, &tp->p_waiting); + chSchGoSleepS(THD_STATE_WTEXIT); + } + msg = tp->p_u.exitcode; + chSysUnlock(); +#if CH_USE_DYNAMIC + chThdRelease(tp); +#endif + return msg; +} +#endif /* CH_USE_WAITEXIT */ + +/** @} */ diff --git a/Project/os/kernel/src/chvt.c b/Project/os/kernel/src/chvt.c new file mode 100644 index 0000000..fc33048 --- /dev/null +++ b/Project/os/kernel/src/chvt.c @@ -0,0 +1,142 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chvt.c + * @brief Time and Virtual Timers related code. + * + * @addtogroup time + * @details Time and Virtual Timers related APIs and services. + * @{ + */ + +#include "ch.h" + +/** + * @brief Virtual timers delta list header. + */ +VTList vtlist; + +/** + * @brief Virtual Timers initialization. + * @note Internal use only. + * + * @notapi + */ +void _vt_init(void) { + + vtlist.vt_next = vtlist.vt_prev = (void *)&vtlist; + vtlist.vt_time = (systime_t)-1; + vtlist.vt_systime = 0; +} + +/** + * @brief Enables a virtual timer. + * @note The associated function is invoked by an interrupt handler within + * the I-Locked state, see @ref system_states. + * + * @param[out] vtp the @p VirtualTimer structure pointer + * @param[in] time the number of ticks before the operation timeouts, the + * special values are handled as follow: + * - @a TIME_INFINITE is allowed but interpreted as a + * normal time specification. + * - @a TIME_IMMEDIATE this value is not allowed. + * . + * @param[in] vtfunc the timer callback function. After invoking the + * callback the timer is disabled and the structure can + * be disposed or reused. + * @param[in] par a parameter that will be passed to the callback + * function + * + * @iclass + */ +void chVTSetI(VirtualTimer *vtp, systime_t time, vtfunc_t vtfunc, void *par) { + VirtualTimer *p; + + chDbgCheckClassI(); + chDbgCheck((vtp != NULL) && (vtfunc != NULL) && (time != TIME_IMMEDIATE), + "chVTSetI"); + + vtp->vt_par = par; + vtp->vt_func = vtfunc; + p = vtlist.vt_next; + while (p->vt_time < time) { + time -= p->vt_time; + p = p->vt_next; + } + + vtp->vt_prev = (vtp->vt_next = p)->vt_prev; + vtp->vt_prev->vt_next = p->vt_prev = vtp; + vtp->vt_time = time; + if (p != (void *)&vtlist) + p->vt_time -= time; +} + +/** + * @brief Disables a Virtual Timer. + * @note The timer MUST be active when this function is invoked. + * + * @param[in] vtp the @p VirtualTimer structure pointer + * + * @iclass + */ +void chVTResetI(VirtualTimer *vtp) { + + chDbgCheckClassI(); + chDbgCheck(vtp != NULL, "chVTResetI"); + chDbgAssert(vtp->vt_func != NULL, + "chVTResetI(), #1", + "timer not set or already triggered"); + + if (vtp->vt_next != (void *)&vtlist) + vtp->vt_next->vt_time += vtp->vt_time; + vtp->vt_prev->vt_next = vtp->vt_next; + vtp->vt_next->vt_prev = vtp->vt_prev; + vtp->vt_func = (vtfunc_t)NULL; +} + +/** + * @brief Checks if the current system time is within the specified time + * window. + * @note When start==end then the function returns always true because the + * whole time range is specified. + * + * @param[in] start the start of the time window (inclusive) + * @param[in] end the end of the time window (non inclusive) + * @retval TRUE current time within the specified time window. + * @retval FALSE current time not within the specified time window. + * + * @api + */ +bool_t chTimeIsWithin(systime_t start, systime_t end) { + + systime_t time = chTimeNow(); + return end > start ? (time >= start) && (time < end) : + (time >= start) || (time < end); +} + +/** @} */ diff --git a/Project/os/kernel/templates/chconf.h b/Project/os/kernel/templates/chconf.h new file mode 100644 index 0000000..cc866e3 --- /dev/null +++ b/Project/os/kernel/templates/chconf.h @@ -0,0 +1,542 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/Project/os/kernel/templates/chcore.c b/Project/os/kernel/templates/chcore.c new file mode 100644 index 0000000..9039e74 --- /dev/null +++ b/Project/os/kernel/templates/chcore.c @@ -0,0 +1,141 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* * <-disabled + * @file templates/chcore.c + * @brief Port related template code. + * @details This file is a template of the system driver functions provided by + * a port. Some of the following functions may be implemented as + * macros in chcore.h if the implementer decides that there is an + * advantage in doing so, for example because performance concerns. + * + * @addtogroup core + * @details Non portable code templates. + * @{ + */ + +#include "ch.h" + +/** + * @brief Port-related initialization code. + * @note This function is usually empty. + */ +void port_init(void) { +} + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform more + * actions. + */ +void port_lock(void) { +} + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform more + * actions. + */ +void port_unlock(void) { +} + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + */ +void port_lock_from_isr(void) { +} + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + */ +void port_unlock_from_isr(void) { +} + +/** + * @brief Disables all the interrupt sources. + * @note Of course non-maskable interrupt sources are not included. + */ +void port_disable(void) { +} + +/** + * @brief Disables the interrupt sources below kernel-level priority. + * @note Interrupt sources above kernel level remains enabled. + */ +void port_suspend(void) { +} + +/** + * @brief Enables all the interrupt sources. + */ +void port_enable(void) { +} + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + */ +void port_wait_for_interrupt(void) { +} + +/** + * @brief Halts the system. + * @details This function is invoked by the operating system when an + * unrecoverable error is detected (for example because a programming + * error in the application code that triggers an assertion while in + * debug mode). + */ +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +void port_switch(Thread *ntp, Thread *otp) { +} + +/** @} */ diff --git a/Project/os/kernel/templates/chcore.h b/Project/os/kernel/templates/chcore.h new file mode 100644 index 0000000..3da96c0 --- /dev/null +++ b/Project/os/kernel/templates/chcore.h @@ -0,0 +1,220 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* * <-disabled + * @file templates/chcore.h + * @brief Port related template macros and structures. + * @details This file is a template of the system driver macros provided by + * a port. + * + * @addtogroup core + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +/*===========================================================================*/ +/* Port constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + */ +#ifndef PORT_IDLE_THREAD_STACK_SIZE +#define PORT_IDLE_THREAD_STACK_SIZE 0 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * This value can be zero on those architecture where there is a + * separate interrupt stack and the stack space between @p intctx and + * @p extctx is known to be zero. + */ +#ifndef PORT_INT_REQUIRED_STACK +#define PORT_INT_REQUIRED_STACK 0 +#endif + +/*===========================================================================*/ +/* Port derived parameters. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +/** + * @brief Unique macro for the implemented architecture. + */ +#define CH_ARCHITECTURE_XXX + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "" + +/** + * @brief Name of the architecture variant (optional). + */ +#define CH_ARCHITECTURE_VARIANT_NAME "" + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "GCC" + +/** + * @brief Port-specific information string. + */ +#define CH_PORT_INFO "" + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +/** + * @brief Base type for stack and memory alignment. + */ +typedef uint8_t stkalign_t; + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + */ +struct extctx { +}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching. + */ +struct intctx { +}; + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details This structure usually contains just the saved stack pointer + * defined as a pointer to a @p intctx structure. + */ +struct context { + struct intctx *sp; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ +} + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + * @note Not all architectures support fast interrupts, in this case this + * macro must be omitted. + */ +#define PORT_FAST_IRQ_HANDLER(id) void id(void) + +#ifdef __cplusplus +extern "C" { +#endif + void port_init(void); + void port_lock(void); + void port_unlock(void); + void port_lock_from_isr(void); + void port_unlock_from_isr(void); + void port_disable(void); + void port_suspend(void); + void port_enable(void); + void port_wait_for_interrupt(void); + void port_halt(void); + void port_switch(Thread *ntp, Thread *otp); +#ifdef __cplusplus +} +#endif + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/Project/os/kernel/templates/chtypes.h b/Project/os/kernel/templates/chtypes.h new file mode 100644 index 0000000..3708cd5 --- /dev/null +++ b/Project/os/kernel/templates/chtypes.h @@ -0,0 +1,137 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file templates/chtypes.h + * @brief System types template. + * @details The types defined in this file may change depending on the target + * architecture. You may also try to optimize the size of the various + * types in order to privilege size or performance, be careful in + * doing so. + * + * @addtogroup types + * @details System types and macros. + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#define __need_NULL +#define __need_size_t +#include + +#if !defined(_STDINT_H) && !defined(__STDINT_H_) +#include +#endif + +/** + * @brief Boolean, recommended the fastest signed. + */ +typedef int32_t bool_t; + +/** + * @brief Thread mode flags, uint8_t is ok. + */ +typedef uint8_t tmode_t; + +/** + * @brief Thread state, uint8_t is ok. + */ +typedef uint8_t tstate_t; + +/** + * @brief Thread references counter, uint8_t is ok. + */ +typedef uint8_t trefs_t; + +/** + * @brief Priority, use the fastest unsigned type. + */ +typedef uint32_t tprio_t; + +/** + * @brief Message, use signed pointer equivalent. + */ +typedef int32_t msg_t; + +/** + * @brief Event Id, use fastest signed. + */ +typedef int32_t eventid_t; + +/** + * @brief Event Mask, recommended fastest unsigned. + */ +typedef uint32_t eventmask_t; + +/** + * @brief System Time, recommended fastest unsigned. + */ +typedef uint32_t systime_t; + +/** + * @brief Counter, recommended fastest signed. + */ +typedef int32_t cnt_t; + +/** + * @brief Inline function modifier. + */ +#define INLINE inline + +/** + * @brief ROM constant modifier. + * @note This is required because some compilers require a custom keyword, + * usually this macro is just set to "const" for the GCC compiler. + * @note This macro is not used to place constants in different address + * spaces (like AVR requires for example) because it is assumed that + * a pointer to a ROMCONST constant is compatible with a pointer + * to a normal variable. It is just like the "const" keyword but + * requires that the constant is placed in ROM if the architecture + * supports it. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + */ +#define PACK_STRUCT_STRUCT __attribute__((packed)) + +/** + * @brief Packed structure modifier (before). + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/ARM/AT91SAM7/armparams.h b/Project/os/ports/GCC/ARM/AT91SAM7/armparams.h new file mode 100644 index 0000000..39a936d --- /dev/null +++ b/Project/os/ports/GCC/ARM/AT91SAM7/armparams.h @@ -0,0 +1,63 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file ARM/AT91SAM7/armparams.h + * @brief ARM7 AT91SAM7 Specific Parameters. + * + * @defgroup ARM_AT91SAM7 AT91SAM7 Specific Parameters + * @ingroup ARM_SPECIFIC + * @details This file contains the ARM specific parameters for the + * AT91SAM7 platform. + * @{ + */ + +#ifndef _ARMPARAMS_H_ +#define _ARMPARAMS_H_ + +/** + * @brief ARM core model. + */ +#define ARM_CORE ARM_CORE_ARM7TDMI + +/** + * @brief AT91SAM7-specific wait for interrupt. + * @details This implementation writes 1 into the PMC_SCDR register. + */ +#if !defined(port_wait_for_interrupt) || defined(__DOXYGEN__) +#if ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() { \ + (*((volatile uint32_t *)0xFFFFFC04)) = 1; \ +} +#else +#define port_wait_for_interrupt() +#endif +#endif + +#endif /* _ARMPARAMS_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7S256.ld b/Project/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7S256.ld new file mode 100644 index 0000000..f643781 --- /dev/null +++ b/Project/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7S256.ld @@ -0,0 +1,112 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * AT91SAM7S256 memory setup. + */ +__und_stack_size__ = 0x0004; +__abt_stack_size__ = 0x0004; +__fiq_stack_size__ = 0x0010; +__irq_stack_size__ = 0x0080; +__svc_stack_size__ = 0x0004; +__sys_stack_size__ = 0x0400; +__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; + +MEMORY +{ + flash : org = 0x100000, len = 256k + ram : org = 0x200020, len = 64k - 0x20 +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(16) SUBALIGN(16) + { + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.ctors) + *(.dtors) + } > flash + + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; +__main_thread_stack_base__ = __ram_end__ - __stacks_total_size__; diff --git a/Project/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7X256.ld b/Project/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7X256.ld new file mode 100644 index 0000000..9d0ae7a --- /dev/null +++ b/Project/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7X256.ld @@ -0,0 +1,112 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * AT91SAM7X256 memory setup. + */ +__und_stack_size__ = 0x0004; +__abt_stack_size__ = 0x0004; +__fiq_stack_size__ = 0x0010; +__irq_stack_size__ = 0x0080; +__svc_stack_size__ = 0x0004; +__sys_stack_size__ = 0x0400; +__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; + +MEMORY +{ + flash : org = 0x100000, len = 256k + ram : org = 0x200020, len = 64k - 0x20 +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(16) SUBALIGN(16) + { + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.ctors) + *(.dtors) + } > flash + + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; +__main_thread_stack_base__ = __ram_end__ - __stacks_total_size__; diff --git a/Project/os/ports/GCC/ARM/AT91SAM7/port.mk b/Project/os/ports/GCC/ARM/AT91SAM7/port.mk new file mode 100644 index 0000000..2cafd01 --- /dev/null +++ b/Project/os/ports/GCC/ARM/AT91SAM7/port.mk @@ -0,0 +1,11 @@ +# List of the ChibiOS/RT ARM7 AT91SAM7 port files. +PORTSRC = ${CHIBIOS}/os/ports/GCC/ARM/chcore.c + +PORTASM = ${CHIBIOS}/os/ports/GCC/ARM/crt0.s \ + ${CHIBIOS}/os/ports/GCC/ARM/chcoreasm.s \ + ${CHIBIOS}/os/ports/GCC/ARM/AT91SAM7/vectors.s + +PORTINC = ${CHIBIOS}/os/ports/GCC/ARM \ + ${CHIBIOS}/os/ports/GCC/ARM/AT91SAM7 + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARM/AT91SAM7/ld diff --git a/Project/os/ports/GCC/ARM/AT91SAM7/vectors.s b/Project/os/ports/GCC/ARM/AT91SAM7/vectors.s new file mode 100644 index 0000000..ac7d3d7 --- /dev/null +++ b/Project/os/ports/GCC/ARM/AT91SAM7/vectors.s @@ -0,0 +1,111 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file ARM/AT91SAM7/vectors.s + * @brief Interrupt vectors for the AT91SAM7 family. + * + * @defgroup ARM_AT91SAM7_VECTORS AT91SAM7 Interrupt Vectors + * @ingroup ARM_SPECIFIC + * @details Interrupt vectors for the AT91SAM7 family. + * @{ + */ + +#if defined(__DOXYGEN__) +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +void _unhandled_exception(void) {} +#endif + +#if !defined(__DOXYGEN__) + +.section vectors +.code 32 +.balign 4 +/* + * System entry points. + */ +_start: + ldr pc, _reset + ldr pc, _undefined + ldr pc, _swi + ldr pc, _prefetch + ldr pc, _abort + nop + ldr pc, [pc,#-0xF20] /* AIC - AIC_IVR */ + ldr pc, [pc,#-0xF20] /* AIC - AIC_FVR */ + +_reset: + .word ResetHandler /* In crt0.s */ +_undefined: + .word UndHandler +_swi: + .word SwiHandler +_prefetch: + .word PrefetchHandler +_abort: + .word AbortHandler + .word 0 + .word 0 + .word 0 + +.text +.code 32 +.balign 4 + +/* + * Default exceptions handlers. The handlers are declared weak in order to be + * replaced by the real handling code. Everything is defaulted to an infinite + * loop. + */ +.weak UndHandler +UndHandler: + +.weak SwiHandler +SwiHandler: + +.weak PrefetchHandler +PrefetchHandler: + +.weak AbortHandler +AbortHandler: + +.weak FiqHandler +FiqHandler: + +.global _unhandled_exception +_unhandled_exception: + b _unhandled_exception + +#endif + +/** @} */ diff --git a/Project/os/ports/GCC/ARM/AT91SAM7/wfi.h b/Project/os/ports/GCC/ARM/AT91SAM7/wfi.h new file mode 100644 index 0000000..d32ddc3 --- /dev/null +++ b/Project/os/ports/GCC/ARM/AT91SAM7/wfi.h @@ -0,0 +1,43 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +#ifndef _WFI_H_ +#define _WFI_H_ + +#include "board.h" + +#ifndef port_wait_for_interrupt +#if ENABLE_WFI_IDLE != 0 +#define port_wait_for_interrupt() { \ + AT91C_BASE_SYS->PMC_SCDR = AT91C_PMC_PCK; \ +} +#else +#define port_wait_for_interrupt() +#endif +#endif + +#endif /* _WFI_H_ */ diff --git a/Project/os/ports/GCC/ARM/LPC214x/armparams.h b/Project/os/ports/GCC/ARM/LPC214x/armparams.h new file mode 100644 index 0000000..d9e3138 --- /dev/null +++ b/Project/os/ports/GCC/ARM/LPC214x/armparams.h @@ -0,0 +1,63 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file ARM/LPC214x/armparams.h + * @brief ARM7 LPC214x Specific Parameters. + * + * @defgroup ARM_LPC214x LPC214x Specific Parameters + * @ingroup ARM_SPECIFIC + * @details This file contains the ARM specific parameters for the + * LPC214x platform. + * @{ + */ + +#ifndef _ARMPARAMS_H_ +#define _ARMPARAMS_H_ + +/** + * @brief ARM core model. + */ +#define ARM_CORE ARM_CORE_ARM7TDMI + +/** + * @brief LPC214x-specific wait for interrupt code. + * @details This implementation writes 1 into the PCON register. + */ +#if !defined(port_wait_for_interrupt) || defined(__DOXYGEN__) +#if ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() { \ + (*((volatile uint32_t *)0xE01FC0C0)) = 1; \ +} +#else +#define port_wait_for_interrupt() +#endif +#endif + +#endif /* _ARMPARAMS_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/ARM/LPC214x/ld/LPC2148.ld b/Project/os/ports/GCC/ARM/LPC214x/ld/LPC2148.ld new file mode 100644 index 0000000..be45faa --- /dev/null +++ b/Project/os/ports/GCC/ARM/LPC214x/ld/LPC2148.ld @@ -0,0 +1,115 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * LPC2148 memory setup. + */ +__und_stack_size__ = 0x0004; +__abt_stack_size__ = 0x0004; +__fiq_stack_size__ = 0x0010; +__irq_stack_size__ = 0x0080; +__svc_stack_size__ = 0x0004; +__sys_stack_size__ = 0x0400; +__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; + +MEMORY +{ + flash : org = 0x00000000, len = 512k - 12k + ram : org = 0x40000200, len = 32k - 0x200 - 288 +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; +__dma_start__ = 0x7FD00000; +__dma_size__ = 8k; +__dma_end__ = 0x7FD00000 + __dma_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(16) SUBALIGN(16) + { + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.ctors) + *(.dtors) + } > flash + + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; +__main_thread_stack_base__ = __ram_end__ - __stacks_total_size__; diff --git a/Project/os/ports/GCC/ARM/LPC214x/port.mk b/Project/os/ports/GCC/ARM/LPC214x/port.mk new file mode 100644 index 0000000..339f1d6 --- /dev/null +++ b/Project/os/ports/GCC/ARM/LPC214x/port.mk @@ -0,0 +1,11 @@ +# List of the ChibiOS/RT ARM7 LPC214x port files. +PORTSRC = ${CHIBIOS}/os/ports/GCC/ARM/chcore.c + +PORTASM = ${CHIBIOS}/os/ports/GCC/ARM/crt0.s \ + ${CHIBIOS}/os/ports/GCC/ARM/chcoreasm.s \ + ${CHIBIOS}/os/ports/GCC/ARM/LPC214x/vectors.s + +PORTINC = ${CHIBIOS}/os/ports/GCC/ARM \ + ${CHIBIOS}/os/ports/GCC/ARM/LPC214x + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARM/LPC214x/ld diff --git a/Project/os/ports/GCC/ARM/LPC214x/vectors.s b/Project/os/ports/GCC/ARM/LPC214x/vectors.s new file mode 100644 index 0000000..cbdd767 --- /dev/null +++ b/Project/os/ports/GCC/ARM/LPC214x/vectors.s @@ -0,0 +1,108 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file ARM/LPC214x/vectors.s + * @brief Interrupt vectors for the LPC214x family. + * + * @defgroup ARM_LPC214x_VECTORS LPC214x Interrupt Vectors + * @ingroup ARM_SPECIFIC + * @details Interrupt vectors for the LPC214x family. + * @{ + */ + +#if defined(__DOXYGEN__) +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +void _unhandled_exception(void) {} +#endif + +#if !defined(__DOXYGEN__) + +.section vectors +.code 32 +.balign 4 +/* + * System entry points. + */ +_start: + ldr pc, _reset + ldr pc, _undefined + ldr pc, _swi + ldr pc, _prefetch + ldr pc, _abort + nop + ldr pc, [pc,#-0xFF0] /* VIC - IRQ Vector Register */ + ldr pc, _fiq + +_reset: + .word ResetHandler /* In crt0.s */ +_undefined: + .word UndHandler +_swi: + .word SwiHandler +_prefetch: + .word PrefetchHandler +_abort: + .word AbortHandler +_fiq: + .word FiqHandler + .word 0 + .word 0 + +/* + * Default exceptions handlers. The handlers are declared weak in order to be + * replaced by the real handling code. Everything is defaulted to an infinite + * loop. + */ +.weak UndHandler +UndHandler: + +.weak SwiHandler +SwiHandler: + +.weak PrefetchHandler +PrefetchHandler: + +.weak AbortHandler +AbortHandler: + +.weak FiqHandler +FiqHandler: + +.global _unhandled_exception +_unhandled_exception: + b _unhandled_exception + +#endif + +/** @} */ diff --git a/Project/os/ports/GCC/ARM/LPC214x/wfi.h b/Project/os/ports/GCC/ARM/LPC214x/wfi.h new file mode 100644 index 0000000..46c1878 --- /dev/null +++ b/Project/os/ports/GCC/ARM/LPC214x/wfi.h @@ -0,0 +1,43 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +#ifndef _WFI_H_ +#define _WFI_H_ + +#include "lpc214x.h" + +#ifndef port_wait_for_interrupt +#if ENABLE_WFI_IDLE != 0 +#define port_wait_for_interrupt() { \ + PCON = 1; \ +} +#else +#define port_wait_for_interrupt() +#endif +#endif + +#endif /* _WFI_H_ */ diff --git a/Project/os/ports/GCC/ARM/chcore.c b/Project/os/ports/GCC/ARM/chcore.c new file mode 100644 index 0000000..1580d87 --- /dev/null +++ b/Project/os/ports/GCC/ARM/chcore.c @@ -0,0 +1,51 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file ARM/chcore.c + * @brief ARM7/9 architecture port code. + * + * @addtogroup ARM_CORE + * @{ + */ + +#include "ch.h" + +/** + * Halts the system. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** @} */ diff --git a/Project/os/ports/GCC/ARM/chcore.h b/Project/os/ports/GCC/ARM/chcore.h new file mode 100644 index 0000000..98d0f1c --- /dev/null +++ b/Project/os/ports/GCC/ARM/chcore.h @@ -0,0 +1,485 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file ARM/chcore.h + * @brief ARM7/9 architecture port macros and structures. + * + * @addtogroup ARM_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +/*===========================================================================*/ +/* Port constants. */ +/*===========================================================================*/ + +/* Core variants identifiers.*/ +#define ARM_CORE_ARM7TDMI 7 /**< ARM77TDMI core identifier. */ +#define ARM_CORE_ARM9 9 /**< ARM9 core identifier. */ + +/* Inclusion of the ARM implementation specific parameters.*/ +#include "armparams.h" + +/* ARM core check, only ARM7TDMI and ARM9 supported right now.*/ +#if (ARM_CORE == ARM_CORE_ARM7TDMI) || (ARM_CORE == ARM_CORE_ARM9) +#else +#error "unknown or unsupported ARM core" +#endif + +/*===========================================================================*/ +/* Port statically derived parameters. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief If enabled allows the idle thread to enter a low power mode. + */ +#ifndef ARM_ENABLE_WFI_IDLE +#define ARM_ENABLE_WFI_IDLE FALSE +#endif + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +/** + * @brief Macro defining a generic ARM architecture. + */ +#define CH_ARCHITECTURE_ARM + +#if defined(__DOXYGEN__) +/** + * @brief Macro defining the specific ARM architecture. + * @note This macro is for documentation only, the real name changes + * depending on the selected architecture, the possible names are: + * - CH_ARCHITECTURE_ARM7TDMI. + * - CH_ARCHITECTURE_ARM9. + * . + */ +#define CH_ARCHITECTURE_ARMx + +/** + * @brief Name of the implemented architecture. + * @note The value is for documentation only, the real value changes + * depending on the selected architecture, the possible values are: + * - "ARM7". + * - "ARM9". + * . + */ +#define CH_ARCHITECTURE_NAME "ARMx" + +/** + * @brief Name of the architecture variant (optional). + * @note The value is for documentation only, the real value changes + * depending on the selected architecture, the possible values are: + * - "ARM7TDMI" + * - "ARM9" + * . + */ +#define CH_CORE_VARIANT_NAME "ARMxy" + +/** + * @brief Port-specific information string. + * @note The value is for documentation only, the real value changes + * depending on the selected options, the possible values are: + * - "Pure ARM" + * - "Pure THUMB" + * - "Interworking" + * . + */ +#define CH_PORT_INFO "ARM|THUMB|Interworking" + +#elif ARM_CORE == ARM_CORE_ARM7TDMI +#define CH_ARCHITECTURE_ARM7TDMI +#define CH_ARCHITECTURE_NAME "ARM7" +#define CH_CORE_VARIANT_NAME "ARM7TDMI" + +#elif ARM_MODEL == ARM_VARIANT_ARM9 +#define CH_ARCHITECTURE_ARM9 +#define CH_ARCHITECTURE_NAME "ARM9" +#define CH_CORE_VARIANT_NAME "ARM9" +#endif + +#if THUMB_PRESENT +#if THUMB_NO_INTERWORKING +#define CH_PORT_INFO "Pure THUMB mode" +#else /* !THUMB_NO_INTERWORKING */ +#define CH_PORT_INFO "Interworking mode" +#endif /* !THUMB_NO_INTERWORKING */ +#else /* !THUMB_PRESENT */ +#define CH_PORT_INFO "Pure ARM mode" +#endif /* !THUMB_PRESENT */ + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "GCC " __VERSION__ + +/*===========================================================================*/ +/* Port implementation part (common). */ +/*===========================================================================*/ + +/** + * @brief 32 bits stack and memory alignment enforcement. + */ +typedef uint32_t stkalign_t; + +/** + * @brief Generic ARM register. + */ +typedef void *regarm_t; + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + */ +struct extctx { + regarm_t spsr_irq; + regarm_t lr_irq; + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t r12; + regarm_t lr_usr; +}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching. + */ +struct intctx { + regarm_t r4; + regarm_t r5; + regarm_t r6; + regarm_t r7; + regarm_t r8; + regarm_t r9; + regarm_t r10; + regarm_t r11; + regarm_t lr; +}; + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details In this port the structure just holds a pointer to the @p intctx + * structure representing the stack pointer at context switch time. + */ +struct context { + struct intctx *r13; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->r4 = pf; \ + tp->p_ctx.r13->r5 = arg; \ + tp->p_ctx.r13->lr = _port_thread_start; \ +} + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + * @note In this port it is set to 4 because the idle thread does have + * a stack frame when compiling without optimizations. + */ +#ifndef PORT_IDLE_THREAD_STACK_SIZE +#define PORT_IDLE_THREAD_STACK_SIZE 4 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * This value can be zero on those architecture where there is a + * separate interrupt stack and the stack space between @p intctx and + * @p extctx is known to be zero. + * @note In this port 0x10 is a safe value, it can be reduced after careful + * analysis of the generated code. + */ +#ifndef PORT_INT_REQUIRED_STACK +#define PORT_INT_REQUIRED_STACK 0x10 +#endif + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + * @note This macro has a different implementation depending if compiled in + * ARM or THUMB mode. + * @note The THUMB implementation starts with ARM code because interrupt + * vectors are always invoked in ARM mode regardless the bit 0 + * value. The switch in THUMB mode is done in the function prologue so + * it is transparent to the user code. + */ +#if !defined(PORT_IRQ_PROLOGUE) +#ifdef THUMB +#define PORT_IRQ_PROLOGUE() { \ + asm volatile (".code 32 \n\t" \ + "stmfd sp!, {r0-r3, r12, lr} \n\t" \ + "add r0, pc, #1 \n\t" \ + "bx r0 \n\t" \ + ".code 16" : : : "memory"); \ +} +#else /* !THUMB */ +#define PORT_IRQ_PROLOGUE() { \ + asm volatile ("stmfd sp!, {r0-r3, r12, lr}" : : : "memory"); \ +} +#endif /* !THUMB */ +#endif /* !defined(PORT_IRQ_PROLOGUE) */ + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + * @note This macro has a different implementation depending if compiled in + * ARM or THUMB mode. + */ +#if !defined(PORT_IRQ_EPILOGUE) +#ifdef THUMB +#define PORT_IRQ_EPILOGUE() { \ + asm volatile ("ldr r0, =_port_irq_common \n\t" \ + "bx r0" : : : "memory"); \ +} +#else /* !THUMB */ +#define PORT_IRQ_EPILOGUE() { \ + asm volatile ("b _port_irq_common" : : : "memory"); \ +} +#endif /* !THUMB */ +#endif /* !defined(PORT_IRQ_EPILOGUE) */ + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#if !defined(PORT_IRQ_HANDLER) +#define PORT_IRQ_HANDLER(id) __attribute__((naked)) void id(void) +#endif /* !defined(PORT_IRQ_HANDLER) */ + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#if !defined(PORT_FAST_IRQ_HANDLER) +#define PORT_FAST_IRQ_HANDLER(id) \ + __attribute__((interrupt("FIQ"))) void id(void) +#endif /* !defined(PORT_FAST_IRQ_HANDLER) */ + +/** + * @brief Port-related initialization code. + * @note This function is empty in this port. + */ +#define port_init() + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform + * more actions. + * @note In this port it disables the IRQ sources and keeps FIQ sources + * enabled. + */ +#ifdef THUMB +#define port_lock() { \ + asm volatile ("bl _port_lock_thumb" : : : "r3", "lr", "memory"); \ +} +#else /* !THUMB */ +#define port_lock() asm volatile ("msr CPSR_c, #0x9F" : : : "memory") +#endif /* !THUMB */ + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform + * more actions. + * @note In this port it enables both the IRQ and FIQ sources. + */ +#ifdef THUMB +#define port_unlock() { \ + asm volatile ("bl _port_unlock_thumb" : : : "r3", "lr", "memory"); \ +} +#else /* !THUMB */ +#define port_unlock() asm volatile ("msr CPSR_c, #0x1F" : : : "memory") +#endif /* !THUMB */ + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + * @note Empty in this port. + */ +#define port_lock_from_isr() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + * @note Empty in this port. + */ +#define port_unlock_from_isr() + +/** + * @brief Disables all the interrupt sources. + * @note Of course non-maskable interrupt sources are not included. + * @note In this port it disables both the IRQ and FIQ sources. + * @note Implements a workaround for spurious interrupts taken from the NXP + * LPC214x datasheet. + */ +#ifdef THUMB +#define port_disable() { \ + asm volatile ("bl _port_disable_thumb" : : : "r3", "lr", "memory"); \ +} +#else /* !THUMB */ +#define port_disable() { \ + asm volatile ("mrs r3, CPSR \n\t" \ + "orr r3, #0x80 \n\t" \ + "msr CPSR_c, r3 \n\t" \ + "orr r3, #0x40 \n\t" \ + "msr CPSR_c, r3" : : : "r3", "memory"); \ +} +#endif /* !THUMB */ + +/** + * @brief Disables the interrupt sources below kernel-level priority. + * @note Interrupt sources above kernel level remains enabled. + * @note In this port it disables the IRQ sources and enables the + * FIQ sources. + */ +#ifdef THUMB +#define port_suspend() { \ + asm volatile ("bl _port_suspend_thumb" : : : "r3", "lr", "memory"); \ +} +#else /* !THUMB */ +#define port_suspend() asm volatile ("msr CPSR_c, #0x9F" : : : "memory") +#endif /* !THUMB */ + +/** + * @brief Enables all the interrupt sources. + * @note In this port it enables both the IRQ and FIQ sources. + */ +#ifdef THUMB +#define port_enable() { \ + asm volatile ("bl _port_enable_thumb" : : : "r3", "lr", "memory"); \ +} +#else /* !THUMB */ +#define port_enable() asm volatile ("msr CPSR_c, #0x1F" : : : "memory") +#endif /* !THUMB */ + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * @note Implemented as inlined code for performance reasons. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#ifdef THUMB +#if CH_DBG_ENABLE_STACK_CHECK +#define port_switch(ntp, otp) { \ + register struct intctx *r13 asm ("r13"); \ + if ((stkalign_t *)(r13 - 1) < otp->p_stklimit) \ + chDbgPanic("stack overflow"); \ + _port_switch_thumb(ntp, otp); \ +} +#else /* !CH_DBG_ENABLE_STACK_CHECK */ +#define port_switch(ntp, otp) _port_switch_thumb(ntp, otp) +#endif /* !CH_DBG_ENABLE_STACK_CHECK */ +#else /* !THUMB */ +#if CH_DBG_ENABLE_STACK_CHECK +#define port_switch(ntp, otp) { \ + register struct intctx *r13 asm ("r13"); \ + if ((stkalign_t *)(r13 - 1) < otp->p_stklimit) \ + chDbgPanic("stack overflow"); \ + _port_switch_arm(ntp, otp); \ +} +#else /* !CH_DBG_ENABLE_STACK_CHECK */ +#define port_switch(ntp, otp) _port_switch_arm(ntp, otp) +#endif /* !CH_DBG_ENABLE_STACK_CHECK */ +#endif /* !THUMB */ + +#ifdef __cplusplus +extern "C" { +#endif + void port_halt(void); +#ifdef THUMB + void _port_switch_thumb(Thread *ntp, Thread *otp); +#else /* !THUMB */ + void _port_switch_arm(Thread *ntp, Thread *otp); +#endif /* !THUMB */ + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/ARM/chcoreasm.s b/Project/os/ports/GCC/ARM/chcoreasm.s new file mode 100644 index 0000000..1ebba3b --- /dev/null +++ b/Project/os/ports/GCC/ARM/chcoreasm.s @@ -0,0 +1,266 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file ARM/chcoreasm.s + * @brief ARM7/9 architecture port low level code. + * + * @addtogroup ARM_CORE + * @{ + */ + +#include "chconf.h" + +#define FALSE 0 +#define TRUE 1 + +#if !defined(__DOXYGEN__) + +.set MODE_USR, 0x10 +.set MODE_FIQ, 0x11 +.set MODE_IRQ, 0x12 +.set MODE_SVC, 0x13 +.set MODE_ABT, 0x17 +.set MODE_UND, 0x1B +.set MODE_SYS, 0x1F + +.equ I_BIT, 0x80 +.equ F_BIT, 0x40 + +.text + +/* + * Interrupt enable/disable functions, only present if there is THUMB code in + * the system because those are inlined in ARM code. + */ +#ifdef THUMB_PRESENT +.balign 16 +.code 16 +.thumb_func +.global _port_disable_thumb +_port_disable_thumb: + mov r3, pc + bx r3 +.code 32 + mrs r3, CPSR + orr r3, #I_BIT + msr CPSR_c, r3 + orr r3, #F_BIT + msr CPSR_c, r3 + bx lr + +.balign 16 +.code 16 +.thumb_func +.global _port_suspend_thumb +_port_suspend_thumb: +.thumb_func +.global _port_lock_thumb +_port_lock_thumb: + mov r3, pc + bx r3 +.code 32 + msr CPSR_c, #MODE_SYS | I_BIT + bx lr + +.balign 16 +.code 16 +.thumb_func +.global _port_enable_thumb +_port_enable_thumb: +.thumb_func +.global _port_unlock_thumb +_port_unlock_thumb: + mov r3, pc + bx r3 +.code 32 + msr CPSR_c, #MODE_SYS + bx lr + +#endif + +.balign 16 +#ifdef THUMB_PRESENT +.code 16 +.thumb_func +.global _port_switch_thumb +_port_switch_thumb: + mov r2, pc + bx r2 + // Jumps into _port_switch_arm in ARM mode +#endif +.code 32 +.global _port_switch_arm +_port_switch_arm: +#ifdef CH_CURRP_REGISTER_CACHE + stmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} + str sp, [r1, #12] + ldr sp, [r0, #12] +#ifdef THUMB_PRESENT + ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} + bx lr +#else /* !THUMB_PRESENT */ + ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, pc} +#endif /* !THUMB_PRESENT */ +#else /* !CH_CURRP_REGISTER_CACHE */ + stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} + str sp, [r1, #12] + ldr sp, [r0, #12] +#ifdef THUMB_PRESENT + ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} + bx lr +#else /* !THUMB_PRESENT */ + ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} +#endif /* !THUMB_PRESENT */ +#endif /* !CH_CURRP_REGISTER_CACHE */ + +/* + * Common exit point for all IRQ routines, it performs the rescheduling if + * required. + * System stack frame structure after a context switch in the + * interrupt handler: + * + * High +------------+ + * | LR_USR | -+ + * | R12 | | + * | R3 | | + * | R2 | | External context: IRQ handler frame + * | R1 | | + * | R0 | | + * | PC | | (user code return address) + * | PSR_USR | -+ (user code status) + * | .... | <- chSchDoReschedule() stack frame, optimize it for space + * | LR | -+ (system code return address) + * | R11 | | + * | R10 | | + * | R9 | | + * | R8 | | Internal context: chSysSwitch() frame + * | (R7) | | (optional, see CH_CURRP_REGISTER_CACHE) + * | R6 | | + * | R5 | | + * SP-> | R4 | -+ + * Low +------------+ + */ +.balign 16 +#ifdef THUMB_NO_INTERWORKING +.code 16 +.thumb_func +.globl _port_irq_common +_port_irq_common: + bl chSchIsPreemptionRequired + mov lr, pc + bx lr +.code 32 +#else /* !THUMB_NO_INTERWORKING */ +.code 32 +.globl _port_irq_common +_port_irq_common: + bl chSchIsPreemptionRequired +#endif /* !THUMB_NO_INTERWORKING */ + cmp r0, #0 // Simply returns if a + ldmeqfd sp!, {r0-r3, r12, lr} // reschedule is not + subeqs pc, lr, #4 // required. + + // Saves the IRQ mode registers in the system stack. + ldmfd sp!, {r0-r3, r12, lr} // IRQ stack now empty. + msr CPSR_c, #MODE_SYS | I_BIT + stmfd sp!, {r0-r3, r12, lr} // Registers on System Stack. + msr CPSR_c, #MODE_IRQ | I_BIT + mrs r0, SPSR + mov r1, lr + msr CPSR_c, #MODE_SYS | I_BIT + stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ. + + // Context switch. +#ifdef THUMB_NO_INTERWORKING + add r0, pc, #1 + bx r0 +.code 16 +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif + mov lr, pc + bx lr +.code 32 +#else /* !THUMB_NO_INTERWORKING */ +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif +#endif /* !THUMB_NO_INTERWORKING */ + + // Re-establish the IRQ conditions again. + ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ. + msr CPSR_c, #MODE_IRQ | I_BIT + msr SPSR_fsxc, r0 + mov lr, r1 + msr CPSR_c, #MODE_SYS | I_BIT + ldmfd sp!, {r0-r3, r12, lr} + msr CPSR_c, #MODE_IRQ | I_BIT + subs pc, lr, #4 + +/* + * Threads trampoline code. + * NOTE: The threads always start in ARM mode and then switches to the + * thread-function mode. + */ +.balign 16 +.code 32 +.globl _port_thread_start +_port_thread_start: +#if CH_DBG_SYSTEM_STATE_CHECK + mov r0, #0 + ldr r1, =dbg_lock_cnt + str r0, [r1] +#endif + msr CPSR_c, #MODE_SYS +#ifndef THUMB_NO_INTERWORKING + mov r0, r5 + mov lr, pc + bx r4 + bl chThdExit +#else /* !THUMB_NO_INTERWORKING */ + add r0, pc, #1 + bx r0 +.code 16 + mov r0, r5 + bl jmpr4 + bl chThdExit +jmpr4: + bx r4 +#endif /* !THUMB_NO_INTERWORKING */ + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/Project/os/ports/GCC/ARM/chtypes.h b/Project/os/ports/GCC/ARM/chtypes.h new file mode 100644 index 0000000..48bc6a1 --- /dev/null +++ b/Project/os/ports/GCC/ARM/chtypes.h @@ -0,0 +1,90 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file ARM/chtypes.h + * @brief ARM7/9 architecture port system types. + * + * @addtogroup ARM_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#define __need_NULL +#define __need_size_t +#define __need_ptrdiff_t +#include + +#if !defined(_STDINT_H) && !defined(__STDINT_H_) +#include +#endif + +typedef int32_t bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint32_t tprio_t; /**< Thread priority. */ +typedef int32_t msg_t; /**< Inter-thread message. */ +typedef int32_t eventid_t; /**< Event Id. */ +typedef uint32_t eventmask_t; /**< Events mask. */ +typedef uint32_t systime_t; /**< System time. */ +typedef int32_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE inline + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note It uses the "packed" GCC attribute. + */ +#define PACK_STRUCT_STRUCT __attribute__((packed)) + +/** + * @brief Packed structure modifier (before). + * @note Empty in this port. + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/ARM/crt0.s b/Project/os/ports/GCC/ARM/crt0.s new file mode 100644 index 0000000..90b1cfa --- /dev/null +++ b/Project/os/ports/GCC/ARM/crt0.s @@ -0,0 +1,169 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file ARM/crt0.s + * @brief Generic ARM7/9 startup file for ChibiOS/RT. + * + * @addtogroup ARM_CORE + * @{ + */ + +#if !defined(__DOXYGEN__) + + .set MODE_USR, 0x10 + .set MODE_FIQ, 0x11 + .set MODE_IRQ, 0x12 + .set MODE_SVC, 0x13 + .set MODE_ABT, 0x17 + .set MODE_UND, 0x1B + .set MODE_SYS, 0x1F + + .set I_BIT, 0x80 + .set F_BIT, 0x40 + + .text + .code 32 + .balign 4 + +/* + * Reset handler. + */ + .global ResetHandler +ResetHandler: + /* + * Stack pointers initialization. + */ + ldr r0, =__ram_end__ + /* Undefined */ + msr CPSR_c, #MODE_UND | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__und_stack_size__ + sub r0, r0, r1 + /* Abort */ + msr CPSR_c, #MODE_ABT | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__abt_stack_size__ + sub r0, r0, r1 + /* FIQ */ + msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__fiq_stack_size__ + sub r0, r0, r1 + /* IRQ */ + msr CPSR_c, #MODE_IRQ | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__irq_stack_size__ + sub r0, r0, r1 + /* Supervisor */ + msr CPSR_c, #MODE_SVC | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__svc_stack_size__ + sub r0, r0, r1 + /* System */ + msr CPSR_c, #MODE_SYS | I_BIT | F_BIT + mov sp, r0 +// ldr r1, =__sys_stack_size__ +// sub r0, r0, r1 + /* + * Early initialization. + */ +#ifndef THUMB_NO_INTERWORKING + bl __early_init +#else + add r0, pc, #1 + bx r0 + .code 16 + bl __early_init + mov r0, pc + bx r0 + .code 32 +#endif + /* + * Data initialization. + * NOTE: It assumes that the DATA size is a multiple of 4. + */ + ldr r1, =_textdata + ldr r2, =_data + ldr r3, =_edata +dataloop: + cmp r2, r3 + ldrlo r0, [r1], #4 + strlo r0, [r2], #4 + blo dataloop + /* + * BSS initialization. + * NOTE: It assumes that the BSS size is a multiple of 4. + */ + mov r0, #0 + ldr r1, =_bss_start + ldr r2, =_bss_end +bssloop: + cmp r1, r2 + strlo r0, [r1], #4 + blo bssloop + /* + * Main program invocation. + */ +#ifdef THUMB_NO_INTERWORKING + add r0, pc, #1 + bx r0 + .code 16 + bl main + ldr r1, =_main_exit_handler + bx r1 + .code 32 +#else + bl main + b _main_exit_handler +#endif + +/* + * Default main function exit handler. + */ + .weak _main_exit_handler + .global _main_exit_handler +_main_exit_handler: +.loop: b .loop + +/* + * Default early initialization code. It is declared weak in order to be + * replaced by the real initialization code. + * Early initialization is performed just after reset before BSS and DATA + * segments initialization. + */ +#ifdef THUMB_NO_INTERWORKING + .thumb_func + .code 16 +#endif + .weak __early_init +hwinit0: + bx lr + .code 32 +#endif + +/** @} */ diff --git a/Project/os/ports/GCC/ARM/port.dox b/Project/os/ports/GCC/ARM/port.dox new file mode 100644 index 0000000..14a3600 --- /dev/null +++ b/Project/os/ports/GCC/ARM/port.dox @@ -0,0 +1,233 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup ARM ARM7/9 + * @details ARM7/9 port for the GCC compiler. + * + * @section ARM_INTRO Introduction + * The ARM7/9-GCC port supports the ARM7/9 core in the following three modes: + * - Pure ARM mode, this is the preferred mode for code speed, this + * mode increases the memory footprint however. This mode is enabled when + * all the modules are compiled in ARM mode, see the Makefiles. + * - Pure THUMB mode, this is the preferred mode for code size. In + * this mode the execution speed is slower than the ARM mode. This mode + * is enabled when all the modules are compiled in THUMB mode, see the + * Makefiles. + * - Interworking mode, when in the system there are ARM modules mixed + * with THUMB modules then the interworking compiler option is enabled. + * This is usually the slowest mode and the code size is not as good as + * in pure THUMB mode. + * . + * @section ARM_STATES Mapping of the System States in the ARM7/9 port + * The ChibiOS/RT logical system states are mapped as follow in the ARM7/9 + * port: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated, usually the CPU goes through several + * hardware states during the startup phase. + * - Normal. This is the state the system has after executing + * @p chSysInit(). In this state the CPU has both the interrupt sources + * (IRQ and FIQ) enabled and is running in ARM System Mode. + * - Suspended. In this state the IRQ sources are disabled but the FIQ + * sources are served, the core is running in ARM System Mode. + * - Disabled. Both the IRQ and FIQ sources are disabled, the core is + * running in ARM System Mode. + * - Sleep. ARM7/9 cores does not have an explicit built-in low power + * mode but there are clock stop modes implemented in custom ways by the + * various silicon vendors. This state is implemented in each microcontroller + * support code in a different way, the core is running (or freezed...) + * in ARM System Mode. + * - S-Locked. IRQ sources disabled, core running in ARM System Mode. + * - I-Locked. IRQ sources disabled, core running in ARM IRQ Mode. Note + * that this state is not different from the SRI state in this port, the + * @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in + * order to formally change state because this may change). + * - Serving Regular Interrupt. IRQ sources disabled, core running in + * ARM IRQ Mode. See also the I-Locked state. + * - Serving Fast Interrupt. IRQ and FIQ sources disabled, core running + * in ARM FIQ Mode. + * - Serving Non-Maskable Interrupt. There are no asynchronous NMI + * sources in ARM7/9 architecture but synchronous SVC, ABT and UND exception + * handlers can be seen as belonging to this category. + * - Halted. Implemented as an infinite loop after disabling both IRQ + * and FIQ sources. The ARM state is whatever the processor was running when + * @p chSysHalt() was invoked. + * . + * @section ARM_NOTES The ARM7/9 port notes + * The ARM7/9 port is organized as follow: + * - The @p main() function is invoked in system mode. + * - Each thread has a private user/system stack, the system has a single + * interrupt stack where all the interrupts are processed. + * - The threads are started in system mode. + * - The threads code can run in system mode or user mode, however the + * code running in user mode cannot invoke the ChibiOS/RT APIs directly + * because privileged instructions are used inside.
+ * The kernel APIs can be eventually invoked by using a SWI entry point + * that handles the switch in system mode and the return in user mode. + * - Other modes are not preempt-able because the system code assumes the + * threads running in system mode. When running in supervisor or other + * modes make sure that the interrupts are globally disabled. + * - Interrupts nesting is not supported in the ARM7/9 port because their + * implementation, even if possible, is not really efficient in this + * architecture. + * - FIQ sources can preempt the kernel (by design) so it is not possible to + * invoke the kernel APIs from inside a FIQ handler. FIQ handlers are not + * affected by the kernel activity so there is not added jitter. + * . + * @section ARM_IH ARM7/9 Interrupt Handlers + * In the current implementation the ARM7/9 Interrupt handlers do not save + * function-saved registers so you need to make sure your code saves them + * or does not use them (this happens because in the ARM7/9 port all the + * OS interrupt handler functions are declared naked).
+ * Function-trashed registers (R0-R3, R12, LR, SR) are saved/restored by the + * system macros @p CH_IRQ_PROLOGUE() and @p CH_IRQ_EPILOGUE().
+ * The easiest way to ensure this is to just invoke a normal function from + * within the interrupt handler, the function code will save all the required + * registers.
+ * Example: + * @code + * CH_IRQ_HANDLER(irq_handler) { + * CH_IRQ_PROLOGUE(); + * + * serve_interrupt(); + * + * VICVectAddr = 0; // This is LPC214x-specific. + * CH_IRQ_EPILOGUE(); + * } + * @endcode + * This is not a bug but an implementation choice, this solution allows to + * have interrupt handlers compiled in thumb mode without have to use an + * interworking mode (the mode switch is hidden in the macros), this + * greatly improves code efficiency and size. You can look at the serial + * driver for real examples of interrupt handlers.
+ * It is important that the serve_interrupt() interrupt function is not + * inlined by the compiler into the ISR or the code could still modify + * the unsaved registers, this can be accomplished using GCC by adding + * the attribute "noinline" to the function: + * @code + * #if defined(__GNUC__) + * __attribute__((noinline)) + * #endif + * static void serve_interrupt(void) { + * } + * @endcode + * Note that several commercial compilers support a GNU-like functions + * attribute mechanism.
+ * Alternative ways are to use an appropriate pragma directive or disable + * inlining optimizations in the modules containing the interrupt handlers. + * + * @ingroup gcc + */ + +/** + * @defgroup ARM_CONF Configuration Options + * @details ARM7/9 specific configuration options. The ARM7/9 port allows some + * architecture-specific configurations settings that can be overridden by + * redefining them in @p chconf.h. Usually there is no need to change the + * default values. + * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used + * by an interrupt handler between the @p extctx and @p intctx + * structures.
+ * In practice this value is the stack space used by the chSchDoReschedule() + * stack frame.
+ * This value can be affected by a variety of external things like compiler + * version, compiler options, kernel settings (speed/size) and so on.
+ * The default for this value is @p 0x10 which should be a safe value, you + * can trim this down by defining the macro externally. This would save + * some valuable RAM space for each thread present in the system.
+ * The default value is set into ./os/ports/GCC/ARM/chcore.h. + * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE + * thread. Usually there is no need to change this value unless inserting + * code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro. + * - @p ARM_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the + * an implementation-specific clock stop mode from within the idle loop. + * This option is defaulted to FALSE because it can create problems with + * some debuggers. Setting this option to TRUE reduces the system power + * requirements. + * . + * @ingroup ARM + */ + +/** + * @defgroup ARM_CORE Core Port Implementation + * @details ARM7/9 specific port code, structures and macros. + * + * @ingroup ARM + */ + +/** + * @defgroup ARM_STARTUP Startup Support + * @details ARM7/9 startup code support. ChibiOS/RT provides its own generic + * startup file for the ARM7/9 port. Of course it is not mandatory to use it + * but care should be taken about the startup phase details. + * + * @section ARM_STARTUP_1 Startup Process + * The startup process, as implemented, is the following: + * -# The stacks are initialized by assigning them the sizes defined in the + * linker script (usually named @p ch.ld). Stack areas are allocated from + * the highest RAM location downward. + * -# The ARM state is switched to System with both IRQ and FIQ sources + * disabled. + * -# An early initialization routine @p hwinit0 is invoked, if the symbol is + * not defined then an empty default routine is executed (weak symbol). + * -# DATA and BSS segments are initialized. + * -# A late initialization routine @p hwinit1 is invoked, if the symbol not + * defined then an empty default routine is executed (weak symbol).
+ * This late initialization function is also the proper place for a + * @a bootloader, if your application requires one. + * -# The @p main() function is invoked with the parameters @p argc and @p argv + * set to zero. + * -# Should the @p main() function return a branch is performed to the weak + * symbol _main_exit_handler. The default code is an endless empty loop. + * . + * @section ARM_STARTUP_2 Expected linker symbols + * The startup code starts at the symbol @p ResetHandler and expects the + * following symbols to be defined in the linker script: + * - @p __ram_end__ RAM end location +1. + * - @p __und_stack_size__ Undefined Instruction stack size. + * - @p __abt_stack_size__ Memory Abort stack size. + * - @p __fiq_stack_size__ FIQ service stack size. + * - @p __irq_stack_size__ IRQ service stack size. + * - @p __svc_stack_size__ SVC service stack size. + * - @p __sys_stack_size__ System/User stack size. This is the stack area used + * by the @p main() function. + * - @p _textdata address of the data segment source read only data. + * - @p _data data segment start location. + * - @p _edata data segment end location +1. + * - @p _bss_start BSS start location. + * - @p _bss_end BSS end location +1. + * . + * @ingroup ARM + */ + +/** + * @defgroup ARM_SPECIFIC Specific Implementations + * @details Platform-specific port code. + * + * @ingroup ARM + */ diff --git a/Project/os/ports/GCC/ARM/rules.mk b/Project/os/ports/GCC/ARM/rules.mk new file mode 100644 index 0000000..7884103 --- /dev/null +++ b/Project/os/ports/GCC/ARM/rules.mk @@ -0,0 +1,209 @@ +# ARM7/9 common makefile scripts and rules. + +# Output directory and files +ifeq ($(BUILDDIR),) + BUILDDIR = build +endif +ifeq ($(BUILDDIR),.) + BUILDDIR = build +endif +OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \ + $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp + +# Automatic compiler options +OPT = $(USE_OPT) +COPT = $(USE_COPT) +CPPOPT = $(USE_CPPOPT) +ifeq ($(USE_LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections +endif + +# Source files groups and paths +ifeq ($(USE_THUMB),yes) + TCSRC += $(CSRC) + TCPPSRC += $(CPPSRC) +else + ACSRC += $(CSRC) + ACPPSRC += $(CPPSRC) +endif +ASRC = $(ACSRC)$(ACPPSRC) +TSRC = $(TCSRC)$(TCPPSRC) +SRCPATHS = $(sort $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC))) + +# Various directories +OBJDIR = $(BUILDDIR)/obj +LSTDIR = $(BUILDDIR)/lst + +# Object files groups +ACOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o))) +ACPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o))) +TCOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o))) +TCPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o))) +ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o))) +OBJS = $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) + +# Paths +IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) +LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) + +# Macros +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) + +# Libs +LIBS = $(DLIBS) $(ULIBS) + +# Various settings +MCFLAGS = -mcpu=$(MCU) +ODFLAGS = -x --syms +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) +CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) +CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) +ifeq ($(USE_LINK_GC),yes) + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) +else + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch $(LLIBDIR) +endif + +# Thumb interwork enabled only if needed because it kills performance. +ifneq ($(TSRC),) + CFLAGS += -DTHUMB_PRESENT + CPPFLAGS += -DTHUMB_PRESENT + ASFLAGS += -DTHUMB_PRESENT + ifneq ($(ASRC),) + # Mixed ARM and THUMB mode. + CFLAGS += -mthumb-interwork + CPPFLAGS += -mthumb-interwork + ASFLAGS += -mthumb-interwork + LDFLAGS += -mthumb-interwork + else + # Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly. + CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING + CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING + ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb + LDFLAGS += -mno-thumb-interwork -mthumb + endif +else + # Pure ARM mode + CFLAGS += -mno-thumb-interwork + CPPFLAGS += -mno-thumb-interwork + ASFLAGS += -mno-thumb-interwork + LDFLAGS += -mno-thumb-interwork +endif + +# Generate dependency information +CFLAGS += -MD -MP -MF .dep/$(@F).d +CPPFLAGS += -MD -MP -MF .dep/$(@F).d + +# Paths where to search for sources +VPATH = $(SRCPATHS) + +# +# Makefile rules +# + +all: $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK + +MAKE_ALL_RULE_HOOK: + +$(OBJS): | $(BUILDDIR) + +$(BUILDDIR) $(OBJDIR) $(LSTDIR): +ifneq ($(USE_VERBOSE_COMPILE),yes) + @echo Compiler Options + @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o + @echo +endif + mkdir -p $(OBJDIR) + mkdir -p $(LSTDIR) + +$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@ +endif + +$(TCPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@ +endif + +$(ACOBJS) : $(OBJDIR)/%.o : %.c Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@ +endif + +$(TCOBJS) : $(OBJDIR)/%.o : %.c Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@ +endif + +$(ASMOBJS) : $(OBJDIR)/%.o : %.s Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@ +endif + +%.elf: $(OBJS) $(LDSCRIPT) +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ +else + @echo Linking $@ + @$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ +endif + +%.hex: %.elf $(LDSCRIPT) +ifeq ($(USE_VERBOSE_COMPILE),yes) + $(HEX) $< $@ +else + @echo Creating $@ + @$(HEX) $< $@ +endif + +%.bin: %.elf $(LDSCRIPT) +ifeq ($(USE_VERBOSE_COMPILE),yes) + $(BIN) $< $@ +else + @echo Creating $@ + @$(BIN) $< $@ +endif + +%.dmp: %.elf $(LDSCRIPT) +ifeq ($(USE_VERBOSE_COMPILE),yes) + $(OD) $(ODFLAGS) $< > $@ +else + @echo Creating $@ + @$(OD) $(ODFLAGS) $< > $@ + @echo Done +endif + +clean: + @echo Cleaning + -rm -fR .dep $(BUILDDIR) + @echo Done + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/Project/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h b/Project/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h new file mode 100644 index 0000000..8f8ee41 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/ARMCMx/LPC11xx/cmparams.h + * @brief ARM Cortex-M0 parameters for the LPC11xx. + * + * @defgroup ARMCMx_LPC11xx LPC11xx Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M0 specific parameters for the + * LPC11xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M0 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 2 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC1114.ld b/Project/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC1114.ld new file mode 100644 index 0000000..380299b --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC1114.ld @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * LPC1114 memory setup. + */ +__main_stack_size__ = 0x0200; +__process_stack_size__ = 0x0200; + +MEMORY +{ + flash : org = 0x00000000, len = 32k + ram : org = 0x10000000, len = 8k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/Project/os/ports/GCC/ARMCMx/LPC11xx/port.mk b/Project/os/ports/GCC/ARMCMx/LPC11xx/port.mk new file mode 100644 index 0000000..8bfd25a --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/LPC11xx/port.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/RT Cortex-M0 LPC11xx port files. +PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/vectors.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v6m.c \ + ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ + ${CHIBIOS}/os/ports/common/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC11xx + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC11xx/ld diff --git a/Project/os/ports/GCC/ARMCMx/LPC11xx/vectors.c b/Project/os/ports/GCC/ARMCMx/LPC11xx/vectors.c new file mode 100644 index 0000000..5633aed --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/LPC11xx/vectors.c @@ -0,0 +1,205 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/ARMCMx/LPC11xx/vectors.c + * @brief Interrupt vectors for the LPC11xx family. + * + * @defgroup ARMCMx_LPC11xx_VECTORS LPC11xx Interrupt Vectors + * @ingroup ARMCMx_SPECIFIC + * @details Interrupt vectors for the LPC11xx family. + * @{ + */ + +#include "ch.h" + +/** + * @brief Type of an IRQ vector. + */ +typedef void (*irq_vector_t)(void); + +/** + * @brief Type of a structure representing the whole vectors table. + */ +typedef struct { + uint32_t *init_stack; + irq_vector_t reset_vector; + irq_vector_t nmi_vector; + irq_vector_t hardfault_vector; + irq_vector_t memmanage_vector; + irq_vector_t busfault_vector; + irq_vector_t usagefault_vector; + irq_vector_t vector1c; + irq_vector_t vector20; + irq_vector_t vector24; + irq_vector_t vector28; + irq_vector_t svcall_vector; + irq_vector_t debugmonitor_vector; + irq_vector_t vector34; + irq_vector_t pendsv_vector; + irq_vector_t systick_vector; + irq_vector_t vectors[32]; +} vectors_t; + +#if !defined(__DOXYGEN__) +extern uint32_t __main_stack_end__; +extern void ResetHandler(void); +extern void NMIVector(void); +extern void HardFaultVector(void); +extern void MemManageVector(void); +extern void BusFaultVector(void); +extern void UsageFaultVector(void); +extern void Vector1C(void); +extern void Vector20(void); +extern void Vector24(void); +extern void Vector28(void); +extern void SVCallVector(void); +extern void DebugMonitorVector(void); +extern void Vector34(void); +extern void PendSVVector(void); +extern void SysTickVector(void); +extern void Vector40(void); +extern void Vector44(void); +extern void Vector48(void); +extern void Vector4C(void); +extern void Vector50(void); +extern void Vector54(void); +extern void Vector58(void); +extern void Vector5C(void); +extern void Vector60(void); +extern void Vector64(void); +extern void Vector68(void); +extern void Vector6C(void); +extern void Vector70(void); +extern void Vector74(void); +extern void Vector78(void); +extern void Vector7C(void); +extern void Vector80(void); +extern void Vector84(void); +extern void Vector88(void); +extern void Vector8C(void); +extern void Vector90(void); +extern void Vector94(void); +extern void Vector98(void); +extern void Vector9C(void); +extern void VectorA0(void); +extern void VectorA4(void); +extern void VectorA8(void); +extern void VectorAC(void); +extern void VectorB0(void); +extern void VectorB4(void); +extern void VectorB8(void); +extern void VectorBC(void); +#endif + +/** + * @brief LPC11xx vectors table. + */ +#if !defined(__DOXYGEN__) +__attribute__ ((section("vectors"))) +#endif +vectors_t _vectors = { + &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, + MemManageVector, BusFaultVector, UsageFaultVector, Vector1C, + Vector20, Vector24, Vector28, SVCallVector, + DebugMonitorVector, Vector34, PendSVVector, SysTickVector, + { + Vector40, Vector44, Vector48, Vector4C, + Vector50, Vector54, Vector58, Vector5C, + Vector60, Vector64, Vector68, Vector6C, + Vector70, Vector74, Vector78, Vector7C, + Vector80, Vector84, Vector88, Vector8C, + Vector90, Vector94, Vector98, Vector9C, + VectorA0, VectorA4, VectorA8, VectorAC, + VectorB0, VectorB4, VectorB8, VectorBC + } +}; + +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +#if !defined(__DOXYGEN__) +__attribute__ ((naked)) +#endif +void _unhandled_exception(void) { + + while (TRUE) + ; +} + +void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); +void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); +void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); + +/** @} */ diff --git a/Project/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h b/Project/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h new file mode 100644 index 0000000..eb35785 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/ARMCMx/LPC13xx/cmparams.h + * @brief ARM Cortex-M3 LPC13xx Specific Parameters. + * + * @defgroup ARMCMx_LPC13xx LPC13xx Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * LPC13xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 3 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/ARMCMx/LPC13xx/ld/LPC1343.ld b/Project/os/ports/GCC/ARMCMx/LPC13xx/ld/LPC1343.ld new file mode 100644 index 0000000..8ef7e37 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/LPC13xx/ld/LPC1343.ld @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * LPC1343 memory setup. + */ +__main_stack_size__ = 0x0200; +__process_stack_size__ = 0x0200; + +MEMORY +{ + flash : org = 0x00000000, len = 32k + ram : org = 0x10000000, len = 8k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/Project/os/ports/GCC/ARMCMx/LPC13xx/port.mk b/Project/os/ports/GCC/ARMCMx/LPC13xx/port.mk new file mode 100644 index 0000000..fa392c5 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/LPC13xx/port.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/RT Cortex-M0 LPC13xx port files. +PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC13xx/vectors.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ + ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ + ${CHIBIOS}/os/ports/common/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC13xx + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC13xx/ld diff --git a/Project/os/ports/GCC/ARMCMx/LPC13xx/vectors.c b/Project/os/ports/GCC/ARMCMx/LPC13xx/vectors.c new file mode 100644 index 0000000..4575004 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/LPC13xx/vectors.c @@ -0,0 +1,264 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/ARMCMx/LPC13xx/vectors.c + * @brief Interrupt vectors for the LPC13xx family. + * + * @defgroup ARMCMx_LPC13xx_VECTORS LPC13xx Interrupt Vectors + * @ingroup ARMCMx_SPECIFIC + * @details Interrupt vectors for the LPC13xx family. + * @{ + */ + +#include "ch.h" + +/** + * @brief Type of an IRQ vector. + */ +typedef void (*irq_vector_t)(void); + +/** + * @brief Type of a structure representing the whole vectors table. + */ +typedef struct { + uint32_t *init_stack; + irq_vector_t reset_vector; + irq_vector_t nmi_vector; + irq_vector_t hardfault_vector; + irq_vector_t memmanage_vector; + irq_vector_t busfault_vector; + irq_vector_t usagefault_vector; + irq_vector_t vector1c; + irq_vector_t vector20; + irq_vector_t vector24; + irq_vector_t vector28; + irq_vector_t svcall_vector; + irq_vector_t debugmonitor_vector; + irq_vector_t vector34; + irq_vector_t pendsv_vector; + irq_vector_t systick_vector; + irq_vector_t vectors[58]; +} vectors_t; + +#if !defined(__DOXYGEN__) +extern uint32_t __main_stack_end__; +extern void ResetHandler(void); +extern void NMIVector(void); +extern void HardFaultVector(void); +extern void MemManageVector(void); +extern void BusFaultVector(void); +extern void UsageFaultVector(void); +extern void Vector1C(void); +extern void Vector20(void); +extern void Vector24(void); +extern void Vector28(void); +extern void SVCallVector(void); +extern void DebugMonitorVector(void); +extern void Vector34(void); +extern void PendSVVector(void); +extern void SysTickVector(void); +extern void Vector40(void); +extern void Vector44(void); +extern void Vector48(void); +extern void Vector4C(void); +extern void Vector50(void); +extern void Vector54(void); +extern void Vector58(void); +extern void Vector5C(void); +extern void Vector60(void); +extern void Vector64(void); +extern void Vector68(void); +extern void Vector6C(void); +extern void Vector70(void); +extern void Vector74(void); +extern void Vector78(void); +extern void Vector7C(void); +extern void Vector80(void); +extern void Vector84(void); +extern void Vector88(void); +extern void Vector8C(void); +extern void Vector90(void); +extern void Vector94(void); +extern void Vector98(void); +extern void Vector9C(void); +extern void VectorA0(void); +extern void VectorA4(void); +extern void VectorA8(void); +extern void VectorAC(void); +extern void VectorB0(void); +extern void VectorB4(void); +extern void VectorB8(void); +extern void VectorBC(void); +extern void VectorC0(void); +extern void VectorC4(void); +extern void VectorC8(void); +extern void VectorCC(void); +extern void VectorD0(void); +extern void VectorD4(void); +extern void VectorD8(void); +extern void VectorDC(void); +extern void VectorE0(void); +extern void VectorE4(void); +extern void VectorE8(void); +extern void VectorEC(void); +extern void VectorF0(void); +extern void VectorF4(void); +extern void VectorF8(void); +extern void VectorFC(void); +extern void Vector100(void); +extern void Vector104(void); +extern void Vector108(void); +extern void Vector10C(void); +extern void Vector110(void); +extern void Vector114(void); +extern void Vector118(void); +extern void Vector11C(void); +extern void Vector120(void); +extern void Vector124(void); +#endif + +/** + * @brief LPC13xx vectors table. + */ +#if !defined(__DOXYGEN__) +__attribute__ ((section("vectors"))) +#endif +vectors_t _vectors = { + &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, + MemManageVector, BusFaultVector, UsageFaultVector, Vector1C, + Vector20, Vector24, Vector28, SVCallVector, + DebugMonitorVector, Vector34, PendSVVector, SysTickVector, + { + Vector40, Vector44, Vector48, Vector4C, + Vector50, Vector54, Vector58, Vector5C, + Vector60, Vector64, Vector68, Vector6C, + Vector70, Vector74, Vector78, Vector7C, + Vector80, Vector84, Vector88, Vector8C, + Vector90, Vector94, Vector98, Vector9C, + VectorA0, VectorA4, VectorA8, VectorAC, + VectorB0, VectorB4, VectorB8, VectorBC, + VectorC0, VectorC4, VectorC8, VectorCC, + VectorD0, VectorD4, VectorD8, VectorDC, + VectorE0, VectorE4, VectorE8, VectorEC, + VectorF0, VectorF4, VectorF8, VectorFC, + Vector100, Vector104, Vector108, Vector10C, + Vector110, Vector114, Vector118, Vector11C, + Vector120, Vector124 + } +}; + +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +#if !defined(__DOXYGEN__) +__attribute__ ((naked)) +#endif +void _unhandled_exception(void) { + + while (TRUE) + ; +} + +void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); +void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); +void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorCC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorDC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorEC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorFC(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector100(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector104(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector108(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector10C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector110(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector114(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector118(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector11C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector120(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector124(void) __attribute__((weak, alias("_unhandled_exception"))); + +/** @} */ diff --git a/Project/os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h b/Project/os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h new file mode 100644 index 0000000..b7bb6a9 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/ARMCMx/STM32F1xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32F1xx. + * + * @defgroup ARMCMx_STM32F1xx STM32F1xx Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * STM32F1xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F100xB.ld b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F100xB.ld new file mode 100644 index 0000000..e3248fc --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F100xB.ld @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * ST32F100xB memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 128k + ram : org = 0x20000000, len = 8k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xB.ld b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xB.ld new file mode 100644 index 0000000..1ff4ea9 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xB.ld @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * ST32F103xB memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 128k + ram : org = 0x20000000, len = 20k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xE.ld b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xE.ld new file mode 100644 index 0000000..a69953f --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xE.ld @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * ST32F103xE memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 512k + ram : org = 0x20000000, len = 64k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG.ld b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG.ld new file mode 100644 index 0000000..74c56a0 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG.ld @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * ST32F103xG memory setup. + */ +__main_stack_size__ = 0x0600; +__process_stack_size__ = 0x0600; + +MEMORY +{ + flash : org = 0x08000000, len = 384k + ram : org = 0x20000000, len = 64k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG_1M_96K.ld b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG_1M_96K.ld new file mode 100644 index 0000000..b24efe7 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG_1M_96K.ld @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * ST32F103xG memory setup. + */ +__main_stack_size__ = 0x0A00; +__process_stack_size__ = 0x0A00; + +MEMORY +{ + flash : org = 0x08000000, len = 1M + ram : org = 0x20000000, len = 96k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG_386K_64K.ld b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG_386K_64K.ld new file mode 100644 index 0000000..52b7deb --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG_386K_64K.ld @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * ST32F103xG memory setup. + */ +__main_stack_size__ = 0x0A00; +__process_stack_size__ = 0x0A00; + +MEMORY +{ + flash : org = 0x08000000, len = 384k + ram : org = 0x20000000, len = 64k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG_768K_96K.ld b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG_768K_96K.ld new file mode 100644 index 0000000..1dcff94 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG_768K_96K.ld @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * ST32F103xG memory setup. + */ +__main_stack_size__ = 0x0200; +__process_stack_size__ = 0x0A00; + +MEMORY +{ + flash : org = 0x08000000, len = 768K + ram : org = 0x20000000, len = 96k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG_768K_96K_WISMARTINO.ld b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG_768K_96K_WISMARTINO.ld new file mode 100644 index 0000000..0b70601 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG_768K_96K_WISMARTINO.ld @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * ST32F103xG memory setup. + */ +__main_stack_size__ = 0x0A00; +__process_stack_size__ = 0x0A00; + +MEMORY +{ + flash : org = 0x08008000, len = 736K + ram : org = 0x20000000, len = 96k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG_768K_96K_bl.ld b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG_768K_96K_bl.ld new file mode 100644 index 0000000..3d957b4 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG_768K_96K_bl.ld @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * ST32F103xG memory setup. + */ +__main_stack_size__ = 0x0A00; +__process_stack_size__ = 0x0A00; + +MEMORY +{ + flash : org = 0x08003000, len = 768K + ram : org = 0x20000000, len = 96k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG_768K_96K_bootloader_ota.ld b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG_768K_96K_bootloader_ota.ld new file mode 100644 index 0000000..54bf03c --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG_768K_96K_bootloader_ota.ld @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * ST32F103xG memory setup. + */ +__main_stack_size__ = 0x0200; +__process_stack_size__ = 0x0A00; + +MEMORY +{ + flash : org = 0x08042800, len = 768K + ram : org = 0x20000000, len = 96k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F107xC.ld b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F107xC.ld new file mode 100644 index 0000000..e70774b --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F107xC.ld @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * ST32F107xC memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 256k + ram : org = 0x20000000, len = 64k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/Project/os/ports/GCC/ARMCMx/STM32F1xx/port.mk b/Project/os/ports/GCC/ARMCMx/STM32F1xx/port.mk new file mode 100644 index 0000000..1ba6c67 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F1xx/port.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/RT Cortex-M3 STM32 port files. +PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ + ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ + ${CHIBIOS}/os/ports/common/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F1xx + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F1xx/ld diff --git a/Project/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c b/Project/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c new file mode 100644 index 0000000..0735637 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c @@ -0,0 +1,339 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/ARMCMx/STM32F1xx/vectors.c + * @brief Interrupt vectors for the STM32F1xx family. + * + * @defgroup ARMCMx_STM32F1xx_VECTORS STM32F1xx Interrupt Vectors + * @ingroup ARMCMx_SPECIFIC + * @details Interrupt vectors for the STM32F1xx family. + * One of the following macros must be defined on the + * compiler command line or in a file named board.h: + * - @p STM32F10X_LD + * - @p STM32F10X_LD_VL + * - @p STM32F10X_MD + * - @p STM32F10X_MD_VL + * - @p STM32F10X_HD + * - @p STM32F10X_XL + * - @p STM32F10X_CL + * . + * This is required in order to include a vectors table with + * the correct length for the specified STM32 model. + * @{ + */ + +#include "ch.h" + +#if !defined(STM32F10X_LD) && !defined(STM32F10X_LD_VL) && \ + !defined(STM32F10X_MD) && !defined(STM32F10X_MD_VL) && \ + !defined(STM32F10X_HD) && !defined(STM32F10X_XL) && \ + !defined(STM32F10X_CL) +#include "board.h" +#endif + +#if defined(STM32F10X_MD_VL) || defined(__DOXYGEN__) +#define NUM_VECTORS 46 +#elif defined(STM32F10X_HD) || defined(STM32F10X_XL) +#define NUM_VECTORS 60 +#elif defined(STM32F10X_CL) +#define NUM_VECTORS 68 +#else +#define NUM_VECTORS 43 +#endif + +/** + * @brief Type of an IRQ vector. + */ +typedef void (*irq_vector_t)(void); + +/** + * @brief Type of a structure representing the whole vectors table. + */ +typedef struct { + uint32_t *init_stack; + irq_vector_t reset_vector; + irq_vector_t nmi_vector; + irq_vector_t hardfault_vector; + irq_vector_t memmanage_vector; + irq_vector_t busfault_vector; + irq_vector_t usagefault_vector; + irq_vector_t vector1c; + irq_vector_t vector20; + irq_vector_t vector24; + irq_vector_t vector28; + irq_vector_t svcall_vector; + irq_vector_t debugmonitor_vector; + irq_vector_t vector34; + irq_vector_t pendsv_vector; + irq_vector_t systick_vector; + irq_vector_t vectors[NUM_VECTORS]; +} vectors_t; + +#if !defined(__DOXYGEN__) +extern uint32_t __main_stack_end__; +extern void ResetHandler(void); +extern void NMIVector(void); +extern void HardFaultVector(void); +extern void MemManageVector(void); +extern void BusFaultVector(void); +extern void UsageFaultVector(void); +extern void Vector1C(void); +extern void Vector20(void); +extern void Vector24(void); +extern void Vector28(void); +extern void SVCallVector(void); +extern void DebugMonitorVector(void); +extern void Vector34(void); +extern void PendSVVector(void); +extern void SysTickVector(void); +extern void Vector40(void); +extern void Vector44(void); +extern void Vector48(void); +extern void Vector4C(void); +extern void Vector50(void); +extern void Vector54(void); +extern void Vector58(void); +extern void Vector5C(void); +extern void Vector60(void); +extern void Vector64(void); +extern void Vector68(void); +extern void Vector6C(void); +extern void Vector70(void); +extern void Vector74(void); +extern void Vector78(void); +extern void Vector7C(void); +extern void Vector80(void); +extern void Vector84(void); +extern void Vector88(void); +extern void Vector8C(void); +extern void Vector90(void); +extern void Vector94(void); +extern void Vector98(void); +extern void Vector9C(void); +extern void VectorA0(void); +extern void VectorA4(void); +extern void VectorA8(void); +extern void VectorAC(void); +extern void VectorB0(void); +extern void VectorB4(void); +extern void VectorB8(void); +extern void VectorBC(void); +extern void VectorC0(void); +extern void VectorC4(void); +extern void VectorC8(void); +extern void VectorCC(void); +extern void VectorD0(void); +extern void VectorD4(void); +extern void VectorD8(void); +extern void VectorDC(void); +extern void VectorE0(void); +extern void VectorE4(void); +extern void VectorE8(void); +#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \ + defined(STM32F10X_XL) || defined(STM32F10X_CL) +extern void VectorEC(void); +extern void VectorF0(void); +extern void VectorF4(void); +#endif +#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL) +extern void VectorF8(void); +extern void VectorFC(void); +extern void Vector100(void); +extern void Vector104(void); +extern void Vector108(void); +extern void Vector10C(void); +extern void Vector110(void); +extern void Vector114(void); +extern void Vector118(void); +extern void Vector11C(void); +extern void Vector120(void); +extern void Vector124(void); +extern void Vector128(void); +extern void Vector12C(void); +#endif +#if defined(STM32F10X_CL) +extern void Vector130(void); +extern void Vector134(void); +extern void Vector138(void); +extern void Vector13C(void); +extern void Vector140(void); +extern void Vector144(void); +extern void Vector148(void); +extern void Vector14C(void); +#endif +#endif + +/** + * @brief STM32 vectors table. + */ +#if !defined(__DOXYGEN__) +__attribute__ ((section("vectors"))) +#endif +vectors_t _vectors = { + &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, + MemManageVector, BusFaultVector, UsageFaultVector, Vector1C, + Vector20, Vector24, Vector28, SVCallVector, + DebugMonitorVector, Vector34, PendSVVector, SysTickVector, + { + Vector40, Vector44, Vector48, Vector4C, + Vector50, Vector54, Vector58, Vector5C, + Vector60, Vector64, Vector68, Vector6C, + Vector70, Vector74, Vector78, Vector7C, + Vector80, Vector84, Vector88, Vector8C, + Vector90, Vector94, Vector98, Vector9C, + VectorA0, VectorA4, VectorA8, VectorAC, + VectorB0, VectorB4, VectorB8, VectorBC, + VectorC0, VectorC4, VectorC8, VectorCC, + VectorD0, VectorD4, VectorD8, VectorDC, + VectorE0, VectorE4, VectorE8, +#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \ + defined(STM32F10X_XL) || defined(STM32F10X_CL) + VectorEC, VectorF0, VectorF4, +#endif +#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL) + VectorF8, VectorFC, Vector100, Vector104, + Vector108, Vector10C, Vector110, Vector114, + Vector118, Vector11C, Vector120, Vector124, + Vector128, Vector12C, +#endif +#if defined(STM32F10X_CL) + Vector130, Vector134, Vector138, Vector13C, + Vector140, Vector144, Vector148, Vector14C +#endif + } +}; + +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +#if !defined(__DOXYGEN__) +__attribute__ ((naked)) +#endif +void print(const char *fmt, ...); +void _unhandled_exception(void) { + + print("ERROR:_unhandled_exception\n"); + while (TRUE) + ; +} + +void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); +void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); +void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorCC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorDC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE8(void) __attribute__((weak, alias("_unhandled_exception"))); +#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \ + defined(STM32F10X_XL) || defined(STM32F10X_CL) +void VectorEC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF4(void) __attribute__((weak, alias("_unhandled_exception"))); +#endif +#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL) +void VectorF8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorFC(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector100(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector104(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector108(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector10C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector110(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector114(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector118(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector11C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector120(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector124(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector128(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector12C(void) __attribute__((weak, alias("_unhandled_exception"))); +#endif +#if defined(STM32F10X_CL) +void Vector130(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector134(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector138(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector13C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector140(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector144(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector148(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector14C(void) __attribute__((weak, alias("_unhandled_exception"))); +#endif + +/** @} */ diff --git a/Project/os/ports/GCC/ARMCMx/STM32F2xx/cmparams.h b/Project/os/ports/GCC/ARMCMx/STM32F2xx/cmparams.h new file mode 100644 index 0000000..f5ff586 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F2xx/cmparams.h @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/ARMCMx/STM32F2xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32F2xx. + * + * @defgroup ARMCMx_STM32F2xx STM32F2xx Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M4 specific parameters for the + * STM32F2xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/ARMCMx/STM32F2xx/ld/STM32F205xB.ld b/Project/os/ports/GCC/ARMCMx/STM32F2xx/ld/STM32F205xB.ld new file mode 100644 index 0000000..d8e14e5 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F2xx/ld/STM32F205xB.ld @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * ST32F205xB memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 128k + ram : org = 0x20000000, len = 64k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/Project/os/ports/GCC/ARMCMx/STM32F2xx/ld/STM32F207xG.ld b/Project/os/ports/GCC/ARMCMx/STM32F2xx/ld/STM32F207xG.ld new file mode 100644 index 0000000..38618f6 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F2xx/ld/STM32F207xG.ld @@ -0,0 +1,158 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * ST32F207xG memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 1M + ram : org = 0x20000000, len = 112k + ethram : org = 0x2001C000, len = 16k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/Project/os/ports/GCC/ARMCMx/STM32F2xx/port.mk b/Project/os/ports/GCC/ARMCMx/STM32F2xx/port.mk new file mode 100644 index 0000000..9510416 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F2xx/port.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/RT Cortex-M3 STM32 port files. +PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F2xx/vectors.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ + ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ + ${CHIBIOS}/os/ports/common/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F2xx + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F2xx/ld diff --git a/Project/os/ports/GCC/ARMCMx/STM32F2xx/vectors.c b/Project/os/ports/GCC/ARMCMx/STM32F2xx/vectors.c new file mode 100644 index 0000000..41f7764 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F2xx/vectors.c @@ -0,0 +1,316 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/ARMCMx/STM32F2xx/vectors.c + * @brief Interrupt vectors for the STM32F2xx family. + * + * @defgroup ARMCMx_STM32F2xx_VECTORS STM32F2xx Interrupt Vectors + * @ingroup ARMCMx_SPECIFIC + * @details Interrupt vectors for the STM32F2xx family. + * @{ + */ + +#include "ch.h" + +/** + * @brief Type of an IRQ vector. + */ +typedef void (*irq_vector_t)(void); + +/** + * @brief Type of a structure representing the whole vectors table. + */ +typedef struct { + uint32_t *init_stack; + irq_vector_t reset_vector; + irq_vector_t nmi_vector; + irq_vector_t hardfault_vector; + irq_vector_t memmanage_vector; + irq_vector_t busfault_vector; + irq_vector_t usagefault_vector; + irq_vector_t vector1c; + irq_vector_t vector20; + irq_vector_t vector24; + irq_vector_t vector28; + irq_vector_t svcall_vector; + irq_vector_t debugmonitor_vector; + irq_vector_t vector34; + irq_vector_t pendsv_vector; + irq_vector_t systick_vector; + irq_vector_t vectors[81]; +} vectors_t; + +#if !defined(__DOXYGEN__) +extern uint32_t __main_stack_end__; +extern void ResetHandler(void); +extern void NMIVector(void); +extern void HardFaultVector(void); +extern void MemManageVector(void); +extern void BusFaultVector(void); +extern void UsageFaultVector(void); +extern void Vector1C(void); +extern void Vector20(void); +extern void Vector24(void); +extern void Vector28(void); +extern void SVCallVector(void); +extern void DebugMonitorVector(void); +extern void Vector34(void); +extern void PendSVVector(void); +extern void SysTickVector(void); +extern void Vector40(void); +extern void Vector44(void); +extern void Vector48(void); +extern void Vector4C(void); +extern void Vector50(void); +extern void Vector54(void); +extern void Vector58(void); +extern void Vector5C(void); +extern void Vector60(void); +extern void Vector64(void); +extern void Vector68(void); +extern void Vector6C(void); +extern void Vector70(void); +extern void Vector74(void); +extern void Vector78(void); +extern void Vector7C(void); +extern void Vector80(void); +extern void Vector84(void); +extern void Vector88(void); +extern void Vector8C(void); +extern void Vector90(void); +extern void Vector94(void); +extern void Vector98(void); +extern void Vector9C(void); +extern void VectorA0(void); +extern void VectorA4(void); +extern void VectorA8(void); +extern void VectorAC(void); +extern void VectorB0(void); +extern void VectorB4(void); +extern void VectorB8(void); +extern void VectorBC(void); +extern void VectorC0(void); +extern void VectorC4(void); +extern void VectorC8(void); +extern void VectorCC(void); +extern void VectorD0(void); +extern void VectorD4(void); +extern void VectorD8(void); +extern void VectorDC(void); +extern void VectorE0(void); +extern void VectorE4(void); +extern void VectorE8(void); +extern void VectorEC(void); +extern void VectorF0(void); +extern void VectorF4(void); +extern void VectorF8(void); +extern void VectorFC(void); +extern void Vector100(void); +extern void Vector104(void); +extern void Vector108(void); +extern void Vector10C(void); +extern void Vector110(void); +extern void Vector114(void); +extern void Vector118(void); +extern void Vector11C(void); +extern void Vector120(void); +extern void Vector124(void); +extern void Vector128(void); +extern void Vector12C(void); +extern void Vector130(void); +extern void Vector134(void); +extern void Vector138(void); +extern void Vector13C(void); +extern void Vector140(void); +extern void Vector144(void); +extern void Vector148(void); +extern void Vector14C(void); +extern void Vector150(void); +extern void Vector154(void); +extern void Vector158(void); +extern void Vector15C(void); +extern void Vector160(void); +extern void Vector164(void); +extern void Vector168(void); +extern void Vector16C(void); +extern void Vector170(void); +extern void Vector174(void); +extern void Vector178(void); +extern void Vector17C(void); +extern void Vector180(void); +#endif + +/** + * @brief STM32 vectors table. + */ +#if !defined(__DOXYGEN__) +__attribute__ ((section("vectors"))) +#endif +vectors_t _vectors = { + &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, + MemManageVector, BusFaultVector, UsageFaultVector, Vector1C, + Vector20, Vector24, Vector28, SVCallVector, + DebugMonitorVector, Vector34, PendSVVector, SysTickVector, + { + Vector40, Vector44, Vector48, Vector4C, + Vector50, Vector54, Vector58, Vector5C, + Vector60, Vector64, Vector68, Vector6C, + Vector70, Vector74, Vector78, Vector7C, + Vector80, Vector84, Vector88, Vector8C, + Vector90, Vector94, Vector98, Vector9C, + VectorA0, VectorA4, VectorA8, VectorAC, + VectorB0, VectorB4, VectorB8, VectorBC, + VectorC0, VectorC4, VectorC8, VectorCC, + VectorD0, VectorD4, VectorD8, VectorDC, + VectorE0, VectorE4, VectorE8, VectorEC, + VectorF0, VectorF4, VectorF8, VectorFC, + Vector100, Vector104, Vector108, Vector10C, + Vector110, Vector114, Vector118, Vector11C, + Vector120, Vector124, Vector128, Vector12C, + Vector130, Vector134, Vector138, Vector13C, + Vector140, Vector144, Vector148, Vector14C, + Vector150, Vector154, Vector158, Vector15C, + Vector160, Vector164, Vector168, Vector16C, + Vector170, Vector174, Vector178, Vector17C, + Vector180 + } +}; + +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +#if !defined(__DOXYGEN__) +__attribute__ ((naked)) +#endif +void _unhandled_exception(void) { + + while (TRUE) + ; +} + +void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); +void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); +void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorCC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorDC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorEC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorFC(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector100(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector104(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector108(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector10C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector110(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector114(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector118(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector11C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector120(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector124(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector128(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector12C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector130(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector134(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector138(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector13C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector140(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector144(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector148(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector14C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector150(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector154(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector158(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector15C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector160(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector164(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector168(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector16C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector170(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector174(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector178(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector17C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector180(void) __attribute__((weak, alias("_unhandled_exception"))); + +/** @} */ diff --git a/Project/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h b/Project/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h new file mode 100644 index 0000000..b411499 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/ARMCMx/STM32F4xx/cmparams.h + * @brief ARM Cortex-M4 parameters for the STM32F4xx. + * + * @defgroup ARMCMx_STM32F4xx STM32F4xx Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M4 specific parameters for the + * STM32F4xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M4 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU TRUE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F405xG.ld b/Project/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F405xG.ld new file mode 100644 index 0000000..f094d7b --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F405xG.ld @@ -0,0 +1,159 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * ST32F405xG memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 1M + ram : org = 0x20000000, len = 112k + ethram : org = 0x2001C000, len = 16k + ccmram : org = 0x10000000, len = 64k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/Project/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG.ld b/Project/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG.ld new file mode 100644 index 0000000..e7690fe --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG.ld @@ -0,0 +1,167 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * ST32F407xG memory setup. + */ +__main_stack_size__ = 0x1400; +__process_stack_size__ = 0x1400; + +MEMORY +{ + flash : org = 0x08000000, len = 1M + ram : org = 0x20000000, len = 128k + ccmram : org = 0x10000000, len = 64k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .ccm (NOLOAD): + { + PROVIDE(_cmm_start = .); + . = ALIGN(4); + *(.ccm) + . = ALIGN(4); + PROVIDE(_cmmend = .); + } > ccmram + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/Project/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG_CCM.ld b/Project/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG_CCM.ld new file mode 100644 index 0000000..4c60664 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG_CCM.ld @@ -0,0 +1,179 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * ST32F407xG memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 1M + ram : org = 0x20000000, len = 128k + ccmram : org = 0x10000000, len = 64k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ccmram + + .ccm : + { + PROVIDE(_cmm_start = .); + . = ALIGN(4); + *(.bss.mainthread.*) + . = ALIGN(4); + *(.bss._idle_thread_wa) + . = ALIGN(4); + *(.bss.rlist) + . = ALIGN(4); + *(.bss.vtlist) + . = ALIGN(4); + *(.bss.endmem) + . = ALIGN(4); + *(.bss.nextmem) + . = ALIGN(4); + *(.bss.default_heap) + . = ALIGN(4); + PROVIDE(_cmmend = .); + } > ccmram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/Project/os/ports/GCC/ARMCMx/STM32F4xx/port.mk b/Project/os/ports/GCC/ARMCMx/STM32F4xx/port.mk new file mode 100644 index 0000000..743f825 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F4xx/port.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/RT Cortex-M4 STM32 port files. +PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ + ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ + ${CHIBIOS}/os/ports/common/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F4xx + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F4xx/ld diff --git a/Project/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c b/Project/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c new file mode 100644 index 0000000..56a7870 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c @@ -0,0 +1,318 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/ARMCMx/STM32F4xx/vectors.c + * @brief Interrupt vectors for the STM32F4xx family. + * + * @defgroup ARMCMx_STM32F4xx_VECTORS STM32F4xx Interrupt Vectors + * @ingroup ARMCMx_SPECIFIC + * @details Interrupt vectors for the STM32F4xx family. + * @{ + */ + +#include "ch.h" + +/** + * @brief Type of an IRQ vector. + */ +typedef void (*irq_vector_t)(void); + +/** + * @brief Type of a structure representing the whole vectors table. + */ +typedef struct { + uint32_t *init_stack; + irq_vector_t reset_vector; + irq_vector_t nmi_vector; + irq_vector_t hardfault_vector; + irq_vector_t memmanage_vector; + irq_vector_t busfault_vector; + irq_vector_t usagefault_vector; + irq_vector_t vector1c; + irq_vector_t vector20; + irq_vector_t vector24; + irq_vector_t vector28; + irq_vector_t svcall_vector; + irq_vector_t debugmonitor_vector; + irq_vector_t vector34; + irq_vector_t pendsv_vector; + irq_vector_t systick_vector; + irq_vector_t vectors[82]; +} vectors_t; + +#if !defined(__DOXYGEN__) +extern uint32_t __main_stack_end__; +extern void ResetHandler(void); +extern void NMIVector(void); +extern void HardFaultVector(void); +extern void MemManageVector(void); +extern void BusFaultVector(void); +extern void UsageFaultVector(void); +extern void Vector1C(void); +extern void Vector20(void); +extern void Vector24(void); +extern void Vector28(void); +extern void SVCallVector(void); +extern void DebugMonitorVector(void); +extern void Vector34(void); +extern void PendSVVector(void); +extern void SysTickVector(void); +extern void Vector40(void); +extern void Vector44(void); +extern void Vector48(void); +extern void Vector4C(void); +extern void Vector50(void); +extern void Vector54(void); +extern void Vector58(void); +extern void Vector5C(void); +extern void Vector60(void); +extern void Vector64(void); +extern void Vector68(void); +extern void Vector6C(void); +extern void Vector70(void); +extern void Vector74(void); +extern void Vector78(void); +extern void Vector7C(void); +extern void Vector80(void); +extern void Vector84(void); +extern void Vector88(void); +extern void Vector8C(void); +extern void Vector90(void); +extern void Vector94(void); +extern void Vector98(void); +extern void Vector9C(void); +extern void VectorA0(void); +extern void VectorA4(void); +extern void VectorA8(void); +extern void VectorAC(void); +extern void VectorB0(void); +extern void VectorB4(void); +extern void VectorB8(void); +extern void VectorBC(void); +extern void VectorC0(void); +extern void VectorC4(void); +extern void VectorC8(void); +extern void VectorCC(void); +extern void VectorD0(void); +extern void VectorD4(void); +extern void VectorD8(void); +extern void VectorDC(void); +extern void VectorE0(void); +extern void VectorE4(void); +extern void VectorE8(void); +extern void VectorEC(void); +extern void VectorF0(void); +extern void VectorF4(void); +extern void VectorF8(void); +extern void VectorFC(void); +extern void Vector100(void); +extern void Vector104(void); +extern void Vector108(void); +extern void Vector10C(void); +extern void Vector110(void); +extern void Vector114(void); +extern void Vector118(void); +extern void Vector11C(void); +extern void Vector120(void); +extern void Vector124(void); +extern void Vector128(void); +extern void Vector12C(void); +extern void Vector130(void); +extern void Vector134(void); +extern void Vector138(void); +extern void Vector13C(void); +extern void Vector140(void); +extern void Vector144(void); +extern void Vector148(void); +extern void Vector14C(void); +extern void Vector150(void); +extern void Vector154(void); +extern void Vector158(void); +extern void Vector15C(void); +extern void Vector160(void); +extern void Vector164(void); +extern void Vector168(void); +extern void Vector16C(void); +extern void Vector170(void); +extern void Vector174(void); +extern void Vector178(void); +extern void Vector17C(void); +extern void Vector180(void); +extern void Vector184(void); +#endif + +/** + * @brief STM32 vectors table. + */ +#if !defined(__DOXYGEN__) +__attribute__ ((section("vectors"))) +#endif +vectors_t _vectors = { + &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, + MemManageVector, BusFaultVector, UsageFaultVector, Vector1C, + Vector20, Vector24, Vector28, SVCallVector, + DebugMonitorVector, Vector34, PendSVVector, SysTickVector, + { + Vector40, Vector44, Vector48, Vector4C, + Vector50, Vector54, Vector58, Vector5C, + Vector60, Vector64, Vector68, Vector6C, + Vector70, Vector74, Vector78, Vector7C, + Vector80, Vector84, Vector88, Vector8C, + Vector90, Vector94, Vector98, Vector9C, + VectorA0, VectorA4, VectorA8, VectorAC, + VectorB0, VectorB4, VectorB8, VectorBC, + VectorC0, VectorC4, VectorC8, VectorCC, + VectorD0, VectorD4, VectorD8, VectorDC, + VectorE0, VectorE4, VectorE8, VectorEC, + VectorF0, VectorF4, VectorF8, VectorFC, + Vector100, Vector104, Vector108, Vector10C, + Vector110, Vector114, Vector118, Vector11C, + Vector120, Vector124, Vector128, Vector12C, + Vector130, Vector134, Vector138, Vector13C, + Vector140, Vector144, Vector148, Vector14C, + Vector150, Vector154, Vector158, Vector15C, + Vector160, Vector164, Vector168, Vector16C, + Vector170, Vector174, Vector178, Vector17C, + Vector180, Vector184 + } +}; + +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +#if !defined(__DOXYGEN__) +__attribute__ ((naked)) +#endif +void _unhandled_exception(void) { + + while (TRUE) + ; +} + +void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); +void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); +void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorCC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorDC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorEC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorFC(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector100(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector104(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector108(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector10C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector110(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector114(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector118(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector11C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector120(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector124(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector128(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector12C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector130(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector134(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector138(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector13C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector140(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector144(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector148(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector14C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector150(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector154(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector158(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector15C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector160(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector164(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector168(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector16C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector170(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector174(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector178(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector17C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector180(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector184(void) __attribute__((weak, alias("_unhandled_exception"))); + +/** @} */ diff --git a/Project/os/ports/GCC/ARMCMx/STM32L1xx/cmparams.h b/Project/os/ports/GCC/ARMCMx/STM32L1xx/cmparams.h new file mode 100644 index 0000000..f876430 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32L1xx/cmparams.h @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/ARMCMx/STM32L1xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32L1xx. + * + * @defgroup ARMCMx_STM32L1xx STM32L1xx Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * STM32L1xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/ARMCMx/STM32L1xx/ld/STM32L152xB.ld b/Project/os/ports/GCC/ARMCMx/STM32L1xx/ld/STM32L152xB.ld new file mode 100644 index 0000000..407f78f --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32L1xx/ld/STM32L152xB.ld @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * ST32L1152xB memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 128k + ram : org = 0x20000000, len = 16k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/Project/os/ports/GCC/ARMCMx/STM32L1xx/port.mk b/Project/os/ports/GCC/ARMCMx/STM32L1xx/port.mk new file mode 100644 index 0000000..93b1775 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32L1xx/port.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/RT Cortex-M3 STM32L1xx port files. +PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32L1xx/vectors.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ + ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ + ${CHIBIOS}/os/ports/common/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32L1xx + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32L1xx/ld diff --git a/Project/os/ports/GCC/ARMCMx/STM32L1xx/vectors.c b/Project/os/ports/GCC/ARMCMx/STM32L1xx/vectors.c new file mode 100644 index 0000000..44e3f2c --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/STM32L1xx/vectors.c @@ -0,0 +1,235 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/ARMCMx/STM32L1xx/vectors.c + * @brief Interrupt vectors for the STM32 family. + * + * @defgroup ARMCMx_STM32L1xx_VECTORS STM32L1xx Interrupt Vectors + * @ingroup ARMCMx_SPECIFIC + * @details Interrupt vectors for the STM32L1xx family. + * @{ + */ + +#include "ch.h" + +/** + * @brief Type of an IRQ vector. + */ +typedef void (*irq_vector_t)(void); + +/** + * @brief Type of a structure representing the whole vectors table. + */ +typedef struct { + uint32_t *init_stack; + irq_vector_t reset_vector; + irq_vector_t nmi_vector; + irq_vector_t hardfault_vector; + irq_vector_t memmanage_vector; + irq_vector_t busfault_vector; + irq_vector_t usagefault_vector; + irq_vector_t vector1c; + irq_vector_t vector20; + irq_vector_t vector24; + irq_vector_t vector28; + irq_vector_t svcall_vector; + irq_vector_t debugmonitor_vector; + irq_vector_t vector34; + irq_vector_t pendsv_vector; + irq_vector_t systick_vector; + irq_vector_t vectors[45]; +} vectors_t; + +#if !defined(__DOXYGEN__) +extern uint32_t __main_stack_end__; +extern void ResetHandler(void); +extern void NMIVector(void); +extern void HardFaultVector(void); +extern void MemManageVector(void); +extern void BusFaultVector(void); +extern void UsageFaultVector(void); +extern void Vector1C(void); +extern void Vector20(void); +extern void Vector24(void); +extern void Vector28(void); +extern void SVCallVector(void); +extern void DebugMonitorVector(void); +extern void Vector34(void); +extern void PendSVVector(void); +extern void SysTickVector(void); +extern void Vector40(void); +extern void Vector44(void); +extern void Vector48(void); +extern void Vector4C(void); +extern void Vector50(void); +extern void Vector54(void); +extern void Vector58(void); +extern void Vector5C(void); +extern void Vector60(void); +extern void Vector64(void); +extern void Vector68(void); +extern void Vector6C(void); +extern void Vector70(void); +extern void Vector74(void); +extern void Vector78(void); +extern void Vector7C(void); +extern void Vector80(void); +extern void Vector84(void); +extern void Vector88(void); +extern void Vector8C(void); +extern void Vector90(void); +extern void Vector94(void); +extern void Vector98(void); +extern void Vector9C(void); +extern void VectorA0(void); +extern void VectorA4(void); +extern void VectorA8(void); +extern void VectorAC(void); +extern void VectorB0(void); +extern void VectorB4(void); +extern void VectorB8(void); +extern void VectorBC(void); +extern void VectorC0(void); +extern void VectorC4(void); +extern void VectorC8(void); +extern void VectorCC(void); +extern void VectorD0(void); +extern void VectorD4(void); +extern void VectorD8(void); +extern void VectorDC(void); +extern void VectorE0(void); +extern void VectorE4(void); +extern void VectorE8(void); +extern void VectorEC(void); +extern void VectorF0(void); +#endif /* !defined(__DOXYGEN__) */ + +/** + * @brief STM32L1xx vectors table. + */ +#if !defined(__DOXYGEN__) +__attribute__ ((section("vectors"))) +#endif +vectors_t _vectors = { + &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, + MemManageVector, BusFaultVector, UsageFaultVector, Vector1C, + Vector20, Vector24, Vector28, SVCallVector, + DebugMonitorVector, Vector34, PendSVVector, SysTickVector, + { + Vector40, Vector44, Vector48, Vector4C, + Vector50, Vector54, Vector58, Vector5C, + Vector60, Vector64, Vector68, Vector6C, + Vector70, Vector74, Vector78, Vector7C, + Vector80, Vector84, Vector88, Vector8C, + Vector90, Vector94, Vector98, Vector9C, + VectorA0, VectorA4, VectorA8, VectorAC, + VectorB0, VectorB4, VectorB8, VectorBC, + VectorC0, VectorC4, VectorC8, VectorCC, + VectorD0, VectorD4, VectorD8, VectorDC, + VectorE0, VectorE4, VectorE8, VectorEC, + VectorF0 + } +}; + +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +#if !defined(__DOXYGEN__) +__attribute__ ((naked)) +#endif +void _unhandled_exception(void) { + + while (TRUE) + ; +} + +void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); +void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); +void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorC8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorCC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorD8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorDC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorE8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorEC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorF0(void) __attribute__((weak, alias("_unhandled_exception"))); + +/** @} */ diff --git a/Project/os/ports/GCC/ARMCMx/chcore.c b/Project/os/ports/GCC/ARMCMx/chcore.c new file mode 100644 index 0000000..5c47649 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/chcore.c @@ -0,0 +1,53 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/ARMCMx/chcore.c + * @brief ARM Cortex-Mx port code. + * + * @addtogroup ARMCMx_CORE + * @{ + */ + +#include "ch.h" + +/** + * @brief Halts the system. + * @note The function is declared as a weak symbol, it is possible + * to redefine it in your application code. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** @} */ diff --git a/Project/os/ports/GCC/ARMCMx/chcore.h b/Project/os/ports/GCC/ARMCMx/chcore.h new file mode 100644 index 0000000..254ded0 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/chcore.h @@ -0,0 +1,189 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/ARMCMx/chcore.h + * @brief ARM Cortex-Mx port macros and structures. + * + * @addtogroup ARMCMx_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +/*===========================================================================*/ +/* Port constants (common). */ +/*===========================================================================*/ + +/* Added to make the header stand-alone when included from asm.*/ +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE (!FALSE) +#endif + +#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */ +#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */ +#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */ +#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */ + +/* Inclusion of the Cortex-Mx implementation specific parameters.*/ +#include "cmparams.h" + +/* Cortex model check, only M0 and M3 supported right now.*/ +#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) || \ + (CORTEX_MODEL == CORTEX_M4) +#elif (CORTEX_MODEL == CORTEX_M1) +#warning "untested Cortex-M model" +#else +#error "unknown or unsupported Cortex-M model" +#endif + +/** + * @brief Total priority levels. + */ +#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS) + +/** + * @brief Minimum priority level. + * @details This minimum priority level is calculated from the number of + * priority bits supported by the specific Cortex-Mx implementation. + */ +#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1) + +/** + * @brief Maximum priority level. + * @details The maximum allowed priority level is always zero. + */ +#define CORTEX_MAXIMUM_PRIORITY 0 + +/*===========================================================================*/ +/* Port macros (common). */ +/*===========================================================================*/ + +/** + * @brief Priority level verification macro. + */ +#define CORTEX_IS_VALID_PRIORITY(n) \ + (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS)) + +/** + * @brief Priority level to priority mask conversion macro. + */ +#define CORTEX_PRIORITY_MASK(n) \ + ((n) << (8 - CORTEX_PRIORITY_BITS)) + +/*===========================================================================*/ +/* Port configurable parameters (common). */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port derived parameters (common). */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port exported info (common). */ +/*===========================================================================*/ + +/** + * @brief Macro defining a generic ARM architecture. + */ +#define CH_ARCHITECTURE_ARM + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "GCC " __VERSION__ + +/*===========================================================================*/ +/* Port implementation part (common). */ +/*===========================================================================*/ + +/* Includes the sub-architecture-specific part.*/ +#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1) +#include "chcore_v6m.h" +#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4) +#include "chcore_v7m.h" +#endif + +#if !defined(_FROM_ASM_) + +#include "nvic.h" + +/* The following declarations are there just for Doxygen documentation, the + real declarations are inside the sub-headers.*/ +#if defined(__DOXYGEN__) + +/** + * @brief Stack and memory alignment enforcement. + * @note In this architecture the stack alignment is enforced to 64 bits, + * 32 bits alignment is supported by hardware but deprecated by ARM, + * the implementation choice is to not offer the option. + */ +typedef uint64_t stkalign_t; + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + * @note It is implemented to match the Cortex-Mx exception context. + */ +struct extctx {}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching. + */ +struct intctx {}; + +#endif /* defined(__DOXYGEN__) */ + +/** + * @brief Excludes the default @p chSchIsPreemptionRequired()implementation. + */ +#define PORT_OPTIMIZED_ISPREEMPTIONREQUIRED + +#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__) +/** + * @brief Inline-able version of this kernel function. + */ +#define chSchIsPreemptionRequired() \ + (rlist.r_preempt ? firstprio(&rlist.r_queue) > currp->p_prio : \ + firstprio(&rlist.r_queue) >= currp->p_prio) +#else /* CH_TIME_QUANTUM == 0 */ +#define chSchIsPreemptionRequired() \ + (firstprio(&rlist.r_queue) > currp->p_prio) +#endif /* CH_TIME_QUANTUM == 0 */ + +#endif /* _FROM_ASM_ */ + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/ARMCMx/chcore_v6m.c b/Project/os/ports/GCC/ARMCMx/chcore_v6m.c new file mode 100644 index 0000000..4c152cf --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/chcore_v6m.c @@ -0,0 +1,206 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/ARMCMx/chcore_v6m.c + * @brief ARMv6-M architecture port code. + * + * @addtogroup ARMCMx_V6M_CORE + * @{ + */ + +#include "ch.h" + +/*===========================================================================*/ +/* Port interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief System Timer vector. + * @details This interrupt is used as system tick. + * @note The timer must be initialized in the startup code. + */ +CH_IRQ_HANDLER(SysTickVector) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +/** + * @brief NMI vector. + * @details The NMI vector is used for exception mode re-entering after a + * context switch. + */ +void NMIVector(void) { + register struct extctx *ctxp; + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); + ctxp++; + asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); + port_unlock_from_isr(); +} +#endif /* !CORTEX_ALTERNATE_SWITCH */ + +#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +/** + * @brief PendSV vector. + * @details The PendSV vector is used for exception mode re-entering after a + * context switch. + */ +void PendSVVector(void) { + register struct extctx *ctxp; + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); + ctxp++; + asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); +} +#endif /* CORTEX_ALTERNATE_SWITCH */ + +/*===========================================================================*/ +/* Port exported functions. */ +/*===========================================================================*/ + +/** + * @brief IRQ epilogue code. + * + * @param[in] lr value of the @p LR register on ISR entry + */ +void _port_irq_epilogue(regarm_t lr) { + + if (lr != (regarm_t)0xFFFFFFF1) { + register struct extctx *ctxp; + + port_lock_from_isr(); + /* Adding an artificial exception return context, there is no need to + populate it fully.*/ + asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); + ctxp--; + asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); + ctxp->xpsr = (regarm_t)0x01000000; + + /* The exit sequence is different depending on if a preemption is + required or not.*/ + if (chSchIsPreemptionRequired()) { + /* Preemption is required we need to enforce a context switch.*/ + ctxp->pc = _port_switch_from_isr; + } + else { + /* Preemption not required, we just need to exit the exception + atomically.*/ + ctxp->pc = _port_exit_from_isr; + } + + /* Note, returning without unlocking is intentional, this is done in + order to keep the rest of the context switching atomic.*/ + } +} + +/** + * @brief Post-IRQ switch code. + * @details The switch is performed in thread context then an NMI exception + * is enforced in order to return to the exact point before the + * preemption. + */ +#if !defined(__DOXYGEN__) +__attribute__((naked)) +#endif +void _port_switch_from_isr(void) { + + dbg_check_lock(); + chSchDoReschedule(); + dbg_check_unlock(); + asm volatile ("_port_exit_from_isr:" : : : "memory"); +#if CORTEX_ALTERNATE_SWITCH + SCB_ICSR = ICSR_PENDSVSET; + port_unlock(); +#else + SCB_ICSR = ICSR_NMIPENDSET; +#endif + /* The following loop should never be executed, the exception will kick in + immediately.*/ + while (TRUE) + ; +} + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if !defined(__DOXYGEN__) +__attribute__((naked)) +#endif +void _port_switch(Thread *ntp, Thread *otp) { + register struct intctx *r13 asm ("r13"); + + asm volatile ("push {r4, r5, r6, r7, lr} \n\t" + "mov r4, r8 \n\t" + "mov r5, r9 \n\t" + "mov r6, r10 \n\t" + "mov r7, r11 \n\t" + "push {r4, r5, r6, r7}" : : : "memory"); + + otp->p_ctx.r13 = r13; + r13 = ntp->p_ctx.r13; + + asm volatile ("pop {r4, r5, r6, r7} \n\t" + "mov r8, r4 \n\t" + "mov r9, r5 \n\t" + "mov r10, r6 \n\t" + "mov r11, r7 \n\t" + "pop {r4, r5, r6, r7, pc}" : : "r" (r13) : "memory"); +} + +/** + * @brief Start a thread by invoking its work function. + * @details If the work function returns @p chThdExit() is automatically + * invoked. + */ +void _port_thread_start(void) { + + chSysUnlock(); + asm volatile ("mov r0, r5 \n\t" + "blx r4 \n\t" + "bl chThdExit"); +} + +/** @} */ diff --git a/Project/os/ports/GCC/ARMCMx/chcore_v6m.h b/Project/os/ports/GCC/ARMCMx/chcore_v6m.h new file mode 100644 index 0000000..b381949 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/chcore_v6m.h @@ -0,0 +1,376 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/ARMCMx/chcore_v6m.h + * @brief ARMv6-M architecture port macros and structures. + * + * @addtogroup ARMCMx_V6M_CORE + * @{ + */ + +#ifndef _CHCORE_V6M_H_ +#define _CHCORE_V6M_H_ + +/*===========================================================================*/ +/* Port constants. */ +/*===========================================================================*/ + +/** + * @brief PendSV priority level. + * @note This priority is enforced to be equal to @p 0, + * this handler always has the highest priority that cannot preempt + * the kernel. + */ +#define CORTEX_PRIORITY_PENDSV 0 + +/*===========================================================================*/ +/* Port macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + * @note In this port it is set to 16 because the idle thread does have + * a stack frame when compiling without optimizations. You may + * reduce this value to zero when compiling with optimizations. + */ +#if !defined(PORT_IDLE_THREAD_STACK_SIZE) +#define PORT_IDLE_THREAD_STACK_SIZE 16 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * This value can be zero on those architecture where there is a + * separate interrupt stack and the stack space between @p intctx and + * @p extctx is known to be zero. + * @note In this port it is conservatively set to 32 because the function + * @p chSchDoReschedule() can have a stack frame, especially with + * compiler optimizations disabled. + */ +#if !defined(PORT_INT_REQUIRED_STACK) +#define PORT_INT_REQUIRED_STACK 32 +#endif + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#if !defined(CORTEX_ENABLE_WFI_IDLE) +#define CORTEX_ENABLE_WFI_IDLE FALSE +#endif + +/** + * @brief SYSTICK handler priority. + * @note The default SYSTICK handler priority is calculated as the priority + * level in the middle of the numeric priorities range. + */ +#if !defined(CORTEX_PRIORITY_SYSTICK) +#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) +#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) +/* If it is externally redefined then better perform a validity check on it.*/ +#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" +#endif + +/** + * @brief Alternate preemption method. + * @details Activating this option will make the Kernel use the PendSV + * handler for preemption instead of the NMI handler. + */ +#ifndef CORTEX_ALTERNATE_SWITCH +#define CORTEX_ALTERNATE_SWITCH FALSE +#endif + +/*===========================================================================*/ +/* Port derived parameters. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +/** + * @brief Macro defining the specific ARM architecture. + */ +#define CH_ARCHITECTURE_ARM_v6M + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "ARMv6-M" + +/** + * @brief Name of the architecture variant. + */ +#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__) +#define CH_CORE_VARIANT_NAME "Cortex-M0" +#elif (CORTEX_MODEL == CORTEX_M1) +#define CH_CORE_VARIANT_NAME "Cortex-M1" +#endif + +/** + * @brief Port-specific information string. + */ +#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +#define CH_PORT_INFO "Preemption through NMI" +#else +#define CH_PORT_INFO "Preemption through PendSV" +#endif + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) + +/** + * @brief Generic ARM register. + */ +typedef void *regarm_t; + + /* The documentation of the following declarations is in chconf.h in order + to not have duplicated structure names into the documentation.*/ +#if !defined(__DOXYGEN__) + +typedef uint64_t stkalign_t __attribute__ ((aligned (8))); + +struct extctx { + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t r12; + regarm_t lr_thd; + regarm_t pc; + regarm_t xpsr; +}; + +struct intctx { + regarm_t r8; + regarm_t r9; + regarm_t r10; + regarm_t r11; + regarm_t r4; + regarm_t r5; + regarm_t r6; + regarm_t r7; + regarm_t lr; +}; + +#endif /* !defined(__DOXYGEN__) */ + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details In this port the structure just holds a pointer to the @p intctx + * structure representing the stack pointer at context switch time. + */ +struct context { + struct intctx *r13; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->r4 = pf; \ + tp->p_ctx.r13->r5 = arg; \ + tp->p_ctx.r13->lr = _port_thread_start; \ +} + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() \ + regarm_t _saved_lr; \ + asm volatile ("mov %0, lr" : "=r" (_saved_lr) : : "memory") + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr) + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_FAST_IRQ_HANDLER(id) void id(void) + +/** + * @brief Port-related initialization code. + */ +#define port_init() { \ + SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ + nvicSetSystemHandlerPriority(HANDLER_PENDSV, \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ +} + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform + * more actions. + */ +#define port_lock() asm volatile ("cpsid i" : : : "memory") + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform + * more actions. + */ +#define port_unlock() asm volatile ("cpsie i" : : : "memory") + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_lock_from_isr() port_lock() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_unlock_from_isr() port_unlock() + +/** + * @brief Disables all the interrupt sources. + */ +#define port_disable() asm volatile ("cpsid i" : : : "memory") + +/** + * @brief Disables the interrupt sources below kernel-level priority. + */ +#define port_suspend() asm volatile ("cpsid i" : : : "memory") + +/** + * @brief Enables all the interrupt sources. + */ +#define port_enable() asm volatile ("cpsie i" : : : "memory") + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note Implemented as an inlined @p WFI instruction. + */ +#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() asm volatile ("wfi" : : : "memory") +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) +#define port_switch(ntp, otp) _port_switch(ntp, otp) +#else +#define port_switch(ntp, otp) { \ + register struct intctx *r13 asm ("r13"); \ + if ((stkalign_t *)(r13 - 1) < otp->p_stklimit) \ + chDbgPanic("stack overflow"); \ + _port_switch(ntp, otp); \ +} +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void port_halt(void); + void _port_irq_epilogue(regarm_t lr); + void _port_switch_from_isr(void); + void _port_exit_from_isr(void); + void _port_switch(Thread *ntp, Thread *otp); + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _FROM_ASM_ */ + +#endif /* _CHCORE_V6M_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/ARMCMx/chcore_v7m.c b/Project/os/ports/GCC/ARMCMx/chcore_v7m.c new file mode 100644 index 0000000..ec17b8d --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/chcore_v7m.c @@ -0,0 +1,267 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/ARMCMx/chcore_v7m.c + * @brief ARMv7-M architecture port code. + * + * @addtogroup ARMCMx_V7M_CORE + * @{ + */ + +#include "ch.h" + +/*===========================================================================*/ +/* Port interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief System Timer vector. + * @details This interrupt is used as system tick. + * @note The timer must be initialized in the startup code. + */ +CH_IRQ_HANDLER(SysTickVector) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +/** + * @brief SVC vector. + * @details The SVC vector is used for exception mode re-entering after a + * context switch. + * @note The PendSV vector is only used in advanced kernel mode. + */ +void SVCallVector(void) { + struct extctx *ctxp; + + /* Current PSP value.*/ + asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp++; + +#if CORTEX_USE_FPU + /* Restoring the special register SCB_FPCCR.*/ + SCB_FPCCR = (uint32_t)ctxp->fpccr; + SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx); +#endif + asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); + port_unlock_from_isr(); +} +#endif /* !CORTEX_SIMPLIFIED_PRIORITY */ + +#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +/** + * @brief PendSV vector. + * @details The PendSV vector is used for exception mode re-entering after a + * context switch. + * @note The PendSV vector is only used in compact kernel mode. + */ +void PendSVVector(void) { + struct extctx *ctxp; + + /* Current PSP value.*/ + asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp++; + +#if CORTEX_USE_FPU + /* Restoring the special register SCB_FPCCR.*/ + SCB_FPCCR = (uint32_t)ctxp->fpccr; + SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx); +#endif + asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); +} +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/*===========================================================================*/ +/* Port exported functions. */ +/*===========================================================================*/ + +/** + * @brief Port-related initialization code. + */ +void _port_init(void) { + + /* Initialization of the vector table and priority related settings.*/ + SCB_VTOR = CORTEX_VTOR_INIT; + SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); + + /* Initialization of the system vectors used by the port.*/ + nvicSetSystemHandlerPriority(HANDLER_SVCALL, + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); + nvicSetSystemHandlerPriority(HANDLER_PENDSV, + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); +} + +#if !CH_OPTIMIZE_SPEED +void _port_lock(void) { + register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; + asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); +} + +void _port_unlock(void) { + register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; + asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); +} +#endif + +/** + * @brief Exception exit redirection to _port_switch_from_isr(). + */ +void _port_irq_epilogue(void) { + + port_lock_from_isr(); + if ((SCB_ICSR & ICSR_RETTOBASE) != 0) { + struct extctx *ctxp; + + /* Current PSP value.*/ + asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); + + /* Adding an artificial exception return context, there is no need to + populate it fully.*/ + ctxp--; + asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); + ctxp->xpsr = (regarm_t)0x01000000; + + /* The exit sequence is different depending on if a preemption is + required or not.*/ + if (chSchIsPreemptionRequired()) { + /* Preemption is required we need to enforce a context switch.*/ + ctxp->pc = _port_switch_from_isr; +#if CORTEX_USE_FPU + /* Triggering a lazy FPU state save.*/ + asm volatile ("vmrs APSR_nzcv, FPSCR" : : : "memory"); +#endif + } + else { + /* Preemption not required, we just need to exit the exception + atomically.*/ + ctxp->pc = _port_exit_from_isr; + } + +#if CORTEX_USE_FPU + { + uint32_t fpccr; + + /* Saving the special register SCB_FPCCR into the reserved offset of + the Cortex-M4 exception frame.*/ + (ctxp + 1)->fpccr = (regarm_t)(fpccr = SCB_FPCCR); + + /* Now the FPCCR is modified in order to not restore the FPU status + from the artificial return context.*/ + SCB_FPCCR = fpccr | FPCCR_LSPACT; + } +#endif + + /* Note, returning without unlocking is intentional, this is done in + order to keep the rest of the context switching atomic.*/ + return; + } + port_unlock_from_isr(); +} + +/** + * @brief Post-IRQ switch code. + * @details Exception handlers return here for context switching. + */ +#if !defined(__DOXYGEN__) +__attribute__((naked)) +#endif +void _port_switch_from_isr(void) { + + dbg_check_lock(); + chSchDoReschedule(); + dbg_check_unlock(); + asm volatile ("_port_exit_from_isr:" : : : "memory"); +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) + asm volatile ("svc #0"); +#else /* CORTEX_SIMPLIFIED_PRIORITY */ + SCB_ICSR = ICSR_PENDSVSET; + port_unlock(); + while (TRUE) + ; +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ +} + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if !defined(__DOXYGEN__) +__attribute__((naked)) +#endif +void _port_switch(Thread *ntp, Thread *otp) { + + asm volatile ("push {r4, r5, r6, r7, r8, r9, r10, r11, lr}" + : : : "memory"); +#if CORTEX_USE_FPU + asm volatile ("vpush {s16-s31}" : : : "memory"); +#endif + + asm volatile ("str sp, [%1, #12] \n\t" + "ldr sp, [%0, #12]" : : "r" (ntp), "r" (otp)); + +#if CORTEX_USE_FPU + asm volatile ("vpop {s16-s31}" : : : "memory"); +#endif + asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}" + : : : "memory"); +} + +/** + * @brief Start a thread by invoking its work function. + * @details If the work function returns @p chThdExit() is automatically + * invoked. + */ +void _port_thread_start(void) { + + chSysUnlock(); + asm volatile ("mov r0, r5 \n\t" + "blx r4 \n\t" + "bl chThdExit"); +} + +/** @} */ diff --git a/Project/os/ports/GCC/ARMCMx/chcore_v7m.h b/Project/os/ports/GCC/ARMCMx/chcore_v7m.h new file mode 100644 index 0000000..96f91be --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/chcore_v7m.h @@ -0,0 +1,518 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/ARMCMx/chcore_v7m.h + * @brief ARMv7-M architecture port macros and structures. + * + * @addtogroup ARMCMx_V7M_CORE + * @{ + */ + +#ifndef _CHCORE_V7M_H_ +#define _CHCORE_V7M_H_ + +/*===========================================================================*/ +/* Port constants. */ +/*===========================================================================*/ + +/** + * @brief Disabled value for BASEPRI register. + */ +#define CORTEX_BASEPRI_DISABLED 0 + +/*===========================================================================*/ +/* Port macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + * @note In this port it is set to 16 because the idle thread does have + * a stack frame when compiling without optimizations. You may + * reduce this value to zero when compiling with optimizations. + */ +#if !defined(PORT_IDLE_THREAD_STACK_SIZE) +#define PORT_IDLE_THREAD_STACK_SIZE 16 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * This value can be zero on those architecture where there is a + * separate interrupt stack and the stack space between @p intctx and + * @p extctx is known to be zero. + * @note In this port it is conservatively set to 32 because the function + * @p chSchDoReschedule() can have a stack frame, especially with + * compiler optimizations disabled. + */ +#if !defined(PORT_INT_REQUIRED_STACK) +#define PORT_INT_REQUIRED_STACK 32 +#endif + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#if !defined(CORTEX_ENABLE_WFI_IDLE) +#define CORTEX_ENABLE_WFI_IDLE FALSE +#endif + +/** + * @brief SYSTICK handler priority. + * @note The default SYSTICK handler priority is calculated as the priority + * level in the middle of the numeric priorities range. + */ +#if !defined(CORTEX_PRIORITY_SYSTICK) +#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) +#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) +/* If it is externally redefined then better perform a validity check on it.*/ +#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" +#endif + +/** + * @brief FPU support in context switch. + * @details Activating this option activates the FPU support in the kernel. + */ +#if !defined(CORTEX_USE_FPU) +#define CORTEX_USE_FPU CORTEX_HAS_FPU +#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU +/* This setting requires an FPU presence check in case it is externally + redefined.*/ +#error "the selected core does not have an FPU" +#endif + +/** + * @brief Simplified priority handling flag. + * @details Activating this option makes the Kernel work in compact mode. + */ +#if !defined(CORTEX_SIMPLIFIED_PRIORITY) +#define CORTEX_SIMPLIFIED_PRIORITY FALSE +#endif + +/** + * @brief SVCALL handler priority. + * @note The default SVCALL handler priority is defaulted to + * @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the + * @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts + * priority level. + */ +#if !defined(CORTEX_PRIORITY_SVCALL) +#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1) +#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL) +/* If it is externally redefined then better perform a validity check on it.*/ +#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL" +#endif + +/** + * @brief NVIC VTOR initialization expression. + */ +#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__) +#define CORTEX_VTOR_INIT 0x00000000 +#endif + +/*===========================================================================*/ +/* Port derived parameters. */ +/*===========================================================================*/ + +/** + * @brief BASEPRI level within kernel lock. + * @note In compact kernel mode this constant value is enforced to zero. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define CORTEX_BASEPRI_KERNEL \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1) +#else +#define CORTEX_BASEPRI_KERNEL 0 +#endif + +/** + * @brief PendSV priority level. + * @note This priority is enforced to be equal to @p CORTEX_BASEPRI_KERNEL, + * this handler always have the highest priority that cannot preempt + * the kernel. + */ +#define CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__) +/** + * @brief Macro defining the specific ARM architecture. + */ +#define CH_ARCHITECTURE_ARM_v7M + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "ARMv7-M" + +/** + * @brief Name of the architecture variant. + */ +#define CH_CORE_VARIANT_NAME "Cortex-M3" + +#elif (CORTEX_MODEL == CORTEX_M4) +#define CH_ARCHITECTURE_ARM_v7ME +#define CH_ARCHITECTURE_NAME "ARMv7-ME" +#if CORTEX_USE_FPU +#define CH_CORE_VARIANT_NAME "Cortex-M4F" +#else +#define CH_CORE_VARIANT_NAME "Cortex-M4" +#endif +#endif + +/** + * @brief Port-specific information string. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define CH_PORT_INFO "Advanced kernel mode" +#else +#define CH_PORT_INFO "Compact kernel mode" +#endif + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) + +/** + * @brief Generic ARM register. + */ +typedef void *regarm_t; + +/* The documentation of the following declarations is in chconf.h in order + to not have duplicated structure names into the documentation.*/ +#if !defined(__DOXYGEN__) + +typedef uint64_t stkalign_t __attribute__ ((aligned (8))); + +struct extctx { + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t r12; + regarm_t lr_thd; + regarm_t pc; + regarm_t xpsr; +#if CORTEX_USE_FPU + regarm_t s0; + regarm_t s1; + regarm_t s2; + regarm_t s3; + regarm_t s4; + regarm_t s5; + regarm_t s6; + regarm_t s7; + regarm_t s8; + regarm_t s9; + regarm_t s10; + regarm_t s11; + regarm_t s12; + regarm_t s13; + regarm_t s14; + regarm_t s15; + regarm_t fpscr; + regarm_t fpccr; +#endif /* CORTEX_USE_FPU */ +}; + +struct intctx { +#if CORTEX_USE_FPU + regarm_t s16; + regarm_t s17; + regarm_t s18; + regarm_t s19; + regarm_t s20; + regarm_t s21; + regarm_t s22; + regarm_t s23; + regarm_t s24; + regarm_t s25; + regarm_t s26; + regarm_t s27; + regarm_t s28; + regarm_t s29; + regarm_t s30; + regarm_t s31; +#endif /* CORTEX_USE_FPU */ + regarm_t r4; + regarm_t r5; + regarm_t r6; + regarm_t r7; + regarm_t r8; + regarm_t r9; + regarm_t r10; + regarm_t r11; + regarm_t lr; +}; + +#endif /* !defined(__DOXYGEN__) */ + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details In this port the structure just holds a pointer to the @p intctx + * structure representing the stack pointer at context switch time. + */ +struct context { + struct intctx *r13; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->r4 = pf; \ + tp->p_ctx.r13->r5 = arg; \ + tp->p_ctx.r13->lr = _port_thread_start; \ +} + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() _port_irq_epilogue() + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_FAST_IRQ_HANDLER(id) void id(void) + +/** + * @brief Port-related initialization code. + */ +#define port_init() _port_init() + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform + * more actions. + * @note In this port this it raises the base priority to kernel level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#if CH_OPTIMIZE_SPEED || defined(__DOXYGEN__) +#define port_lock() { \ + register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \ + asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \ +} +#else /* !CH_OPTIMIZE_SPEED */ +#define port_lock() { \ + asm volatile ("bl _port_lock" : : : "r3", "lr", "memory"); \ +} +#endif /* !CH_OPTIMIZE_SPEED */ +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_lock() asm volatile ("cpsid i" : : : "memory") +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform + * more actions. + * @note In this port this it lowers the base priority to user level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#if CH_OPTIMIZE_SPEED || defined(__DOXYGEN__) +#define port_unlock() { \ + register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \ + asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \ +} +#else /* !CH_OPTIMIZE_SPEED */ +#define port_unlock() { \ + asm volatile ("bl _port_unlock" : : : "r3", "lr", "memory"); \ +} +#endif /* !CH_OPTIMIZE_SPEED */ +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_unlock() asm volatile ("cpsie i" : : : "memory") +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_lock_from_isr() port_lock() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + * @note Same as @p port_unlock() in this port. + */ +#define port_unlock_from_isr() port_unlock() + +/** + * @brief Disables all the interrupt sources. + * @note Of course non-maskable interrupt sources are not included. + * @note In this port it disables all the interrupt sources by raising + * the priority mask to level 0. + */ +#define port_disable() asm volatile ("cpsid i" : : : "memory") + +/** + * @brief Disables the interrupt sources below kernel-level priority. + * @note Interrupt sources above kernel level remains enabled. + * @note In this port it raises/lowers the base priority to kernel level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define port_suspend() { \ + register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \ + asm volatile ("msr BASEPRI, %0 \n\t" \ + "cpsie i" : : "r" (tmp) : "memory"); \ +} +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_suspend() asm volatile ("cpsid i" : : : "memory") +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Enables all the interrupt sources. + * @note In this port it lowers the base priority to user level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define port_enable() { \ + register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \ + asm volatile ("msr BASEPRI, %0 \n\t" \ + "cpsie i" : : "r" (tmp) : "memory"); \ +} +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_enable() asm volatile ("cpsie i" : : : "memory") +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note Implemented as an inlined @p WFI instruction. + */ +#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() { \ + asm volatile ("wfi" : : : "memory"); \ +} +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) +#define port_switch(ntp, otp) _port_switch(ntp, otp) +#else +#define port_switch(ntp, otp) { \ + register struct intctx *r13 asm ("r13"); \ + if ((stkalign_t *)(r13 - 1) < otp->p_stklimit) \ + chDbgPanic("stack overflow"); \ + _port_switch(ntp, otp); \ +} +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void port_halt(void); + void _port_init(void); + void _port_irq_epilogue(void); + void _port_switch_from_isr(void); + void _port_exit_from_isr(void); + void _port_switch(Thread *ntp, Thread *otp); + void _port_thread_start(void); +#if !CH_OPTIMIZE_SPEED + void _port_lock(void); + void _port_unlock(void); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _FROM_ASM_ */ + +#endif /* _CHCORE_V7M_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/ARMCMx/chtypes.h b/Project/os/ports/GCC/ARMCMx/chtypes.h new file mode 100644 index 0000000..218d4f5 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/chtypes.h @@ -0,0 +1,88 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/ARMCMx/chtypes.h + * @brief ARM Cortex-Mx port system types. + * + * @addtogroup ARMCMx_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#define __need_NULL +#define __need_size_t +#define __need_ptrdiff_t +#include + +#include + +typedef int32_t bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint32_t tprio_t; /**< Thread priority. */ +typedef int32_t msg_t; /**< Inter-thread message. */ +typedef int32_t eventid_t; /**< Event Id. */ +typedef uint32_t eventmask_t; /**< Events mask. */ +typedef uint32_t systime_t; /**< System time. */ +typedef int32_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE inline + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note It uses the "packed" GCC attribute. + */ +#define PACK_STRUCT_STRUCT __attribute__((packed)) + +/** + * @brief Packed structure modifier (before). + * @note Empty in this port. + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/ARMCMx/crt0.c b/Project/os/ports/GCC/ARMCMx/crt0.c new file mode 100644 index 0000000..72e8aac --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/crt0.c @@ -0,0 +1,347 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file ARMCMx/crt0.c + * @brief Generic ARMvx-M (Cortex-M0/M1/M3/M4) startup file for ChibiOS/RT. + * + * @addtogroup ARMCMx_STARTUP + * @{ + */ + +#include "ch.h" + +typedef void (*funcp_t)(void); +typedef funcp_t * funcpp_t; + +#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0)) + +/* + * Area fill code, it is a macro because here functions cannot be called + * until stacks are initialized. + */ +#define fill32(start, end, filler) { \ + uint32_t *p1 = start; \ + uint32_t *p2 = end; \ + while (p1 < p2) \ + *p1++ = filler; \ +} + +/*===========================================================================*/ +/** + * @name Startup settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Control special register initialization value. + * @details The system is setup to run in privileged mode using the PSP + * stack (dual stack mode). + */ +#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__) +#define CRT0_CONTROL_INIT 0x00000002 +#endif + +/** + * @brief Stack segments initialization switch. + */ +#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__) +#define CRT0_STACKS_FILL_PATTERN 0x55555555 +#endif + +/** + * @brief Stack segments initialization switch. + */ +#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__) +#define CRT0_INIT_STACKS TRUE +#endif + +/** + * @brief DATA segment initialization switch. + */ +#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__) +#define CRT0_INIT_DATA TRUE +#endif + +/** + * @brief BSS segment initialization switch. + */ +#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__) +#define CRT0_INIT_BSS TRUE +#endif + +/** + * @brief Constructors invocation switch. + */ +#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__) +#define CRT0_CALL_CONSTRUCTORS TRUE +#endif + +/** + * @brief Destructors invocation switch. + */ +#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__) +#define CRT0_CALL_DESTRUCTORS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Symbols from the scatter file + */ +/*===========================================================================*/ + +/** + * @brief Main stack lower boundary. + * @details This symbol must be exported by the linker script and represents + * the main stack lower boundary. + */ +extern uint32_t __main_stack_base__; + +/** + * + * @brief Main stack initial position. + * @details This symbol must be exported by the linker script and represents + * the main stack initial position. + */ +extern uint32_t __main_stack_end__; + +/** + * @brief Process stack lower boundary. + * @details This symbol must be exported by the linker script and represents + * the process stack lower boundary. + */ +extern uint32_t __process_stack_base__; + +/** + * @brief Process stack initial position. + * @details This symbol must be exported by the linker script and represents + * the process stack initial position. + */ +extern uint32_t __process_stack_end__; + +/** + * @brief ROM image of the data segment start. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern uint32_t _textdata; + +/** + * @brief Data segment start. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern uint32_t _data; + +/** + * @brief Data segment end. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern uint32_t _edata; + +/** + * @brief BSS segment start. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern uint32_t _bss_start; + +/** + * @brief BSS segment end. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern uint32_t _bss_end; + +/** + * @brief Constructors table start. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern funcp_t __init_array_start; + +/** + * @brief Constructors table end. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern funcp_t __init_array_end; + +/** + * @brief Destructors table start. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern funcp_t __fini_array_start; + +/** + * @brief Destructors table end. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern funcp_t __fini_array_end; + +/** @} */ + +/** + * @brief Application @p main() function. + */ +extern void main(void); + +/** + * @brief Early initialization. + * @details This hook is invoked immediately after the stack initialization + * and before the DATA and BSS segments initialization. The + * default behavior is to do nothing. + * @note This function is a weak symbol. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +void __early_init(void) {} + +/** + * @brief Late initialization. + * @details This hook is invoked after the DATA and BSS segments + * initialization and before any static constructor. The + * default behavior is to do nothing. + * @note This function is a weak symbol. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +void __late_init(void) {} + +/** + * @brief Default @p main() function exit handler. + * @details This handler is invoked or the @p main() function exit. The + * default behavior is to enter an infinite loop. + * @note This function is a weak symbol. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak, naked)) +#endif +void _default_exit(void) { + while (1) + ; +} + +/** + * @brief Reset vector. + */ +#if !defined(__DOXYGEN__) +__attribute__((naked)) +#endif +void ResetHandler(void) { + uint32_t psp, reg; + + /* Process Stack initialization, it is allocated starting from the + symbol __process_stack_end__ and its lower limit is the symbol + __process_stack_base__.*/ + asm volatile ("cpsid i"); + psp = SYMVAL(__process_stack_end__); + asm volatile ("msr PSP, %0" : : "r" (psp)); + +#if CORTEX_USE_FPU + /* Initializing the FPU context save in lazy mode.*/ + SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN; + + /* CP10 and CP11 set to full access.*/ + SCB_CPACR |= 0x00F00000; + + /* FPSCR and FPDSCR initially zero.*/ + reg = 0; + asm volatile ("vmsr FPSCR, %0" : : "r" (reg) : "memory"); + SCB_FPDSCR = reg; + + /* CPU mode initialization, enforced FPCA bit.*/ + reg = CRT0_CONTROL_INIT | 4; +#else + /* CPU mode initialization.*/ + reg = CRT0_CONTROL_INIT; +#endif + asm volatile ("msr CONTROL, %0" : : "r" (reg)); + asm volatile ("isb"); + +#if CRT0_INIT_STACKS + /* Main and Process stacks initialization.*/ + fill32(&__main_stack_base__, + &__main_stack_end__, + CRT0_STACKS_FILL_PATTERN); + fill32(&__process_stack_base__, + &__process_stack_end__, + CRT0_STACKS_FILL_PATTERN); +#endif + + /* Early initialization hook invocation.*/ + __early_init(); + +#if CRT0_INIT_DATA + /* DATA segment initialization.*/ + { + uint32_t *tp, *dp; + + tp = &_textdata; + dp = &_data; + while (dp < &_edata) + *dp++ = *tp++; + } +#endif + +#if CRT0_INIT_BSS + /* BSS segment initialization.*/ + fill32(&_bss_start, &_bss_end, 0); +#endif + + /* Late initialization hook invocation.*/ + __late_init(); + +#if CRT0_CALL_CONSTRUCTORS + /* Constructors invocation.*/ + { + funcpp_t fpp = &__init_array_start; + while (fpp < &__init_array_end) { + (*fpp)(); + fpp++; + } + } +#endif + + /* Invoking application main() function.*/ + main(); + +#if CRT0_CALL_DESTRUCTORS + /* Destructors invocation.*/ + { + funcpp_t fpp = &__fini_array_start; + while (fpp < &__fini_array_end) { + (*fpp)(); + fpp++; + } + } +#endif + + /* Invoking the exit handler.*/ + _default_exit(); +} + +/** @} */ diff --git a/Project/os/ports/GCC/ARMCMx/port.dox b/Project/os/ports/GCC/ARMCMx/port.dox new file mode 100644 index 0000000..9349416 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/port.dox @@ -0,0 +1,265 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup ARMCMx ARM Cortex-Mx + * @details ARM Cortex-Mx port for the GCC compiler. + + * @section ARMCMx_INTRO Introduction + * This port supports all the cores implementing the ARMv6-M and ARMv7-M + * architectures. + * + * @section ARMCMx_MODES Kernel Modes + * The Cortex-Mx port supports two distinct kernel modes: + * - Advanced Kernel mode. In this mode the kernel only masks + * interrupt sources with priorities below or equal to the + * @p CORTEX_BASEPRI_KERNEL level. Higher priorities are not affected by + * the kernel critical sections and can be used for fast interrupts. + * This mode is not available in the ARMv6-M architecture which does not + * support priority masking. + * - Compact Kernel mode. In this mode the kernel handles IRQ priorities + * in a simplified way, all interrupt sources are disabled when the kernel + * enters into a critical zone and re-enabled on exit. This is simple and + * adequate for most applications, this mode results in a more compact and + * faster kernel. + * . + * The selection of the mode is performed using the port configuration option + * @p CORTEX_SIMPLIFIED_PRIORITY. Apart from the different handling of + * interrupts there are no other differences between the two modes. The + * kernel API is exactly the same. + * + * @section ARMCMx_STATES_A System logical states in Compact Kernel mode + * The ChibiOS/RT logical @ref system_states are mapped as follow in Compact + * Kernel mode: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). In this state interrupts are enabled. The processor + * is running in thread-privileged mode. + * - Suspended. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. In this + * mode this state is not different from the Disabled state. + * - Disabled. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. In this + * mode this state is not different from the Suspended state. + * - Sleep. This state is entered with the execution of the specific + * instruction @p wfi. + * - S-Locked. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. + * - I-Locked. In this state the interrupt sources are globally + * disabled. The processor is running in exception-privileged mode. + * - Serving Regular Interrupt. In this state the interrupt sources are + * not globally masked but only interrupts with higher priority can preempt + * the current handler. The processor is running in exception-privileged + * mode. + * - Serving Fast Interrupt. Not implemented in compact kernel mode. + * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific + * asynchronous NMI vector and several synchronous fault vectors that can + * be considered belonging to this category. + * - Halted. Implemented as an infinite loop after globally masking all + * the maskable interrupt sources. The ARM state is whatever the processor + * was running when @p chSysHalt() was invoked. + * + * @section ARMCMx_STATES_B System logical states in Advanced Kernel mode + * The ChibiOS/RT logical @ref system_states are mapped as follow in the + * Advanced Kernel mode: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register + * set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The + * processor is running in thread-privileged mode. + * - Suspended. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in thread-privileged mode. + * - Disabled. Interrupt sources are globally masked. The processor + * is running in thread-privileged mode. + * - Sleep. This state is entered with the execution of the specific + * instruction @p wfi. + * - S-Locked. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in thread-privileged mode. + * - I-Locked. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in exception-privileged mode. + * - Serving Regular Interrupt. In this state the interrupt sources are + * not globally masked but only interrupts with higher priority can preempt + * the current handler. The processor is running in exception-privileged + * mode. + * - Serving Fast Interrupt. Fast interrupts are defined as interrupt + * sources having higher priority level than the kernel + * (@p CORTEX_BASEPRI_KERNEL). In this state is not possible to switch to + * the I-Locked state because fast interrupts can preempt the kernel + * critical zone.
+ * This state is not implemented in the ARMv6-M implementation because + * priority masking is not present in this architecture. + * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific + * asynchronous NMI vector and several synchronous fault vectors that can + * be considered belonging to this category. + * - Halted. Implemented as an infinite loop after globally masking all + * the maskable interrupt sources. The ARM state is whatever the processor + * was running when @p chSysHalt() was invoked. + * . + * @section ARMCMx_NOTES ARM Cortex-Mx/GCC port notes + * The ARM Cortex-Mx port is organized as follow: + * - The @p main() function is invoked in thread-privileged mode. + * - Each thread has a private process stack, the system has a single main + * stack where all the interrupts and exceptions are processed. + * - The threads are started in thread-privileged mode. + * - Interrupt nesting and the other advanced core/NVIC features are supported. + * - The Cortex-Mx port is perfectly generic, support for more devices can be + * easily added by adding a subdirectory under ./os/ports/GCC/ARMCMx + * and giving it the name of the new device, then copy the files from another + * device into the new directory and customize them for the new device. + * . + * @ingroup gcc + */ + +/** + * @defgroup ARMCMx_CONF Configuration Options + * @details ARM Cortex-Mx Configuration Options. The ARMCMx port allows some + * architecture-specific configurations settings that can be overridden + * by redefining them in @p chconf.h. Usually there is no need to change + * the default values. + * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used + * by an interrupt handler between the @p extctx and @p intctx + * structures. + * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE + * thread. Usually there is no need to change this value unless inserting + * code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro. + * - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler. + * - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler. + * - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the + * @p wfi instruction from within the idle loop. This option is + * defaulted to FALSE because it can create problems with some debuggers. + * Setting this option to TRUE reduces the system power requirements. + * . + * @section ARMCMx_CONF_1 ARMv6-M specific options + * The following options are specific for the ARMv6-M architecture: + * - @p CORTEX_ALTERNATE_SWITCH, when activated makes the OS use the PendSV + * exception instead of NMI as preemption handler. + * . + * @section ARMCMx_CONF_2 ARMv7-M specific options + * The following options are specific for the ARMv6-M architecture: + * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler. + * - @p CORTEX_SIMPLIFIED_PRIORITY, when enabled activates the Compact kernel + * mode. + * . + * @ingroup ARMCMx + */ + +/** + * @defgroup ARMCMx_CORE Core Port Implementation + * @details ARM Cortex-Mx specific port code, structures and macros. + * + * @ingroup ARMCMx + */ + +/** + * @defgroup ARMCMx_V6M_CORE ARMv6-M Specific Implementation + * @details ARMv6-M specific port code, structures and macros. + * + * @ingroup ARMCMx_CORE + */ + +/** + * @defgroup ARMCMx_V7M_CORE ARMv7-M Specific Implementation + * @details ARMv7-M specific port code, structures and macros. + * + * @ingroup ARMCMx_CORE + */ + +/** + * @defgroup ARMCMx_STARTUP Startup Support + * @details ChibiOS/RT provides its own generic startup file for the ARM + * Cortex-Mx port. + * Of course it is not mandatory to use it but care should be taken about the + * startup phase details. + * + * @section ARMCMx_STARTUP_1 Startup Process + * The startup process, as implemented, is the following: + * -# Interrupts are masked globally. + * -# The two stacks are initialized by assigning them the sizes defined in + * the linker script (also known as scatter file). + * -# The CPU state is switched to Privileged and the PSP stack is used. + * -# An early initialization routine @p __early_init() is invoked, if the + * symbol is not defined then an empty default routine is executed + * (weak symbol). + * -# DATA and BSS segments are initialized. + * -# Constructors are invoked. + * -# The @p main() function is invoked with no parameters. + * -# Destructors are invoked. + * -# A branch is performed to the weak symbol @p _default_exit(). The + * default code is an endless empty loop. + * . + * @section ARMCMx_STARTUP_2 Expected linker symbols + * The startup code starts at the symbol @p ResetHandler and expects the + * following symbols to be defined in the linker script: + * - @p __ram_end__, end of RAM. + * - @p __main_stack_base__, main stack lower boundary. + * - @p __main_stack_end__, main stack initial position. + * - @p __process_stack_base__, process stack lower boundary. + * - @p __process_stack_end__, process stack initial position. + * - @p _textdata, address of the data segment source read only data. + * - @p _data, start of the data segment. + * - @p _edata, end of the data segment end location. + * - @p _bss_start, start of the BSS. + * - @p _bss_end, end of the BSS segment. + * - @p __init_array_start, start of the constructors array. + * - @p __init_array_end, end of the constructors array. + * - @p __fini_array_start, start of the destructors array. + * - @p __fini_array_end, end of the destructors array. + * . + * Additionally the kernel expects the following symbols: + * - @p __main_thread_stack_base__, this symbol is required when the + * stack checking is enabled (CH_DBG_ENABLE_STACK_CHECK==TRUE), + * it is an alias of @p __process_stack_base__ in this port. + * - @p __heap_base__ and @p __heap_end__, those symbols are required + * if the memory core manager is enabled (CH_USE_MEMCORE==TRUE) + * with a default core size set to zero (CH_MEMCORE_SIZE==0). + * . + * @ingroup ARMCMx + */ + +/** + * @defgroup ARMCMx_NVIC NVIC Support + * @details ARM Cortex-Mx NVIC support. + * + * @ingroup ARMCMx + */ + +/** + * @defgroup ARMCMx_SPECIFIC Specific Implementations + * @details Platform-specific port code. + * + * @ingroup ARMCMx + */ diff --git a/Project/os/ports/GCC/ARMCMx/rules.mk b/Project/os/ports/GCC/ARMCMx/rules.mk new file mode 100644 index 0000000..0d0af92 --- /dev/null +++ b/Project/os/ports/GCC/ARMCMx/rules.mk @@ -0,0 +1,248 @@ +# ARM Cortex-Mx common makefile scripts and rules. + +# Output directory and files +ifeq ($(BUILDDIR),) + BUILDDIR = build +endif +ifeq ($(BUILDDIR),.) + BUILDDIR = build +endif + +ifeq ($(BUILD_LIBRARY),yes) + +OUTFILES = $(BUILDDIR)/$(PROJECT).a + +else +OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \ + $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp +endif + +# Automatic compiler options +OPT = $(USE_OPT) +COPT = $(USE_COPT) +CPPOPT = $(USE_CPPOPT) +ifeq ($(USE_LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections -fno-common +endif + +# Source files groups and paths +ifeq ($(USE_THUMB),yes) + TCSRC += $(CSRC) + TCPPSRC += $(CPPSRC) +else + ACSRC += $(CSRC) + ACPPSRC += $(CPPSRC) +endif +ASRC = $(ACSRC)$(ACPPSRC) +TSRC = $(TCSRC)$(TCPPSRC) +SRCPATHS = $(sort $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC))) + +# Various directories +OBJDIR = $(BUILDDIR)/obj +LSTDIR = $(BUILDDIR)/lst + +# Object files groups +ACOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o))) +ACPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o))) +TCOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o))) +TCPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o))) +ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o))) +OBJS = $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) + +# Paths +IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) +LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) + +# Macros +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) + +# Libs +LIBS = $(DLIBS) $(ULIBS) + +# Various settings +MCFLAGS = -mcpu=$(MCU) +ODFLAGS = -x --syms +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) +CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) +CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) +ifeq ($(USE_LINK_GC),yes) + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) +else + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch $(LLIBDIR) +endif + +# Thumb interwork enabled only if needed because it kills performance. +ifneq ($(TSRC),) + CFLAGS += -DTHUMB_PRESENT + CPPFLAGS += -DTHUMB_PRESENT + ASFLAGS += -DTHUMB_PRESENT + ifneq ($(ASRC),) + # Mixed ARM and THUMB mode. + CFLAGS += -mthumb-interwork + CPPFLAGS += -mthumb-interwork + ASFLAGS += -mthumb-interwork + LDFLAGS += -mthumb-interwork + else + # Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly. + CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING + CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING + ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb + LDFLAGS += -mno-thumb-interwork -mthumb + endif +else + # Pure ARM mode + CFLAGS += -mno-thumb-interwork + CPPFLAGS += -mno-thumb-interwork + ASFLAGS += -mno-thumb-interwork + LDFLAGS += -mno-thumb-interwork +endif + +# Generate dependency information +CFLAGS += -MD -MP -MF .dep/$(@F).d +CPPFLAGS += -MD -MP -MF .dep/$(@F).d + +# Paths where to search for sources +VPATH = $(SRCPATHS) + +# +# Makefile rules +# + +all: $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK EXTERNAL + +MAKE_ALL_RULE_HOOK: + +$(OBJS): | $(BUILDDIR) + +$(BUILDDIR) $(OBJDIR) $(LSTDIR): +ifeq ($(BUILD_LIBRARY),yes) +ifneq ($(USE_VERBOSE_COMPILE),yes) + @echo Compiler Options + @echo $(AR) $(ARFLAGS) $(OBJS) $(LDSCRIPT) + @echo +endif +else +ifneq ($(USE_VERBOSE_COMPILE),yes) + @echo Compiler Options + @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o + @echo +endif +endif + + mkdir -p $(OBJDIR) + mkdir -p $(LSTDIR) + +$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@ +endif + +$(TCPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@ +endif + +$(ACOBJS) : $(OBJDIR)/%.o : %.c Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@ +endif + +$(TCOBJS) : $(OBJDIR)/%.o : %.c Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@ +endif + +$(ASMOBJS) : $(OBJDIR)/%.o : %.s Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@ +endif + + +%.a: $(OBJS) $(LDSCRIPT) +ifeq ($(BUILD_LIBRARY),yes) +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(AR) $(ARFLAGS) $@ $(OBJS) +else + @echo Linking $@ + $(AR) $(ARFLAGS) $@ $(OBJS) +endif +else + @echo Use Lib: $@ +endif + + +%.elf: $(OBJS) $(LDSCRIPT) $(LIBS) +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ +else + @echo Linking $@ + @$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ +endif +ifneq ($(SIZE),) + $(SIZE) -A -d $@ +endif + +%.hex: %.elf $(LDSCRIPT) +ifeq ($(USE_VERBOSE_COMPILE),yes) + $(HEX) $< $@ +else + @echo Creating $@ + @$(HEX) $< $@ +endif + +%.bin: %.elf $(LDSCRIPT) +ifeq ($(USE_VERBOSE_COMPILE),yes) + $(BIN) $< $@ +else + @echo Creating $@ + @$(BIN) $< $@ +endif + +%.dmp: %.elf $(LDSCRIPT) +ifeq ($(USE_VERBOSE_COMPILE),yes) + $(OD) $(ODFLAGS) $< > $@ +else + @echo Creating $@ + @$(OD) $(ODFLAGS) $< > $@ + @echo Done +endif + + +clean: + -rm -fR .dep $(BUILDDIR) + @echo Done + +#-rm -fR .dep $(BUILDDIR) + + +# +# Include the dependency files, should be the last of the makefile +# +#-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) +-include $(shell mkdir .dep 2>/dev/null) +#-include $(wildcard .dep/*) + +# *** EOF *** diff --git a/Project/os/ports/GCC/AVR/chcore.c b/Project/os/ports/GCC/AVR/chcore.c new file mode 100644 index 0000000..12b418f --- /dev/null +++ b/Project/os/ports/GCC/AVR/chcore.c @@ -0,0 +1,140 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AVR/chcore.c + * @brief AVR architecture port code. + * + * @addtogroup AVR_CORE + * @{ + */ + +#include "ch.h" + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * @note The function is declared as a weak symbol, it is possible to + * redefine it in your application code. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if !defined(__DOXYGEN__) +__attribute__((naked, weak)) +#endif +void port_switch(Thread *ntp, Thread *otp) { + + asm volatile ("push r2"); + asm volatile ("push r3"); + asm volatile ("push r4"); + asm volatile ("push r5"); + asm volatile ("push r6"); + asm volatile ("push r7"); + asm volatile ("push r8"); + asm volatile ("push r9"); + asm volatile ("push r10"); + asm volatile ("push r11"); + asm volatile ("push r12"); + asm volatile ("push r13"); + asm volatile ("push r14"); + asm volatile ("push r15"); + asm volatile ("push r16"); + asm volatile ("push r17"); + asm volatile ("push r28"); + asm volatile ("push r29"); + + asm volatile ("movw r30, r22"); + asm volatile ("in r0, 0x3d"); + asm volatile ("std Z+5, r0"); + asm volatile ("in r0, 0x3e"); + asm volatile ("std Z+6, r0"); + + asm volatile ("movw r30, r24"); + asm volatile ("ldd r0, Z+5"); + asm volatile ("out 0x3d, r0"); + asm volatile ("ldd r0, Z+6"); + asm volatile ("out 0x3e, r0"); + + asm volatile ("pop r29"); + asm volatile ("pop r28"); + asm volatile ("pop r17"); + asm volatile ("pop r16"); + asm volatile ("pop r15"); + asm volatile ("pop r14"); + asm volatile ("pop r13"); + asm volatile ("pop r12"); + asm volatile ("pop r11"); + asm volatile ("pop r10"); + asm volatile ("pop r9"); + asm volatile ("pop r8"); + asm volatile ("pop r7"); + asm volatile ("pop r6"); + asm volatile ("pop r5"); + asm volatile ("pop r4"); + asm volatile ("pop r3"); + asm volatile ("pop r2"); + asm volatile ("ret"); +} + +/** + * @brief Halts the system. + * @details This function is invoked by the operating system when an + * unrecoverable error is detected (for example because a programming + * error in the application code that triggers an assertion while in + * debug mode). + * @note The function is declared as a weak symbol, it is possible to + * redefine it in your application code. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** + * @brief Start a thread by invoking its work function. + * @details If the work function returns @p chThdExit() is automatically + * invoked. + */ +void _port_thread_start(void) { + + chSysUnlock(); + asm volatile ("movw r24, r4"); + asm volatile ("movw r30, r2"); + asm volatile ("icall"); + asm volatile ("call chThdExit"); +} + +/** @} */ diff --git a/Project/os/ports/GCC/AVR/chcore.h b/Project/os/ports/GCC/AVR/chcore.h new file mode 100644 index 0000000..f402208 --- /dev/null +++ b/Project/os/ports/GCC/AVR/chcore.h @@ -0,0 +1,332 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AVR/chcore.h + * @brief AVR architecture port macros and structures. + * + * @addtogroup AVR_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +#include +#include + +#if CH_DBG_ENABLE_STACK_CHECK +#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port" +#endif + +/** + * @brief If enabled allows the idle thread to enter a low power mode. + */ +#ifndef ENABLE_WFI_IDLE +#define ENABLE_WFI_IDLE 0 +#endif + +/** + * @brief Macro defining the AVR architecture. + */ +#define CH_ARCHITECTURE_AVR + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "AVR" + +/** + * @brief Name of the architecture variant (optional). + */ +#define CH_CORE_VARIANT_NAME "MegaAVR" + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "GCC " __VERSION__ + +/** + * @brief Port-specific information string. + */ +#define CH_PORT_INFO "None" + +/** + * @brief 8 bits stack and memory alignment enforcement. + */ +typedef uint8_t stkalign_t; + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + * @note The field @p _next is not part of the context, it represents the + * offset of the structure relative to the stack pointer. + */ +struct extctx { + uint8_t _next; + uint8_t r31; + uint8_t r30; + uint8_t r27; + uint8_t r26; + uint8_t r25; + uint8_t r24; + uint8_t r23; + uint8_t r22; + uint8_t r21; + uint8_t r20; + uint8_t r19; + uint8_t r18; + uint8_t sr; + uint8_t r1; + uint8_t r0; + uint16_t pc; +}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching. + * @note The field @p _next is not part of the context, it represents the + * offset of the structure relative to the stack pointer. + */ +struct intctx { + uint8_t _next; + uint8_t r29; + uint8_t r28; + uint8_t r17; + uint8_t r16; + uint8_t r15; + uint8_t r14; + uint8_t r13; + uint8_t r12; + uint8_t r11; + uint8_t r10; + uint8_t r9; + uint8_t r8; + uint8_t r7; + uint8_t r6; + uint8_t r5; + uint8_t r4; + uint8_t r3; + uint8_t r2; + uint8_t pcl; + uint8_t pch; +}; + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details In the AVR port this structure just holds a pointer to the + * @p intctx structure representing the stack pointer at the time + * of the context switch. + */ +struct context { + struct intctx *sp; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.sp = (struct intctx*)((uint8_t *)workspace + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.sp->r2 = (int)pf; \ + tp->p_ctx.sp->r3 = (int)pf >> 8; \ + tp->p_ctx.sp->r4 = (int)arg; \ + tp->p_ctx.sp->r5 = (int)arg >> 8; \ + tp->p_ctx.sp->pcl = (int)_port_thread_start >> 8; \ + tp->p_ctx.sp->pch = (int)_port_thread_start; \ +} + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + * @note In this port it is set to 8. + */ +#ifndef PORT_IDLE_THREAD_STACK_SIZE +#define PORT_IDLE_THREAD_STACK_SIZE 8 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * This value can be zero on those architecture where there is a + * separate interrupt stack and the stack space between @p intctx and + * @p extctx is known to be zero. + * @note In this port the default is 32 bytes per thread. + */ +#ifndef PORT_INT_REQUIRED_STACK +#define PORT_INT_REQUIRED_STACK 32 +#endif + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + (sizeof(struct intctx) - 1) + \ + (sizeof(struct extctx) - 1) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + * @note This code tricks the compiler to save all the specified registers + * by "touching" them. + */ +#define PORT_IRQ_PROLOGUE() { \ + asm ("" : : : "r18", "r19", "r20", "r21", "r22", "r23", "r24", \ + "r25", "r26", "r27", "r30", "r31"); \ +} + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() { \ + dbg_check_lock(); \ + if (chSchIsPreemptionRequired()) \ + chSchDoReschedule(); \ + dbg_check_unlock(); \ +} + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) ISR(id) + +/** + * @brief Port-related initialization code. + * @note This function is empty in this port. + */ +#define port_init() + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform more + * actions. + * @note Implemented as global interrupt disable. + */ +#define port_lock() asm volatile ("cli" : : : "memory") + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform more + * actions. + * @note Implemented as global interrupt enable. + */ +#define port_unlock() asm volatile ("sei" : : : "memory") + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + * @note This function is empty in this port. + */ +#define port_lock_from_isr() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + * @note This function is empty in this port. + */ +#define port_unlock_from_isr() + +/** + * @brief Disables all the interrupt sources. + * @note Of course non-maskable interrupt sources are not included. + * @note Implemented as global interrupt disable. + */ +#define port_disable() asm volatile ("cli" : : : "memory") + +/** + * @brief Disables the interrupt sources below kernel-level priority. + * @note Interrupt sources above kernel level remains enabled. + * @note Same as @p port_disable() in this port, there is no difference + * between the two states. + */ +#define port_suspend() asm volatile ("cli" : : : "memory") + +/** + * @brief Enables all the interrupt sources. + * @note Implemented as global interrupt enable. + */ +#define port_enable() asm volatile ("sei" : : : "memory") + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note This port function is implemented as inlined code for performance + * reasons. + */ +#if ENABLE_WFI_IDLE != 0 +#define port_wait_for_interrupt() { \ + asm volatile ("sleep" : : : "memory"); \ +} +#else +#define port_wait_for_interrupt() +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void port_switch(Thread *ntp, Thread *otp); + void port_halt(void); + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/AVR/chtypes.h b/Project/os/ports/GCC/AVR/chtypes.h new file mode 100644 index 0000000..cf60e5f --- /dev/null +++ b/Project/os/ports/GCC/AVR/chtypes.h @@ -0,0 +1,90 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file AVR/chtypes.h + * @brief AVR architecture port system types. + * + * @addtogroup AVR_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#define __need_NULL +#define __need_size_t +#define __need_ptrdiff_t +#include + +#if !defined(_STDINT_H) && !defined(__STDINT_H_) +#include +#endif + +typedef int8_t bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint8_t tprio_t; /**< Thread priority. */ +typedef int16_t msg_t; /**< Inter-thread message. */ +typedef uint8_t eventid_t; /**< Event Id. */ +typedef uint8_t eventmask_t; /**< Events mask. */ +typedef uint16_t systime_t; /**< System time. */ +typedef int8_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE inline + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note It uses the "packed" GCC attribute. + */ +#define PACK_STRUCT_STRUCT __attribute__((packed)) + +/** + * @brief Packed structure modifier (before). + * @note Empty in this port. + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/AVR/port.dox b/Project/os/ports/GCC/AVR/port.dox new file mode 100644 index 0000000..f1e1679 --- /dev/null +++ b/Project/os/ports/GCC/AVR/port.dox @@ -0,0 +1,94 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup AVR MegaAVR + * @details AVR port for the GCC compiler. + * + * @section AVR_STATES Mapping of the System States in the AVR port + * The ChibiOS/RT logical @ref system_states are mapped as follow in the AVR + * port: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). Interrupts are enabled. + * - Suspended. Interrupts are disabled. + * - Disabled. Interrupts are disabled. This state is equivalent to the + * Suspended state because there are no fast interrupts in this architecture. + * - Sleep. This state is entered with the execution of the specific + * instruction @p sleep. + * - S-Locked. Interrupts are disabled. + * - I-Locked. This state is equivalent to the SRI state, the + * @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in + * order to formally change state because this may change). + * - Serving Regular Interrupt. Normal interrupt service code. + * - Serving Fast Interrupt. Not present in this architecture. + * - Serving Non-Maskable Interrupt. Not present in this architecture. + * - Halted. Implemented as an infinite loop with interrupts disabled. + * . + * @section AVR_NOTES The AVR port notes + * - The AVR does not have a dedicated interrupt stack, make sure to reserve + * enough stack space for interrupts in each thread stack. This can be done + * by modifying the @p INT_REQUIRED_STACK macro into + * ./ports/AVR/chcore.h. + * . + * @ingroup gcc + */ + +/** + * @defgroup AVR_CONF Configuration Options + * @details AVR Configuration Options. The AVR port allows some + * architecture-specific configurations settings that can be overridden + * by redefining them in @p chconf.h. Usually there is no need to change + * the default values. + * - @p INT_REQUIRED_STACK, this value represent the amount of stack space + * used by the interrupt handlers.
+ * The default for this value is @p 32, this space is allocated for each + * thread so be careful in order to not waste precious RAM space. + * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE + * thread. Usually there is no need to change this value unless inserting + * code in the IDLE thread hook macro. + * . + * @ingroup AVR + */ + +/** + * @defgroup AVR_CORE Core Port Implementation + * @details AVR specific port code, structures and macros. + * + * @ingroup AVR + */ + + /** + * @defgroup AVR_STARTUP Startup Support + * @details ChibiOS/RT doed not provide startup files for the AVR, there + * are no special startup requirement so the normal toolchain-provided + * startup files can be used. + * + * @ingroup AVR + */ diff --git a/Project/os/ports/GCC/AVR/port.mk b/Project/os/ports/GCC/AVR/port.mk new file mode 100644 index 0000000..7cafb56 --- /dev/null +++ b/Project/os/ports/GCC/AVR/port.mk @@ -0,0 +1,6 @@ +# List of the ChibiOS/RT AVR port files. +PORTSRC = ${CHIBIOS}/os/ports/GCC/AVR/chcore.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/GCC/AVR diff --git a/Project/os/ports/GCC/MSP430/chcore.c b/Project/os/ports/GCC/MSP430/chcore.c new file mode 100644 index 0000000..3e47cdd --- /dev/null +++ b/Project/os/ports/GCC/MSP430/chcore.c @@ -0,0 +1,109 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file MSP430/chcore.c + * @brief MSP430 architecture port code. + * + * @addtogroup MSP430_CORE + * @{ + */ + +#include "ch.h" + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * @note The function is declared as a weak symbol, it is possible to + * redefine it in your application code. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if !defined(__DOXYGEN__) +__attribute__((naked, weak)) +#endif +void port_switch(Thread *ntp, Thread *otp) { + register struct intctx *sp asm("r1"); + + asm volatile ("push r11 \n\t" \ + "push r10 \n\t" \ + "push r9 \n\t" \ + "push r8 \n\t" \ + "push r7 \n\t" \ + "push r6 \n\t" \ + "push r5 \n\t" \ + "push r4" : : : "memory"); + otp->p_ctx.sp = sp; + sp = ntp->p_ctx.sp; + asm volatile ("pop r4 \n\t" \ + "pop r5 \n\t" \ + "pop r6 \n\t" \ + "pop r7 \n\t" \ + "pop r8 \n\t" \ + "pop r9 \n\t" \ + "pop r10 \n\t" \ + "pop r11 \n\t" \ + "ret" : : "r" (sp) : "memory"); +} + +/** + * @brief Halts the system. + * @details This function is invoked by the operating system when an + * unrecoverable error is detected (for example because a programming + * error in the application code that triggers an assertion while in + * debug mode). + * @note The function is declared as a weak symbol, it is possible to + * redefine it in your application code. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** + * @brief Start a thread by invoking its work function. + * @details If the work function returns @p chThdExit() is automatically + * invoked. + */ +void _port_thread_start(void) { + + chSysUnlock(); + asm volatile ("mov r11, r15 \n\t" \ + "call r10 \n\t" \ + "call #chThdExit"); +} + +/** @} */ diff --git a/Project/os/ports/GCC/MSP430/chcore.h b/Project/os/ports/GCC/MSP430/chcore.h new file mode 100644 index 0000000..ffc40db --- /dev/null +++ b/Project/os/ports/GCC/MSP430/chcore.h @@ -0,0 +1,322 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file MSP430/chcore.h + * @brief MSP430 architecture port macros and structures. + * + * @addtogroup MSP430_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +#include +#include + +#if CH_DBG_ENABLE_STACK_CHECK +#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port" +#endif + +/** + * @brief Enables the use of a wait state in the idle thread loop. + */ +#ifndef ENABLE_WFI_IDLE +#define ENABLE_WFI_IDLE 0 +#endif + +/** + * @brief Macro defining the MSP430 architecture. + */ +#define CH_ARCHITECTURE_MSP430 + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "MSP430" + +/** + * @brief Name of the architecture variant (optional). + */ +#define CH_CORE_VARIANT_NAME "MSP430" + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "GCC " __VERSION__ + +/** + * @brief Port-specific information string. + */ +#define CH_PORT_INFO "None" + +/** + * @brief 16 bits stack and memory alignment enforcement. + */ +typedef uint16_t stkalign_t; + +/** + * @brief Generic MSP430 register. + */ +typedef void *regmsp_t; + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + */ +struct extctx { + regmsp_t r12; + regmsp_t r13; + regmsp_t r14; + regmsp_t r15; + regmsp_t sr; + regmsp_t pc; +}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching. + */ +struct intctx { + regmsp_t r4; + regmsp_t r5; + regmsp_t r6; + regmsp_t r7; + regmsp_t r8; + regmsp_t r9; + regmsp_t r10; + regmsp_t r11; + regmsp_t pc; +}; + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details This structure usually contains just the saved stack pointer + * defined as a pointer to a @p intctx structure. + */ +struct context { + struct intctx *sp; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.sp = (struct intctx *)((uint8_t *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.sp->r10 = pf; \ + tp->p_ctx.sp->r11 = arg; \ + tp->p_ctx.sp->pc = _port_thread_start; \ +} + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + */ +#ifndef PORT_IDLE_THREAD_STACK_SIZE +#define PORT_IDLE_THREAD_STACK_SIZE 0 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * This value can be zero on those architecture where there is a + * separate interrupt stack and the stack space between @p intctx and + * @p extctx is known to be zero. + * @note In this port the default is 32 bytes per thread. + */ +#ifndef PORT_INT_REQUIRED_STACK +#define PORT_INT_REQUIRED_STACK 32 +#endif + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() { \ + dbg_check_lock(); \ + if (chSchIsPreemptionRequired()) \ + chSchDoReschedule(); \ + dbg_check_unlock(); \ +} + +#define ISRNAME(pre, id) pre##id + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) ISR(id, ISRNAME(vect, id)) + +/** + * @brief Port-related initialization code. + * @note This function is empty in this port. + */ +#define port_init() + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform more + * actions. + * @note Implemented as global interrupt disable. + */ +#define port_lock() asm volatile ("dint" : : : "memory") + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform more + * actions. + * @note Implemented as global interrupt enable. + */ +#define port_unlock() asm volatile ("eint" : : : "memory") + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependen#define PORT_IRQ_EPILOGUE() { \ + if (chSchIsPreemptionRequired()) \ + chSchDoReschedule(); \ +} + * t, + * in its simplest form it is void. + * @note This function is empty in this port. + */ +#define port_lock_from_isr() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + * @note This function is empty in this port. + */ +#define port_unlock_from_isr() + +/** + * @brief Disables all the interrupt sources. + * @note Of course non-maskable interrupt sources are not included. + * @note Implemented as global interrupt disable. + */ +#define port_disable() asm volatile ("dint" : : : "memory") + +/** + * @brief Disables the interrupt sources below kernel-level priority. + * @note Interrupt sources above kernel level remains enabled. + * @note Same as @p port_disable() in this port, there is no difference + * between the two states. + */ +#define port_suspend() asm volatile ("dint" : : : "memory") + +/** + * @brief Enables all the interrupt sources. + * @note Implemented as global interrupt enable. + */ +#define port_enable() asm volatile ("eint" : : : "memory") + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note This port function is implemented as inlined code for performance + * reasons. + * @note The port code does not define a low power mode, this macro has to + * be defined externally. The default implementation is a "nop", not + * a real low power mode. + */ +#if ENABLE_WFI_IDLE != 0 +#ifndef port_wait_for_interrupt +#define port_wait_for_interrupt() { \ + asm volatile ("nop" : : : "memory"); \ +} +#endif +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Wrapper of the assembler @p _port_switch() function. + */ +#define port_switch(ntp, otp) _port_switch(ntp, otp) + +/** + * @brief Wrapper of the assembler @p _port_halt() function. + */ +#define port_halt() _port_halt() + +#ifdef __cplusplus +extern "C" { +#endif + void _port_switch(Thread *ntp, Thread *otp); + void _port_halt(void); + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/MSP430/chtypes.h b/Project/os/ports/GCC/MSP430/chtypes.h new file mode 100644 index 0000000..6f0d661 --- /dev/null +++ b/Project/os/ports/GCC/MSP430/chtypes.h @@ -0,0 +1,90 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file MSP430/chtypes.h + * @brief MSP430 architecture port system types. + * + * @addtogroup MSP430_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#define __need_NULL +#define __need_size_t +#define __need_ptrdiff_t +#include + +#if !defined(_STDINT_H) && !defined(__STDINT_H_) +#include +#endif + +typedef int16_t bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint16_t tprio_t; /**< Thread priority. */ +typedef int16_t msg_t; /**< Inter-thread message. */ +typedef int16_t eventid_t; /**< Event Id. */ +typedef uint16_t eventmask_t; /**< Events mask. */ +typedef uint16_t systime_t; /**< System time. */ +typedef int16_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE inline + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note It uses the "packed" GCC attribute. + */ +#define PACK_STRUCT_STRUCT __attribute__((packed)) + +/** + * @brief Packed structure modifier (before). + * @note Empty in this port. + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/MSP430/port.dox b/Project/os/ports/GCC/MSP430/port.dox new file mode 100644 index 0000000..8c0f7bf --- /dev/null +++ b/Project/os/ports/GCC/MSP430/port.dox @@ -0,0 +1,102 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup MSP430 MSP430 + * @details MSP430 port for the GCC compiler. + * + * @section MSP430_INTRO Introduction + * This port supports all the cores implementing the MSP430 architecture. + * + * @section MSP430_STATES Mapping of the System States in the MSP430 port + * The ChibiOS/RT logical @ref system_states are mapped as follow in the MSP430 + * port: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). Interrupts are enabled. + * - Suspended. Interrupts are disabled. + * - Disabled. Interrupts are disabled. This state is equivalent to the + * Suspended state because there are no fast interrupts in this architecture. + * - Sleep. Not yet implemented. + * - S-Locked. Interrupts are disabled. + * - I-Locked. This state is equivalent to the SRI state, the + * @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in + * order to formally change state because this may change). + * - Serving Regular Interrupt. Normal interrupt service code. + * - Serving Fast Interrupt. Not present in this architecture. + * - Serving Non-Maskable Interrupt. The MSP430 has several non + * maskable interrupt sources that can be associated to this state. + * - Halted. Implemented as an infinite loop with interrupts disabled. + * . + * @section MSP430_NOTES The MSP430 port notes + * - The MSP430 does not have a dedicated interrupt stack, make sure to reserve + * enough stack space for interrupts in each thread stack. This can be done + * by modifying the @p INT_REQUIRED_STACK configuration options. + * - The state of the hardware multiplier is not saved in the thread context, + * make sure to use it in Suspended state (interrupts masked). + * - The port code does not define the switch to a low power mode for the + * idle thread because the MSP430 has several low power modes. You can + * select the proper low power mode for you application by defining the + * macro @p port_wait_for_interrupt(). + * . + * @ingroup gcc + */ + +/** + * @defgroup MSP430_CONF Configuration Options + * @details MSP430 Configuration Options. The MSP430 port allows some + * architecture-specific configurations settings that can be overridden + * by redefining them in @p chconf.h. Usually there is no need to change + * the default values. + * - @p INT_REQUIRED_STACK, this value represent the amount of stack space + * used by the interrupt handlers.
+ * The default for this value is @p 32, this space is allocated for each + * thread so be careful in order to not waste precious RAM space. + * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE + * thread. Usually there is no need to change this value unless inserting + * code in the IDLE thread hook macro. + * . + * @ingroup MSP430 + */ + +/** + * @defgroup MSP430_CORE Core Port Implementation + * @details MSP430 specific port code, structures and macros. + * + * @ingroup MSP430 + */ + + /** + * @defgroup MSP430_STARTUP Startup Support + * @details ChibiOS/RT doed not provide startup files for the MSP430, there + * are no special startup requirement so the normal toolchain-provided + * startup files can be used. + * + * @ingroup MSP430 + */ diff --git a/Project/os/ports/GCC/MSP430/port.mk b/Project/os/ports/GCC/MSP430/port.mk new file mode 100644 index 0000000..8291fa9 --- /dev/null +++ b/Project/os/ports/GCC/MSP430/port.mk @@ -0,0 +1,6 @@ +# List of the ChibiOS/RT MSP430 port files. +PORTSRC = + +PORTASM = ${CHIBIOS}/os/ports/GCC/MSP430/chcoreasm.s + +PORTINC = ${CHIBIOS}/os/ports/GCC/MSP430 diff --git a/Project/os/ports/GCC/MSP430/rules.mk b/Project/os/ports/GCC/MSP430/rules.mk new file mode 100644 index 0000000..e5df109 --- /dev/null +++ b/Project/os/ports/GCC/MSP430/rules.mk @@ -0,0 +1,87 @@ +# MSP430 makefile scripts and rules. + +# Automatic compiler options +OPT = $(USE_OPT) +COPT = $(USE_COPT) +CPPOPT = $(USE_CPPOPT) +ifeq ($(USE_LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections +endif + +# Source files groups +SRC = $(CSRC)$(CPPSRC) + +# Object files groups +COBJS = $(CSRC:.c=.o) +CPPOBJS = $(CPPSRC:.cpp=.o) +ASMOBJS = $(ASMSRC:.s=.o) +OBJS = $(ASMOBJS) $(COBJS) $(CPPOBJS) + +# Paths +IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) +LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) + +# Macros +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) + +# Libs +LIBS = $(DLIBS) $(ULIBS) + +MCFLAGS = -mmcu=$(MCU) +ODFLAGS = -x --syms +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) +ifeq ($(LINK_GC),yes) + LDFLAGS = $(MCFLAGS) -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) +else + LDFLAGS = $(MCFLAGS) -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LLIBDIR) +endif + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# Makefile rules +# +all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp MAKE_ALL_RULE_HOOK + +MAKE_ALL_RULE_HOOK: + +$(CPPOBJS) : %.o : %.cpp + @echo + $(CPPC) -c $(CPPFLAGS) -I . $(IINCDIR) $< -o $@ + +$(COBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) -I . $(IINCDIR) $< -o $@ + +$(ASMOBJS) : %.o : %.s + @echo + $(AS) -c $(ASFLAGS) -I . $(IINCDIR) $< -o $@ + +%elf: $(OBJS) + @echo + $(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ + +%hex: %elf + $(HEX) $< $@ + +%bin: %elf + $(BIN) $< $@ + +%dmp: %elf + $(OD) $(ODFLAGS) $< > $@ + +clean: + -rm -f $(OBJS) + -rm -f $(CSRC:.c=.lst) $(CPPSRC:.cpp=.lst) $(ASMSRC:.s=.lst) + -rm -f $(PROJECT).elf $(PROJECT).dmp $(PROJECT).map $(PROJECT).hex $(PROJECT).bin + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/Project/os/ports/GCC/PPC/SPC56x/ivor.s b/Project/os/ports/GCC/PPC/SPC56x/ivor.s new file mode 100644 index 0000000..9dbe2cd --- /dev/null +++ b/Project/os/ports/GCC/PPC/SPC56x/ivor.s @@ -0,0 +1,206 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file SPC56x/ivor.s + * @brief PowerPC IVORx handlers. + * + * @addtogroup PPC_CORE + * @{ + */ + +#include "chconf.h" + +#define FALSE 0 +#define TRUE 1 + +#if !defined(__DOXYGEN__) + /* + * INTC registers address. + */ + .equ INTC_IACKR, 0xfff48010 + .equ INTC_EOIR, 0xfff48018 + + .section .handlers + + /* + * IVOR10 handler (Book-E decrementer). + */ + .align 4 + .globl IVOR10 +IVOR10: + /* Creation of the external stack frame (extctx structure).*/ + stwu %sp, -80(%sp) /* Size of the extctx structure.*/ + stw %r0, 32(%sp) /* Saves GPR0. */ + mfSRR0 %r0 + stw %r0, 8(%sp) /* Saves PC. */ + mfSRR1 %r0 + stw %r0, 12(%sp) /* Saves MSR. */ + mfCR %r0 + stw %r0, 16(%sp) /* Saves CR. */ + mfLR %r0 + stw %r0, 20(%sp) /* Saves LR. */ + mfCTR %r0 + stw %r0, 24(%sp) /* Saves CTR. */ + mfXER %r0 + stw %r0, 28(%sp) /* Saves XER. */ + stw %r3, 36(%sp) /* Saves GPR3...GPR12. */ + stw %r4, 40(%sp) + stw %r5, 44(%sp) + stw %r6, 48(%sp) + stw %r7, 52(%sp) + stw %r8, 56(%sp) + stw %r9, 60(%sp) + stw %r10, 64(%sp) + stw %r11, 68(%sp) + stw %r12, 72(%sp) + + /* Reset DIE bit in TSR register.*/ + lis %r3, 0x0800 /* DIS bit mask. */ + mtspr 336, %r3 /* TSR register. */ + +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_enter_isr + bl dbg_check_lock_from_isr +#endif + bl chSysTimerHandlerI +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock_from_isr + bl dbg_check_leave_isr +#endif + + /* System tick handler invocation.*/ +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_lock +#endif + bl chSchIsPreemptionRequired + cmpli cr0, %r3, 0 + beq cr0, .ctxrestore + bl chSchDoReschedule + b .ctxrestore + + /* + * IVOR4 handler (Book-E external interrupt). + */ + .align 4 + .globl IVOR4 +IVOR4: + /* Creation of the external stack frame (extctx structure).*/ + stwu %sp, -80(%sp) /* Size of the extctx structure.*/ + stw %r0, 32(%sp) /* Saves GPR0. */ + mfSRR0 %r0 + stw %r0, 8(%sp) /* Saves PC. */ + mfSRR1 %r0 + stw %r0, 12(%sp) /* Saves MSR. */ + mfCR %r0 + stw %r0, 16(%sp) /* Saves CR. */ + mfLR %r0 + stw %r0, 20(%sp) /* Saves LR. */ + mfCTR %r0 + stw %r0, 24(%sp) /* Saves CTR. */ + mfXER %r0 + stw %r0, 28(%sp) /* Saves XER. */ + stw %r3, 36(%sp) /* Saves GPR3...GPR12. */ + stw %r4, 40(%sp) + stw %r5, 44(%sp) + stw %r6, 48(%sp) + stw %r7, 52(%sp) + stw %r8, 56(%sp) + stw %r9, 60(%sp) + stw %r10, 64(%sp) + stw %r11, 68(%sp) + stw %r12, 72(%sp) + + /* Software vector address from the INTC register.*/ + lis %r3, INTC_IACKR@h + ori %r3, %r3, INTC_IACKR@l /* IACKR register address. */ + lwz %r3, 0(%r3) /* IACKR register value. */ + lwz %r3, 0(%r3) + mtCTR %r3 /* Software handler address. */ + +#if PPC_USE_IRQ_PREEMPTION + /* Allows preemption while executing the software handler.*/ + wrteei 1 +#endif + + /* Exectes the software handler.*/ + bctrl + +#if PPC_USE_IRQ_PREEMPTION + /* Prevents preemption again.*/ + wrteei 0 +#endif + + /* Informs the INTC that the interrupt has been served.*/ + mbar 0 + lis %r3, INTC_EOIR@h + ori %r3, %r3, INTC_EOIR@l + stw %r3, 0(%r3) /* Writing any value should do. */ + + /* Verifies if a reschedule is required.*/ +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_lock +#endif + bl chSchIsPreemptionRequired + cmpli cr0, %r3, 0 + beq cr0, .ctxrestore + bl chSchDoReschedule + + /* Context restore.*/ +.ctxrestore: +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif + lwz %r3, 36(%sp) /* Restores GPR3...GPR12. */ + lwz %r4, 40(%sp) + lwz %r5, 44(%sp) + lwz %r6, 48(%sp) + lwz %r7, 52(%sp) + lwz %r8, 56(%sp) + lwz %r9, 60(%sp) + lwz %r10, 64(%sp) + lwz %r11, 68(%sp) + lwz %r12, 72(%sp) + lwz %r0, 8(%sp) + mtSRR0 %r0 /* Restores PC. */ + lwz %r0, 12(%sp) + mtSRR1 %r0 /* Restores MSR. */ + lwz %r0, 16(%sp) + mtCR %r0 /* Restores CR. */ + lwz %r0, 20(%sp) + mtLR %r0 /* Restores LR. */ + lwz %r0, 24(%sp) + mtCTR %r0 /* Restores CTR. */ + lwz %r0, 28(%sp) + mtXER %r0 /* Restores XER. */ + lwz %r0, 32(%sp) /* Restores GPR0. */ + addi %sp, %sp, 80 /* Back to the previous frame. */ + rfi + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/Project/os/ports/GCC/PPC/SPC56x/vectors.s b/Project/os/ports/GCC/PPC/SPC56x/vectors.s new file mode 100644 index 0000000..21f19e3 --- /dev/null +++ b/Project/os/ports/GCC/PPC/SPC56x/vectors.s @@ -0,0 +1,1502 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file SPC56x/vectors.s + * @brief SPC56x vectors table. + * + * @addtogroup PPC_CORE + * @{ + */ +/** @cond never */ + + /* + * BAM info, SWT off, WTE off, VLE off. + */ + .section .bam + .long 0x005A0000 + .long _boot_address + + /* + * Software vectors table. The vectors are accessed from the IVOR4 + * handler only. In order to declare an interrupt handler just create + * a function withe the same name of a vector, the symbol will + * override the weak symbol declared here. + */ + .section .vectors + .align 4 + .globl _vectors +_vectors: + .long vector0 + .long vector1 + .long vector2 + .long vector3 + .long vector4 + .long vector5 + .long vector6 + .long vector7 + .long vector8 + .long vector9 + .long vector10 + .long vector11 + .long vector12 + .long vector13 + .long vector14 + .long vector15 + .long vector16 + .long vector17 + .long vector18 + .long vector19 + .long vector20 + .long vector21 + .long vector22 + .long vector23 + .long vector24 + .long vector25 + .long vector26 + .long vector27 + .long vector28 + .long vector29 + .long vector30 + .long vector31 + .long vector32 + .long vector33 + .long vector34 + .long vector35 + .long vector36 + .long vector37 + .long vector38 + .long vector39 + .long vector40 + .long vector41 + .long vector42 + .long vector43 + .long vector44 + .long vector45 + .long vector46 + .long vector47 + .long vector48 + .long vector49 + .long vector50 + .long vector51 + .long vector52 + .long vector53 + .long vector54 + .long vector55 + .long vector56 + .long vector57 + .long vector58 + .long vector59 + .long vector60 + .long vector61 + .long vector62 + .long vector63 + .long vector64 + .long vector65 + .long vector66 + .long vector67 + .long vector68 + .long vector69 + .long vector70 + .long vector71 + .long vector72 + .long vector73 + .long vector74 + .long vector75 + .long vector76 + .long vector77 + .long vector78 + .long vector79 + .long vector80 + .long vector81 + .long vector82 + .long vector83 + .long vector84 + .long vector85 + .long vector86 + .long vector87 + .long vector88 + .long vector89 + .long vector90 + .long vector91 + .long vector92 + .long vector93 + .long vector94 + .long vector95 + .long vector96 + .long vector97 + .long vector98 + .long vector99 + .long vector100 + .long vector101 + .long vector102 + .long vector103 + .long vector104 + .long vector105 + .long vector106 + .long vector107 + .long vector108 + .long vector109 + .long vector110 + .long vector111 + .long vector112 + .long vector113 + .long vector114 + .long vector115 + .long vector116 + .long vector117 + .long vector118 + .long vector119 + .long vector120 + .long vector121 + .long vector122 + .long vector123 + .long vector124 + .long vector125 + .long vector126 + .long vector127 + .long vector128 + .long vector129 + .long vector130 + .long vector131 + .long vector132 + .long vector133 + .long vector134 + .long vector135 + .long vector136 + .long vector137 + .long vector138 + .long vector139 + .long vector140 + .long vector141 + .long vector142 + .long vector143 + .long vector144 + .long vector145 + .long vector146 + .long vector147 + .long vector148 + .long vector149 + .long vector150 + .long vector151 + .long vector152 + .long vector153 + .long vector154 + .long vector155 + .long vector156 + .long vector157 + .long vector158 + .long vector159 + .long vector160 + .long vector161 + .long vector162 + .long vector163 + .long vector164 + .long vector165 + .long vector166 + .long vector167 + .long vector168 + .long vector169 + .long vector170 + .long vector171 + .long vector172 + .long vector173 + .long vector174 + .long vector175 + .long vector176 + .long vector177 + .long vector178 + .long vector179 + .long vector180 + .long vector181 + .long vector182 + .long vector183 + .long vector184 + .long vector185 + .long vector186 + .long vector187 + .long vector188 + .long vector189 + .long vector190 + .long vector191 + .long vector192 + .long vector193 + .long vector194 + .long vector195 + .long vector196 + .long vector197 + .long vector198 + .long vector199 + .long vector200 + .long vector201 + .long vector202 + .long vector203 + .long vector204 + .long vector205 + .long vector206 + .long vector207 + .long vector208 + .long vector209 + .long vector210 + .long vector211 + .long vector212 + .long vector213 + .long vector214 + .long vector215 + .long vector216 + .long vector217 + .long vector218 + .long vector219 + .long vector220 + .long vector221 + .long vector222 + .long vector223 + .long vector224 + .long vector225 + .long vector226 + .long vector227 + .long vector228 + .long vector229 + .long vector230 + .long vector231 + .long vector232 + .long vector233 + .long vector234 + .long vector235 + .long vector236 + .long vector237 + .long vector238 + .long vector239 + .long vector240 + .long vector241 + .long vector242 + .long vector243 + .long vector244 + .long vector245 + .long vector246 + .long vector247 + .long vector248 + .long vector249 + .long vector250 + .long vector251 + .long vector252 + .long vector253 + .long vector254 + .long vector255 + .long vector256 + .long vector257 + .long vector258 + .long vector259 + .long vector260 + .long vector261 + .long vector262 + .long vector263 + .long vector264 + .long vector265 + .long vector266 + .long vector267 + .long vector268 + .long vector269 + .long vector270 + .long vector271 + .long vector272 + .long vector273 + .long vector274 + .long vector275 + .long vector276 + .long vector277 + .long vector278 + .long vector279 + .long vector280 + .long vector281 + .long vector282 + .long vector283 + .long vector284 + .long vector285 + .long vector286 + .long vector287 + .long vector288 + .long vector289 + .long vector290 + .long vector291 + .long vector292 + .long vector293 + .long vector294 + .long vector295 + .long vector296 + .long vector297 + .long vector298 + .long vector299 + .long vector300 + .long vector301 + .long vector302 + .long vector303 + .long vector304 + .long vector305 + .long vector306 + .long vector307 + .long vector308 + .long vector309 + .long vector310 + .long vector311 + .long vector312 + .long vector313 + .long vector314 + .long vector315 + .long vector316 + .long vector317 + .long vector318 + .long vector319 + .long vector320 + .long vector321 + .long vector322 + .long vector323 + .long vector324 + .long vector325 + .long vector326 + .long vector327 + .long vector328 + .long vector329 + .long vector330 + .long vector331 + .long vector332 + .long vector333 + .long vector334 + .long vector335 + .long vector336 + .long vector337 + .long vector338 + .long vector339 + .long vector340 + .long vector341 + .long vector342 + .long vector343 + .long vector344 + .long vector345 + .long vector346 + .long vector347 + .long vector348 + .long vector349 + .long vector350 + .long vector351 + .long vector352 + .long vector353 + .long vector354 + .long vector355 + .long vector356 + .long vector357 + .long vector358 + .long vector359 + + .text + .align 2 + .weak vector0 +vector0: + + .weak vector1 +vector1: + + .weak vector2 +vector2: + + .weak vector3 +vector3: + + .weak vector4 +vector4: + + .weak vector5 +vector5: + + .weak vector6 +vector6: + + .weak vector7 +vector7: + + .weak vector8 +vector8: + + .weak vector9 +vector9: + + .weak vector10 +vector10: + + .weak vector11 +vector11: + + .weak vector12 +vector12: + + .weak vector13 +vector13: + + .weak vector14 +vector14: + + .weak vector15 +vector15: + + .weak vector16 +vector16: + + .weak vector17 +vector17: + + .weak vector18 +vector18: + + .weak vector19 +vector19: + + .weak vector20 +vector20: + + .weak vector21 +vector21: + + .weak vector22 +vector22: + + .weak vector23 +vector23: + + .weak vector24 +vector24: + + .weak vector25 +vector25: + + .weak vector26 +vector26: + + .weak vector27 +vector27: + + .weak vector28 +vector28: + + .weak vector29 +vector29: + + .weak vector30 +vector30: + + .weak vector31 +vector31: + + .weak vector32 +vector32: + + .weak vector33 +vector33: + + .weak vector34 +vector34: + + .weak vector35 +vector35: + + .weak vector36 +vector36: + + .weak vector37 +vector37: + + .weak vector38 +vector38: + + .weak vector39 +vector39: + + .weak vector40 +vector40: + + .weak vector41 +vector41: + + .weak vector42 +vector42: + + .weak vector43 +vector43: + + .weak vector44 +vector44: + + .weak vector45 +vector45: + + .weak vector46 +vector46: + + .weak vector47 +vector47: + + .weak vector48 +vector48: + + .weak vector49 +vector49: + + .weak vector50 +vector50: + + .weak vector51 +vector51: + + .weak vector52 +vector52: + + .weak vector53 +vector53: + + .weak vector54 +vector54: + + .weak vector55 +vector55: + + .weak vector56 +vector56: + + .weak vector57 +vector57: + + .weak vector58 +vector58: + + .weak vector59 +vector59: + + .weak vector60 +vector60: + + .weak vector61 +vector61: + + .weak vector62 +vector62: + + .weak vector63 +vector63: + + .weak vector64 +vector64: + + .weak vector65 +vector65: + + .weak vector66 +vector66: + + .weak vector67 +vector67: + + .weak vector68 +vector68: + + .weak vector69 +vector69: + + .weak vector70 +vector70: + + .weak vector71 +vector71: + + .weak vector72 +vector72: + + .weak vector73 +vector73: + + .weak vector74 +vector74: + + .weak vector75 +vector75: + + .weak vector76 +vector76: + + .weak vector77 +vector77: + + .weak vector78 +vector78: + + .weak vector79 +vector79: + + .weak vector80 +vector80: + + .weak vector81 +vector81: + + .weak vector82 +vector82: + + .weak vector83 +vector83: + + .weak vector84 +vector84: + + .weak vector85 +vector85: + + .weak vector86 +vector86: + + .weak vector87 +vector87: + + .weak vector88 +vector88: + + .weak vector89 +vector89: + + .weak vector90 +vector90: + + .weak vector91 +vector91: + + .weak vector92 +vector92: + + .weak vector93 +vector93: + + .weak vector94 +vector94: + + .weak vector95 +vector95: + + .weak vector96 +vector96: + + .weak vector97 +vector97: + + .weak vector98 +vector98: + + .weak vector99 +vector99: + + .weak vector100 +vector100: + + .weak vector101 +vector101: + + .weak vector102 +vector102: + + .weak vector103 +vector103: + + .weak vector104 +vector104: + + .weak vector105 +vector105: + + .weak vector106 +vector106: + + .weak vector107 +vector107: + + .weak vector108 +vector108: + + .weak vector109 +vector109: + + .weak vector110 +vector110: + + .weak vector111 +vector111: + + .weak vector112 +vector112: + + .weak vector113 +vector113: + + .weak vector114 +vector114: + + .weak vector115 +vector115: + + .weak vector116 +vector116: + + .weak vector117 +vector117: + + .weak vector118 +vector118: + + .weak vector119 +vector119: + + .weak vector120 +vector120: + + .weak vector121 +vector121: + + .weak vector122 +vector122: + + .weak vector123 +vector123: + + .weak vector124 +vector124: + + .weak vector125 +vector125: + + .weak vector126 +vector126: + + .weak vector127 +vector127: + + .weak vector128 +vector128: + + .weak vector129 +vector129: + + .weak vector130 +vector130: + + .weak vector131 +vector131: + + .weak vector132 +vector132: + + .weak vector133 +vector133: + + .weak vector134 +vector134: + + .weak vector135 +vector135: + + .weak vector136 +vector136: + + .weak vector137 +vector137: + + .weak vector138 +vector138: + + .weak vector139 +vector139: + + .weak vector140 +vector140: + + .weak vector141 +vector141: + + .weak vector142 +vector142: + + .weak vector143 +vector143: + + .weak vector144 +vector144: + + .weak vector145 +vector145: + + .weak vector146 +vector146: + + .weak vector147 +vector147: + + .weak vector148 +vector148: + + .weak vector149 +vector149: + + .weak vector150 +vector150: + + .weak vector151 +vector151: + + .weak vector152 +vector152: + + .weak vector153 +vector153: + + .weak vector154 +vector154: + + .weak vector155 +vector155: + + .weak vector156 +vector156: + + .weak vector157 +vector157: + + .weak vector158 +vector158: + + .weak vector159 +vector159: + + .weak vector160 +vector160: + + .weak vector161 +vector161: + + .weak vector162 +vector162: + + .weak vector163 +vector163: + + .weak vector164 +vector164: + + .weak vector165 +vector165: + + .weak vector166 +vector166: + + .weak vector167 +vector167: + + .weak vector168 +vector168: + + .weak vector169 +vector169: + + .weak vector170 +vector170: + + .weak vector171 +vector171: + + .weak vector172 +vector172: + + .weak vector173 +vector173: + + .weak vector174 +vector174: + + .weak vector175 +vector175: + + .weak vector176 +vector176: + + .weak vector177 +vector177: + + .weak vector178 +vector178: + + .weak vector179 +vector179: + + .weak vector180 +vector180: + + .weak vector181 +vector181: + + .weak vector182 +vector182: + + .weak vector183 +vector183: + + .weak vector184 +vector184: + + .weak vector185 +vector185: + + .weak vector186 +vector186: + + .weak vector187 +vector187: + + .weak vector188 +vector188: + + .weak vector189 +vector189: + + .weak vector190 +vector190: + + .weak vector191 +vector191: + + .weak vector192 +vector192: + + .weak vector193 +vector193: + + .weak vector194 +vector194: + + .weak vector195 +vector195: + + .weak vector196 +vector196: + + .weak vector197 +vector197: + + .weak vector198 +vector198: + + .weak vector199 +vector199: + + .weak vector200 +vector200: + + .weak vector201 +vector201: + + .weak vector202 +vector202: + + .weak vector203 +vector203: + + .weak vector204 +vector204: + + .weak vector205 +vector205: + + .weak vector206 +vector206: + + .weak vector207 +vector207: + + .weak vector208 +vector208: + + .weak vector209 +vector209: + + .weak vector210 +vector210: + + .weak vector211 +vector211: + + .weak vector212 +vector212: + + .weak vector213 +vector213: + + .weak vector214 +vector214: + + .weak vector215 +vector215: + + .weak vector216 +vector216: + + .weak vector217 +vector217: + + .weak vector218 +vector218: + + .weak vector219 +vector219: + + .weak vector220 +vector220: + + .weak vector221 +vector221: + + .weak vector222 +vector222: + + .weak vector223 +vector223: + + .weak vector224 +vector224: + + .weak vector225 +vector225: + + .weak vector226 +vector226: + + .weak vector227 +vector227: + + .weak vector228 +vector228: + + .weak vector229 +vector229: + + .weak vector230 +vector230: + + .weak vector231 +vector231: + + .weak vector232 +vector232: + + .weak vector233 +vector233: + + .weak vector234 +vector234: + + .weak vector235 +vector235: + + .weak vector236 +vector236: + + .weak vector237 +vector237: + + .weak vector238 +vector238: + + .weak vector239 +vector239: + + .weak vector240 +vector240: + + .weak vector241 +vector241: + + .weak vector242 +vector242: + + .weak vector243 +vector243: + + .weak vector244 +vector244: + + .weak vector245 +vector245: + + .weak vector246 +vector246: + + .weak vector247 +vector247: + + .weak vector248 +vector248: + + .weak vector249 +vector249: + + .weak vector250 +vector250: + + .weak vector251 +vector251: + + .weak vector252 +vector252: + + .weak vector253 +vector253: + + .weak vector254 +vector254: + + .weak vector255 +vector255: + + .weak vector256 +vector256: + + .weak vector257 +vector257: + + .weak vector258 +vector258: + + .weak vector259 +vector259: + + .weak vector260 +vector260: + + .weak vector261 +vector261: + + .weak vector262 +vector262: + + .weak vector263 +vector263: + + .weak vector264 +vector264: + + .weak vector265 +vector265: + + .weak vector266 +vector266: + + .weak vector267 +vector267: + + .weak vector268 +vector268: + + .weak vector269 +vector269: + + .weak vector270 +vector270: + + .weak vector271 +vector271: + + .weak vector272 +vector272: + + .weak vector273 +vector273: + + .weak vector274 +vector274: + + .weak vector275 +vector275: + + .weak vector276 +vector276: + + .weak vector277 +vector277: + + .weak vector278 +vector278: + + .weak vector279 +vector279: + + .weak vector280 +vector280: + + .weak vector281 +vector281: + + .weak vector282 +vector282: + + .weak vector283 +vector283: + + .weak vector284 +vector284: + + .weak vector285 +vector285: + + .weak vector286 +vector286: + + .weak vector287 +vector287: + + .weak vector288 +vector288: + + .weak vector289 +vector289: + + .weak vector290 +vector290: + + .weak vector291 +vector291: + + .weak vector292 +vector292: + + .weak vector293 +vector293: + + .weak vector294 +vector294: + + .weak vector295 +vector295: + + .weak vector296 +vector296: + + .weak vector297 +vector297: + + .weak vector298 +vector298: + + .weak vector299 +vector299: + + .weak vector300 +vector300: + + .weak vector301 +vector301: + + .weak vector302 +vector302: + + .weak vector303 +vector303: + + .weak vector304 +vector304: + + .weak vector305 +vector305: + + .weak vector306 +vector306: + + .weak vector307 +vector307: + + .weak vector308 +vector308: + + .weak vector309 +vector309: + + .weak vector310 +vector310: + + .weak vector311 +vector311: + + .weak vector312 +vector312: + + .weak vector313 +vector313: + + .weak vector314 +vector314: + + .weak vector315 +vector315: + + .weak vector316 +vector316: + + .weak vector317 +vector317: + + .weak vector318 +vector318: + + .weak vector319 +vector319: + + .weak vector320 +vector320: + + .weak vector321 +vector321: + + .weak vector322 +vector322: + + .weak vector323 +vector323: + + .weak vector324 +vector324: + + .weak vector325 +vector325: + + .weak vector326 +vector326: + + .weak vector327 +vector327: + + .weak vector328 +vector328: + + .weak vector329 +vector329: + + .weak vector330 +vector330: + + .weak vector331 +vector331: + + .weak vector332 +vector332: + + .weak vector333 +vector333: + + .weak vector334 +vector334: + + .weak vector335 +vector335: + + .weak vector336 +vector336: + + .weak vector337 +vector337: + + .weak vector338 +vector338: + + .weak vector339 +vector339: + + .weak vector340 +vector340: + + .weak vector341 +vector341: + + .weak vector342 +vector342: + + .weak vector343 +vector343: + + .weak vector344 +vector344: + + .weak vector345 +vector345: + + .weak vector346 +vector346: + + .weak vector347 +vector347: + + .weak vector348 +vector348: + + .weak vector349 +vector349: + + .weak vector350 +vector350: + + .weak vector351 +vector351: + + .weak vector352 +vector352: + + .weak vector353 +vector353: + + .weak vector354 +vector354: + + .weak vector355 +vector355: + + .weak vector356 +vector356: + + .weak vector357 +vector357: + + .weak vector358 +vector358: + + .weak vector359 +vector359: + + .globl _unhandled_irq +_unhandled_irq: + b _unhandled_irq + +/** @endcond */ +/** @} */ diff --git a/Project/os/ports/GCC/PPC/chcore.c b/Project/os/ports/GCC/PPC/chcore.c new file mode 100644 index 0000000..4cda949 --- /dev/null +++ b/Project/os/ports/GCC/PPC/chcore.c @@ -0,0 +1,99 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file PPC/chcore.c + * @brief PowerPC architecture port code. + * + * @addtogroup PPC_CORE + * @{ + */ + +#include "ch.h" + +/** + * @brief Halts the system. + * @details This function is invoked by the operating system when an + * unrecoverable error is detected (for example because a programming + * error in the application code that triggers an assertion while + * in debug mode). + */ +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +void port_switch(Thread *ntp, Thread *otp) { + + (void)otp; + (void)ntp; + + asm ("subi %sp, %sp, 80"); /* Size of the intctx structure. */ + asm ("mflr %r0"); + asm ("stw %r0, 84(%sp)"); /* LR into the caller frame. */ + asm ("mfcr %r0"); + asm ("stw %r0, 0(%sp)"); /* CR. */ + asm ("stmw %r14, 4(%sp)"); /* GPR14...GPR31. */ + + asm ("stw %sp, 12(%r4)"); /* Store swapped-out stack. */ + asm ("lwz %sp, 12(%r3)"); /* Load swapped-in stack. */ + + asm ("lmw %r14, 4(%sp)"); /* GPR14...GPR31. */ + asm ("lwz %r0, 0(%sp)"); /* CR. */ + asm ("mtcr %r0"); + asm ("lwz %r0, 84(%sp)"); /* LR from the caller frame. */ + asm ("mtlr %r0"); + asm ("addi %sp, %sp, 80"); /* Size of the intctx structure. */ +} + +/** + * @brief Start a thread by invoking its work function. + * @details If the work function returns @p chThdExit() is automatically + * invoked. + */ +void _port_thread_start(void) { + + chSysUnlock(); + asm ("mr %r3, %r31"); /* Thread parameter. */ + asm ("mtctr %r30"); + asm ("bctrl"); /* Invoke thread function. */ + asm ("bl chThdExit"); /* Thread termination on exit. */ +} + +/** @} */ diff --git a/Project/os/ports/GCC/PPC/chcore.h b/Project/os/ports/GCC/PPC/chcore.h new file mode 100644 index 0000000..9e83b5e --- /dev/null +++ b/Project/os/ports/GCC/PPC/chcore.h @@ -0,0 +1,341 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file PPC/chcore.h + * @brief PowerPC architecture port macros and structures. + * + * @addtogroup PPC_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +#if CH_DBG_ENABLE_STACK_CHECK +#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port" +#endif + +/* + * Port-related configuration parameters. + */ + +/** + * @brief Enables the use of the @p WFI instruction. + */ +#ifndef ENABLE_WFI_IDLE +#define ENABLE_WFI_IDLE 0 +#endif + +/* Core variants identifiers.*/ +#define PPC_VARIANT_e200z3 3 /**< e200z3 core identifier. */ +#define PPC_VARIANT_e200z4 4 /**< e200z4 core identifier. */ + +/** + * @brief Core variant selector. + * @details This setting affects the predefined architecture strings and + * possibly code paths and structures into the port layer. + */ +#if !defined(PPC_VARIANT) || defined(__DOXYGEN__) +#define PPC_VARIANT PPC_VARIANT_e200z3 +#endif + +/** + * @brief Unique macro for the implemented architecture. + */ +#define CH_ARCHITECTURE_PPC + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "Power Architecture" + +/** + * @brief Name of the architecture variant. + */ +#if (PPC_VARIANT == PPC_VARIANT_e200z3) || defined(__DOXYGEN__) +#define CH_CORE_VARIANT_NAME "e200z3" +#elif PPC_VARIANT == PPC_VARIANT_e200z4 +#define CH_CORE_VARIANT_NAME "e200z4" +#else +#error "unknown or unsupported PowerPC variant specified" +#endif + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "GCC " __VERSION__ + +/** + * @brief Port-specific information string. + */ +#define CH_PORT_INFO "None" + +/** + * @brief Base type for stack and memory alignment. + */ +typedef struct { + uint8_t a[8]; +} stkalign_t __attribute__((aligned(8))); + +/** + * @brief Generic PPC register. + */ +typedef void *regppc_t; + +/** + * @brief Mandatory part of a stack frame. + */ +struct eabi_frame { + regppc_t slink; /**< Stack back link. */ + regppc_t shole; /**< Stack hole for LR storage. */ +}; + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + * @note R2 and R13 are not saved because those are assumed to be immutable + * during the system life cycle. + */ +struct extctx { + struct eabi_frame frame; + /* Start of the e_stmvsrrw frame (offset 8).*/ + regppc_t pc; + regppc_t msr; + /* Start of the e_stmvsprw frame (offset 16).*/ + regppc_t cr; + regppc_t lr; + regppc_t ctr; + regppc_t xer; + /* Start of the e_stmvgprw frame (offset 32).*/ + regppc_t r0; + regppc_t r3; + regppc_t r4; + regppc_t r5; + regppc_t r6; + regppc_t r7; + regppc_t r8; + regppc_t r9; + regppc_t r10; + regppc_t r11; + regppc_t r12; + regppc_t padding; + }; + + /** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching. + * @note R2 and R13 are not saved because those are assumed to be immutable + * during the system life cycle. + * @note LR is stored in the caller contex so it is not present in this + * structure. + */ +struct intctx { + regppc_t cr; /* Part of it is not volatile... */ + regppc_t r14; + regppc_t r15; + regppc_t r16; + regppc_t r17; + regppc_t r18; + regppc_t r19; + regppc_t r20; + regppc_t r21; + regppc_t r22; + regppc_t r23; + regppc_t r24; + regppc_t r25; + regppc_t r26; + regppc_t r27; + regppc_t r28; + regppc_t r29; + regppc_t r30; + regppc_t r31; + regppc_t padding; +}; + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details This structure usually contains just the saved stack pointer + * defined as a pointer to a @p intctx structure. + */ +struct context { + struct intctx *sp; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + uint8_t *sp = (uint8_t *)workspace + wsize - sizeof(struct eabi_frame); \ + ((struct eabi_frame *)sp)->slink = 0; \ + ((struct eabi_frame *)sp)->shole = _port_thread_start; \ + tp->p_ctx.sp = (struct intctx *)(sp - sizeof(struct intctx)); \ + tp->p_ctx.sp->r31 = arg; \ + tp->p_ctx.sp->r30 = pf; \ +} + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + */ +#ifndef PORT_IDLE_THREAD_STACK_SIZE +#define PORT_IDLE_THREAD_STACK_SIZE 0 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * This value can be zero on those architecture where there is a + * separate interrupt stack and the stack space between @p intctx and + * @p extctx is known to be zero. + */ +#ifndef PORT_INT_REQUIRED_STACK +#define PORT_INT_REQUIRED_STACK 128 +#endif + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * @brief Kernel port layer initialization. + * @details IVPR4 and IVPR10 initialization, INTC_IACKR_PRC0 initialization. + */ +#define port_init() { \ + asm volatile ("li %r3, IVOR4@l \t\n" \ + "mtIVOR4 %r3 \t\n" \ + "li %r3, IVOR10@l \t\n" \ + "mtIVOR10 %r3"); \ +} + +/** + * @details Implemented as global interrupt disable. + */ +#define port_lock() asm volatile ("wrteei 0" : : : "memory") + +/** + * @details Implemented as global interrupt enable. + */ +#define port_unlock() asm volatile("wrteei 1" : : : "memory") + +/** + * @details Implemented as global interrupt disable. + */ +#define port_lock_from_isr() /*asm ("wrteei 0")*/ + +/** + * @details Implemented as global interrupt enable. + */ +#define port_unlock_from_isr() /*asm ("wrteei 1")*/ + +/** + * @details Implemented as global interrupt disable. + */ +#define port_disable() asm volatile ("wrteei 0" : : : "memory") + +/** + * @details Same as @p port_disable() in this port, there is no difference + * between the two states. + */ +#define port_suspend() asm volatile ("wrteei 0" : : : "memory") + +/** + * @details Implemented as global interrupt enable. + */ +#define port_enable() asm volatile ("wrteei 1" : : : "memory") + +/** + * @details This port function is implemented as inlined code for performance + * reasons. + */ +#if ENABLE_WFI_IDLE != 0 +#ifndef port_wait_for_interrupt +#define port_wait_for_interrupt() { \ + asm volatile ("wait" : : : "memory"); \ +} +#endif +#else +#define port_wait_for_interrupt() +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void port_halt(void); + void port_switch(Thread *ntp, Thread *otp); + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/PPC/chtypes.h b/Project/os/ports/GCC/PPC/chtypes.h new file mode 100644 index 0000000..f7299e0 --- /dev/null +++ b/Project/os/ports/GCC/PPC/chtypes.h @@ -0,0 +1,102 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file PPC/chtypes.h + * @brief PowerPC architecture port system types. + * + * @addtogroup PPC_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#define __need_NULL +#define __need_size_t +#include + +#if !defined(_STDINT_H) && !defined(__STDINT_H_) +#include +#endif + +/* + * Derived generic types. + */ +typedef volatile int8_t vint8_t; /**< Volatile signed 8 bits. */ +typedef volatile uint8_t vuint8_t; /**< Volatile unsigned 8 bits. */ +typedef volatile int16_t vint16_t; /**< Volatile signed 16 bits. */ +typedef volatile uint16_t vuint16_t; /**< Volatile unsigned 16 bits. */ +typedef volatile int32_t vint32_t; /**< Volatile signed 32 bits. */ +typedef volatile uint32_t vuint32_t; /**< Volatile unsigned 32 bits. */ + +/* + * Kernel types. + */ +typedef int32_t bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint32_t tprio_t; /**< Thread priority. */ +typedef int32_t msg_t; /**< Inter-thread message. */ +typedef int32_t eventid_t; /**< Event Id. */ +typedef uint32_t eventmask_t; /**< Events mask. */ +typedef uint32_t systime_t; /**< System time. */ +typedef int32_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE inline + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note It uses the "packed" GCC attribute. + */ +#define PACK_STRUCT_STRUCT __attribute__((packed)) + +/** + * @brief Packed structure modifier (before). + * @note Empty in this port. + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/PPC/crt0.s b/Project/os/ports/GCC/PPC/crt0.s new file mode 100644 index 0000000..272542e --- /dev/null +++ b/Project/os/ports/GCC/PPC/crt0.s @@ -0,0 +1,121 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file PPC/crt0.s + * @brief Generic PowerPC startup file for ChibiOS/RT. + * + * @addtogroup PPC_CORE + * @{ + */ +/** @cond never */ + + .section .text + .align 2 + .globl _boot_address +_boot_address: + /* + * Stack setup. + */ + lis %r1, __ram_end__@h + ori %r1, %r1, __ram_end__@l + li %r0, 0 + stwu %r0, -8(%r1) + /* + * IVPR initialization. + */ + lis %r4, __ivpr_base__@h + mtIVPR %r4 + /* + * Small sections registers initialization. + */ + lis %r2, __sdata2_start__@h + ori %r2, %r2, __sdata2_start__@l + lis %r13, __sdata_start__@h + ori %r13, %r13, __sdata_start__@l + /* + * Early initialization. + */ + bl __early_init + /* + * BSS clearing. + */ + lis %r4, __bss_start__@h + ori %r4, %r4, __bss_start__@l + lis %r5, __bss_end__@h + ori %r5, %r5, __bss_end__@l + li %r7, 0 +.bssloop: + cmpl cr0, %r4, %r5 + bge cr0, .bssend + stw %r7, 0(%r4) + addi %r4, %r4, 4 + b .bssloop +.bssend: + /* + * DATA initialization. + */ + lis %r4, __romdata_start__@h + ori %r4, %r4, __romdata_start__@l + lis %r5, __data_start__@h + ori %r5, %r5, __data_start__@l + lis %r6, __data_end__@h + ori %r6, %r6, __data_end__@l +.dataloop: + cmpl cr0, %r5, %r6 + bge cr0, .dataend + lwz %r7, 0(%r4) + addi %r4, %r4, 4 + stw %r7, 0(%r5) + addi %r5, %r5, 4 + b .dataloop +.dataend: + /* + * Main program invocation. + */ + bl main + b _main_exit_handler + + /* + * Default main exit code, infinite loop. + */ + .weak _main_exit_handler + .globl _main_exit_handler +_main_exit_handler: +forever: + b forever + + /* + * Default initialization code, none. + */ + .weak __early_init + .globl __early_init +__early_init: + blr + +/** @endcond */ +/** @} */ diff --git a/Project/os/ports/GCC/PPC/port.dox b/Project/os/ports/GCC/PPC/port.dox new file mode 100644 index 0000000..4afda1a --- /dev/null +++ b/Project/os/ports/GCC/PPC/port.dox @@ -0,0 +1,139 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup PPC Power Architecture + * @details Power Architecture port for the GCC compiler. + * + * @section PPC_INTRO Introduction + * This port supports cores implementing a 32 bits Power Architecture. + * + * @section PPC_STATES Mapping of the System States in the Power Architecture port + * The ChibiOS/RT logical @ref system_states are mapped as follow in the + * PowerPC port: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). Interrupts are enabled. + * - Suspended. Interrupts are disabled. + * - Disabled. Interrupts are disabled. This state is equivalent to the + * Suspended state because there are no fast interrupts in this architecture. + * - Sleep. This state is entered with the execution of the specific + * instruction @p wait. + * - S-Locked. Interrupts are disabled. + * - I-Locked. This state is equivalent to the SRI state, the + * @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in + * order to formally change state because this may change). + * - Serving Regular Interrupt. Normal interrupt service code. + * - Serving Fast Interrupt. Not present in this architecture. + * - Serving Non-Maskable Interrupt. The PowerPC has several non + * maskable interrupt sources that can be associated to this state. + * - Halted. Implemented as an infinite loop with interrupts disabled. + * . + * @section PPC_NOTES The PowerPC port notes + * The PowerPC port is organized as follow: + * - The @p main() function is invoked in privileged mode. + * - Each thread has a private stack with extra storage for interrupts + * servicing. + * - The Book-E Decrementer Timer, mapped on IVOR10, is used for system tick. + * - Interrupt nesting is not currently supported. + * . + * @ingroup gcc + */ + +/** + * @defgroup PPC_CONF Configuration Options + * @details PowerPC Configuration Options. The PowerPC port allows some + * architecture-specific configurations settings that can be overridden by + * redefining them in @p chconf.h. Usually there is no need to change the + * default values. + * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used + * by an interrupt handler between the @p extctx and @p intctx + * structures. + * The default for this value is @p 128 bytes, this space is allocated for + * each thread so be careful in order to not waste precious RAM space. + * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE + * thread. Usually there is no need to change this value unless inserting + * code in the IDLE thread hook macro. + * - @p ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the @p wait + * instruction from within the idle loop. This is defaulted to 0 because + * it can create problems with some debuggers. Setting this option to 1 + * reduces the system power requirements. + * . + * @ingroup PPC + */ + +/** + * @defgroup PPC_CORE Core Port Implementation + * @brief PowerPC specific port code, structures and macros. + * + * @ingroup PPC + */ + +/** + * @defgroup PPC_STARTUP Startup Support + * @brief + * @details PPC startup code support. ChibiOS/RT provides its own generic + * startup file for the PowerPC port. + * Of course it is not mandatory to use it but care should be taken about the + * startup phase details. + * + * @section PPC_STARTUP_1 Startup Process + * The startup process, as implemented, is the following: + * -# The stacks pointer is initialized into the area defined in the linker + * script. + * -# The IVPR register is setup according to the linker script. + * -# The R2 and R13 registers are set to pointer to the SDA areas according + * to the EABI specification. + * -# An early initialization routine @p hwinit0 is invoked, if the symbol is + * not defined then an empty default routine is executed (weak symbol). + * -# DATA and BSS segments are initialized. + * -# A late initialization routine @p hwinit1 is invoked, if the symbol not + * defined then an empty default routine is executed (weak symbol).
+ * This late initialization function is also the proper place for a + * @a bootloader, if your application requires one. + * -# The @p main() function is invoked with the parameters @p argc and @p argv + * set to zero. + * -# Should the @p main() function return a branch is performed to the weak + * symbol @p _main_exit_handler. The default code is an endless empty loop. + * . + * @section PPC_STARTUP_2 Expected linker symbols + * The startup code starts at the symbol @p _boot_address and expects the + * following symbols to be defined in the linker script: + * - @p __ram_end__ RAM end location +1. + * - @p __sdata2_start__ small constants data area + * - @p __sdata_start__ small variables data area + * - @p __romdata_start__ address of the data segment source read only data. + * - @p __data_start__ data segment start location. + * - @p __data_end__ data segment end location +1. + * - @p __bss_start__ BSS start location. + * - @p __bss_end__ BSS end location +1. + * - @p __ivpr_base__ IVPR register initialization address. + * . + * @ingroup PPC + */ diff --git a/Project/os/ports/GCC/PPC/port.mk b/Project/os/ports/GCC/PPC/port.mk new file mode 100644 index 0000000..4f14365 --- /dev/null +++ b/Project/os/ports/GCC/PPC/port.mk @@ -0,0 +1,6 @@ +# List of the ChibiOS/RT PPC port files. +PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c + +PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/crt0.s + +PORTINC = ${CHIBIOS}/os/ports/GCC/PPC diff --git a/Project/os/ports/GCC/PPC/rules.mk b/Project/os/ports/GCC/PPC/rules.mk new file mode 100644 index 0000000..b5f5060 --- /dev/null +++ b/Project/os/ports/GCC/PPC/rules.mk @@ -0,0 +1,90 @@ +# PPC e200Z makefile scripts and rules. + +# Automatic compiler options +OPT = $(USE_OPT) +COPT = $(USE_COPT) +CPPOPT = $(USE_CPPOPT) +ifeq ($(USE_CURRP_CACHING),yes) + OPT += -ffixed-r7 -DCH_CURRP_REGISTER_CACHE='"r7"' +endif +ifeq ($(USE_LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections +endif + +# Source files groups +SRC = $(CSRC)$(CPPSRC) + +# Object files groups +COBJS = $(CSRC:.c=.o) +CPPOBJS = $(CPPSRC:.cpp=.o) +ASMOBJS = $(ASMSRC:.s=.o) +OBJS = $(ASMOBJS) $(COBJS) $(CPPOBJS) + +# Paths +IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) +LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) + +# Macros +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) + +# Libs +LIBS = $(DLIBS) $(ULIBS) + +MCFLAGS = -mcpu=$(MCU) +ODFLAGS = -x --syms +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) +ifeq ($(LINK_GC),yes) + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) +else + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LLIBDIR) +endif + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# Makefile rules +# +all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp MAKE_ALL_RULE_HOOK + +MAKE_ALL_RULE_HOOK: + +$(CPPOBJS) : %.o : %.cpp + @echo + $(CPPC) -c $(CPPFLAGS) -I . $(IINCDIR) $< -o $@ + +$(COBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) -I . $(IINCDIR) $< -o $@ + +$(ASMOBJS) : %.o : %.s + @echo + $(AS) -c $(ASFLAGS) -I . $(IINCDIR) $< -o $@ + +%elf: $(OBJS) + @echo + $(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ + +%hex: %elf + $(HEX) $< $@ + +%bin: %elf + $(BIN) $< $@ + +%dmp: %elf + $(OD) $(ODFLAGS) $< > $@ + +clean: + -rm -f $(OBJS) + -rm -f $(CSRC:.c=.lst) $(CPPSRC:.cpp=.lst) $(ASMSRC:.s=.lst) + -rm -f $(PROJECT).elf $(PROJECT).dmp $(PROJECT).map $(PROJECT).hex $(PROJECT).bin + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/Project/os/ports/GCC/SIMIA32/chcore.c b/Project/os/ports/GCC/SIMIA32/chcore.c new file mode 100644 index 0000000..c1aaf17 --- /dev/null +++ b/Project/os/ports/GCC/SIMIA32/chcore.c @@ -0,0 +1,93 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @addtogroup SIMIA32_CORE + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" + +/** + * Performs a context switch between two threads. + * @param otp the thread to be switched out + * @param ntp the thread to be switched in + */ +__attribute__((used)) +static void __dummy(Thread *ntp, Thread *otp) { + (void)ntp; (void)otp; + + asm volatile ( +#if defined(WIN32) + ".globl @port_switch@8 \n\t" + "@port_switch@8:" +#elif defined(__APPLE__) + ".globl _port_switch \n\t" + "_port_switch:" +#else + ".globl port_switch \n\t" + "port_switch:" +#endif + "push %ebp \n\t" + "push %esi \n\t" + "push %edi \n\t" + "push %ebx \n\t" + "movl %esp, 12(%edx) \n\t" + "movl 12(%ecx), %esp \n\t" + "pop %ebx \n\t" + "pop %edi \n\t" + "pop %esi \n\t" + "pop %ebp \n\t" + "ret"); +} + +/** + * Halts the system. In this implementation it just exits the simulation. + */ +__attribute__((fastcall)) +void port_halt(void) { + + exit(2); +} + +/** + * @brief Start a thread by invoking its work function. + * @details If the work function returns @p chThdExit() is automatically + * invoked. + */ +__attribute__((cdecl, noreturn)) +void _port_thread_start(msg_t (*pf)(void *), void *p) { + + chSysUnlock(); + chThdExit(pf(p)); + while(1); +} + +/** @} */ diff --git a/Project/os/ports/GCC/SIMIA32/chcore.h b/Project/os/ports/GCC/SIMIA32/chcore.h new file mode 100644 index 0000000..7822d0e --- /dev/null +++ b/Project/os/ports/GCC/SIMIA32/chcore.h @@ -0,0 +1,250 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @addtogroup SIMIA32_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +#if CH_DBG_ENABLE_STACK_CHECK +#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port" +#endif + +/** + * Macro defining the a simulated architecture into x86. + */ +#define CH_ARCHITECTURE_SIMIA32 + +/** + * Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "Simulator" + +/** + * @brief Name of the architecture variant (optional). + */ +#define CH_CORE_VARIANT_NAME "x86 (integer only)" + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "GCC " __VERSION__ + +/** + * @brief Port-specific information string. + */ +#define CH_PORT_INFO "No preemption" + +/** + * 16 bytes stack alignment. + */ +typedef struct { + uint8_t a[16]; +} stkalign_t __attribute__((aligned(16))); + +/** + * Generic x86 register. + */ +typedef void *regx86; + +/** + * Interrupt saved context. + * This structure represents the stack frame saved during a preemption-capable + * interrupt handler. + */ +struct extctx { +}; + +/** + * System saved context. + * @note In this demo the floating point registers are not saved. + */ +struct intctx { + regx86 ebx; + regx86 edi; + regx86 esi; + regx86 ebp; + regx86 eip; +}; + +/** + * Platform dependent part of the @p Thread structure. + * This structure usually contains just the saved stack pointer defined as a + * pointer to a @p intctx structure. + */ +struct context { + struct intctx volatile *esp; +}; + +#define APUSH(p, a) (p) -= sizeof(void *), *(void **)(p) = (void*)(a) + +/* Darwin requires the stack to be aligned to a 16-byte boundary at + * the time of a call instruction (in case the called function needs + * to save MMX registers). This aligns to 'mod' module 16, so that we'll end + * up with the right alignment after pushing the args. */ +#define AALIGN(p, mask, mod) p = (void *)((((uintptr_t)(p) - mod) & ~mask) + mod) + +/** + * Platform dependent part of the @p chThdCreateI() API. + * This code usually setup the context switching frame represented by a + * @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + uint8_t *esp = (uint8_t *)workspace + wsize; \ + APUSH(esp, 0); \ + uint8_t *savebp = esp; \ + AALIGN(esp, 15, 8); \ + APUSH(esp, arg); \ + APUSH(esp, pf); \ + APUSH(esp, 0); \ + esp -= sizeof(struct intctx); \ + ((struct intctx *)esp)->eip = _port_thread_start; \ + ((struct intctx *)esp)->ebx = 0; \ + ((struct intctx *)esp)->edi = 0; \ + ((struct intctx *)esp)->esi = 0; \ + ((struct intctx *)esp)->ebp = savebp; \ + tp->p_ctx.esp = (struct intctx *)esp; \ +} + +/** + * Stack size for the system idle thread. + */ +#ifndef PORT_IDLE_THREAD_STACK_SIZE +#define PORT_IDLE_THREAD_STACK_SIZE 256 +#endif + +/** + * Per-thread stack overhead for interrupts servicing, it is used in the + * calculation of the correct working area size. + * It requires stack space because the simulated "interrupt handlers" can + * invoke host library functions inside so it better have a lot of space. + */ +#ifndef PORT_INT_REQUIRED_STACK +#define PORT_INT_REQUIRED_STACK 16384 +#endif + +/** + * Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + + /** + * Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(void *) * 4 + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * Macro used to allocate a thread working area aligned as both position and + * size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * IRQ prologue code, inserted at the start of all IRQ handlers enabled to + * invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * IRQ epilogue code, inserted at the end of all IRQ handlers enabled to + * invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() + +/** + * IRQ handler function declaration. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * Simulator initialization. + */ +#define port_init() + +/** + * Does nothing in this simulator. + */ +#define port_lock() asm volatile("nop") + +/** + * Does nothing in this simulator. + */ +#define port_unlock() asm volatile("nop") + +/** + * Does nothing in this simulator. + */ +#define port_lock_from_isr() + +/** + * Does nothing in this simulator. + */ +#define port_unlock_from_isr() + +/** + * Does nothing in this simulator. + */ +#define port_disable() + +/** + * Does nothing in this simulator. + */ +#define port_suspend() + +/** + * Does nothing in this simulator. + */ +#define port_enable() + +/** + * In the simulator this does a polling pass on the simulated interrupt + * sources. + */ +#define port_wait_for_interrupt() ChkIntSources() + +#ifdef __cplusplus +extern "C" { +#endif + __attribute__((fastcall)) void port_switch(Thread *ntp, Thread *otp); + __attribute__((fastcall)) void port_halt(void); + __attribute__((cdecl, noreturn)) void _port_thread_start(msg_t (*pf)(void *), + void *p); + void ChkIntSources(void); +#ifdef __cplusplus +} +#endif + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/Project/os/ports/GCC/SIMIA32/chtypes.h b/Project/os/ports/GCC/SIMIA32/chtypes.h new file mode 100644 index 0000000..7e2b301 --- /dev/null +++ b/Project/os/ports/GCC/SIMIA32/chtypes.h @@ -0,0 +1,80 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#define __need_NULL +#define __need_size_t +#define __need_ptrdiff_t +#include + +#if !defined(_STDINT_H) && !defined(__STDINT_H_) +#include +#endif + +typedef int32_t bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint32_t tprio_t; /**< Thread priority. */ +typedef int32_t msg_t; /**< Inter-thread message. */ +typedef int32_t eventid_t; /**< Event Id. */ +typedef uint32_t eventmask_t; /**< Events mask. */ +typedef uint32_t systime_t; /**< System time. */ +typedef int32_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE inline + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note It uses the "packed" GCC attribute. + */ +#define PACK_STRUCT_STRUCT __attribute__((packed)) + +/** + * @brief Packed structure modifier (before). + * @note Empty in this port. + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ diff --git a/Project/os/ports/GCC/SIMIA32/port.mk b/Project/os/ports/GCC/SIMIA32/port.mk new file mode 100644 index 0000000..8f053ab --- /dev/null +++ b/Project/os/ports/GCC/SIMIA32/port.mk @@ -0,0 +1,6 @@ +# List of the ChibiOS/RT SIMIA32 port files. +PORTSRC = ${CHIBIOS}/os/ports/GCC/SIMIA32/chcore.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/GCC/SIMIA32 diff --git a/Project/os/ports/IAR/ARMCMx/LPC11xx/cmparams.h b/Project/os/ports/IAR/ARMCMx/LPC11xx/cmparams.h new file mode 100644 index 0000000..43b5299 --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/LPC11xx/cmparams.h @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file IAR/ARMCMx/LPC11xx/cmparams.h + * @brief ARM Cortex-M0 parameters for the LPC11xx. + * + * @defgroup IAR_ARMCMx_LPC11xx LPC11xx Specific Parameters + * @ingroup IAR_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M0 specific parameters for the + * LPC11xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M0 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 2 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/Project/os/ports/IAR/ARMCMx/LPC11xx/vectors.s b/Project/os/ports/IAR/ARMCMx/LPC11xx/vectors.s new file mode 100644 index 0000000..9b2194e --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/LPC11xx/vectors.s @@ -0,0 +1,194 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + + MODULE ?vectors + + AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE + PRESERVE8 + + SECTION IRQSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA + +__vector_table: + DCD SFE(IRQSTACK) + DCD __iar_program_start + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + +/* + * Default interrupt handlers. + */ + PUBWEAK NMIVector + PUBWEAK HardFaultVector + PUBWEAK MemManageVector + PUBWEAK BusFaultVector + PUBWEAK UsageFaultVector + PUBWEAK Vector1C + PUBWEAK Vector20 + PUBWEAK Vector24 + PUBWEAK Vector28 + PUBWEAK SVCallVector + PUBWEAK DebugMonitorVector + PUBWEAK Vector34 + PUBWEAK PendSVVector + PUBWEAK SysTickVector + PUBWEAK Vector40 + PUBWEAK Vector44 + PUBWEAK Vector48 + PUBWEAK Vector4C + PUBWEAK Vector50 + PUBWEAK Vector54 + PUBWEAK Vector58 + PUBWEAK Vector5C + PUBWEAK Vector60 + PUBWEAK Vector64 + PUBWEAK Vector68 + PUBWEAK Vector6C + PUBWEAK Vector70 + PUBWEAK Vector74 + PUBWEAK Vector78 + PUBWEAK Vector7C + PUBWEAK Vector80 + PUBWEAK Vector84 + PUBWEAK Vector88 + PUBWEAK Vector8C + PUBWEAK Vector90 + PUBWEAK Vector94 + PUBWEAK Vector98 + PUBWEAK Vector9C + PUBWEAK VectorA0 + PUBWEAK VectorA4 + PUBWEAK VectorA8 + PUBWEAK VectorAC + PUBWEAK VectorB0 + PUBWEAK VectorB4 + PUBWEAK VectorB8 + PUBWEAK VectorBC + PUBLIC _unhandled_exception + + SECTION .text:CODE:REORDER(1) + THUMB + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +_unhandled_exception + b _unhandled_exception + + END diff --git a/Project/os/ports/IAR/ARMCMx/LPC13xx/cmparams.h b/Project/os/ports/IAR/ARMCMx/LPC13xx/cmparams.h new file mode 100644 index 0000000..6cfea45 --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/LPC13xx/cmparams.h @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file IAR/ARMCMx/LPC13xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the LPC13xx. + * + * @defgroup IAR_ARMCMx_LPC13xx LPC13xx Specific Parameters + * @ingroup IAR_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * LPC13xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 3 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/Project/os/ports/IAR/ARMCMx/LPC13xx/vectors.s b/Project/os/ports/IAR/ARMCMx/LPC13xx/vectors.s new file mode 100644 index 0000000..1a367f8 --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/LPC13xx/vectors.s @@ -0,0 +1,266 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + + MODULE ?vectors + + AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE + PRESERVE8 + + SECTION IRQSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA + +__vector_table: + DCD SFE(IRQSTACK) + DCD __iar_program_start + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + DCD VectorC0 + DCD VectorC4 + DCD VectorC8 + DCD VectorCC + DCD VectorD0 + DCD VectorD4 + DCD VectorD8 + DCD VectorDC + DCD VectorE0 + DCD VectorE4 + DCD VectorE8 + DCD VectorEC + DCD VectorF0 + DCD VectorF4 + DCD VectorF8 + DCD VectorFC + DCD Vector100 + DCD Vector104 + DCD Vector108 + DCD Vector10C + DCD Vector110 + DCD Vector114 + DCD Vector118 + DCD Vector11C + +/* + * Default interrupt handlers. + */ + PUBWEAK NMIVector + PUBWEAK HardFaultVector + PUBWEAK MemManageVector + PUBWEAK BusFaultVector + PUBWEAK UsageFaultVector + PUBWEAK Vector1C + PUBWEAK Vector20 + PUBWEAK Vector24 + PUBWEAK Vector28 + PUBWEAK SVCallVector + PUBWEAK DebugMonitorVector + PUBWEAK Vector34 + PUBWEAK PendSVVector + PUBWEAK SysTickVector + PUBWEAK Vector40 + PUBWEAK Vector44 + PUBWEAK Vector48 + PUBWEAK Vector4C + PUBWEAK Vector50 + PUBWEAK Vector54 + PUBWEAK Vector58 + PUBWEAK Vector5C + PUBWEAK Vector60 + PUBWEAK Vector64 + PUBWEAK Vector68 + PUBWEAK Vector6C + PUBWEAK Vector70 + PUBWEAK Vector74 + PUBWEAK Vector78 + PUBWEAK Vector7C + PUBWEAK Vector80 + PUBWEAK Vector84 + PUBWEAK Vector88 + PUBWEAK Vector8C + PUBWEAK Vector90 + PUBWEAK Vector94 + PUBWEAK Vector98 + PUBWEAK Vector9C + PUBWEAK VectorA0 + PUBWEAK VectorA4 + PUBWEAK VectorA8 + PUBWEAK VectorAC + PUBWEAK VectorB0 + PUBWEAK VectorB4 + PUBWEAK VectorB8 + PUBWEAK VectorBC + PUBWEAK VectorC0 + PUBWEAK VectorC4 + PUBWEAK VectorC8 + PUBWEAK VectorCC + PUBWEAK VectorD0 + PUBWEAK VectorD4 + PUBWEAK VectorD8 + PUBWEAK VectorDC + PUBWEAK VectorE0 + PUBWEAK VectorE4 + PUBWEAK VectorE8 + PUBWEAK VectorEC + PUBWEAK VectorF0 + PUBWEAK VectorF4 + PUBWEAK VectorF8 + PUBWEAK VectorFC + PUBWEAK Vector100 + PUBWEAK Vector104 + PUBWEAK Vector108 + PUBWEAK Vector10C + PUBWEAK Vector110 + PUBWEAK Vector114 + PUBWEAK Vector118 + PUBWEAK Vector11C + PUBLIC _unhandled_exception + + SECTION .text:CODE:REORDER(1) + THUMB + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +VectorC0 +VectorC4 +VectorC8 +VectorCC +VectorD0 +VectorD4 +VectorD8 +VectorDC +VectorE0 +VectorE4 +VectorE8 +VectorEC +VectorF0 +VectorF4 +VectorF8 +VectorFC +Vector100 +Vector104 +Vector108 +Vector10C +Vector110 +Vector114 +Vector118 +Vector11C +_unhandled_exception + b _unhandled_exception + + END diff --git a/Project/os/ports/IAR/ARMCMx/STM32F1xx/cmparams.h b/Project/os/ports/IAR/ARMCMx/STM32F1xx/cmparams.h new file mode 100644 index 0000000..a2d6a47 --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/STM32F1xx/cmparams.h @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file IAR/ARMCMx/STM32F1xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32F1xx. + * + * @defgroup IAR_ARMCMx_STM32F1xx STM32F1xx Specific Parameters + * @ingroup IAR_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * STM32F1xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/Project/os/ports/IAR/ARMCMx/STM32F1xx/vectors.s b/Project/os/ports/IAR/ARMCMx/STM32F1xx/vectors.s new file mode 100644 index 0000000..7005057 --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/STM32F1xx/vectors.s @@ -0,0 +1,317 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +#if !defined(STM32F10X_LD) && !defined(STM32F10X_LD_VL) && \ + !defined(STM32F10X_MD) && !defined(STM32F10X_MD_VL) && \ + !defined(STM32F10X_HD) && !defined(STM32F10X_XL) && \ + !defined(STM32F10X_CL) +#define _FROM_ASM_ +#include "board.h" +#endif + + MODULE ?vectors + + AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE + PRESERVE8 + + SECTION IRQSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(3) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA + +__vector_table: + DCD SFE(IRQSTACK) + DCD __iar_program_start + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + DCD VectorC0 + DCD VectorC4 + DCD VectorC8 + DCD VectorCC + DCD VectorD0 + DCD VectorD4 + DCD VectorD8 + DCD VectorDC + DCD VectorE0 + DCD VectorE4 + DCD VectorE8 +#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \ + defined(STM32F10X_XL) || defined(STM32F10X_CL) + DCD VectorEC + DCD VectorF0 + DCD VectorF4 +#endif +#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL) + DCD VectorF8 + DCD VectorFC + DCD Vector100 + DCD Vector104 + DCD Vector108 + DCD Vector10C + DCD Vector110 + DCD Vector114 + DCD Vector118 + DCD Vector11C + DCD Vector120 + DCD Vector124 + DCD Vector128 + DCD Vector12C +#endif +#if defined(STM32F10X_CL) + DCD Vector130 + DCD Vector134 + DCD Vector138 + DCD Vector13C + DCD Vector140 + DCD Vector144 + DCD Vector148 + DCD Vector14C +#endif + +/* + * Default interrupt handlers. + */ + PUBWEAK NMIVector + PUBWEAK HardFaultVector + PUBWEAK MemManageVector + PUBWEAK BusFaultVector + PUBWEAK UsageFaultVector + PUBWEAK Vector1C + PUBWEAK Vector20 + PUBWEAK Vector24 + PUBWEAK Vector28 + PUBWEAK SVCallVector + PUBWEAK DebugMonitorVector + PUBWEAK Vector34 + PUBWEAK PendSVVector + PUBWEAK SysTickVector + PUBWEAK Vector40 + PUBWEAK Vector44 + PUBWEAK Vector48 + PUBWEAK Vector4C + PUBWEAK Vector50 + PUBWEAK Vector54 + PUBWEAK Vector58 + PUBWEAK Vector5C + PUBWEAK Vector60 + PUBWEAK Vector64 + PUBWEAK Vector68 + PUBWEAK Vector6C + PUBWEAK Vector70 + PUBWEAK Vector74 + PUBWEAK Vector78 + PUBWEAK Vector7C + PUBWEAK Vector80 + PUBWEAK Vector84 + PUBWEAK Vector88 + PUBWEAK Vector8C + PUBWEAK Vector90 + PUBWEAK Vector94 + PUBWEAK Vector98 + PUBWEAK Vector9C + PUBWEAK VectorA0 + PUBWEAK VectorA4 + PUBWEAK VectorA8 + PUBWEAK VectorAC + PUBWEAK VectorB0 + PUBWEAK VectorB4 + PUBWEAK VectorB8 + PUBWEAK VectorBC + PUBWEAK VectorC0 + PUBWEAK VectorC4 + PUBWEAK VectorC8 + PUBWEAK VectorCC + PUBWEAK VectorD0 + PUBWEAK VectorD4 + PUBWEAK VectorD8 + PUBWEAK VectorDC + PUBWEAK VectorE0 + PUBWEAK VectorE4 + PUBWEAK VectorE8 + PUBWEAK VectorEC + PUBWEAK VectorF0 + PUBWEAK VectorF4 + PUBWEAK VectorF8 + PUBWEAK VectorFC + PUBWEAK Vector100 + PUBWEAK Vector104 + PUBWEAK Vector108 + PUBWEAK Vector10C + PUBWEAK Vector110 + PUBWEAK Vector114 + PUBWEAK Vector118 + PUBWEAK Vector11C + PUBWEAK Vector120 + PUBWEAK Vector124 + PUBWEAK Vector128 + PUBWEAK Vector12C + PUBWEAK Vector130 + PUBWEAK Vector134 + PUBWEAK Vector138 + PUBWEAK Vector13C + PUBWEAK Vector140 + PUBWEAK Vector144 + PUBWEAK Vector148 + PUBWEAK Vector14C + PUBLIC _unhandled_exception + + SECTION .text:CODE:REORDER(1) + THUMB + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +VectorC0 +VectorC4 +VectorC8 +VectorCC +VectorD0 +VectorD4 +VectorD8 +VectorDC +VectorE0 +VectorE4 +VectorE8 +VectorEC +VectorF0 +VectorF4 +VectorF8 +VectorFC +Vector100 +Vector104 +Vector108 +Vector10C +Vector110 +Vector114 +Vector118 +Vector11C +Vector120 +Vector124 +Vector128 +Vector12C +Vector130 +Vector134 +Vector138 +Vector13C +Vector140 +Vector144 +Vector148 +Vector14C +_unhandled_exception + b _unhandled_exception + + END diff --git a/Project/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h b/Project/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h new file mode 100644 index 0000000..605fc7b --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file IAR/ARMCMx/STM32F4xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32F4xx. + * + * @defgroup IAR_ARMCMx_STM32F4xx STM32F4xx Specific Parameters + * @ingroup IAR_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M4 specific parameters for the + * STM32F4xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M4 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU TRUE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/Project/os/ports/IAR/ARMCMx/STM32F4xx/vectors.s b/Project/os/ports/IAR/ARMCMx/STM32F4xx/vectors.s new file mode 100644 index 0000000..44a7f41 --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/STM32F4xx/vectors.s @@ -0,0 +1,344 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + + MODULE ?vectors + + AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE + PRESERVE8 + + SECTION IRQSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(3) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA + +__vector_table: + DCD SFE(IRQSTACK) + DCD __iar_program_start + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + DCD VectorC0 + DCD VectorC4 + DCD VectorC8 + DCD VectorCC + DCD VectorD0 + DCD VectorD4 + DCD VectorD8 + DCD VectorDC + DCD VectorE0 + DCD VectorE4 + DCD VectorE8 + DCD VectorEC + DCD VectorF0 + DCD VectorF4 + DCD VectorF8 + DCD VectorFC + DCD Vector100 + DCD Vector104 + DCD Vector108 + DCD Vector10C + DCD Vector110 + DCD Vector114 + DCD Vector118 + DCD Vector11C + DCD Vector120 + DCD Vector124 + DCD Vector128 + DCD Vector12C + DCD Vector130 + DCD Vector134 + DCD Vector138 + DCD Vector13C + DCD Vector140 + DCD Vector144 + DCD Vector148 + DCD Vector14C + DCD Vector150 + DCD Vector154 + DCD Vector158 + DCD Vector15C + DCD Vector160 + DCD Vector164 + DCD Vector168 + DCD Vector16C + DCD Vector170 + DCD Vector174 + DCD Vector178 + DCD Vector17C + DCD Vector180 + DCD Vector184 + +/* + * Default interrupt handlers. + */ + PUBWEAK NMIVector + PUBWEAK HardFaultVector + PUBWEAK MemManageVector + PUBWEAK BusFaultVector + PUBWEAK UsageFaultVector + PUBWEAK Vector1C + PUBWEAK Vector20 + PUBWEAK Vector24 + PUBWEAK Vector28 + PUBWEAK SVCallVector + PUBWEAK DebugMonitorVector + PUBWEAK Vector34 + PUBWEAK PendSVVector + PUBWEAK SysTickVector + PUBWEAK Vector40 + PUBWEAK Vector44 + PUBWEAK Vector48 + PUBWEAK Vector4C + PUBWEAK Vector50 + PUBWEAK Vector54 + PUBWEAK Vector58 + PUBWEAK Vector5C + PUBWEAK Vector60 + PUBWEAK Vector64 + PUBWEAK Vector68 + PUBWEAK Vector6C + PUBWEAK Vector70 + PUBWEAK Vector74 + PUBWEAK Vector78 + PUBWEAK Vector7C + PUBWEAK Vector80 + PUBWEAK Vector84 + PUBWEAK Vector88 + PUBWEAK Vector8C + PUBWEAK Vector90 + PUBWEAK Vector94 + PUBWEAK Vector98 + PUBWEAK Vector9C + PUBWEAK VectorA0 + PUBWEAK VectorA4 + PUBWEAK VectorA8 + PUBWEAK VectorAC + PUBWEAK VectorB0 + PUBWEAK VectorB4 + PUBWEAK VectorB8 + PUBWEAK VectorBC + PUBWEAK VectorC0 + PUBWEAK VectorC4 + PUBWEAK VectorC8 + PUBWEAK VectorCC + PUBWEAK VectorD0 + PUBWEAK VectorD4 + PUBWEAK VectorD8 + PUBWEAK VectorDC + PUBWEAK VectorE0 + PUBWEAK VectorE4 + PUBWEAK VectorE8 + PUBWEAK VectorEC + PUBWEAK VectorF0 + PUBWEAK VectorF4 + PUBWEAK VectorF8 + PUBWEAK VectorFC + PUBWEAK Vector100 + PUBWEAK Vector104 + PUBWEAK Vector108 + PUBWEAK Vector10C + PUBWEAK Vector110 + PUBWEAK Vector114 + PUBWEAK Vector118 + PUBWEAK Vector11C + PUBWEAK Vector120 + PUBWEAK Vector124 + PUBWEAK Vector128 + PUBWEAK Vector12C + PUBWEAK Vector130 + PUBWEAK Vector134 + PUBWEAK Vector138 + PUBWEAK Vector13C + PUBWEAK Vector140 + PUBWEAK Vector144 + PUBWEAK Vector148 + PUBWEAK Vector14C + PUBWEAK Vector150 + PUBWEAK Vector154 + PUBWEAK Vector158 + PUBWEAK Vector15C + PUBWEAK Vector160 + PUBWEAK Vector164 + PUBWEAK Vector168 + PUBWEAK Vector16C + PUBWEAK Vector170 + PUBWEAK Vector174 + PUBWEAK Vector178 + PUBWEAK Vector17C + PUBWEAK Vector180 + PUBWEAK Vector184 + PUBLIC _unhandled_exception + + SECTION .text:CODE:REORDER(1) + THUMB + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +VectorC0 +VectorC4 +VectorC8 +VectorCC +VectorD0 +VectorD4 +VectorD8 +VectorDC +VectorE0 +VectorE4 +VectorE8 +VectorEC +VectorF0 +VectorF4 +VectorF8 +VectorFC +Vector100 +Vector104 +Vector108 +Vector10C +Vector110 +Vector114 +Vector118 +Vector11C +Vector120 +Vector124 +Vector128 +Vector12C +Vector130 +Vector134 +Vector138 +Vector13C +Vector140 +Vector144 +Vector148 +Vector14C +Vector150 +Vector154 +Vector158 +Vector15C +Vector160 +Vector164 +Vector168 +Vector16C +Vector170 +Vector174 +Vector178 +Vector17C +Vector180 +Vector184 +_unhandled_exception + b _unhandled_exception + + END diff --git a/Project/os/ports/IAR/ARMCMx/STM32L1xx/cmparams.h b/Project/os/ports/IAR/ARMCMx/STM32L1xx/cmparams.h new file mode 100644 index 0000000..4882669 --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/STM32L1xx/cmparams.h @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file IAR/ARMCMx/STM32L1xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32L1xx. + * + * @defgroup IAR_ARMCMx_STM32L1xx STM32L1xx Specific Parameters + * @ingroup IAR_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * STM32L1xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/Project/os/ports/IAR/ARMCMx/STM32L1xx/vectors.s b/Project/os/ports/IAR/ARMCMx/STM32L1xx/vectors.s new file mode 100644 index 0000000..e6cb71a --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/STM32L1xx/vectors.s @@ -0,0 +1,238 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +#if !defined(STM32L1XX_MD) +#define _FROM_ASM_ +#include "board.h" +#endif + + MODULE ?vectors + + AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE + PRESERVE8 + + SECTION IRQSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(3) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA + +__vector_table: + DCD SFE(IRQSTACK) + DCD __iar_program_start + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + DCD VectorC0 + DCD VectorC4 + DCD VectorC8 + DCD VectorCC + DCD VectorD0 + DCD VectorD4 + DCD VectorD8 + DCD VectorDC + DCD VectorE0 + DCD VectorE4 + DCD VectorE8 + DCD VectorEC + DCD VectorF0 + +/* + * Default interrupt handlers. + */ + PUBWEAK NMIVector + PUBWEAK HardFaultVector + PUBWEAK MemManageVector + PUBWEAK BusFaultVector + PUBWEAK UsageFaultVector + PUBWEAK Vector1C + PUBWEAK Vector20 + PUBWEAK Vector24 + PUBWEAK Vector28 + PUBWEAK SVCallVector + PUBWEAK DebugMonitorVector + PUBWEAK Vector34 + PUBWEAK PendSVVector + PUBWEAK SysTickVector + PUBWEAK Vector40 + PUBWEAK Vector44 + PUBWEAK Vector48 + PUBWEAK Vector4C + PUBWEAK Vector50 + PUBWEAK Vector54 + PUBWEAK Vector58 + PUBWEAK Vector5C + PUBWEAK Vector60 + PUBWEAK Vector64 + PUBWEAK Vector68 + PUBWEAK Vector6C + PUBWEAK Vector70 + PUBWEAK Vector74 + PUBWEAK Vector78 + PUBWEAK Vector7C + PUBWEAK Vector80 + PUBWEAK Vector84 + PUBWEAK Vector88 + PUBWEAK Vector8C + PUBWEAK Vector90 + PUBWEAK Vector94 + PUBWEAK Vector98 + PUBWEAK Vector9C + PUBWEAK VectorA0 + PUBWEAK VectorA4 + PUBWEAK VectorA8 + PUBWEAK VectorAC + PUBWEAK VectorB0 + PUBWEAK VectorB4 + PUBWEAK VectorB8 + PUBWEAK VectorBC + PUBWEAK VectorC0 + PUBWEAK VectorC4 + PUBWEAK VectorC8 + PUBWEAK VectorCC + PUBWEAK VectorD0 + PUBWEAK VectorD4 + PUBWEAK VectorD8 + PUBWEAK VectorDC + PUBWEAK VectorE0 + PUBWEAK VectorE4 + PUBWEAK VectorE8 + PUBWEAK VectorEC + PUBWEAK VectorF0 + PUBLIC _unhandled_exception + + SECTION .text:CODE:REORDER(1) + THUMB + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +VectorC0 +VectorC4 +VectorC8 +VectorCC +VectorD0 +VectorD4 +VectorD8 +VectorDC +VectorE0 +VectorE4 +VectorE8 +VectorEC +VectorF0 +_unhandled_exception + b _unhandled_exception + + END diff --git a/Project/os/ports/IAR/ARMCMx/chcore.c b/Project/os/ports/IAR/ARMCMx/chcore.c new file mode 100644 index 0000000..654c67e --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/chcore.c @@ -0,0 +1,53 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file IAR/ARMCMx/chcore.c + * @brief ARM Cortex-Mx port code. + * + * @addtogroup IAR_ARMCMx_CORE + * @{ + */ + +#include "ch.h" + +/** + * @brief Halts the system. + * @note The function is declared as a weak symbol, it is possible + * to redefine it in your application code. + */ +#if !defined(__DOXYGEN__) +__weak +#endif +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** @} */ diff --git a/Project/os/ports/IAR/ARMCMx/chcore.h b/Project/os/ports/IAR/ARMCMx/chcore.h new file mode 100644 index 0000000..e9f72b1 --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/chcore.h @@ -0,0 +1,190 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file IAR/ARMCMx/chcore.h + * @brief ARM Cortex-Mx port macros and structures. + * + * @addtogroup IAR_ARMCMx_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +/*===========================================================================*/ +/* Port constants (common). */ +/*===========================================================================*/ + +/* Added to make the header stand-alone when included from asm.*/ +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE (!FALSE) +#endif + +#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */ +#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */ +#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */ +#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */ + +/* Inclusion of the Cortex-Mx implementation specific parameters.*/ +#include "cmparams.h" + +/* Cortex model check, only M0 and M3 supported right now.*/ +#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) || \ + (CORTEX_MODEL == CORTEX_M4) +#elif (CORTEX_MODEL == CORTEX_M1) +#error "untested Cortex-M model" +#else +#error "unknown or unsupported Cortex-M model" +#endif + +/** + * @brief Total priority levels. + */ +#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS) + +/** + * @brief Minimum priority level. + * @details This minimum priority level is calculated from the number of + * priority bits supported by the specific Cortex-Mx implementation. + */ +#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1) + +/** + * @brief Maximum priority level. + * @details The maximum allowed priority level is always zero. + */ +#define CORTEX_MAXIMUM_PRIORITY 0 + +/*===========================================================================*/ +/* Port macros (common). */ +/*===========================================================================*/ + +/** + * @brief Priority level verification macro. + */ +#define CORTEX_IS_VALID_PRIORITY(n) \ + (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS)) + +/** + * @brief Priority level to priority mask conversion macro. + */ +#define CORTEX_PRIORITY_MASK(n) \ + ((n) << (8 - CORTEX_PRIORITY_BITS)) + +/*===========================================================================*/ +/* Port configurable parameters (common). */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port derived parameters (common). */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port exported info (common). */ +/*===========================================================================*/ + +/** + * @brief Macro defining a generic ARM architecture. + */ +#define CH_ARCHITECTURE_ARM + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "IAR" + +/*===========================================================================*/ +/* Port implementation part (common). */ +/*===========================================================================*/ + +/* Includes the sub-architecture-specific part.*/ +#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1) +#include "chcore_v6m.h" +#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4) +#include "chcore_v7m.h" +#endif + +#if !defined(_FROM_ASM_) + +#include +#include "nvic.h" + +/* The following declarations are there just for Doxygen documentation, the + real declarations are inside the sub-headers.*/ +#if defined(__DOXYGEN__) + +/** + * @brief Stack and memory alignment enforcement. + * @note In this architecture the stack alignment is enforced to 64 bits, + * 32 bits alignment is supported by hardware but deprecated by ARM, + * the implementation choice is to not offer the option. + */ +typedef uint64_t stkalign_t; + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + * @note It is implemented to match the Cortex-Mx exception context. + */ +struct extctx {}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching. + */ +struct intctx {}; + +#endif /* defined(__DOXYGEN__) */ + +/** + * @brief Excludes the default @p chSchIsPreemptionRequired()implementation. + */ +#define PORT_OPTIMIZED_ISPREEMPTIONREQUIRED + +#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__) +/** + * @brief Inline-able version of this kernel function. + */ +#define chSchIsPreemptionRequired() \ + (rlist.r_preempt ? firstprio(&rlist.r_queue) > currp->p_prio : \ + firstprio(&rlist.r_queue) >= currp->p_prio) +#else /* CH_TIME_QUANTUM == 0 */ +#define chSchIsPreemptionRequired() \ + (firstprio(&rlist.r_queue) > currp->p_prio) +#endif /* CH_TIME_QUANTUM == 0 */ + +#endif /* _FROM_ASM_ */ + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/Project/os/ports/IAR/ARMCMx/chcore_v6m.c b/Project/os/ports/IAR/ARMCMx/chcore_v6m.c new file mode 100644 index 0000000..fe492d4 --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/chcore_v6m.c @@ -0,0 +1,132 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file IAR/ARMCMx/chcore_v6m.c + * @brief ARMv6-M architecture port code. + * + * @addtogroup IAR_ARMCMx_V6M_CORE + * @{ + */ + +#include "ch.h" + +/*===========================================================================*/ +/* Port interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief System Timer vector. + * @details This interrupt is used as system tick. + * @note The timer must be initialized in the startup code. + */ +CH_IRQ_HANDLER(SysTickVector) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +/** + * @brief NMI vector. + * @details The NMI vector is used for exception mode re-entering after a + * context switch. + */ +void NMIVector(void) { + register struct extctx *ctxp; + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp = (struct extctx *)__get_PSP(); + ctxp++; + __set_PSP((unsigned long)ctxp); + port_unlock_from_isr(); +} +#endif /* !CORTEX_ALTERNATE_SWITCH */ + +#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +/** + * @brief PendSV vector. + * @details The PendSV vector is used for exception mode re-entering after a + * context switch. + */ +void PendSVVector(void) { + register struct extctx *ctxp; + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp = (struct extctx *)__get_PSP(); + ctxp++; + __set_PSP((unsigned long)ctxp); +} +#endif /* CORTEX_ALTERNATE_SWITCH */ + +/*===========================================================================*/ +/* Port exported functions. */ +/*===========================================================================*/ + +/** + * @brief IRQ epilogue code. + * + * @param[in] lr value of the @p LR register on ISR entry + */ +void _port_irq_epilogue(regarm_t lr) { + + if (lr != (regarm_t)0xFFFFFFF1) { + register struct extctx *ctxp; + + port_lock_from_isr(); + /* Adding an artificial exception return context, there is no need to + populate it fully.*/ + ctxp = (struct extctx *)__get_PSP(); + ctxp--; + __set_PSP((unsigned long)ctxp); + ctxp->xpsr = (regarm_t)0x01000000; + + /* The exit sequence is different depending on if a preemption is + required or not.*/ + if (chSchIsPreemptionRequired()) { + /* Preemption is required we need to enforce a context switch.*/ + ctxp->pc = (regarm_t)_port_switch_from_isr; + } + else { + /* Preemption not required, we just need to exit the exception + atomically.*/ + ctxp->pc = (regarm_t)_port_exit_from_isr; + } + + /* Note, returning without unlocking is intentional, this is done in + order to keep the rest of the context switching atomic.*/ + } +} + +/** @} */ diff --git a/Project/os/ports/IAR/ARMCMx/chcore_v6m.h b/Project/os/ports/IAR/ARMCMx/chcore_v6m.h new file mode 100644 index 0000000..feaaa81 --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/chcore_v6m.h @@ -0,0 +1,379 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file IAR/ARMCMx/chcore_v6m.h + * @brief ARMv6-M architecture port macros and structures. + * + * @addtogroup IAR_ARMCMx_V6M_CORE + * @{ + */ + +#ifndef _CHCORE_V6M_H_ +#define _CHCORE_V6M_H_ + +/*===========================================================================*/ +/* Port constants. */ +/*===========================================================================*/ + +/** + * @brief PendSV priority level. + * @note This priority is enforced to be equal to @p 0, + * this handler always has the highest priority that cannot preempt + * the kernel. + */ +#define CORTEX_PRIORITY_PENDSV 0 + +/*===========================================================================*/ +/* Port macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + * @note In this port it is set to 16 because the idle thread does have + * a stack frame when compiling without optimizations. You may + * reduce this value to zero when compiling with optimizations. + */ +#if !defined(PORT_IDLE_THREAD_STACK_SIZE) +#define PORT_IDLE_THREAD_STACK_SIZE 16 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * This value can be zero on those architecture where there is a + * separate interrupt stack and the stack space between @p intctx and + * @p extctx is known to be zero. + * @note In this port it is conservatively set to 32 because the function + * @p chSchDoReschedule() can have a stack frame, especially with + * compiler optimizations disabled. + */ +#if !defined(PORT_INT_REQUIRED_STACK) +#define PORT_INT_REQUIRED_STACK 32 +#endif + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#if !defined(CORTEX_ENABLE_WFI_IDLE) +#define CORTEX_ENABLE_WFI_IDLE FALSE +#endif + +/** + * @brief SYSTICK handler priority. + * @note The default SYSTICK handler priority is calculated as the priority + * level in the middle of the numeric priorities range. + */ +#if !defined(CORTEX_PRIORITY_SYSTICK) +#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) +#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) +/* If it is externally redefined then better perform a validity check on it.*/ +#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" +#endif + +/** + * @brief Alternate preemption method. + * @details Activating this option will make the Kernel use the PendSV + * handler for preemption instead of the NMI handler. + */ +#ifndef CORTEX_ALTERNATE_SWITCH +#define CORTEX_ALTERNATE_SWITCH FALSE +#endif + +/*===========================================================================*/ +/* Port derived parameters. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +/** + * @brief Macro defining the specific ARM architecture. + */ +#define CH_ARCHITECTURE_ARM_v6M + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "ARMv6-M" + +/** + * @brief Name of the architecture variant. + */ +#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__) +#define CH_CORE_VARIANT_NAME "Cortex-M0" +#elif (CORTEX_MODEL == CORTEX_M1) +#define CH_CORE_VARIANT_NAME "Cortex-M1" +#endif + +/** + * @brief Port-specific information string. + */ +#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +#define CH_PORT_INFO "Preemption through NMI" +#else +#define CH_PORT_INFO "Preemption through PendSV" +#endif + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) + +/** + * @brief Generic ARM register. + */ +typedef void *regarm_t; + +/** + * @brief Stack and memory alignment enforcement. + * @note In this architecture the stack alignment is enforced to 64 bits, + * 32 bits alignment is supported by hardware but deprecated by ARM, + * the implementation choice is to not offer the option. + */ +typedef uint64_t stkalign_t; + + /* The documentation of the following declarations is in chconf.h in order + to not have duplicated structure names into the documentation.*/ +#if !defined(__DOXYGEN__) + +struct extctx { + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t r12; + regarm_t lr_thd; + regarm_t pc; + regarm_t xpsr; +}; + +struct intctx { + regarm_t r8; + regarm_t r9; + regarm_t r10; + regarm_t r11; + regarm_t r4; + regarm_t r5; + regarm_t r6; + regarm_t r7; + regarm_t lr; +}; + +#endif /* !defined(__DOXYGEN__) */ + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details In this port the structure just holds a pointer to the @p intctx + * structure representing the stack pointer at context switch time. + */ +struct context { + struct intctx *r13; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->r4 = (regarm_t)pf; \ + tp->p_ctx.r13->r5 = (regarm_t)arg; \ + tp->p_ctx.r13->lr = (regarm_t)_port_thread_start; \ +} + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() regarm_t _saved_lr = (regarm_t)__get_LR() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr) + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_FAST_IRQ_HANDLER(id) void id(void) + +/** + * @brief Port-related initialization code. + */ +#define port_init() { \ + SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ + nvicSetSystemHandlerPriority(HANDLER_PENDSV, \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ +} + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform + * more actions. + */ +#define port_lock() __disable_interrupt() + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform + * more actions. + */ +#define port_unlock() __enable_interrupt() + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_lock_from_isr() port_lock() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_unlock_from_isr() port_unlock() + +/** + * @brief Disables all the interrupt sources. + */ +#define port_disable() __disable_interrupt() + +/** + * @brief Disables the interrupt sources below kernel-level priority. + */ +#define port_suspend() __disable_interrupt() + +/** + * @brief Enables all the interrupt sources. + */ +#define port_enable() __enable_interrupt() + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note Implemented as an inlined @p WFI instruction. + */ +#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() asm ("wfi") +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) +#define port_switch(ntp, otp) _port_switch(ntp, otp) +#else +#define port_switch(ntp, otp) { \ + if ((stkalign_t *)(__get_SP() - sizeof(struct intctx)) < otp->p_stklimit) \ + chDbgPanic("stack overflow"); \ + _port_switch(ntp, otp); \ +} +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void port_halt(void); + void _port_irq_epilogue(regarm_t lr); + void _port_switch_from_isr(void); + void _port_exit_from_isr(void); + void _port_switch(Thread *ntp, Thread *otp); + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _FROM_ASM_ */ + +#endif /* _CHCORE_V6M_H_ */ + +/** @} */ diff --git a/Project/os/ports/IAR/ARMCMx/chcore_v7m.c b/Project/os/ports/IAR/ARMCMx/chcore_v7m.c new file mode 100644 index 0000000..88a889b --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/chcore_v7m.c @@ -0,0 +1,205 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file IAR/ARMCMx/chcore_v7m.c + * @brief ARMv7-M architecture port code. + * + * @addtogroup IAR_ARMCMx_V7M_CORE + * @{ + */ + +#include "ch.h" + +/*===========================================================================*/ +/* Port interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief System Timer vector. + * @details This interrupt is used as system tick. + * @note The timer must be initialized in the startup code. + */ +CH_IRQ_HANDLER(SysTickVector) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +/** + * @brief SVC vector. + * @details The SVC vector is used for exception mode re-entering after a + * context switch. + * @note The PendSV vector is only used in advanced kernel mode. + */ +void SVCallVector(void) { + struct extctx *ctxp; + + /* Current PSP value.*/ + ctxp = (struct extctx *)__get_PSP(); + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp++; + +#if CORTEX_USE_FPU + /* Restoring the special register SCB_FPCCR.*/ + SCB_FPCCR = (uint32_t)ctxp->fpccr; + SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx); +#endif + __set_PSP((unsigned long)ctxp); + port_unlock_from_isr(); +} +#endif /* !CORTEX_SIMPLIFIED_PRIORITY */ + +#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +/** + * @brief PendSV vector. + * @details The PendSV vector is used for exception mode re-entering after a + * context switch. + * @note The PendSV vector is only used in compact kernel mode. + */ +void PendSVVector(void) { + struct extctx *ctxp; + + /* Current PSP value.*/ + ctxp = (struct extctx *)__get_PSP(); + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp++; + +#if CORTEX_USE_FPU + /* Restoring the special register SCB_FPCCR.*/ + SCB_FPCCR = (uint32_t)ctxp->fpccr; + SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx); +#endif + __set_PSP((unsigned long)ctxp); +} +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/*===========================================================================*/ +/* Port exported functions. */ +/*===========================================================================*/ + +/** + * @brief Port-related initialization code. + */ +void _port_init(void) { + + /* Initialization of the vector table and priority related settings.*/ + SCB_VTOR = CORTEX_VTOR_INIT; + SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); + +#if CORTEX_USE_FPU + { + /* Initializing the FPU context save in lazy mode.*/ + SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN; + + /* CP10 and CP11 set to full access.*/ + SCB_CPACR |= 0x00F00000; + + /* Enables FPU context save/restore on exception entry/exit (FPCA bit).*/ + __set_CONTROL(__get_CONTROL() | 4); + + /* FPSCR and FPDSCR initially zero.*/ + __set_FPSCR(0); + SCB_FPDSCR = 0; + } +#endif + + /* Initialization of the system vectors used by the port.*/ + nvicSetSystemHandlerPriority(HANDLER_SVCALL, + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); + nvicSetSystemHandlerPriority(HANDLER_PENDSV, + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); +} + +/** + * @brief Exception exit redirection to _port_switch_from_isr(). + */ +void _port_irq_epilogue(void) { + + port_lock_from_isr(); + if ((SCB_ICSR & ICSR_RETTOBASE) != 0) { + struct extctx *ctxp; + + /* Current PSP value.*/ + ctxp = (struct extctx *)__get_PSP(); + + /* Adding an artificial exception return context, there is no need to + populate it fully.*/ + ctxp--; + __set_PSP((unsigned long)ctxp); + ctxp->xpsr = (regarm_t)0x01000000; + + /* The exit sequence is different depending on if a preemption is + required or not.*/ + if (chSchIsPreemptionRequired()) { + /* Preemption is required we need to enforce a context switch.*/ + ctxp->pc = (regarm_t)_port_switch_from_isr; +#if CORTEX_USE_FPU + /* Triggering a lazy FPU state save.*/ + (void)__get_FPSCR(); +#endif + } + else { + /* Preemption not required, we just need to exit the exception + atomically.*/ + ctxp->pc = (regarm_t)_port_exit_from_isr; + } + +#if CORTEX_USE_FPU + { + uint32_t fpccr; + + /* Saving the special register SCB_FPCCR into the reserved offset of + the Cortex-M4 exception frame.*/ + (ctxp + 1)->fpccr = (regarm_t)(fpccr = SCB_FPCCR); + + /* Now the FPCCR is modified in order to not restore the FPU status + from the artificial return context.*/ + SCB_FPCCR = fpccr | FPCCR_LSPACT; + } +#endif + + /* Note, returning without unlocking is intentional, this is done in + order to keep the rest of the context switching atomic.*/ + return; + } + port_unlock_from_isr(); +} + +/** @} */ diff --git a/Project/os/ports/IAR/ARMCMx/chcore_v7m.h b/Project/os/ports/IAR/ARMCMx/chcore_v7m.h new file mode 100644 index 0000000..538ff3d --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/chcore_v7m.h @@ -0,0 +1,497 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file IAR/ARMCMx/chcore_v7m.h + * @brief ARMv7-M architecture port macros and structures. + * + * @addtogroup IAR_ARMCMx_V7M_CORE + * @{ + */ + +#ifndef _CHCORE_V7M_H_ +#define _CHCORE_V7M_H_ + +/*===========================================================================*/ +/* Port constants. */ +/*===========================================================================*/ + +/** + * @brief Disabled value for BASEPRI register. + */ +#define CORTEX_BASEPRI_DISABLED 0 + +/*===========================================================================*/ +/* Port macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + * @note In this port it is set to 16 because the idle thread does have + * a stack frame when compiling without optimizations. You may + * reduce this value to zero when compiling with optimizations. + */ +#if !defined(PORT_IDLE_THREAD_STACK_SIZE) +#define PORT_IDLE_THREAD_STACK_SIZE 16 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * This value can be zero on those architecture where there is a + * separate interrupt stack and the stack space between @p intctx and + * @p extctx is known to be zero. + * @note In this port it is conservatively set to 32 because the function + * @p chSchDoReschedule() can have a stack frame, especially with + * compiler optimizations disabled. + */ +#if !defined(PORT_INT_REQUIRED_STACK) +#define PORT_INT_REQUIRED_STACK 32 +#endif + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#if !defined(CORTEX_ENABLE_WFI_IDLE) +#define CORTEX_ENABLE_WFI_IDLE FALSE +#endif + +/** + * @brief SYSTICK handler priority. + * @note The default SYSTICK handler priority is calculated as the priority + * level in the middle of the numeric priorities range. + */ +#if !defined(CORTEX_PRIORITY_SYSTICK) +#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) +#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) +/* If it is externally redefined then better perform a validity check on it.*/ +#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" +#endif + +/** + * @brief FPU support in context switch. + * @details Activating this option activates the FPU support in the kernel. + */ +#if !defined(CORTEX_USE_FPU) +#define CORTEX_USE_FPU CORTEX_HAS_FPU +#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU +/* This setting requires an FPU presence check in case it is externally + redefined.*/ +#error "the selected core does not have an FPU" +#endif + +/** + * @brief Simplified priority handling flag. + * @details Activating this option makes the Kernel work in compact mode. + */ +#if !defined(CORTEX_SIMPLIFIED_PRIORITY) +#define CORTEX_SIMPLIFIED_PRIORITY FALSE +#endif + +/** + * @brief SVCALL handler priority. + * @note The default SVCALL handler priority is defaulted to + * @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the + * @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts + * priority level. + */ +#if !defined(CORTEX_PRIORITY_SVCALL) +#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1) +#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL) +/* If it is externally redefined then better perform a validity check on it.*/ +#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL" +#endif + +/** + * @brief NVIC VTOR initialization expression. + */ +#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__) +#define CORTEX_VTOR_INIT 0x00000000 +#endif + +/*===========================================================================*/ +/* Port derived parameters. */ +/*===========================================================================*/ + +/** + * @brief BASEPRI level within kernel lock. + * @note In compact kernel mode this constant value is enforced to zero. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define CORTEX_BASEPRI_KERNEL \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1) +#else +#define CORTEX_BASEPRI_KERNEL 0 +#endif + +/** + * @brief PendSV priority level. + * @note This priority is enforced to be equal to @p CORTEX_BASEPRI_KERNEL, + * this handler always have the highest priority that cannot preempt + * the kernel. + */ +#define CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__) +/** + * @brief Macro defining the specific ARM architecture. + */ +#define CH_ARCHITECTURE_ARM_v7M + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "ARMv7-M" + +/** + * @brief Name of the architecture variant. + */ +#define CH_CORE_VARIANT_NAME "Cortex-M3" + +#elif (CORTEX_MODEL == CORTEX_M4) +#define CH_ARCHITECTURE_ARM_v7ME +#define CH_ARCHITECTURE_NAME "ARMv7-ME" +#if CORTEX_USE_FPU +#define CH_CORE_VARIANT_NAME "Cortex-M4F" +#else +#define CH_CORE_VARIANT_NAME "Cortex-M4" +#endif +#endif + +/** + * @brief Port-specific information string. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define CH_PORT_INFO "Advanced kernel mode" +#else +#define CH_PORT_INFO "Compact kernel mode" +#endif + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) + +/** + * @brief Generic ARM register. + */ +typedef void *regarm_t; + +/** + * @brief Stack and memory alignment enforcement. + * @note In this architecture the stack alignment is enforced to 64 bits, + * 32 bits alignment is supported by hardware but deprecated by ARM, + * the implementation choice is to not offer the option. + */ +typedef uint64_t stkalign_t; + +/* The documentation of the following declarations is in chconf.h in order + to not have duplicated structure names into the documentation.*/ +#if !defined(__DOXYGEN__) + +struct extctx { + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t r12; + regarm_t lr_thd; + regarm_t pc; + regarm_t xpsr; +#if CORTEX_USE_FPU + regarm_t s0; + regarm_t s1; + regarm_t s2; + regarm_t s3; + regarm_t s4; + regarm_t s5; + regarm_t s6; + regarm_t s7; + regarm_t s8; + regarm_t s9; + regarm_t s10; + regarm_t s11; + regarm_t s12; + regarm_t s13; + regarm_t s14; + regarm_t s15; + regarm_t fpscr; + regarm_t fpccr; +#endif /* CORTEX_USE_FPU */ +}; + +struct intctx { +#if CORTEX_USE_FPU + regarm_t s16; + regarm_t s17; + regarm_t s18; + regarm_t s19; + regarm_t s20; + regarm_t s21; + regarm_t s22; + regarm_t s23; + regarm_t s24; + regarm_t s25; + regarm_t s26; + regarm_t s27; + regarm_t s28; + regarm_t s29; + regarm_t s30; + regarm_t s31; +#endif /* CORTEX_USE_FPU */ + regarm_t r4; + regarm_t r5; + regarm_t r6; + regarm_t r7; + regarm_t r8; + regarm_t r9; + regarm_t r10; + regarm_t r11; + regarm_t lr; +}; + +#endif /* !defined(__DOXYGEN__) */ + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details In this port the structure just holds a pointer to the @p intctx + * structure representing the stack pointer at context switch time. + */ +struct context { + struct intctx *r13; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->r4 = (regarm_t)pf; \ + tp->p_ctx.r13->r5 = (regarm_t)arg; \ + tp->p_ctx.r13->lr = (regarm_t)_port_thread_start; \ +} + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() _port_irq_epilogue() + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_FAST_IRQ_HANDLER(id) void id(void) + +/** + * @brief Port-related initialization code. + */ +#define port_init() _port_init() + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform + * more actions. + * @note In this port this it raises the base priority to kernel level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define port_lock() __set_BASEPRI(CORTEX_BASEPRI_KERNEL) +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_lock() __disable_interrupt() +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform + * more actions. + * @note In this port this it lowers the base priority to user level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define port_unlock() __set_BASEPRI(CORTEX_BASEPRI_DISABLED) +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_unlock() __enable_interrupt() +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_lock_from_isr() port_lock() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + * @note Same as @p port_unlock() in this port. + */ +#define port_unlock_from_isr() port_unlock() + +/** + * @brief Disables all the interrupt sources. + * @note Of course non-maskable interrupt sources are not included. + * @note In this port it disables all the interrupt sources by raising + * the priority mask to level 0. + */ +#define port_disable() __disable_interrupt() + +/** + * @brief Disables the interrupt sources below kernel-level priority. + * @note Interrupt sources above kernel level remains enabled. + * @note In this port it raises/lowers the base priority to kernel level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define port_suspend() { \ + __set_BASEPRI(CORTEX_BASEPRI_KERNEL); \ + __enable_interrupt(); \ +} +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_suspend() __disable_interrupt() +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Enables all the interrupt sources. + * @note In this port it lowers the base priority to user level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define port_enable() { \ + __set_BASEPRI(CORTEX_BASEPRI_DISABLED); \ + __enable_interrupt(); \ +} +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_enable() __enable_interrupt() +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note Implemented as an inlined @p WFI instruction. + */ +#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() asm ("wfi") +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) +#define port_switch(ntp, otp) _port_switch(ntp, otp) +#else +#define port_switch(ntp, otp) { \ + if ((stkalign_t *)(__get_SP() - sizeof(struct intctx)) < otp->p_stklimit) \ + chDbgPanic("stack overflow"); \ + _port_switch(ntp, otp); \ +} +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void port_halt(void); + void _port_init(void); + void _port_irq_epilogue(void); + void _port_switch_from_isr(void); + void _port_exit_from_isr(void); + void _port_switch(Thread *ntp, Thread *otp); + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _FROM_ASM_ */ + +#endif /* _CHCORE_V7M_H_ */ + +/** @} */ diff --git a/Project/os/ports/IAR/ARMCMx/chcoreasm_v6m.s b/Project/os/ports/IAR/ARMCMx/chcoreasm_v6m.s new file mode 100644 index 0000000..525c058 --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/chcoreasm_v6m.s @@ -0,0 +1,118 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + + MODULE ?chcoreasm_v6m + + AAPCS INTERWORK, VFP_COMPATIBLE + PRESERVE8 + +/* + * Imports the Cortex-Mx configuration headers. + */ +#define _FROM_ASM_ +#include "chconf.h" +#include "chcore.h" + +CONTEXT_OFFSET SET 12 +SCB_ICSR SET 0xE000ED04 + + SECTION .text:CODE:NOROOT(2) + + EXTERN chThdExit + EXTERN chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + EXTERN dbg_check_unlock + EXTERN dbg_check_lock +#endif + + THUMB + +/* + * Performs a context switch between two threads. + */ + PUBLIC _port_switch +_port_switch: + push {r4, r5, r6, r7, lr} + mov r4, r8 + mov r5, r9 + mov r6, r10 + mov r7, r11 + push {r4, r5, r6, r7} + mov r3, sp + str r3, [r1, #CONTEXT_OFFSET] + ldr r3, [r0, #CONTEXT_OFFSET] + mov sp, r3 + pop {r4, r5, r6, r7} + mov r8, r4 + mov r9, r5 + mov r10, r6 + mov r11, r7 + pop {r4, r5, r6, r7, pc} + +/* + * Start a thread by invoking its work function. + * If the work function returns @p chThdExit() is automatically invoked. + */ + PUBLIC _port_thread_start +_port_thread_start: +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif + cpsie i + mov r0, r5 + blx r4 + bl chThdExit + +/* + * Post-IRQ switch code. + * Exception handlers return here for context switching. + */ + PUBLIC _port_switch_from_isr + PUBLIC _port_exit_from_isr +_port_switch_from_isr: +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif +_port_exit_from_isr: + ldr r2, =SCB_ICSR + movs r3, #128 +#if CORTEX_ALTERNATE_SWITCH + lsls r3, r3, #21 + str r3, [r2, #0] + cpsie i +#else + lsls r3, r3, #24 + str r3, [r2, #0] +#endif +waithere: + b waithere + + END diff --git a/Project/os/ports/IAR/ARMCMx/chcoreasm_v7m.s b/Project/os/ports/IAR/ARMCMx/chcoreasm_v7m.s new file mode 100644 index 0000000..61450ab --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/chcoreasm_v7m.s @@ -0,0 +1,116 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + + MODULE ?chcoreasm_v7m + + AAPCS INTERWORK, VFP_COMPATIBLE + PRESERVE8 + +/* + * Imports the Cortex-Mx configuration headers. + */ +#define _FROM_ASM_ +#include "chconf.h" +#include "chcore.h" + +CONTEXT_OFFSET SET 12 +SCB_ICSR SET 0xE000ED04 +ICSR_PENDSVSET SET 0x10000000 + + SECTION .text:CODE:NOROOT(2) + + EXTERN chThdExit + EXTERN chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + EXTERN dbg_check_unlock + EXTERN dbg_check_lock +#endif + + THUMB + +/* + * Performs a context switch between two threads. + */ + PUBLIC _port_switch +_port_switch: + push {r4, r5, r6, r7, r8, r9, r10, r11, lr} +#if CORTEX_USE_FPU + vpush {s16-s31} +#endif + str sp, [r1, #CONTEXT_OFFSET] + ldr sp, [r0, #CONTEXT_OFFSET] +#if CORTEX_USE_FPU + vpop {s16-s31} +#endif + pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} + +/* + * Start a thread by invoking its work function. + * If the work function returns @p chThdExit() is automatically invoked. + */ + PUBLIC _port_thread_start +_port_thread_start: +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif +#if CORTEX_SIMPLIFIED_PRIORITY + cpsie i +#else + movs r3, #CORTEX_BASEPRI_DISABLED + msr BASEPRI, r3 +#endif + mov r0, r5 + blx r4 + bl chThdExit + +/* + * Post-IRQ switch code. + * Exception handlers return here for context switching. + */ + PUBLIC _port_switch_from_isr + PUBLIC _port_exit_from_isr +_port_switch_from_isr: +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif +_port_exit_from_isr: +#if CORTEX_SIMPLIFIED_PRIORITY + mov r3, #LWRD SCB_ICSR + movt r3, #HWRD SCB_ICSR + mov r2, #ICSR_PENDSVSET + str r2, [r3] + cpsie i +.L3: b .L3 +#else + svc #0 +#endif + + END diff --git a/Project/os/ports/IAR/ARMCMx/chtypes.h b/Project/os/ports/IAR/ARMCMx/chtypes.h new file mode 100644 index 0000000..595f4f7 --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/chtypes.h @@ -0,0 +1,87 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file IAR/ARMCMx/chtypes.h + * @brief ARM Cortex-Mx port system types. + * + * @addtogroup IAR_ARMCMx_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#define __need_NULL +#define __need_size_t +#define __need_ptrdiff_t +#include + +#include + +typedef int32_t bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint32_t tprio_t; /**< Thread priority. */ +typedef int32_t msg_t; /**< Inter-thread message. */ +typedef int32_t eventid_t; /**< Event Id. */ +typedef uint32_t eventmask_t; /**< Events mask. */ +typedef uint32_t systime_t; /**< System time. */ +typedef int32_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE inline + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note Empty in this port. + */ +#define PACK_STRUCT_STRUCT + +/** + * @brief Packed structure modifier (before). + */ +#define PACK_STRUCT_BEGIN __packed + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/Project/os/ports/IAR/ARMCMx/cstartup.s b/Project/os/ports/IAR/ARMCMx/cstartup.s new file mode 100644 index 0000000..0066b01 --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/cstartup.s @@ -0,0 +1,75 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + + MODULE ?cstartup + +CONTROL_MODE_PRIVILEGED SET 0 +CONTROL_MODE_UNPRIVILEGED SET 1 +CONTROL_USE_MSP SET 0 +CONTROL_USE_PSP SET 2 + + AAPCS INTERWORK, VFP_COMPATIBLE, ROPI + PRESERVE8 + + SECTION .intvec:CODE:NOROOT(3) + + SECTION CSTACK:DATA:NOROOT(3) + PUBLIC __main_thread_stack_base__ +__main_thread_stack_base__: + PUBLIC __heap_end__ +__heap_end__: + + SECTION SYSHEAP:DATA:NOROOT(3) + PUBLIC __heap_base__ +__heap_base__: + + PUBLIC __iar_program_start + EXTERN __vector_table + EXTWEAK __iar_init_core + EXTWEAK __iar_init_vfp + EXTERN __cmain + + SECTION .text:CODE:REORDER(2) + REQUIRE __vector_table + THUMB +__iar_program_start: + cpsid i + ldr r0, =SFE(CSTACK) + msr PSP, r0 + movs r0, #CONTROL_MODE_PRIVILEGED | CONTROL_USE_PSP + msr CONTROL, r0 + isb + bl __early_init + bl __iar_init_core + bl __iar_init_vfp + b __cmain + + PUBWEAK __early_init +__early_init: + bx lr + + END diff --git a/Project/os/ports/IAR/ARMCMx/port.dox b/Project/os/ports/IAR/ARMCMx/port.dox new file mode 100644 index 0000000..2ea9066 --- /dev/null +++ b/Project/os/ports/IAR/ARMCMx/port.dox @@ -0,0 +1,235 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup IAR_ARMCMx ARM Cortex-Mx + * @details ARM Cortex-Mx port for the IAR compiler. + + * @section IAR_ARMCMx_INTRO Introduction + * This port supports all the cores implementing the ARMv6-M and ARMv7-M + * architectures. + * + * @section IAR_ARMCMx_MODES Kernel Modes + * The Cortex-Mx port supports two distinct kernel modes: + * - Advanced Kernel mode. In this mode the kernel only masks + * interrupt sources with priorities below or equal to the + * @p CORTEX_BASEPRI_KERNEL level. Higher priorities are not affected by + * the kernel critical sections and can be used for fast interrupts. + * This mode is not available in the ARMv6-M architecture which does not + * support priority masking. + * - Compact Kernel mode. In this mode the kernel handles IRQ priorities + * in a simplified way, all interrupt sources are disabled when the kernel + * enters into a critical zone and re-enabled on exit. This is simple and + * adequate for most applications, this mode results in a more compact and + * faster kernel. + * . + * The selection of the mode is performed using the port configuration option + * @p CORTEX_SIMPLIFIED_PRIORITY. Apart from the different handling of + * interrupts there are no other differences between the two modes. The + * kernel API is exactly the same. + * + * @section IAR_ARMCMx_STATES_A System logical states in Compact Kernel mode + * The ChibiOS/RT logical @ref system_states are mapped as follow in Compact + * Kernel mode: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). In this state interrupts are enabled. The processor + * is running in thread-privileged mode. + * - Suspended. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. In this + * mode this state is not different from the Disabled state. + * - Disabled. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. In this + * mode this state is not different from the Suspended state. + * - Sleep. This state is entered with the execution of the specific + * instruction @p wfi. + * - S-Locked. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. + * - I-Locked. In this state the interrupt sources are globally + * disabled. The processor is running in exception-privileged mode. + * - Serving Regular Interrupt. In this state the interrupt sources are + * not globally masked but only interrupts with higher priority can preempt + * the current handler. The processor is running in exception-privileged + * mode. + * - Serving Fast Interrupt. Not implemented in compact kernel mode. + * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific + * asynchronous NMI vector and several synchronous fault vectors that can + * be considered belonging to this category. + * - Halted. Implemented as an infinite loop after globally masking all + * the maskable interrupt sources. The ARM state is whatever the processor + * was running when @p chSysHalt() was invoked. + * + * @section IAR_ARMCMx_STATES_B System logical states in Advanced Kernel mode + * The ChibiOS/RT logical @ref system_states are mapped as follow in the + * Advanced Kernel mode: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register + * set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The + * processor is running in thread-privileged mode. + * - Suspended. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in thread-privileged mode. + * - Disabled. Interrupt sources are globally masked. The processor + * is running in thread-privileged mode. + * - Sleep. This state is entered with the execution of the specific + * instruction @p wfi. + * - S-Locked. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in thread-privileged mode. + * - I-Locked. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in exception-privileged mode. + * - Serving Regular Interrupt. In this state the interrupt sources are + * not globally masked but only interrupts with higher priority can preempt + * the current handler. The processor is running in exception-privileged + * mode. + * - Serving Fast Interrupt. Fast interrupts are defined as interrupt + * sources having higher priority level than the kernel + * (@p CORTEX_BASEPRI_KERNEL). In this state is not possible to switch to + * the I-Locked state because fast interrupts can preempt the kernel + * critical zone.
+ * This state is not implemented in the ARMv6-M implementation because + * priority masking is not present in this architecture. + * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific + * asynchronous NMI vector and several synchronous fault vectors that can + * be considered belonging to this category. + * - Halted. Implemented as an infinite loop after globally masking all + * the maskable interrupt sources. The ARM state is whatever the processor + * was running when @p chSysHalt() was invoked. + * . + * @section IAR_ARMCMx_NOTES ARM Cortex-Mx/IAR port notes + * The ARM Cortex-Mx port is organized as follow: + * - The @p main() function is invoked in thread-privileged mode. + * - Each thread has a private process stack, the system has a single main + * stack where all the interrupts and exceptions are processed. + * - The threads are started in thread-privileged mode. + * - Interrupt nesting and the other advanced core/NVIC features are supported. + * - The Cortex-Mx port is perfectly generic, support for more devices can be + * easily added by adding a subdirectory under ./os/ports/IAR/ARMCMx + * and giving it the name of the new device, then copy the files from another + * device into the new directory and customize them for the new device. + * . + * @ingroup iar + */ + +/** + * @defgroup IAR_ARMCMx_CONF Configuration Options + * @details ARM Cortex-Mx Configuration Options. The ARMCMx port allows some + * architecture-specific configurations settings that can be overridden + * by redefining them in @p chconf.h. Usually there is no need to change + * the default values. + * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used + * by an interrupt handler between the @p extctx and @p intctx + * structures. + * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE + * thread. Usually there is no need to change this value unless inserting + * code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro. + * - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler. + * - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler. + * - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the + * @p wfi instruction from within the idle loop. This option is + * defaulted to FALSE because it can create problems with some debuggers. + * Setting this option to TRUE reduces the system power requirements. + * . + * @section IAR_ARMCMx_CONF_1 ARMv6-M specific options + * The following options are specific for the ARMv6-M architecture: + * - @p CORTEX_ALTERNATE_SWITCH, when activated makes the OS use the PendSV + * exception instead of NMI as preemption handler. + * . + * @section IAR_ARMCMx_CONF_2 ARMv7-M specific options + * The following options are specific for the ARMv6-M architecture: + * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler. + * - @p CORTEX_SIMPLIFIED_PRIORITY, when enabled activates the Compact kernel + * mode. + * . + * @ingroup IAR_ARMCMx + */ + +/** + * @defgroup IAR_ARMCMx_CORE Core Port Implementation + * @details ARM Cortex-Mx specific port code, structures and macros. + * + * @ingroup IAR_ARMCMx + */ + +/** + * @defgroup IAR_ARMCMx_V6M_CORE ARMv6-M Specific Implementation + * @details ARMv6-M specific port code, structures and macros. + * + * @ingroup IAR_ARMCMx_CORE + */ + +/** + * @defgroup IAR_ARMCMx_V7M_CORE ARMv7-M Specific Implementation + * @details ARMv7-M specific port code, structures and macros. + * + * @ingroup IAR_ARMCMx_CORE + */ + +/** + * @defgroup IAR_ARMCMx_STARTUP Startup Support + * @details ChibiOS/RT provides its own generic startup file for the ARM + * Cortex-Mx port. + * Of course it is not mandatory to use it but care should be taken about the + * startup phase details. + * + * @section IAR_ARMCMx_STARTUP_1 Startup Process + * The startup process, as implemented, is the following: + * -# Interrupts are masked globally. + * -# The two stacks are initialized by assigning them the sizes defined in the + * linker script (usually named @p ch.icf). + * -# The CPU state is switched to Privileged and the PSP stack is used. + * -# An early initialization routine @p __early_init() is invoked, if the + * symbol is not defined then an empty default routine is executed + * (weak symbol). + * -# Control is passed to the C runtime entry point @p __cmain that performs + * the required initializations before invoking the @p main() function. + * . + * @ingroup IAR_ARMCMx + */ + +/** + * @defgroup IAR_ARMCMx_NVIC NVIC Support + * @details ARM Cortex-Mx NVIC support. + * + * @ingroup IAR_ARMCMx + */ + +/** + * @defgroup IAR_ARMCMx_SPECIFIC Specific Implementations + * @details Platform-specific port code. + * + * @ingroup IAR_ARMCMx + */ diff --git a/Project/os/ports/RC/STM8/chcore.c b/Project/os/ports/RC/STM8/chcore.c new file mode 100644 index 0000000..62f0a2a --- /dev/null +++ b/Project/os/ports/RC/STM8/chcore.c @@ -0,0 +1,84 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file RC/STM8/chcore.c + * @brief STM8 (Raisonance) architecture port code. + * + * @addtogroup STM8_RAISONANCE_CORE + * @{ + */ +#pragma SRC("tmp.asm") + +#include "ch.h" + +page0 ReadyList rlist; + +/** + * @brief Performs a context switch between two threads. + * + * @param otp the thread to be switched out + */ +void _port_switch(Thread *otp) { + + (void)otp; + /* Asm because unoptimal code would generated by using _getSP_().*/ +#pragma ASM + LDW Y,SP ; old context pointer + LDW (5,X),Y ; SP saved in otp->p_ctx.sp + LDW X,rlist + 5 ; r_current (currp) field + LDW X,(5,X) ; currp->p_ctx.sp + LDW SP,X ; new context pointer +#pragma ENDASM +} + +/** + * @brief Thread start code. + */ +void _port_thread_start(void) { + + chSysUnlock(); +#pragma ASM + POPW X +#pragma ENDASM +} + +/** + * @brief Halts the system. + * @details This function is invoked by the operating system when an + * unrecoverable error is detected (for example because a programming + * error in the application code that triggers an assertion while in + * debug mode). + */ +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** @} */ diff --git a/Project/os/ports/RC/STM8/chcore.h b/Project/os/ports/RC/STM8/chcore.h new file mode 100644 index 0000000..da29a72 --- /dev/null +++ b/Project/os/ports/RC/STM8/chcore.h @@ -0,0 +1,341 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file RC/STM8/chcore.h + * @brief STM8 (Raisonance) architecture port macros and structures. + * + * @addtogroup STM8_RAISONANCE_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +#include + +#if CH_DBG_ENABLE_STACK_CHECK +#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port" +#endif + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#ifndef STM8_ENABLE_WFI_IDLE +#define STM8_ENABLE_WFI_IDLE FALSE +#endif + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +/** + * @brief Unique macro for the implemented architecture. + */ +#define CH_ARCHITECTURE_STM8 + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "STM8" + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "Raisonance" + +/** + * @brief Port-specific information string. + */ +#define CH_PORT_INFO "None" + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +/** + * @brief Base type for stack alignment. + * @note No alignment constraints so uint8_t. + */ +typedef uint8_t stkalign_t; + +/** + * @brief Generic STM8 function pointer. + * @note It is used to allocate the proper size for return addresses in + * context-related structures. + */ +typedef void (*stm8func_t)(void); + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + * @note The structure requires one dummy field at its start because the + * stack is handled as preincremented/postdecremented. + */ +struct extctx { + uint8_t _next; + uint16_t cx; + uint16_t bx; + uint8_t cc; + uint8_t a; + uint16_t x; + uint16_t y; + uint8_t pce; + uint8_t pch; + uint8_t pcl; +}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching.. + * @note The structure requires one dummy field at its start because the + * stack is handled as preincremented/postdecremented. + */ +struct intctx { + uint8_t _next; + stm8func_t pc; /* Function pointer sized return address. */ +}; + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details This structure usually contains just the saved stack pointer + * defined as a pointer to a @p intctx structure. + */ +struct context { + struct intctx *sp; +}; + +/** + * @brief Start context. + * @details This context is the stack organization for the trampoline code + * @p _port_thread_start(). + */ +struct stm8_startctx { + uint8_t _next; + stm8func_t ts; /* Trampoline address. */ + void *arg; /* Thread argument. */ + stm8func_t pc; /* Thread function address. */ + stm8func_t ret; /* chThdExit() address. */ +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + struct stm8_startctx *scp; \ + scp = (struct stm8_startctx *)((uint8_t *)workspace + wsize - \ + sizeof(struct stm8_startctx)); \ + scp->ts = _port_thread_start; \ + scp->arg = arg; \ + scp->pc = (stm8func_t)pf; \ + scp->ret = (stm8func_t)chThdExit; \ + tp->p_ctx.sp = (struct intctx *)scp; \ +} + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + */ +#ifndef PORT_IDLE_THREAD_STACK_SIZE +#define PORT_IDLE_THREAD_STACK_SIZE 0 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This is a safe value, you may trim it down after reading the + * right size in the map file. + */ +#ifndef PORT_INT_REQUIRED_STACK +#define PORT_INT_REQUIRED_STACK 48 +#endif + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + (sizeof(struct intctx) - 1) + \ + (sizeof(struct extctx) - 1) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() { \ +} + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() { \ + dbg_check_lock(); \ + if (chSchIsPreemptionRequired()) \ + chSchDoReschedule(); \ + dbg_check_unlock(); \ +} + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void vector##id(void) interrupt id + +/** + * @brief Port-related initialization code. + * @note None in this port. + */ +#define port_init() + +/** + * @brief Kernel-lock action. + * @note Implemented as global interrupts disable. + */ +#define port_lock() _sim_() + +/** + * @brief Kernel-unlock action. + * @note Implemented as global interrupts enable. + */ +#define port_unlock() _rim_() + +/** + * @brief Kernel-lock action from an interrupt handler. + * @note This function is empty in this port. + */ +#define port_lock_from_isr() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @note This function is empty in this port. + */ +#define port_unlock_from_isr() + +/** + * @brief Disables all the interrupt sources. + * @note Implemented as global interrupts disable. + * @note Of course non-maskable interrupt sources are not included. + */ +#define port_disable() _sim_() + +/** + * @brief Disables the interrupt sources that are not supposed to preempt + * the kernel. + * @note Same as @p port_disable() in this port, there is no difference + * between the two states. + */ +#define port_suspend() _sim_() + +/** + * @brief Enables all the interrupt sources. + * @note Implemented as global interrupt enable. + */ +#define port_enable() _rim_() + +/** + * @brief Enters an architecture-dependent halt mode. + * @note Implemented with the specific "wfi" instruction. + */ +#if STM8_ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() _wfi_() +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note Implemented as a call to a low level assembler routine. + * + * @param ntp the thread to be switched in + * @param otp the thread to be switched out + */ +#define port_switch(ntp, otp) _port_switch(otp) + +#ifdef __cplusplus +extern "C" { +#endif + void _port_switch(Thread *otp); + void _port_thread_start(void); + void port_halt(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Scheduler captured code. */ +/*===========================================================================*/ + +#define PORT_OPTIMIZED_RLIST_VAR +#define PORT_OPTIMIZED_RLIST_EXT +#define PORT_OPTIMIZED_READYLIST_STRUCT + +typedef struct { + ThreadsQueue r_queue; + tprio_t r_prio; + Thread *r_current; +#if CH_USE_REGISTRY + Thread *r_newer; + Thread *r_older; +#endif + /* End of the fields shared with the Thread structure.*/ +#if CH_TIME_QUANTUM > 0 + cnt_t r_preempt; +#endif +} ReadyList; + +page0 extern ReadyList rlist; + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/Project/os/ports/RC/STM8/chtypes.h b/Project/os/ports/RC/STM8/chtypes.h new file mode 100644 index 0000000..07e33d5 --- /dev/null +++ b/Project/os/ports/RC/STM8/chtypes.h @@ -0,0 +1,138 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file RC/STM8/chtypes.h + * @brief STM8 (Raisonance) port system types. + * + * @addtogroup STM8_RAISONANCE_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#define __need_NULL +#define __need_size_t +#include + +//#if !defined(_STDINT_H) && !defined(__STDINT_H_) +//#include +//#endif + +typedef unsigned char uint8_t; /**< C99-style 8 bits unsigned. */ +typedef signed char int8_t; /**< C99-style 8 bits signed. */ +typedef unsigned int uint16_t; /**< C99-style 16 bits unsigned. */ +typedef signed int int16_t; /**< C99-style 16 bits signed. */ +typedef unsigned long uint32_t; /**< C99-style 32 bits unsigned. */ +typedef signed long int32_t; /**< C99-style 32 bits signed. */ +typedef uint8_t uint_fast8_t; /**< C99-style 8 bits unsigned. */ +typedef uint16_t uint_fast16_t; /**< C99-style 16 bits unsigned. */ +typedef uint32_t uint_fast32_t; /**< C99-style 32 bits unsigned. */ + +/** + * @brief Boolean, recommended the fastest signed. + */ +typedef int8_t bool_t; + +/** + * @brief Thread mode flags, uint8_t is ok. + */ +typedef uint8_t tmode_t; + +/** + * @brief Thread state, uint8_t is ok. + */ +typedef uint8_t tstate_t; + +/** + * @brief Thread references counter, uint8_t is ok. + */ +typedef uint8_t trefs_t; + +/** + * @brief Priority, use the fastest unsigned type. + */ +typedef uint8_t tprio_t; + +/** + * @brief Message, use signed pointer equivalent. + */ +typedef int16_t msg_t; + +/** + * @brief Event Id, use fastest signed. + */ +typedef int8_t eventid_t; + +/** + * @brief Event Mask, recommended fastest unsigned. + */ +typedef uint8_t eventmask_t; + +/** + * @brief System Time, recommended fastest unsigned. + */ +typedef uint16_t systime_t; + +/** + * @brief Counter, recommended fastest signed. + */ +typedef int8_t cnt_t; + +/** + * @brief Inline function modifier. + */ +#define INLINE inline + +/** + * @brief ROM constant modifier. + * @note Uses the "const" keyword in this port. + */ +#define ROMCONST code + +/** + * @brief Packed structure modifier (within). + * @note Empty in this port. + */ +#define PACK_STRUCT_STRUCT + +/** + * @brief Packed structure modifier (before). + * @note Empty in this port. + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/Project/os/ports/RC/STM8/port.dox b/Project/os/ports/RC/STM8/port.dox new file mode 100644 index 0000000..1279bb7 --- /dev/null +++ b/Project/os/ports/RC/STM8/port.dox @@ -0,0 +1,102 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup STM8_RAISONANCE STM8 + * @details STM8 port for the Raisonance C compiler. + * + * @section STM8_RAISONANCE_INTRO Introduction + * This port supports all STM8 8 bits MCUs. + * + * @section STM8_RAISONANCE_STATES Mapping of the System States in the STM8 port + * The ChibiOS/RT logical @ref system_states are mapped as follow in the STM8 + * port: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). Interrupts are enabled. + * - Suspended. Interrupts are disabled. + * - Disabled. Interrupts are disabled. This state is equivalent to the + * Suspended state because there are no fast interrupts in this architecture. + * - Sleep. Implemented with "wait" instruction insertion in the idle + * loop. + * - S-Locked. Interrupts are disabled. + * - I-Locked. This state is equivalent to the SRI state, the + * @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in + * order to formally change state because this may change). + * - Serving Regular Interrupt. Normal interrupt service code. + * - Serving Fast Interrupt. Not present in this architecture. + * - Serving Non-Maskable Interrupt. The STM8 ha non + * maskable interrupt sources that can be associated to this state. + * - Halted. Implemented as an infinite loop with interrupts disabled. + * . + * @section STM8_RAISONANCE_NOTES The STM8 port notes + * - The STM8 does not have a dedicated interrupt stack, make sure to reserve + * enough stack space for interrupts in each thread stack. This can be done + * by modifying the @p INT_REQUIRED_STACK macro into + * ./os/ports/RC/STM8/chcore.h. + * - The kernel currently supports only the small memory model so the + * kernel files should be loaded in the first 64K. Note that this is not + * a problem because upper addresses can be used by the user code, the + * kernel can context switch code running there. + * - The configuration option @p CH_OPTIMIZE_SPEED is not currently supported + * because the missing support of the @p inline "C" keyword in the + * compiler. + * . + * @ingroup raisonance + */ + +/** + * @defgroup STM8_RAISONANCE_CONF Configuration Options + * @details STM8 Configuration Options. The STM8 port allows some + * architecture-specific configurations settings that can be overridden + * by redefining them in @p chconf.h. Usually there is no need to change + * the default values. + * - @p INT_REQUIRED_STACK, this value represent the amount of stack space + * used by the interrupt handlers.
+ * The default for this value is @p 48, this space is allocated for each + * thread so be careful in order to not waste precious RAM space. + * . + * @ingroup STM8_RAISONANCE + */ + +/** + * @defgroup STM8_RAISONANCE_CORE Core Port Implementation + * @details STM8 specific port code, structures and macros. + * + * @ingroup STM8_RAISONANCE + */ + + /** + * @defgroup STM8_RAISONANCE_STARTUP Startup Support + * @details ChibiOS/RT doed not provide startup files for the STM8, there + * are no special startup requirement so the normal toolchain-provided + * startup files can be used. + * + * @ingroup STM8_RAISONANCE + */ diff --git a/Project/os/ports/RVCT/ARMCMx/LPC11xx/cmparams.h b/Project/os/ports/RVCT/ARMCMx/LPC11xx/cmparams.h new file mode 100644 index 0000000..f6d239e --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/LPC11xx/cmparams.h @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file RVCT/ARMCMx/LPC11xx/cmparams.h + * @brief ARM Cortex-M0 parameters for the LPC11xx. + * + * @defgroup RVCT_ARMCMx_LPC11xx LPC11xx Specific Parameters + * @ingroup RVCT_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M0 specific parameters for the + * LPC11xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M0 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 2 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/Project/os/ports/RVCT/ARMCMx/LPC11xx/vectors.s b/Project/os/ports/RVCT/ARMCMx/LPC11xx/vectors.s new file mode 100644 index 0000000..cb4091e --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/LPC11xx/vectors.s @@ -0,0 +1,190 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + + PRESERVE8 + + AREA RESET, DATA, READONLY + + IMPORT __initial_msp + IMPORT Reset_Handler + EXPORT __Vectors + +__Vectors + DCD __initial_msp + DCD Reset_Handler + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + + AREA |.text|, CODE, READONLY + THUMB + +/* + * Default interrupt handlers. + */ + EXPORT _unhandled_exception +_unhandled_exception PROC + EXPORT NMIVector [WEAK] + EXPORT HardFaultVector [WEAK] + EXPORT MemManageVector [WEAK] + EXPORT BusFaultVector [WEAK] + EXPORT UsageFaultVector [WEAK] + EXPORT Vector1C [WEAK] + EXPORT Vector20 [WEAK] + EXPORT Vector24 [WEAK] + EXPORT Vector28 [WEAK] + EXPORT SVCallVector [WEAK] + EXPORT DebugMonitorVector [WEAK] + EXPORT Vector34 [WEAK] + EXPORT PendSVVector [WEAK] + EXPORT SysTickVector [WEAK] + EXPORT Vector40 [WEAK] + EXPORT Vector44 [WEAK] + EXPORT Vector48 [WEAK] + EXPORT Vector4C [WEAK] + EXPORT Vector50 [WEAK] + EXPORT Vector54 [WEAK] + EXPORT Vector58 [WEAK] + EXPORT Vector5C [WEAK] + EXPORT Vector60 [WEAK] + EXPORT Vector64 [WEAK] + EXPORT Vector68 [WEAK] + EXPORT Vector6C [WEAK] + EXPORT Vector70 [WEAK] + EXPORT Vector74 [WEAK] + EXPORT Vector78 [WEAK] + EXPORT Vector7C [WEAK] + EXPORT Vector80 [WEAK] + EXPORT Vector84 [WEAK] + EXPORT Vector88 [WEAK] + EXPORT Vector8C [WEAK] + EXPORT Vector90 [WEAK] + EXPORT Vector94 [WEAK] + EXPORT Vector98 [WEAK] + EXPORT Vector9C [WEAK] + EXPORT VectorA0 [WEAK] + EXPORT VectorA4 [WEAK] + EXPORT VectorA8 [WEAK] + EXPORT VectorAC [WEAK] + EXPORT VectorB0 [WEAK] + EXPORT VectorB4 [WEAK] + EXPORT VectorB8 [WEAK] + EXPORT VectorBC [WEAK] + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC + b _unhandled_exception + ENDP + + END diff --git a/Project/os/ports/RVCT/ARMCMx/LPC13xx/cmparams.h b/Project/os/ports/RVCT/ARMCMx/LPC13xx/cmparams.h new file mode 100644 index 0000000..3eaa4b1 --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/LPC13xx/cmparams.h @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file RVCT/ARMCMx/LPC13xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the LPC13xx. + * + * @defgroup RVCT_ARMCMx_LPC13xx LPC13xx Specific Parameters + * @ingroup RVCT_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * LPC13xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 3 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/Project/os/ports/RVCT/ARMCMx/LPC13xx/vectors.s b/Project/os/ports/RVCT/ARMCMx/LPC13xx/vectors.s new file mode 100644 index 0000000..a9bdfad --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/LPC13xx/vectors.s @@ -0,0 +1,262 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + + PRESERVE8 + + AREA RESET, DATA, READONLY + + IMPORT __initial_msp + IMPORT Reset_Handler + EXPORT __Vectors + +__Vectors + DCD __initial_msp + DCD Reset_Handler + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + DCD VectorC0 + DCD VectorC4 + DCD VectorC8 + DCD VectorCC + DCD VectorD0 + DCD VectorD4 + DCD VectorD8 + DCD VectorDC + DCD VectorE0 + DCD VectorE4 + DCD VectorE8 + DCD VectorEC + DCD VectorF0 + DCD VectorF4 + DCD VectorF8 + DCD VectorFC + DCD Vector100 + DCD Vector104 + DCD Vector108 + DCD Vector10C + DCD Vector110 + DCD Vector114 + DCD Vector118 + DCD Vector11C + + AREA |.text|, CODE, READONLY + THUMB + +/* + * Default interrupt handlers. + */ + EXPORT _unhandled_exception +_unhandled_exception PROC + EXPORT NMIVector [WEAK] + EXPORT HardFaultVector [WEAK] + EXPORT MemManageVector [WEAK] + EXPORT BusFaultVector [WEAK] + EXPORT UsageFaultVector [WEAK] + EXPORT Vector1C [WEAK] + EXPORT Vector20 [WEAK] + EXPORT Vector24 [WEAK] + EXPORT Vector28 [WEAK] + EXPORT SVCallVector [WEAK] + EXPORT DebugMonitorVector [WEAK] + EXPORT Vector34 [WEAK] + EXPORT PendSVVector [WEAK] + EXPORT SysTickVector [WEAK] + EXPORT Vector40 [WEAK] + EXPORT Vector44 [WEAK] + EXPORT Vector48 [WEAK] + EXPORT Vector4C [WEAK] + EXPORT Vector50 [WEAK] + EXPORT Vector54 [WEAK] + EXPORT Vector58 [WEAK] + EXPORT Vector5C [WEAK] + EXPORT Vector60 [WEAK] + EXPORT Vector64 [WEAK] + EXPORT Vector68 [WEAK] + EXPORT Vector6C [WEAK] + EXPORT Vector70 [WEAK] + EXPORT Vector74 [WEAK] + EXPORT Vector78 [WEAK] + EXPORT Vector7C [WEAK] + EXPORT Vector80 [WEAK] + EXPORT Vector84 [WEAK] + EXPORT Vector88 [WEAK] + EXPORT Vector8C [WEAK] + EXPORT Vector90 [WEAK] + EXPORT Vector94 [WEAK] + EXPORT Vector98 [WEAK] + EXPORT Vector9C [WEAK] + EXPORT VectorA0 [WEAK] + EXPORT VectorA4 [WEAK] + EXPORT VectorA8 [WEAK] + EXPORT VectorAC [WEAK] + EXPORT VectorB0 [WEAK] + EXPORT VectorB4 [WEAK] + EXPORT VectorB8 [WEAK] + EXPORT VectorBC [WEAK] + EXPORT VectorC0 [WEAK] + EXPORT VectorC4 [WEAK] + EXPORT VectorC8 [WEAK] + EXPORT VectorCC [WEAK] + EXPORT VectorD0 [WEAK] + EXPORT VectorD4 [WEAK] + EXPORT VectorD8 [WEAK] + EXPORT VectorDC [WEAK] + EXPORT VectorE0 [WEAK] + EXPORT VectorE4 [WEAK] + EXPORT VectorE8 [WEAK] + EXPORT VectorEC [WEAK] + EXPORT VectorF0 [WEAK] + EXPORT VectorF4 [WEAK] + EXPORT VectorF8 [WEAK] + EXPORT VectorFC [WEAK] + EXPORT Vector100 [WEAK] + EXPORT Vector104 [WEAK] + EXPORT Vector108 [WEAK] + EXPORT Vector10C [WEAK] + EXPORT Vector110 [WEAK] + EXPORT Vector114 [WEAK] + EXPORT Vector118 [WEAK] + EXPORT Vector11C [WEAK] + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +VectorC0 +VectorC4 +VectorC8 +VectorCC +VectorD0 +VectorD4 +VectorD8 +VectorDC +VectorE0 +VectorE4 +VectorE8 +VectorEC +VectorF0 +VectorF4 +VectorF8 +VectorFC +Vector100 +Vector104 +Vector108 +Vector10C +Vector110 +Vector114 +Vector118 +Vector11C + b _unhandled_exception + ENDP + + END diff --git a/Project/os/ports/RVCT/ARMCMx/STM32F1xx/cmparams.h b/Project/os/ports/RVCT/ARMCMx/STM32F1xx/cmparams.h new file mode 100644 index 0000000..738cd2f --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/STM32F1xx/cmparams.h @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file RVCT/ARMCMx/STM32F1xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32F1xx. + * + * @defgroup RVCT_ARMCMx_STM32F1xx STM32F1xx Specific Parameters + * @ingroup RVCT_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * STM32F1xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/Project/os/ports/RVCT/ARMCMx/STM32F1xx/vectors.s b/Project/os/ports/RVCT/ARMCMx/STM32F1xx/vectors.s new file mode 100644 index 0000000..59610fa --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/STM32F1xx/vectors.s @@ -0,0 +1,313 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +#if !defined(STM32F10X_LD) && !defined(STM32F10X_LD_VL) && \ + !defined(STM32F10X_MD) && !defined(STM32F10X_MD_VL) && \ + !defined(STM32F10X_HD) && !defined(STM32F10X_XL) && \ + !defined(STM32F10X_CL) +#define _FROM_ASM_ +#include "board.h" +#endif + + PRESERVE8 + + AREA RESET, DATA, READONLY + + IMPORT __initial_msp + IMPORT Reset_Handler + EXPORT __Vectors + +__Vectors + DCD __initial_msp + DCD Reset_Handler + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + DCD VectorC0 + DCD VectorC4 + DCD VectorC8 + DCD VectorCC + DCD VectorD0 + DCD VectorD4 + DCD VectorD8 + DCD VectorDC + DCD VectorE0 + DCD VectorE4 + DCD VectorE8 +#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \ + defined(STM32F10X_XL) || defined(STM32F10X_CL) + DCD VectorEC + DCD VectorF0 + DCD VectorF4 +#endif +#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL) + DCD VectorF8 + DCD VectorFC + DCD Vector100 + DCD Vector104 + DCD Vector108 + DCD Vector10C + DCD Vector110 + DCD Vector114 + DCD Vector118 + DCD Vector11C + DCD Vector120 + DCD Vector124 + DCD Vector128 + DCD Vector12C +#endif +#if defined(STM32F10X_CL) + DCD Vector130 + DCD Vector134 + DCD Vector138 + DCD Vector13C + DCD Vector140 + DCD Vector144 + DCD Vector148 + DCD Vector14C +#endif + + AREA |.text|, CODE, READONLY + THUMB + +/* + * Default interrupt handlers. + */ + EXPORT _unhandled_exception +_unhandled_exception PROC + EXPORT NMIVector [WEAK] + EXPORT HardFaultVector [WEAK] + EXPORT MemManageVector [WEAK] + EXPORT BusFaultVector [WEAK] + EXPORT UsageFaultVector [WEAK] + EXPORT Vector1C [WEAK] + EXPORT Vector20 [WEAK] + EXPORT Vector24 [WEAK] + EXPORT Vector28 [WEAK] + EXPORT SVCallVector [WEAK] + EXPORT DebugMonitorVector [WEAK] + EXPORT Vector34 [WEAK] + EXPORT PendSVVector [WEAK] + EXPORT SysTickVector [WEAK] + EXPORT Vector40 [WEAK] + EXPORT Vector44 [WEAK] + EXPORT Vector48 [WEAK] + EXPORT Vector4C [WEAK] + EXPORT Vector50 [WEAK] + EXPORT Vector54 [WEAK] + EXPORT Vector58 [WEAK] + EXPORT Vector5C [WEAK] + EXPORT Vector60 [WEAK] + EXPORT Vector64 [WEAK] + EXPORT Vector68 [WEAK] + EXPORT Vector6C [WEAK] + EXPORT Vector70 [WEAK] + EXPORT Vector74 [WEAK] + EXPORT Vector78 [WEAK] + EXPORT Vector7C [WEAK] + EXPORT Vector80 [WEAK] + EXPORT Vector84 [WEAK] + EXPORT Vector88 [WEAK] + EXPORT Vector8C [WEAK] + EXPORT Vector90 [WEAK] + EXPORT Vector94 [WEAK] + EXPORT Vector98 [WEAK] + EXPORT Vector9C [WEAK] + EXPORT VectorA0 [WEAK] + EXPORT VectorA4 [WEAK] + EXPORT VectorA8 [WEAK] + EXPORT VectorAC [WEAK] + EXPORT VectorB0 [WEAK] + EXPORT VectorB4 [WEAK] + EXPORT VectorB8 [WEAK] + EXPORT VectorBC [WEAK] + EXPORT VectorC0 [WEAK] + EXPORT VectorC4 [WEAK] + EXPORT VectorC8 [WEAK] + EXPORT VectorCC [WEAK] + EXPORT VectorD0 [WEAK] + EXPORT VectorD4 [WEAK] + EXPORT VectorD8 [WEAK] + EXPORT VectorDC [WEAK] + EXPORT VectorE0 [WEAK] + EXPORT VectorE4 [WEAK] + EXPORT VectorE8 [WEAK] + EXPORT VectorEC [WEAK] + EXPORT VectorF0 [WEAK] + EXPORT VectorF4 [WEAK] + EXPORT VectorF8 [WEAK] + EXPORT VectorFC [WEAK] + EXPORT Vector100 [WEAK] + EXPORT Vector104 [WEAK] + EXPORT Vector108 [WEAK] + EXPORT Vector10C [WEAK] + EXPORT Vector110 [WEAK] + EXPORT Vector114 [WEAK] + EXPORT Vector118 [WEAK] + EXPORT Vector11C [WEAK] + EXPORT Vector120 [WEAK] + EXPORT Vector124 [WEAK] + EXPORT Vector128 [WEAK] + EXPORT Vector12C [WEAK] + EXPORT Vector130 [WEAK] + EXPORT Vector134 [WEAK] + EXPORT Vector138 [WEAK] + EXPORT Vector13C [WEAK] + EXPORT Vector140 [WEAK] + EXPORT Vector144 [WEAK] + EXPORT Vector148 [WEAK] + EXPORT Vector14C [WEAK] + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +VectorC0 +VectorC4 +VectorC8 +VectorCC +VectorD0 +VectorD4 +VectorD8 +VectorDC +VectorE0 +VectorE4 +VectorE8 +VectorEC +VectorF0 +VectorF4 +VectorF8 +VectorFC +Vector100 +Vector104 +Vector108 +Vector10C +Vector110 +Vector114 +Vector118 +Vector11C +Vector120 +Vector124 +Vector128 +Vector12C +Vector130 +Vector134 +Vector138 +Vector13C +Vector140 +Vector144 +Vector148 +Vector14C + b _unhandled_exception + ENDP + + END diff --git a/Project/os/ports/RVCT/ARMCMx/STM32F4xx/cmparams.h b/Project/os/ports/RVCT/ARMCMx/STM32F4xx/cmparams.h new file mode 100644 index 0000000..56fc9b1 --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/STM32F4xx/cmparams.h @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file RVCT/ARMCMx/STM32F4xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32F4xx. + * + * @defgroup RVCT_ARMCMx_STM32F4xx STM32F4xx Specific Parameters + * @ingroup RVCT_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M4 specific parameters for the + * STM32F4xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M4 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU TRUE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/Project/os/ports/RVCT/ARMCMx/STM32F4xx/vectors.s b/Project/os/ports/RVCT/ARMCMx/STM32F4xx/vectors.s new file mode 100644 index 0000000..dd4840c --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/STM32F4xx/vectors.s @@ -0,0 +1,345 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +#if !defined(STM32F4XX) +#define _FROM_ASM_ +#include "board.h" +#endif + + PRESERVE8 + + AREA RESET, DATA, READONLY + + IMPORT __initial_msp + IMPORT Reset_Handler + EXPORT __Vectors + +__Vectors + DCD __initial_msp + DCD Reset_Handler + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + DCD VectorC0 + DCD VectorC4 + DCD VectorC8 + DCD VectorCC + DCD VectorD0 + DCD VectorD4 + DCD VectorD8 + DCD VectorDC + DCD VectorE0 + DCD VectorE4 + DCD VectorE8 + DCD VectorEC + DCD VectorF0 + DCD VectorF4 + DCD VectorF8 + DCD VectorFC + DCD Vector100 + DCD Vector104 + DCD Vector108 + DCD Vector10C + DCD Vector110 + DCD Vector114 + DCD Vector118 + DCD Vector11C + DCD Vector120 + DCD Vector124 + DCD Vector128 + DCD Vector12C + DCD Vector130 + DCD Vector134 + DCD Vector138 + DCD Vector13C + DCD Vector140 + DCD Vector144 + DCD Vector148 + DCD Vector14C + DCD Vector150 + DCD Vector154 + DCD Vector158 + DCD Vector15C + DCD Vector160 + DCD Vector164 + DCD Vector168 + DCD Vector16C + DCD Vector170 + DCD Vector174 + DCD Vector178 + DCD Vector17C + DCD Vector180 + DCD Vector184 + + AREA |.text|, CODE, READONLY + THUMB + +/* + * Default interrupt handlers. + */ + EXPORT _unhandled_exception +_unhandled_exception PROC + EXPORT NMIVector [WEAK] + EXPORT HardFaultVector [WEAK] + EXPORT MemManageVector [WEAK] + EXPORT BusFaultVector [WEAK] + EXPORT UsageFaultVector [WEAK] + EXPORT Vector1C [WEAK] + EXPORT Vector20 [WEAK] + EXPORT Vector24 [WEAK] + EXPORT Vector28 [WEAK] + EXPORT SVCallVector [WEAK] + EXPORT DebugMonitorVector [WEAK] + EXPORT Vector34 [WEAK] + EXPORT PendSVVector [WEAK] + EXPORT SysTickVector [WEAK] + EXPORT Vector40 [WEAK] + EXPORT Vector44 [WEAK] + EXPORT Vector48 [WEAK] + EXPORT Vector4C [WEAK] + EXPORT Vector50 [WEAK] + EXPORT Vector54 [WEAK] + EXPORT Vector58 [WEAK] + EXPORT Vector5C [WEAK] + EXPORT Vector60 [WEAK] + EXPORT Vector64 [WEAK] + EXPORT Vector68 [WEAK] + EXPORT Vector6C [WEAK] + EXPORT Vector70 [WEAK] + EXPORT Vector74 [WEAK] + EXPORT Vector78 [WEAK] + EXPORT Vector7C [WEAK] + EXPORT Vector80 [WEAK] + EXPORT Vector84 [WEAK] + EXPORT Vector88 [WEAK] + EXPORT Vector8C [WEAK] + EXPORT Vector90 [WEAK] + EXPORT Vector94 [WEAK] + EXPORT Vector98 [WEAK] + EXPORT Vector9C [WEAK] + EXPORT VectorA0 [WEAK] + EXPORT VectorA4 [WEAK] + EXPORT VectorA8 [WEAK] + EXPORT VectorAC [WEAK] + EXPORT VectorB0 [WEAK] + EXPORT VectorB4 [WEAK] + EXPORT VectorB8 [WEAK] + EXPORT VectorBC [WEAK] + EXPORT VectorC0 [WEAK] + EXPORT VectorC4 [WEAK] + EXPORT VectorC8 [WEAK] + EXPORT VectorCC [WEAK] + EXPORT VectorD0 [WEAK] + EXPORT VectorD4 [WEAK] + EXPORT VectorD8 [WEAK] + EXPORT VectorDC [WEAK] + EXPORT VectorE0 [WEAK] + EXPORT VectorE4 [WEAK] + EXPORT VectorE8 [WEAK] + EXPORT VectorEC [WEAK] + EXPORT VectorF0 [WEAK] + EXPORT VectorF4 [WEAK] + EXPORT VectorF8 [WEAK] + EXPORT VectorFC [WEAK] + EXPORT Vector100 [WEAK] + EXPORT Vector104 [WEAK] + EXPORT Vector108 [WEAK] + EXPORT Vector10C [WEAK] + EXPORT Vector110 [WEAK] + EXPORT Vector114 [WEAK] + EXPORT Vector118 [WEAK] + EXPORT Vector11C [WEAK] + EXPORT Vector120 [WEAK] + EXPORT Vector124 [WEAK] + EXPORT Vector128 [WEAK] + EXPORT Vector12C [WEAK] + EXPORT Vector130 [WEAK] + EXPORT Vector134 [WEAK] + EXPORT Vector138 [WEAK] + EXPORT Vector13C [WEAK] + EXPORT Vector140 [WEAK] + EXPORT Vector144 [WEAK] + EXPORT Vector148 [WEAK] + EXPORT Vector14C [WEAK] + EXPORT Vector150 [WEAK] + EXPORT Vector154 [WEAK] + EXPORT Vector158 [WEAK] + EXPORT Vector15C [WEAK] + EXPORT Vector160 [WEAK] + EXPORT Vector164 [WEAK] + EXPORT Vector168 [WEAK] + EXPORT Vector16C [WEAK] + EXPORT Vector170 [WEAK] + EXPORT Vector174 [WEAK] + EXPORT Vector178 [WEAK] + EXPORT Vector17C [WEAK] + EXPORT Vector180 [WEAK] + EXPORT Vector184 [WEAK] + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +VectorC0 +VectorC4 +VectorC8 +VectorCC +VectorD0 +VectorD4 +VectorD8 +VectorDC +VectorE0 +VectorE4 +VectorE8 +VectorEC +VectorF0 +VectorF4 +VectorF8 +VectorFC +Vector100 +Vector104 +Vector108 +Vector10C +Vector110 +Vector114 +Vector118 +Vector11C +Vector120 +Vector124 +Vector128 +Vector12C +Vector130 +Vector134 +Vector138 +Vector13C +Vector140 +Vector144 +Vector148 +Vector14C +Vector150 +Vector154 +Vector158 +Vector15C +Vector160 +Vector164 +Vector168 +Vector16C +Vector170 +Vector174 +Vector178 +Vector17C +Vector180 +Vector184 + b _unhandled_exception + ENDP + + END diff --git a/Project/os/ports/RVCT/ARMCMx/STM32L1xx/cmparams.h b/Project/os/ports/RVCT/ARMCMx/STM32L1xx/cmparams.h new file mode 100644 index 0000000..ceef702 --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/STM32L1xx/cmparams.h @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file RVCT/ARMCMx/STM32L1xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32L1xx. + * + * @defgroup RVCT_ARMCMx_STM32L1xx STM32L1xx Specific Parameters + * @ingroup RVCT_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * STM32L1xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/Project/os/ports/RVCT/ARMCMx/STM32L1xx/vectors.s b/Project/os/ports/RVCT/ARMCMx/STM32L1xx/vectors.s new file mode 100644 index 0000000..5ed746a --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/STM32L1xx/vectors.s @@ -0,0 +1,234 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +#if !defined(STM32L1XX_MD) +#define _FROM_ASM_ +#include "board.h" +#endif + + PRESERVE8 + + AREA RESET, DATA, READONLY + + IMPORT __initial_msp + IMPORT Reset_Handler + EXPORT __Vectors + +__Vectors + DCD __initial_msp + DCD Reset_Handler + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + DCD VectorC0 + DCD VectorC4 + DCD VectorC8 + DCD VectorCC + DCD VectorD0 + DCD VectorD4 + DCD VectorD8 + DCD VectorDC + DCD VectorE0 + DCD VectorE4 + DCD VectorE8 + DCD VectorEC + DCD VectorF0 + + AREA |.text|, CODE, READONLY + THUMB + +/* + * Default interrupt handlers. + */ + EXPORT _unhandled_exception +_unhandled_exception PROC + EXPORT NMIVector [WEAK] + EXPORT HardFaultVector [WEAK] + EXPORT MemManageVector [WEAK] + EXPORT BusFaultVector [WEAK] + EXPORT UsageFaultVector [WEAK] + EXPORT Vector1C [WEAK] + EXPORT Vector20 [WEAK] + EXPORT Vector24 [WEAK] + EXPORT Vector28 [WEAK] + EXPORT SVCallVector [WEAK] + EXPORT DebugMonitorVector [WEAK] + EXPORT Vector34 [WEAK] + EXPORT PendSVVector [WEAK] + EXPORT SysTickVector [WEAK] + EXPORT Vector40 [WEAK] + EXPORT Vector44 [WEAK] + EXPORT Vector48 [WEAK] + EXPORT Vector4C [WEAK] + EXPORT Vector50 [WEAK] + EXPORT Vector54 [WEAK] + EXPORT Vector58 [WEAK] + EXPORT Vector5C [WEAK] + EXPORT Vector60 [WEAK] + EXPORT Vector64 [WEAK] + EXPORT Vector68 [WEAK] + EXPORT Vector6C [WEAK] + EXPORT Vector70 [WEAK] + EXPORT Vector74 [WEAK] + EXPORT Vector78 [WEAK] + EXPORT Vector7C [WEAK] + EXPORT Vector80 [WEAK] + EXPORT Vector84 [WEAK] + EXPORT Vector88 [WEAK] + EXPORT Vector8C [WEAK] + EXPORT Vector90 [WEAK] + EXPORT Vector94 [WEAK] + EXPORT Vector98 [WEAK] + EXPORT Vector9C [WEAK] + EXPORT VectorA0 [WEAK] + EXPORT VectorA4 [WEAK] + EXPORT VectorA8 [WEAK] + EXPORT VectorAC [WEAK] + EXPORT VectorB0 [WEAK] + EXPORT VectorB4 [WEAK] + EXPORT VectorB8 [WEAK] + EXPORT VectorBC [WEAK] + EXPORT VectorC0 [WEAK] + EXPORT VectorC4 [WEAK] + EXPORT VectorC8 [WEAK] + EXPORT VectorCC [WEAK] + EXPORT VectorD0 [WEAK] + EXPORT VectorD4 [WEAK] + EXPORT VectorD8 [WEAK] + EXPORT VectorDC [WEAK] + EXPORT VectorE0 [WEAK] + EXPORT VectorE4 [WEAK] + EXPORT VectorE8 [WEAK] + EXPORT VectorEC [WEAK] + EXPORT VectorF0 [WEAK] + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +VectorC0 +VectorC4 +VectorC8 +VectorCC +VectorD0 +VectorD4 +VectorD8 +VectorDC +VectorE0 +VectorE4 +VectorE8 +VectorEC +VectorF0 + b _unhandled_exception + ENDP + + END diff --git a/Project/os/ports/RVCT/ARMCMx/chcore.c b/Project/os/ports/RVCT/ARMCMx/chcore.c new file mode 100644 index 0000000..602752b --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/chcore.c @@ -0,0 +1,53 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file RVCT/ARMCMx/chcore.c + * @brief ARM Cortex-Mx port code. + * + * @addtogroup RVCT_ARMCMx_CORE + * @{ + */ + +#include "ch.h" + +/** + * @brief Halts the system. + * @note The function is declared as a weak symbol, it is possible + * to redefine it in your application code. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** @} */ diff --git a/Project/os/ports/RVCT/ARMCMx/chcore.h b/Project/os/ports/RVCT/ARMCMx/chcore.h new file mode 100644 index 0000000..64df4c5 --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/chcore.h @@ -0,0 +1,189 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file RVCT/ARMCMx/chcore.h + * @brief ARM Cortex-Mx port macros and structures. + * + * @addtogroup RVCT_ARMCMx_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +/*===========================================================================*/ +/* Port constants (common). */ +/*===========================================================================*/ + +/* Added to make the header stand-alone when included from asm.*/ +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE (!FALSE) +#endif + +#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */ +#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */ +#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */ +#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */ + +/* Inclusion of the Cortex-Mx implementation specific parameters.*/ +#include "cmparams.h" + +/* Cortex model check, only M0 and M3 supported right now.*/ +#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) || \ + (CORTEX_MODEL == CORTEX_M4) +#elif (CORTEX_MODEL == CORTEX_M1) +#error "untested Cortex-M model" +#else +#error "unknown or unsupported Cortex-M model" +#endif + +/** + * @brief Total priority levels. + */ +#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS) + +/** + * @brief Minimum priority level. + * @details This minimum priority level is calculated from the number of + * priority bits supported by the specific Cortex-Mx implementation. + */ +#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1) + +/** + * @brief Maximum priority level. + * @details The maximum allowed priority level is always zero. + */ +#define CORTEX_MAXIMUM_PRIORITY 0 + +/*===========================================================================*/ +/* Port macros (common). */ +/*===========================================================================*/ + +/** + * @brief Priority level verification macro. + */ +#define CORTEX_IS_VALID_PRIORITY(n) \ + (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS)) + +/** + * @brief Priority level to priority mask conversion macro. + */ +#define CORTEX_PRIORITY_MASK(n) \ + ((n) << (8 - CORTEX_PRIORITY_BITS)) + +/*===========================================================================*/ +/* Port configurable parameters (common). */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port derived parameters (common). */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port exported info (common). */ +/*===========================================================================*/ + +/** + * @brief Macro defining a generic ARM architecture. + */ +#define CH_ARCHITECTURE_ARM + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "RVCT" + +/*===========================================================================*/ +/* Port implementation part (common). */ +/*===========================================================================*/ + +/* Includes the sub-architecture-specific part.*/ +#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1) +#include "chcore_v6m.h" +#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4) +#include "chcore_v7m.h" +#endif + +#if !defined(_FROM_ASM_) + +#include "nvic.h" + +/* The following declarations are there just for Doxygen documentation, the + real declarations are inside the sub-headers.*/ +#if defined(__DOXYGEN__) + +/** + * @brief Stack and memory alignment enforcement. + * @note In this architecture the stack alignment is enforced to 64 bits, + * 32 bits alignment is supported by hardware but deprecated by ARM, + * the implementation choice is to not offer the option. + */ +typedef uint64_t stkalign_t; + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + * @note It is implemented to match the Cortex-Mx exception context. + */ +struct extctx {}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching. + */ +struct intctx {}; + +#endif /* defined(__DOXYGEN__) */ + +/** + * @brief Excludes the default @p chSchIsPreemptionRequired()implementation. + */ +#define PORT_OPTIMIZED_ISPREEMPTIONREQUIRED + +#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__) +/** + * @brief Inline-able version of this kernel function. + */ +#define chSchIsPreemptionRequired() \ + (rlist.r_preempt ? firstprio(&rlist.r_queue) > currp->p_prio : \ + firstprio(&rlist.r_queue) >= currp->p_prio) +#else /* CH_TIME_QUANTUM == 0 */ +#define chSchIsPreemptionRequired() \ + (firstprio(&rlist.r_queue) > currp->p_prio) +#endif /* CH_TIME_QUANTUM == 0 */ + +#endif /* _FROM_ASM_ */ + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/Project/os/ports/RVCT/ARMCMx/chcore_v6m.c b/Project/os/ports/RVCT/ARMCMx/chcore_v6m.c new file mode 100644 index 0000000..9f03899 --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/chcore_v6m.c @@ -0,0 +1,135 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file RVCT/ARMCMx/chcore_v6m.c + * @brief ARMv6-M architecture port code. + * + * @addtogroup RVCT_ARMCMx_V6M_CORE + * @{ + */ + +#include "ch.h" + +/*===========================================================================*/ +/* Port interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief System Timer vector. + * @details This interrupt is used as system tick. + * @note The timer must be initialized in the startup code. + */ +CH_IRQ_HANDLER(SysTickVector) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +/** + * @brief NMI vector. + * @details The NMI vector is used for exception mode re-entering after a + * context switch. + */ +void NMIVector(void) { + register struct extctx *ctxp; + register uint32_t psp __asm("psp"); + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp = (struct extctx *)psp; + ctxp++; + psp = (uint32_t)ctxp; + port_unlock_from_isr(); +} +#endif /* !CORTEX_ALTERNATE_SWITCH */ + +#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +/** + * @brief PendSV vector. + * @details The PendSV vector is used for exception mode re-entering after a + * context switch. + */ +void PendSVVector(void) { + register struct extctx *ctxp; + register uint32_t psp __asm("psp"); + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp = (struct extctx *)psp; + ctxp++; + psp = (uint32_t)ctxp; +} +#endif /* CORTEX_ALTERNATE_SWITCH */ + +/*===========================================================================*/ +/* Port exported functions. */ +/*===========================================================================*/ + +/** + * @brief IRQ epilogue code. + * + * @param[in] lr value of the @p LR register on ISR entry + */ +void _port_irq_epilogue(regarm_t lr) { + + if (lr != (regarm_t)0xFFFFFFF1) { + register struct extctx *ctxp; + register uint32_t psp __asm("psp"); + + port_lock_from_isr(); + /* Adding an artificial exception return context, there is no need to + populate it fully.*/ + ctxp = (struct extctx *)psp; + ctxp--; + psp = (uint32_t)ctxp; + ctxp->xpsr = (regarm_t)0x01000000; + + /* The exit sequence is different depending on if a preemption is + required or not.*/ + if (chSchIsPreemptionRequired()) { + /* Preemption is required we need to enforce a context switch.*/ + ctxp->pc = (regarm_t)_port_switch_from_isr; + } + else { + /* Preemption not required, we just need to exit the exception + atomically.*/ + ctxp->pc = (regarm_t)_port_exit_from_isr; + } + + /* Note, returning without unlocking is intentional, this is done in + order to keep the rest of the context switching atomic.*/ + } +} + +/** @} */ diff --git a/Project/os/ports/RVCT/ARMCMx/chcore_v6m.h b/Project/os/ports/RVCT/ARMCMx/chcore_v6m.h new file mode 100644 index 0000000..0ee5b9c --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/chcore_v6m.h @@ -0,0 +1,380 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file RVCT/ARMCMx/chcore_v6m.h + * @brief ARMv6-M architecture port macros and structures. + * + * @addtogroup RVCT_ARMCMx_V6M_CORE + * @{ + */ + +#ifndef _CHCORE_V6M_H_ +#define _CHCORE_V6M_H_ + +/*===========================================================================*/ +/* Port constants. */ +/*===========================================================================*/ + +/** + * @brief PendSV priority level. + * @note This priority is enforced to be equal to @p 0, + * this handler always has the highest priority that cannot preempt + * the kernel. + */ +#define CORTEX_PRIORITY_PENDSV 0 + +/*===========================================================================*/ +/* Port macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + * @note In this port it is set to 16 because the idle thread does have + * a stack frame when compiling without optimizations. You may + * reduce this value to zero when compiling with optimizations. + */ +#if !defined(PORT_IDLE_THREAD_STACK_SIZE) +#define PORT_IDLE_THREAD_STACK_SIZE 16 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * This value can be zero on those architecture where there is a + * separate interrupt stack and the stack space between @p intctx and + * @p extctx is known to be zero. + * @note In this port it is conservatively set to 32 because the function + * @p chSchDoReschedule() can have a stack frame, especially with + * compiler optimizations disabled. + */ +#if !defined(PORT_INT_REQUIRED_STACK) +#define PORT_INT_REQUIRED_STACK 32 +#endif + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#if !defined(CORTEX_ENABLE_WFI_IDLE) +#define CORTEX_ENABLE_WFI_IDLE FALSE +#endif + +/** + * @brief SYSTICK handler priority. + * @note The default SYSTICK handler priority is calculated as the priority + * level in the middle of the numeric priorities range. + */ +#if !defined(CORTEX_PRIORITY_SYSTICK) +#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) +#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) +/* If it is externally redefined then better perform a validity check on it.*/ +#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" +#endif + +/** + * @brief Alternate preemption method. + * @details Activating this option will make the Kernel use the PendSV + * handler for preemption instead of the NMI handler. + */ +#ifndef CORTEX_ALTERNATE_SWITCH +#define CORTEX_ALTERNATE_SWITCH FALSE +#endif + +/*===========================================================================*/ +/* Port derived parameters. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +/** + * @brief Macro defining the specific ARM architecture. + */ +#define CH_ARCHITECTURE_ARM_v6M + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "ARMv6-M" + +/** + * @brief Name of the architecture variant. + */ +#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__) +#define CH_CORE_VARIANT_NAME "Cortex-M0" +#elif (CORTEX_MODEL == CORTEX_M1) +#define CH_CORE_VARIANT_NAME "Cortex-M1" +#endif + +/** + * @brief Port-specific information string. + */ +#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) +#define CH_PORT_INFO "Preemption through NMI" +#else +#define CH_PORT_INFO "Preemption through PendSV" +#endif + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) + +/** + * @brief Generic ARM register. + */ +typedef void *regarm_t; + +/** + * @brief Stack and memory alignment enforcement. + * @note In this architecture the stack alignment is enforced to 64 bits, + * 32 bits alignment is supported by hardware but deprecated by ARM, + * the implementation choice is to not offer the option. + */ +typedef uint64_t stkalign_t; + + /* The documentation of the following declarations is in chconf.h in order + to not have duplicated structure names into the documentation.*/ +#if !defined(__DOXYGEN__) + +struct extctx { + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t r12; + regarm_t lr_thd; + regarm_t pc; + regarm_t xpsr; +}; + +struct intctx { + regarm_t r8; + regarm_t r9; + regarm_t r10; + regarm_t r11; + regarm_t r4; + regarm_t r5; + regarm_t r6; + regarm_t r7; + regarm_t lr; +}; + +#endif /* !defined(__DOXYGEN__) */ + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details In this port the structure just holds a pointer to the @p intctx + * structure representing the stack pointer at context switch time. + */ +struct context { + struct intctx *r13; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->r4 = (regarm_t)pf; \ + tp->p_ctx.r13->r5 = (regarm_t)arg; \ + tp->p_ctx.r13->lr = (regarm_t)_port_thread_start; \ +} + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() regarm_t _saved_lr = (regarm_t)__return_address() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr) + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_FAST_IRQ_HANDLER(id) void id(void) + +/** + * @brief Port-related initialization code. + */ +#define port_init() { \ + SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ + nvicSetSystemHandlerPriority(HANDLER_PENDSV, \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ +} + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform + * more actions. + */ +#define port_lock() __disable_irq() + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform + * more actions. + */ +#define port_unlock() __enable_irq() + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_lock_from_isr() port_lock() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_unlock_from_isr() port_unlock() + +/** + * @brief Disables all the interrupt sources. + */ +#define port_disable() __disable_irq() + +/** + * @brief Disables the interrupt sources below kernel-level priority. + */ +#define port_suspend() __disable_irq() + +/** + * @brief Enables all the interrupt sources. + */ +#define port_enable() __enable_irq() + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note Implemented as an inlined @p WFI instruction. + */ +#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() __wfi() +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) +#define port_switch(ntp, otp) _port_switch(ntp, otp) +#else +#define port_switch(ntp, otp) { \ + uint8_t *r13 = (uint8_t *)__current_sp(); \ + if ((stkalign_t *)(r13 - sizeof(struct intctx)) < otp->p_stklimit) \ + chDbgPanic("stack overflow"); \ + _port_switch(ntp, otp); \ +} +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void port_halt(void); + void _port_irq_epilogue(regarm_t lr); + void _port_switch_from_isr(void); + void _port_exit_from_isr(void); + void _port_switch(Thread *ntp, Thread *otp); + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _FROM_ASM_ */ + +#endif /* _CHCORE_V6M_H_ */ + +/** @} */ diff --git a/Project/os/ports/RVCT/ARMCMx/chcore_v7m.c b/Project/os/ports/RVCT/ARMCMx/chcore_v7m.c new file mode 100644 index 0000000..a72a95c --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/chcore_v7m.c @@ -0,0 +1,212 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file RVCT/ARMCMx/chcore_v7m.c + * @brief ARMv7-M architecture port code. + * + * @addtogroup RVCT_ARMCMx_V7M_CORE + * @{ + */ + +#include "ch.h" + +/*===========================================================================*/ +/* Port interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief System Timer vector. + * @details This interrupt is used as system tick. + * @note The timer must be initialized in the startup code. + */ +CH_IRQ_HANDLER(SysTickVector) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +/** + * @brief SVC vector. + * @details The SVC vector is used for exception mode re-entering after a + * context switch. + * @note The PendSV vector is only used in advanced kernel mode. + */ +void SVCallVector(void) { + struct extctx *ctxp; + register uint32_t psp __asm("psp"); + + /* Current PSP value.*/ + ctxp = (struct extctx *)psp; + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp++; + +#if CORTEX_USE_FPU + /* Restoring the special register SCB_FPCCR.*/ + SCB_FPCCR = (uint32_t)ctxp->fpccr; + SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx); +#endif + psp = (uint32_t)ctxp; + port_unlock_from_isr(); +} +#endif /* !CORTEX_SIMPLIFIED_PRIORITY */ + +#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +/** + * @brief PendSV vector. + * @details The PendSV vector is used for exception mode re-entering after a + * context switch. + * @note The PendSV vector is only used in compact kernel mode. + */ +void PendSVVector(void) { + struct extctx *ctxp; + register uint32_t psp __asm("psp"); + + /* Current PSP value.*/ + ctxp = (struct extctx *)psp; + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp++; + +#if CORTEX_USE_FPU + /* Restoring the special register SCB_FPCCR.*/ + SCB_FPCCR = (uint32_t)ctxp->fpccr; + SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx); +#endif + psp = (uint32_t)ctxp; +} +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/*===========================================================================*/ +/* Port exported functions. */ +/*===========================================================================*/ + +/** + * @brief Port-related initialization code. + */ +void _port_init(void) { + + /* Initialization of the vector table and priority related settings.*/ + SCB_VTOR = CORTEX_VTOR_INIT; + SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); + +#if CORTEX_USE_FPU + { + register uint32_t control __asm("control"); + register uint32_t fpscr __asm("fpscr"); + + /* Initializing the FPU context save in lazy mode.*/ + SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN; + + /* CP10 and CP11 set to full access in the startup code.*/ +/* SCB_CPACR |= 0x00F00000;*/ + + /* Enables FPU context save/restore on exception entry/exit (FPCA bit).*/ + control |= 4; + + /* FPSCR and FPDSCR initially zero.*/ + fpscr = 0; + SCB_FPDSCR = 0; + } +#endif + + /* Initialization of the system vectors used by the port.*/ + nvicSetSystemHandlerPriority(HANDLER_SVCALL, + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); + nvicSetSystemHandlerPriority(HANDLER_PENDSV, + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); +} + +/** + * @brief Exception exit redirection to _port_switch_from_isr(). + */ +void _port_irq_epilogue(void) { + + port_lock_from_isr(); + if ((SCB_ICSR & ICSR_RETTOBASE) != 0) { + struct extctx *ctxp; + register uint32_t psp __asm("psp"); + + /* Current PSP value.*/ + ctxp = (struct extctx *)psp; + + /* Adding an artificial exception return context, there is no need to + populate it fully.*/ + ctxp--; + psp = (uint32_t)ctxp; + ctxp->xpsr = (regarm_t)0x01000000; + + /* The exit sequence is different depending on if a preemption is + required or not.*/ + if (chSchIsPreemptionRequired()) { +#if CORTEX_USE_FPU + /* Triggering a lazy FPU state save.*/ + register uint32_t fpscr __asm("fpscr"); + ctxp->r0 = (regarm_t)fpscr; +#endif + /* Preemption is required we need to enforce a context switch.*/ + ctxp->pc = (regarm_t)_port_switch_from_isr; + } + else { + /* Preemption not required, we just need to exit the exception + atomically.*/ + ctxp->pc = (regarm_t)_port_exit_from_isr; + } + +#if CORTEX_USE_FPU + { + uint32_t fpccr; + + /* Saving the special register SCB_FPCCR into the reserved offset of + the Cortex-M4 exception frame.*/ + (ctxp + 1)->fpccr = (regarm_t)(fpccr = SCB_FPCCR); + + /* Now the FPCCR is modified in order to not restore the FPU status + from the artificial return context.*/ + SCB_FPCCR = fpccr | FPCCR_LSPACT; + } +#endif + + /* Note, returning without unlocking is intentional, this is done in + order to keep the rest of the context switching atomic.*/ + return; + } + port_unlock_from_isr(); +} + +/** @} */ diff --git a/Project/os/ports/RVCT/ARMCMx/chcore_v7m.h b/Project/os/ports/RVCT/ARMCMx/chcore_v7m.h new file mode 100644 index 0000000..9c71eab --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/chcore_v7m.h @@ -0,0 +1,505 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file RVCT/ARMCMx/chcore_v7m.h + * @brief ARMv7-M architecture port macros and structures. + * + * @addtogroup RVCT_ARMCMx_V7M_CORE + * @{ + */ + +#ifndef _CHCORE_V7M_H_ +#define _CHCORE_V7M_H_ + +/*===========================================================================*/ +/* Port constants. */ +/*===========================================================================*/ + +/** + * @brief Disabled value for BASEPRI register. + */ +#define CORTEX_BASEPRI_DISABLED 0 + +/*===========================================================================*/ +/* Port macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + * @note In this port it is set to 16 because the idle thread does have + * a stack frame when compiling without optimizations. You may + * reduce this value to zero when compiling with optimizations. + */ +#if !defined(PORT_IDLE_THREAD_STACK_SIZE) +#define PORT_IDLE_THREAD_STACK_SIZE 16 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * This value can be zero on those architecture where there is a + * separate interrupt stack and the stack space between @p intctx and + * @p extctx is known to be zero. + * @note In this port it is conservatively set to 32 because the function + * @p chSchDoReschedule() can have a stack frame, especially with + * compiler optimizations disabled. + */ +#if !defined(PORT_INT_REQUIRED_STACK) +#define PORT_INT_REQUIRED_STACK 32 +#endif + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#if !defined(CORTEX_ENABLE_WFI_IDLE) +#define CORTEX_ENABLE_WFI_IDLE FALSE +#endif + +/** + * @brief SYSTICK handler priority. + * @note The default SYSTICK handler priority is calculated as the priority + * level in the middle of the numeric priorities range. + */ +#if !defined(CORTEX_PRIORITY_SYSTICK) +#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) +#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) +/* If it is externally redefined then better perform a validity check on it.*/ +#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" +#endif + +/** + * @brief FPU support in context switch. + * @details Activating this option activates the FPU support in the kernel. + */ +#if !defined(CORTEX_USE_FPU) +#define CORTEX_USE_FPU CORTEX_HAS_FPU +#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU +/* This setting requires an FPU presence check in case it is externally + redefined.*/ +#error "the selected core does not have an FPU" +#endif + +/** + * @brief Simplified priority handling flag. + * @details Activating this option makes the Kernel work in compact mode. + */ +#if !defined(CORTEX_SIMPLIFIED_PRIORITY) +#define CORTEX_SIMPLIFIED_PRIORITY FALSE +#endif + +/** + * @brief SVCALL handler priority. + * @note The default SVCALL handler priority is defaulted to + * @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the + * @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts + * priority level. + */ +#if !defined(CORTEX_PRIORITY_SVCALL) +#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1) +#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL) +/* If it is externally redefined then better perform a validity check on it.*/ +#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL" +#endif + +/** + * @brief NVIC VTOR initialization expression. + */ +#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__) +#define CORTEX_VTOR_INIT 0x00000000 +#endif + +/*===========================================================================*/ +/* Port derived parameters. */ +/*===========================================================================*/ + +/** + * @brief BASEPRI level within kernel lock. + * @note In compact kernel mode this constant value is enforced to zero. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define CORTEX_BASEPRI_KERNEL \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1) +#else +#define CORTEX_BASEPRI_KERNEL 0 +#endif + +/** + * @brief PendSV priority level. + * @note This priority is enforced to be equal to @p CORTEX_BASEPRI_KERNEL, + * this handler always have the highest priority that cannot preempt + * the kernel. + */ +#define CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__) +/** + * @brief Macro defining the specific ARM architecture. + */ +#define CH_ARCHITECTURE_ARM_v7M + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "ARMv7-M" + +/** + * @brief Name of the architecture variant. + */ +#define CH_CORE_VARIANT_NAME "Cortex-M3" + +#elif (CORTEX_MODEL == CORTEX_M4) +#define CH_ARCHITECTURE_ARM_v7ME +#define CH_ARCHITECTURE_NAME "ARMv7-ME" +#if CORTEX_USE_FPU +#define CH_CORE_VARIANT_NAME "Cortex-M4F" +#else +#define CH_CORE_VARIANT_NAME "Cortex-M4" +#endif +#endif + +/** + * @brief Port-specific information string. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define CH_PORT_INFO "Advanced kernel mode" +#else +#define CH_PORT_INFO "Compact kernel mode" +#endif + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) + +/** + * @brief Generic ARM register. + */ +typedef void *regarm_t; + +/** + * @brief Stack and memory alignment enforcement. + * @note In this architecture the stack alignment is enforced to 64 bits, + * 32 bits alignment is supported by hardware but deprecated by ARM, + * the implementation choice is to not offer the option. + */ +typedef uint64_t stkalign_t; + +/* The documentation of the following declarations is in chconf.h in order + to not have duplicated structure names into the documentation.*/ +#if !defined(__DOXYGEN__) + +struct extctx { + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t r12; + regarm_t lr_thd; + regarm_t pc; + regarm_t xpsr; +#if CORTEX_USE_FPU + regarm_t s0; + regarm_t s1; + regarm_t s2; + regarm_t s3; + regarm_t s4; + regarm_t s5; + regarm_t s6; + regarm_t s7; + regarm_t s8; + regarm_t s9; + regarm_t s10; + regarm_t s11; + regarm_t s12; + regarm_t s13; + regarm_t s14; + regarm_t s15; + regarm_t fpscr; + regarm_t fpccr; +#endif /* CORTEX_USE_FPU */ +}; + +struct intctx { +#if CORTEX_USE_FPU + regarm_t s16; + regarm_t s17; + regarm_t s18; + regarm_t s19; + regarm_t s20; + regarm_t s21; + regarm_t s22; + regarm_t s23; + regarm_t s24; + regarm_t s25; + regarm_t s26; + regarm_t s27; + regarm_t s28; + regarm_t s29; + regarm_t s30; + regarm_t s31; +#endif /* CORTEX_USE_FPU */ + regarm_t r4; + regarm_t r5; + regarm_t r6; + regarm_t r7; + regarm_t r8; + regarm_t r9; + regarm_t r10; + regarm_t r11; + regarm_t lr; +}; + +#endif /* !defined(__DOXYGEN__) */ + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details In this port the structure just holds a pointer to the @p intctx + * structure representing the stack pointer at context switch time. + */ +struct context { + struct intctx *r13; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->r4 = (regarm_t)pf; \ + tp->p_ctx.r13->r5 = (regarm_t)arg; \ + tp->p_ctx.r13->lr = (regarm_t)_port_thread_start; \ +} + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() _port_irq_epilogue() + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_FAST_IRQ_HANDLER(id) void id(void) + +/** + * @brief Port-related initialization code. + */ +#define port_init() _port_init() + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform + * more actions. + * @note In this port this it raises the base priority to kernel level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define port_lock() { \ + register uint32_t basepri __asm("basepri"); \ + basepri = CORTEX_BASEPRI_KERNEL; \ +} +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_lock() __disable_irq() +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform + * more actions. + * @note In this port this it lowers the base priority to user level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define port_unlock() { \ + register uint32_t basepri __asm("basepri"); \ + basepri = CORTEX_BASEPRI_DISABLED; \ +} +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_unlock() __enable_irq() +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_lock_from_isr() port_lock() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + * @note Same as @p port_unlock() in this port. + */ +#define port_unlock_from_isr() port_unlock() + +/** + * @brief Disables all the interrupt sources. + * @note Of course non-maskable interrupt sources are not included. + * @note In this port it disables all the interrupt sources by raising + * the priority mask to level 0. + */ +#define port_disable() __disable_irq() + +/** + * @brief Disables the interrupt sources below kernel-level priority. + * @note Interrupt sources above kernel level remains enabled. + * @note In this port it raises/lowers the base priority to kernel level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define port_suspend() { \ + register uint32_t basepri __asm("basepri"); \ + basepri = CORTEX_BASEPRI_KERNEL; \ +} +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_suspend() __disable_irq() +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Enables all the interrupt sources. + * @note In this port it lowers the base priority to user level. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define port_enable() { \ + register uint32_t basepri __asm("basepri"); \ + basepri = CORTEX_BASEPRI_DISABLED; \ + __enable_irq(); \ +} +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_enable() __enable_irq() +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note Implemented as an inlined @p WFI instruction. + */ +#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() __wfi() +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) +#define port_switch(ntp, otp) _port_switch(ntp, otp) +#else +#define port_switch(ntp, otp) { \ + uint8_t *r13 = (uint8_t *)__current_sp(); \ + if ((stkalign_t *)(r13 - sizeof(struct intctx)) < otp->p_stklimit) \ + chDbgPanic("stack overflow"); \ + _port_switch(ntp, otp); \ +} +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void port_halt(void); + void _port_init(void); + void _port_irq_epilogue(void); + void _port_switch_from_isr(void); + void _port_exit_from_isr(void); + void _port_switch(Thread *ntp, Thread *otp); + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _FROM_ASM_ */ + +#endif /* _CHCORE_V7M_H_ */ + +/** @} */ diff --git a/Project/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s b/Project/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s new file mode 100644 index 0000000..2349ca2 --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s @@ -0,0 +1,115 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * Imports the Cortex-Mx configuration headers. + */ +#define _FROM_ASM_ +#include "chconf.h" +#include "chcore.h" + +CONTEXT_OFFSET EQU 12 +SCB_ICSR EQU 0xE000ED04 + + PRESERVE8 + THUMB + AREA |.text|, CODE, READONLY + + IMPORT chThdExit + IMPORT chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + IMPORT dbg_check_unlock + IMPORT dbg_check_lock +#endif + +/* + * Performs a context switch between two threads. + */ + EXPORT _port_switch +_port_switch PROC + push {r4, r5, r6, r7, lr} + mov r4, r8 + mov r5, r9 + mov r6, r10 + mov r7, r11 + push {r4, r5, r6, r7} + mov r3, sp + str r3, [r1, #CONTEXT_OFFSET] + ldr r3, [r0, #CONTEXT_OFFSET] + mov sp, r3 + pop {r4, r5, r6, r7} + mov r8, r4 + mov r9, r5 + mov r10, r6 + mov r11, r7 + pop {r4, r5, r6, r7, pc} + ENDP + +/* + * Start a thread by invoking its work function. + * If the work function returns @p chThdExit() is automatically invoked. + */ + EXPORT _port_thread_start +_port_thread_start PROC +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif + cpsie i + mov r0, r5 + blx r4 + bl chThdExit + ENDP + +/* + * Post-IRQ switch code. + * Exception handlers return here for context switching. + */ + EXPORT _port_switch_from_isr + EXPORT _port_exit_from_isr +_port_switch_from_isr PROC +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif +_port_exit_from_isr + ldr r2, =SCB_ICSR + movs r3, #128 +#if CORTEX_ALTERNATE_SWITCH + lsls r3, r3, #21 + str r3, [r2, #0] + cpsie i +#else + lsls r3, r3, #24 + str r3, [r2, #0] +#endif +waithere b waithere + ENDP + + END diff --git a/Project/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s b/Project/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s new file mode 100644 index 0000000..e91782b --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s @@ -0,0 +1,114 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * Imports the Cortex-Mx configuration headers. + */ +#define _FROM_ASM_ +#include "chconf.h" +#include "chcore.h" + +CONTEXT_OFFSET EQU 12 +SCB_ICSR EQU 0xE000ED04 +ICSR_PENDSVSET EQU 0x10000000 + + PRESERVE8 + THUMB + AREA |.text|, CODE, READONLY + + IMPORT chThdExit + IMPORT chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + IMPORT dbg_check_unlock + IMPORT dbg_check_lock +#endif + +/* + * Performs a context switch between two threads. + */ + EXPORT _port_switch +_port_switch PROC + push {r4, r5, r6, r7, r8, r9, r10, r11, lr} +#if CORTEX_USE_FPU + vpush {s16-s31} +#endif + str sp, [r1, #CONTEXT_OFFSET] + ldr sp, [r0, #CONTEXT_OFFSET] +#if CORTEX_USE_FPU + vpop {s16-s31} +#endif + pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} + ENDP + +/* + * Start a thread by invoking its work function. + * If the work function returns @p chThdExit() is automatically invoked. + */ + EXPORT _port_thread_start +_port_thread_start PROC +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif +#if CORTEX_SIMPLIFIED_PRIORITY + cpsie i +#else + movs r3, #CORTEX_BASEPRI_DISABLED + msr BASEPRI, r3 +#endif + mov r0, r5 + blx r4 + bl chThdExit + ENDP + +/* + * Post-IRQ switch code. + * Exception handlers return here for context switching. + */ + EXPORT _port_switch_from_isr + EXPORT _port_exit_from_isr +_port_switch_from_isr PROC +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif +_port_exit_from_isr +#if CORTEX_SIMPLIFIED_PRIORITY + mov r3, #SCB_ICSR :AND: 0xFFFF + movt r3, #SCB_ICSR :SHR: 16 + mov r2, #ICSR_PENDSVSET + str r2, [r3, #0] + cpsie i +waithere b waithere +#else + svc #0 +#endif + ENDP + + END diff --git a/Project/os/ports/RVCT/ARMCMx/chtypes.h b/Project/os/ports/RVCT/ARMCMx/chtypes.h new file mode 100644 index 0000000..3c71d77 --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/chtypes.h @@ -0,0 +1,87 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file RVCT/ARMCMx/chtypes.h + * @brief ARM Cortex-Mx port system types. + * + * @addtogroup RVCT_ARMCMx_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#define __need_NULL +#define __need_size_t +#define __need_ptrdiff_t +#include + +#include + +typedef int32_t bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint32_t tprio_t; /**< Thread priority. */ +typedef int32_t msg_t; /**< Inter-thread message. */ +typedef int32_t eventid_t; /**< Event Id. */ +typedef uint32_t eventmask_t; /**< Events mask. */ +typedef uint32_t systime_t; /**< System time. */ +typedef int32_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE __inline + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note Empty in this port. + */ +#define PACK_STRUCT_STRUCT + +/** + * @brief Packed structure modifier (before). + */ +#define PACK_STRUCT_BEGIN __packed + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/Project/os/ports/RVCT/ARMCMx/cstartup.s b/Project/os/ports/RVCT/ARMCMx/cstartup.s new file mode 100644 index 0000000..68aa7a6 --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/cstartup.s @@ -0,0 +1,128 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// Main Stack Configuration (IRQ Stack) +;// Main Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +;// +main_stack_size EQU 0x00000400 + +;// Process Stack Configuration +;// Process Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +;// +proc_stack_size EQU 0x00000400 + +;// C-runtime heap size +;// C-runtime heap size (in Bytes) <0x0-0xFFFFFFFF:8> +;// +heap_size EQU 0x00000400 + + AREA MSTACK, NOINIT, READWRITE, ALIGN=3 +main_stack_mem SPACE main_stack_size + EXPORT __initial_msp +__initial_msp + + AREA CSTACK, NOINIT, READWRITE, ALIGN=3 +__main_thread_stack_base__ + EXPORT __main_thread_stack_base__ +proc_stack_mem SPACE proc_stack_size + EXPORT __initial_sp +__initial_sp + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE heap_size +__heap_limit + +CONTROL_MODE_PRIVILEGED EQU 0 +CONTROL_MODE_UNPRIVILEGED EQU 1 +CONTROL_USE_MSP EQU 0 +CONTROL_USE_PSP EQU 2 + + PRESERVE8 + THUMB + + AREA |.text|, CODE, READONLY + +/* + * Reset handler. + */ + IMPORT __main + EXPORT Reset_Handler +Reset_Handler PROC + cpsid i + ldr r0, =__initial_sp + msr PSP, r0 + movs r0, #CONTROL_MODE_PRIVILEGED :OR: CONTROL_USE_PSP + msr CONTROL, r0 + isb + bl __early_init + + IF {CPU} = "Cortex-M4.fp" + LDR R0, =0xE000ED88 ; Enable CP10,CP11 + LDR R1, [R0] + ORR R1, R1, #(0xF << 20) + STR R1, [R0] + ENDIF + + ldr r0, =__main + bx r0 + ENDP + +__early_init PROC + EXPORT __early_init [WEAK] + bx lr + ENDP + + ALIGN + +/* + * User Initial Stack & Heap. + */ + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + ldr r0, =Heap_Mem + ldr r1, =(proc_stack_mem + proc_stack_size) + ldr r2, =(Heap_Mem + heap_size) + ldr r3, =proc_stack_mem + bx lr + + ALIGN + + ENDIF + + END diff --git a/Project/os/ports/RVCT/ARMCMx/port.dox b/Project/os/ports/RVCT/ARMCMx/port.dox new file mode 100644 index 0000000..5d39cf6 --- /dev/null +++ b/Project/os/ports/RVCT/ARMCMx/port.dox @@ -0,0 +1,240 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup RVCT_ARMCMx ARM Cortex-Mx + * @details ARM Cortex-Mx port for the RVCT compiler. + + * @section RVCT_ARMCMx_INTRO Introduction + * This port supports all the cores implementing the ARMv6-M and ARMv7-M + * architectures. + * + * @section RVCT_ARMCMx_MODES Kernel Modes + * The Cortex-Mx port supports two distinct kernel modes: + * - Advanced Kernel mode. In this mode the kernel only masks + * interrupt sources with priorities below or equal to the + * @p CORTEX_BASEPRI_KERNEL level. Higher priorities are not affected by + * the kernel critical sections and can be used for fast interrupts. + * This mode is not available in the ARMv6-M architecture which does not + * support priority masking. + * - Compact Kernel mode. In this mode the kernel handles IRQ priorities + * in a simplified way, all interrupt sources are disabled when the kernel + * enters into a critical zone and re-enabled on exit. This is simple and + * adequate for most applications, this mode results in a more compact and + * faster kernel. + * . + * The selection of the mode is performed using the port configuration option + * @p CORTEX_SIMPLIFIED_PRIORITY. Apart from the different handling of + * interrupts there are no other differences between the two modes. The + * kernel API is exactly the same. + * + * @section RVCT_ARMCMx_STATES_A System logical states in Compact Kernel mode + * The ChibiOS/RT logical @ref system_states are mapped as follow in Compact + * Kernel mode: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). In this state interrupts are enabled. The processor + * is running in thread-privileged mode. + * - Suspended. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. In this + * mode this state is not different from the Disabled state. + * - Disabled. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. In this + * mode this state is not different from the Suspended state. + * - Sleep. This state is entered with the execution of the specific + * instruction @p wfi. + * - S-Locked. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. + * - I-Locked. In this state the interrupt sources are globally + * disabled. The processor is running in exception-privileged mode. + * - Serving Regular Interrupt. In this state the interrupt sources are + * not globally masked but only interrupts with higher priority can preempt + * the current handler. The processor is running in exception-privileged + * mode. + * - Serving Fast Interrupt. Not implemented in compact kernel mode. + * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific + * asynchronous NMI vector and several synchronous fault vectors that can + * be considered belonging to this category. + * - Halted. Implemented as an infinite loop after globally masking all + * the maskable interrupt sources. The ARM state is whatever the processor + * was running when @p chSysHalt() was invoked. + * + * @section RVCT_ARMCMx_STATES_B System logical states in Advanced Kernel mode + * The ChibiOS/RT logical @ref system_states are mapped as follow in the + * Advanced Kernel mode: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register + * set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The + * processor is running in thread-privileged mode. + * - Suspended. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in thread-privileged mode. + * - Disabled. Interrupt sources are globally masked. The processor + * is running in thread-privileged mode. + * - Sleep. This state is entered with the execution of the specific + * instruction @p wfi. + * - S-Locked. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in thread-privileged mode. + * - I-Locked. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in exception-privileged mode. + * - Serving Regular Interrupt. In this state the interrupt sources are + * not globally masked but only interrupts with higher priority can preempt + * the current handler. The processor is running in exception-privileged + * mode. + * - Serving Fast Interrupt. Fast interrupts are defined as interrupt + * sources having higher priority level than the kernel + * (@p CORTEX_BASEPRI_KERNEL). In this state is not possible to switch to + * the I-Locked state because fast interrupts can preempt the kernel + * critical zone.
+ * This state is not implemented in the ARMv6-M implementation because + * priority masking is not present in this architecture. + * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific + * asynchronous NMI vector and several synchronous fault vectors that can + * be considered belonging to this category. + * - Halted. Implemented as an infinite loop after globally masking all + * the maskable interrupt sources. The ARM state is whatever the processor + * was running when @p chSysHalt() was invoked. + * . + * @section RVCT_ARMCMx_NOTES ARM Cortex-Mx/RVCT port notes + * The ARM Cortex-Mx port is organized as follow: + * - The @p main() function is invoked in thread-privileged mode. + * - Each thread has a private process stack, the system has a single main + * stack where all the interrupts and exceptions are processed. + * - The threads are started in thread-privileged mode. + * - Interrupt nesting and the other advanced core/NVIC features are supported. + * - The Cortex-Mx port is perfectly generic, support for more devices can be + * easily added by adding a subdirectory under ./os/ports/RVCT/ARMCMx + * and giving it the name of the new device, then copy the files from another + * device into the new directory and customize them for the new device. + * - The free uVision is not able to handle scatter files, the following + * options are required in the project options under "Preprocesso symbols" + * in order to use the unused RAM as heap automatically: + * __heap_base__=Image$$RW_IRAM1$$ZI$$Limit + * __heap_end__=Image$$RW_IRAM2$$Base + * . + * @ingroup rvct + */ + +/** + * @defgroup RVCT_ARMCMx_CONF Configuration Options + * @details ARM Cortex-Mx Configuration Options. The ARMCMx port allows some + * architecture-specific configurations settings that can be overridden + * by redefining them in @p chconf.h. Usually there is no need to change + * the default values. + * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used + * by an interrupt handler between the @p extctx and @p intctx + * structures. + * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE + * thread. Usually there is no need to change this value unless inserting + * code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro. + * - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler. + * - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler. + * - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the + * @p wfi instruction from within the idle loop. This option is + * defaulted to FALSE because it can create problems with some debuggers. + * Setting this option to TRUE reduces the system power requirements. + * . + * @section RVCT_ARMCMx_CONF_1 ARMv6-M specific options + * The following options are specific for the ARMv6-M architecture: + * - @p CORTEX_ALTERNATE_SWITCH, when activated makes the OS use the PendSV + * exception instead of NMI as preemption handler. + * . + * @section RVCT_ARMCMx_CONF_2 ARMv7-M specific options + * The following options are specific for the ARMv6-M architecture: + * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler. + * - @p CORTEX_SIMPLIFIED_PRIORITY, when enabled activates the Compact kernel + * mode. + * . + * @ingroup RVCT_ARMCMx + */ + +/** + * @defgroup RVCT_ARMCMx_CORE Core Port Implementation + * @details ARM Cortex-Mx specific port code, structures and macros. + * + * @ingroup RVCT_ARMCMx + */ + +/** + * @defgroup RVCT_ARMCMx_V6M_CORE ARMv6-M Specific Implementation + * @details ARMv6-M specific port code, structures and macros. + * + * @ingroup RVCT_ARMCMx_CORE + */ + +/** + * @defgroup RVCT_ARMCMx_V7M_CORE ARMv7-M Specific Implementation + * @details ARMv7-M specific port code, structures and macros. + * + * @ingroup RVCT_ARMCMx_CORE + */ + +/** + * @defgroup RVCT_ARMCMx_STARTUP Startup Support + * @details ChibiOS/RT provides its own generic startup file for the ARM + * Cortex-Mx port. + * Of course it is not mandatory to use it but care should be taken about the + * startup phase details. + * + * @section RVCT_ARMCMx_STARTUP_1 Startup Process + * The startup process, as implemented, is the following: + * -# Interrupts are masked globally. + * -# The two stacks are initialized by assigning them the sizes defined in + * cstartup.s file and accessible through the configuration wizard. + * -# The CPU state is switched to Privileged and the PSP stack is used. + * -# An early initialization routine @p __early_init() is invoked, if the + * symbol is not defined then an empty default routine is executed + * (weak symbol). + * -# Control is passed to the C runtime entry point @p __main that performs + * the required initializations before invoking the @p main() function. + * . + * @ingroup RVCT_ARMCMx + */ + +/** + * @defgroup RVCT_ARMCMx_NVIC NVIC Support + * @details ARM Cortex-Mx NVIC support. + * + * @ingroup RVCT_ARMCMx + */ + +/** + * @defgroup RVCT_ARMCMx_SPECIFIC Specific Implementations + * @details Platform-specific port code. + * + * @ingroup RVCT_ARMCMx + */ diff --git a/Project/os/ports/common/ARMCMx/CMSIS/include/arm_common_tables.h b/Project/os/ports/common/ARMCMx/CMSIS/include/arm_common_tables.h new file mode 100644 index 0000000..34f910f --- /dev/null +++ b/Project/os/ports/common/ARMCMx/CMSIS/include/arm_common_tables.h @@ -0,0 +1,35 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 11. November 2010 +* $Revision: V1.0.2 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern uint16_t armBitRevTable[256]; +extern q15_t armRecipTableQ15[64]; +extern q31_t armRecipTableQ31[64]; +extern const q31_t realCoefAQ31[1024]; +extern const q31_t realCoefBQ31[1024]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/Project/os/ports/common/ARMCMx/CMSIS/include/arm_math.h b/Project/os/ports/common/ARMCMx/CMSIS/include/arm_math.h new file mode 100644 index 0000000..d8901db --- /dev/null +++ b/Project/os/ports/common/ARMCMx/CMSIS/include/arm_math.h @@ -0,0 +1,7051 @@ +/* ---------------------------------------------------------------------- + * Copyright (C) 2010 ARM Limited. All rights reserved. + * + * $Date: 15. July 2011 + * $Revision: V1.0.10 + * + * Project: CMSIS DSP Library + * Title: arm_math.h + * + * Description: Public header file for CMSIS DSP Library + * + * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 + * + * Version 1.0.10 2011/7/15 + * Big Endian support added and Merged M0 and M3/M4 Source code. + * + * Version 1.0.3 2010/11/29 + * Re-organized the CMSIS folders and updated documentation. + * + * Version 1.0.2 2010/11/11 + * Documentation updated. + * + * Version 1.0.1 2010/10/05 + * Production release and review comments incorporated. + * + * Version 1.0.0 2010/09/20 + * Production release and review comments incorporated. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of modules each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Processor Support + * + * The library is completely written in C and is fully CMSIS compliant. + * High performance is achieved through maximum use of Cortex-M4 intrinsics. + * + * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor, + * with the DSP intrinsics being emulated through software. + * + * + * Toolchain Support + * + * The library has been developed and tested with MDK-ARM version 4.21. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Using the Library + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 depending on the target processor in the application. + * + * Examples + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Building the Library + * + * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\DSP_Lib\Source\ARM folder. + * - arm_cortexM0b_math.uvproj + * - arm_cortexM0l_math.uvproj + * - arm_cortexM3b_math.uvproj + * - arm_cortexM3l_math.uvproj + * - arm_cortexM4b_math.uvproj + * - arm_cortexM4l_math.uvproj + * - arm_cortexM4bf_math.uvproj + * - arm_cortexM4lf_math.uvproj + * + * Each library project have differant pre-processor macros. + * + * ARM_MATH_CMx: + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target. + * + * ARM_MATH_BIG_ENDIAN: + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * ARM_MATH_MATRIX_CHECK: + * Define macro for checking on the input and output sizes of matrices + * + * ARM_MATH_ROUNDING: + * Define macro for rounding on support functions + * + * __FPU_PRESENT: + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + * + * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above. + * + * Copyright Notice + * + * Copyright (C) 2010 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the #define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" +#else +#include "ARMCM4.h" +#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" + #include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#define PI 3.14159265358979f + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x800000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#define __SIMD32(addr) (*(int32_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +#if defined (ARM_MATH_CM0) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) + + static __INLINE uint32_t __CLZ(q31_t data); + + + static __INLINE uint32_t __CLZ(q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return(count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0) + + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0 */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (char) x; + s = (char) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (char) x; + s = (char) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t)(((short) x * (short) (y >> 16)) - + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t)(((short) x * (short) (y >> 16)) + + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) y)) + + ((short) x * (short) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + + +#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t *pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t *pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t *pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + #ifdef ARM_MATH_CM0 + q15_t A1; + q15_t A2; + #else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ + #endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; + float32_t x1; + float32_t xSpacing; + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + + /** + * @brief Processing function for the Q15 CFFT/CIFFT. + * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Initialization function for the Q15 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Processing function for the Q31 CFFT/CIFFT. + * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Initialization function for the Q31 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Processing function for the floating-point CFFT/CIFFT. + * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Initialization function for the floating-point CFFT/CIFFT. + * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + + + /*---------------------------------------------------------------------- + * Internal functions prototypes FFT function + ----------------------------------------------------------------------*/ + + /** + * @brief Core function for the floating-point CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to the twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the floating-point CIFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @param[in] onebyfftLen value of 1/fftLen. + * @return none. + */ + + void arm_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftSize length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table. + * @param[in] *pBitRevTab points to the bit reversal table. + * @return none. + */ + + void arm_bitreversal_f32( + float32_t *pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + uint16_t *pBitRevTab); + + /** + * @brief Core function for the Q31 CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_q31( + q31_t *pSrc, + uint32_t fftLen, + q31_t *pCoef, + uint32_t twidCoefModifier); + + /** + * @brief Core function for the Q31 CIFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + q31_t * pCoef, + uint32_t twidCoefModifier); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + * @param[in] *pBitRevTab points to bit reversal table. + * @return none. + */ + + void arm_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + uint16_t *pBitRevTab); + + /** + * @brief Core function for the Q15 CFFT butterfly process. + * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef16 points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_q15( + q15_t *pSrc16, + uint32_t fftLen, + q15_t *pCoef16, + uint32_t twidCoefModifier); + + /** + * @brief Core function for the Q15 CIFFT butterfly process. + * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef16 points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_inverse_q15( + q15_t *pSrc16, + uint32_t fftLen, + q15_t *pCoef16, + uint32_t twidCoefModifier); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + * @param[in] *pBitRevTab points to bit reversal table. + * @return none. + */ + + void arm_bitreversal_q15( + q15_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + uint16_t *pBitRevTab); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + /** + * @brief Processing function for the Q15 RFFT/RIFFT. + * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Initialization function for the Q15 RFFT/RIFFT. + * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Processing function for the Q31 RFFT/RIFFT. + * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Initialization function for the Q31 RFFT/RIFFT. + * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure. + * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Initialization function for the floating-point RFFT/RIFFT. + * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure. + * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Processing function for the floating-point RFFT/RIFFT. + * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t *pkCoeffs, + float32_t *pvCoeffs, + float32_t *pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t *pkCoeffs, + q31_t *pvCoeffs, + q31_t *pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t *pkCoeffs, + q15_t *pvCoeffs, + q15_t *pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t *pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t *pSinVal, + float32_t *pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t *pSinVal, + q31_t *pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + + /* Implementation of PID controller */ + + #ifdef ARM_MATH_CM0 + + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0 )* in ; + + #else + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + #endif + + #ifdef ARM_MATH_CM0 + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0] ; + acc += (q31_t) S->A2 * S->state[1] ; + + #else + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc); + + #endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (x - S->x1) / xSpacing; + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if(i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues-1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i +1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0)/(x1-x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData, + q31_t x, uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (nValues - 1)) + { + return(pYData[nValues - 1]); + } + else if(index < 0) + { + return(pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (nValues - 1)) + { + return(pYData[nValues - 1]); + } + else if(index < 0) + { + return(pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + + if(index >= (nValues - 1)) + { + return(pYData[nValues - 1]); + } + else if(index < 0) + { + return(pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + static __INLINE arm_status arm_sqrt_f32( + float32_t in, float32_t *pOut) + { + if(in > 0) + { + +// #if __FPU_USED + #if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); + #else + *pOut = sqrtf(in); + #endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, q31_t *pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, q15_t *pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1)) + { + return(0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex-1) * S->numCols ; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex-1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) + { + return(0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) + { + return(0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) + { + return(0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + + +/** + * + * End of file. + */ diff --git a/Project/os/ports/common/ARMCMx/CMSIS/include/core_cm0.h b/Project/os/ports/common/ARMCMx/CMSIS/include/core_cm0.h new file mode 100644 index 0000000..edd5221 --- /dev/null +++ b/Project/os/ports/common/ARMCMx/CMSIS/include/core_cm0.h @@ -0,0 +1,665 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + + +/** \mainpage CMSIS Cortex-M0 + + This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. + It consists of: + + - Cortex-M Core Register Definitions + - Cortex-M functions + - Cortex-M instructions + + The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease + access to the Cortex-M Core + */ + +/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions + CMSIS violates following MISRA-C2004 Rules: + + - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \defgroup CMSIS_core_definitions CMSIS Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core + - Cortex-M core Revision Number + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + /* add preprocessor checks */ +#endif + +#include /*!< standard types definitions */ +#include "core_cmInstr.h" /*!< Core Instruction Access */ +#include "core_cmFunc.h" /*!< Core Function Access */ + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*@} end of group CMSIS_core_definitions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** \defgroup CMSIS_core_register CMSIS Core Register + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE CMSIS Core + Type definitions for the Cortex-M Core Registers + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC CMSIS NVIC + Type definitions for the Cortex-M NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB CMSIS SCB + Type definitions for the Cortex-M System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick CMSIS SysTick + Type definitions for the Cortex-M System Timer Registers + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug CMSIS Core Debug + Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP + and not via processor. Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + This function enables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to enable + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + This function disables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to disable + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + This function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Number of the interrupt for get pending + \return 0 Interrupt status is not pending + \return 1 Interrupt status is pending + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + This function sets the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for set pending + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + This function clears the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for clear pending + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + This function sets the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + Note: The priority cannot be set for every core interrupt. + + \param [in] IRQn Number of the interrupt for set priority + \param [in] priority Priority to set + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + This function reads the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + The returned priority value is automatically aligned to the implemented + priority bits of the microcontroller. + + \param [in] IRQn Number of the interrupt for get priority + \return Interrupt Priority + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + This function initiate a system reset request to reset the MCU. + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + This function initialises the system tick timer and its interrupt and start the system tick timer. + Counter is in free running mode to generate periodical interrupts. + + \param [in] ticks Number of ticks between two interrupts + \return 0 Function succeeded + \return 1 Function failed + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/Project/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h b/Project/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h new file mode 100644 index 0000000..0ced2ca --- /dev/null +++ b/Project/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h @@ -0,0 +1,1244 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V2.11 + * @date 08. September 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + + +/** \mainpage CMSIS Cortex-M3 + + This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. + It consists of: + + - Cortex-M Core Register Definitions + - Cortex-M functions + - Cortex-M instructions + + The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease + access to the Cortex-M Core + */ + +/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions + CMSIS violates following MISRA-C2004 Rules: + + - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \defgroup CMSIS_core_definitions CMSIS Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core + - Cortex-M core Revision Number + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +#define __FPU_USED 0 /*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + /* add preprocessor checks */ +#endif + +#include /*!< standard types definitions */ +#include "core_cmInstr.h" /*!< Core Instruction Access */ +#include "core_cmFunc.h" /*!< Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*@} end of group CMSIS_core_definitions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** \defgroup CMSIS_core_register CMSIS Core Register + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE CMSIS Core + Type definitions for the Cortex-M Core Registers + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC CMSIS NVIC + Type definitions for the Cortex-M NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB CMSIS SCB + Type definitions for the Cortex-M System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB + Type definitions for the Cortex-M System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick CMSIS SysTick + Type definitions for the Cortex-M System Timer Registers + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM CMSIS ITM + Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ +#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU CMSIS MPU + Type definitions for the Cortex-M Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug CMSIS Core Debug + Type definitions for the Cortex-M Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions + @{ + */ + +/** \brief Set Priority Grouping + + This function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + This function gets the priority grouping from NVIC Interrupt Controller. + Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + + \return Priority grouping field + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + This function enables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to enable + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + This function disables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to disable + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + This function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Number of the interrupt for get pending + \return 0 Interrupt status is not pending + \return 1 Interrupt status is pending + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + This function sets the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for set pending + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + This function clears the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for clear pending + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + This function reads the active register in NVIC and returns the active bit. + \param [in] IRQn Number of the interrupt for get active + \return 0 Interrupt status is not active + \return 1 Interrupt status is active + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + This function sets the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + Note: The priority cannot be set for every core interrupt. + + \param [in] IRQn Number of the interrupt for set priority + \param [in] priority Priority to set + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + This function reads the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + The returned priority value is automatically aligned to the implemented + priority bits of the microcontroller. + + \param [in] IRQn Number of the interrupt for get priority + \return Interrupt Priority + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + This function encodes the priority for an interrupt with the given priority group, + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The returned priority value can be used for NVIC_SetPriority(...) function + + \param [in] PriorityGroup Used priority group + \param [in] PreemptPriority Preemptive priority value (starting from 0) + \param [in] SubPriority Sub priority value (starting from 0) + \return Encoded priority for the interrupt + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + This function decodes an interrupt priority value with the given priority group to + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The priority value can be retrieved with NVIC_GetPriority(...) function + + \param [in] Priority Priority value + \param [in] PriorityGroup Used priority group + \param [out] pPreemptPriority Preemptive priority value (starting from 0) + \param [out] pSubPriority Sub priority value (starting from 0) + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + This function initiate a system reset request to reset the MCU. + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + This function initialises the system tick timer and its interrupt and start the system tick timer. + Counter is in free running mode to generate periodical interrupts. + + \param [in] ticks Number of ticks between two interrupts + \return 0 Function succeeded + \return 1 Function failed + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** \brief ITM Send Character + + This function transmits a character via the ITM channel 0. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \param [in] ch Character to transmit + \return Character to transmit + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + This function inputs a character via external variable ITM_RxBuffer. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \return Received character + \return -1 No character received + */ +static __INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + This function checks external variable ITM_RxBuffer whether a character is available or not. + It returns '1' if a character is available and '0' if no character is available. + + \return 0 No character available + \return 1 Character available + */ +static __INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/Project/os/ports/common/ARMCMx/CMSIS/include/core_cm4.h b/Project/os/ports/common/ARMCMx/CMSIS/include/core_cm4.h new file mode 100644 index 0000000..76bf829 --- /dev/null +++ b/Project/os/ports/common/ARMCMx/CMSIS/include/core_cm4.h @@ -0,0 +1,1378 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + + +/** \mainpage CMSIS Cortex-M4 + + This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. + It consists of: + + - Cortex-M Core Register Definitions + - Cortex-M functions + - Cortex-M instructions + - Cortex-M SIMD instructions + + The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease + access to the Cortex-M Core + */ + +/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions + CMSIS violates following MISRA-C2004 Rules: + + - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \defgroup CMSIS_core_definitions CMSIS Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core + - Cortex-M core Revision Number + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + /* add preprocessor checks to define __FPU_USED */ + #define __FPU_USED 0 +#endif + +#include /*!< standard types definitions */ +#include /*!< Core Instruction Access */ +#include /*!< Core Function Access */ +#include /*!< Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*@} end of group CMSIS_core_definitions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** \defgroup CMSIS_core_register CMSIS Core Register + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE CMSIS Core + Type definitions for the Cortex-M Core Registers + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC CMSIS NVIC + Type definitions for the Cortex-M NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB CMSIS SCB + Type definitions for the Cortex-M System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB + Type definitions for the Cortex-M System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick CMSIS SysTick + Type definitions for the Cortex-M System Timer Registers + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM CMSIS ITM + Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ +#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU CMSIS MPU + Type definitions for the Cortex-M Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU CMSIS FPU + Type definitions for the Cortex-M Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug CMSIS Core Debug + Type definitions for the Cortex-M Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions + @{ + */ + +/** \brief Set Priority Grouping + + This function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + This function gets the priority grouping from NVIC Interrupt Controller. + Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + + \return Priority grouping field + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + This function enables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to enable + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + This function disables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to disable + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + This function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Number of the interrupt for get pending + \return 0 Interrupt status is not pending + \return 1 Interrupt status is pending + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + This function sets the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for set pending + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + This function clears the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for clear pending + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + This function reads the active register in NVIC and returns the active bit. + \param [in] IRQn Number of the interrupt for get active + \return 0 Interrupt status is not active + \return 1 Interrupt status is active + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + This function sets the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + Note: The priority cannot be set for every core interrupt. + + \param [in] IRQn Number of the interrupt for set priority + \param [in] priority Priority to set + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + This function reads the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + The returned priority value is automatically aligned to the implemented + priority bits of the microcontroller. + + \param [in] IRQn Number of the interrupt for get priority + \return Interrupt Priority + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + This function encodes the priority for an interrupt with the given priority group, + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The returned priority value can be used for NVIC_SetPriority(...) function + + \param [in] PriorityGroup Used priority group + \param [in] PreemptPriority Preemptive priority value (starting from 0) + \param [in] SubPriority Sub priority value (starting from 0) + \return Encoded priority for the interrupt + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + This function decodes an interrupt priority value with the given priority group to + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The priority value can be retrieved with NVIC_GetPriority(...) function + + \param [in] Priority Priority value + \param [in] PriorityGroup Used priority group + \param [out] pPreemptPriority Preemptive priority value (starting from 0) + \param [out] pSubPriority Sub priority value (starting from 0) + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + This function initiate a system reset request to reset the MCU. + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + This function initialises the system tick timer and its interrupt and start the system tick timer. + Counter is in free running mode to generate periodical interrupts. + + \param [in] ticks Number of ticks between two interrupts + \return 0 Function succeeded + \return 1 Function failed + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** \brief ITM Send Character + + This function transmits a character via the ITM channel 0. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \param [in] ch Character to transmit + \return Character to transmit + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + This function inputs a character via external variable ITM_RxBuffer. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \return Received character + \return -1 No character received + */ +static __INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + This function checks external variable ITM_RxBuffer whether a character is available or not. + It returns '1' if a character is available and '0' if no character is available. + + \return 0 No character available + \return 1 Character available + */ +static __INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/Project/os/ports/common/ARMCMx/CMSIS/include/core_cm4_simd.h b/Project/os/ports/common/ARMCMx/CMSIS/include/core_cm4_simd.h new file mode 100644 index 0000000..4791886 --- /dev/null +++ b/Project/os/ports/common/ARMCMx/CMSIS/include/core_cm4_simd.h @@ -0,0 +1,701 @@ +/**************************************************************************//** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + +/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/ +/* intrinsic __SADD8 see intrinsics.h */ +/* intrinsic __QADD8 see intrinsics.h */ +/* intrinsic __SHADD8 see intrinsics.h */ +/* intrinsic __UADD8 see intrinsics.h */ +/* intrinsic __UQADD8 see intrinsics.h */ +/* intrinsic __UHADD8 see intrinsics.h */ +/* intrinsic __SSUB8 see intrinsics.h */ +/* intrinsic __QSUB8 see intrinsics.h */ +/* intrinsic __SHSUB8 see intrinsics.h */ +/* intrinsic __USUB8 see intrinsics.h */ +/* intrinsic __UQSUB8 see intrinsics.h */ +/* intrinsic __UHSUB8 see intrinsics.h */ +/* intrinsic __SADD16 see intrinsics.h */ +/* intrinsic __QADD16 see intrinsics.h */ +/* intrinsic __SHADD16 see intrinsics.h */ +/* intrinsic __UADD16 see intrinsics.h */ +/* intrinsic __UQADD16 see intrinsics.h */ +/* intrinsic __UHADD16 see intrinsics.h */ +/* intrinsic __SSUB16 see intrinsics.h */ +/* intrinsic __QSUB16 see intrinsics.h */ +/* intrinsic __SHSUB16 see intrinsics.h */ +/* intrinsic __USUB16 see intrinsics.h */ +/* intrinsic __UQSUB16 see intrinsics.h */ +/* intrinsic __UHSUB16 see intrinsics.h */ +/* intrinsic __SASX see intrinsics.h */ +/* intrinsic __QASX see intrinsics.h */ +/* intrinsic __SHASX see intrinsics.h */ +/* intrinsic __UASX see intrinsics.h */ +/* intrinsic __UQASX see intrinsics.h */ +/* intrinsic __UHASX see intrinsics.h */ +/* intrinsic __SSAX see intrinsics.h */ +/* intrinsic __QSAX see intrinsics.h */ +/* intrinsic __SHSAX see intrinsics.h */ +/* intrinsic __USAX see intrinsics.h */ +/* intrinsic __UQSAX see intrinsics.h */ +/* intrinsic __UHSAX see intrinsics.h */ +/* intrinsic __USAD8 see intrinsics.h */ +/* intrinsic __USADA8 see intrinsics.h */ +/* intrinsic __SSAT16 see intrinsics.h */ +/* intrinsic __USAT16 see intrinsics.h */ +/* intrinsic __UXTB16 see intrinsics.h */ +/* intrinsic __SXTB16 see intrinsics.h */ +/* intrinsic __UXTAB16 see intrinsics.h */ +/* intrinsic __SXTAB16 see intrinsics.h */ +/* intrinsic __SMUAD see intrinsics.h */ +/* intrinsic __SMUADX see intrinsics.h */ +/* intrinsic __SMLAD see intrinsics.h */ +/* intrinsic __SMLADX see intrinsics.h */ +/* intrinsic __SMLALD see intrinsics.h */ +/* intrinsic __SMLALDX see intrinsics.h */ +/* intrinsic __SMUSD see intrinsics.h */ +/* intrinsic __SMUSDX see intrinsics.h */ +/* intrinsic __SMLSD see intrinsics.h */ +/* intrinsic __SMLSDX see intrinsics.h */ +/* intrinsic __SMLSLD see intrinsics.h */ +/* intrinsic __SMLSLDX see intrinsics.h */ +/* intrinsic __SEL see intrinsics.h */ +/* intrinsic __QADD see intrinsics.h */ +/* intrinsic __QSUB see intrinsics.h */ +/* intrinsic __PKHBT see intrinsics.h */ +/* intrinsic __PKHTB see intrinsics.h */ + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLALD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLALDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLSLD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLSLDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +/* not yet supported */ +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CORE_CM4_SIMD_H */ + +#ifdef __cplusplus +} +#endif diff --git a/Project/os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h b/Project/os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h new file mode 100644 index 0000000..ecf22a6 --- /dev/null +++ b/Project/os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h @@ -0,0 +1,612 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V2.10 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +static __INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +static __INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +static __INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); +#else +/* CHIBIOS FIX */ + (void)fpscr; +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/Project/os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h b/Project/os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h new file mode 100644 index 0000000..ceb4f87 --- /dev/null +++ b/Project/os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h @@ -0,0 +1,585 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +static __INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +static __INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) static __INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) static __INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) static __INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) static __INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) static __INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) static __INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) +{ + __ASM volatile ("clrex"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/Project/os/ports/common/ARMCMx/CMSIS/readme.txt b/Project/os/ports/common/ARMCMx/CMSIS/readme.txt new file mode 100644 index 0000000..6e21724 --- /dev/null +++ b/Project/os/ports/common/ARMCMx/CMSIS/readme.txt @@ -0,0 +1,6 @@ +CMSIS is Copyright (C) 2011 ARM Limited. All rights reserved. + +This directory contains only part of the CMSIS package. If you need the whole +package please download it from: + +http://www.onarm.com diff --git a/Project/os/ports/common/ARMCMx/nvic.c b/Project/os/ports/common/ARMCMx/nvic.c new file mode 100644 index 0000000..a71ca32 --- /dev/null +++ b/Project/os/ports/common/ARMCMx/nvic.c @@ -0,0 +1,81 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file common/ARMCMx/nvic.c + * @brief Cortex-Mx NVIC support code. + * + * @addtogroup COMMON_ARMCMx_NVIC + * @{ + */ + +#include "ch.h" +#include "nvic.h" + +/** + * @brief Sets the priority of an interrupt handler and enables it. + * @note The parameters are not tested for correctness. + * + * @param[in] n the interrupt number + * @param[in] prio the interrupt priority mask + */ +void nvicEnableVector(uint32_t n, uint32_t prio) { + unsigned sh = (n & 3) << 3; + + NVIC_IPR(n >> 2) = (NVIC_IPR(n >> 2) & ~(0xFF << sh)) | (prio << sh); + NVIC_ICPR(n >> 5) = 1 << (n & 0x1F); + NVIC_ISER(n >> 5) = 1 << (n & 0x1F); +} + +/** + * @brief Disables an interrupt handler. + * @note The parameters are not tested for correctness. + * + * @param[in] n the interrupt number + */ +void nvicDisableVector(uint32_t n) { + unsigned sh = (n & 3) << 3; + + NVIC_ICER(n >> 5) = 1 << (n & 0x1F); + NVIC_IPR(n >> 2) = NVIC_IPR(n >> 2) & ~(0xFF << sh); +} + +/** + * @brief Changes the priority of a system handler. + * @note The parameters are not tested for correctness. + * + * @param[in] handler the system handler number + * @param[in] prio the system handler priority mask + */ +void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio) { + unsigned sh = (handler & 3) * 8; + + SCB_SHPR(handler >> 2) = (SCB_SHPR(handler >> 2) & + ~(0xFF << sh)) | (prio << sh); +} + +/** @} */ diff --git a/Project/os/ports/common/ARMCMx/nvic.h b/Project/os/ports/common/ARMCMx/nvic.h new file mode 100644 index 0000000..729f326 --- /dev/null +++ b/Project/os/ports/common/ARMCMx/nvic.h @@ -0,0 +1,300 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file common/ARMCMx/nvic.h + * @brief Cortex-Mx NVIC support macros and structures. + * + * @addtogroup COMMON_ARMCMx_NVIC + * @{ + */ + +#ifndef _NVIC_H_ +#define _NVIC_H_ + +/** + * @name System vector numbers + * @{ + */ +#define HANDLER_MEM_MANAGE 0 /**< MEM MANAGE vector id. */ +#define HANDLER_BUS_FAULT 1 /**< BUS FAULT vector id. */ +#define HANDLER_USAGE_FAULT 2 /**< USAGE FAULT vector id. */ +#define HANDLER_RESERVED_3 3 +#define HANDLER_RESERVED_4 4 +#define HANDLER_RESERVED_5 5 +#define HANDLER_RESERVED_6 6 +#define HANDLER_SVCALL 7 /**< SVCALL vector id. */ +#define HANDLER_DEBUG_MONITOR 8 /**< DEBUG MONITOR vector id. */ +#define HANDLER_RESERVED_9 9 +#define HANDLER_PENDSV 10 /**< PENDSV vector id. */ +#define HANDLER_SYSTICK 11 /**< SYS TCK vector id. */ +/** @} */ + +typedef volatile uint8_t IOREG8; /**< 8 bits I/O register type. */ +typedef volatile uint32_t IOREG32; /**< 32 bits I/O register type. */ + +/** + * @brief NVIC ITCR register. + */ +#define NVIC_ITCR (*((IOREG32 *)0xE000E004U)) + +/** + * @brief Structure representing the SYSTICK I/O space. + */ +typedef struct { + IOREG32 CSR; + IOREG32 RVR; + IOREG32 CVR; + IOREG32 CBVR; +} CMx_ST; + +/** + * @brief SYSTICK peripheral base address. + */ +#define STBase ((CMx_ST *)0xE000E010U) +#define ST_CSR (STBase->CSR) +#define ST_RVR (STBase->RVR) +#define ST_CVR (STBase->CVR) +#define ST_CBVR (STBase->CBVR) + +#define CSR_ENABLE_MASK (0x1U << 0) +#define ENABLE_OFF_BITS (0U << 0) +#define ENABLE_ON_BITS (1U << 0) +#define CSR_TICKINT_MASK (0x1U << 1) +#define TICKINT_DISABLED_BITS (0U << 1) +#define TICKINT_ENABLED_BITS (1U << 1) +#define CSR_CLKSOURCE_MASK (0x1U << 2) +#define CLKSOURCE_EXT_BITS (0U << 2) +#define CLKSOURCE_CORE_BITS (1U << 2) +#define CSR_COUNTFLAG_MASK (0x1U << 16) + +#define RVR_RELOAD_MASK (0xFFFFFFU << 0) + +#define CVR_CURRENT_MASK (0xFFFFFFU << 0) + +#define CBVR_TENMS_MASK (0xFFFFFFU << 0) +#define CBVR_SKEW_MASK (0x1U << 30) +#define CBVR_NOREF_MASK (0x1U << 31) + +/** + * @brief Structure representing the NVIC I/O space. + */ +typedef struct { + IOREG32 ISER[8]; + IOREG32 unused1[24]; + IOREG32 ICER[8]; + IOREG32 unused2[24]; + IOREG32 ISPR[8]; + IOREG32 unused3[24]; + IOREG32 ICPR[8]; + IOREG32 unused4[24]; + IOREG32 IABR[8]; + IOREG32 unused5[56]; + IOREG32 IPR[60]; + IOREG32 unused6[644]; + IOREG32 STIR; +} CMx_NVIC; + +/** + * @brief NVIC peripheral base address. + */ +#define NVICBase ((CMx_NVIC *)0xE000E100U) +#define NVIC_ISER(n) (NVICBase->ISER[n]) +#define NVIC_ICER(n) (NVICBase->ICER[n]) +#define NVIC_ISPR(n) (NVICBase->ISPR[n]) +#define NVIC_ICPR(n) (NVICBase->ICPR[n]) +#define NVIC_IABR(n) (NVICBase->IABR[n]) +#define NVIC_IPR(n) (NVICBase->IPR[n]) +#define NVIC_STIR (NVICBase->STIR) + +/** + * @brief Structure representing the System Control Block I/O space. + */ +typedef struct { + IOREG32 CPUID; + IOREG32 ICSR; + IOREG32 VTOR; + IOREG32 AIRCR; + IOREG32 SCR; + IOREG32 CCR; + IOREG32 SHPR[3]; + IOREG32 SHCSR; + IOREG32 CFSR; + IOREG32 HFSR; + IOREG32 DFSR; + IOREG32 MMFAR; + IOREG32 BFAR; + IOREG32 AFSR; + IOREG32 PFR[2]; + IOREG32 DFR; + IOREG32 ADR; + IOREG32 MMFR[4]; + IOREG32 SAR[5]; + IOREG32 unused1[5]; + IOREG32 CPACR; +} CMx_SCB; + +/** + * @brief SCB peripheral base address. + */ +#define SCBBase ((CMx_SCB *)0xE000ED00U) +#define SCB_CPUID (SCBBase->CPUID) +#define SCB_ICSR (SCBBase->ICSR) +#define SCB_VTOR (SCBBase->VTOR) +#define SCB_AIRCR (SCBBase->AIRCR) +#define SCB_SCR (SCBBase->SCR) +#define SCB_CCR (SCBBase->CCR) +#define SCB_SHPR(n) (SCBBase->SHPR[n]) +#define SCB_SHCSR (SCBBase->SHCSR) +#define SCB_CFSR (SCBBase->CFSR) +#define SCB_HFSR (SCBBase->HFSR) +#define SCB_DFSR (SCBBase->DFSR) +#define SCB_MMFAR (SCBBase->MMFAR) +#define SCB_BFAR (SCBBase->BFAR) +#define SCB_AFSR (SCBBase->AFSR) +#define SCB_PFR(n) (SCBBase->PFR[n]) +#define SCB_DFR (SCBBase->DFR) +#define SCB_ADR (SCBBase->ADR) +#define SCB_MMFR(n) (SCBBase->MMFR[n]) +#define SCB_SAR(n) (SCBBase->SAR[n]) +#define SCB_CPACR (SCBBase->CPACR) + +#define ICSR_VECTACTIVE_MASK (0x1FFU << 0) +#define ICSR_RETTOBASE (0x1U << 11) +#define ICSR_VECTPENDING_MASK (0x1FFU << 12) +#define ICSR_ISRPENDING (0x1U << 22) +#define ICSR_ISRPREEMPT (0x1U << 23) +#define ICSR_PENDSTCLR (0x1U << 25) +#define ICSR_PENDSTSET (0x1U << 26) +#define ICSR_PENDSVCLR (0x1U << 27) +#define ICSR_PENDSVSET (0x1U << 28) +#define ICSR_NMIPENDSET (0x1U << 31) + +#define AIRCR_VECTKEY 0x05FA0000U +#define AIRCR_PRIGROUP_MASK (0x7U << 8) +#define AIRCR_PRIGROUP(n) ((n##U) << 8) + +/** + * @brief Structure representing the FPU I/O space. + */ +typedef struct { + IOREG32 unused1[1]; + IOREG32 FPCCR; + IOREG32 FPCAR; + IOREG32 FPDSCR; + IOREG32 MVFR0; + IOREG32 MVFR1; +} CMx_FPU; + +/** + * @brief FPU peripheral base address. + */ +#define FPUBase ((CMx_FPU *)0xE000EF30U) +#define SCB_FPCCR (FPUBase->FPCCR) +#define SCB_FPCAR (FPUBase->FPCAR) +#define SCB_FPDSCR (FPUBase->FPDSCR) +#define SCB_MVFR0 (FPUBase->MVFR0) +#define SCB_MVFR1 (FPUBase->MVFR1) + +#define FPCCR_ASPEN (0x1U << 31) +#define FPCCR_LSPEN (0x1U << 30) +#define FPCCR_MONRDY (0x1U << 8) +#define FPCCR_BFRDY (0x1U << 6) +#define FPCCR_MMRDY (0x1U << 5) +#define FPCCR_HFRDY (0x1U << 4) +#define FPCCR_THREAD (0x1U << 3) +#define FPCCR_USER (0x1U << 1) +#define FPCCR_LSPACT (0x1U << 0) + +#define FPDSCR_AHP (0x1U << 26) +#define FPDSCR_DN (0x1U << 25) +#define FPDSCR_FZ (0x1U << 24) +#define FPDSCR_RMODE(n) ((n##U) << 22) + +/** + * @brief Structure representing the SCS I/O space. + */ +typedef struct { + IOREG32 DHCSR; + IOREG32 DCRSR; + IOREG32 DCRDR; + IOREG32 DEMCR; +} CMx_SCS; + +/** + * @brief SCS peripheral base address. + */ +#define SCSBase ((CMx_SCS *)0xE000EDF0U) +#define SCS_DHCSR (SCSBase->DHCSR) +#define SCS_DCRSR (SCSBase->DCRSR) +#define SCS_DCRDR (SCSBase->DCRDR) +#define SCS_DEMCR (SCSBase->DEMCR) + +#define SCS_DEMCR_TRCENA (0x1U << 24) + +/** + * @brief Structure representing the DWT I/O space. + */ +typedef struct { + IOREG32 CTRL; + IOREG32 CYCCNT; + IOREG32 CPICNT; + IOREG32 EXCCNT; + IOREG32 SLEEPCNT; + IOREG32 LSUCNT; + IOREG32 FOLDCNT; + IOREG32 PCSR; +} CMx_DWT; + +/** + * @brief DWT peripheral base address. + */ +#define DWTBase ((CMx_DWT *)0xE0001000U) +#define DWT_CTRL (DWTBase->CTRL) +#define DWT_CYCCNT (DWTBase->CYCCNT) +#define DWT_CPICNT (DWTBase->CPICNT) +#define DWT_EXCCNT (DWTBase->EXCCNT) +#define DWT_SLEEPCNT (DWTBase->SLEEPCNT) +#define DWT_LSUCNT (DWTBase->LSUCNT) +#define DWT_FOLDCNT (DWTBase->FOLDCNT) +#define DWT_PCSR (DWTBase->PCSR) + +#define DWT_CTRL_CYCCNTENA (0x1U << 0) + +#ifdef __cplusplus +extern "C" { +#endif + void nvicEnableVector(uint32_t n, uint32_t prio); + void nvicDisableVector(uint32_t n); + void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio); +#ifdef __cplusplus +} +#endif + +#endif /* _NVIC_H_ */ + +/** @} */ diff --git a/Project/os/ports/cosmic/STM8/chcore.c b/Project/os/ports/cosmic/STM8/chcore.c new file mode 100644 index 0000000..882dba1 --- /dev/null +++ b/Project/os/ports/cosmic/STM8/chcore.c @@ -0,0 +1,78 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file cosmic/STM8/chcore.c + * @brief STM8 (Cosmic) architecture port code. + * + * @addtogroup STM8_COSMIC_CORE + * @{ + */ + +#include "ch.h" + +@tiny ReadyList rlist; + +/** + * @brief Performs a context switch between two threads. + * + * @param otp the thread to be switched out + */ +void _port_switch(Thread *otp) { + + _asm(" xref _rlist \n" + " ldw y,sp \n" + " ldw (5,x),y \n" + " ldw x,_rlist+5 \n" + " ldw x,(5,x) \n" + " ldw sp,x \n", otp); +} + +/** + * @brief Thread start code. + */ +void _port_thread_start(void) { + + chSysUnlock(); + _asm(" popw x \n"); +} + +/** + * @brief Halts the system. + * @details This function is invoked by the operating system when an + * unrecoverable error is detected (for example because a programming + * error in the application code that triggers an assertion while in + * debug mode). + */ +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** @} */ diff --git a/Project/os/ports/cosmic/STM8/chcore.h b/Project/os/ports/cosmic/STM8/chcore.h new file mode 100644 index 0000000..b65829e --- /dev/null +++ b/Project/os/ports/cosmic/STM8/chcore.h @@ -0,0 +1,339 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file cosmic/STM8/chcore.h + * @brief STM8 (Cosmic) architecture port macros and structures. + * + * @addtogroup STM8_COSMIC_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +#if CH_DBG_ENABLE_STACK_CHECK +#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port" +#endif + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#ifndef STM8_ENABLE_WFI_IDLE +#define STM8_ENABLE_WFI_IDLE FALSE +#endif + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +/** + * @brief Unique macro for the implemented architecture. + */ +#define CH_ARCHITECTURE_STM8 + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "STM8" + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "Cosmic" + +/** + * @brief Port-specific information string. + */ +#define CH_PORT_INFO "None" + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +/** + * @brief Base type for stack alignment. + * @note No alignment constraints so uint8_t. + */ +typedef uint8_t stkalign_t; + +/** + * @brief Generic STM8 function pointer. + * @note It is used to allocate the proper size for return addresses in + * context-related structures. + */ +typedef void (*stm8func_t)(void); + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + * @note The structure requires one dummy field at its start because the + * stack is handled as preincremented/postdecremented. + */ +struct extctx { + uint8_t _next; + uint8_t c_lreg[4]; + uint8_t c_y[3]; + uint8_t c_x[3]; + uint8_t cc; + uint8_t a; + uint16_t x; + uint16_t y; + uint8_t pce; + uint8_t pch; + uint8_t pcl; +}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching.. + * @note The structure requires one dummy field at its start because the + * stack is handled as preincremented/postdecremented. + */ +struct intctx { + uint8_t _next; + stm8func_t pc; /* Function pointer sized return address. */ +}; + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details This structure usually contains just the saved stack pointer + * defined as a pointer to a @p intctx structure. + */ +struct context { + struct intctx *sp; +}; + +/** + * @brief Start context. + * @details This context is the stack organization for the trampoline code + * @p _port_thread_start(). + */ +struct stm8_startctx { + uint8_t _next; + stm8func_t ts; /* Trampoline address. */ + void *arg; /* Thread argument. */ + stm8func_t pc; /* Thread function address. */ + stm8func_t ret; /* chThdExit() address. */ +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + struct stm8_startctx *scp; \ + scp = (struct stm8_startctx *)((uint8_t *)workspace + wsize - \ + sizeof(struct stm8_startctx)); \ + scp->ts = _port_thread_start; \ + scp->arg = arg; \ + scp->pc = (stm8func_t)pf; \ + scp->ret = (stm8func_t)chThdExit; \ + tp->p_ctx.sp = (struct intctx *)scp; \ +} + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + */ +#ifndef PORT_IDLE_THREAD_STACK_SIZE +#define PORT_IDLE_THREAD_STACK_SIZE 0 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This is a safe value, you may trim it down after reading the + * right size in the map file. + */ +#ifndef PORT_INT_REQUIRED_STACK +#define PORT_INT_REQUIRED_STACK 48 +#endif + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + (sizeof(struct intctx) - 1) + \ + (sizeof(struct extctx) - 1) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() { \ + dbg_check_lock(); \ + if (chSchIsPreemptionRequired()) \ + chSchDoReschedule(); \ + dbg_check_unlock(); \ +} + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) @far @interrupt @svlreg void vector##id(void) + +/** + * @brief Port-related initialization code. + * @note None in this port. + */ +#define port_init() + +/** + * @brief Kernel-lock action. + * @note Implemented as global interrupts disable. + */ +#define port_lock() _asm("sim") + +/** + * @brief Kernel-unlock action. + * @note Implemented as global interrupts enable. + */ +#define port_unlock() _asm("rim") + +/** + * @brief Kernel-lock action from an interrupt handler. + * @note This function is empty in this port. + */ +#define port_lock_from_isr() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @note This function is empty in this port. + */ +#define port_unlock_from_isr() + +/** + * @brief Disables all the interrupt sources. + * @note Implemented as global interrupts disable. + * @note Of course non-maskable interrupt sources are not included. + */ +#define port_disable() _asm("sim") + +/** + * @brief Disables the interrupt sources that are not supposed to preempt + * the kernel. + * @note Same as @p port_disable() in this port, there is no difference + * between the two states. + */ +#define port_suspend() _asm("sim") + +/** + * @brief Enables all the interrupt sources. + * @note Implemented as global interrupt enable. + */ +#define port_enable() _asm("rim") + +/** + * @brief Enters an architecture-dependent halt mode. + * @note Implemented with the specific "wfi" instruction. + */ +#if STM8_ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() _asm("wfi") +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note Implemented as a call to a low level assembler routine. + * + * @param ntp the thread to be switched in + * @param otp the thread to be switched out + */ +#define port_switch(ntp, otp) _port_switch(otp) + +#ifdef __cplusplus +extern "C" { +#endif + void _port_switch(Thread *otp); + void _port_thread_start(void); + void port_halt(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Scheduler captured code. */ +/*===========================================================================*/ + +#define PORT_OPTIMIZED_RLIST_VAR +#define PORT_OPTIMIZED_RLIST_EXT +#define PORT_OPTIMIZED_READYLIST_STRUCT + +typedef struct { + ThreadsQueue r_queue; + tprio_t r_prio; + Thread *r_current; +#if CH_USE_REGISTRY + Thread *r_newer; + Thread *r_older; +#endif + /* End of the fields shared with the Thread structure.*/ +#if CH_TIME_QUANTUM > 0 + cnt_t r_preempt; +#endif +} ReadyList; + +@tiny extern ReadyList rlist; + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/Project/os/ports/cosmic/STM8/chtypes.h b/Project/os/ports/cosmic/STM8/chtypes.h new file mode 100644 index 0000000..ab7b021 --- /dev/null +++ b/Project/os/ports/cosmic/STM8/chtypes.h @@ -0,0 +1,138 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file cosmic/STM8/chtypes.h + * @brief STM8 (Cosmic) port system types. + * + * @addtogroup STM8_COSMIC_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#define __need_NULL +#define __need_size_t +#include + +//#if !defined(_STDINT_H) && !defined(__STDINT_H_) +//#include +//#endif + +typedef unsigned char uint8_t; /**< C99-style 8 bits unsigned. */ +typedef signed char int8_t; /**< C99-style 8 bits signed. */ +typedef unsigned int uint16_t; /**< C99-style 16 bits unsigned. */ +typedef signed int int16_t; /**< C99-style 16 bits signed. */ +typedef unsigned long uint32_t; /**< C99-style 32 bits unsigned. */ +typedef signed long int32_t; /**< C99-style 32 bits signed. */ +typedef uint8_t uint_fast8_t; /**< C99-style 8 bits unsigned. */ +typedef uint16_t uint_fast16_t; /**< C99-style 16 bits unsigned. */ +typedef uint32_t uint_fast32_t; /**< C99-style 32 bits unsigned. */ + +/** + * @brief Boolean, recommended the fastest signed. + */ +typedef int8_t bool_t; + +/** + * @brief Thread mode flags, uint8_t is ok. + */ +typedef uint8_t tmode_t; + +/** + * @brief Thread state, uint8_t is ok. + */ +typedef uint8_t tstate_t; + +/** + * @brief Thread references counter, uint8_t is ok. + */ +typedef uint8_t trefs_t; + +/** + * @brief Priority, use the fastest unsigned type. + */ +typedef uint8_t tprio_t; + +/** + * @brief Message, use signed pointer equivalent. + */ +typedef int16_t msg_t; + +/** + * @brief Event Id, use fastest signed. + */ +typedef int8_t eventid_t; + +/** + * @brief Event Mask, recommended fastest unsigned. + */ +typedef uint8_t eventmask_t; + +/** + * @brief System Time, recommended fastest unsigned. + */ +typedef uint16_t systime_t; + +/** + * @brief Counter, recommended fastest signed. + */ +typedef int8_t cnt_t; + +/** + * @brief Inline function modifier. + */ +#define INLINE @inline + +/** + * @brief ROM constant modifier. + * @note Uses the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note Empty in this port. + */ +#define PACK_STRUCT_STRUCT + +/** + * @brief Packed structure modifier (before). + * @note Empty in this port. + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/Project/os/ports/cosmic/STM8/port.dox b/Project/os/ports/cosmic/STM8/port.dox new file mode 100644 index 0000000..ec396a2 --- /dev/null +++ b/Project/os/ports/cosmic/STM8/port.dox @@ -0,0 +1,102 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup STM8_COSMIC STM8 + * @details STM8 port for the Cosmic C compiler. + * + * @section STM8_COSMIC_INTRO Introduction + * This port supports all STM8 8 bits MCUs. + * + * @section STM8_COSMIC_STATES Mapping of the System States in the STM8 port + * The ChibiOS/RT logical @ref system_states are mapped as follow in the STM8 + * port: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). Interrupts are enabled. + * - Suspended. Interrupts are disabled. + * - Disabled. Interrupts are disabled. This state is equivalent to the + * Suspended state because there are no fast interrupts in this architecture. + * - Sleep. Implemented with "wait" instruction insertion in the idle + * loop. + * - S-Locked. Interrupts are disabled. + * - I-Locked. This state is equivalent to the SRI state, the + * @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in + * order to formally change state because this may change). + * - Serving Regular Interrupt. Normal interrupt service code. + * - Serving Fast Interrupt. Not present in this architecture. + * - Serving Non-Maskable Interrupt. The STM8 ha non + * maskable interrupt sources that can be associated to this state. + * - Halted. Implemented as an infinite loop with interrupts disabled. + * . + * @section STM8_COSMIC_NOTES The STM8 port notes + * - The STM8 does not have a dedicated interrupt stack, make sure to reserve + * enough stack space for interrupts in each thread stack. This can be done + * by modifying the @p INT_REQUIRED_STACK macro into + * ./os/ports/cosmic/STM8/chcore.h. + * - The kernel currently supports only the small memory model so the + * kernel files should be loaded in the first 64K. Note that this is not + * a problem because upper addresses can be used by the user code, the + * kernel can context switch code running there. + * - The configuration option @p CH_OPTIMIZE_SPEED is not currently supported + * because the missing support of the @p inline "C" keyword in the + * compiler. + * . + * @ingroup cosmic + */ + +/** + * @defgroup STM8_COSMIC_CONF Configuration Options + * @details STM8 Configuration Options. The STM8 port allows some + * architecture-specific configurations settings that can be overridden + * by redefining them in @p chconf.h. Usually there is no need to change + * the default values. + * - @p INT_REQUIRED_STACK, this value represent the amount of stack space + * used by the interrupt handlers.
+ * The default for this value is @p 48, this space is allocated for each + * thread so be careful in order to not waste precious RAM space. + * . + * @ingroup STM8_COSMIC + */ + +/** + * @defgroup STM8_COSMIC_CORE Core Port Implementation + * @details STM8 specific port code, structures and macros. + * + * @ingroup STM8_COSMIC + */ + + /** + * @defgroup STM8_COSMIC_STARTUP Startup Support + * @details ChibiOS/RT doed not provide startup files for the STM8, there + * are no special startup requirement so the normal toolchain-provided + * startup files can be used. + * + * @ingroup STM8_COSMIC + */ diff --git a/Project/os/ports/ports.dox b/Project/os/ports/ports.dox new file mode 100644 index 0000000..a3a63a2 --- /dev/null +++ b/Project/os/ports/ports.dox @@ -0,0 +1,67 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup ports Ports + * This section describes the technical details of the various supported + * ChibiOS/RT ports. + */ + +/** + * @defgroup gcc GCC Ports + * Ports for the GCC compiler or derivatives. + * + * @ingroup ports + */ + +/** + * @defgroup iar IAR Ports + * Ports for the IAR compiler. + * + * @ingroup ports + */ + +/** + * @defgroup rvct RVCT Ports + * Ports for the RVCT compiler. + * + * @ingroup ports + */ + +/** + * @defgroup cosmic Cosmic Compiler Ports + * Ports for the Compiler compiler. + * + * @ingroup ports + */ + +/** + * @defgroup raisonance Raisonance Compiler Ports + * Ports for the Raisonance compiler. + * + * @ingroup ports + */ diff --git a/Project/os/various/ch.cpp b/Project/os/various/ch.cpp new file mode 100644 index 0000000..61d3d84 --- /dev/null +++ b/Project/os/various/ch.cpp @@ -0,0 +1,344 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ +/** + * @file ch.cpp + * @brief C++ wrapper code. + * + * @addtogroup cpp_library + * @{ + */ + +#include "ch.hpp" + +namespace chibios_rt { + + /*------------------------------------------------------------------------* + * chibios_rt::System * + *------------------------------------------------------------------------*/ + void System::Init(void) { + + chSysInit(); + } + + void System::Lock(void) { + + chSysLock(); + } + + void System::Unlock(void) { + + chSysUnlock(); + } + + systime_t System::GetTime(void) { + + return chTimeNow(); + } + + /*------------------------------------------------------------------------* + * chibios_rt::Timer * + *------------------------------------------------------------------------*/ + void Timer::Set(systime_t time, vtfunc_t vtfunc, void *par) { + + chVTSetI(&timer, time, vtfunc, par); + } + + void Timer::Reset() { + + chVTResetI(&timer); + } + + bool Timer::IsArmed(void) { + + return chVTIsArmedI(&timer); + } + + /*------------------------------------------------------------------------* + * chibios_rt::BaseThread * + *------------------------------------------------------------------------*/ + static msg_t thdstart(void *arg) { + + return ((BaseThread *)arg)->Main(); + } + + BaseThread::BaseThread(void *workspace, size_t wsize, tprio_t prio) { + + thread_ref = chThdCreateStatic(workspace, wsize, prio, thdstart, this); + } + + void BaseThread::Exit(msg_t msg) { + + chThdExit(msg); + } + +#if CH_USE_WAITEXIT + msg_t BaseThread::Wait(void) { + + return chThdWait(thread_ref); + } +#endif /* CH_USE_WAITEXIT */ + + void BaseThread::SetPriority(tprio_t newprio) { + + chThdSetPriority(newprio); + } + + void BaseThread::Resume(void) { + + chThdResume(thread_ref); + } + + void BaseThread::Terminate(void) { + + chThdTerminate(thread_ref); + } + + void BaseThread::Sleep(systime_t n) { + + chThdSleep(n); + } + + void BaseThread::SleepUntil(systime_t time) { + + chThdSleepUntil(time); + } + +#if CH_USE_MESSAGES + msg_t BaseThread::SendMessage(::Thread* tp, msg_t msg) { + + return chMsgSend(tp, msg); + } + + msg_t BaseThread::SendMessage(msg_t msg) { + + return chMsgSend(thread_ref, msg); + } + + Thread *BaseThread::WaitMessage(void) { + + return chMsgWait(); + } + + msg_t BaseThread::GetMessage(Thread* tp) { + + return chMsgGet(tp); + } + + void BaseThread::ReleaseMessage(Thread* tp, msg_t msg) { + + chMsgRelease(tp, msg); + } + + bool BaseThread::IsPendingMessage(void) { + + return chMsgIsPendingI(currp); + } +#endif /* CH_USE_MESSAGES */ + + msg_t BaseThread::Main(void) { + + return 0; + } + +#if CH_USE_SEMAPHORES + /*------------------------------------------------------------------------* + * chibios_rt::Semaphore * + *------------------------------------------------------------------------*/ + Semaphore::Semaphore(cnt_t n) { + + chSemInit(&sem, n); + } + + void Semaphore::Reset(cnt_t n) { + + chSemReset(&sem, n); + } + + msg_t Semaphore::Wait(void) { + + return chSemWait(&sem); + } + + msg_t Semaphore::WaitTimeout(systime_t time) { + + return chSemWaitTimeout(&sem, time); + } + + void Semaphore::Signal(void) { + + chSemSignal(&sem); + } + +#if CH_USE_SEMSW + msg_t Semaphore::SignalWait(Semaphore *ssem, Semaphore *wsem) { + + return chSemSignalWait(&ssem->sem, &wsem->sem); + } +#endif /* CH_USE_SEMSW */ +#endif /* CH_USE_SEMAPHORES */ + +#if CH_USE_MUTEXES + /*------------------------------------------------------------------------* + * chibios_rt::Mutex * + *------------------------------------------------------------------------*/ + Mutex::Mutex(void) { + + chMtxInit(&mutex); + } + + bool Mutex::TryLock(void) { + + return chMtxTryLock(&mutex); + } + + void Mutex::Lock(void) { + + chMtxLock(&mutex); + } + + void Mutex::Unlock(void) { + + chMtxUnlock(); + } + + void UnlockAll(void) { + + chMtxUnlockAll(); + } + +#if CH_USE_CONDVARS + /*------------------------------------------------------------------------* + * chibios_rt::CondVar * + *------------------------------------------------------------------------*/ + CondVar::CondVar(void) { + + chCondInit(&condvar); + } + + void CondVar::Signal(void) { + + chCondSignal(&condvar); + } + + void CondVar::Broadcast(void) { + + chCondBroadcast(&condvar); + } + + msg_t CondVar::Wait(void) { + + return chCondWait(&condvar); + } + +#if CH_USE_CONDVARS_TIMEOUT + msg_t CondVar::WaitTimeout(systime_t time) { + + return chCondWaitTimeout(&condvar, time); + } +#endif /* CH_USE_CONDVARS_TIMEOUT */ +#endif /* CH_USE_CONDVARS */ +#endif /* CH_USE_MUTEXES */ + +#if CH_USE_EVENTS + /*------------------------------------------------------------------------* + * chibios_rt::Event * + *------------------------------------------------------------------------*/ + Event::Event(void) { + + chEvtInit(&event); + } + + void Event::Register(EventListener *elp, eventid_t eid) { + + chEvtRegister(&event,elp, eid); + } + + void Event::RegisterMask(EventListener *elp, eventmask_t emask) { + + chEvtRegisterMask(&event,elp, emask); + } + + void Event::Unregister(EventListener *elp) { + + chEvtUnregister(&event, elp); + } + + void Event::Broadcast(void) { + + chEvtBroadcast(&event); + } + + eventmask_t Event::ClearFlags(eventmask_t mask) { + + return chEvtClearFlags(mask); + } + + eventmask_t Event::AddFlags(eventmask_t mask) { + + return chEvtAddFlags(mask); + } + + void Event::Dispatch(const evhandler_t handlers[], eventmask_t mask) { + + chEvtDispatch(handlers, mask); + } + + eventmask_t Event::WaitOne(eventmask_t ewmask) { + + return chEvtWaitOne(ewmask); + } + + eventmask_t Event::WaitAny(eventmask_t ewmask) { + + return chEvtWaitAny(ewmask); + } + + eventmask_t Event::WaitAll(eventmask_t ewmask) { + + return chEvtWaitAll(ewmask); + } + +#if CH_USE_EVENTS_TIMEOUT + eventmask_t Event::WaitOneTimeout(eventmask_t ewmask, systime_t time) { + + return chEvtWaitOneTimeout(ewmask, time); + } + + eventmask_t Event::WaitAnyTimeout(eventmask_t ewmask, systime_t time) { + + return chEvtWaitAnyTimeout(ewmask, time); + } + + eventmask_t Event::WaitAllTimeout(eventmask_t ewmask, systime_t time) { + + return chEvtWaitAllTimeout(ewmask, time); + } +#endif /* CH_USE_EVENTS_TIMEOUT */ +#endif /* CH_USE_EVENTS */ +} + +/** @} */ diff --git a/Project/os/various/ch.hpp b/Project/os/various/ch.hpp new file mode 100644 index 0000000..763d749 --- /dev/null +++ b/Project/os/various/ch.hpp @@ -0,0 +1,646 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file ch.hpp + * @brief C++ wrapper classes and definitions. + * + * @addtogroup cpp_library + * @{ + */ + +#include + +#ifndef _CH_HPP_ +#define _CH_HPP_ + +namespace chibios_rt { + + /** + * @brief Class encapsulating the base system functionalities. + */ + class System { + public: + /** + * @brief ChibiOS/RT initialization. + * @details The system is initialized, the idle thread is spawned and the + * current instruction flow becomes the main thread with priority + * @p NORMALPRIO. + */ + static void Init(void); + + /** + * @brief Kernel lock. + * @note On some ports it is faster to invoke chSysLock() directly because + * inlining. + */ + static void Lock(void); + + /** + * @brief Kernel unlock. + * @note On some ports it is faster to invoke chSysUnlock() directly + * because inlining. + */ + static void Unlock(void); + + /** + * @brief Returns the system time as system ticks. + * @note The system tick time interval is implementation dependent. + * + * @return The system time. + */ + static systime_t GetTime(void); + }; + + /** + * @brief Timer class. + */ + class Timer { + public: + /** + * @brief Embedded @p VirtualTimer structure. + */ + struct ::VirtualTimer timer; + + /** + * @brief Starts the timer. + * @note It must be called with the interrupts disabled. + * @note The associated function is invoked by an interrupt handler. + * + * @param[in] time the time in system ticks + * @param[in] vtfunc the timer callback function + * @param[in] par the parameter for the callback function + */ + void Set(systime_t time, vtfunc_t vtfunc, void *par); + + /** + * @brief Resets the timer. + * @note It must be called with the interrupts disabled. + * @note The timer MUST be active when this function is invoked. + */ + void Reset(); + + /** + * @brief Returns the timer status. + * + * @retval TRUE The timer is armed. + * @retval FALSE The timer already fired its callback. + */ + bool IsArmed(void); + }; + + /** + * @brief Base class for a ChibiOS/RT thread. + * @details The thread body is the virtual function @p Main(). + */ + class BaseThread { + public: + /** + * @brief Pointer to the system thread. + */ + ::Thread *thread_ref; + + /** + * @brief Thread constructor. + * @details The thread object is initialized and a system thread is + * started. + * + * @param[in] workspace pointer to the workspace area + * @param[in] wsize size of the workspace area + * @param[in] prio thread priority + */ + BaseThread(void *workspace, size_t wsize, tprio_t prio); + + /** + * @brief Thread exit. + * + * @param[in] msg the exit message + */ + static void Exit(msg_t msg); + +#if CH_USE_WAITEXIT + /** + * @brief Synchronization on Thread exit. + * + * @return The exit message from the thread. + */ + msg_t Wait(void); +#endif /* CH_USE_WAITEXIT */ + + /** + * @brief Resumes the thread. + * @details The thread encapsulated into the object is resumed. + */ + void Resume(void); + + /** + * @brief Changes the thread priority. + * + * @param[in] newprio The new priority level + */ + static void SetPriority(tprio_t newprio); + + /** + * @brief Requests thread termination. + * @details A termination flag is pended on the thread, it is thread + * responsibility to detect it and exit. + */ + void Terminate(void); + + /** + * @brief Suspends the thread execution for the specified number of + * system ticks. + * + * @param[in] n the number of system ticks + */ + static void Sleep(systime_t n); + + /** + * @brief Suspends the thread execution until the specified time arrives. + * + * @param[in] time the system time + */ + static void SleepUntil(systime_t time); + +#if CH_USE_MESSAGES + /** + * @brief Sends a message to the thread and returns the answer. + * + * @param[in] tp the target thread + * @param[in] msg the sent message + * @return The returned message. + */ + static msg_t SendMessage(::Thread *tp, msg_t msg); + + /** + * @brief Sends a message to the thread and returns the answer. + * + * @param[in] msg the sent message + * @return The returned message. + */ + msg_t SendMessage(msg_t msg); + + /** + * @brief Waits for a message. + * + * @return The sebder thread. + */ + static Thread *WaitMessage(void); + + /** + * @brief Returns an enqueued message or @p NULL. + * + * @param[in] tp the sender thread + * @return The incoming message. + */ + static msg_t GetMessage(Thread* tp); + + /** + * @brief Releases the next message in queue with a reply. + * + * @param[in] tp the sender thread + * @param[in] msg the answer message + */ + static void ReleaseMessage(Thread* tp, msg_t msg); + + /** + * @brief Returns true if there is at least one message in queue. + * + * @retval TRUE A message is waiting in queue. + * @retval FALSE A message is not waiting in queue. + */ + static bool IsPendingMessage(void); +#endif /* CH_USE_MESSAGES */ + + /** + * @brief Thread body function. + * + * @return The exit message. + */ + virtual msg_t Main(void); + }; + + /** + * @brief Enhanced threads template class. + * @details This class introduces thread names and static working area + * allocation. + * + * @param N the working area size for the thread class + */ + template + class EnhancedThread : public BaseThread { + protected: + WORKING_AREA(wa, N); // Thread working area. + + public: + /** + * @brief The thread name. + */ + const char *name; + + /** + * @brief Full constructor. + * @details This constructor allows to set a priority level for the new + * thread. + * + * @param[in] tname the name to be assigned to the thread + * @param[in] prio the priority to be assigned to the thread + */ + EnhancedThread(const char *tname, tprio_t prio) : + BaseThread(wa, sizeof wa, prio) { + + name = tname; + } + + /** + * @brief Simplified constructor. + * @details This constructor allows to create a thread by simply + * specifying a name. In is assumed @p NORMALPRIO as initial + * priority. + * + * @param[in] tname the name to be assigned to the thread + */ + EnhancedThread(const char *tname) : + BaseThread(wa, sizeof wa, NORMALPRIO) { + + name = tname; + } + }; + +#if CH_USE_SEMAPHORES + /** + * @brief Class encapsulating a semaphore. + */ + class Semaphore { + public: + /** + * @brief Embedded @p ::Semaphore structure. + */ + struct ::Semaphore sem; + + /** + * @brief Semaphore constructor. + * @details The embedded @p ::Semaphore structure is initialized. + * + * @param[in] n the semaphore counter value, must be greater + * or equal to zero + */ + Semaphore(cnt_t n); + + /** + * @brief Resets a semaphore. + * + * @param[in] n the new semaphore counter value, must be + * greater or equal to zero + */ + void Reset(cnt_t n); + + /** + * @brief Wait operation on the semaphore. + * + * @retval RDY_OK if the semaphore was signaled or not taken. + * @retval RDY_RESET if the semaphore was reset. + */ + msg_t Wait(void); + + /** + * @brief Wait operation on the semaphore with timeout. + * + * @param[in] time the number of ticks before the operation fails + * @retval RDY_OK if the semaphore was signaled or not taken. + * @retval RDY_RESET if the semaphore was reset. + * @retval RDY_TIMEOUT if the semaphore was not signaled or reset + * within the specified timeout. + */ + msg_t WaitTimeout(systime_t time); + + /** + * @brief Signal operation on the semaphore. + * @details The semaphore is signaled, the next thread in queue, if any, + * is awakened. + */ + void Signal(void); + +#if CH_USE_SEMSW + /** + * @brief Atomic signal and wait operations. + * + * @param[in] ssem pointer to a @p Semaphore to be signaled + * @param[in] wsem pointer to a @p Semaphore to be wait on + * @retval RDY_OK if the semaphore was signaled or not taken. + * @retval RDY_RESET if the semaphore was reset. + */ + static msg_t SignalWait(Semaphore *ssem, Semaphore *wsem); +#endif /* CH_USE_SEMSW */ + }; +#endif /* CH_USE_SEMAPHORES */ + +#if CH_USE_MUTEXES + /** + * @brief Class encapsulating a mutex. + */ + class Mutex { + public: + /** + * @brief Embedded @p ::Mutex structure. + */ + struct ::Mutex mutex; + + /** + * @brief Mutex constructor. + * @details The embedded @p ::Mutex structure is initialized. + */ + Mutex(void); + + /** + * @brief Tries a lock operation on the mutex. + * + * @retval TRUE if the mutex was successfully acquired + * @retval FALSE if the lock attempt failed. + */ + bool TryLock(void); + + /** + * @brief Locks the mutex. + * @details Performs a lock operation on the mutex, if the mutex is + * already locked then the thread enters the mutex priority + * queue and waits. + */ + void Lock(void); + + /** + * @brief Unlocks the mutex. + * @details Performs an unlock operation on the mutex, the next waiting + * thread, if any, is resumed and locks the mutex. + */ + static void Unlock(void); + + /** + * @brief Unlocks all the mutexes owned by the invoking thread. + * @details This operation is MUCH MORE efficient than releasing + * the mutexes one by one and not just because the call overhead, + * this function does not have any overhead related to the + * priority inheritance mechanism. + */ + static void UnlockAll(void); + }; + +#if CH_USE_CONDVARS + /** + * @brief Class encapsulating a conditional variable. + */ + class CondVar { + public: + /** + * @brief Embedded @p ::CondVar structure. + */ + struct ::CondVar condvar; + + /** + * @brief CondVar constructor. + * @details The embedded @p ::CondVar structure is initialized. + */ + CondVar(void); + + /** + * @brief Signals the CondVar. + * @details The next thread waiting on the @p CondVar, if any, is awakened. + */ + void Signal(void); + + /** + * @brief Broadcasts the CondVar. + * @details All the threads waiting on the @p CondVar, if any, are awakened. + */ + void Broadcast(void); + + /** + * @brief Waits on the CondVar while releasing the controlling mutex. + * + * @return The wakep mode. + * @retval RDY_OK if the condvar was signaled using + * @p chCondSignal(). + * @retval RDY_RESET if the condvar was signaled using + * @p chCondBroadcast(). + */ + msg_t Wait(void); + +#if CH_USE_CONDVARS_TIMEOUT + /** + * @brief Waits on the CondVar while releasing the controlling mutex. + * + * @param[in] time the number of ticks before the operation fails + * @return The wakep mode. + * @retval RDY_OK if the condvar was signaled using + * @p chCondSignal(). + * @retval RDY_RESET if the condvar was signaled using + * @p chCondBroadcast(). + * @retval RDY_TIMEOUT if the condvar was not signaled within the + * specified timeout. + */ + msg_t WaitTimeout(systime_t time); +#endif /* CH_USE_CONDVARS_TIMEOUT */ + }; +#endif /* CH_USE_CONDVARS */ +#endif /* CH_USE_MUTEXES */ + +#if CH_USE_EVENTS + /** + * @brief Class encapsulating an event source. + */ + class Event { + public: + /** + * @brief Embedded @p ::EventSource structure. + */ + struct ::EventSource event; + + /** + * @brief Event constructor. + * @details The embedded @p ::EventSource structure is initialized. + */ + Event(void); + + /** + * @brief Registers a listener on the event source. + * + * @param[in] elp pointer to the @p EventListener structure + * @param[in] eid numeric identifier assigned to the Event + * Listener + */ + void Register(EventListener *elp, eventid_t eid); + + /** + * @brief Registers an Event Listener on an Event Source. + * @note Multiple Event Listeners can specify the same bits to be added. + * + * @param[in] elp pointer to the @p EventListener structure + * @param[in] emask the mask of event flags to be pended to the + * thread when the event source is broadcasted + */ + void RegisterMask(EventListener *elp, eventmask_t emask); + + /** + * @brief Unregisters a listener. + * @details The specified listeners is no more signaled by the event + * source. + * + * @param[in] elp the listener to be unregistered + */ + void Unregister(EventListener *elp); + + /** + * @brief Broadcasts an event. + * @details All the listeners registered on the event source are signaled. + */ + void Broadcast(void); + + /** + * @brief Clears specified events from the pending events mask. + * + * @param[in] mask the events to be cleared + * @return The pending events that were cleared. + */ + static eventmask_t ClearFlags(eventmask_t mask); + + /** + * @brief Makes an events mask pending in the current thread. + * @details This functon is @b much faster than using @p Broadcast(). + * + * @param[in] mask the events to be pended + * @return The current pending events mask. + */ + static eventmask_t AddFlags(eventmask_t mask); + + /** + * @brief Invokes the event handlers associated with a mask. + * + * @param[in] mask mask of the events to be dispatched + * @param[in] handlers an array of @p evhandler_t. The array must be + * have indexes from zero up the higher registered + * event identifier. + */ + static void Dispatch(const evhandler_t handlers[], eventmask_t mask); + + /** + * @brief Waits for a single event. + * @details A pending event among those specified in @p ewmask is selected, + * cleared and its mask returned. + * @note One and only one event is served in the function, the one with + * the lowest event id. The function is meant to be invoked into + * a loop in order to serve all the pending events.
+ * This means that Event Listeners with a lower event identifier + * have an higher priority. + * + * @param[in] ewmask mask of the events that the function should + * wait for, @p ALL_EVENTS enables all the events + * @return The mask of the lowest id served and cleared + * event. + */ + static eventmask_t WaitOne(eventmask_t ewmask); + + /** + * @brief Waits for any of the specified events. + * @details The function waits for any event among those specified in + * @p ewmask to become pending then the events are cleared and + * returned. + * + * @param[in] ewmask mask of the events that the function should + * wait for, @p ALL_EVENTS enables all the events + * @return The mask of the served and cleared events. + */ + static eventmask_t WaitAny(eventmask_t ewmask); + + /** + * @brief Waits for all the specified event flags then clears them. + * @details The function waits for all the events specified in @p ewmask + * to become pending then the events are cleared and returned. + * + * @param[in] ewmask mask of the event ids that the function should + * wait for + * @return The mask of the served and cleared events. + */ + static eventmask_t WaitAll(eventmask_t ewmask); + +#if CH_USE_EVENTS_TIMEOUT + /** + * @brief Waits for a single event. + * @details A pending event among those specified in @p ewmask is selected, + * cleared and its mask returned. + * @note One and only one event is served in the function, the one with + * the lowest event id. The function is meant to be invoked into + * a loop in order to serve all the pending events.
+ * This means that Event Listeners with a lower event identifier + * have an higher priority. + * + * @param[in] ewmask mask of the events that the function should + * wait for, @p ALL_EVENTS enables all the events + * + * @param[in] time the number of ticks before the operation timouts + * @return The mask of the lowest id served and cleared + * event. + * @retval 0 if the specified timeout expired. + */ + static eventmask_t WaitOneTimeout(eventmask_t ewmask, systime_t time); + + /** + * @brief Waits for any of the specified events. + * @details The function waits for any event among those specified in + * @p ewmask to become pending then the events are cleared and + * returned. + * + * @param[in] ewmask mask of the events that the function should + * wait for, @p ALL_EVENTS enables all the events + * @param[in] time the number of ticks before the operation + * timouts + * @return The mask of the served and cleared events. + * @retval 0 if the specified timeout expired. + */ + static eventmask_t WaitAnyTimeout(eventmask_t ewmask, systime_t time); + + /** + * @brief Waits for all the specified event flags then clears them. + * @details The function waits for all the events specified in @p ewmask + * to become pending then the events are cleared and returned. + * + * @param[in] ewmask mask of the event ids that the function should + * wait for + * @param[in] time the number of ticks before the operation + * timouts + * @return The mask of the served and cleared events. + * @retval 0 if the specified timeout expired. + */ + static eventmask_t WaitAllTimeout(eventmask_t ewmask, systime_t time); + +#endif /* CH_USE_EVENTS_TIMEOUT */ + }; +#endif /* CH_USE_EVENTS */ +} + +#endif /* _CH_HPP_ */ + +/** @} */ diff --git a/Project/os/various/chprintf.c b/Project/os/various/chprintf.c new file mode 100644 index 0000000..1852088 --- /dev/null +++ b/Project/os/various/chprintf.c @@ -0,0 +1,224 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chprintf.c + * @brief Mini printf-like functionality. + * + * @addtogroup chprintf + * @{ + */ + +#include + +#include "ch.h" + +#define MAX_FILLER 11 + +static char *ltoa(char *p, long num, unsigned radix) { + int i; + char *q; + + q = p + MAX_FILLER; + do { + i = (int)(num % radix); + i += '0'; + if (i > '9') + i += 'A' - '0' - 10; + *--q = i; + } while ((num /= radix) != 0); + + i = (int)(p + MAX_FILLER - q); + do + *p++ = *q++; + while (--i); + + return p; +} + +/** + * @brief System formatted output function. + * @details This function implements a minimal @p printf() like functionality + * with output on a @p BaseChannel. + * The general parameters format is: %[-][width|*][.precision|*][l|L]p. + * The following parameter types (p) are supported: + * - x hexadecimal integer. + * - X hexadecimal long. + * - o octal integer. + * - O octal long. + * - d decimal signed integer. + * - D decimal signed long. + * - u decimal unsigned integer. + * - U decimal unsigned long. + * - c character. + * - s string. + * . + * @note Floating point types are not implemented, this function is meant + * as a system utility and not a full implementation. + * + * @param[in] chp pointer to a @p BaseChannel implementing object + * @param[in] fmt formatting string + */ +void chprintf(BaseChannel *chp, const char *fmt, ...) { + va_list ap; + char tmpbuf[MAX_FILLER + 1]; + char *p, *s, c, filler; + int i, precision, width; + bool_t is_long, left_align; + long l; + + va_start(ap, fmt); + while (TRUE) { + c = *fmt++; + if (c == 0) { + va_end(ap); + return; + } + if (c != '%') { + chIOPut(chp, (uint8_t)c); + continue; + } + p = tmpbuf; + s = tmpbuf; + left_align = FALSE; + if (*fmt == '-') { + fmt++; + left_align = TRUE; + } + filler = ' '; + if (*fmt == '.') { + fmt++; + filler = '0'; + } + width = 0; + while (TRUE) { + c = *fmt++; + if (c >= '0' && c <= '9') + c -= '0'; + else if (c == '*') + c = va_arg(ap, int); + else + break; + width = width * 10 + c; + } + precision = 0; + if (c == '.') { + while (TRUE) { + c = *fmt++; + if (c >= '0' && c <= '9') + c -= '0'; + else if (c == '*') + c = va_arg(ap, int); + else + break; + precision *= 10; + precision += c; + } + } + /* Long modifier.*/ + if (c == 'l' || c == 'L') { + is_long = TRUE; + if (*fmt) + c = *fmt++; + } + else + is_long = (c >= 'A') && (c <= 'Z'); + + /* Command decoding.*/ + switch (c) { + case 'c': + filler = ' '; + *p++ = va_arg(ap, int); + break; + case 's': + filler = ' '; + if ((s = va_arg(ap, char *)) == 0) + s = "(null)"; + if (precision == 0) + precision = 32767; + for (p = s; *p && (--precision >= 0); p++) + ; + break; + case 'D': + case 'd': + if (is_long) + l = va_arg(ap, long); + else + l = va_arg(ap, int); + if (l < 0) { + *p++ = '-'; + l = -l; + } + p = ltoa(p, l, 10); + break; + case 'X': + case 'x': + c = 16; + goto unsigned_common; + case 'U': + case 'u': + c = 10; + goto unsigned_common; + case 'O': + case 'o': + c = 8; +unsigned_common: + if (is_long) + l = va_arg(ap, long); + else + l = va_arg(ap, int); + p = ltoa(p, l, c); + break; + default: + *p++ = c; + break; + } + i = (int)(p - s); + if ((width -= i) < 0) + width = 0; + if (left_align == FALSE) + width = -width; + if (width < 0) { + if (*s == '-' && filler == '0') { + chIOPut(chp, (uint8_t)*s++); + i--; + } + do + chIOPut(chp, (uint8_t)filler); + while (++width != 0); + } + while (--i >= 0) + chIOPut(chp, (uint8_t)*s++); + + while (width) { + chIOPut(chp, (uint8_t)filler); + width--; + } + } +} + +/** @} */ diff --git a/Project/os/various/chprintf.h b/Project/os/various/chprintf.h new file mode 100644 index 0000000..ed6120c --- /dev/null +++ b/Project/os/various/chprintf.h @@ -0,0 +1,49 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file chprintf.h + * @brief Mini printf-like functionality. + * + * @addtogroup chprintf + * @{ + */ + +#ifndef _CHPRINTF_H_ +#define _CHPRINTF_H_ + +#ifdef __cplusplus +extern "C" { +#endif + void chprintf(BaseChannel *chp, const char *fmt, ...); +#ifdef __cplusplus +} +#endif + +#endif /* _CHPRINTF_H_ */ + +/** @} */ diff --git a/Project/os/various/evtimer.c b/Project/os/various/evtimer.c new file mode 100644 index 0000000..ea8cb7d --- /dev/null +++ b/Project/os/various/evtimer.c @@ -0,0 +1,78 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file evtimer.c + * @brief Events Generator Timer code. + * + * @addtogroup event_timer + * @{ + */ + +#include "ch.h" +#include "evtimer.h" + +static void tmrcb(void *p) { + EvTimer *etp = p; + + chEvtBroadcastI(&etp->et_es); + chVTSetI(&etp->et_vt, etp->et_interval, tmrcb, etp); +} + +/** + * @brief Starts the timer + * @details If the timer was already running then the function has no effect. + * + * @param etp pointer to an initialized @p EvTimer structure. + */ +void evtStart(EvTimer *etp) { + + chSysLock(); + + if (!chVTIsArmedI(&etp->et_vt)) + chVTSetI(&etp->et_vt, etp->et_interval, tmrcb, etp); + + chSysUnlock(); +} + +/** + * @brief Stops the timer. + * @details If the timer was already stopped then the function has no effect. + * + * @param etp pointer to an initialized @p EvTimer structure. + */ +void evtStop(EvTimer *etp) { + + chSysLock(); + + if (chVTIsArmedI(&etp->et_vt)) + chVTResetI(&etp->et_vt); + + chSysUnlock(); +} + +/** @} */ diff --git a/Project/os/various/evtimer.h b/Project/os/various/evtimer.h new file mode 100644 index 0000000..5ca9ed7 --- /dev/null +++ b/Project/os/various/evtimer.h @@ -0,0 +1,71 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file evtimer.h + * @brief Events Generator Timer structures and macros. + * + * @addtogroup event_timer + * @{ + */ + +#ifndef _EVTIMER_H_ +#define _EVTIMER_H_ + +/** + * @brief Event timer structure. + */ +typedef struct { + VirtualTimer et_vt; + EventSource et_es; + systime_t et_interval; +} EvTimer; + +#ifdef __cplusplus +extern "C" { +#endif + void evtStart(EvTimer *etp); + void evtStop(EvTimer *etp); +#ifdef __cplusplus +} +#endif + +/** + * @brief Initializes an @p EvTimer structure. + * + * @param etp the EvTimer structure to be initialized + * @param time the interval in system ticks + */ +#define evtInit(etp, time) { \ + chEvtInit(&(etp)->et_es); \ + (etp)->et_vt.vt_func = NULL; \ + (etp)->et_interval = (time); \ +} + +#endif /* _EVTIMER_H_ */ + +/** @} */ diff --git a/Project/os/various/lis302dl.c b/Project/os/various/lis302dl.c new file mode 100644 index 0000000..6ef3b9c --- /dev/null +++ b/Project/os/various/lis302dl.c @@ -0,0 +1,110 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file lis302dl.c + * @brief LIS302DL MEMS interface module through SPI code. + * + * @addtogroup lis302dl + * @{ + */ + +#include "ch.h" +#include "hal.h" +#include "lis302dl.h" + +static uint8_t txbuf[2]; +static uint8_t rxbuf[2]; + +/** + * @brief Reads a register value. + * @pre The SPI interface must be initialized and the driver started. + * + * @param[in] spip pointer to the SPI initerface + * @param[in] reg register number + * @return The register value. + */ +uint8_t lis302dlReadRegister(SPIDriver *spip, uint8_t reg) { + + spiSelect(spip); + txbuf[0] = 0x80 | reg; + txbuf[1] = 0xff; + spiExchange(spip, 2, txbuf, rxbuf); + spiUnselect(spip); + return rxbuf[1]; +} + +/** + * @brief Writes a value into a register. + * @pre The SPI interface must be initialized and the driver started. + * + * @param[in] spip pointer to the SPI initerface + * @param[in] reg register number + * @param[in] value the value to be written + */ +void lis302dlWriteRegister(SPIDriver *spip, uint8_t reg, uint8_t value) { + + switch (reg) { + default: + /* Reserved register must not be written, according to the datasheet + this could permanently damage the device.*/ + chDbgAssert(FALSE, "lis302dlWriteRegister(), #1", "reserved register"); + case LIS302DL_WHO_AM_I: + case LIS302DL_HP_FILTER_RESET: + case LIS302DL_STATUS_REG: + case LIS302DL_OUTX: + case LIS302DL_OUTY: + case LIS302DL_OUTZ: + case LIS302DL_FF_WU_SRC1: + case LIS302DL_FF_WU_SRC2: + case LIS302DL_CLICK_SRC: + /* Read only registers cannot be written, the command is ignored.*/ + return; + case LIS302DL_CTRL_REG1: + case LIS302DL_CTRL_REG2: + case LIS302DL_CTRL_REG3: + case LIS302DL_FF_WU_CFG1: + case LIS302DL_FF_WU_THS1: + case LIS302DL_FF_WU_DURATION1: + case LIS302DL_FF_WU_CFG2: + case LIS302DL_FF_WU_THS2: + case LIS302DL_FF_WU_DURATION2: + case LIS302DL_CLICK_CFG: + case LIS302DL_CLICK_THSY_X: + case LIS302DL_CLICK_THSZ: + case LIS302DL_CLICK_TIMELIMIT: + case LIS302DL_CLICK_LATENCY: + case LIS302DL_CLICK_WINDOW: + spiSelect(spip); + txbuf[0] = reg; + txbuf[1] = value; + spiSend(spip, 2, txbuf); + spiUnselect(spip); + } +} + +/** @} */ diff --git a/Project/os/various/lis302dl.h b/Project/os/various/lis302dl.h new file mode 100644 index 0000000..169ce9a --- /dev/null +++ b/Project/os/various/lis302dl.h @@ -0,0 +1,80 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file lis302dl.h + * @brief LIS302DL MEMS interface module through SPI header. + * + * @addtogroup lis302dl + * @{ + */ + +#ifndef _LIS302DL_H_ +#define _LIS302DL_H_ + +/** + * @name LIS302DL register names + * @{ + */ +#define LIS302DL_WHO_AM_I 0x0F +#define LIS302DL_CTRL_REG1 0x20 +#define LIS302DL_CTRL_REG2 0x21 +#define LIS302DL_CTRL_REG3 0x22 +#define LIS302DL_HP_FILTER_RESET 0x23 +#define LIS302DL_STATUS_REG 0x27 +#define LIS302DL_OUTX 0x29 +#define LIS302DL_OUTY 0x2B +#define LIS302DL_OUTZ 0x2D +#define LIS302DL_FF_WU_CFG1 0x30 +#define LIS302DL_FF_WU_SRC1 0x31 +#define LIS302DL_FF_WU_THS1 0x32 +#define LIS302DL_FF_WU_DURATION1 0x33 +#define LIS302DL_FF_WU_CFG2 0x34 +#define LIS302DL_FF_WU_SRC2 0x35 +#define LIS302DL_FF_WU_THS2 0x36 +#define LIS302DL_FF_WU_DURATION2 0x37 +#define LIS302DL_CLICK_CFG 0x38 +#define LIS302DL_CLICK_SRC 0x39 +#define LIS302DL_CLICK_THSY_X 0x3B +#define LIS302DL_CLICK_THSZ 0x3C +#define LIS302DL_CLICK_TIMELIMIT 0x3D +#define LIS302DL_CLICK_LATENCY 0x3E +#define LIS302DL_CLICK_WINDOW 0x3F +/** @} */ + +#ifdef __cplusplus +extern "C" { +#endif + uint8_t lis302dlReadRegister(SPIDriver *spip, uint8_t reg); + void lis302dlWriteRegister(SPIDriver *spip, uint8_t reg, uint8_t value); +#ifdef __cplusplus +} +#endif + +#endif /* _LIS302DL_H_ */ + +/** @} */ diff --git a/Project/os/various/memstreams.c b/Project/os/various/memstreams.c new file mode 100644 index 0000000..0ca0443 --- /dev/null +++ b/Project/os/various/memstreams.c @@ -0,0 +1,103 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file memstreams.c + * @brief Memory streams code. + * + * @addtogroup memory_streams + * @{ + */ + +#include + +#include "ch.h" +#include "memstreams.h" + +/* + * @brief Write virtual method implementation. + * + * @param[in] ip pointer to a @p MemoryStream object + * @param[in] bp pointer to the data buffer + * @param[in] n the maximum amount of data to be transferred + * @return The number of bytes transferred. The return value can + * be less than the specified number of bytes if the + * stream reaches a physical end of file and cannot be + * extended. + */ +static size_t writes(void *ip, const uint8_t *bp, size_t n) { + MemoryStream *msp = ip; + + if (msp->size - msp->eos < n) + n = msp->size - msp->eos; + memcpy(msp->buffer + msp->eos, bp, n); + msp->eos += n; + return n; +} + +/* + * @brief Read virtual method implementation. + * + * @param[in] ip pointer to a @p MemoryStream object + * @param[out] bp pointer to the data buffer + * @param[in] n the maximum amount of data to be transferred + * @return The number of bytes transferred. The return value can + * be less than the specified number of bytes if the + * stream reaches the end of the available data. + */ +static size_t reads(void *ip, uint8_t *bp, size_t n) { + MemoryStream *msp = ip; + + if (msp->eos - msp->offset < n) + n = msp->eos - msp->offset; + memcpy(bp, msp->buffer + msp->offset, n); + msp->offset += n; + return n; +} + +static const struct MemStreamVMT vmt = {writes, reads}; + +/** + * @brief Memory stream object initialization. + * + * @param[out] msp pointer to the @p MemoryStream object to be initialized + * @param[in] buffer pointer to the memory buffer for the memory stream + * @param[in] size total size of the memory stream buffer + * @param[in] eos initial End Of Stream offset. Normally you need to + * put this to zero for RAM buffers or equal to @p size + * for ROM streams. + */ +void msObjectInit(MemoryStream *msp, uint8_t *buffer, size_t size, size_t eos) { + + msp->vmt = &vmt; + msp->buffer = buffer; + msp->size = size; + msp->eos = eos; + msp->offset = 0; +} + +/** @} */ diff --git a/Project/os/various/memstreams.h b/Project/os/various/memstreams.h new file mode 100644 index 0000000..f97228b --- /dev/null +++ b/Project/os/various/memstreams.h @@ -0,0 +1,81 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file memstreams.h + * @brief Memory streams structures and macros. + + * @addtogroup memory_streams + * @{ + */ + +#ifndef _MEMSTREAMS_H_ +#define _MEMSTREAMS_H_ + +/** + * @brief @p RamStream specific data. + */ +#define _memory_stream_data \ + _base_sequential_stream_data \ + /* Pointer to the stream buffer.*/ \ + uint8_t *buffer; \ + /* Size of the stream.*/ \ + size_t size; \ + /* Current end of stream.*/ \ + size_t eos; \ + /* Current read offset.*/ \ + size_t offset; + +/** + * @brief @p MemStream virtual methods table. + */ +struct MemStreamVMT { + _base_sequential_stream_methods +}; + +/** + * @extends BaseSequentialStream + * + * @brief Memory stream object. + */ +typedef struct { + /** @brief Virtual Methods Table.*/ + const struct MemStreamVMT *vmt; + _memory_stream_data +} MemoryStream; + +#ifdef __cplusplus +extern "C" { +#endif + void msObjectInit(MemoryStream *msp, uint8_t *buffer, size_t size, size_t eos); +#ifdef __cplusplus +} +#endif + +#endif /* _MEMSTREAMS_H_ */ + +/** @} */ diff --git a/Project/os/various/shell.c b/Project/os/various/shell.c new file mode 100644 index 0000000..e6124e5 --- /dev/null +++ b/Project/os/various/shell.c @@ -0,0 +1,296 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file shell.c + * @brief Simple CLI shell code. + * + * @addtogroup SHELL + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" +#include "shell.h" +#include "chprintf.h" + +/** + * @brief Shell termination event source. + */ +EventSource shell_terminated; + +static char *_strtok(char *str, const char *delim, char **saveptr) { + char *token; + if (str) + *saveptr = str; + token = *saveptr; + + if (!token) + return NULL; + + token += strspn(token, delim); + *saveptr = strpbrk(token, delim); + if (*saveptr) + *(*saveptr)++ = '\0'; + + return *token ? token : NULL; +} + +static void usage(BaseChannel *chp, char *p) { + + chprintf(chp, "Usage: %s\r\n", p); +} + +static void list_commands(BaseChannel *chp, const ShellCommand *scp) { + + while (scp->sc_name != NULL) { + chprintf(chp, "%s ", scp->sc_name); + scp++; + } +} + +static void cmd_info(BaseChannel *chp, int argc, char *argv[]) { + + (void)argv; + if (argc > 0) { + usage(chp, "info"); + return; + } + + chprintf(chp, "Kernel: %s\r\n", CH_KERNEL_VERSION); +#ifdef CH_COMPILER_NAME + chprintf(chp, "Compiler: %s\r\n", CH_COMPILER_NAME); +#endif + chprintf(chp, "Architecture: %s\r\n", CH_ARCHITECTURE_NAME); +#ifdef CH_CORE_VARIANT_NAME + chprintf(chp, "Core Variant: %s\r\n", CH_CORE_VARIANT_NAME); +#endif +#ifdef CH_PORT_INFO + chprintf(chp, "Port Info: %s\r\n", CH_PORT_INFO); +#endif +#ifdef PLATFORM_NAME + chprintf(chp, "Platform: %s\r\n", PLATFORM_NAME); +#endif +#ifdef BOARD_NAME + chprintf(chp, "Board: %s\r\n", BOARD_NAME); +#endif +#ifdef __DATE__ +#ifdef __TIME__ + chprintf(chp, "Build time: %s%s%s\r\n", __DATE__, " - ", __TIME__); +#endif +#endif +} + +static void cmd_systime(BaseChannel *chp, int argc, char *argv[]) { + + (void)argv; + if (argc > 0) { + usage(chp, "systime"); + return; + } + chprintf(chp, "%lu\r\n", (unsigned long)chTimeNow()); +} + +/** + * @brief Array of the default commands. + */ +static ShellCommand local_commands[] = { + {"info", cmd_info}, + {"systime", cmd_systime}, + {NULL, NULL} +}; + +static bool_t cmdexec(const ShellCommand *scp, BaseChannel *chp, + char *name, int argc, char *argv[]) { + + while (scp->sc_name != NULL) { + if (strcasecmp(scp->sc_name, name) == 0) { + scp->sc_function(chp, argc, argv); + return FALSE; + } + scp++; + } + return TRUE; +} + +/** + * @brief Shell thread function. + * + * @param[in] p pointer to a @p BaseChannel object + * @return Termination reason. + * @retval RDY_OK terminated by command. + * @retval RDY_RESET terminated by reset condition on the I/O channel. + */ +static msg_t shell_thread(void *p) { + int n; + msg_t msg = RDY_OK; + BaseChannel *chp = ((ShellConfig *)p)->sc_channel; + const ShellCommand *scp = ((ShellConfig *)p)->sc_commands; + char *lp, *cmd, *tokp, line[SHELL_MAX_LINE_LENGTH]; + char *args[SHELL_MAX_ARGUMENTS + 1]; + + chRegSetThreadName("shell"); + chprintf(chp, "\r\nChibiOS/RT Shell\r\n"); + while (TRUE) { + chprintf(chp, "ch> "); + if (shellGetLine(chp, line, sizeof(line))) { + chprintf(chp, "\r\nlogout"); + break; + } + lp = _strtok(line, " \t", &tokp); + cmd = lp; + n = 0; + while ((lp = _strtok(NULL, " \t", &tokp)) != NULL) { + if (n >= SHELL_MAX_ARGUMENTS) { + chprintf(chp, "too many arguments\r\n"); + cmd = NULL; + break; + } + args[n++] = lp; + } + args[n] = NULL; + if (cmd != NULL) { + if (strcasecmp(cmd, "exit") == 0) { + if (n > 0) { + usage(chp, "exit"); + continue; + } + break; + } + else if (strcasecmp(cmd, "help") == 0) { + if (n > 0) { + usage(chp, "help"); + continue; + } + chprintf(chp, "Commands: help exit "); + list_commands(chp, local_commands); + if (scp != NULL) + list_commands(chp, scp); + chprintf(chp, "\r\n"); + } + else if (cmdexec(local_commands, chp, cmd, n, args) && + ((scp == NULL) || cmdexec(scp, chp, cmd, n, args))) { + chprintf(chp, "%s", cmd); + chprintf(chp, " ?\r\n"); + } + } + } + /* Atomically broadcasting the event source and terminating the thread, + there is not a chSysUnlock() because the thread terminates upon return.*/ + chSysLock(); + chEvtBroadcastI(&shell_terminated); + chThdExitS(msg); + return 0; /* Never executed.*/ +} + +/** + * @brief Shell manager initialization. + */ +void shellInit(void) { + + chEvtInit(&shell_terminated); +} + +/** + * @brief Spawns a new shell. + * @pre @p CH_USE_MALLOC_HEAP and @p CH_USE_DYNAMIC must be enabled. + * + * @param[in] scp pointer to a @p ShellConfig object + * @param[in] size size of the shell working area to be allocated + * @param[in] prio priority level for the new shell + * @return A pointer to the shell thread. + * @retval NULL thread creation failed because memory allocation. + */ +#if CH_USE_HEAP && CH_USE_DYNAMIC +Thread *shellCreate(const ShellConfig *scp, size_t size, tprio_t prio) { + + return chThdCreateFromHeap(NULL, size, prio, shell_thread, (void *)scp); +} +#endif + +/** + * @brief Create statically allocated shell thread. + * + * @param[in] scp pointer to a @p ShellConfig object + * @param[in] wsp pointer to a working area dedicated to the shell thread stack + * @param[in] size size of the shell working area + * @param[in] prio priority level for the new shell + * @return A pointer to the shell thread. + */ +Thread *shellCreateStatic(const ShellConfig *scp, void *wsp, + size_t size, tprio_t prio) { + + return chThdCreateStatic(wsp, size, prio, shell_thread, (void *)scp); +} + +/** + * @brief Reads a whole line from the input channel. + * + * @param[in] chp pointer to a @p BaseChannel object + * @param[in] line pointer to the line buffer + * @param[in] size buffer maximum length + * @return The operation status. + * @retval TRUE the channel was reset or CTRL-D pressed. + * @retval FALSE operation successful. + */ +bool_t shellGetLine(BaseChannel *chp, char *line, unsigned size) { + char *p = line; + + while (TRUE) { + short c = (short)chIOGet(chp); + if (c < 0) + return TRUE; + if (c == 4) { + chprintf(chp, "^D"); + return TRUE; + } + if (c == 8) { + if (p != line) { + chIOPut(chp, (uint8_t)c); + chIOPut(chp, 0x20); + chIOPut(chp, (uint8_t)c); + p--; + } + continue; + } + if (c == '\r') { + chprintf(chp, "\r\n"); + *p = 0; + return FALSE; + } + if (c < 0x20) + continue; + if (p < line + size - 1) { + chIOPut(chp, (uint8_t)c); + *p++ = (char)c; + } + } +} + +/** @} */ diff --git a/Project/os/various/shell.h b/Project/os/various/shell.h new file mode 100644 index 0000000..e363c23 --- /dev/null +++ b/Project/os/various/shell.h @@ -0,0 +1,94 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file shell.h + * @brief Simple CLI shell header. + * + * @addtogroup SHELL + * @{ + */ + +#ifndef _SHELL_H_ +#define _SHELL_H_ + +/** + * @brief Shell maximum input line length. + */ +#if !defined(SHELL_MAX_LINE_LENGTH) || defined(__DOXYGEN__) +#define SHELL_MAX_LINE_LENGTH 64 +#endif + +/** + * @brief Shell maximum arguments per command. + */ +#if !defined(SHELL_MAX_ARGUMENTS) || defined(__DOXYGEN__) +#define SHELL_MAX_ARGUMENTS 4 +#endif + +/** + * @brief Command handler function type. + */ +typedef void (*shellcmd_t)(BaseChannel *chp, int argc, char *argv[]); + +/** + * @brief Custom command entry type. + */ +typedef struct { + const char *sc_name; /**< @brief Command name. */ + shellcmd_t sc_function; /**< @brief Command function. */ +} ShellCommand; + +/** + * @brief Shell descriptor type. + */ +typedef struct { + BaseChannel *sc_channel; /**< @brief I/O channel associated + to the shell. */ + const ShellCommand *sc_commands; /**< @brief Shell extra commands + table. */ +} ShellConfig; + +#if !defined(__DOXYGEN__) +extern EventSource shell_terminated; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void shellInit(void); + Thread *shellCreate(const ShellConfig *scp, size_t size, tprio_t prio); + Thread *shellCreateStatic(const ShellConfig *scp, void *wsp, + size_t size, tprio_t prio); + bool_t shellGetLine(BaseChannel *chp, char *line, unsigned size); +#ifdef __cplusplus +} +#endif + +#endif /* _SHELL_H_ */ + +/** @} */ diff --git a/Project/os/various/syscalls.c b/Project/os/various/syscalls.c new file mode 100644 index 0000000..2c52bb0 --- /dev/null +++ b/Project/os/various/syscalls.c @@ -0,0 +1,211 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ +/* +* **** This file incorporates work covered by the following copyright and **** +* **** permission notice: **** +* +* Copyright (c) 2009 by Michael Fischer. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +**************************************************************************** +* History: +* +* 28.03.09 mifi First Version, based on the original syscall.c from +* newlib version 1.17.0 +* 17.08.09 gdisirio Modified the file for use under ChibiOS/RT +* 15.11.09 gdisirio Added read and write handling +****************************************************************************/ + +#include +#include +#include +#include +#include + +#include "ch.h" +#if defined(STDOUT_SD) || defined(STDIN_SD) +#include "hal.h" +#endif + +/***************************************************************************/ + +int _read_r(struct _reent *r, int file, char * ptr, int len) +{ + (void)r; +#if defined(STDIN_SD) + if (!len || (file != 0)) { + __errno_r(r) = EINVAL; + return -1; + } + len = sdRead(&STDIN_SD, (uint8_t *)ptr, (size_t)len); + return len; +#else + (void)file; + (void)ptr; + (void)len; + __errno_r(r) = EINVAL; + return -1; +#endif +} + +/***************************************************************************/ + +int _lseek_r(struct _reent *r, int file, int ptr, int dir) +{ + (void)r; + (void)file; + (void)ptr; + (void)dir; + + return 0; +} + +/***************************************************************************/ + +int _write_r(struct _reent *r, int file, char * ptr, int len) +{ + (void)r; + (void)file; + (void)ptr; +#if defined(STDOUT_SD) + if (file != 1) { + __errno_r(r) = EINVAL; + return -1; + } + sdWrite(&STDOUT_SD, (uint8_t *)ptr, (size_t)len); +#endif + return len; +} + +/***************************************************************************/ + +int _close_r(struct _reent *r, int file) +{ + (void)r; + (void)file; + + return 0; +} + +/***************************************************************************/ + +caddr_t _sbrk_r(struct _reent *r, int incr) +{ +#if CH_USE_MEMCORE + void *p; + + chDbgCheck(incr > 0, "_sbrk_r"); + + (void)r; + p = chCoreAlloc((size_t)incr); + if (p == NULL) { + __errno_r(r) = ENOMEM; + return (caddr_t)-1; + } + return (caddr_t)p; +#else + __errno_r(r) = ENOMEM; + return (caddr_t)-1; +#endif +} + +/***************************************************************************/ + +int _fstat_r(struct _reent *r, int file, struct stat * st) +{ + (void)r; + (void)file; + + memset(st, 0, sizeof(*st)); + st->st_mode = S_IFCHR; + return 0; +} + +/***************************************************************************/ + +int _isatty_r(struct _reent *r, int fd) +{ + (void)r; + (void)fd; + + return 1; +} + +void * _realloc_r(struct _reent *re, _PTR oldAddr, size_t newSize) { + void *newAddr; + + newAddr = chHeapAlloc(NULL, newSize); + + if (newAddr == NULL) + return NULL; + + /* copy old block into new one */ + memcpy((void *)newAddr, (void *)oldAddr, (size_t)newSize); + + chHeapFree(oldAddr); + + return newAddr; +} + +void * _calloc_r(struct _reent *re, size_t num, size_t size) { + return chHeapAlloc(NULL,num*size); +} + +void *_malloc_r(struct _reent *re, size_t size) { + return chHeapAlloc(NULL,size); +} + +void _free_r(struct _reent *re, void * ptr) { + chHeapFree(ptr); +} + +/*** EOF ***/ diff --git a/Project/os/various/various.dox b/Project/os/various/various.dox new file mode 100644 index 0000000..e019e02 --- /dev/null +++ b/Project/os/various/various.dox @@ -0,0 +1,93 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @defgroup various Various + * + * @brief Utilities Library. + * @details This is a collection of useful library code that is not part of + * the base kernel services. + *

Notes

+ * The library code does not follow the same naming convention of the + * system APIs in order to make very clear that it is not "core" code.
+ * The main difference is that library code is not formally tested in the + * test suite but through usage in the various demo applications. + */ + +/** + * @defgroup cpp_library C++ Wrapper + * + * @brief C++ wrapper module. + * @details This module allows to use the ChibiOS/RT functionalities + * from C++ as classes and objects rather the traditional "C" APIs. + * + * @ingroup various + */ + +/** + * @defgroup memory_streams Memory Streams + * + * @brief Memory Streams. + * @details This module allows to use a memory area (RAM or ROM) using a + * @ref data_streams interface. + * + * @ingroup various + */ + +/** + * @defgroup event_timer Periodic Events Timer + * + * @brief Periodic Event Timer. + * @details This timer generates an event at regular intervals. The + * listening threads can use the event to perform time related + * activities. Multiple threads can listen to the same timer. + * + * @ingroup various + */ + +/** + * @defgroup SHELL Command Shell + * + * @brief Small extendible command line shell. + * @details This module implements a generic extendible command line interface. + * The CLI just requires an I/O channel (@p BaseChannel), more + * commands can be added to the shell using the configuration + * structure. + * + * @ingroup various + */ + +/** + * @defgroup lis302dl Interface module for LIS302DL MEMS. + * + * @brief Interface module for LIS302DL MEMS. + * @details This module implements a generic interface for the LIS302DL + * STMicroelectronics MEMS device. The communication is performed + * through a standard SPI driver. + * + * @ingroup various + */